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ac/nir: drop nir_to_llvm_context from visit_var_atomic()
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 struct nir_to_llvm_context;
50
51 struct ac_nir_context {
52 struct ac_llvm_context ac;
53 struct ac_shader_abi *abi;
54
55 gl_shader_stage stage;
56
57 struct hash_table *defs;
58 struct hash_table *phis;
59 struct hash_table *vars;
60
61 LLVMValueRef main_function;
62 LLVMBasicBlockRef continue_block;
63 LLVMBasicBlockRef break_block;
64
65 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
66
67 int num_locals;
68 LLVMValueRef *locals;
69
70 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
71 };
72
73 struct nir_to_llvm_context {
74 struct ac_llvm_context ac;
75 const struct ac_nir_compiler_options *options;
76 struct ac_shader_variant_info *shader_info;
77 struct ac_shader_abi abi;
78 struct ac_nir_context *nir;
79
80 unsigned max_workgroup_size;
81 LLVMContextRef context;
82 LLVMModuleRef module;
83 LLVMBuilderRef builder;
84 LLVMValueRef main_function;
85
86 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
87 LLVMValueRef ring_offsets;
88
89 LLVMValueRef vertex_buffers;
90 LLVMValueRef rel_auto_id;
91 LLVMValueRef vs_prim_id;
92 LLVMValueRef ls_out_layout;
93 LLVMValueRef es2gs_offset;
94
95 LLVMValueRef tcs_offchip_layout;
96 LLVMValueRef tcs_out_offsets;
97 LLVMValueRef tcs_out_layout;
98 LLVMValueRef tcs_in_layout;
99 LLVMValueRef oc_lds;
100 LLVMValueRef merged_wave_info;
101 LLVMValueRef tess_factor_offset;
102 LLVMValueRef tes_rel_patch_id;
103 LLVMValueRef tes_u;
104 LLVMValueRef tes_v;
105
106 LLVMValueRef gsvs_ring_stride;
107 LLVMValueRef gsvs_num_entries;
108 LLVMValueRef gs2vs_offset;
109 LLVMValueRef gs_wave_id;
110 LLVMValueRef gs_vtx_offset[6];
111
112 LLVMValueRef esgs_ring;
113 LLVMValueRef gsvs_ring;
114 LLVMValueRef hs_ring_tess_offchip;
115 LLVMValueRef hs_ring_tess_factor;
116
117 LLVMValueRef sample_pos_offset;
118 LLVMValueRef persp_sample, persp_center, persp_centroid;
119 LLVMValueRef linear_sample, linear_center, linear_centroid;
120
121 gl_shader_stage stage;
122
123 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
124
125 uint64_t input_mask;
126 uint64_t output_mask;
127 uint8_t num_output_clips;
128 uint8_t num_output_culls;
129
130 bool is_gs_copy_shader;
131 LLVMValueRef gs_next_vertex;
132 unsigned gs_max_out_vertices;
133
134 unsigned tes_primitive_mode;
135 uint64_t tess_outputs_written;
136 uint64_t tess_patch_outputs_written;
137
138 uint32_t tcs_patch_outputs_read;
139 uint64_t tcs_outputs_read;
140 };
141
142 static inline struct nir_to_llvm_context *
143 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
144 {
145 struct nir_to_llvm_context *ctx = NULL;
146 return container_of(abi, ctx, abi);
147 }
148
149 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
150 const nir_deref_var *deref,
151 enum ac_descriptor_type desc_type,
152 const nir_tex_instr *instr,
153 bool image, bool write);
154
155 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
156 {
157 return (index * 4) + chan;
158 }
159
160 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
161 {
162 /* handle patch indices separate */
163 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
164 return 0;
165 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
166 return 1;
167 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
168 return 2 + (slot - VARYING_SLOT_PATCH0);
169
170 if (slot == VARYING_SLOT_POS)
171 return 0;
172 if (slot == VARYING_SLOT_PSIZ)
173 return 1;
174 if (slot == VARYING_SLOT_CLIP_DIST0)
175 return 2;
176 /* 3 is reserved for clip dist as well */
177 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
178 return 4 + (slot - VARYING_SLOT_VAR0);
179 unreachable("illegal slot in get unique index\n");
180 }
181
182 static void set_llvm_calling_convention(LLVMValueRef func,
183 gl_shader_stage stage)
184 {
185 enum radeon_llvm_calling_convention calling_conv;
186
187 switch (stage) {
188 case MESA_SHADER_VERTEX:
189 case MESA_SHADER_TESS_EVAL:
190 calling_conv = RADEON_LLVM_AMDGPU_VS;
191 break;
192 case MESA_SHADER_GEOMETRY:
193 calling_conv = RADEON_LLVM_AMDGPU_GS;
194 break;
195 case MESA_SHADER_TESS_CTRL:
196 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
197 break;
198 case MESA_SHADER_FRAGMENT:
199 calling_conv = RADEON_LLVM_AMDGPU_PS;
200 break;
201 case MESA_SHADER_COMPUTE:
202 calling_conv = RADEON_LLVM_AMDGPU_CS;
203 break;
204 default:
205 unreachable("Unhandle shader type");
206 }
207
208 LLVMSetFunctionCallConv(func, calling_conv);
209 }
210
211 #define MAX_ARGS 23
212 struct arg_info {
213 LLVMTypeRef types[MAX_ARGS];
214 LLVMValueRef *assign[MAX_ARGS];
215 unsigned array_params_mask;
216 uint8_t count;
217 uint8_t sgpr_count;
218 uint8_t num_sgprs_used;
219 uint8_t num_vgprs_used;
220 };
221
222 enum ac_arg_regfile {
223 ARG_SGPR,
224 ARG_VGPR,
225 };
226
227 static void
228 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
229 LLVMValueRef *param_ptr)
230 {
231 assert(info->count < MAX_ARGS);
232
233 info->assign[info->count] = param_ptr;
234 info->types[info->count] = type;
235 info->count++;
236
237 if (regfile == ARG_SGPR) {
238 info->num_sgprs_used += ac_get_type_size(type) / 4;
239 info->sgpr_count++;
240 } else {
241 assert(regfile == ARG_VGPR);
242 info->num_vgprs_used += ac_get_type_size(type) / 4;
243 }
244 }
245
246 static inline void
247 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
248 {
249 info->array_params_mask |= (1 << info->count);
250 add_arg(info, ARG_SGPR, type, param_ptr);
251 }
252
253 static void assign_arguments(LLVMValueRef main_function,
254 struct arg_info *info)
255 {
256 unsigned i;
257 for (i = 0; i < info->count; i++) {
258 if (info->assign[i])
259 *info->assign[i] = LLVMGetParam(main_function, i);
260 }
261 }
262
263 static LLVMValueRef
264 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
265 LLVMBuilderRef builder, LLVMTypeRef *return_types,
266 unsigned num_return_elems,
267 struct arg_info *args,
268 unsigned max_workgroup_size,
269 bool unsafe_math)
270 {
271 LLVMTypeRef main_function_type, ret_type;
272 LLVMBasicBlockRef main_function_body;
273
274 if (num_return_elems)
275 ret_type = LLVMStructTypeInContext(ctx, return_types,
276 num_return_elems, true);
277 else
278 ret_type = LLVMVoidTypeInContext(ctx);
279
280 /* Setup the function */
281 main_function_type =
282 LLVMFunctionType(ret_type, args->types, args->count, 0);
283 LLVMValueRef main_function =
284 LLVMAddFunction(module, "main", main_function_type);
285 main_function_body =
286 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
287 LLVMPositionBuilderAtEnd(builder, main_function_body);
288
289 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
290 for (unsigned i = 0; i < args->sgpr_count; ++i) {
291 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
292
293 if (args->array_params_mask & (1 << i)) {
294 LLVMValueRef P = LLVMGetParam(main_function, i);
295 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
296 ac_add_attr_dereferenceable(P, UINT64_MAX);
297 }
298 }
299
300 if (max_workgroup_size) {
301 ac_llvm_add_target_dep_function_attr(main_function,
302 "amdgpu-max-work-group-size",
303 max_workgroup_size);
304 }
305 if (unsafe_math) {
306 /* These were copied from some LLVM test. */
307 LLVMAddTargetDependentFunctionAttr(main_function,
308 "less-precise-fpmad",
309 "true");
310 LLVMAddTargetDependentFunctionAttr(main_function,
311 "no-infs-fp-math",
312 "true");
313 LLVMAddTargetDependentFunctionAttr(main_function,
314 "no-nans-fp-math",
315 "true");
316 LLVMAddTargetDependentFunctionAttr(main_function,
317 "unsafe-fp-math",
318 "true");
319 LLVMAddTargetDependentFunctionAttr(main_function,
320 "no-signed-zeros-fp-math",
321 "true");
322 }
323 return main_function;
324 }
325
326 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
327 LLVMValueRef param, unsigned rshift,
328 unsigned bitwidth)
329 {
330 LLVMValueRef value = param;
331 if (rshift)
332 value = LLVMBuildLShr(ctx->builder, value,
333 LLVMConstInt(ctx->i32, rshift, false), "");
334
335 if (rshift + bitwidth < 32) {
336 unsigned mask = (1 << bitwidth) - 1;
337 value = LLVMBuildAnd(ctx->builder, value,
338 LLVMConstInt(ctx->i32, mask, false), "");
339 }
340 return value;
341 }
342
343 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
344 {
345 switch (ctx->stage) {
346 case MESA_SHADER_TESS_CTRL:
347 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
348 case MESA_SHADER_TESS_EVAL:
349 return ctx->tes_rel_patch_id;
350 break;
351 default:
352 unreachable("Illegal stage");
353 }
354 }
355
356 /* Tessellation shaders pass outputs to the next shader using LDS.
357 *
358 * LS outputs = TCS inputs
359 * TCS outputs = TES inputs
360 *
361 * The LDS layout is:
362 * - TCS inputs for patch 0
363 * - TCS inputs for patch 1
364 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
365 * - ...
366 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
367 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
368 * - TCS outputs for patch 1
369 * - Per-patch TCS outputs for patch 1
370 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
371 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
372 * - ...
373 *
374 * All three shaders VS(LS), TCS, TES share the same LDS space.
375 */
376 static LLVMValueRef
377 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
378 {
379 if (ctx->stage == MESA_SHADER_VERTEX)
380 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
381 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
382 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
383 else {
384 assert(0);
385 return NULL;
386 }
387 }
388
389 static LLVMValueRef
390 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
391 {
392 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
393 }
394
395 static LLVMValueRef
396 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
397 {
398 return LLVMBuildMul(ctx->builder,
399 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
400 LLVMConstInt(ctx->ac.i32, 4, false), "");
401 }
402
403 static LLVMValueRef
404 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
405 {
406 return LLVMBuildMul(ctx->builder,
407 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
408 LLVMConstInt(ctx->ac.i32, 4, false), "");
409 }
410
411 static LLVMValueRef
412 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
413 {
414 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
415 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
416
417 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
418 }
419
420 static LLVMValueRef
421 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
422 {
423 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
424 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
425 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
426
427 return LLVMBuildAdd(ctx->builder, patch0_offset,
428 LLVMBuildMul(ctx->builder, patch_stride,
429 rel_patch_id, ""),
430 "");
431 }
432
433 static LLVMValueRef
434 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
435 {
436 LLVMValueRef patch0_patch_data_offset =
437 get_tcs_out_patch0_patch_data_offset(ctx);
438 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
439 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
440
441 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
442 LLVMBuildMul(ctx->builder, patch_stride,
443 rel_patch_id, ""),
444 "");
445 }
446
447 static void
448 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
449 uint32_t indirect_offset)
450 {
451 ud_info->sgpr_idx = *sgpr_idx;
452 ud_info->num_sgprs = num_sgprs;
453 ud_info->indirect = indirect_offset > 0;
454 ud_info->indirect_offset = indirect_offset;
455 *sgpr_idx += num_sgprs;
456 }
457
458 static void
459 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
460 uint8_t num_sgprs)
461 {
462 struct ac_userdata_info *ud_info =
463 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
464 assert(ud_info);
465
466 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
467 }
468
469 static void
470 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
471 uint32_t indirect_offset)
472 {
473 struct ac_userdata_info *ud_info =
474 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
475 assert(ud_info);
476
477 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
478 }
479
480 struct user_sgpr_info {
481 bool need_ring_offsets;
482 uint8_t sgpr_count;
483 bool indirect_all_descriptor_sets;
484 };
485
486 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
487 gl_shader_stage stage)
488 {
489 switch (stage) {
490 case MESA_SHADER_VERTEX:
491 if (ctx->shader_info->info.needs_multiview_view_index ||
492 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
493 return true;
494 break;
495 case MESA_SHADER_TESS_EVAL:
496 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
497 return true;
498 break;
499 case MESA_SHADER_GEOMETRY:
500 case MESA_SHADER_TESS_CTRL:
501 if (ctx->shader_info->info.needs_multiview_view_index)
502 return true;
503 break;
504 default:
505 break;
506 }
507 return false;
508 }
509
510 static uint8_t
511 count_vs_user_sgprs(struct nir_to_llvm_context *ctx)
512 {
513 uint8_t count = 0;
514
515 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
516 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
517
518 return count;
519 }
520
521 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
522 gl_shader_stage stage,
523 bool has_previous_stage,
524 gl_shader_stage previous_stage,
525 bool needs_view_index,
526 struct user_sgpr_info *user_sgpr_info)
527 {
528 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
529
530 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
531 if (stage == MESA_SHADER_GEOMETRY ||
532 stage == MESA_SHADER_VERTEX ||
533 stage == MESA_SHADER_TESS_CTRL ||
534 stage == MESA_SHADER_TESS_EVAL ||
535 ctx->is_gs_copy_shader)
536 user_sgpr_info->need_ring_offsets = true;
537
538 if (stage == MESA_SHADER_FRAGMENT &&
539 ctx->shader_info->info.ps.needs_sample_positions)
540 user_sgpr_info->need_ring_offsets = true;
541
542 /* 2 user sgprs will nearly always be allocated for scratch/rings */
543 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
544 user_sgpr_info->sgpr_count += 2;
545 }
546
547 switch (stage) {
548 case MESA_SHADER_COMPUTE:
549 if (ctx->shader_info->info.cs.uses_grid_size)
550 user_sgpr_info->sgpr_count += 3;
551 break;
552 case MESA_SHADER_FRAGMENT:
553 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
554 break;
555 case MESA_SHADER_VERTEX:
556 if (!ctx->is_gs_copy_shader)
557 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
558 if (ctx->options->key.vs.as_ls)
559 user_sgpr_info->sgpr_count++;
560 break;
561 case MESA_SHADER_TESS_CTRL:
562 if (has_previous_stage) {
563 if (previous_stage == MESA_SHADER_VERTEX)
564 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
565 user_sgpr_info->sgpr_count++;
566 }
567 user_sgpr_info->sgpr_count += 4;
568 break;
569 case MESA_SHADER_TESS_EVAL:
570 user_sgpr_info->sgpr_count += 1;
571 break;
572 case MESA_SHADER_GEOMETRY:
573 if (has_previous_stage) {
574 if (previous_stage == MESA_SHADER_VERTEX) {
575 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
576 } else {
577 user_sgpr_info->sgpr_count++;
578 }
579 }
580 user_sgpr_info->sgpr_count += 2;
581 break;
582 default:
583 break;
584 }
585
586 if (needs_view_index)
587 user_sgpr_info->sgpr_count++;
588
589 if (ctx->shader_info->info.loads_push_constants)
590 user_sgpr_info->sgpr_count += 2;
591
592 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
593 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
594
595 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
596 user_sgpr_info->sgpr_count += 2;
597 user_sgpr_info->indirect_all_descriptor_sets = true;
598 } else {
599 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
600 }
601 }
602
603 static void
604 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
605 gl_shader_stage stage,
606 bool has_previous_stage,
607 gl_shader_stage previous_stage,
608 const struct user_sgpr_info *user_sgpr_info,
609 struct arg_info *args,
610 LLVMValueRef *desc_sets)
611 {
612 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
613 unsigned num_sets = ctx->options->layout ?
614 ctx->options->layout->num_sets : 0;
615 unsigned stage_mask = 1 << stage;
616
617 if (has_previous_stage)
618 stage_mask |= 1 << previous_stage;
619
620 /* 1 for each descriptor set */
621 if (!user_sgpr_info->indirect_all_descriptor_sets) {
622 for (unsigned i = 0; i < num_sets; ++i) {
623 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
624 add_array_arg(args, type,
625 &ctx->descriptor_sets[i]);
626 }
627 }
628 } else {
629 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
630 }
631
632 if (ctx->shader_info->info.loads_push_constants) {
633 /* 1 for push constants and dynamic descriptors */
634 add_array_arg(args, type, &ctx->abi.push_constants);
635 }
636 }
637
638 static void
639 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
640 gl_shader_stage stage,
641 bool has_previous_stage,
642 gl_shader_stage previous_stage,
643 struct arg_info *args)
644 {
645 if (!ctx->is_gs_copy_shader &&
646 (stage == MESA_SHADER_VERTEX ||
647 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
648 if (ctx->shader_info->info.vs.has_vertex_buffers) {
649 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
650 &ctx->vertex_buffers);
651 }
652 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
653 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
654 if (ctx->shader_info->info.vs.needs_draw_id) {
655 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
656 }
657 }
658 }
659
660 static void
661 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
662 {
663 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
664 if (!ctx->is_gs_copy_shader) {
665 if (ctx->options->key.vs.as_ls) {
666 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
667 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
668 } else {
669 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
670 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
671 }
672 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
673 }
674 }
675
676 static void
677 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
678 {
679 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
680 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
681 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
682 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
683 }
684
685 static void
686 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
687 bool has_previous_stage, gl_shader_stage previous_stage,
688 const struct user_sgpr_info *user_sgpr_info,
689 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
690 {
691 unsigned num_sets = ctx->options->layout ?
692 ctx->options->layout->num_sets : 0;
693 unsigned stage_mask = 1 << stage;
694
695 if (has_previous_stage)
696 stage_mask |= 1 << previous_stage;
697
698 if (!user_sgpr_info->indirect_all_descriptor_sets) {
699 for (unsigned i = 0; i < num_sets; ++i) {
700 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
701 set_loc_desc(ctx, i, user_sgpr_idx, 0);
702 } else
703 ctx->descriptor_sets[i] = NULL;
704 }
705 } else {
706 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
707 user_sgpr_idx, 2);
708
709 for (unsigned i = 0; i < num_sets; ++i) {
710 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
711 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
712 ctx->descriptor_sets[i] =
713 ac_build_load_to_sgpr(&ctx->ac,
714 desc_sets,
715 LLVMConstInt(ctx->ac.i32, i, false));
716
717 } else
718 ctx->descriptor_sets[i] = NULL;
719 }
720 ctx->shader_info->need_indirect_descriptor_sets = true;
721 }
722
723 if (ctx->shader_info->info.loads_push_constants) {
724 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
725 }
726 }
727
728 static void
729 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
730 gl_shader_stage stage, bool has_previous_stage,
731 gl_shader_stage previous_stage,
732 uint8_t *user_sgpr_idx)
733 {
734 if (!ctx->is_gs_copy_shader &&
735 (stage == MESA_SHADER_VERTEX ||
736 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
737 if (ctx->shader_info->info.vs.has_vertex_buffers) {
738 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
739 user_sgpr_idx, 2);
740 }
741
742 unsigned vs_num = 2;
743 if (ctx->shader_info->info.vs.needs_draw_id)
744 vs_num++;
745
746 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
747 user_sgpr_idx, vs_num);
748 }
749 }
750
751 static void create_function(struct nir_to_llvm_context *ctx,
752 gl_shader_stage stage,
753 bool has_previous_stage,
754 gl_shader_stage previous_stage)
755 {
756 uint8_t user_sgpr_idx;
757 struct user_sgpr_info user_sgpr_info;
758 struct arg_info args = {};
759 LLVMValueRef desc_sets;
760 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
761 allocate_user_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, needs_view_index, &user_sgpr_info);
763
764 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
765 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
766 &ctx->ring_offsets);
767 }
768
769 switch (stage) {
770 case MESA_SHADER_COMPUTE:
771 declare_global_input_sgprs(ctx, stage, has_previous_stage,
772 previous_stage, &user_sgpr_info,
773 &args, &desc_sets);
774
775 if (ctx->shader_info->info.cs.uses_grid_size) {
776 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
777 &ctx->abi.num_work_groups);
778 }
779
780 for (int i = 0; i < 3; i++) {
781 ctx->abi.workgroup_ids[i] = NULL;
782 if (ctx->shader_info->info.cs.uses_block_id[i]) {
783 add_arg(&args, ARG_SGPR, ctx->ac.i32,
784 &ctx->abi.workgroup_ids[i]);
785 }
786 }
787
788 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
789 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
790 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
791 &ctx->abi.local_invocation_ids);
792 break;
793 case MESA_SHADER_VERTEX:
794 declare_global_input_sgprs(ctx, stage, has_previous_stage,
795 previous_stage, &user_sgpr_info,
796 &args, &desc_sets);
797 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
798 previous_stage, &args);
799
800 if (needs_view_index)
801 add_arg(&args, ARG_SGPR, ctx->ac.i32,
802 &ctx->abi.view_index);
803 if (ctx->options->key.vs.as_es)
804 add_arg(&args, ARG_SGPR, ctx->ac.i32,
805 &ctx->es2gs_offset);
806 else if (ctx->options->key.vs.as_ls)
807 add_arg(&args, ARG_SGPR, ctx->ac.i32,
808 &ctx->ls_out_layout);
809
810 declare_vs_input_vgprs(ctx, &args);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (has_previous_stage) {
814 // First 6 system regs
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
816 add_arg(&args, ARG_SGPR, ctx->ac.i32,
817 &ctx->merged_wave_info);
818 add_arg(&args, ARG_SGPR, ctx->ac.i32,
819 &ctx->tess_factor_offset);
820
821 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
822 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
823 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
824
825 declare_global_input_sgprs(ctx, stage,
826 has_previous_stage,
827 previous_stage,
828 &user_sgpr_info, &args,
829 &desc_sets);
830 declare_vs_specific_input_sgprs(ctx, stage,
831 has_previous_stage,
832 previous_stage, &args);
833
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->ls_out_layout);
836
837 add_arg(&args, ARG_SGPR, ctx->ac.i32,
838 &ctx->tcs_offchip_layout);
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->tcs_out_offsets);
841 add_arg(&args, ARG_SGPR, ctx->ac.i32,
842 &ctx->tcs_out_layout);
843 add_arg(&args, ARG_SGPR, ctx->ac.i32,
844 &ctx->tcs_in_layout);
845 if (needs_view_index)
846 add_arg(&args, ARG_SGPR, ctx->ac.i32,
847 &ctx->abi.view_index);
848
849 add_arg(&args, ARG_VGPR, ctx->ac.i32,
850 &ctx->abi.tcs_patch_id);
851 add_arg(&args, ARG_VGPR, ctx->ac.i32,
852 &ctx->abi.tcs_rel_ids);
853
854 declare_vs_input_vgprs(ctx, &args);
855 } else {
856 declare_global_input_sgprs(ctx, stage,
857 has_previous_stage,
858 previous_stage,
859 &user_sgpr_info, &args,
860 &desc_sets);
861
862 add_arg(&args, ARG_SGPR, ctx->ac.i32,
863 &ctx->tcs_offchip_layout);
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->tcs_out_offsets);
866 add_arg(&args, ARG_SGPR, ctx->ac.i32,
867 &ctx->tcs_out_layout);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tcs_in_layout);
870 if (needs_view_index)
871 add_arg(&args, ARG_SGPR, ctx->ac.i32,
872 &ctx->abi.view_index);
873
874 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
875 add_arg(&args, ARG_SGPR, ctx->ac.i32,
876 &ctx->tess_factor_offset);
877 add_arg(&args, ARG_VGPR, ctx->ac.i32,
878 &ctx->abi.tcs_patch_id);
879 add_arg(&args, ARG_VGPR, ctx->ac.i32,
880 &ctx->abi.tcs_rel_ids);
881 }
882 break;
883 case MESA_SHADER_TESS_EVAL:
884 declare_global_input_sgprs(ctx, stage, has_previous_stage,
885 previous_stage, &user_sgpr_info,
886 &args, &desc_sets);
887
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
889 if (needs_view_index)
890 add_arg(&args, ARG_SGPR, ctx->ac.i32,
891 &ctx->abi.view_index);
892
893 if (ctx->options->key.tes.as_es) {
894 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
895 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
896 add_arg(&args, ARG_SGPR, ctx->ac.i32,
897 &ctx->es2gs_offset);
898 } else {
899 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
900 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
901 }
902 declare_tes_input_vgprs(ctx, &args);
903 break;
904 case MESA_SHADER_GEOMETRY:
905 if (has_previous_stage) {
906 // First 6 system regs
907 add_arg(&args, ARG_SGPR, ctx->ac.i32,
908 &ctx->gs2vs_offset);
909 add_arg(&args, ARG_SGPR, ctx->ac.i32,
910 &ctx->merged_wave_info);
911 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
912
913 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
914 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
915 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
916
917 declare_global_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &user_sgpr_info, &args,
921 &desc_sets);
922
923 if (previous_stage == MESA_SHADER_TESS_EVAL) {
924 add_arg(&args, ARG_SGPR, ctx->ac.i32,
925 &ctx->tcs_offchip_layout);
926 } else {
927 declare_vs_specific_input_sgprs(ctx, stage,
928 has_previous_stage,
929 previous_stage,
930 &args);
931 }
932
933 add_arg(&args, ARG_SGPR, ctx->ac.i32,
934 &ctx->gsvs_ring_stride);
935 add_arg(&args, ARG_SGPR, ctx->ac.i32,
936 &ctx->gsvs_num_entries);
937 if (needs_view_index)
938 add_arg(&args, ARG_SGPR, ctx->ac.i32,
939 &ctx->abi.view_index);
940
941 add_arg(&args, ARG_VGPR, ctx->ac.i32,
942 &ctx->gs_vtx_offset[0]);
943 add_arg(&args, ARG_VGPR, ctx->ac.i32,
944 &ctx->gs_vtx_offset[2]);
945 add_arg(&args, ARG_VGPR, ctx->ac.i32,
946 &ctx->abi.gs_prim_id);
947 add_arg(&args, ARG_VGPR, ctx->ac.i32,
948 &ctx->abi.gs_invocation_id);
949 add_arg(&args, ARG_VGPR, ctx->ac.i32,
950 &ctx->gs_vtx_offset[4]);
951
952 if (previous_stage == MESA_SHADER_VERTEX) {
953 declare_vs_input_vgprs(ctx, &args);
954 } else {
955 declare_tes_input_vgprs(ctx, &args);
956 }
957 } else {
958 declare_global_input_sgprs(ctx, stage,
959 has_previous_stage,
960 previous_stage,
961 &user_sgpr_info, &args,
962 &desc_sets);
963
964 add_arg(&args, ARG_SGPR, ctx->ac.i32,
965 &ctx->gsvs_ring_stride);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32,
967 &ctx->gsvs_num_entries);
968 if (needs_view_index)
969 add_arg(&args, ARG_SGPR, ctx->ac.i32,
970 &ctx->abi.view_index);
971
972 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
973 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[0]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[1]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_prim_id);
980 add_arg(&args, ARG_VGPR, ctx->ac.i32,
981 &ctx->gs_vtx_offset[2]);
982 add_arg(&args, ARG_VGPR, ctx->ac.i32,
983 &ctx->gs_vtx_offset[3]);
984 add_arg(&args, ARG_VGPR, ctx->ac.i32,
985 &ctx->gs_vtx_offset[4]);
986 add_arg(&args, ARG_VGPR, ctx->ac.i32,
987 &ctx->gs_vtx_offset[5]);
988 add_arg(&args, ARG_VGPR, ctx->ac.i32,
989 &ctx->abi.gs_invocation_id);
990 }
991 break;
992 case MESA_SHADER_FRAGMENT:
993 declare_global_input_sgprs(ctx, stage, has_previous_stage,
994 previous_stage, &user_sgpr_info,
995 &args, &desc_sets);
996
997 if (ctx->shader_info->info.ps.needs_sample_positions)
998 add_arg(&args, ARG_SGPR, ctx->ac.i32,
999 &ctx->sample_pos_offset);
1000
1001 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1002 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
1003 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
1004 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
1005 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1006 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1007 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1008 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1009 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1010 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1011 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1012 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1013 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1014 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1015 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1016 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1017 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1018 break;
1019 default:
1020 unreachable("Shader stage not implemented");
1021 }
1022
1023 ctx->main_function = create_llvm_function(
1024 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
1025 ctx->max_workgroup_size,
1026 ctx->options->unsafe_math);
1027 set_llvm_calling_convention(ctx->main_function, stage);
1028
1029
1030 ctx->shader_info->num_input_vgprs = 0;
1031 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1032
1033 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1034
1035 if (ctx->stage != MESA_SHADER_FRAGMENT)
1036 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1037
1038 assign_arguments(ctx->main_function, &args);
1039
1040 user_sgpr_idx = 0;
1041
1042 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1043 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1044 &user_sgpr_idx, 2);
1045 if (ctx->options->supports_spill) {
1046 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1047 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1048 NULL, 0, AC_FUNC_ATTR_READNONE);
1049 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
1050 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1051 }
1052 }
1053
1054 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1055 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1056 if (has_previous_stage)
1057 user_sgpr_idx = 0;
1058
1059 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1060 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1061
1062 switch (stage) {
1063 case MESA_SHADER_COMPUTE:
1064 if (ctx->shader_info->info.cs.uses_grid_size) {
1065 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1066 &user_sgpr_idx, 3);
1067 }
1068 break;
1069 case MESA_SHADER_VERTEX:
1070 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1071 previous_stage, &user_sgpr_idx);
1072 if (ctx->abi.view_index)
1073 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1074 if (ctx->options->key.vs.as_ls) {
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 }
1078 if (ctx->options->key.vs.as_ls)
1079 ac_declare_lds_as_pointer(&ctx->ac);
1080 break;
1081 case MESA_SHADER_TESS_CTRL:
1082 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1083 previous_stage, &user_sgpr_idx);
1084 if (has_previous_stage)
1085 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1086 &user_sgpr_idx, 1);
1087 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1088 if (ctx->abi.view_index)
1089 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1090 ac_declare_lds_as_pointer(&ctx->ac);
1091 break;
1092 case MESA_SHADER_TESS_EVAL:
1093 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1094 if (ctx->abi.view_index)
1095 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1096 break;
1097 case MESA_SHADER_GEOMETRY:
1098 if (has_previous_stage) {
1099 if (previous_stage == MESA_SHADER_VERTEX)
1100 set_vs_specific_input_locs(ctx, stage,
1101 has_previous_stage,
1102 previous_stage,
1103 &user_sgpr_idx);
1104 else
1105 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1106 &user_sgpr_idx, 1);
1107 }
1108 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1109 &user_sgpr_idx, 2);
1110 if (ctx->abi.view_index)
1111 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1112 if (has_previous_stage)
1113 ac_declare_lds_as_pointer(&ctx->ac);
1114 break;
1115 case MESA_SHADER_FRAGMENT:
1116 if (ctx->shader_info->info.ps.needs_sample_positions) {
1117 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1118 &user_sgpr_idx, 1);
1119 }
1120 break;
1121 default:
1122 unreachable("Shader stage not implemented");
1123 }
1124
1125 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1126 }
1127
1128 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1129 LLVMValueRef value, unsigned count)
1130 {
1131 unsigned num_components = ac_get_llvm_num_components(value);
1132 if (count == num_components)
1133 return value;
1134
1135 LLVMValueRef masks[] = {
1136 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1137 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1138
1139 if (count == 1)
1140 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1141 "");
1142
1143 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1144 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1145 }
1146
1147 static void
1148 build_store_values_extended(struct ac_llvm_context *ac,
1149 LLVMValueRef *values,
1150 unsigned value_count,
1151 unsigned value_stride,
1152 LLVMValueRef vec)
1153 {
1154 LLVMBuilderRef builder = ac->builder;
1155 unsigned i;
1156
1157 for (i = 0; i < value_count; i++) {
1158 LLVMValueRef ptr = values[i * value_stride];
1159 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1160 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1161 LLVMBuildStore(builder, value, ptr);
1162 }
1163 }
1164
1165 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1166 const nir_ssa_def *def)
1167 {
1168 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1169 if (def->num_components > 1) {
1170 type = LLVMVectorType(type, def->num_components);
1171 }
1172 return type;
1173 }
1174
1175 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1176 {
1177 assert(src.is_ssa);
1178 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1179 return (LLVMValueRef)entry->data;
1180 }
1181
1182
1183 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1184 const struct nir_block *b)
1185 {
1186 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1187 return (LLVMBasicBlockRef)entry->data;
1188 }
1189
1190 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1191 nir_alu_src src,
1192 unsigned num_components)
1193 {
1194 LLVMValueRef value = get_src(ctx, src.src);
1195 bool need_swizzle = false;
1196
1197 assert(value);
1198 LLVMTypeRef type = LLVMTypeOf(value);
1199 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1200 ? LLVMGetVectorSize(type)
1201 : 1;
1202
1203 for (unsigned i = 0; i < num_components; ++i) {
1204 assert(src.swizzle[i] < src_components);
1205 if (src.swizzle[i] != i)
1206 need_swizzle = true;
1207 }
1208
1209 if (need_swizzle || num_components != src_components) {
1210 LLVMValueRef masks[] = {
1211 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1212 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1213 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1214 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1215
1216 if (src_components > 1 && num_components == 1) {
1217 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1218 masks[0], "");
1219 } else if (src_components == 1 && num_components > 1) {
1220 LLVMValueRef values[] = {value, value, value, value};
1221 value = ac_build_gather_values(&ctx->ac, values, num_components);
1222 } else {
1223 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1224 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1225 swizzle, "");
1226 }
1227 }
1228 assert(!src.negate);
1229 assert(!src.abs);
1230 return value;
1231 }
1232
1233 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1234 LLVMIntPredicate pred, LLVMValueRef src0,
1235 LLVMValueRef src1)
1236 {
1237 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1238 return LLVMBuildSelect(ctx->builder, result,
1239 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1240 ctx->i32_0, "");
1241 }
1242
1243 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1244 LLVMRealPredicate pred, LLVMValueRef src0,
1245 LLVMValueRef src1)
1246 {
1247 LLVMValueRef result;
1248 src0 = ac_to_float(ctx, src0);
1249 src1 = ac_to_float(ctx, src1);
1250 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1251 return LLVMBuildSelect(ctx->builder, result,
1252 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1253 ctx->i32_0, "");
1254 }
1255
1256 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1257 const char *intrin,
1258 LLVMTypeRef result_type,
1259 LLVMValueRef src0)
1260 {
1261 char name[64];
1262 LLVMValueRef params[] = {
1263 ac_to_float(ctx, src0),
1264 };
1265
1266 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1267 ac_get_elem_bits(ctx, result_type));
1268 assert(length < sizeof(name));
1269 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1270 }
1271
1272 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1273 const char *intrin,
1274 LLVMTypeRef result_type,
1275 LLVMValueRef src0, LLVMValueRef src1)
1276 {
1277 char name[64];
1278 LLVMValueRef params[] = {
1279 ac_to_float(ctx, src0),
1280 ac_to_float(ctx, src1),
1281 };
1282
1283 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1284 ac_get_elem_bits(ctx, result_type));
1285 assert(length < sizeof(name));
1286 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1287 }
1288
1289 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1290 const char *intrin,
1291 LLVMTypeRef result_type,
1292 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1293 {
1294 char name[64];
1295 LLVMValueRef params[] = {
1296 ac_to_float(ctx, src0),
1297 ac_to_float(ctx, src1),
1298 ac_to_float(ctx, src2),
1299 };
1300
1301 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1302 ac_get_elem_bits(ctx, result_type));
1303 assert(length < sizeof(name));
1304 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1305 }
1306
1307 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1308 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1309 {
1310 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1311 ctx->i32_0, "");
1312 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1313 }
1314
1315 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1316 LLVMIntPredicate pred,
1317 LLVMValueRef src0, LLVMValueRef src1)
1318 {
1319 return LLVMBuildSelect(ctx->builder,
1320 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1321 src0,
1322 src1, "");
1323
1324 }
1325 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1326 LLVMValueRef src0)
1327 {
1328 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1329 LLVMBuildNeg(ctx->builder, src0, ""));
1330 }
1331
1332 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1333 LLVMValueRef src0,
1334 unsigned bitsize)
1335 {
1336 LLVMValueRef cmp, val, zero, one;
1337 LLVMTypeRef type;
1338
1339 if (bitsize == 32) {
1340 type = ctx->f32;
1341 zero = ctx->f32_0;
1342 one = ctx->f32_1;
1343 } else {
1344 type = ctx->f64;
1345 zero = ctx->f64_0;
1346 one = ctx->f64_1;
1347 }
1348
1349 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1350 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1351 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1352 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1353 return val;
1354 }
1355
1356 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0, unsigned bitsize)
1358 {
1359 LLVMValueRef cmp, val, zero, one;
1360 LLVMTypeRef type;
1361
1362 if (bitsize == 32) {
1363 type = ctx->i32;
1364 zero = ctx->i32_0;
1365 one = ctx->i32_1;
1366 } else {
1367 type = ctx->i64;
1368 zero = ctx->i64_0;
1369 one = ctx->i64_1;
1370 }
1371
1372 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1373 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1374 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1375 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1376 return val;
1377 }
1378
1379 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1380 LLVMValueRef src0, unsigned bitsize)
1381 {
1382 LLVMTypeRef type;
1383 char *intr;
1384
1385 if (bitsize == 32) {
1386 intr = "llvm.floor.f32";
1387 type = ctx->f32;
1388 } else {
1389 intr = "llvm.floor.f64";
1390 type = ctx->f64;
1391 }
1392
1393 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1394 LLVMValueRef params[] = {
1395 fsrc0,
1396 };
1397 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1398 AC_FUNC_ATTR_READNONE);
1399 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1400 }
1401
1402 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1403 const char *intrin,
1404 LLVMValueRef src0, LLVMValueRef src1)
1405 {
1406 LLVMTypeRef ret_type;
1407 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1408 LLVMValueRef res;
1409 LLVMValueRef params[] = { src0, src1 };
1410 ret_type = LLVMStructTypeInContext(ctx->context, types,
1411 2, true);
1412
1413 res = ac_build_intrinsic(ctx, intrin, ret_type,
1414 params, 2, AC_FUNC_ATTR_READNONE);
1415
1416 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1417 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1418 return res;
1419 }
1420
1421 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1422 LLVMValueRef src0)
1423 {
1424 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1425 }
1426
1427 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1428 LLVMValueRef src0)
1429 {
1430 src0 = ac_to_float(ctx, src0);
1431 return LLVMBuildSExt(ctx->builder,
1432 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1433 ctx->i32, "");
1434 }
1435
1436 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1437 LLVMValueRef src0,
1438 unsigned bitsize)
1439 {
1440 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1441
1442 if (bitsize == 32)
1443 return result;
1444
1445 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1446 }
1447
1448 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1449 LLVMValueRef src0)
1450 {
1451 return LLVMBuildSExt(ctx->builder,
1452 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1453 ctx->i32, "");
1454 }
1455
1456 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1457 LLVMValueRef src0)
1458 {
1459 LLVMValueRef result;
1460 LLVMValueRef cond = NULL;
1461
1462 src0 = ac_to_float(ctx, src0);
1463 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1464
1465 if (ctx->chip_class >= VI) {
1466 LLVMValueRef args[2];
1467 /* Check if the result is a denormal - and flush to 0 if so. */
1468 args[0] = result;
1469 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1470 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1471 }
1472
1473 /* need to convert back up to f32 */
1474 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1475
1476 if (ctx->chip_class >= VI)
1477 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1478 else {
1479 /* for SI/CIK */
1480 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1481 * so compare the result and flush to 0 if it's smaller.
1482 */
1483 LLVMValueRef temp, cond2;
1484 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1485 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1486 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1487 temp, "");
1488 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1489 temp, ctx->f32_0, "");
1490 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1491 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1492 }
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1)
1498 {
1499 LLVMValueRef dst64, result;
1500 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1501 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1502
1503 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1504 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1505 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1510 LLVMValueRef src0, LLVMValueRef src1)
1511 {
1512 LLVMValueRef dst64, result;
1513 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1514 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1515
1516 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1517 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1518 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1519 return result;
1520 }
1521
1522 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1523 bool is_signed,
1524 const LLVMValueRef srcs[3])
1525 {
1526 LLVMValueRef result;
1527 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1528
1529 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1530 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1531 return result;
1532 }
1533
1534 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1535 LLVMValueRef src0, LLVMValueRef src1,
1536 LLVMValueRef src2, LLVMValueRef src3)
1537 {
1538 LLVMValueRef bfi_args[3], result;
1539
1540 bfi_args[0] = LLVMBuildShl(ctx->builder,
1541 LLVMBuildSub(ctx->builder,
1542 LLVMBuildShl(ctx->builder,
1543 ctx->i32_1,
1544 src3, ""),
1545 ctx->i32_1, ""),
1546 src2, "");
1547 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1548 bfi_args[2] = src0;
1549
1550 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1551
1552 /* Calculate:
1553 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1554 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1555 */
1556 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1557 LLVMBuildAnd(ctx->builder, bfi_args[0],
1558 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1559
1560 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1561 return result;
1562 }
1563
1564 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1565 LLVMValueRef src0)
1566 {
1567 LLVMValueRef comp[2];
1568
1569 src0 = ac_to_float(ctx, src0);
1570 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1571 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1572
1573 return ac_build_cvt_pkrtz_f16(ctx, comp);
1574 }
1575
1576 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1577 LLVMValueRef src0)
1578 {
1579 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1580 LLVMValueRef temps[2], result, val;
1581 int i;
1582
1583 for (i = 0; i < 2; i++) {
1584 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1585 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1586 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1587 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1588 }
1589
1590 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1591 ctx->i32_0, "");
1592 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1593 ctx->i32_1, "");
1594 return result;
1595 }
1596
1597 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1598 nir_op op,
1599 LLVMValueRef src0)
1600 {
1601 unsigned mask;
1602 int idx;
1603 LLVMValueRef result;
1604
1605 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1606 mask = AC_TID_MASK_LEFT;
1607 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1608 mask = AC_TID_MASK_TOP;
1609 else
1610 mask = AC_TID_MASK_TOP_LEFT;
1611
1612 /* for DDX we want to next X pixel, DDY next Y pixel. */
1613 if (op == nir_op_fddx_fine ||
1614 op == nir_op_fddx_coarse ||
1615 op == nir_op_fddx)
1616 idx = 1;
1617 else
1618 idx = 2;
1619
1620 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1621 return result;
1622 }
1623
1624 /*
1625 * this takes an I,J coordinate pair,
1626 * and works out the X and Y derivatives.
1627 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1628 */
1629 static LLVMValueRef emit_ddxy_interp(
1630 struct ac_nir_context *ctx,
1631 LLVMValueRef interp_ij)
1632 {
1633 LLVMValueRef result[4], a;
1634 unsigned i;
1635
1636 for (i = 0; i < 2; i++) {
1637 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1638 LLVMConstInt(ctx->ac.i32, i, false), "");
1639 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1640 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1641 }
1642 return ac_build_gather_values(&ctx->ac, result, 4);
1643 }
1644
1645 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1646 {
1647 LLVMValueRef src[4], result = NULL;
1648 unsigned num_components = instr->dest.dest.ssa.num_components;
1649 unsigned src_components;
1650 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1651
1652 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1653 switch (instr->op) {
1654 case nir_op_vec2:
1655 case nir_op_vec3:
1656 case nir_op_vec4:
1657 src_components = 1;
1658 break;
1659 case nir_op_pack_half_2x16:
1660 src_components = 2;
1661 break;
1662 case nir_op_unpack_half_2x16:
1663 src_components = 1;
1664 break;
1665 default:
1666 src_components = num_components;
1667 break;
1668 }
1669 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1670 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1671
1672 switch (instr->op) {
1673 case nir_op_fmov:
1674 case nir_op_imov:
1675 result = src[0];
1676 break;
1677 case nir_op_fneg:
1678 src[0] = ac_to_float(&ctx->ac, src[0]);
1679 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1680 break;
1681 case nir_op_ineg:
1682 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1683 break;
1684 case nir_op_inot:
1685 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1686 break;
1687 case nir_op_iadd:
1688 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_fadd:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 src[1] = ac_to_float(&ctx->ac, src[1]);
1693 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1694 break;
1695 case nir_op_fsub:
1696 src[0] = ac_to_float(&ctx->ac, src[0]);
1697 src[1] = ac_to_float(&ctx->ac, src[1]);
1698 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1699 break;
1700 case nir_op_isub:
1701 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_imul:
1704 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_imod:
1707 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1708 break;
1709 case nir_op_umod:
1710 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1711 break;
1712 case nir_op_fmod:
1713 src[0] = ac_to_float(&ctx->ac, src[0]);
1714 src[1] = ac_to_float(&ctx->ac, src[1]);
1715 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1716 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1717 ac_to_float_type(&ctx->ac, def_type), result);
1718 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1719 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1720 break;
1721 case nir_op_frem:
1722 src[0] = ac_to_float(&ctx->ac, src[0]);
1723 src[1] = ac_to_float(&ctx->ac, src[1]);
1724 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1725 break;
1726 case nir_op_irem:
1727 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1728 break;
1729 case nir_op_idiv:
1730 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1731 break;
1732 case nir_op_udiv:
1733 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1734 break;
1735 case nir_op_fmul:
1736 src[0] = ac_to_float(&ctx->ac, src[0]);
1737 src[1] = ac_to_float(&ctx->ac, src[1]);
1738 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1739 break;
1740 case nir_op_frcp:
1741 src[0] = ac_to_float(&ctx->ac, src[0]);
1742 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1743 src[0]);
1744 break;
1745 case nir_op_iand:
1746 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1747 break;
1748 case nir_op_ior:
1749 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1750 break;
1751 case nir_op_ixor:
1752 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1753 break;
1754 case nir_op_ishl:
1755 result = LLVMBuildShl(ctx->ac.builder, src[0],
1756 LLVMBuildZExt(ctx->ac.builder, src[1],
1757 LLVMTypeOf(src[0]), ""),
1758 "");
1759 break;
1760 case nir_op_ishr:
1761 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1762 LLVMBuildZExt(ctx->ac.builder, src[1],
1763 LLVMTypeOf(src[0]), ""),
1764 "");
1765 break;
1766 case nir_op_ushr:
1767 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1768 LLVMBuildZExt(ctx->ac.builder, src[1],
1769 LLVMTypeOf(src[0]), ""),
1770 "");
1771 break;
1772 case nir_op_ilt:
1773 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1774 break;
1775 case nir_op_ine:
1776 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1777 break;
1778 case nir_op_ieq:
1779 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1780 break;
1781 case nir_op_ige:
1782 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1783 break;
1784 case nir_op_ult:
1785 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1786 break;
1787 case nir_op_uge:
1788 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1789 break;
1790 case nir_op_feq:
1791 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1792 break;
1793 case nir_op_fne:
1794 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1795 break;
1796 case nir_op_flt:
1797 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1798 break;
1799 case nir_op_fge:
1800 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1801 break;
1802 case nir_op_fabs:
1803 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1804 ac_to_float_type(&ctx->ac, def_type), src[0]);
1805 break;
1806 case nir_op_iabs:
1807 result = emit_iabs(&ctx->ac, src[0]);
1808 break;
1809 case nir_op_imax:
1810 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1811 break;
1812 case nir_op_imin:
1813 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1814 break;
1815 case nir_op_umax:
1816 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1817 break;
1818 case nir_op_umin:
1819 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1820 break;
1821 case nir_op_isign:
1822 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1823 break;
1824 case nir_op_fsign:
1825 src[0] = ac_to_float(&ctx->ac, src[0]);
1826 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1827 break;
1828 case nir_op_ffloor:
1829 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1830 ac_to_float_type(&ctx->ac, def_type), src[0]);
1831 break;
1832 case nir_op_ftrunc:
1833 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1834 ac_to_float_type(&ctx->ac, def_type), src[0]);
1835 break;
1836 case nir_op_fceil:
1837 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1838 ac_to_float_type(&ctx->ac, def_type), src[0]);
1839 break;
1840 case nir_op_fround_even:
1841 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1842 ac_to_float_type(&ctx->ac, def_type),src[0]);
1843 break;
1844 case nir_op_ffract:
1845 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1846 break;
1847 case nir_op_fsin:
1848 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1849 ac_to_float_type(&ctx->ac, def_type), src[0]);
1850 break;
1851 case nir_op_fcos:
1852 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1853 ac_to_float_type(&ctx->ac, def_type), src[0]);
1854 break;
1855 case nir_op_fsqrt:
1856 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1857 ac_to_float_type(&ctx->ac, def_type), src[0]);
1858 break;
1859 case nir_op_fexp2:
1860 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1861 ac_to_float_type(&ctx->ac, def_type), src[0]);
1862 break;
1863 case nir_op_flog2:
1864 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1865 ac_to_float_type(&ctx->ac, def_type), src[0]);
1866 break;
1867 case nir_op_frsq:
1868 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1869 ac_to_float_type(&ctx->ac, def_type), src[0]);
1870 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1871 result);
1872 break;
1873 case nir_op_fpow:
1874 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1875 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1876 break;
1877 case nir_op_fmax:
1878 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1879 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1880 if (ctx->ac.chip_class < GFX9 &&
1881 instr->dest.dest.ssa.bit_size == 32) {
1882 /* Only pre-GFX9 chips do not flush denorms. */
1883 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1884 ac_to_float_type(&ctx->ac, def_type),
1885 result);
1886 }
1887 break;
1888 case nir_op_fmin:
1889 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1890 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1891 if (ctx->ac.chip_class < GFX9 &&
1892 instr->dest.dest.ssa.bit_size == 32) {
1893 /* Only pre-GFX9 chips do not flush denorms. */
1894 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1895 ac_to_float_type(&ctx->ac, def_type),
1896 result);
1897 }
1898 break;
1899 case nir_op_ffma:
1900 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1901 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1902 break;
1903 case nir_op_ibitfield_extract:
1904 result = emit_bitfield_extract(&ctx->ac, true, src);
1905 break;
1906 case nir_op_ubitfield_extract:
1907 result = emit_bitfield_extract(&ctx->ac, false, src);
1908 break;
1909 case nir_op_bitfield_insert:
1910 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1911 break;
1912 case nir_op_bitfield_reverse:
1913 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1914 break;
1915 case nir_op_bit_count:
1916 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1917 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1918 else {
1919 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1920 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1921 }
1922 break;
1923 case nir_op_vec2:
1924 case nir_op_vec3:
1925 case nir_op_vec4:
1926 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1927 src[i] = ac_to_integer(&ctx->ac, src[i]);
1928 result = ac_build_gather_values(&ctx->ac, src, num_components);
1929 break;
1930 case nir_op_f2i32:
1931 case nir_op_f2i64:
1932 src[0] = ac_to_float(&ctx->ac, src[0]);
1933 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1934 break;
1935 case nir_op_f2u32:
1936 case nir_op_f2u64:
1937 src[0] = ac_to_float(&ctx->ac, src[0]);
1938 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1939 break;
1940 case nir_op_i2f32:
1941 case nir_op_i2f64:
1942 src[0] = ac_to_integer(&ctx->ac, src[0]);
1943 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1944 break;
1945 case nir_op_u2f32:
1946 case nir_op_u2f64:
1947 src[0] = ac_to_integer(&ctx->ac, src[0]);
1948 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1949 break;
1950 case nir_op_f2f64:
1951 src[0] = ac_to_float(&ctx->ac, src[0]);
1952 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1953 break;
1954 case nir_op_f2f32:
1955 src[0] = ac_to_float(&ctx->ac, src[0]);
1956 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1957 break;
1958 case nir_op_u2u32:
1959 case nir_op_u2u64:
1960 src[0] = ac_to_integer(&ctx->ac, src[0]);
1961 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1962 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1963 else
1964 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1965 break;
1966 case nir_op_i2i32:
1967 case nir_op_i2i64:
1968 src[0] = ac_to_integer(&ctx->ac, src[0]);
1969 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1970 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1971 else
1972 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1973 break;
1974 case nir_op_bcsel:
1975 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1976 break;
1977 case nir_op_find_lsb:
1978 src[0] = ac_to_integer(&ctx->ac, src[0]);
1979 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1980 break;
1981 case nir_op_ufind_msb:
1982 src[0] = ac_to_integer(&ctx->ac, src[0]);
1983 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1984 break;
1985 case nir_op_ifind_msb:
1986 src[0] = ac_to_integer(&ctx->ac, src[0]);
1987 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1988 break;
1989 case nir_op_uadd_carry:
1990 src[0] = ac_to_integer(&ctx->ac, src[0]);
1991 src[1] = ac_to_integer(&ctx->ac, src[1]);
1992 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1993 break;
1994 case nir_op_usub_borrow:
1995 src[0] = ac_to_integer(&ctx->ac, src[0]);
1996 src[1] = ac_to_integer(&ctx->ac, src[1]);
1997 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1998 break;
1999 case nir_op_b2f:
2000 result = emit_b2f(&ctx->ac, src[0]);
2001 break;
2002 case nir_op_f2b:
2003 result = emit_f2b(&ctx->ac, src[0]);
2004 break;
2005 case nir_op_b2i:
2006 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2007 break;
2008 case nir_op_i2b:
2009 src[0] = ac_to_integer(&ctx->ac, src[0]);
2010 result = emit_i2b(&ctx->ac, src[0]);
2011 break;
2012 case nir_op_fquantize2f16:
2013 result = emit_f2f16(&ctx->ac, src[0]);
2014 break;
2015 case nir_op_umul_high:
2016 src[0] = ac_to_integer(&ctx->ac, src[0]);
2017 src[1] = ac_to_integer(&ctx->ac, src[1]);
2018 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2019 break;
2020 case nir_op_imul_high:
2021 src[0] = ac_to_integer(&ctx->ac, src[0]);
2022 src[1] = ac_to_integer(&ctx->ac, src[1]);
2023 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2024 break;
2025 case nir_op_pack_half_2x16:
2026 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2027 break;
2028 case nir_op_unpack_half_2x16:
2029 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2030 break;
2031 case nir_op_fddx:
2032 case nir_op_fddy:
2033 case nir_op_fddx_fine:
2034 case nir_op_fddy_fine:
2035 case nir_op_fddx_coarse:
2036 case nir_op_fddy_coarse:
2037 result = emit_ddxy(ctx, instr->op, src[0]);
2038 break;
2039
2040 case nir_op_unpack_64_2x32_split_x: {
2041 assert(ac_get_llvm_num_components(src[0]) == 1);
2042 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2043 ctx->ac.v2i32,
2044 "");
2045 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2046 ctx->ac.i32_0, "");
2047 break;
2048 }
2049
2050 case nir_op_unpack_64_2x32_split_y: {
2051 assert(ac_get_llvm_num_components(src[0]) == 1);
2052 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2053 ctx->ac.v2i32,
2054 "");
2055 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2056 ctx->ac.i32_1, "");
2057 break;
2058 }
2059
2060 case nir_op_pack_64_2x32_split: {
2061 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2062 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2063 src[0], ctx->ac.i32_0, "");
2064 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2065 src[1], ctx->ac.i32_1, "");
2066 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2067 break;
2068 }
2069
2070 default:
2071 fprintf(stderr, "Unknown NIR alu instr: ");
2072 nir_print_instr(&instr->instr, stderr);
2073 fprintf(stderr, "\n");
2074 abort();
2075 }
2076
2077 if (result) {
2078 assert(instr->dest.dest.is_ssa);
2079 result = ac_to_integer(&ctx->ac, result);
2080 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2081 result);
2082 }
2083 }
2084
2085 static void visit_load_const(struct ac_nir_context *ctx,
2086 const nir_load_const_instr *instr)
2087 {
2088 LLVMValueRef values[4], value = NULL;
2089 LLVMTypeRef element_type =
2090 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2091
2092 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2093 switch (instr->def.bit_size) {
2094 case 32:
2095 values[i] = LLVMConstInt(element_type,
2096 instr->value.u32[i], false);
2097 break;
2098 case 64:
2099 values[i] = LLVMConstInt(element_type,
2100 instr->value.u64[i], false);
2101 break;
2102 default:
2103 fprintf(stderr,
2104 "unsupported nir load_const bit_size: %d\n",
2105 instr->def.bit_size);
2106 abort();
2107 }
2108 }
2109 if (instr->def.num_components > 1) {
2110 value = LLVMConstVector(values, instr->def.num_components);
2111 } else
2112 value = values[0];
2113
2114 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2115 }
2116
2117 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2118 LLVMTypeRef type)
2119 {
2120 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2121 return LLVMBuildBitCast(ctx->builder, ptr,
2122 LLVMPointerType(type, addr_space), "");
2123 }
2124
2125 static LLVMValueRef
2126 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2127 {
2128 LLVMValueRef size =
2129 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2130 LLVMConstInt(ctx->ac.i32, 2, false), "");
2131
2132 /* VI only */
2133 if (ctx->ac.chip_class == VI && in_elements) {
2134 /* On VI, the descriptor contains the size in bytes,
2135 * but TXQ must return the size in elements.
2136 * The stride is always non-zero for resources using TXQ.
2137 */
2138 LLVMValueRef stride =
2139 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2140 ctx->ac.i32_1, "");
2141 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2142 LLVMConstInt(ctx->ac.i32, 16, false), "");
2143 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2144 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2145
2146 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2147 }
2148 return size;
2149 }
2150
2151 /**
2152 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2153 * intrinsic names).
2154 */
2155 static void build_int_type_name(
2156 LLVMTypeRef type,
2157 char *buf, unsigned bufsize)
2158 {
2159 assert(bufsize >= 6);
2160
2161 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2162 snprintf(buf, bufsize, "v%ui32",
2163 LLVMGetVectorSize(type));
2164 else
2165 strcpy(buf, "i32");
2166 }
2167
2168 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2169 struct ac_image_args *args,
2170 const nir_tex_instr *instr)
2171 {
2172 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2173 LLVMValueRef coord = args->addr;
2174 LLVMValueRef half_texel[2];
2175 LLVMValueRef compare_cube_wa = NULL;
2176 LLVMValueRef result;
2177 int c;
2178 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2179
2180 //TODO Rect
2181 {
2182 struct ac_image_args txq_args = { 0 };
2183
2184 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2185 txq_args.opcode = ac_image_get_resinfo;
2186 txq_args.dmask = 0xf;
2187 txq_args.addr = ctx->i32_0;
2188 txq_args.resource = args->resource;
2189 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2190
2191 for (c = 0; c < 2; c++) {
2192 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2193 LLVMConstInt(ctx->i32, c, false), "");
2194 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2195 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2196 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2197 LLVMConstReal(ctx->f32, -0.5), "");
2198 }
2199 }
2200
2201 LLVMValueRef orig_coords = args->addr;
2202
2203 for (c = 0; c < 2; c++) {
2204 LLVMValueRef tmp;
2205 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2206 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2207 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2208 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2209 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2210 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2211 }
2212
2213
2214 /*
2215 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2216 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2217 * workaround by sampling using a scaled type and converting.
2218 * This is taken from amdgpu-pro shaders.
2219 */
2220 /* NOTE this produces some ugly code compared to amdgpu-pro,
2221 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2222 * and then reads them back. -pro generates two selects,
2223 * one s_cmp for the descriptor rewriting
2224 * one v_cmp for the coordinate and result changes.
2225 */
2226 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2227 LLVMValueRef tmp, tmp2;
2228
2229 /* workaround 8/8/8/8 uint/sint cube gather bug */
2230 /* first detect it then change to a scaled read and f2i */
2231 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2232 tmp2 = tmp;
2233
2234 /* extract the DATA_FORMAT */
2235 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2236 LLVMConstInt(ctx->i32, 6, false), false);
2237
2238 /* is the DATA_FORMAT == 8_8_8_8 */
2239 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2240
2241 if (stype == GLSL_TYPE_UINT)
2242 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2243 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2244 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2245 else
2246 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2247 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2248 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2249
2250 /* replace the NUM FORMAT in the descriptor */
2251 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2252 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2253
2254 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2255
2256 /* don't modify the coordinates for this case */
2257 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2258 }
2259 args->addr = coord;
2260 result = ac_build_image_opcode(ctx, args);
2261
2262 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2263 LLVMValueRef tmp, tmp2;
2264
2265 /* if the cube workaround is in place, f2i the result. */
2266 for (c = 0; c < 4; c++) {
2267 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2268 if (stype == GLSL_TYPE_UINT)
2269 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2270 else
2271 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2272 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2273 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2274 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2275 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2276 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2277 }
2278 }
2279 return result;
2280 }
2281
2282 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2283 const nir_tex_instr *instr,
2284 bool lod_is_zero,
2285 struct ac_image_args *args)
2286 {
2287 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2288 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2289
2290 return ac_build_buffer_load_format(&ctx->ac,
2291 args->resource,
2292 args->addr,
2293 ctx->ac.i32_0,
2294 util_last_bit(mask),
2295 false, true);
2296 }
2297
2298 args->opcode = ac_image_sample;
2299 args->compare = instr->is_shadow;
2300
2301 switch (instr->op) {
2302 case nir_texop_txf:
2303 case nir_texop_txf_ms:
2304 case nir_texop_samples_identical:
2305 args->opcode = lod_is_zero ||
2306 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2307 ac_image_load : ac_image_load_mip;
2308 args->compare = false;
2309 args->offset = false;
2310 break;
2311 case nir_texop_txb:
2312 args->bias = true;
2313 break;
2314 case nir_texop_txl:
2315 if (lod_is_zero)
2316 args->level_zero = true;
2317 else
2318 args->lod = true;
2319 break;
2320 case nir_texop_txs:
2321 case nir_texop_query_levels:
2322 args->opcode = ac_image_get_resinfo;
2323 break;
2324 case nir_texop_tex:
2325 if (ctx->stage != MESA_SHADER_FRAGMENT)
2326 args->level_zero = true;
2327 break;
2328 case nir_texop_txd:
2329 args->deriv = true;
2330 break;
2331 case nir_texop_tg4:
2332 args->opcode = ac_image_gather4;
2333 args->level_zero = true;
2334 break;
2335 case nir_texop_lod:
2336 args->opcode = ac_image_get_lod;
2337 args->compare = false;
2338 args->offset = false;
2339 break;
2340 default:
2341 break;
2342 }
2343
2344 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2345 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2346 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2347 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2348 }
2349 }
2350 return ac_build_image_opcode(&ctx->ac, args);
2351 }
2352
2353 static LLVMValueRef
2354 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2355 unsigned desc_set, unsigned binding)
2356 {
2357 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2358 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2359 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2360 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2361 unsigned base_offset = layout->binding[binding].offset;
2362 LLVMValueRef offset, stride;
2363
2364 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2365 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2366 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2367 layout->binding[binding].dynamic_offset_offset;
2368 desc_ptr = ctx->abi.push_constants;
2369 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2370 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2371 } else
2372 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2373
2374 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2375 index = LLVMBuildMul(ctx->builder, index, stride, "");
2376 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2377
2378 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2379 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2380 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2381
2382 return desc_ptr;
2383 }
2384
2385 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2386 nir_intrinsic_instr *instr)
2387 {
2388 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2389 LLVMValueRef index = get_src(ctx, instr->src[1]);
2390
2391 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2392 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2393 return result;
2394 }
2395
2396 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2397 nir_intrinsic_instr *instr)
2398 {
2399 LLVMValueRef ptr, addr;
2400
2401 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2402 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2403 get_src(ctx, instr->src[0]), "");
2404
2405 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2406 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2407
2408 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2409 }
2410
2411 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2412 const nir_intrinsic_instr *instr)
2413 {
2414 LLVMValueRef index = get_src(ctx, instr->src[0]);
2415
2416 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2417 }
2418
2419 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2420 {
2421 uint32_t new_mask = 0;
2422 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2423 if (mask & (1u << i))
2424 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2425 return new_mask;
2426 }
2427
2428 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2429 unsigned start, unsigned count)
2430 {
2431 LLVMTypeRef type = LLVMTypeOf(src);
2432
2433 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2434 assert(start == 0);
2435 assert(count == 1);
2436 return src;
2437 }
2438
2439 unsigned src_elements = LLVMGetVectorSize(type);
2440 assert(start < src_elements);
2441 assert(start + count <= src_elements);
2442
2443 if (start == 0 && count == src_elements)
2444 return src;
2445
2446 if (count == 1)
2447 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2448
2449 assert(count <= 8);
2450 LLVMValueRef indices[8];
2451 for (unsigned i = 0; i < count; ++i)
2452 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2453
2454 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2455 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2456 }
2457
2458 static void visit_store_ssbo(struct ac_nir_context *ctx,
2459 nir_intrinsic_instr *instr)
2460 {
2461 const char *store_name;
2462 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2463 LLVMTypeRef data_type = ctx->ac.f32;
2464 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2465 int components_32bit = elem_size_mult * instr->num_components;
2466 unsigned writemask = nir_intrinsic_write_mask(instr);
2467 LLVMValueRef base_data, base_offset;
2468 LLVMValueRef params[6];
2469
2470 params[1] = ctx->abi->load_ssbo(ctx->abi,
2471 get_src(ctx, instr->src[1]), true);
2472 params[2] = ctx->ac.i32_0; /* vindex */
2473 params[4] = ctx->ac.i1false; /* glc */
2474 params[5] = ctx->ac.i1false; /* slc */
2475
2476 if (components_32bit > 1)
2477 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2478
2479 writemask = widen_mask(writemask, elem_size_mult);
2480
2481 base_data = ac_to_float(&ctx->ac, src_data);
2482 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2483 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2484 data_type, "");
2485 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2486 while (writemask) {
2487 int start, count;
2488 LLVMValueRef data;
2489 LLVMValueRef offset;
2490
2491 u_bit_scan_consecutive_range(&writemask, &start, &count);
2492
2493 /* Due to an LLVM limitation, split 3-element writes
2494 * into a 2-element and a 1-element write. */
2495 if (count == 3) {
2496 writemask |= 1 << (start + 2);
2497 count = 2;
2498 }
2499
2500 if (count > 4) {
2501 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2502 count = 4;
2503 }
2504
2505 if (count == 4) {
2506 store_name = "llvm.amdgcn.buffer.store.v4f32";
2507 } else if (count == 2) {
2508 store_name = "llvm.amdgcn.buffer.store.v2f32";
2509
2510 } else {
2511 assert(count == 1);
2512 store_name = "llvm.amdgcn.buffer.store.f32";
2513 }
2514 data = extract_vector_range(&ctx->ac, base_data, start, count);
2515
2516 offset = base_offset;
2517 if (start != 0) {
2518 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2519 }
2520 params[0] = data;
2521 params[3] = offset;
2522 ac_build_intrinsic(&ctx->ac, store_name,
2523 ctx->ac.voidt, params, 6, 0);
2524 }
2525 }
2526
2527 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2528 const nir_intrinsic_instr *instr)
2529 {
2530 const char *name;
2531 LLVMValueRef params[6];
2532 int arg_count = 0;
2533
2534 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2535 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2536 }
2537 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2538 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2539 get_src(ctx, instr->src[0]),
2540 true);
2541 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2542 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2543 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2544
2545 switch (instr->intrinsic) {
2546 case nir_intrinsic_ssbo_atomic_add:
2547 name = "llvm.amdgcn.buffer.atomic.add";
2548 break;
2549 case nir_intrinsic_ssbo_atomic_imin:
2550 name = "llvm.amdgcn.buffer.atomic.smin";
2551 break;
2552 case nir_intrinsic_ssbo_atomic_umin:
2553 name = "llvm.amdgcn.buffer.atomic.umin";
2554 break;
2555 case nir_intrinsic_ssbo_atomic_imax:
2556 name = "llvm.amdgcn.buffer.atomic.smax";
2557 break;
2558 case nir_intrinsic_ssbo_atomic_umax:
2559 name = "llvm.amdgcn.buffer.atomic.umax";
2560 break;
2561 case nir_intrinsic_ssbo_atomic_and:
2562 name = "llvm.amdgcn.buffer.atomic.and";
2563 break;
2564 case nir_intrinsic_ssbo_atomic_or:
2565 name = "llvm.amdgcn.buffer.atomic.or";
2566 break;
2567 case nir_intrinsic_ssbo_atomic_xor:
2568 name = "llvm.amdgcn.buffer.atomic.xor";
2569 break;
2570 case nir_intrinsic_ssbo_atomic_exchange:
2571 name = "llvm.amdgcn.buffer.atomic.swap";
2572 break;
2573 case nir_intrinsic_ssbo_atomic_comp_swap:
2574 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2575 break;
2576 default:
2577 abort();
2578 }
2579
2580 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2581 }
2582
2583 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2584 const nir_intrinsic_instr *instr)
2585 {
2586 LLVMValueRef results[2];
2587 int load_components;
2588 int num_components = instr->num_components;
2589 if (instr->dest.ssa.bit_size == 64)
2590 num_components *= 2;
2591
2592 for (int i = 0; i < num_components; i += load_components) {
2593 load_components = MIN2(num_components - i, 4);
2594 const char *load_name;
2595 LLVMTypeRef data_type = ctx->ac.f32;
2596 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2597 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2598
2599 if (load_components == 3)
2600 data_type = LLVMVectorType(ctx->ac.f32, 4);
2601 else if (load_components > 1)
2602 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2603
2604 if (load_components >= 3)
2605 load_name = "llvm.amdgcn.buffer.load.v4f32";
2606 else if (load_components == 2)
2607 load_name = "llvm.amdgcn.buffer.load.v2f32";
2608 else if (load_components == 1)
2609 load_name = "llvm.amdgcn.buffer.load.f32";
2610 else
2611 unreachable("unhandled number of components");
2612
2613 LLVMValueRef params[] = {
2614 ctx->abi->load_ssbo(ctx->abi,
2615 get_src(ctx, instr->src[0]),
2616 false),
2617 ctx->ac.i32_0,
2618 offset,
2619 ctx->ac.i1false,
2620 ctx->ac.i1false,
2621 };
2622
2623 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2624 }
2625
2626 assume(results[0]);
2627 LLVMValueRef ret = results[0];
2628 if (num_components > 4 || num_components == 3) {
2629 LLVMValueRef masks[] = {
2630 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2631 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2632 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2633 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2634 };
2635
2636 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2637 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2638 results[num_components > 4 ? 1 : 0], swizzle, "");
2639 }
2640
2641 return LLVMBuildBitCast(ctx->ac.builder, ret,
2642 get_def_type(ctx, &instr->dest.ssa), "");
2643 }
2644
2645 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2646 const nir_intrinsic_instr *instr)
2647 {
2648 LLVMValueRef ret;
2649 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2650 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2651 int num_components = instr->num_components;
2652
2653 if (ctx->abi->load_ubo)
2654 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2655
2656 if (instr->dest.ssa.bit_size == 64)
2657 num_components *= 2;
2658
2659 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2660 NULL, 0, false, false, true, true);
2661 ret = trim_vector(&ctx->ac, ret, num_components);
2662 return LLVMBuildBitCast(ctx->ac.builder, ret,
2663 get_def_type(ctx, &instr->dest.ssa), "");
2664 }
2665
2666 static void
2667 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2668 bool vs_in, unsigned *vertex_index_out,
2669 LLVMValueRef *vertex_index_ref,
2670 unsigned *const_out, LLVMValueRef *indir_out)
2671 {
2672 unsigned const_offset = 0;
2673 nir_deref *tail = &deref->deref;
2674 LLVMValueRef offset = NULL;
2675
2676 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2677 tail = tail->child;
2678 nir_deref_array *deref_array = nir_deref_as_array(tail);
2679 if (vertex_index_out)
2680 *vertex_index_out = deref_array->base_offset;
2681
2682 if (vertex_index_ref) {
2683 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2684 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2685 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2686 }
2687 *vertex_index_ref = vtx;
2688 }
2689 }
2690
2691 if (deref->var->data.compact) {
2692 assert(tail->child->deref_type == nir_deref_type_array);
2693 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2694 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2695 /* We always lower indirect dereferences for "compact" array vars. */
2696 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2697
2698 const_offset = deref_array->base_offset;
2699 goto out;
2700 }
2701
2702 while (tail->child != NULL) {
2703 const struct glsl_type *parent_type = tail->type;
2704 tail = tail->child;
2705
2706 if (tail->deref_type == nir_deref_type_array) {
2707 nir_deref_array *deref_array = nir_deref_as_array(tail);
2708 LLVMValueRef index, stride, local_offset;
2709 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2710
2711 const_offset += size * deref_array->base_offset;
2712 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2713 continue;
2714
2715 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2716 index = get_src(ctx, deref_array->indirect);
2717 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2718 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2719
2720 if (offset)
2721 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2722 else
2723 offset = local_offset;
2724 } else if (tail->deref_type == nir_deref_type_struct) {
2725 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2726
2727 for (unsigned i = 0; i < deref_struct->index; i++) {
2728 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2729 const_offset += glsl_count_attribute_slots(ft, vs_in);
2730 }
2731 } else
2732 unreachable("unsupported deref type");
2733
2734 }
2735 out:
2736 if (const_offset && offset)
2737 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2738 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2739 "");
2740
2741 *const_out = const_offset;
2742 *indir_out = offset;
2743 }
2744
2745
2746 /* The offchip buffer layout for TCS->TES is
2747 *
2748 * - attribute 0 of patch 0 vertex 0
2749 * - attribute 0 of patch 0 vertex 1
2750 * - attribute 0 of patch 0 vertex 2
2751 * ...
2752 * - attribute 0 of patch 1 vertex 0
2753 * - attribute 0 of patch 1 vertex 1
2754 * ...
2755 * - attribute 1 of patch 0 vertex 0
2756 * - attribute 1 of patch 0 vertex 1
2757 * ...
2758 * - per patch attribute 0 of patch 0
2759 * - per patch attribute 0 of patch 1
2760 * ...
2761 *
2762 * Note that every attribute has 4 components.
2763 */
2764 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2765 LLVMValueRef vertex_index,
2766 LLVMValueRef param_index)
2767 {
2768 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2769 LLVMValueRef param_stride, constant16;
2770 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2771
2772 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2773 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2774 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2775 num_patches, "");
2776
2777 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2778 if (vertex_index) {
2779 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2780 vertices_per_patch, "");
2781
2782 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2783 vertex_index, "");
2784
2785 param_stride = total_vertices;
2786 } else {
2787 base_addr = rel_patch_id;
2788 param_stride = num_patches;
2789 }
2790
2791 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2792 LLVMBuildMul(ctx->builder, param_index,
2793 param_stride, ""), "");
2794
2795 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2796
2797 if (!vertex_index) {
2798 LLVMValueRef patch_data_offset =
2799 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2800
2801 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2802 patch_data_offset, "");
2803 }
2804 return base_addr;
2805 }
2806
2807 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2808 unsigned param,
2809 unsigned const_index,
2810 bool is_compact,
2811 LLVMValueRef vertex_index,
2812 LLVMValueRef indir_index)
2813 {
2814 LLVMValueRef param_index;
2815
2816 if (indir_index)
2817 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2818 indir_index, "");
2819 else {
2820 if (const_index && !is_compact)
2821 param += const_index;
2822 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2823 }
2824 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2825 }
2826
2827 static void
2828 mark_tess_output(struct nir_to_llvm_context *ctx,
2829 bool is_patch, uint32_t param)
2830
2831 {
2832 if (is_patch) {
2833 ctx->tess_patch_outputs_written |= (1ull << param);
2834 } else
2835 ctx->tess_outputs_written |= (1ull << param);
2836 }
2837
2838 static LLVMValueRef
2839 get_dw_address(struct nir_to_llvm_context *ctx,
2840 LLVMValueRef dw_addr,
2841 unsigned param,
2842 unsigned const_index,
2843 bool compact_const_index,
2844 LLVMValueRef vertex_index,
2845 LLVMValueRef stride,
2846 LLVMValueRef indir_index)
2847
2848 {
2849
2850 if (vertex_index) {
2851 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2852 LLVMBuildMul(ctx->builder,
2853 vertex_index,
2854 stride, ""), "");
2855 }
2856
2857 if (indir_index)
2858 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2859 LLVMBuildMul(ctx->builder, indir_index,
2860 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2861 else if (const_index && !compact_const_index)
2862 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2863 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2864
2865 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2866 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2867
2868 if (const_index && compact_const_index)
2869 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2870 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2871 return dw_addr;
2872 }
2873
2874 static LLVMValueRef
2875 load_tcs_varyings(struct ac_shader_abi *abi,
2876 LLVMValueRef vertex_index,
2877 LLVMValueRef indir_index,
2878 unsigned const_index,
2879 unsigned location,
2880 unsigned driver_location,
2881 unsigned component,
2882 unsigned num_components,
2883 bool is_patch,
2884 bool is_compact,
2885 bool load_input)
2886 {
2887 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2888 LLVMValueRef dw_addr, stride;
2889 LLVMValueRef value[4], result;
2890 unsigned param = shader_io_get_unique_index(location);
2891
2892 if (load_input) {
2893 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2894 dw_addr = get_tcs_in_current_patch_offset(ctx);
2895 } else {
2896 if (!is_patch) {
2897 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2898 dw_addr = get_tcs_out_current_patch_offset(ctx);
2899 } else {
2900 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2901 stride = NULL;
2902 }
2903 }
2904
2905 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2906 indir_index);
2907
2908 for (unsigned i = 0; i < num_components + component; i++) {
2909 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2910 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2911 ctx->ac.i32_1, "");
2912 }
2913 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2914 return result;
2915 }
2916
2917 static void
2918 store_tcs_output(struct ac_shader_abi *abi,
2919 LLVMValueRef vertex_index,
2920 LLVMValueRef param_index,
2921 unsigned const_index,
2922 unsigned location,
2923 unsigned driver_location,
2924 LLVMValueRef src,
2925 unsigned component,
2926 bool is_patch,
2927 bool is_compact,
2928 unsigned writemask)
2929 {
2930 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2931 LLVMValueRef dw_addr;
2932 LLVMValueRef stride = NULL;
2933 LLVMValueRef buf_addr = NULL;
2934 unsigned param;
2935 bool store_lds = true;
2936
2937 if (is_patch) {
2938 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2939 store_lds = false;
2940 } else {
2941 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2942 store_lds = false;
2943 }
2944
2945 param = shader_io_get_unique_index(location);
2946 if (location == VARYING_SLOT_CLIP_DIST0 &&
2947 is_compact && const_index > 3) {
2948 const_index -= 3;
2949 param++;
2950 }
2951
2952 if (!is_patch) {
2953 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2954 dw_addr = get_tcs_out_current_patch_offset(ctx);
2955 } else {
2956 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2957 }
2958
2959 mark_tess_output(ctx, is_patch, param);
2960
2961 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2962 param_index);
2963 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2964 vertex_index, param_index);
2965
2966 bool is_tess_factor = false;
2967 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2968 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2969 is_tess_factor = true;
2970
2971 unsigned base = is_compact ? const_index : 0;
2972 for (unsigned chan = 0; chan < 8; chan++) {
2973 if (!(writemask & (1 << chan)))
2974 continue;
2975 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2976
2977 if (store_lds || is_tess_factor) {
2978 LLVMValueRef dw_addr_chan =
2979 LLVMBuildAdd(ctx->builder, dw_addr,
2980 LLVMConstInt(ctx->ac.i32, chan, false), "");
2981 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2982 }
2983
2984 if (!is_tess_factor && writemask != 0xF)
2985 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2986 buf_addr, ctx->oc_lds,
2987 4 * (base + chan), 1, 0, true, false);
2988 }
2989
2990 if (writemask == 0xF) {
2991 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2992 buf_addr, ctx->oc_lds,
2993 (base * 4), 1, 0, true, false);
2994 }
2995 }
2996
2997 static LLVMValueRef
2998 load_tes_input(struct ac_shader_abi *abi,
2999 LLVMValueRef vertex_index,
3000 LLVMValueRef param_index,
3001 unsigned const_index,
3002 unsigned location,
3003 unsigned driver_location,
3004 unsigned component,
3005 unsigned num_components,
3006 bool is_patch,
3007 bool is_compact,
3008 bool load_input)
3009 {
3010 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3011 LLVMValueRef buf_addr;
3012 LLVMValueRef result;
3013 unsigned param = shader_io_get_unique_index(location);
3014
3015 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3016 const_index -= 3;
3017 param++;
3018 }
3019
3020 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3021 is_compact, vertex_index, param_index);
3022
3023 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3024 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
3025
3026 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3027 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3028 result = trim_vector(&ctx->ac, result, num_components);
3029 return result;
3030 }
3031
3032 static LLVMValueRef
3033 load_gs_input(struct ac_shader_abi *abi,
3034 unsigned location,
3035 unsigned driver_location,
3036 unsigned component,
3037 unsigned num_components,
3038 unsigned vertex_index,
3039 unsigned const_index,
3040 LLVMTypeRef type)
3041 {
3042 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3043 LLVMValueRef vtx_offset;
3044 unsigned param, vtx_offset_param;
3045 LLVMValueRef value[4], result;
3046
3047 vtx_offset_param = vertex_index;
3048 assert(vtx_offset_param < 6);
3049 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
3050 LLVMConstInt(ctx->ac.i32, 4, false), "");
3051
3052 param = shader_io_get_unique_index(location);
3053
3054 for (unsigned i = component; i < num_components + component; i++) {
3055 if (ctx->ac.chip_class >= GFX9) {
3056 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3057 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3058 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3059 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3060 } else {
3061 LLVMValueRef soffset =
3062 LLVMConstInt(ctx->ac.i32,
3063 (param * 4 + i + const_index) * 256,
3064 false);
3065
3066 value[i] = ac_build_buffer_load(&ctx->ac,
3067 ctx->esgs_ring, 1,
3068 ctx->ac.i32_0,
3069 vtx_offset, soffset,
3070 0, 1, 0, true, false);
3071
3072 value[i] = LLVMBuildBitCast(ctx->builder, value[i],
3073 type, "");
3074 }
3075 }
3076 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3077 result = ac_to_integer(&ctx->ac, result);
3078 return result;
3079 }
3080
3081 static LLVMValueRef
3082 build_gep_for_deref(struct ac_nir_context *ctx,
3083 nir_deref_var *deref)
3084 {
3085 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3086 assert(entry->data);
3087 LLVMValueRef val = entry->data;
3088 nir_deref *tail = deref->deref.child;
3089 while (tail != NULL) {
3090 LLVMValueRef offset;
3091 switch (tail->deref_type) {
3092 case nir_deref_type_array: {
3093 nir_deref_array *array = nir_deref_as_array(tail);
3094 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3095 if (array->deref_array_type ==
3096 nir_deref_array_type_indirect) {
3097 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3098 get_src(ctx,
3099 array->indirect),
3100 "");
3101 }
3102 break;
3103 }
3104 case nir_deref_type_struct: {
3105 nir_deref_struct *deref_struct =
3106 nir_deref_as_struct(tail);
3107 offset = LLVMConstInt(ctx->ac.i32,
3108 deref_struct->index, 0);
3109 break;
3110 }
3111 default:
3112 unreachable("bad deref type");
3113 }
3114 val = ac_build_gep0(&ctx->ac, val, offset);
3115 tail = tail->child;
3116 }
3117 return val;
3118 }
3119
3120 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3121 nir_intrinsic_instr *instr,
3122 bool load_inputs)
3123 {
3124 LLVMValueRef result;
3125 LLVMValueRef vertex_index = NULL;
3126 LLVMValueRef indir_index = NULL;
3127 unsigned const_index = 0;
3128 unsigned location = instr->variables[0]->var->data.location;
3129 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3130 const bool is_patch = instr->variables[0]->var->data.patch;
3131 const bool is_compact = instr->variables[0]->var->data.compact;
3132
3133 get_deref_offset(ctx, instr->variables[0],
3134 false, NULL, is_patch ? NULL : &vertex_index,
3135 &const_index, &indir_index);
3136
3137 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3138 const_index, location, driver_location,
3139 instr->variables[0]->var->data.location_frac,
3140 instr->num_components,
3141 is_patch, is_compact, load_inputs);
3142 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3143 }
3144
3145 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3146 nir_intrinsic_instr *instr)
3147 {
3148 LLVMValueRef values[8];
3149 int idx = instr->variables[0]->var->data.driver_location;
3150 int ve = instr->dest.ssa.num_components;
3151 unsigned comp = instr->variables[0]->var->data.location_frac;
3152 LLVMValueRef indir_index;
3153 LLVMValueRef ret;
3154 unsigned const_index;
3155 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3156 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3157 instr->variables[0]->var->data.mode == nir_var_shader_in;
3158 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3159 &const_index, &indir_index);
3160
3161 if (instr->dest.ssa.bit_size == 64)
3162 ve *= 2;
3163
3164 switch (instr->variables[0]->var->data.mode) {
3165 case nir_var_shader_in:
3166 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3167 ctx->stage == MESA_SHADER_TESS_EVAL) {
3168 return load_tess_varyings(ctx, instr, true);
3169 }
3170
3171 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3172 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3173 LLVMValueRef indir_index;
3174 unsigned const_index, vertex_index;
3175 get_deref_offset(ctx, instr->variables[0],
3176 false, &vertex_index, NULL,
3177 &const_index, &indir_index);
3178
3179 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3180 instr->variables[0]->var->data.driver_location,
3181 instr->variables[0]->var->data.location_frac, ve,
3182 vertex_index, const_index, type);
3183 }
3184
3185 for (unsigned chan = comp; chan < ve + comp; chan++) {
3186 if (indir_index) {
3187 unsigned count = glsl_count_attribute_slots(
3188 instr->variables[0]->var->type,
3189 ctx->stage == MESA_SHADER_VERTEX);
3190 count -= chan / 4;
3191 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3192 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3193 stride, false, true);
3194
3195 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3196 tmp_vec,
3197 indir_index, "");
3198 } else
3199 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3200 }
3201 break;
3202 case nir_var_local:
3203 for (unsigned chan = 0; chan < ve; chan++) {
3204 if (indir_index) {
3205 unsigned count = glsl_count_attribute_slots(
3206 instr->variables[0]->var->type, false);
3207 count -= chan / 4;
3208 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3209 &ctx->ac, ctx->locals + idx + chan, count,
3210 stride, true, true);
3211
3212 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3213 tmp_vec,
3214 indir_index, "");
3215 } else {
3216 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3217 }
3218 }
3219 break;
3220 case nir_var_shared: {
3221 LLVMValueRef address = build_gep_for_deref(ctx,
3222 instr->variables[0]);
3223 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3224 return LLVMBuildBitCast(ctx->ac.builder, val,
3225 get_def_type(ctx, &instr->dest.ssa),
3226 "");
3227 }
3228 case nir_var_shader_out:
3229 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3230 return load_tess_varyings(ctx, instr, false);
3231 }
3232
3233 for (unsigned chan = comp; chan < ve + comp; chan++) {
3234 if (indir_index) {
3235 unsigned count = glsl_count_attribute_slots(
3236 instr->variables[0]->var->type, false);
3237 count -= chan / 4;
3238 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3239 &ctx->ac, ctx->outputs + idx + chan, count,
3240 stride, true, true);
3241
3242 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3243 tmp_vec,
3244 indir_index, "");
3245 } else {
3246 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3247 ctx->outputs[idx + chan + const_index * stride],
3248 "");
3249 }
3250 }
3251 break;
3252 default:
3253 unreachable("unhandle variable mode");
3254 }
3255 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3256 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3257 }
3258
3259 static void
3260 visit_store_var(struct ac_nir_context *ctx,
3261 nir_intrinsic_instr *instr)
3262 {
3263 LLVMValueRef temp_ptr, value;
3264 int idx = instr->variables[0]->var->data.driver_location;
3265 unsigned comp = instr->variables[0]->var->data.location_frac;
3266 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3267 int writemask = instr->const_index[0] << comp;
3268 LLVMValueRef indir_index;
3269 unsigned const_index;
3270 get_deref_offset(ctx, instr->variables[0], false,
3271 NULL, NULL, &const_index, &indir_index);
3272
3273 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3274
3275 src = LLVMBuildBitCast(ctx->ac.builder, src,
3276 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3277 "");
3278
3279 writemask = widen_mask(writemask, 2);
3280 }
3281
3282 switch (instr->variables[0]->var->data.mode) {
3283 case nir_var_shader_out:
3284
3285 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3286 LLVMValueRef vertex_index = NULL;
3287 LLVMValueRef indir_index = NULL;
3288 unsigned const_index = 0;
3289 const unsigned location = instr->variables[0]->var->data.location;
3290 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3291 const unsigned comp = instr->variables[0]->var->data.location_frac;
3292 const bool is_patch = instr->variables[0]->var->data.patch;
3293 const bool is_compact = instr->variables[0]->var->data.compact;
3294
3295 get_deref_offset(ctx, instr->variables[0],
3296 false, NULL, is_patch ? NULL : &vertex_index,
3297 &const_index, &indir_index);
3298
3299 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3300 const_index, location, driver_location,
3301 src, comp, is_patch, is_compact, writemask);
3302 return;
3303 }
3304
3305 for (unsigned chan = 0; chan < 8; chan++) {
3306 int stride = 4;
3307 if (!(writemask & (1 << chan)))
3308 continue;
3309
3310 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3311
3312 if (instr->variables[0]->var->data.compact)
3313 stride = 1;
3314 if (indir_index) {
3315 unsigned count = glsl_count_attribute_slots(
3316 instr->variables[0]->var->type, false);
3317 count -= chan / 4;
3318 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3319 &ctx->ac, ctx->outputs + idx + chan, count,
3320 stride, true, true);
3321
3322 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3323 value, indir_index, "");
3324 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3325 count, stride, tmp_vec);
3326
3327 } else {
3328 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3329
3330 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3331 }
3332 }
3333 break;
3334 case nir_var_local:
3335 for (unsigned chan = 0; chan < 8; chan++) {
3336 if (!(writemask & (1 << chan)))
3337 continue;
3338
3339 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3340 if (indir_index) {
3341 unsigned count = glsl_count_attribute_slots(
3342 instr->variables[0]->var->type, false);
3343 count -= chan / 4;
3344 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3345 &ctx->ac, ctx->locals + idx + chan, count,
3346 4, true, true);
3347
3348 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3349 value, indir_index, "");
3350 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3351 count, 4, tmp_vec);
3352 } else {
3353 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3354
3355 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3356 }
3357 }
3358 break;
3359 case nir_var_shared: {
3360 int writemask = instr->const_index[0];
3361 LLVMValueRef address = build_gep_for_deref(ctx,
3362 instr->variables[0]);
3363 LLVMValueRef val = get_src(ctx, instr->src[0]);
3364 unsigned components =
3365 glsl_get_vector_elements(
3366 nir_deref_tail(&instr->variables[0]->deref)->type);
3367 if (writemask == (1 << components) - 1) {
3368 val = LLVMBuildBitCast(
3369 ctx->ac.builder, val,
3370 LLVMGetElementType(LLVMTypeOf(address)), "");
3371 LLVMBuildStore(ctx->ac.builder, val, address);
3372 } else {
3373 for (unsigned chan = 0; chan < 4; chan++) {
3374 if (!(writemask & (1 << chan)))
3375 continue;
3376 LLVMValueRef ptr =
3377 LLVMBuildStructGEP(ctx->ac.builder,
3378 address, chan, "");
3379 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3380 chan);
3381 src = LLVMBuildBitCast(
3382 ctx->ac.builder, src,
3383 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3384 LLVMBuildStore(ctx->ac.builder, src, ptr);
3385 }
3386 }
3387 break;
3388 }
3389 default:
3390 break;
3391 }
3392 }
3393
3394 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3395 {
3396 switch (dim) {
3397 case GLSL_SAMPLER_DIM_BUF:
3398 return 1;
3399 case GLSL_SAMPLER_DIM_1D:
3400 return array ? 2 : 1;
3401 case GLSL_SAMPLER_DIM_2D:
3402 return array ? 3 : 2;
3403 case GLSL_SAMPLER_DIM_MS:
3404 return array ? 4 : 3;
3405 case GLSL_SAMPLER_DIM_3D:
3406 case GLSL_SAMPLER_DIM_CUBE:
3407 return 3;
3408 case GLSL_SAMPLER_DIM_RECT:
3409 case GLSL_SAMPLER_DIM_SUBPASS:
3410 return 2;
3411 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3412 return 3;
3413 default:
3414 break;
3415 }
3416 return 0;
3417 }
3418
3419
3420
3421 /* Adjust the sample index according to FMASK.
3422 *
3423 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3424 * which is the identity mapping. Each nibble says which physical sample
3425 * should be fetched to get that sample.
3426 *
3427 * For example, 0x11111100 means there are only 2 samples stored and
3428 * the second sample covers 3/4 of the pixel. When reading samples 0
3429 * and 1, return physical sample 0 (determined by the first two 0s
3430 * in FMASK), otherwise return physical sample 1.
3431 *
3432 * The sample index should be adjusted as follows:
3433 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3434 */
3435 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3436 LLVMValueRef coord_x, LLVMValueRef coord_y,
3437 LLVMValueRef coord_z,
3438 LLVMValueRef sample_index,
3439 LLVMValueRef fmask_desc_ptr)
3440 {
3441 LLVMValueRef fmask_load_address[4];
3442 LLVMValueRef res;
3443
3444 fmask_load_address[0] = coord_x;
3445 fmask_load_address[1] = coord_y;
3446 if (coord_z) {
3447 fmask_load_address[2] = coord_z;
3448 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3449 }
3450
3451 struct ac_image_args args = {0};
3452
3453 args.opcode = ac_image_load;
3454 args.da = coord_z ? true : false;
3455 args.resource = fmask_desc_ptr;
3456 args.dmask = 0xf;
3457 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3458
3459 res = ac_build_image_opcode(ctx, &args);
3460
3461 res = ac_to_integer(ctx, res);
3462 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3463 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3464
3465 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3466 res,
3467 ctx->i32_0, "");
3468
3469 LLVMValueRef sample_index4 =
3470 LLVMBuildMul(ctx->builder, sample_index, four, "");
3471 LLVMValueRef shifted_fmask =
3472 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3473 LLVMValueRef final_sample =
3474 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3475
3476 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3477 * resource descriptor is 0 (invalid),
3478 */
3479 LLVMValueRef fmask_desc =
3480 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3481 ctx->v8i32, "");
3482
3483 LLVMValueRef fmask_word1 =
3484 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3485 ctx->i32_1, "");
3486
3487 LLVMValueRef word1_is_nonzero =
3488 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3489 fmask_word1, ctx->i32_0, "");
3490
3491 /* Replace the MSAA sample index. */
3492 sample_index =
3493 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3494 final_sample, sample_index, "");
3495 return sample_index;
3496 }
3497
3498 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3499 const nir_intrinsic_instr *instr)
3500 {
3501 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3502
3503 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3504 LLVMValueRef coords[4];
3505 LLVMValueRef masks[] = {
3506 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3507 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3508 };
3509 LLVMValueRef res;
3510 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3511
3512 int count;
3513 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3514 bool is_array = glsl_sampler_type_is_array(type);
3515 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3516 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3517 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3518 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3519 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3520 count = image_type_to_components_count(dim, is_array);
3521
3522 if (is_ms) {
3523 LLVMValueRef fmask_load_address[3];
3524 int chan;
3525
3526 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3527 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3528 if (is_array)
3529 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3530 else
3531 fmask_load_address[2] = NULL;
3532 if (add_frag_pos) {
3533 for (chan = 0; chan < 2; ++chan)
3534 fmask_load_address[chan] =
3535 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3536 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3537 ctx->ac.i32, ""), "");
3538 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3539 }
3540 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3541 fmask_load_address[0],
3542 fmask_load_address[1],
3543 fmask_load_address[2],
3544 sample_index,
3545 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3546 }
3547 if (count == 1 && !gfx9_1d) {
3548 if (instr->src[0].ssa->num_components)
3549 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3550 else
3551 res = src0;
3552 } else {
3553 int chan;
3554 if (is_ms)
3555 count--;
3556 for (chan = 0; chan < count; ++chan) {
3557 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3558 }
3559 if (add_frag_pos) {
3560 for (chan = 0; chan < 2; ++chan)
3561 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3562 ctx->ac.i32, ""), "");
3563 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3564 count++;
3565 }
3566
3567 if (gfx9_1d) {
3568 if (is_array) {
3569 coords[2] = coords[1];
3570 coords[1] = ctx->ac.i32_0;
3571 } else
3572 coords[1] = ctx->ac.i32_0;
3573 count++;
3574 }
3575
3576 if (is_ms) {
3577 coords[count] = sample_index;
3578 count++;
3579 }
3580
3581 if (count == 3) {
3582 coords[3] = LLVMGetUndef(ctx->ac.i32);
3583 count = 4;
3584 }
3585 res = ac_build_gather_values(&ctx->ac, coords, count);
3586 }
3587 return res;
3588 }
3589
3590 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3591 const nir_intrinsic_instr *instr)
3592 {
3593 LLVMValueRef params[7];
3594 LLVMValueRef res;
3595 char intrinsic_name[64];
3596 const nir_variable *var = instr->variables[0]->var;
3597 const struct glsl_type *type = var->type;
3598
3599 if(instr->variables[0]->deref.child)
3600 type = instr->variables[0]->deref.child->type;
3601
3602 type = glsl_without_array(type);
3603
3604 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3605 if (dim == GLSL_SAMPLER_DIM_BUF) {
3606 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3607 unsigned num_channels = util_last_bit(mask);
3608 LLVMValueRef rsrc, vindex;
3609
3610 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3611 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3612 ctx->ac.i32_0, "");
3613
3614 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3615 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3616 ctx->ac.i32_0, num_channels,
3617 false, false);
3618 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3619
3620 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3621 res = ac_to_integer(&ctx->ac, res);
3622 } else {
3623 bool is_da = glsl_sampler_type_is_array(type) ||
3624 dim == GLSL_SAMPLER_DIM_CUBE ||
3625 dim == GLSL_SAMPLER_DIM_3D ||
3626 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3627 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3628 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3629 LLVMValueRef glc = ctx->ac.i1false;
3630 LLVMValueRef slc = ctx->ac.i1false;
3631
3632 params[0] = get_image_coords(ctx, instr);
3633 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3634 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3635 params[3] = glc;
3636 params[4] = slc;
3637 params[5] = ctx->ac.i1false;
3638 params[6] = da;
3639
3640 ac_get_image_intr_name("llvm.amdgcn.image.load",
3641 ctx->ac.v4f32, /* vdata */
3642 LLVMTypeOf(params[0]), /* coords */
3643 LLVMTypeOf(params[1]), /* rsrc */
3644 intrinsic_name, sizeof(intrinsic_name));
3645
3646 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3647 params, 7, AC_FUNC_ATTR_READONLY);
3648 }
3649 return ac_to_integer(&ctx->ac, res);
3650 }
3651
3652 static void visit_image_store(struct ac_nir_context *ctx,
3653 nir_intrinsic_instr *instr)
3654 {
3655 LLVMValueRef params[8];
3656 char intrinsic_name[64];
3657 const nir_variable *var = instr->variables[0]->var;
3658 const struct glsl_type *type = glsl_without_array(var->type);
3659 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3660 LLVMValueRef glc = ctx->ac.i1false;
3661 bool force_glc = ctx->ac.chip_class == SI;
3662 if (force_glc)
3663 glc = ctx->ac.i1true;
3664
3665 if (dim == GLSL_SAMPLER_DIM_BUF) {
3666 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3667 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3668 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3669 ctx->ac.i32_0, ""); /* vindex */
3670 params[3] = ctx->ac.i32_0; /* voffset */
3671 params[4] = glc; /* glc */
3672 params[5] = ctx->ac.i1false; /* slc */
3673 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3674 params, 6, 0);
3675 } else {
3676 bool is_da = glsl_sampler_type_is_array(type) ||
3677 dim == GLSL_SAMPLER_DIM_CUBE ||
3678 dim == GLSL_SAMPLER_DIM_3D;
3679 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3680 LLVMValueRef slc = ctx->ac.i1false;
3681
3682 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3683 params[1] = get_image_coords(ctx, instr); /* coords */
3684 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3685 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3686 params[4] = glc;
3687 params[5] = slc;
3688 params[6] = ctx->ac.i1false;
3689 params[7] = da;
3690
3691 ac_get_image_intr_name("llvm.amdgcn.image.store",
3692 LLVMTypeOf(params[0]), /* vdata */
3693 LLVMTypeOf(params[1]), /* coords */
3694 LLVMTypeOf(params[2]), /* rsrc */
3695 intrinsic_name, sizeof(intrinsic_name));
3696
3697 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3698 params, 8, 0);
3699 }
3700
3701 }
3702
3703 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3704 const nir_intrinsic_instr *instr)
3705 {
3706 LLVMValueRef params[7];
3707 int param_count = 0;
3708 const nir_variable *var = instr->variables[0]->var;
3709
3710 const char *atomic_name;
3711 char intrinsic_name[41];
3712 const struct glsl_type *type = glsl_without_array(var->type);
3713 MAYBE_UNUSED int length;
3714
3715 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3716
3717 switch (instr->intrinsic) {
3718 case nir_intrinsic_image_atomic_add:
3719 atomic_name = "add";
3720 break;
3721 case nir_intrinsic_image_atomic_min:
3722 atomic_name = is_unsigned ? "umin" : "smin";
3723 break;
3724 case nir_intrinsic_image_atomic_max:
3725 atomic_name = is_unsigned ? "umax" : "smax";
3726 break;
3727 case nir_intrinsic_image_atomic_and:
3728 atomic_name = "and";
3729 break;
3730 case nir_intrinsic_image_atomic_or:
3731 atomic_name = "or";
3732 break;
3733 case nir_intrinsic_image_atomic_xor:
3734 atomic_name = "xor";
3735 break;
3736 case nir_intrinsic_image_atomic_exchange:
3737 atomic_name = "swap";
3738 break;
3739 case nir_intrinsic_image_atomic_comp_swap:
3740 atomic_name = "cmpswap";
3741 break;
3742 default:
3743 abort();
3744 }
3745
3746 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3747 params[param_count++] = get_src(ctx, instr->src[3]);
3748 params[param_count++] = get_src(ctx, instr->src[2]);
3749
3750 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3751 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3752 NULL, true, true);
3753 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3754 ctx->ac.i32_0, ""); /* vindex */
3755 params[param_count++] = ctx->ac.i32_0; /* voffset */
3756 params[param_count++] = ctx->ac.i1false; /* slc */
3757
3758 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3759 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3760 } else {
3761 char coords_type[8];
3762
3763 bool da = glsl_sampler_type_is_array(type) ||
3764 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3765
3766 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3767 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3768 NULL, true, true);
3769 params[param_count++] = ctx->ac.i1false; /* r128 */
3770 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3771 params[param_count++] = ctx->ac.i1false; /* slc */
3772
3773 build_int_type_name(LLVMTypeOf(coords),
3774 coords_type, sizeof(coords_type));
3775
3776 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3777 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3778 }
3779
3780 assert(length < sizeof(intrinsic_name));
3781 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3782 }
3783
3784 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3785 const nir_intrinsic_instr *instr)
3786 {
3787 LLVMValueRef res;
3788 const nir_variable *var = instr->variables[0]->var;
3789 const struct glsl_type *type = instr->variables[0]->var->type;
3790 bool da = glsl_sampler_type_is_array(var->type) ||
3791 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3792 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3793 if(instr->variables[0]->deref.child)
3794 type = instr->variables[0]->deref.child->type;
3795
3796 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3797 return get_buffer_size(ctx,
3798 get_sampler_desc(ctx, instr->variables[0],
3799 AC_DESC_BUFFER, NULL, true, false), true);
3800
3801 struct ac_image_args args = { 0 };
3802
3803 args.da = da;
3804 args.dmask = 0xf;
3805 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3806 args.opcode = ac_image_get_resinfo;
3807 args.addr = ctx->ac.i32_0;
3808
3809 res = ac_build_image_opcode(&ctx->ac, &args);
3810
3811 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3812
3813 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3814 glsl_sampler_type_is_array(type)) {
3815 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3816 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3817 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3818 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3819 }
3820 if (ctx->ac.chip_class >= GFX9 &&
3821 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3822 glsl_sampler_type_is_array(type)) {
3823 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3824 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3825 ctx->ac.i32_1, "");
3826
3827 }
3828 return res;
3829 }
3830
3831 #define NOOP_WAITCNT 0xf7f
3832 #define LGKM_CNT 0x07f
3833 #define VM_CNT 0xf70
3834
3835 static void emit_membar(struct ac_llvm_context *ac,
3836 const nir_intrinsic_instr *instr)
3837 {
3838 unsigned waitcnt = NOOP_WAITCNT;
3839
3840 switch (instr->intrinsic) {
3841 case nir_intrinsic_memory_barrier:
3842 case nir_intrinsic_group_memory_barrier:
3843 waitcnt &= VM_CNT & LGKM_CNT;
3844 break;
3845 case nir_intrinsic_memory_barrier_atomic_counter:
3846 case nir_intrinsic_memory_barrier_buffer:
3847 case nir_intrinsic_memory_barrier_image:
3848 waitcnt &= VM_CNT;
3849 break;
3850 case nir_intrinsic_memory_barrier_shared:
3851 waitcnt &= LGKM_CNT;
3852 break;
3853 default:
3854 break;
3855 }
3856 if (waitcnt != NOOP_WAITCNT)
3857 ac_build_waitcnt(ac, waitcnt);
3858 }
3859
3860 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3861 {
3862 /* SI only (thanks to a hw bug workaround):
3863 * The real barrier instruction isn’t needed, because an entire patch
3864 * always fits into a single wave.
3865 */
3866 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3867 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3868 return;
3869 }
3870 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3871 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3872 }
3873
3874 static void emit_discard(struct ac_nir_context *ctx,
3875 const nir_intrinsic_instr *instr)
3876 {
3877 LLVMValueRef cond;
3878
3879 if (instr->intrinsic == nir_intrinsic_discard_if) {
3880 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3881 get_src(ctx, instr->src[0]),
3882 ctx->ac.i32_0, "");
3883 } else {
3884 assert(instr->intrinsic == nir_intrinsic_discard);
3885 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3886 }
3887
3888 ac_build_kill_if_false(&ctx->ac, cond);
3889 }
3890
3891 static LLVMValueRef
3892 visit_load_helper_invocation(struct ac_nir_context *ctx)
3893 {
3894 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3895 "llvm.amdgcn.ps.live",
3896 ctx->ac.i1, NULL, 0,
3897 AC_FUNC_ATTR_READNONE);
3898 result = LLVMBuildNot(ctx->ac.builder, result, "");
3899 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3900 }
3901
3902 static LLVMValueRef
3903 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3904 {
3905 LLVMValueRef result;
3906 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3907 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3908 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3909
3910 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3911 }
3912
3913 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3914 const nir_intrinsic_instr *instr)
3915 {
3916 LLVMValueRef ptr, result;
3917 LLVMValueRef src = get_src(ctx, instr->src[0]);
3918 ptr = build_gep_for_deref(ctx, instr->variables[0]);
3919
3920 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3921 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3922 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3923 ptr, src, src1,
3924 LLVMAtomicOrderingSequentiallyConsistent,
3925 LLVMAtomicOrderingSequentiallyConsistent,
3926 false);
3927 } else {
3928 LLVMAtomicRMWBinOp op;
3929 switch (instr->intrinsic) {
3930 case nir_intrinsic_var_atomic_add:
3931 op = LLVMAtomicRMWBinOpAdd;
3932 break;
3933 case nir_intrinsic_var_atomic_umin:
3934 op = LLVMAtomicRMWBinOpUMin;
3935 break;
3936 case nir_intrinsic_var_atomic_umax:
3937 op = LLVMAtomicRMWBinOpUMax;
3938 break;
3939 case nir_intrinsic_var_atomic_imin:
3940 op = LLVMAtomicRMWBinOpMin;
3941 break;
3942 case nir_intrinsic_var_atomic_imax:
3943 op = LLVMAtomicRMWBinOpMax;
3944 break;
3945 case nir_intrinsic_var_atomic_and:
3946 op = LLVMAtomicRMWBinOpAnd;
3947 break;
3948 case nir_intrinsic_var_atomic_or:
3949 op = LLVMAtomicRMWBinOpOr;
3950 break;
3951 case nir_intrinsic_var_atomic_xor:
3952 op = LLVMAtomicRMWBinOpXor;
3953 break;
3954 case nir_intrinsic_var_atomic_exchange:
3955 op = LLVMAtomicRMWBinOpXchg;
3956 break;
3957 default:
3958 return NULL;
3959 }
3960
3961 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
3962 LLVMAtomicOrderingSequentiallyConsistent,
3963 false);
3964 }
3965 return result;
3966 }
3967
3968 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
3969 enum glsl_interp_mode interp, unsigned location)
3970 {
3971 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3972
3973 switch (interp) {
3974 case INTERP_MODE_FLAT:
3975 default:
3976 return NULL;
3977 case INTERP_MODE_SMOOTH:
3978 case INTERP_MODE_NONE:
3979 if (location == INTERP_CENTER)
3980 return ctx->persp_center;
3981 else if (location == INTERP_CENTROID)
3982 return ctx->persp_centroid;
3983 else if (location == INTERP_SAMPLE)
3984 return ctx->persp_sample;
3985 break;
3986 case INTERP_MODE_NOPERSPECTIVE:
3987 if (location == INTERP_CENTER)
3988 return ctx->linear_center;
3989 else if (location == INTERP_CENTROID)
3990 return ctx->linear_centroid;
3991 else if (location == INTERP_SAMPLE)
3992 return ctx->linear_sample;
3993 break;
3994 }
3995 return NULL;
3996 }
3997
3998 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
3999 LLVMValueRef sample_id)
4000 {
4001 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4002
4003 LLVMValueRef result;
4004 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4005
4006 ptr = LLVMBuildBitCast(ctx->builder, ptr,
4007 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4008
4009 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
4010 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4011
4012 return result;
4013 }
4014
4015 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4016 {
4017 LLVMValueRef values[2];
4018
4019 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4020 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4021 return ac_build_gather_values(&ctx->ac, values, 2);
4022 }
4023
4024 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4025 {
4026 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4027 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4028 ctx->options->key.fs.log2_num_samples :
4029 ctx->options->key.fs.log2_ps_iter_samples;
4030
4031 /* The bit pattern matches that used by fixed function fragment
4032 * processing. */
4033 static const uint16_t ps_iter_masks[] = {
4034 0xffff, /* not used */
4035 0x5555,
4036 0x1111,
4037 0x0101,
4038 0x0001,
4039 };
4040 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4041
4042 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4043
4044 LLVMValueRef result, sample_id;
4045 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4046 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4047 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4048 return result;
4049 }
4050
4051 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4052 const nir_intrinsic_instr *instr)
4053 {
4054 LLVMValueRef result[4];
4055 LLVMValueRef interp_param, attr_number;
4056 unsigned location;
4057 unsigned chan;
4058 LLVMValueRef src_c0 = NULL;
4059 LLVMValueRef src_c1 = NULL;
4060 LLVMValueRef src0 = NULL;
4061 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4062 switch (instr->intrinsic) {
4063 case nir_intrinsic_interp_var_at_centroid:
4064 location = INTERP_CENTROID;
4065 break;
4066 case nir_intrinsic_interp_var_at_sample:
4067 case nir_intrinsic_interp_var_at_offset:
4068 location = INTERP_CENTER;
4069 src0 = get_src(ctx, instr->src[0]);
4070 break;
4071 default:
4072 break;
4073 }
4074
4075 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4076 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4077 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4078 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4079 LLVMValueRef sample_position;
4080 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4081
4082 /* fetch sample ID */
4083 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4084
4085 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4086 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4087 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4088 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4089 }
4090 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4091 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4092
4093 if (location == INTERP_CENTER) {
4094 LLVMValueRef ij_out[2];
4095 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4096
4097 /*
4098 * take the I then J parameters, and the DDX/Y for it, and
4099 * calculate the IJ inputs for the interpolator.
4100 * temp1 = ddx * offset/sample.x + I;
4101 * interp_param.I = ddy * offset/sample.y + temp1;
4102 * temp1 = ddx * offset/sample.x + J;
4103 * interp_param.J = ddy * offset/sample.y + temp1;
4104 */
4105 for (unsigned i = 0; i < 2; i++) {
4106 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4107 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4108 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4109 ddxy_out, ix_ll, "");
4110 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4111 ddxy_out, iy_ll, "");
4112 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4113 interp_param, ix_ll, "");
4114 LLVMValueRef temp1, temp2;
4115
4116 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4117 ctx->ac.f32, "");
4118
4119 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4120 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4121
4122 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4123 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4124
4125 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4126 temp2, ctx->ac.i32, "");
4127 }
4128 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4129
4130 }
4131
4132 for (chan = 0; chan < 4; chan++) {
4133 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4134
4135 if (interp_param) {
4136 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4137 interp_param, ctx->ac.v2f32, "");
4138 LLVMValueRef i = LLVMBuildExtractElement(
4139 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4140 LLVMValueRef j = LLVMBuildExtractElement(
4141 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4142
4143 result[chan] = ac_build_fs_interp(&ctx->ac,
4144 llvm_chan, attr_number,
4145 ctx->abi->prim_mask, i, j);
4146 } else {
4147 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4148 LLVMConstInt(ctx->ac.i32, 2, false),
4149 llvm_chan, attr_number,
4150 ctx->abi->prim_mask);
4151 }
4152 }
4153 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4154 instr->variables[0]->var->data.location_frac);
4155 }
4156
4157 static void
4158 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4159 {
4160 LLVMValueRef gs_next_vertex;
4161 LLVMValueRef can_emit;
4162 int idx;
4163 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4164
4165 assert(stream == 0);
4166
4167 /* Write vertex attribute values to GSVS ring */
4168 gs_next_vertex = LLVMBuildLoad(ctx->builder,
4169 ctx->gs_next_vertex,
4170 "");
4171
4172 /* If this thread has already emitted the declared maximum number of
4173 * vertices, kill it: excessive vertex emissions are not supposed to
4174 * have any effect, and GS threads have no externally observable
4175 * effects other than emitting vertices.
4176 */
4177 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
4178 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4179 ac_build_kill_if_false(&ctx->ac, can_emit);
4180
4181 /* loop num outputs */
4182 idx = 0;
4183 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4184 LLVMValueRef *out_ptr = &addrs[i * 4];
4185 int length = 4;
4186 int slot = idx;
4187 int slot_inc = 1;
4188
4189 if (!(ctx->output_mask & (1ull << i)))
4190 continue;
4191
4192 if (i == VARYING_SLOT_CLIP_DIST0) {
4193 /* pack clip and cull into a single set of slots */
4194 length = ctx->num_output_clips + ctx->num_output_culls;
4195 if (length > 4)
4196 slot_inc = 2;
4197 }
4198 for (unsigned j = 0; j < length; j++) {
4199 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
4200 out_ptr[j], "");
4201 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4202 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
4203 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4204
4205 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
4206
4207 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4208 out_val, 1,
4209 voffset, ctx->gs2vs_offset, 0,
4210 1, 1, true, true);
4211 }
4212 idx += slot_inc;
4213 }
4214
4215 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
4216 ctx->ac.i32_1, "");
4217 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
4218
4219 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4220 }
4221
4222 static void
4223 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4224 {
4225 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4226 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4227 }
4228
4229 static LLVMValueRef
4230 load_tess_coord(struct ac_shader_abi *abi)
4231 {
4232 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4233
4234 LLVMValueRef coord[4] = {
4235 ctx->tes_u,
4236 ctx->tes_v,
4237 ctx->ac.f32_0,
4238 ctx->ac.f32_0,
4239 };
4240
4241 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4242 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4243 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4244
4245 return ac_build_gather_values(&ctx->ac, coord, 3);
4246 }
4247
4248 static LLVMValueRef
4249 load_patch_vertices_in(struct ac_shader_abi *abi)
4250 {
4251 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4252 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4253 }
4254
4255 static void visit_intrinsic(struct ac_nir_context *ctx,
4256 nir_intrinsic_instr *instr)
4257 {
4258 LLVMValueRef result = NULL;
4259
4260 switch (instr->intrinsic) {
4261 case nir_intrinsic_ballot:
4262 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4263 break;
4264 case nir_intrinsic_read_invocation:
4265 case nir_intrinsic_read_first_invocation: {
4266 LLVMValueRef args[2];
4267
4268 /* Value */
4269 args[0] = get_src(ctx, instr->src[0]);
4270
4271 unsigned num_args;
4272 const char *intr_name;
4273 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4274 num_args = 2;
4275 intr_name = "llvm.amdgcn.readlane";
4276
4277 /* Invocation */
4278 args[1] = get_src(ctx, instr->src[1]);
4279 } else {
4280 num_args = 1;
4281 intr_name = "llvm.amdgcn.readfirstlane";
4282 }
4283
4284 /* We currently have no other way to prevent LLVM from lifting the icmp
4285 * calls to a dominating basic block.
4286 */
4287 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4288
4289 result = ac_build_intrinsic(&ctx->ac, intr_name,
4290 ctx->ac.i32, args, num_args,
4291 AC_FUNC_ATTR_READNONE |
4292 AC_FUNC_ATTR_CONVERGENT);
4293 break;
4294 }
4295 case nir_intrinsic_load_subgroup_invocation:
4296 result = ac_get_thread_id(&ctx->ac);
4297 break;
4298 case nir_intrinsic_load_work_group_id: {
4299 LLVMValueRef values[3];
4300
4301 for (int i = 0; i < 3; i++) {
4302 values[i] = ctx->abi->workgroup_ids[i] ?
4303 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4304 }
4305
4306 result = ac_build_gather_values(&ctx->ac, values, 3);
4307 break;
4308 }
4309 case nir_intrinsic_load_base_vertex: {
4310 result = ctx->abi->base_vertex;
4311 break;
4312 }
4313 case nir_intrinsic_load_local_group_size:
4314 result = ctx->abi->load_local_group_size(ctx->abi);
4315 break;
4316 case nir_intrinsic_load_vertex_id_zero_base: {
4317 result = ctx->abi->vertex_id;
4318 break;
4319 }
4320 case nir_intrinsic_load_local_invocation_id: {
4321 result = ctx->abi->local_invocation_ids;
4322 break;
4323 }
4324 case nir_intrinsic_load_base_instance:
4325 result = ctx->abi->start_instance;
4326 break;
4327 case nir_intrinsic_load_draw_id:
4328 result = ctx->abi->draw_id;
4329 break;
4330 case nir_intrinsic_load_view_index:
4331 result = ctx->abi->view_index;
4332 break;
4333 case nir_intrinsic_load_invocation_id:
4334 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4335 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4336 else
4337 result = ctx->abi->gs_invocation_id;
4338 break;
4339 case nir_intrinsic_load_primitive_id:
4340 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4341 result = ctx->abi->gs_prim_id;
4342 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4343 result = ctx->abi->tcs_patch_id;
4344 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4345 result = ctx->abi->tes_patch_id;
4346 } else
4347 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4348 break;
4349 case nir_intrinsic_load_sample_id:
4350 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4351 break;
4352 case nir_intrinsic_load_sample_pos:
4353 result = load_sample_pos(ctx);
4354 break;
4355 case nir_intrinsic_load_sample_mask_in:
4356 result = ctx->abi->load_sample_mask_in(ctx->abi);
4357 break;
4358 case nir_intrinsic_load_frag_coord: {
4359 LLVMValueRef values[4] = {
4360 ctx->abi->frag_pos[0],
4361 ctx->abi->frag_pos[1],
4362 ctx->abi->frag_pos[2],
4363 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4364 };
4365 result = ac_build_gather_values(&ctx->ac, values, 4);
4366 break;
4367 }
4368 case nir_intrinsic_load_front_face:
4369 result = ctx->abi->front_face;
4370 break;
4371 case nir_intrinsic_load_helper_invocation:
4372 result = visit_load_helper_invocation(ctx);
4373 break;
4374 case nir_intrinsic_load_instance_id:
4375 result = ctx->abi->instance_id;
4376 break;
4377 case nir_intrinsic_load_num_work_groups:
4378 result = ctx->abi->num_work_groups;
4379 break;
4380 case nir_intrinsic_load_local_invocation_index:
4381 result = visit_load_local_invocation_index(ctx);
4382 break;
4383 case nir_intrinsic_load_push_constant:
4384 result = visit_load_push_constant(ctx, instr);
4385 break;
4386 case nir_intrinsic_vulkan_resource_index: {
4387 LLVMValueRef index = get_src(ctx, instr->src[0]);
4388 unsigned desc_set = nir_intrinsic_desc_set(instr);
4389 unsigned binding = nir_intrinsic_binding(instr);
4390
4391 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4392 binding);
4393 break;
4394 }
4395 case nir_intrinsic_vulkan_resource_reindex:
4396 result = visit_vulkan_resource_reindex(ctx, instr);
4397 break;
4398 case nir_intrinsic_store_ssbo:
4399 visit_store_ssbo(ctx, instr);
4400 break;
4401 case nir_intrinsic_load_ssbo:
4402 result = visit_load_buffer(ctx, instr);
4403 break;
4404 case nir_intrinsic_ssbo_atomic_add:
4405 case nir_intrinsic_ssbo_atomic_imin:
4406 case nir_intrinsic_ssbo_atomic_umin:
4407 case nir_intrinsic_ssbo_atomic_imax:
4408 case nir_intrinsic_ssbo_atomic_umax:
4409 case nir_intrinsic_ssbo_atomic_and:
4410 case nir_intrinsic_ssbo_atomic_or:
4411 case nir_intrinsic_ssbo_atomic_xor:
4412 case nir_intrinsic_ssbo_atomic_exchange:
4413 case nir_intrinsic_ssbo_atomic_comp_swap:
4414 result = visit_atomic_ssbo(ctx, instr);
4415 break;
4416 case nir_intrinsic_load_ubo:
4417 result = visit_load_ubo_buffer(ctx, instr);
4418 break;
4419 case nir_intrinsic_get_buffer_size:
4420 result = visit_get_buffer_size(ctx, instr);
4421 break;
4422 case nir_intrinsic_load_var:
4423 result = visit_load_var(ctx, instr);
4424 break;
4425 case nir_intrinsic_store_var:
4426 visit_store_var(ctx, instr);
4427 break;
4428 case nir_intrinsic_image_load:
4429 result = visit_image_load(ctx, instr);
4430 break;
4431 case nir_intrinsic_image_store:
4432 visit_image_store(ctx, instr);
4433 break;
4434 case nir_intrinsic_image_atomic_add:
4435 case nir_intrinsic_image_atomic_min:
4436 case nir_intrinsic_image_atomic_max:
4437 case nir_intrinsic_image_atomic_and:
4438 case nir_intrinsic_image_atomic_or:
4439 case nir_intrinsic_image_atomic_xor:
4440 case nir_intrinsic_image_atomic_exchange:
4441 case nir_intrinsic_image_atomic_comp_swap:
4442 result = visit_image_atomic(ctx, instr);
4443 break;
4444 case nir_intrinsic_image_size:
4445 result = visit_image_size(ctx, instr);
4446 break;
4447 case nir_intrinsic_shader_clock:
4448 result = ac_build_shader_clock(&ctx->ac);
4449 break;
4450 case nir_intrinsic_discard:
4451 case nir_intrinsic_discard_if:
4452 emit_discard(ctx, instr);
4453 break;
4454 case nir_intrinsic_memory_barrier:
4455 case nir_intrinsic_group_memory_barrier:
4456 case nir_intrinsic_memory_barrier_atomic_counter:
4457 case nir_intrinsic_memory_barrier_buffer:
4458 case nir_intrinsic_memory_barrier_image:
4459 case nir_intrinsic_memory_barrier_shared:
4460 emit_membar(&ctx->ac, instr);
4461 break;
4462 case nir_intrinsic_barrier:
4463 emit_barrier(&ctx->ac, ctx->stage);
4464 break;
4465 case nir_intrinsic_var_atomic_add:
4466 case nir_intrinsic_var_atomic_imin:
4467 case nir_intrinsic_var_atomic_umin:
4468 case nir_intrinsic_var_atomic_imax:
4469 case nir_intrinsic_var_atomic_umax:
4470 case nir_intrinsic_var_atomic_and:
4471 case nir_intrinsic_var_atomic_or:
4472 case nir_intrinsic_var_atomic_xor:
4473 case nir_intrinsic_var_atomic_exchange:
4474 case nir_intrinsic_var_atomic_comp_swap:
4475 result = visit_var_atomic(ctx, instr);
4476 break;
4477 case nir_intrinsic_interp_var_at_centroid:
4478 case nir_intrinsic_interp_var_at_sample:
4479 case nir_intrinsic_interp_var_at_offset:
4480 result = visit_interp(ctx, instr);
4481 break;
4482 case nir_intrinsic_emit_vertex:
4483 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
4484 break;
4485 case nir_intrinsic_end_primitive:
4486 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4487 break;
4488 case nir_intrinsic_load_tess_coord:
4489 result = ctx->abi->load_tess_coord(ctx->abi);
4490 break;
4491 case nir_intrinsic_load_tess_level_outer:
4492 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4493 break;
4494 case nir_intrinsic_load_tess_level_inner:
4495 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4496 break;
4497 case nir_intrinsic_load_patch_vertices_in:
4498 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4499 break;
4500 case nir_intrinsic_vote_all: {
4501 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4502 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4503 break;
4504 }
4505 case nir_intrinsic_vote_any: {
4506 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4507 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4508 break;
4509 }
4510 case nir_intrinsic_vote_eq: {
4511 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4512 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4513 break;
4514 }
4515 default:
4516 fprintf(stderr, "Unknown intrinsic: ");
4517 nir_print_instr(&instr->instr, stderr);
4518 fprintf(stderr, "\n");
4519 break;
4520 }
4521 if (result) {
4522 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4523 }
4524 }
4525
4526 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4527 LLVMValueRef buffer_ptr, bool write)
4528 {
4529 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4530 LLVMValueRef result;
4531
4532 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4533
4534 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4535 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4536
4537 return result;
4538 }
4539
4540 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4541 {
4542 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4543 LLVMValueRef result;
4544
4545 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4546
4547 result = LLVMBuildLoad(ctx->builder, buffer_ptr, "");
4548 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4549
4550 return result;
4551 }
4552
4553 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4554 unsigned descriptor_set,
4555 unsigned base_index,
4556 unsigned constant_index,
4557 LLVMValueRef index,
4558 enum ac_descriptor_type desc_type,
4559 bool image, bool write)
4560 {
4561 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4562 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4563 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4564 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4565 unsigned offset = binding->offset;
4566 unsigned stride = binding->size;
4567 unsigned type_size;
4568 LLVMBuilderRef builder = ctx->builder;
4569 LLVMTypeRef type;
4570
4571 assert(base_index < layout->binding_count);
4572
4573 switch (desc_type) {
4574 case AC_DESC_IMAGE:
4575 type = ctx->ac.v8i32;
4576 type_size = 32;
4577 break;
4578 case AC_DESC_FMASK:
4579 type = ctx->ac.v8i32;
4580 offset += 32;
4581 type_size = 32;
4582 break;
4583 case AC_DESC_SAMPLER:
4584 type = ctx->ac.v4i32;
4585 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4586 offset += 64;
4587
4588 type_size = 16;
4589 break;
4590 case AC_DESC_BUFFER:
4591 type = ctx->ac.v4i32;
4592 type_size = 16;
4593 break;
4594 default:
4595 unreachable("invalid desc_type\n");
4596 }
4597
4598 offset += constant_index * stride;
4599
4600 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4601 (!index || binding->immutable_samplers_equal)) {
4602 if (binding->immutable_samplers_equal)
4603 constant_index = 0;
4604
4605 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4606
4607 LLVMValueRef constants[] = {
4608 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4609 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4610 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4611 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4612 };
4613 return ac_build_gather_values(&ctx->ac, constants, 4);
4614 }
4615
4616 assert(stride % type_size == 0);
4617
4618 if (!index)
4619 index = ctx->ac.i32_0;
4620
4621 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4622
4623 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4624 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4625
4626 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4627 }
4628
4629 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4630 const nir_deref_var *deref,
4631 enum ac_descriptor_type desc_type,
4632 const nir_tex_instr *tex_instr,
4633 bool image, bool write)
4634 {
4635 LLVMValueRef index = NULL;
4636 unsigned constant_index = 0;
4637 unsigned descriptor_set;
4638 unsigned base_index;
4639
4640 if (!deref) {
4641 assert(tex_instr && !image);
4642 descriptor_set = 0;
4643 base_index = tex_instr->sampler_index;
4644 } else {
4645 const nir_deref *tail = &deref->deref;
4646 while (tail->child) {
4647 const nir_deref_array *child = nir_deref_as_array(tail->child);
4648 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4649
4650 if (!array_size)
4651 array_size = 1;
4652
4653 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4654
4655 if (child->deref_array_type == nir_deref_array_type_indirect) {
4656 LLVMValueRef indirect = get_src(ctx, child->indirect);
4657
4658 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4659 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4660
4661 if (!index)
4662 index = indirect;
4663 else
4664 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4665 }
4666
4667 constant_index += child->base_offset * array_size;
4668
4669 tail = &child->deref;
4670 }
4671 descriptor_set = deref->var->data.descriptor_set;
4672 base_index = deref->var->data.binding;
4673 }
4674
4675 return ctx->abi->load_sampler_desc(ctx->abi,
4676 descriptor_set,
4677 base_index,
4678 constant_index, index,
4679 desc_type, image, write);
4680 }
4681
4682 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4683 struct ac_image_args *args,
4684 const nir_tex_instr *instr,
4685 nir_texop op,
4686 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4687 LLVMValueRef *param, unsigned count,
4688 unsigned dmask)
4689 {
4690 unsigned is_rect = 0;
4691 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4692
4693 if (op == nir_texop_lod)
4694 da = false;
4695 /* Pad to power of two vector */
4696 while (count < util_next_power_of_two(count))
4697 param[count++] = LLVMGetUndef(ctx->i32);
4698
4699 if (count > 1)
4700 args->addr = ac_build_gather_values(ctx, param, count);
4701 else
4702 args->addr = param[0];
4703
4704 args->resource = res_ptr;
4705 args->sampler = samp_ptr;
4706
4707 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4708 args->addr = param[0];
4709 return;
4710 }
4711
4712 args->dmask = dmask;
4713 args->unorm = is_rect;
4714 args->da = da;
4715 }
4716
4717 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4718 *
4719 * SI-CI:
4720 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4721 * filtering manually. The driver sets img7 to a mask clearing
4722 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4723 * s_and_b32 samp0, samp0, img7
4724 *
4725 * VI:
4726 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4727 */
4728 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4729 LLVMValueRef res, LLVMValueRef samp)
4730 {
4731 LLVMBuilderRef builder = ctx->ac.builder;
4732 LLVMValueRef img7, samp0;
4733
4734 if (ctx->ac.chip_class >= VI)
4735 return samp;
4736
4737 img7 = LLVMBuildExtractElement(builder, res,
4738 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4739 samp0 = LLVMBuildExtractElement(builder, samp,
4740 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4741 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4742 return LLVMBuildInsertElement(builder, samp, samp0,
4743 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4744 }
4745
4746 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4747 nir_tex_instr *instr,
4748 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4749 LLVMValueRef *fmask_ptr)
4750 {
4751 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4752 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4753 else
4754 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4755 if (samp_ptr) {
4756 if (instr->sampler)
4757 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4758 else
4759 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4760 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4761 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4762 }
4763 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4764 instr->op == nir_texop_samples_identical))
4765 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4766 }
4767
4768 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4769 LLVMValueRef coord)
4770 {
4771 coord = ac_to_float(ctx, coord);
4772 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4773 coord = ac_to_integer(ctx, coord);
4774 return coord;
4775 }
4776
4777 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4778 {
4779 LLVMValueRef result = NULL;
4780 struct ac_image_args args = { 0 };
4781 unsigned dmask = 0xf;
4782 LLVMValueRef address[16];
4783 LLVMValueRef coords[5];
4784 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4785 LLVMValueRef bias = NULL, offsets = NULL;
4786 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4787 LLVMValueRef ddx = NULL, ddy = NULL;
4788 LLVMValueRef derivs[6];
4789 unsigned chan, count = 0;
4790 unsigned const_src = 0, num_deriv_comp = 0;
4791 bool lod_is_zero = false;
4792
4793 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4794
4795 for (unsigned i = 0; i < instr->num_srcs; i++) {
4796 switch (instr->src[i].src_type) {
4797 case nir_tex_src_coord:
4798 coord = get_src(ctx, instr->src[i].src);
4799 break;
4800 case nir_tex_src_projector:
4801 break;
4802 case nir_tex_src_comparator:
4803 comparator = get_src(ctx, instr->src[i].src);
4804 break;
4805 case nir_tex_src_offset:
4806 offsets = get_src(ctx, instr->src[i].src);
4807 const_src = i;
4808 break;
4809 case nir_tex_src_bias:
4810 bias = get_src(ctx, instr->src[i].src);
4811 break;
4812 case nir_tex_src_lod: {
4813 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4814
4815 if (val && val->i32[0] == 0)
4816 lod_is_zero = true;
4817 lod = get_src(ctx, instr->src[i].src);
4818 break;
4819 }
4820 case nir_tex_src_ms_index:
4821 sample_index = get_src(ctx, instr->src[i].src);
4822 break;
4823 case nir_tex_src_ms_mcs:
4824 break;
4825 case nir_tex_src_ddx:
4826 ddx = get_src(ctx, instr->src[i].src);
4827 num_deriv_comp = instr->src[i].src.ssa->num_components;
4828 break;
4829 case nir_tex_src_ddy:
4830 ddy = get_src(ctx, instr->src[i].src);
4831 break;
4832 case nir_tex_src_texture_offset:
4833 case nir_tex_src_sampler_offset:
4834 case nir_tex_src_plane:
4835 default:
4836 break;
4837 }
4838 }
4839
4840 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4841 result = get_buffer_size(ctx, res_ptr, true);
4842 goto write_result;
4843 }
4844
4845 if (instr->op == nir_texop_texture_samples) {
4846 LLVMValueRef res, samples, is_msaa;
4847 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4848 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4849 LLVMConstInt(ctx->ac.i32, 3, false), "");
4850 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4851 LLVMConstInt(ctx->ac.i32, 28, false), "");
4852 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4853 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4854 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4855 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4856
4857 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4858 LLVMConstInt(ctx->ac.i32, 16, false), "");
4859 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4860 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4861 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4862 samples, "");
4863 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4864 ctx->ac.i32_1, "");
4865 result = samples;
4866 goto write_result;
4867 }
4868
4869 if (coord)
4870 for (chan = 0; chan < instr->coord_components; chan++)
4871 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4872
4873 if (offsets && instr->op != nir_texop_txf) {
4874 LLVMValueRef offset[3], pack;
4875 for (chan = 0; chan < 3; ++chan)
4876 offset[chan] = ctx->ac.i32_0;
4877
4878 args.offset = true;
4879 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4880 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4881 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4882 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4883 if (chan)
4884 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4885 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4886 }
4887 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4888 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4889 address[count++] = pack;
4890
4891 }
4892 /* pack LOD bias value */
4893 if (instr->op == nir_texop_txb && bias) {
4894 address[count++] = bias;
4895 }
4896
4897 /* Pack depth comparison value */
4898 if (instr->is_shadow && comparator) {
4899 LLVMValueRef z = ac_to_float(&ctx->ac,
4900 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4901
4902 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4903 * so the depth comparison value isn't clamped for Z16 and
4904 * Z24 anymore. Do it manually here.
4905 *
4906 * It's unnecessary if the original texture format was
4907 * Z32_FLOAT, but we don't know that here.
4908 */
4909 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4910 z = ac_build_clamp(&ctx->ac, z);
4911
4912 address[count++] = z;
4913 }
4914
4915 /* pack derivatives */
4916 if (ddx || ddy) {
4917 int num_src_deriv_channels, num_dest_deriv_channels;
4918 switch (instr->sampler_dim) {
4919 case GLSL_SAMPLER_DIM_3D:
4920 case GLSL_SAMPLER_DIM_CUBE:
4921 num_deriv_comp = 3;
4922 num_src_deriv_channels = 3;
4923 num_dest_deriv_channels = 3;
4924 break;
4925 case GLSL_SAMPLER_DIM_2D:
4926 default:
4927 num_src_deriv_channels = 2;
4928 num_dest_deriv_channels = 2;
4929 num_deriv_comp = 2;
4930 break;
4931 case GLSL_SAMPLER_DIM_1D:
4932 num_src_deriv_channels = 1;
4933 if (ctx->ac.chip_class >= GFX9) {
4934 num_dest_deriv_channels = 2;
4935 num_deriv_comp = 2;
4936 } else {
4937 num_dest_deriv_channels = 1;
4938 num_deriv_comp = 1;
4939 }
4940 break;
4941 }
4942
4943 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4944 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
4945 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
4946 }
4947 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4948 derivs[i] = ctx->ac.f32_0;
4949 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4950 }
4951 }
4952
4953 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4954 for (chan = 0; chan < instr->coord_components; chan++)
4955 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4956 if (instr->coord_components == 3)
4957 coords[3] = LLVMGetUndef(ctx->ac.f32);
4958 ac_prepare_cube_coords(&ctx->ac,
4959 instr->op == nir_texop_txd, instr->is_array,
4960 instr->op == nir_texop_lod, coords, derivs);
4961 if (num_deriv_comp)
4962 num_deriv_comp--;
4963 }
4964
4965 if (ddx || ddy) {
4966 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4967 address[count++] = derivs[i];
4968 }
4969
4970 /* Pack texture coordinates */
4971 if (coord) {
4972 address[count++] = coords[0];
4973 if (instr->coord_components > 1) {
4974 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4975 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4976 }
4977 address[count++] = coords[1];
4978 }
4979 if (instr->coord_components > 2) {
4980 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4981 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4982 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4983 instr->op != nir_texop_txf) {
4984 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4985 }
4986 address[count++] = coords[2];
4987 }
4988
4989 if (ctx->ac.chip_class >= GFX9) {
4990 LLVMValueRef filler;
4991 if (instr->op == nir_texop_txf)
4992 filler = ctx->ac.i32_0;
4993 else
4994 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4995
4996 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4997 /* No nir_texop_lod, because it does not take a slice
4998 * even with array textures. */
4999 if (instr->is_array && instr->op != nir_texop_lod ) {
5000 address[count] = address[count - 1];
5001 address[count - 1] = filler;
5002 count++;
5003 } else
5004 address[count++] = filler;
5005 }
5006 }
5007 }
5008
5009 /* Pack LOD */
5010 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5011 instr->op == nir_texop_txf)) {
5012 address[count++] = lod;
5013 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5014 address[count++] = sample_index;
5015 } else if(instr->op == nir_texop_txs) {
5016 count = 0;
5017 if (lod)
5018 address[count++] = lod;
5019 else
5020 address[count++] = ctx->ac.i32_0;
5021 }
5022
5023 for (chan = 0; chan < count; chan++) {
5024 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5025 address[chan], ctx->ac.i32, "");
5026 }
5027
5028 if (instr->op == nir_texop_samples_identical) {
5029 LLVMValueRef txf_address[4];
5030 struct ac_image_args txf_args = { 0 };
5031 unsigned txf_count = count;
5032 memcpy(txf_address, address, sizeof(txf_address));
5033
5034 if (!instr->is_array)
5035 txf_address[2] = ctx->ac.i32_0;
5036 txf_address[3] = ctx->ac.i32_0;
5037
5038 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5039 fmask_ptr, NULL,
5040 txf_address, txf_count, 0xf);
5041
5042 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5043
5044 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5045 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5046 goto write_result;
5047 }
5048
5049 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5050 instr->op != nir_texop_txs) {
5051 unsigned sample_chan = instr->is_array ? 3 : 2;
5052 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5053 address[0],
5054 address[1],
5055 instr->is_array ? address[2] : NULL,
5056 address[sample_chan],
5057 fmask_ptr);
5058 }
5059
5060 if (offsets && instr->op == nir_texop_txf) {
5061 nir_const_value *const_offset =
5062 nir_src_as_const_value(instr->src[const_src].src);
5063 int num_offsets = instr->src[const_src].src.ssa->num_components;
5064 assert(const_offset);
5065 num_offsets = MIN2(num_offsets, instr->coord_components);
5066 if (num_offsets > 2)
5067 address[2] = LLVMBuildAdd(ctx->ac.builder,
5068 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5069 if (num_offsets > 1)
5070 address[1] = LLVMBuildAdd(ctx->ac.builder,
5071 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5072 address[0] = LLVMBuildAdd(ctx->ac.builder,
5073 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5074
5075 }
5076
5077 /* TODO TG4 support */
5078 if (instr->op == nir_texop_tg4) {
5079 if (instr->is_shadow)
5080 dmask = 1;
5081 else
5082 dmask = 1 << instr->component;
5083 }
5084 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5085 res_ptr, samp_ptr, address, count, dmask);
5086
5087 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5088
5089 if (instr->op == nir_texop_query_levels)
5090 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5091 else if (instr->is_shadow && instr->is_new_style_shadow &&
5092 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5093 instr->op != nir_texop_tg4)
5094 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5095 else if (instr->op == nir_texop_txs &&
5096 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5097 instr->is_array) {
5098 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5099 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5100 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5101 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5102 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5103 } else if (ctx->ac.chip_class >= GFX9 &&
5104 instr->op == nir_texop_txs &&
5105 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5106 instr->is_array) {
5107 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5108 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5109 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5110 ctx->ac.i32_1, "");
5111 } else if (instr->dest.ssa.num_components != 4)
5112 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5113
5114 write_result:
5115 if (result) {
5116 assert(instr->dest.is_ssa);
5117 result = ac_to_integer(&ctx->ac, result);
5118 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5119 }
5120 }
5121
5122
5123 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5124 {
5125 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5126 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5127
5128 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5129 _mesa_hash_table_insert(ctx->phis, instr, result);
5130 }
5131
5132 static void visit_post_phi(struct ac_nir_context *ctx,
5133 nir_phi_instr *instr,
5134 LLVMValueRef llvm_phi)
5135 {
5136 nir_foreach_phi_src(src, instr) {
5137 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5138 LLVMValueRef llvm_src = get_src(ctx, src->src);
5139
5140 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5141 }
5142 }
5143
5144 static void phi_post_pass(struct ac_nir_context *ctx)
5145 {
5146 struct hash_entry *entry;
5147 hash_table_foreach(ctx->phis, entry) {
5148 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5149 (LLVMValueRef)entry->data);
5150 }
5151 }
5152
5153
5154 static void visit_ssa_undef(struct ac_nir_context *ctx,
5155 const nir_ssa_undef_instr *instr)
5156 {
5157 unsigned num_components = instr->def.num_components;
5158 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5159 LLVMValueRef undef;
5160
5161 if (num_components == 1)
5162 undef = LLVMGetUndef(type);
5163 else {
5164 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5165 }
5166 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5167 }
5168
5169 static void visit_jump(struct ac_nir_context *ctx,
5170 const nir_jump_instr *instr)
5171 {
5172 switch (instr->type) {
5173 case nir_jump_break:
5174 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5175 LLVMClearInsertionPosition(ctx->ac.builder);
5176 break;
5177 case nir_jump_continue:
5178 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5179 LLVMClearInsertionPosition(ctx->ac.builder);
5180 break;
5181 default:
5182 fprintf(stderr, "Unknown NIR jump instr: ");
5183 nir_print_instr(&instr->instr, stderr);
5184 fprintf(stderr, "\n");
5185 abort();
5186 }
5187 }
5188
5189 static void visit_cf_list(struct ac_nir_context *ctx,
5190 struct exec_list *list);
5191
5192 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5193 {
5194 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5195 nir_foreach_instr(instr, block)
5196 {
5197 switch (instr->type) {
5198 case nir_instr_type_alu:
5199 visit_alu(ctx, nir_instr_as_alu(instr));
5200 break;
5201 case nir_instr_type_load_const:
5202 visit_load_const(ctx, nir_instr_as_load_const(instr));
5203 break;
5204 case nir_instr_type_intrinsic:
5205 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5206 break;
5207 case nir_instr_type_tex:
5208 visit_tex(ctx, nir_instr_as_tex(instr));
5209 break;
5210 case nir_instr_type_phi:
5211 visit_phi(ctx, nir_instr_as_phi(instr));
5212 break;
5213 case nir_instr_type_ssa_undef:
5214 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5215 break;
5216 case nir_instr_type_jump:
5217 visit_jump(ctx, nir_instr_as_jump(instr));
5218 break;
5219 default:
5220 fprintf(stderr, "Unknown NIR instr type: ");
5221 nir_print_instr(instr, stderr);
5222 fprintf(stderr, "\n");
5223 abort();
5224 }
5225 }
5226
5227 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5228 }
5229
5230 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5231 {
5232 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5233
5234 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5235 LLVMBasicBlockRef merge_block =
5236 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5237 LLVMBasicBlockRef if_block =
5238 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5239 LLVMBasicBlockRef else_block = merge_block;
5240 if (!exec_list_is_empty(&if_stmt->else_list))
5241 else_block = LLVMAppendBasicBlockInContext(
5242 ctx->ac.context, fn, "");
5243
5244 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5245 ctx->ac.i32_0, "");
5246 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5247
5248 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5249 visit_cf_list(ctx, &if_stmt->then_list);
5250 if (LLVMGetInsertBlock(ctx->ac.builder))
5251 LLVMBuildBr(ctx->ac.builder, merge_block);
5252
5253 if (!exec_list_is_empty(&if_stmt->else_list)) {
5254 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5255 visit_cf_list(ctx, &if_stmt->else_list);
5256 if (LLVMGetInsertBlock(ctx->ac.builder))
5257 LLVMBuildBr(ctx->ac.builder, merge_block);
5258 }
5259
5260 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5261 }
5262
5263 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5264 {
5265 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5266 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5267 LLVMBasicBlockRef break_parent = ctx->break_block;
5268
5269 ctx->continue_block =
5270 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5271 ctx->break_block =
5272 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5273
5274 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5275 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5276 visit_cf_list(ctx, &loop->body);
5277
5278 if (LLVMGetInsertBlock(ctx->ac.builder))
5279 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5280 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5281
5282 ctx->continue_block = continue_parent;
5283 ctx->break_block = break_parent;
5284 }
5285
5286 static void visit_cf_list(struct ac_nir_context *ctx,
5287 struct exec_list *list)
5288 {
5289 foreach_list_typed(nir_cf_node, node, node, list)
5290 {
5291 switch (node->type) {
5292 case nir_cf_node_block:
5293 visit_block(ctx, nir_cf_node_as_block(node));
5294 break;
5295
5296 case nir_cf_node_if:
5297 visit_if(ctx, nir_cf_node_as_if(node));
5298 break;
5299
5300 case nir_cf_node_loop:
5301 visit_loop(ctx, nir_cf_node_as_loop(node));
5302 break;
5303
5304 default:
5305 assert(0);
5306 }
5307 }
5308 }
5309
5310 static void
5311 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5312 struct nir_variable *variable)
5313 {
5314 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5315 LLVMValueRef t_offset;
5316 LLVMValueRef t_list;
5317 LLVMValueRef input;
5318 LLVMValueRef buffer_index;
5319 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5320 int idx = variable->data.location;
5321 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5322 uint8_t input_usage_mask =
5323 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5324 unsigned num_channels = util_last_bit(input_usage_mask);
5325
5326 variable->data.driver_location = idx * 4;
5327
5328 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5329 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5330 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5331 ctx->abi.start_instance, "");
5332 if (ctx->options->key.vs.as_ls) {
5333 ctx->shader_info->vs.vgpr_comp_cnt =
5334 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5335 } else {
5336 ctx->shader_info->vs.vgpr_comp_cnt =
5337 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5338 }
5339 } else
5340 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5341 ctx->abi.base_vertex, "");
5342 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5343
5344 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5345
5346 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5347 buffer_index,
5348 ctx->ac.i32_0,
5349 num_channels, false, true);
5350
5351 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5352
5353 for (unsigned chan = 0; chan < 4; chan++) {
5354 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5355 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5356 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5357 input, llvm_chan, ""));
5358 }
5359 }
5360 }
5361
5362 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5363 unsigned attr,
5364 LLVMValueRef interp_param,
5365 LLVMValueRef prim_mask,
5366 LLVMValueRef result[4])
5367 {
5368 LLVMValueRef attr_number;
5369 unsigned chan;
5370 LLVMValueRef i, j;
5371 bool interp = interp_param != NULL;
5372
5373 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5374
5375 /* fs.constant returns the param from the middle vertex, so it's not
5376 * really useful for flat shading. It's meant to be used for custom
5377 * interpolation (but the intrinsic can't fetch from the other two
5378 * vertices).
5379 *
5380 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5381 * to do the right thing. The only reason we use fs.constant is that
5382 * fs.interp cannot be used on integers, because they can be equal
5383 * to NaN.
5384 */
5385 if (interp) {
5386 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5387 ctx->ac.v2f32, "");
5388
5389 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5390 ctx->ac.i32_0, "");
5391 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5392 ctx->ac.i32_1, "");
5393 }
5394
5395 for (chan = 0; chan < 4; chan++) {
5396 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5397
5398 if (interp) {
5399 result[chan] = ac_build_fs_interp(&ctx->ac,
5400 llvm_chan,
5401 attr_number,
5402 prim_mask, i, j);
5403 } else {
5404 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5405 LLVMConstInt(ctx->ac.i32, 2, false),
5406 llvm_chan,
5407 attr_number,
5408 prim_mask);
5409 }
5410 }
5411 }
5412
5413 static void
5414 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5415 struct nir_variable *variable)
5416 {
5417 int idx = variable->data.location;
5418 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5419 LLVMValueRef interp;
5420
5421 variable->data.driver_location = idx * 4;
5422 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5423
5424 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5425 unsigned interp_type;
5426 if (variable->data.sample) {
5427 interp_type = INTERP_SAMPLE;
5428 ctx->shader_info->info.ps.force_persample = true;
5429 } else if (variable->data.centroid)
5430 interp_type = INTERP_CENTROID;
5431 else
5432 interp_type = INTERP_CENTER;
5433
5434 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5435 } else
5436 interp = NULL;
5437
5438 for (unsigned i = 0; i < attrib_count; ++i)
5439 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5440
5441 }
5442
5443 static void
5444 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5445 struct nir_shader *nir) {
5446 nir_foreach_variable(variable, &nir->inputs)
5447 handle_vs_input_decl(ctx, variable);
5448 }
5449
5450 static void
5451 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5452 struct nir_shader *nir)
5453 {
5454 if (!ctx->options->key.fs.multisample)
5455 return;
5456
5457 bool uses_center = false;
5458 bool uses_centroid = false;
5459 nir_foreach_variable(variable, &nir->inputs) {
5460 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5461 variable->data.sample)
5462 continue;
5463
5464 if (variable->data.centroid)
5465 uses_centroid = true;
5466 else
5467 uses_center = true;
5468 }
5469
5470 if (uses_center && uses_centroid) {
5471 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5472 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5473 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5474 }
5475 }
5476
5477 static void
5478 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5479 struct nir_shader *nir)
5480 {
5481 prepare_interp_optimize(ctx, nir);
5482
5483 nir_foreach_variable(variable, &nir->inputs)
5484 handle_fs_input_decl(ctx, variable);
5485
5486 unsigned index = 0;
5487
5488 if (ctx->shader_info->info.ps.uses_input_attachments ||
5489 ctx->shader_info->info.needs_multiview_view_index)
5490 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5491
5492 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5493 LLVMValueRef interp_param;
5494 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5495
5496 if (!(ctx->input_mask & (1ull << i)))
5497 continue;
5498
5499 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5500 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5501 interp_param = *inputs;
5502 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5503 inputs);
5504
5505 if (!interp_param)
5506 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5507 ++index;
5508 } else if (i == VARYING_SLOT_POS) {
5509 for(int i = 0; i < 3; ++i)
5510 inputs[i] = ctx->abi.frag_pos[i];
5511
5512 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5513 ctx->abi.frag_pos[3]);
5514 }
5515 }
5516 ctx->shader_info->fs.num_interp = index;
5517 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5518 ctx->shader_info->fs.has_pcoord = true;
5519 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5520 ctx->shader_info->fs.prim_id_input = true;
5521 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5522 ctx->shader_info->fs.layer_input = true;
5523 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5524
5525 if (ctx->shader_info->info.needs_multiview_view_index)
5526 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5527 }
5528
5529 static LLVMValueRef
5530 ac_build_alloca(struct ac_llvm_context *ac,
5531 LLVMTypeRef type,
5532 const char *name)
5533 {
5534 LLVMBuilderRef builder = ac->builder;
5535 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5536 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5537 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5538 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5539 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5540 LLVMValueRef res;
5541
5542 if (first_instr) {
5543 LLVMPositionBuilderBefore(first_builder, first_instr);
5544 } else {
5545 LLVMPositionBuilderAtEnd(first_builder, first_block);
5546 }
5547
5548 res = LLVMBuildAlloca(first_builder, type, name);
5549 LLVMBuildStore(builder, LLVMConstNull(type), res);
5550
5551 LLVMDisposeBuilder(first_builder);
5552
5553 return res;
5554 }
5555
5556 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5557 LLVMTypeRef type,
5558 const char *name)
5559 {
5560 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5561 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5562 return ptr;
5563 }
5564
5565 static void
5566 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5567 struct nir_variable *variable,
5568 struct nir_shader *shader,
5569 gl_shader_stage stage)
5570 {
5571 int idx = variable->data.location + variable->data.index;
5572 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5573 uint64_t mask_attribs;
5574
5575 variable->data.driver_location = idx * 4;
5576
5577 /* tess ctrl has it's own load/store paths for outputs */
5578 if (stage == MESA_SHADER_TESS_CTRL)
5579 return;
5580
5581 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5582 if (stage == MESA_SHADER_VERTEX ||
5583 stage == MESA_SHADER_TESS_EVAL ||
5584 stage == MESA_SHADER_GEOMETRY) {
5585 if (idx == VARYING_SLOT_CLIP_DIST0) {
5586 int length = shader->info.clip_distance_array_size +
5587 shader->info.cull_distance_array_size;
5588 if (stage == MESA_SHADER_VERTEX) {
5589 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5590 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5591 }
5592 if (stage == MESA_SHADER_TESS_EVAL) {
5593 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5594 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5595 }
5596
5597 if (length > 4)
5598 attrib_count = 2;
5599 else
5600 attrib_count = 1;
5601 mask_attribs = 1ull << idx;
5602 }
5603 }
5604
5605 ctx->output_mask |= mask_attribs;
5606 }
5607
5608 static void
5609 handle_shader_output_decl(struct ac_nir_context *ctx,
5610 struct nir_shader *nir,
5611 struct nir_variable *variable)
5612 {
5613 unsigned output_loc = variable->data.driver_location / 4;
5614 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5615
5616 /* tess ctrl has it's own load/store paths for outputs */
5617 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5618 return;
5619
5620 if (ctx->stage == MESA_SHADER_VERTEX ||
5621 ctx->stage == MESA_SHADER_TESS_EVAL ||
5622 ctx->stage == MESA_SHADER_GEOMETRY) {
5623 int idx = variable->data.location + variable->data.index;
5624 if (idx == VARYING_SLOT_CLIP_DIST0) {
5625 int length = nir->info.clip_distance_array_size +
5626 nir->info.cull_distance_array_size;
5627
5628 if (length > 4)
5629 attrib_count = 2;
5630 else
5631 attrib_count = 1;
5632 }
5633 }
5634
5635 for (unsigned i = 0; i < attrib_count; ++i) {
5636 for (unsigned chan = 0; chan < 4; chan++) {
5637 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5638 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5639 }
5640 }
5641 }
5642
5643 static LLVMTypeRef
5644 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5645 enum glsl_base_type type)
5646 {
5647 switch (type) {
5648 case GLSL_TYPE_INT:
5649 case GLSL_TYPE_UINT:
5650 case GLSL_TYPE_BOOL:
5651 case GLSL_TYPE_SUBROUTINE:
5652 return ctx->ac.i32;
5653 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5654 return ctx->ac.f32;
5655 case GLSL_TYPE_INT64:
5656 case GLSL_TYPE_UINT64:
5657 return ctx->ac.i64;
5658 case GLSL_TYPE_DOUBLE:
5659 return ctx->ac.f64;
5660 default:
5661 unreachable("unknown GLSL type");
5662 }
5663 }
5664
5665 static LLVMTypeRef
5666 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5667 const struct glsl_type *type)
5668 {
5669 if (glsl_type_is_scalar(type)) {
5670 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5671 }
5672
5673 if (glsl_type_is_vector(type)) {
5674 return LLVMVectorType(
5675 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5676 glsl_get_vector_elements(type));
5677 }
5678
5679 if (glsl_type_is_matrix(type)) {
5680 return LLVMArrayType(
5681 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5682 glsl_get_matrix_columns(type));
5683 }
5684
5685 if (glsl_type_is_array(type)) {
5686 return LLVMArrayType(
5687 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5688 glsl_get_length(type));
5689 }
5690
5691 assert(glsl_type_is_struct(type));
5692
5693 LLVMTypeRef member_types[glsl_get_length(type)];
5694
5695 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5696 member_types[i] =
5697 glsl_to_llvm_type(ctx,
5698 glsl_get_struct_field(type, i));
5699 }
5700
5701 return LLVMStructTypeInContext(ctx->context, member_types,
5702 glsl_get_length(type), false);
5703 }
5704
5705 static void
5706 setup_locals(struct ac_nir_context *ctx,
5707 struct nir_function *func)
5708 {
5709 int i, j;
5710 ctx->num_locals = 0;
5711 nir_foreach_variable(variable, &func->impl->locals) {
5712 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5713 variable->data.driver_location = ctx->num_locals * 4;
5714 variable->data.location_frac = 0;
5715 ctx->num_locals += attrib_count;
5716 }
5717 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5718 if (!ctx->locals)
5719 return;
5720
5721 for (i = 0; i < ctx->num_locals; i++) {
5722 for (j = 0; j < 4; j++) {
5723 ctx->locals[i * 4 + j] =
5724 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5725 }
5726 }
5727 }
5728
5729 static void
5730 setup_shared(struct ac_nir_context *ctx,
5731 struct nir_shader *nir)
5732 {
5733 nir_foreach_variable(variable, &nir->shared) {
5734 LLVMValueRef shared =
5735 LLVMAddGlobalInAddressSpace(
5736 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5737 variable->name ? variable->name : "",
5738 AC_LOCAL_ADDR_SPACE);
5739 _mesa_hash_table_insert(ctx->vars, variable, shared);
5740 }
5741 }
5742
5743 /* Initialize arguments for the shader export intrinsic */
5744 static void
5745 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5746 LLVMValueRef *values,
5747 unsigned target,
5748 struct ac_export_args *args)
5749 {
5750 /* Default is 0xf. Adjusted below depending on the format. */
5751 args->enabled_channels = 0xf;
5752
5753 /* Specify whether the EXEC mask represents the valid mask */
5754 args->valid_mask = 0;
5755
5756 /* Specify whether this is the last export */
5757 args->done = 0;
5758
5759 /* Specify the target we are exporting */
5760 args->target = target;
5761
5762 args->compr = false;
5763 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5764 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5765 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5766 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5767
5768 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5769 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5770 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5771 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5772 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5773 unsigned chan;
5774
5775 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5776 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5777 unsigned bits, bool hi) = NULL;
5778
5779 switch(col_format) {
5780 case V_028714_SPI_SHADER_ZERO:
5781 args->enabled_channels = 0; /* writemask */
5782 args->target = V_008DFC_SQ_EXP_NULL;
5783 break;
5784
5785 case V_028714_SPI_SHADER_32_R:
5786 args->enabled_channels = 1;
5787 args->out[0] = values[0];
5788 break;
5789
5790 case V_028714_SPI_SHADER_32_GR:
5791 args->enabled_channels = 0x3;
5792 args->out[0] = values[0];
5793 args->out[1] = values[1];
5794 break;
5795
5796 case V_028714_SPI_SHADER_32_AR:
5797 args->enabled_channels = 0x9;
5798 args->out[0] = values[0];
5799 args->out[3] = values[3];
5800 break;
5801
5802 case V_028714_SPI_SHADER_FP16_ABGR:
5803 packf = ac_build_cvt_pkrtz_f16;
5804 break;
5805
5806 case V_028714_SPI_SHADER_UNORM16_ABGR:
5807 packf = ac_build_cvt_pknorm_u16;
5808 break;
5809
5810 case V_028714_SPI_SHADER_SNORM16_ABGR:
5811 packf = ac_build_cvt_pknorm_i16;
5812 break;
5813
5814 case V_028714_SPI_SHADER_UINT16_ABGR:
5815 packi = ac_build_cvt_pk_u16;
5816 break;
5817
5818 case V_028714_SPI_SHADER_SINT16_ABGR:
5819 packi = ac_build_cvt_pk_i16;
5820 break;
5821
5822 default:
5823 case V_028714_SPI_SHADER_32_ABGR:
5824 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5825 break;
5826 }
5827
5828 /* Pack f16 or norm_i16/u16. */
5829 if (packf) {
5830 for (chan = 0; chan < 2; chan++) {
5831 LLVMValueRef pack_args[2] = {
5832 values[2 * chan],
5833 values[2 * chan + 1]
5834 };
5835 LLVMValueRef packed;
5836
5837 packed = packf(&ctx->ac, pack_args);
5838 args->out[chan] = ac_to_float(&ctx->ac, packed);
5839 }
5840 args->compr = 1; /* COMPR flag */
5841 }
5842
5843 /* Pack i16/u16. */
5844 if (packi) {
5845 for (chan = 0; chan < 2; chan++) {
5846 LLVMValueRef pack_args[2] = {
5847 ac_to_integer(&ctx->ac, values[2 * chan]),
5848 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5849 };
5850 LLVMValueRef packed;
5851
5852 packed = packi(&ctx->ac, pack_args,
5853 is_int8 ? 8 : is_int10 ? 10 : 16,
5854 chan == 1);
5855 args->out[chan] = ac_to_float(&ctx->ac, packed);
5856 }
5857 args->compr = 1; /* COMPR flag */
5858 }
5859 return;
5860 }
5861
5862 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5863
5864 for (unsigned i = 0; i < 4; ++i)
5865 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5866 }
5867
5868 static void
5869 radv_export_param(struct nir_to_llvm_context *ctx, unsigned index,
5870 LLVMValueRef *values)
5871 {
5872 struct ac_export_args args;
5873
5874 si_llvm_init_export_args(ctx, values,
5875 V_008DFC_SQ_EXP_PARAM + index, &args);
5876 ac_build_export(&ctx->ac, &args);
5877 }
5878
5879 static LLVMValueRef
5880 radv_load_output(struct nir_to_llvm_context *ctx, unsigned index, unsigned chan)
5881 {
5882 LLVMValueRef output =
5883 ctx->nir->outputs[radeon_llvm_reg_index_soa(index, chan)];
5884
5885 return LLVMBuildLoad(ctx->builder, output, "");
5886 }
5887
5888 static void
5889 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5890 bool export_prim_id,
5891 struct ac_vs_output_info *outinfo)
5892 {
5893 uint32_t param_count = 0;
5894 unsigned target;
5895 unsigned pos_idx, num_pos_exports = 0;
5896 struct ac_export_args args, pos_args[4] = {};
5897 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5898 int i;
5899
5900 if (ctx->options->key.has_multiview_view_index) {
5901 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5902 if(!*tmp_out) {
5903 for(unsigned i = 0; i < 4; ++i)
5904 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5905 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5906 }
5907
5908 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
5909 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5910 }
5911
5912 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5913 sizeof(outinfo->vs_output_param_offset));
5914
5915 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5916 LLVMValueRef slots[8];
5917 unsigned j;
5918
5919 if (outinfo->cull_dist_mask)
5920 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5921
5922 i = VARYING_SLOT_CLIP_DIST0;
5923 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5924 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
5925
5926 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5927 slots[i] = LLVMGetUndef(ctx->ac.f32);
5928
5929 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5930 target = V_008DFC_SQ_EXP_POS + 3;
5931 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5932 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5933 &args, sizeof(args));
5934 }
5935
5936 target = V_008DFC_SQ_EXP_POS + 2;
5937 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5938 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5939 &args, sizeof(args));
5940
5941 }
5942
5943 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5944 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5945 for (unsigned j = 0; j < 4; j++)
5946 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
5947 }
5948 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5949
5950 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5951 outinfo->writes_pointsize = true;
5952 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
5953 }
5954
5955 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5956 outinfo->writes_layer = true;
5957 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
5958 }
5959
5960 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5961 outinfo->writes_viewport_index = true;
5962 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
5963 }
5964
5965 if (outinfo->writes_pointsize ||
5966 outinfo->writes_layer ||
5967 outinfo->writes_viewport_index) {
5968 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5969 (outinfo->writes_layer == true ? 4 : 0));
5970 pos_args[1].valid_mask = 0;
5971 pos_args[1].done = 0;
5972 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5973 pos_args[1].compr = 0;
5974 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5975 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5976 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5977 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5978
5979 if (outinfo->writes_pointsize == true)
5980 pos_args[1].out[0] = psize_value;
5981 if (outinfo->writes_layer == true)
5982 pos_args[1].out[2] = layer_value;
5983 if (outinfo->writes_viewport_index == true) {
5984 if (ctx->options->chip_class >= GFX9) {
5985 /* GFX9 has the layer in out.z[10:0] and the viewport
5986 * index in out.z[19:16].
5987 */
5988 LLVMValueRef v = viewport_index_value;
5989 v = ac_to_integer(&ctx->ac, v);
5990 v = LLVMBuildShl(ctx->builder, v,
5991 LLVMConstInt(ctx->ac.i32, 16, false),
5992 "");
5993 v = LLVMBuildOr(ctx->builder, v,
5994 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5995
5996 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5997 pos_args[1].enabled_channels |= 1 << 2;
5998 } else {
5999 pos_args[1].out[3] = viewport_index_value;
6000 pos_args[1].enabled_channels |= 1 << 3;
6001 }
6002 }
6003 }
6004 for (i = 0; i < 4; i++) {
6005 if (pos_args[i].out[0])
6006 num_pos_exports++;
6007 }
6008
6009 pos_idx = 0;
6010 for (i = 0; i < 4; i++) {
6011 if (!pos_args[i].out[0])
6012 continue;
6013
6014 /* Specify the target we are exporting */
6015 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6016 if (pos_idx == num_pos_exports)
6017 pos_args[i].done = 1;
6018 ac_build_export(&ctx->ac, &pos_args[i]);
6019 }
6020
6021 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6022 LLVMValueRef values[4];
6023 if (!(ctx->output_mask & (1ull << i)))
6024 continue;
6025
6026 if (i != VARYING_SLOT_LAYER &&
6027 i != VARYING_SLOT_PRIMITIVE_ID &&
6028 i < VARYING_SLOT_VAR0)
6029 continue;
6030
6031 for (unsigned j = 0; j < 4; j++)
6032 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6033
6034 radv_export_param(ctx, param_count, values);
6035
6036 outinfo->vs_output_param_offset[i] = param_count++;
6037 }
6038
6039 if (export_prim_id) {
6040 LLVMValueRef values[4];
6041
6042 values[0] = ctx->vs_prim_id;
6043 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6044 ctx->shader_info->vs.vgpr_comp_cnt);
6045 for (unsigned j = 1; j < 4; j++)
6046 values[j] = ctx->ac.f32_0;
6047
6048 radv_export_param(ctx, param_count, values);
6049
6050 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6051 outinfo->export_prim_id = true;
6052 }
6053
6054 outinfo->pos_exports = num_pos_exports;
6055 outinfo->param_exports = param_count;
6056 }
6057
6058 static void
6059 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6060 struct ac_es_output_info *outinfo)
6061 {
6062 int j;
6063 uint64_t max_output_written = 0;
6064 LLVMValueRef lds_base = NULL;
6065
6066 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6067 int param_index;
6068 int length = 4;
6069
6070 if (!(ctx->output_mask & (1ull << i)))
6071 continue;
6072
6073 if (i == VARYING_SLOT_CLIP_DIST0)
6074 length = ctx->num_output_clips + ctx->num_output_culls;
6075
6076 param_index = shader_io_get_unique_index(i);
6077
6078 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6079 }
6080
6081 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6082
6083 if (ctx->ac.chip_class >= GFX9) {
6084 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6085 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6086 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6087 LLVMConstInt(ctx->ac.i32, 24, false),
6088 LLVMConstInt(ctx->ac.i32, 4, false), false);
6089 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6090 LLVMBuildMul(ctx->ac.builder, wave_idx,
6091 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6092 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6093 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6094 }
6095
6096 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6097 LLVMValueRef dw_addr;
6098 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6099 int param_index;
6100 int length = 4;
6101
6102 if (!(ctx->output_mask & (1ull << i)))
6103 continue;
6104
6105 if (i == VARYING_SLOT_CLIP_DIST0)
6106 length = ctx->num_output_clips + ctx->num_output_culls;
6107
6108 param_index = shader_io_get_unique_index(i);
6109
6110 if (lds_base) {
6111 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
6112 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6113 "");
6114 }
6115 for (j = 0; j < length; j++) {
6116 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
6117 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
6118
6119 if (ctx->ac.chip_class >= GFX9) {
6120 ac_lds_store(&ctx->ac, dw_addr,
6121 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6122 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6123 } else {
6124 ac_build_buffer_store_dword(&ctx->ac,
6125 ctx->esgs_ring,
6126 out_val, 1,
6127 NULL, ctx->es2gs_offset,
6128 (4 * param_index + j) * 4,
6129 1, 1, true, true);
6130 }
6131 }
6132 }
6133 }
6134
6135 static void
6136 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6137 {
6138 LLVMValueRef vertex_id = ctx->rel_auto_id;
6139 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6140 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
6141 vertex_dw_stride, "");
6142
6143 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6144 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
6145 int length = 4;
6146
6147 if (!(ctx->output_mask & (1ull << i)))
6148 continue;
6149
6150 if (i == VARYING_SLOT_CLIP_DIST0)
6151 length = ctx->num_output_clips + ctx->num_output_culls;
6152 int param = shader_io_get_unique_index(i);
6153 mark_tess_output(ctx, false, param);
6154 if (length > 4)
6155 mark_tess_output(ctx, false, param + 1);
6156 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
6157 LLVMConstInt(ctx->ac.i32, param * 4, false),
6158 "");
6159 for (unsigned j = 0; j < length; j++) {
6160 ac_lds_store(&ctx->ac, dw_addr,
6161 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
6162 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
6163 }
6164 }
6165 }
6166
6167 struct ac_build_if_state
6168 {
6169 struct nir_to_llvm_context *ctx;
6170 LLVMValueRef condition;
6171 LLVMBasicBlockRef entry_block;
6172 LLVMBasicBlockRef true_block;
6173 LLVMBasicBlockRef false_block;
6174 LLVMBasicBlockRef merge_block;
6175 };
6176
6177 static LLVMBasicBlockRef
6178 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6179 {
6180 LLVMBasicBlockRef current_block;
6181 LLVMBasicBlockRef next_block;
6182 LLVMBasicBlockRef new_block;
6183
6184 /* get current basic block */
6185 current_block = LLVMGetInsertBlock(ctx->builder);
6186
6187 /* chqeck if there's another block after this one */
6188 next_block = LLVMGetNextBasicBlock(current_block);
6189 if (next_block) {
6190 /* insert the new block before the next block */
6191 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6192 }
6193 else {
6194 /* append new block after current block */
6195 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6196 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6197 }
6198 return new_block;
6199 }
6200
6201 static void
6202 ac_nir_build_if(struct ac_build_if_state *ifthen,
6203 struct nir_to_llvm_context *ctx,
6204 LLVMValueRef condition)
6205 {
6206 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
6207
6208 memset(ifthen, 0, sizeof *ifthen);
6209 ifthen->ctx = ctx;
6210 ifthen->condition = condition;
6211 ifthen->entry_block = block;
6212
6213 /* create endif/merge basic block for the phi functions */
6214 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6215
6216 /* create/insert true_block before merge_block */
6217 ifthen->true_block =
6218 LLVMInsertBasicBlockInContext(ctx->context,
6219 ifthen->merge_block,
6220 "if-true-block");
6221
6222 /* successive code goes into the true block */
6223 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
6224 }
6225
6226 /**
6227 * End a conditional.
6228 */
6229 static void
6230 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6231 {
6232 LLVMBuilderRef builder = ifthen->ctx->builder;
6233
6234 /* Insert branch to the merge block from current block */
6235 LLVMBuildBr(builder, ifthen->merge_block);
6236
6237 /*
6238 * Now patch in the various branch instructions.
6239 */
6240
6241 /* Insert the conditional branch instruction at the end of entry_block */
6242 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6243 if (ifthen->false_block) {
6244 /* we have an else clause */
6245 LLVMBuildCondBr(builder, ifthen->condition,
6246 ifthen->true_block, ifthen->false_block);
6247 }
6248 else {
6249 /* no else clause */
6250 LLVMBuildCondBr(builder, ifthen->condition,
6251 ifthen->true_block, ifthen->merge_block);
6252 }
6253
6254 /* Resume building code at end of the ifthen->merge_block */
6255 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6256 }
6257
6258 static void
6259 write_tess_factors(struct nir_to_llvm_context *ctx)
6260 {
6261 unsigned stride, outer_comps, inner_comps;
6262 struct ac_build_if_state if_ctx, inner_if_ctx;
6263 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6264 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6265 unsigned tess_inner_index, tess_outer_index;
6266 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6267 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6268 int i;
6269 emit_barrier(&ctx->ac, ctx->stage);
6270
6271 switch (ctx->options->key.tcs.primitive_mode) {
6272 case GL_ISOLINES:
6273 stride = 2;
6274 outer_comps = 2;
6275 inner_comps = 0;
6276 break;
6277 case GL_TRIANGLES:
6278 stride = 4;
6279 outer_comps = 3;
6280 inner_comps = 1;
6281 break;
6282 case GL_QUADS:
6283 stride = 6;
6284 outer_comps = 4;
6285 inner_comps = 2;
6286 break;
6287 default:
6288 return;
6289 }
6290
6291 ac_nir_build_if(&if_ctx, ctx,
6292 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6293 invocation_id, ctx->ac.i32_0, ""));
6294
6295 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6296 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6297
6298 mark_tess_output(ctx, true, tess_inner_index);
6299 mark_tess_output(ctx, true, tess_outer_index);
6300 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6301 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6302 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6303 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6304 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6305
6306 for (i = 0; i < 4; i++) {
6307 inner[i] = LLVMGetUndef(ctx->ac.i32);
6308 outer[i] = LLVMGetUndef(ctx->ac.i32);
6309 }
6310
6311 // LINES reverseal
6312 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6313 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6314 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6315 ctx->ac.i32_1, "");
6316 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6317 } else {
6318 for (i = 0; i < outer_comps; i++) {
6319 outer[i] = out[i] =
6320 ac_lds_load(&ctx->ac, lds_outer);
6321 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6322 ctx->ac.i32_1, "");
6323 }
6324 for (i = 0; i < inner_comps; i++) {
6325 inner[i] = out[outer_comps+i] =
6326 ac_lds_load(&ctx->ac, lds_inner);
6327 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6328 ctx->ac.i32_1, "");
6329 }
6330 }
6331
6332 /* Convert the outputs to vectors for stores. */
6333 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6334 vec1 = NULL;
6335
6336 if (stride > 4)
6337 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6338
6339
6340 buffer = ctx->hs_ring_tess_factor;
6341 tf_base = ctx->tess_factor_offset;
6342 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6343 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6344 unsigned tf_offset = 0;
6345
6346 if (ctx->options->chip_class <= VI) {
6347 ac_nir_build_if(&inner_if_ctx, ctx,
6348 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6349 rel_patch_id, ctx->ac.i32_0, ""));
6350
6351 /* Store the dynamic HS control word. */
6352 ac_build_buffer_store_dword(&ctx->ac, buffer,
6353 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6354 1, ctx->ac.i32_0, tf_base,
6355 0, 1, 0, true, false);
6356 tf_offset += 4;
6357
6358 ac_nir_build_endif(&inner_if_ctx);
6359 }
6360
6361 /* Store the tessellation factors. */
6362 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6363 MIN2(stride, 4), byteoffset, tf_base,
6364 tf_offset, 1, 0, true, false);
6365 if (vec1)
6366 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6367 stride - 4, byteoffset, tf_base,
6368 16 + tf_offset, 1, 0, true, false);
6369
6370 //store to offchip for TES to read - only if TES reads them
6371 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6372 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6373 LLVMValueRef tf_inner_offset;
6374 unsigned param_outer, param_inner;
6375
6376 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6377 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6378 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6379
6380 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6381 util_next_power_of_two(outer_comps));
6382
6383 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6384 outer_comps, tf_outer_offset,
6385 ctx->oc_lds, 0, 1, 0, true, false);
6386 if (inner_comps) {
6387 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6388 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6389 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6390
6391 inner_vec = inner_comps == 1 ? inner[0] :
6392 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6393 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6394 inner_comps, tf_inner_offset,
6395 ctx->oc_lds, 0, 1, 0, true, false);
6396 }
6397 }
6398 ac_nir_build_endif(&if_ctx);
6399 }
6400
6401 static void
6402 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6403 {
6404 write_tess_factors(ctx);
6405 }
6406
6407 static bool
6408 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6409 LLVMValueRef *color, unsigned index, bool is_last,
6410 struct ac_export_args *args)
6411 {
6412 /* Export */
6413 si_llvm_init_export_args(ctx, color,
6414 V_008DFC_SQ_EXP_MRT + index, args);
6415
6416 if (is_last) {
6417 args->valid_mask = 1; /* whether the EXEC mask is valid */
6418 args->done = 1; /* DONE bit */
6419 } else if (!args->enabled_channels)
6420 return false; /* unnecessary NULL export */
6421
6422 return true;
6423 }
6424
6425 static void
6426 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6427 LLVMValueRef depth, LLVMValueRef stencil,
6428 LLVMValueRef samplemask)
6429 {
6430 struct ac_export_args args;
6431
6432 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6433
6434 ac_build_export(&ctx->ac, &args);
6435 }
6436
6437 static void
6438 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6439 {
6440 unsigned index = 0;
6441 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6442 struct ac_export_args color_args[8];
6443
6444 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6445 LLVMValueRef values[4];
6446 bool last = false;
6447
6448 if (!(ctx->output_mask & (1ull << i)))
6449 continue;
6450
6451 if (i < FRAG_RESULT_DATA0)
6452 continue;
6453
6454 for (unsigned j = 0; j < 4; j++)
6455 values[j] = ac_to_float(&ctx->ac,
6456 radv_load_output(ctx, i, j));
6457
6458 if (!ctx->shader_info->info.ps.writes_z &&
6459 !ctx->shader_info->info.ps.writes_stencil &&
6460 !ctx->shader_info->info.ps.writes_sample_mask)
6461 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6462
6463 bool ret = si_export_mrt_color(ctx, values,
6464 i - FRAG_RESULT_DATA0,
6465 last, &color_args[index]);
6466 if (ret)
6467 index++;
6468 }
6469
6470 /* Process depth, stencil, samplemask. */
6471 if (ctx->shader_info->info.ps.writes_z) {
6472 depth = ac_to_float(&ctx->ac,
6473 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6474 }
6475 if (ctx->shader_info->info.ps.writes_stencil) {
6476 stencil = ac_to_float(&ctx->ac,
6477 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6478 }
6479 if (ctx->shader_info->info.ps.writes_sample_mask) {
6480 samplemask = ac_to_float(&ctx->ac,
6481 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6482 }
6483
6484 /* Export PS outputs. */
6485 for (unsigned i = 0; i < index; i++)
6486 ac_build_export(&ctx->ac, &color_args[i]);
6487
6488 if (depth || stencil || samplemask)
6489 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6490 else if (!index)
6491 ac_build_export_null(&ctx->ac);
6492 }
6493
6494 static void
6495 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6496 {
6497 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6498 }
6499
6500 static void
6501 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6502 LLVMValueRef *addrs)
6503 {
6504 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6505
6506 switch (ctx->stage) {
6507 case MESA_SHADER_VERTEX:
6508 if (ctx->options->key.vs.as_ls)
6509 handle_ls_outputs_post(ctx);
6510 else if (ctx->options->key.vs.as_es)
6511 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6512 else
6513 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6514 &ctx->shader_info->vs.outinfo);
6515 break;
6516 case MESA_SHADER_FRAGMENT:
6517 handle_fs_outputs_post(ctx);
6518 break;
6519 case MESA_SHADER_GEOMETRY:
6520 emit_gs_epilogue(ctx);
6521 break;
6522 case MESA_SHADER_TESS_CTRL:
6523 handle_tcs_outputs_post(ctx);
6524 break;
6525 case MESA_SHADER_TESS_EVAL:
6526 if (ctx->options->key.tes.as_es)
6527 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6528 else
6529 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6530 &ctx->shader_info->tes.outinfo);
6531 break;
6532 default:
6533 break;
6534 }
6535 }
6536
6537 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6538 {
6539 LLVMPassManagerRef passmgr;
6540 /* Create the pass manager */
6541 passmgr = LLVMCreateFunctionPassManagerForModule(
6542 ctx->module);
6543
6544 /* This pass should eliminate all the load and store instructions */
6545 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6546
6547 /* Add some optimization passes */
6548 LLVMAddScalarReplAggregatesPass(passmgr);
6549 LLVMAddLICMPass(passmgr);
6550 LLVMAddAggressiveDCEPass(passmgr);
6551 LLVMAddCFGSimplificationPass(passmgr);
6552 LLVMAddInstructionCombiningPass(passmgr);
6553
6554 /* Run the pass */
6555 LLVMInitializeFunctionPassManager(passmgr);
6556 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6557 LLVMFinalizeFunctionPassManager(passmgr);
6558
6559 LLVMDisposeBuilder(ctx->builder);
6560 LLVMDisposePassManager(passmgr);
6561 }
6562
6563 static void
6564 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6565 {
6566 struct ac_vs_output_info *outinfo;
6567
6568 switch (ctx->stage) {
6569 case MESA_SHADER_FRAGMENT:
6570 case MESA_SHADER_COMPUTE:
6571 case MESA_SHADER_TESS_CTRL:
6572 case MESA_SHADER_GEOMETRY:
6573 return;
6574 case MESA_SHADER_VERTEX:
6575 if (ctx->options->key.vs.as_ls ||
6576 ctx->options->key.vs.as_es)
6577 return;
6578 outinfo = &ctx->shader_info->vs.outinfo;
6579 break;
6580 case MESA_SHADER_TESS_EVAL:
6581 if (ctx->options->key.vs.as_es)
6582 return;
6583 outinfo = &ctx->shader_info->tes.outinfo;
6584 break;
6585 default:
6586 unreachable("Unhandled shader type");
6587 }
6588
6589 ac_optimize_vs_outputs(&ctx->ac,
6590 ctx->main_function,
6591 outinfo->vs_output_param_offset,
6592 VARYING_SLOT_MAX,
6593 &outinfo->param_exports);
6594 }
6595
6596 static void
6597 ac_setup_rings(struct nir_to_llvm_context *ctx)
6598 {
6599 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6600 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6601 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6602 }
6603
6604 if (ctx->is_gs_copy_shader) {
6605 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6606 }
6607 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6608 LLVMValueRef tmp;
6609 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6610 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6611
6612 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6613
6614 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6615 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6616 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6617 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6618 }
6619
6620 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6621 ctx->stage == MESA_SHADER_TESS_EVAL) {
6622 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6623 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6624 }
6625 }
6626
6627 static unsigned
6628 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6629 const struct nir_shader *nir)
6630 {
6631 switch (nir->info.stage) {
6632 case MESA_SHADER_TESS_CTRL:
6633 return chip_class >= CIK ? 128 : 64;
6634 case MESA_SHADER_GEOMETRY:
6635 return chip_class >= GFX9 ? 128 : 64;
6636 case MESA_SHADER_COMPUTE:
6637 break;
6638 default:
6639 return 0;
6640 }
6641
6642 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6643 nir->info.cs.local_size[1] *
6644 nir->info.cs.local_size[2];
6645 return max_workgroup_size;
6646 }
6647
6648 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6649 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6650 {
6651 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6652 LLVMConstInt(ctx->ac.i32, 8, false),
6653 LLVMConstInt(ctx->ac.i32, 8, false), false);
6654 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6655 ctx->ac.i32_0, "");
6656 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6657 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6658 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6659 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6660 }
6661
6662 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6663 {
6664 for(int i = 5; i >= 0; --i) {
6665 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6666 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6667 LLVMConstInt(ctx->ac.i32, 16, false), false);
6668 }
6669
6670 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6671 LLVMConstInt(ctx->ac.i32, 16, false),
6672 LLVMConstInt(ctx->ac.i32, 8, false), false);
6673 }
6674
6675 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6676 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6677 {
6678 struct ac_nir_context ctx = {};
6679 struct nir_function *func;
6680
6681 ctx.ac = *ac;
6682 ctx.abi = abi;
6683
6684 ctx.nctx = nctx;
6685 if (nctx)
6686 nctx->nir = &ctx;
6687
6688 ctx.stage = nir->info.stage;
6689
6690 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6691
6692 nir_foreach_variable(variable, &nir->outputs)
6693 handle_shader_output_decl(&ctx, nir, variable);
6694
6695 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6696 _mesa_key_pointer_equal);
6697 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6698 _mesa_key_pointer_equal);
6699 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6700 _mesa_key_pointer_equal);
6701
6702 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6703
6704 setup_locals(&ctx, func);
6705
6706 if (nir->info.stage == MESA_SHADER_COMPUTE)
6707 setup_shared(&ctx, nir);
6708
6709 visit_cf_list(&ctx, &func->impl->body);
6710 phi_post_pass(&ctx);
6711
6712 if (nir->info.stage != MESA_SHADER_COMPUTE)
6713 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6714 ctx.outputs);
6715
6716 free(ctx.locals);
6717 ralloc_free(ctx.defs);
6718 ralloc_free(ctx.phis);
6719 ralloc_free(ctx.vars);
6720
6721 if (nctx)
6722 nctx->nir = NULL;
6723 }
6724
6725 static
6726 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6727 struct nir_shader *const *shaders,
6728 int shader_count,
6729 struct ac_shader_variant_info *shader_info,
6730 const struct ac_nir_compiler_options *options)
6731 {
6732 struct nir_to_llvm_context ctx = {0};
6733 unsigned i;
6734 ctx.options = options;
6735 ctx.shader_info = shader_info;
6736 ctx.context = LLVMContextCreate();
6737 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6738
6739 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6740 options->family);
6741 ctx.ac.module = ctx.module;
6742 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6743
6744 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6745 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6746 LLVMSetDataLayout(ctx.module, data_layout_str);
6747 LLVMDisposeTargetData(data_layout);
6748 LLVMDisposeMessage(data_layout_str);
6749
6750 enum ac_float_mode float_mode =
6751 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6752 AC_FLOAT_MODE_DEFAULT;
6753
6754 ctx.builder = ac_create_builder(ctx.context, float_mode);
6755 ctx.ac.builder = ctx.builder;
6756
6757 memset(shader_info, 0, sizeof(*shader_info));
6758
6759 for(int i = 0; i < shader_count; ++i)
6760 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6761
6762 for (i = 0; i < AC_UD_MAX_SETS; i++)
6763 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6764 for (i = 0; i < AC_UD_MAX_UD; i++)
6765 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6766
6767 ctx.max_workgroup_size = 0;
6768 for (int i = 0; i < shader_count; ++i) {
6769 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6770 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6771 shaders[i]));
6772 }
6773
6774 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6775 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6776
6777 ctx.abi.inputs = &ctx.inputs[0];
6778 ctx.abi.emit_outputs = handle_shader_outputs_post;
6779 ctx.abi.emit_vertex = visit_emit_vertex;
6780 ctx.abi.load_ubo = radv_load_ubo;
6781 ctx.abi.load_ssbo = radv_load_ssbo;
6782 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6783 ctx.abi.load_resource = radv_load_resource;
6784 ctx.abi.clamp_shadow_reference = false;
6785
6786 if (shader_count >= 2)
6787 ac_init_exec_full_mask(&ctx.ac);
6788
6789 if (ctx.ac.chip_class == GFX9 &&
6790 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6791 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6792
6793 for(int i = 0; i < shader_count; ++i) {
6794 ctx.stage = shaders[i]->info.stage;
6795 ctx.output_mask = 0;
6796 ctx.tess_outputs_written = 0;
6797 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6798 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6799
6800 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6801 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6802 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6803 ctx.abi.load_inputs = load_gs_input;
6804 ctx.abi.emit_primitive = visit_end_primitive;
6805 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6806 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6807 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6808 ctx.abi.load_tess_varyings = load_tcs_varyings;
6809 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6810 ctx.abi.store_tcs_outputs = store_tcs_output;
6811 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6812 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6813 ctx.abi.load_tess_varyings = load_tes_input;
6814 ctx.abi.load_tess_coord = load_tess_coord;
6815 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6816 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6817 if (shader_info->info.vs.needs_instance_id) {
6818 if (ctx.options->key.vs.as_ls) {
6819 ctx.shader_info->vs.vgpr_comp_cnt =
6820 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6821 } else {
6822 ctx.shader_info->vs.vgpr_comp_cnt =
6823 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6824 }
6825 }
6826 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6827 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6828 ctx.abi.lookup_interp_param = lookup_interp_param;
6829 ctx.abi.load_sample_position = load_sample_position;
6830 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6831 }
6832
6833 if (i)
6834 emit_barrier(&ctx.ac, ctx.stage);
6835
6836 ac_setup_rings(&ctx);
6837
6838 LLVMBasicBlockRef merge_block;
6839 if (shader_count >= 2) {
6840 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6841 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6842 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6843
6844 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6845 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6846 LLVMConstInt(ctx.ac.i32, 8, false), false);
6847 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6848 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6849 thread_id, count, "");
6850 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6851
6852 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6853 }
6854
6855 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6856 handle_fs_inputs(&ctx, shaders[i]);
6857 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6858 handle_vs_inputs(&ctx, shaders[i]);
6859 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6860 prepare_gs_input_vgprs(&ctx);
6861
6862 nir_foreach_variable(variable, &shaders[i]->outputs)
6863 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6864
6865 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6866
6867 if (shader_count >= 2) {
6868 LLVMBuildBr(ctx.ac.builder, merge_block);
6869 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6870 }
6871
6872 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6873 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6874 shaders[i]->info.cull_distance_array_size > 4;
6875 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6876 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6877 shaders[i]->info.gs.vertices_out;
6878 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6879 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6880 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6881 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6882 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6883 }
6884 }
6885
6886 LLVMBuildRetVoid(ctx.builder);
6887
6888 if (options->dump_preoptir)
6889 ac_dump_module(ctx.module);
6890
6891 ac_llvm_finalize_module(&ctx);
6892
6893 if (shader_count == 1)
6894 ac_nir_eliminate_const_vs_outputs(&ctx);
6895
6896 return ctx.module;
6897 }
6898
6899 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6900 {
6901 unsigned *retval = (unsigned *)context;
6902 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6903 char *description = LLVMGetDiagInfoDescription(di);
6904
6905 if (severity == LLVMDSError) {
6906 *retval = 1;
6907 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6908 description);
6909 }
6910
6911 LLVMDisposeMessage(description);
6912 }
6913
6914 static unsigned ac_llvm_compile(LLVMModuleRef M,
6915 struct ac_shader_binary *binary,
6916 LLVMTargetMachineRef tm)
6917 {
6918 unsigned retval = 0;
6919 char *err;
6920 LLVMContextRef llvm_ctx;
6921 LLVMMemoryBufferRef out_buffer;
6922 unsigned buffer_size;
6923 const char *buffer_data;
6924 LLVMBool mem_err;
6925
6926 /* Setup Diagnostic Handler*/
6927 llvm_ctx = LLVMGetModuleContext(M);
6928
6929 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6930 &retval);
6931
6932 /* Compile IR*/
6933 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6934 &err, &out_buffer);
6935
6936 /* Process Errors/Warnings */
6937 if (mem_err) {
6938 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6939 free(err);
6940 retval = 1;
6941 goto out;
6942 }
6943
6944 /* Extract Shader Code*/
6945 buffer_size = LLVMGetBufferSize(out_buffer);
6946 buffer_data = LLVMGetBufferStart(out_buffer);
6947
6948 ac_elf_read(buffer_data, buffer_size, binary);
6949
6950 /* Clean up */
6951 LLVMDisposeMemoryBuffer(out_buffer);
6952
6953 out:
6954 return retval;
6955 }
6956
6957 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6958 LLVMModuleRef llvm_module,
6959 struct ac_shader_binary *binary,
6960 struct ac_shader_config *config,
6961 struct ac_shader_variant_info *shader_info,
6962 gl_shader_stage stage,
6963 bool dump_shader, bool supports_spill)
6964 {
6965 if (dump_shader)
6966 ac_dump_module(llvm_module);
6967
6968 memset(binary, 0, sizeof(*binary));
6969 int v = ac_llvm_compile(llvm_module, binary, tm);
6970 if (v) {
6971 fprintf(stderr, "compile failed\n");
6972 }
6973
6974 if (dump_shader)
6975 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6976
6977 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6978
6979 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6980 LLVMDisposeModule(llvm_module);
6981 LLVMContextDispose(ctx);
6982
6983 if (stage == MESA_SHADER_FRAGMENT) {
6984 shader_info->num_input_vgprs = 0;
6985 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6986 shader_info->num_input_vgprs += 2;
6987 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6988 shader_info->num_input_vgprs += 2;
6989 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6990 shader_info->num_input_vgprs += 2;
6991 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6992 shader_info->num_input_vgprs += 3;
6993 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6994 shader_info->num_input_vgprs += 2;
6995 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6996 shader_info->num_input_vgprs += 2;
6997 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6998 shader_info->num_input_vgprs += 2;
6999 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7000 shader_info->num_input_vgprs += 1;
7001 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7002 shader_info->num_input_vgprs += 1;
7003 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7004 shader_info->num_input_vgprs += 1;
7005 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7006 shader_info->num_input_vgprs += 1;
7007 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7008 shader_info->num_input_vgprs += 1;
7009 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7010 shader_info->num_input_vgprs += 1;
7011 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7012 shader_info->num_input_vgprs += 1;
7013 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7014 shader_info->num_input_vgprs += 1;
7015 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7016 shader_info->num_input_vgprs += 1;
7017 }
7018 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7019
7020 /* +3 for scratch wave offset and VCC */
7021 config->num_sgprs = MAX2(config->num_sgprs,
7022 shader_info->num_input_sgprs + 3);
7023
7024 /* Enable 64-bit and 16-bit denormals, because there is no performance
7025 * cost.
7026 *
7027 * If denormals are enabled, all floating-point output modifiers are
7028 * ignored.
7029 *
7030 * Don't enable denormals for 32-bit floats, because:
7031 * - Floating-point output modifiers would be ignored by the hw.
7032 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7033 * have to stop using those.
7034 * - SI & CI would be very slow.
7035 */
7036 config->float_mode |= V_00B028_FP_64_DENORMS;
7037 }
7038
7039 static void
7040 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7041 {
7042 switch (nir->info.stage) {
7043 case MESA_SHADER_COMPUTE:
7044 for (int i = 0; i < 3; ++i)
7045 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7046 break;
7047 case MESA_SHADER_FRAGMENT:
7048 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7049 break;
7050 case MESA_SHADER_GEOMETRY:
7051 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7052 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7053 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7054 shader_info->gs.invocations = nir->info.gs.invocations;
7055 break;
7056 case MESA_SHADER_TESS_EVAL:
7057 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7058 shader_info->tes.spacing = nir->info.tess.spacing;
7059 shader_info->tes.ccw = nir->info.tess.ccw;
7060 shader_info->tes.point_mode = nir->info.tess.point_mode;
7061 shader_info->tes.as_es = options->key.tes.as_es;
7062 break;
7063 case MESA_SHADER_TESS_CTRL:
7064 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7065 break;
7066 case MESA_SHADER_VERTEX:
7067 shader_info->vs.as_es = options->key.vs.as_es;
7068 shader_info->vs.as_ls = options->key.vs.as_ls;
7069 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7070 if (options->key.vs.as_ls)
7071 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7072 break;
7073 default:
7074 break;
7075 }
7076 }
7077
7078 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7079 struct ac_shader_binary *binary,
7080 struct ac_shader_config *config,
7081 struct ac_shader_variant_info *shader_info,
7082 struct nir_shader *const *nir,
7083 int nir_count,
7084 const struct ac_nir_compiler_options *options,
7085 bool dump_shader)
7086 {
7087
7088 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7089 options);
7090
7091 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7092 for (int i = 0; i < nir_count; ++i)
7093 ac_fill_shader_info(shader_info, nir[i], options);
7094
7095 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7096 if (options->chip_class == GFX9) {
7097 if (nir_count == 2 &&
7098 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7099 shader_info->gs.es_type = nir[0]->info.stage;
7100 }
7101 }
7102 }
7103
7104 static void
7105 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7106 {
7107 LLVMValueRef vtx_offset =
7108 LLVMBuildMul(ctx->builder, ctx->abi.vertex_id,
7109 LLVMConstInt(ctx->ac.i32, 4, false), "");
7110 int idx = 0;
7111
7112 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
7113 int length = 4;
7114 int slot = idx;
7115 int slot_inc = 1;
7116 if (!(ctx->output_mask & (1ull << i)))
7117 continue;
7118
7119 if (i == VARYING_SLOT_CLIP_DIST0) {
7120 /* unpack clip and cull from a single set of slots */
7121 length = ctx->num_output_clips + ctx->num_output_culls;
7122 if (length > 4)
7123 slot_inc = 2;
7124 }
7125
7126 for (unsigned j = 0; j < length; j++) {
7127 LLVMValueRef value, soffset;
7128
7129 soffset = LLVMConstInt(ctx->ac.i32,
7130 (slot * 4 + j) *
7131 ctx->gs_max_out_vertices * 16 * 4, false);
7132
7133 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7134 1, ctx->ac.i32_0,
7135 vtx_offset, soffset,
7136 0, 1, 1, true, false);
7137
7138 LLVMBuildStore(ctx->builder,
7139 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
7140 }
7141 idx += slot_inc;
7142 }
7143 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7144 }
7145
7146 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7147 struct nir_shader *geom_shader,
7148 struct ac_shader_binary *binary,
7149 struct ac_shader_config *config,
7150 struct ac_shader_variant_info *shader_info,
7151 const struct ac_nir_compiler_options *options,
7152 bool dump_shader)
7153 {
7154 struct nir_to_llvm_context ctx = {0};
7155 ctx.context = LLVMContextCreate();
7156 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7157 ctx.options = options;
7158 ctx.shader_info = shader_info;
7159
7160 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7161 options->family);
7162 ctx.ac.module = ctx.module;
7163
7164 ctx.is_gs_copy_shader = true;
7165 LLVMSetTarget(ctx.module, "amdgcn--");
7166
7167 enum ac_float_mode float_mode =
7168 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7169 AC_FLOAT_MODE_DEFAULT;
7170
7171 ctx.builder = ac_create_builder(ctx.context, float_mode);
7172 ctx.ac.builder = ctx.builder;
7173 ctx.stage = MESA_SHADER_VERTEX;
7174
7175 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7176
7177 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7178 ac_setup_rings(&ctx);
7179
7180 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7181 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7182
7183 struct ac_nir_context nir_ctx = {};
7184 nir_ctx.ac = ctx.ac;
7185 nir_ctx.abi = &ctx.abi;
7186
7187 nir_ctx.nctx = &ctx;
7188 ctx.nir = &nir_ctx;
7189
7190 nir_foreach_variable(variable, &geom_shader->outputs) {
7191 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7192 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7193 }
7194
7195 ac_gs_copy_shader_emit(&ctx);
7196
7197 ctx.nir = NULL;
7198
7199 LLVMBuildRetVoid(ctx.builder);
7200
7201 ac_llvm_finalize_module(&ctx);
7202
7203 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
7204 MESA_SHADER_VERTEX,
7205 dump_shader, options->supports_spill);
7206 }