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ac/radv: don't mark tess inner as used if we don't use it.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct radv_shader_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 };
131
132 static inline struct radv_shader_context *
133 radv_shader_context_from_abi(struct ac_shader_abi *abi)
134 {
135 struct radv_shader_context *ctx = NULL;
136 return container_of(abi, ctx, abi);
137 }
138
139 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
140 const nir_deref_var *deref,
141 enum ac_descriptor_type desc_type,
142 const nir_tex_instr *instr,
143 bool image, bool write);
144
145 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
146 {
147 return (index * 4) + chan;
148 }
149
150 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
151 {
152 /* handle patch indices separate */
153 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
154 return 0;
155 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
156 return 1;
157 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
158 return 2 + (slot - VARYING_SLOT_PATCH0);
159
160 if (slot == VARYING_SLOT_POS)
161 return 0;
162 if (slot == VARYING_SLOT_PSIZ)
163 return 1;
164 if (slot == VARYING_SLOT_CLIP_DIST0)
165 return 2;
166 /* 3 is reserved for clip dist as well */
167 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
168 return 4 + (slot - VARYING_SLOT_VAR0);
169 unreachable("illegal slot in get unique index\n");
170 }
171
172 static void set_llvm_calling_convention(LLVMValueRef func,
173 gl_shader_stage stage)
174 {
175 enum radeon_llvm_calling_convention calling_conv;
176
177 switch (stage) {
178 case MESA_SHADER_VERTEX:
179 case MESA_SHADER_TESS_EVAL:
180 calling_conv = RADEON_LLVM_AMDGPU_VS;
181 break;
182 case MESA_SHADER_GEOMETRY:
183 calling_conv = RADEON_LLVM_AMDGPU_GS;
184 break;
185 case MESA_SHADER_TESS_CTRL:
186 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
187 break;
188 case MESA_SHADER_FRAGMENT:
189 calling_conv = RADEON_LLVM_AMDGPU_PS;
190 break;
191 case MESA_SHADER_COMPUTE:
192 calling_conv = RADEON_LLVM_AMDGPU_CS;
193 break;
194 default:
195 unreachable("Unhandle shader type");
196 }
197
198 LLVMSetFunctionCallConv(func, calling_conv);
199 }
200
201 #define MAX_ARGS 23
202 struct arg_info {
203 LLVMTypeRef types[MAX_ARGS];
204 LLVMValueRef *assign[MAX_ARGS];
205 unsigned array_params_mask;
206 uint8_t count;
207 uint8_t sgpr_count;
208 uint8_t num_sgprs_used;
209 uint8_t num_vgprs_used;
210 };
211
212 enum ac_arg_regfile {
213 ARG_SGPR,
214 ARG_VGPR,
215 };
216
217 static void
218 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
219 LLVMValueRef *param_ptr)
220 {
221 assert(info->count < MAX_ARGS);
222
223 info->assign[info->count] = param_ptr;
224 info->types[info->count] = type;
225 info->count++;
226
227 if (regfile == ARG_SGPR) {
228 info->num_sgprs_used += ac_get_type_size(type) / 4;
229 info->sgpr_count++;
230 } else {
231 assert(regfile == ARG_VGPR);
232 info->num_vgprs_used += ac_get_type_size(type) / 4;
233 }
234 }
235
236 static inline void
237 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
238 {
239 info->array_params_mask |= (1 << info->count);
240 add_arg(info, ARG_SGPR, type, param_ptr);
241 }
242
243 static void assign_arguments(LLVMValueRef main_function,
244 struct arg_info *info)
245 {
246 unsigned i;
247 for (i = 0; i < info->count; i++) {
248 if (info->assign[i])
249 *info->assign[i] = LLVMGetParam(main_function, i);
250 }
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems,
257 struct arg_info *args,
258 unsigned max_workgroup_size,
259 bool unsafe_math)
260 {
261 LLVMTypeRef main_function_type, ret_type;
262 LLVMBasicBlockRef main_function_body;
263
264 if (num_return_elems)
265 ret_type = LLVMStructTypeInContext(ctx, return_types,
266 num_return_elems, true);
267 else
268 ret_type = LLVMVoidTypeInContext(ctx);
269
270 /* Setup the function */
271 main_function_type =
272 LLVMFunctionType(ret_type, args->types, args->count, 0);
273 LLVMValueRef main_function =
274 LLVMAddFunction(module, "main", main_function_type);
275 main_function_body =
276 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
277 LLVMPositionBuilderAtEnd(builder, main_function_body);
278
279 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
280 for (unsigned i = 0; i < args->sgpr_count; ++i) {
281 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
282
283 if (args->array_params_mask & (1 << i)) {
284 LLVMValueRef P = LLVMGetParam(main_function, i);
285 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
286 ac_add_attr_dereferenceable(P, UINT64_MAX);
287 }
288 }
289
290 if (max_workgroup_size) {
291 ac_llvm_add_target_dep_function_attr(main_function,
292 "amdgpu-max-work-group-size",
293 max_workgroup_size);
294 }
295 if (unsafe_math) {
296 /* These were copied from some LLVM test. */
297 LLVMAddTargetDependentFunctionAttr(main_function,
298 "less-precise-fpmad",
299 "true");
300 LLVMAddTargetDependentFunctionAttr(main_function,
301 "no-infs-fp-math",
302 "true");
303 LLVMAddTargetDependentFunctionAttr(main_function,
304 "no-nans-fp-math",
305 "true");
306 LLVMAddTargetDependentFunctionAttr(main_function,
307 "unsafe-fp-math",
308 "true");
309 LLVMAddTargetDependentFunctionAttr(main_function,
310 "no-signed-zeros-fp-math",
311 "true");
312 }
313 return main_function;
314 }
315
316 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
317 LLVMValueRef param, unsigned rshift,
318 unsigned bitwidth)
319 {
320 LLVMValueRef value = param;
321 if (rshift)
322 value = LLVMBuildLShr(ctx->builder, value,
323 LLVMConstInt(ctx->i32, rshift, false), "");
324
325 if (rshift + bitwidth < 32) {
326 unsigned mask = (1 << bitwidth) - 1;
327 value = LLVMBuildAnd(ctx->builder, value,
328 LLVMConstInt(ctx->i32, mask, false), "");
329 }
330 return value;
331 }
332
333 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
334 {
335 switch (ctx->stage) {
336 case MESA_SHADER_TESS_CTRL:
337 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
338 case MESA_SHADER_TESS_EVAL:
339 return ctx->tes_rel_patch_id;
340 break;
341 default:
342 unreachable("Illegal stage");
343 }
344 }
345
346 /* Tessellation shaders pass outputs to the next shader using LDS.
347 *
348 * LS outputs = TCS inputs
349 * TCS outputs = TES inputs
350 *
351 * The LDS layout is:
352 * - TCS inputs for patch 0
353 * - TCS inputs for patch 1
354 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
355 * - ...
356 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
357 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
358 * - TCS outputs for patch 1
359 * - Per-patch TCS outputs for patch 1
360 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
361 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
362 * - ...
363 *
364 * All three shaders VS(LS), TCS, TES share the same LDS space.
365 */
366 static LLVMValueRef
367 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
368 {
369 if (ctx->stage == MESA_SHADER_VERTEX)
370 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
371 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
372 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
373 else {
374 assert(0);
375 return NULL;
376 }
377 }
378
379 static LLVMValueRef
380 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
381 {
382 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
383 }
384
385 static LLVMValueRef
386 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
387 {
388 return LLVMBuildMul(ctx->ac.builder,
389 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
390 LLVMConstInt(ctx->ac.i32, 4, false), "");
391 }
392
393 static LLVMValueRef
394 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
395 {
396 return LLVMBuildMul(ctx->ac.builder,
397 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
398 LLVMConstInt(ctx->ac.i32, 4, false), "");
399 }
400
401 static LLVMValueRef
402 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
403 {
404 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
405 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
406
407 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
408 }
409
410 static LLVMValueRef
411 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
412 {
413 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
414 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
415 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
416
417 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
418 LLVMBuildMul(ctx->ac.builder, patch_stride,
419 rel_patch_id, ""),
420 "");
421 }
422
423 static LLVMValueRef
424 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
425 {
426 LLVMValueRef patch0_patch_data_offset =
427 get_tcs_out_patch0_patch_data_offset(ctx);
428 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
429 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
430
431 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
432 LLVMBuildMul(ctx->ac.builder, patch_stride,
433 rel_patch_id, ""),
434 "");
435 }
436
437 static void
438 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
439 uint32_t indirect_offset)
440 {
441 ud_info->sgpr_idx = *sgpr_idx;
442 ud_info->num_sgprs = num_sgprs;
443 ud_info->indirect = indirect_offset > 0;
444 ud_info->indirect_offset = indirect_offset;
445 *sgpr_idx += num_sgprs;
446 }
447
448 static void
449 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
450 uint8_t num_sgprs)
451 {
452 struct ac_userdata_info *ud_info =
453 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
454 assert(ud_info);
455
456 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
457 }
458
459 static void
460 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
461 uint32_t indirect_offset)
462 {
463 struct ac_userdata_info *ud_info =
464 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
465 assert(ud_info);
466
467 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
468 }
469
470 struct user_sgpr_info {
471 bool need_ring_offsets;
472 uint8_t sgpr_count;
473 bool indirect_all_descriptor_sets;
474 };
475
476 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
477 gl_shader_stage stage)
478 {
479 switch (stage) {
480 case MESA_SHADER_VERTEX:
481 if (ctx->shader_info->info.needs_multiview_view_index ||
482 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
483 return true;
484 break;
485 case MESA_SHADER_TESS_EVAL:
486 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
487 return true;
488 break;
489 case MESA_SHADER_GEOMETRY:
490 case MESA_SHADER_TESS_CTRL:
491 if (ctx->shader_info->info.needs_multiview_view_index)
492 return true;
493 break;
494 default:
495 break;
496 }
497 return false;
498 }
499
500 static uint8_t
501 count_vs_user_sgprs(struct radv_shader_context *ctx)
502 {
503 uint8_t count = 0;
504
505 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
506 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
507
508 return count;
509 }
510
511 static void allocate_user_sgprs(struct radv_shader_context *ctx,
512 gl_shader_stage stage,
513 bool has_previous_stage,
514 gl_shader_stage previous_stage,
515 bool needs_view_index,
516 struct user_sgpr_info *user_sgpr_info)
517 {
518 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
519
520 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
521 if (stage == MESA_SHADER_GEOMETRY ||
522 stage == MESA_SHADER_VERTEX ||
523 stage == MESA_SHADER_TESS_CTRL ||
524 stage == MESA_SHADER_TESS_EVAL ||
525 ctx->is_gs_copy_shader)
526 user_sgpr_info->need_ring_offsets = true;
527
528 if (stage == MESA_SHADER_FRAGMENT &&
529 ctx->shader_info->info.ps.needs_sample_positions)
530 user_sgpr_info->need_ring_offsets = true;
531
532 /* 2 user sgprs will nearly always be allocated for scratch/rings */
533 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
534 user_sgpr_info->sgpr_count += 2;
535 }
536
537 switch (stage) {
538 case MESA_SHADER_COMPUTE:
539 if (ctx->shader_info->info.cs.uses_grid_size)
540 user_sgpr_info->sgpr_count += 3;
541 break;
542 case MESA_SHADER_FRAGMENT:
543 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
544 break;
545 case MESA_SHADER_VERTEX:
546 if (!ctx->is_gs_copy_shader)
547 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
548 if (ctx->options->key.vs.as_ls)
549 user_sgpr_info->sgpr_count++;
550 break;
551 case MESA_SHADER_TESS_CTRL:
552 if (has_previous_stage) {
553 if (previous_stage == MESA_SHADER_VERTEX)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 user_sgpr_info->sgpr_count++;
556 }
557 user_sgpr_info->sgpr_count += 4;
558 break;
559 case MESA_SHADER_TESS_EVAL:
560 user_sgpr_info->sgpr_count += 1;
561 break;
562 case MESA_SHADER_GEOMETRY:
563 if (has_previous_stage) {
564 if (previous_stage == MESA_SHADER_VERTEX) {
565 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
566 } else {
567 user_sgpr_info->sgpr_count++;
568 }
569 }
570 user_sgpr_info->sgpr_count += 2;
571 break;
572 default:
573 break;
574 }
575
576 if (needs_view_index)
577 user_sgpr_info->sgpr_count++;
578
579 if (ctx->shader_info->info.loads_push_constants)
580 user_sgpr_info->sgpr_count += 2;
581
582 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
583 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
584
585 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
586 user_sgpr_info->sgpr_count += 2;
587 user_sgpr_info->indirect_all_descriptor_sets = true;
588 } else {
589 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
590 }
591 }
592
593 static void
594 declare_global_input_sgprs(struct radv_shader_context *ctx,
595 gl_shader_stage stage,
596 bool has_previous_stage,
597 gl_shader_stage previous_stage,
598 const struct user_sgpr_info *user_sgpr_info,
599 struct arg_info *args,
600 LLVMValueRef *desc_sets)
601 {
602 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
603 unsigned num_sets = ctx->options->layout ?
604 ctx->options->layout->num_sets : 0;
605 unsigned stage_mask = 1 << stage;
606
607 if (has_previous_stage)
608 stage_mask |= 1 << previous_stage;
609
610 /* 1 for each descriptor set */
611 if (!user_sgpr_info->indirect_all_descriptor_sets) {
612 for (unsigned i = 0; i < num_sets; ++i) {
613 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
614 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
615 add_array_arg(args, type,
616 &ctx->descriptor_sets[i]);
617 }
618 }
619 } else {
620 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
621 }
622
623 if (ctx->shader_info->info.loads_push_constants) {
624 /* 1 for push constants and dynamic descriptors */
625 add_array_arg(args, type, &ctx->abi.push_constants);
626 }
627 }
628
629 static void
630 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
631 gl_shader_stage stage,
632 bool has_previous_stage,
633 gl_shader_stage previous_stage,
634 struct arg_info *args)
635 {
636 if (!ctx->is_gs_copy_shader &&
637 (stage == MESA_SHADER_VERTEX ||
638 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
639 if (ctx->shader_info->info.vs.has_vertex_buffers) {
640 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
641 &ctx->vertex_buffers);
642 }
643 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
644 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
645 if (ctx->shader_info->info.vs.needs_draw_id) {
646 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
647 }
648 }
649 }
650
651 static void
652 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
653 {
654 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
655 if (!ctx->is_gs_copy_shader) {
656 if (ctx->options->key.vs.as_ls) {
657 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
658 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
659 } else {
660 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
661 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
662 }
663 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
664 }
665 }
666
667 static void
668 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
669 {
670 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
671 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
672 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
673 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
674 }
675
676 static void
677 set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
678 bool has_previous_stage, gl_shader_stage previous_stage,
679 const struct user_sgpr_info *user_sgpr_info,
680 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
681 {
682 unsigned num_sets = ctx->options->layout ?
683 ctx->options->layout->num_sets : 0;
684 unsigned stage_mask = 1 << stage;
685
686 if (has_previous_stage)
687 stage_mask |= 1 << previous_stage;
688
689 if (!user_sgpr_info->indirect_all_descriptor_sets) {
690 for (unsigned i = 0; i < num_sets; ++i) {
691 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
692 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
693 set_loc_desc(ctx, i, user_sgpr_idx, 0);
694 } else
695 ctx->descriptor_sets[i] = NULL;
696 }
697 } else {
698 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
699 user_sgpr_idx, 2);
700
701 for (unsigned i = 0; i < num_sets; ++i) {
702 if ((ctx->shader_info->info.desc_set_used_mask & (1 << i)) &&
703 ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
704 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
705 ctx->descriptor_sets[i] =
706 ac_build_load_to_sgpr(&ctx->ac,
707 desc_sets,
708 LLVMConstInt(ctx->ac.i32, i, false));
709
710 } else
711 ctx->descriptor_sets[i] = NULL;
712 }
713 ctx->shader_info->need_indirect_descriptor_sets = true;
714 }
715
716 if (ctx->shader_info->info.loads_push_constants) {
717 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
718 }
719 }
720
721 static void
722 set_vs_specific_input_locs(struct radv_shader_context *ctx,
723 gl_shader_stage stage, bool has_previous_stage,
724 gl_shader_stage previous_stage,
725 uint8_t *user_sgpr_idx)
726 {
727 if (!ctx->is_gs_copy_shader &&
728 (stage == MESA_SHADER_VERTEX ||
729 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
730 if (ctx->shader_info->info.vs.has_vertex_buffers) {
731 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
732 user_sgpr_idx, 2);
733 }
734
735 unsigned vs_num = 2;
736 if (ctx->shader_info->info.vs.needs_draw_id)
737 vs_num++;
738
739 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
740 user_sgpr_idx, vs_num);
741 }
742 }
743
744 static void create_function(struct radv_shader_context *ctx,
745 gl_shader_stage stage,
746 bool has_previous_stage,
747 gl_shader_stage previous_stage)
748 {
749 uint8_t user_sgpr_idx;
750 struct user_sgpr_info user_sgpr_info;
751 struct arg_info args = {};
752 LLVMValueRef desc_sets;
753 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
754 allocate_user_sgprs(ctx, stage, has_previous_stage,
755 previous_stage, needs_view_index, &user_sgpr_info);
756
757 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
758 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
759 &ctx->ring_offsets);
760 }
761
762 switch (stage) {
763 case MESA_SHADER_COMPUTE:
764 declare_global_input_sgprs(ctx, stage, has_previous_stage,
765 previous_stage, &user_sgpr_info,
766 &args, &desc_sets);
767
768 if (ctx->shader_info->info.cs.uses_grid_size) {
769 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
770 &ctx->abi.num_work_groups);
771 }
772
773 for (int i = 0; i < 3; i++) {
774 ctx->abi.workgroup_ids[i] = NULL;
775 if (ctx->shader_info->info.cs.uses_block_id[i]) {
776 add_arg(&args, ARG_SGPR, ctx->ac.i32,
777 &ctx->abi.workgroup_ids[i]);
778 }
779 }
780
781 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
782 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
783 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
784 &ctx->abi.local_invocation_ids);
785 break;
786 case MESA_SHADER_VERTEX:
787 declare_global_input_sgprs(ctx, stage, has_previous_stage,
788 previous_stage, &user_sgpr_info,
789 &args, &desc_sets);
790 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
791 previous_stage, &args);
792
793 if (needs_view_index)
794 add_arg(&args, ARG_SGPR, ctx->ac.i32,
795 &ctx->abi.view_index);
796 if (ctx->options->key.vs.as_es)
797 add_arg(&args, ARG_SGPR, ctx->ac.i32,
798 &ctx->es2gs_offset);
799 else if (ctx->options->key.vs.as_ls)
800 add_arg(&args, ARG_SGPR, ctx->ac.i32,
801 &ctx->ls_out_layout);
802
803 declare_vs_input_vgprs(ctx, &args);
804 break;
805 case MESA_SHADER_TESS_CTRL:
806 if (has_previous_stage) {
807 // First 6 system regs
808 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
809 add_arg(&args, ARG_SGPR, ctx->ac.i32,
810 &ctx->merged_wave_info);
811 add_arg(&args, ARG_SGPR, ctx->ac.i32,
812 &ctx->tess_factor_offset);
813
814 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
815 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
816 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
817
818 declare_global_input_sgprs(ctx, stage,
819 has_previous_stage,
820 previous_stage,
821 &user_sgpr_info, &args,
822 &desc_sets);
823 declare_vs_specific_input_sgprs(ctx, stage,
824 has_previous_stage,
825 previous_stage, &args);
826
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->ls_out_layout);
829
830 add_arg(&args, ARG_SGPR, ctx->ac.i32,
831 &ctx->tcs_offchip_layout);
832 add_arg(&args, ARG_SGPR, ctx->ac.i32,
833 &ctx->tcs_out_offsets);
834 add_arg(&args, ARG_SGPR, ctx->ac.i32,
835 &ctx->tcs_out_layout);
836 add_arg(&args, ARG_SGPR, ctx->ac.i32,
837 &ctx->tcs_in_layout);
838 if (needs_view_index)
839 add_arg(&args, ARG_SGPR, ctx->ac.i32,
840 &ctx->abi.view_index);
841
842 add_arg(&args, ARG_VGPR, ctx->ac.i32,
843 &ctx->abi.tcs_patch_id);
844 add_arg(&args, ARG_VGPR, ctx->ac.i32,
845 &ctx->abi.tcs_rel_ids);
846
847 declare_vs_input_vgprs(ctx, &args);
848 } else {
849 declare_global_input_sgprs(ctx, stage,
850 has_previous_stage,
851 previous_stage,
852 &user_sgpr_info, &args,
853 &desc_sets);
854
855 add_arg(&args, ARG_SGPR, ctx->ac.i32,
856 &ctx->tcs_offchip_layout);
857 add_arg(&args, ARG_SGPR, ctx->ac.i32,
858 &ctx->tcs_out_offsets);
859 add_arg(&args, ARG_SGPR, ctx->ac.i32,
860 &ctx->tcs_out_layout);
861 add_arg(&args, ARG_SGPR, ctx->ac.i32,
862 &ctx->tcs_in_layout);
863 if (needs_view_index)
864 add_arg(&args, ARG_SGPR, ctx->ac.i32,
865 &ctx->abi.view_index);
866
867 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
868 add_arg(&args, ARG_SGPR, ctx->ac.i32,
869 &ctx->tess_factor_offset);
870 add_arg(&args, ARG_VGPR, ctx->ac.i32,
871 &ctx->abi.tcs_patch_id);
872 add_arg(&args, ARG_VGPR, ctx->ac.i32,
873 &ctx->abi.tcs_rel_ids);
874 }
875 break;
876 case MESA_SHADER_TESS_EVAL:
877 declare_global_input_sgprs(ctx, stage, has_previous_stage,
878 previous_stage, &user_sgpr_info,
879 &args, &desc_sets);
880
881 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
882 if (needs_view_index)
883 add_arg(&args, ARG_SGPR, ctx->ac.i32,
884 &ctx->abi.view_index);
885
886 if (ctx->options->key.tes.as_es) {
887 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
888 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
889 add_arg(&args, ARG_SGPR, ctx->ac.i32,
890 &ctx->es2gs_offset);
891 } else {
892 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
893 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
894 }
895 declare_tes_input_vgprs(ctx, &args);
896 break;
897 case MESA_SHADER_GEOMETRY:
898 if (has_previous_stage) {
899 // First 6 system regs
900 add_arg(&args, ARG_SGPR, ctx->ac.i32,
901 &ctx->gs2vs_offset);
902 add_arg(&args, ARG_SGPR, ctx->ac.i32,
903 &ctx->merged_wave_info);
904 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
905
906 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
907 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
908 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
909
910 declare_global_input_sgprs(ctx, stage,
911 has_previous_stage,
912 previous_stage,
913 &user_sgpr_info, &args,
914 &desc_sets);
915
916 if (previous_stage == MESA_SHADER_TESS_EVAL) {
917 add_arg(&args, ARG_SGPR, ctx->ac.i32,
918 &ctx->tcs_offchip_layout);
919 } else {
920 declare_vs_specific_input_sgprs(ctx, stage,
921 has_previous_stage,
922 previous_stage,
923 &args);
924 }
925
926 add_arg(&args, ARG_SGPR, ctx->ac.i32,
927 &ctx->gsvs_ring_stride);
928 add_arg(&args, ARG_SGPR, ctx->ac.i32,
929 &ctx->gsvs_num_entries);
930 if (needs_view_index)
931 add_arg(&args, ARG_SGPR, ctx->ac.i32,
932 &ctx->abi.view_index);
933
934 add_arg(&args, ARG_VGPR, ctx->ac.i32,
935 &ctx->gs_vtx_offset[0]);
936 add_arg(&args, ARG_VGPR, ctx->ac.i32,
937 &ctx->gs_vtx_offset[2]);
938 add_arg(&args, ARG_VGPR, ctx->ac.i32,
939 &ctx->abi.gs_prim_id);
940 add_arg(&args, ARG_VGPR, ctx->ac.i32,
941 &ctx->abi.gs_invocation_id);
942 add_arg(&args, ARG_VGPR, ctx->ac.i32,
943 &ctx->gs_vtx_offset[4]);
944
945 if (previous_stage == MESA_SHADER_VERTEX) {
946 declare_vs_input_vgprs(ctx, &args);
947 } else {
948 declare_tes_input_vgprs(ctx, &args);
949 }
950 } else {
951 declare_global_input_sgprs(ctx, stage,
952 has_previous_stage,
953 previous_stage,
954 &user_sgpr_info, &args,
955 &desc_sets);
956
957 add_arg(&args, ARG_SGPR, ctx->ac.i32,
958 &ctx->gsvs_ring_stride);
959 add_arg(&args, ARG_SGPR, ctx->ac.i32,
960 &ctx->gsvs_num_entries);
961 if (needs_view_index)
962 add_arg(&args, ARG_SGPR, ctx->ac.i32,
963 &ctx->abi.view_index);
964
965 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
966 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
967 add_arg(&args, ARG_VGPR, ctx->ac.i32,
968 &ctx->gs_vtx_offset[0]);
969 add_arg(&args, ARG_VGPR, ctx->ac.i32,
970 &ctx->gs_vtx_offset[1]);
971 add_arg(&args, ARG_VGPR, ctx->ac.i32,
972 &ctx->abi.gs_prim_id);
973 add_arg(&args, ARG_VGPR, ctx->ac.i32,
974 &ctx->gs_vtx_offset[2]);
975 add_arg(&args, ARG_VGPR, ctx->ac.i32,
976 &ctx->gs_vtx_offset[3]);
977 add_arg(&args, ARG_VGPR, ctx->ac.i32,
978 &ctx->gs_vtx_offset[4]);
979 add_arg(&args, ARG_VGPR, ctx->ac.i32,
980 &ctx->gs_vtx_offset[5]);
981 add_arg(&args, ARG_VGPR, ctx->ac.i32,
982 &ctx->abi.gs_invocation_id);
983 }
984 break;
985 case MESA_SHADER_FRAGMENT:
986 declare_global_input_sgprs(ctx, stage, has_previous_stage,
987 previous_stage, &user_sgpr_info,
988 &args, &desc_sets);
989
990 if (ctx->shader_info->info.ps.needs_sample_positions)
991 add_arg(&args, ARG_SGPR, ctx->ac.i32,
992 &ctx->sample_pos_offset);
993
994 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
995 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
996 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
997 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
998 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
999 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
1000 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
1001 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
1002 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1003 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1004 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1005 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1006 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1007 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1008 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1009 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1010 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1011 break;
1012 default:
1013 unreachable("Shader stage not implemented");
1014 }
1015
1016 ctx->main_function = create_llvm_function(
1017 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1018 ctx->max_workgroup_size,
1019 ctx->options->unsafe_math);
1020 set_llvm_calling_convention(ctx->main_function, stage);
1021
1022
1023 ctx->shader_info->num_input_vgprs = 0;
1024 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1025
1026 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1027
1028 if (ctx->stage != MESA_SHADER_FRAGMENT)
1029 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1030
1031 assign_arguments(ctx->main_function, &args);
1032
1033 user_sgpr_idx = 0;
1034
1035 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1036 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1037 &user_sgpr_idx, 2);
1038 if (ctx->options->supports_spill) {
1039 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1040 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1041 NULL, 0, AC_FUNC_ATTR_READNONE);
1042 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1043 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1044 }
1045 }
1046
1047 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1048 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1049 if (has_previous_stage)
1050 user_sgpr_idx = 0;
1051
1052 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1053 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1054
1055 switch (stage) {
1056 case MESA_SHADER_COMPUTE:
1057 if (ctx->shader_info->info.cs.uses_grid_size) {
1058 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1059 &user_sgpr_idx, 3);
1060 }
1061 break;
1062 case MESA_SHADER_VERTEX:
1063 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1064 previous_stage, &user_sgpr_idx);
1065 if (ctx->abi.view_index)
1066 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1067 if (ctx->options->key.vs.as_ls) {
1068 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1069 &user_sgpr_idx, 1);
1070 }
1071 break;
1072 case MESA_SHADER_TESS_CTRL:
1073 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1074 previous_stage, &user_sgpr_idx);
1075 if (has_previous_stage)
1076 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1077 &user_sgpr_idx, 1);
1078 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1079 if (ctx->abi.view_index)
1080 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1081 break;
1082 case MESA_SHADER_TESS_EVAL:
1083 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1084 if (ctx->abi.view_index)
1085 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1086 break;
1087 case MESA_SHADER_GEOMETRY:
1088 if (has_previous_stage) {
1089 if (previous_stage == MESA_SHADER_VERTEX)
1090 set_vs_specific_input_locs(ctx, stage,
1091 has_previous_stage,
1092 previous_stage,
1093 &user_sgpr_idx);
1094 else
1095 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1096 &user_sgpr_idx, 1);
1097 }
1098 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1099 &user_sgpr_idx, 2);
1100 if (ctx->abi.view_index)
1101 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1102 break;
1103 case MESA_SHADER_FRAGMENT:
1104 if (ctx->shader_info->info.ps.needs_sample_positions) {
1105 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1106 &user_sgpr_idx, 1);
1107 }
1108 break;
1109 default:
1110 unreachable("Shader stage not implemented");
1111 }
1112
1113 if (stage == MESA_SHADER_TESS_CTRL ||
1114 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_ls) ||
1115 /* GFX9 has the ESGS ring buffer in LDS. */
1116 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1117 ac_declare_lds_as_pointer(&ctx->ac);
1118 }
1119
1120 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1121 }
1122
1123 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1124 LLVMValueRef value, unsigned count)
1125 {
1126 unsigned num_components = ac_get_llvm_num_components(value);
1127 if (count == num_components)
1128 return value;
1129
1130 LLVMValueRef masks[] = {
1131 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1132 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1133
1134 if (count == 1)
1135 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1136 "");
1137
1138 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1139 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1140 }
1141
1142 static void
1143 build_store_values_extended(struct ac_llvm_context *ac,
1144 LLVMValueRef *values,
1145 unsigned value_count,
1146 unsigned value_stride,
1147 LLVMValueRef vec)
1148 {
1149 LLVMBuilderRef builder = ac->builder;
1150 unsigned i;
1151
1152 for (i = 0; i < value_count; i++) {
1153 LLVMValueRef ptr = values[i * value_stride];
1154 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1155 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1156 LLVMBuildStore(builder, value, ptr);
1157 }
1158 }
1159
1160 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1161 const nir_ssa_def *def)
1162 {
1163 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1164 if (def->num_components > 1) {
1165 type = LLVMVectorType(type, def->num_components);
1166 }
1167 return type;
1168 }
1169
1170 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1171 {
1172 assert(src.is_ssa);
1173 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1174 return (LLVMValueRef)entry->data;
1175 }
1176
1177 static LLVMValueRef
1178 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1179 {
1180 LLVMValueRef ptr = get_src(ctx, src);
1181 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1182 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1183
1184 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1185 LLVMPointerType(ctx->ac.i32, addr_space), "");
1186 }
1187
1188 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1189 const struct nir_block *b)
1190 {
1191 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1192 return (LLVMBasicBlockRef)entry->data;
1193 }
1194
1195 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1196 nir_alu_src src,
1197 unsigned num_components)
1198 {
1199 LLVMValueRef value = get_src(ctx, src.src);
1200 bool need_swizzle = false;
1201
1202 assert(value);
1203 LLVMTypeRef type = LLVMTypeOf(value);
1204 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1205 ? LLVMGetVectorSize(type)
1206 : 1;
1207
1208 for (unsigned i = 0; i < num_components; ++i) {
1209 assert(src.swizzle[i] < src_components);
1210 if (src.swizzle[i] != i)
1211 need_swizzle = true;
1212 }
1213
1214 if (need_swizzle || num_components != src_components) {
1215 LLVMValueRef masks[] = {
1216 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1217 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1218 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1219 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1220
1221 if (src_components > 1 && num_components == 1) {
1222 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1223 masks[0], "");
1224 } else if (src_components == 1 && num_components > 1) {
1225 LLVMValueRef values[] = {value, value, value, value};
1226 value = ac_build_gather_values(&ctx->ac, values, num_components);
1227 } else {
1228 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1229 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1230 swizzle, "");
1231 }
1232 }
1233 assert(!src.negate);
1234 assert(!src.abs);
1235 return value;
1236 }
1237
1238 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1239 LLVMIntPredicate pred, LLVMValueRef src0,
1240 LLVMValueRef src1)
1241 {
1242 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1243 return LLVMBuildSelect(ctx->builder, result,
1244 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1245 ctx->i32_0, "");
1246 }
1247
1248 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1249 LLVMRealPredicate pred, LLVMValueRef src0,
1250 LLVMValueRef src1)
1251 {
1252 LLVMValueRef result;
1253 src0 = ac_to_float(ctx, src0);
1254 src1 = ac_to_float(ctx, src1);
1255 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1256 return LLVMBuildSelect(ctx->builder, result,
1257 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1258 ctx->i32_0, "");
1259 }
1260
1261 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1262 const char *intrin,
1263 LLVMTypeRef result_type,
1264 LLVMValueRef src0)
1265 {
1266 char name[64];
1267 LLVMValueRef params[] = {
1268 ac_to_float(ctx, src0),
1269 };
1270
1271 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1272 ac_get_elem_bits(ctx, result_type));
1273 assert(length < sizeof(name));
1274 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1275 }
1276
1277 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1278 const char *intrin,
1279 LLVMTypeRef result_type,
1280 LLVMValueRef src0, LLVMValueRef src1)
1281 {
1282 char name[64];
1283 LLVMValueRef params[] = {
1284 ac_to_float(ctx, src0),
1285 ac_to_float(ctx, src1),
1286 };
1287
1288 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1289 ac_get_elem_bits(ctx, result_type));
1290 assert(length < sizeof(name));
1291 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1292 }
1293
1294 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1295 const char *intrin,
1296 LLVMTypeRef result_type,
1297 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1298 {
1299 char name[64];
1300 LLVMValueRef params[] = {
1301 ac_to_float(ctx, src0),
1302 ac_to_float(ctx, src1),
1303 ac_to_float(ctx, src2),
1304 };
1305
1306 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1307 ac_get_elem_bits(ctx, result_type));
1308 assert(length < sizeof(name));
1309 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1310 }
1311
1312 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1313 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1314 {
1315 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1316 ctx->i32_0, "");
1317 return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
1318 ac_to_integer(ctx, src2), "");
1319 }
1320
1321 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1322 LLVMIntPredicate pred,
1323 LLVMValueRef src0, LLVMValueRef src1)
1324 {
1325 return LLVMBuildSelect(ctx->builder,
1326 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1327 src0,
1328 src1, "");
1329
1330 }
1331 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1332 LLVMValueRef src0)
1333 {
1334 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1335 LLVMBuildNeg(ctx->builder, src0, ""));
1336 }
1337
1338 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1339 LLVMValueRef src0,
1340 unsigned bitsize)
1341 {
1342 LLVMValueRef cmp, val, zero, one;
1343 LLVMTypeRef type;
1344
1345 if (bitsize == 32) {
1346 type = ctx->f32;
1347 zero = ctx->f32_0;
1348 one = ctx->f32_1;
1349 } else {
1350 type = ctx->f64;
1351 zero = ctx->f64_0;
1352 one = ctx->f64_1;
1353 }
1354
1355 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1356 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1357 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1358 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1359 return val;
1360 }
1361
1362 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1363 LLVMValueRef src0, unsigned bitsize)
1364 {
1365 LLVMValueRef cmp, val, zero, one;
1366 LLVMTypeRef type;
1367
1368 if (bitsize == 32) {
1369 type = ctx->i32;
1370 zero = ctx->i32_0;
1371 one = ctx->i32_1;
1372 } else {
1373 type = ctx->i64;
1374 zero = ctx->i64_0;
1375 one = ctx->i64_1;
1376 }
1377
1378 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1379 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1380 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1381 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1382 return val;
1383 }
1384
1385 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1386 LLVMValueRef src0, unsigned bitsize)
1387 {
1388 LLVMTypeRef type;
1389 char *intr;
1390
1391 if (bitsize == 32) {
1392 intr = "llvm.floor.f32";
1393 type = ctx->f32;
1394 } else {
1395 intr = "llvm.floor.f64";
1396 type = ctx->f64;
1397 }
1398
1399 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1400 LLVMValueRef params[] = {
1401 fsrc0,
1402 };
1403 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1404 AC_FUNC_ATTR_READNONE);
1405 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1406 }
1407
1408 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1409 const char *intrin,
1410 LLVMValueRef src0, LLVMValueRef src1)
1411 {
1412 LLVMTypeRef ret_type;
1413 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1414 LLVMValueRef res;
1415 LLVMValueRef params[] = { src0, src1 };
1416 ret_type = LLVMStructTypeInContext(ctx->context, types,
1417 2, true);
1418
1419 res = ac_build_intrinsic(ctx, intrin, ret_type,
1420 params, 2, AC_FUNC_ATTR_READNONE);
1421
1422 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1423 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1424 return res;
1425 }
1426
1427 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1428 LLVMValueRef src0)
1429 {
1430 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1431 }
1432
1433 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1434 LLVMValueRef src0)
1435 {
1436 src0 = ac_to_float(ctx, src0);
1437 return LLVMBuildSExt(ctx->builder,
1438 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1439 ctx->i32, "");
1440 }
1441
1442 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1443 LLVMValueRef src0,
1444 unsigned bitsize)
1445 {
1446 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1447
1448 if (bitsize == 32)
1449 return result;
1450
1451 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1452 }
1453
1454 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1455 LLVMValueRef src0)
1456 {
1457 return LLVMBuildSExt(ctx->builder,
1458 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1459 ctx->i32, "");
1460 }
1461
1462 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1463 LLVMValueRef src0)
1464 {
1465 LLVMValueRef result;
1466 LLVMValueRef cond = NULL;
1467
1468 src0 = ac_to_float(ctx, src0);
1469 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1470
1471 if (ctx->chip_class >= VI) {
1472 LLVMValueRef args[2];
1473 /* Check if the result is a denormal - and flush to 0 if so. */
1474 args[0] = result;
1475 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1476 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1477 }
1478
1479 /* need to convert back up to f32 */
1480 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1481
1482 if (ctx->chip_class >= VI)
1483 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1484 else {
1485 /* for SI/CIK */
1486 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1487 * so compare the result and flush to 0 if it's smaller.
1488 */
1489 LLVMValueRef temp, cond2;
1490 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1491 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1492 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1493 temp, "");
1494 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1495 temp, ctx->f32_0, "");
1496 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1497 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1498 }
1499 return result;
1500 }
1501
1502 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1503 LLVMValueRef src0, LLVMValueRef src1)
1504 {
1505 LLVMValueRef dst64, result;
1506 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1507 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1508
1509 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1510 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1511 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1512 return result;
1513 }
1514
1515 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1516 LLVMValueRef src0, LLVMValueRef src1)
1517 {
1518 LLVMValueRef dst64, result;
1519 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1520 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1521
1522 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1523 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1524 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1525 return result;
1526 }
1527
1528 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1529 bool is_signed,
1530 const LLVMValueRef srcs[3])
1531 {
1532 LLVMValueRef result;
1533 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1534
1535 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1536 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1537 return result;
1538 }
1539
1540 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1541 LLVMValueRef src0, LLVMValueRef src1,
1542 LLVMValueRef src2, LLVMValueRef src3)
1543 {
1544 LLVMValueRef bfi_args[3], result;
1545
1546 bfi_args[0] = LLVMBuildShl(ctx->builder,
1547 LLVMBuildSub(ctx->builder,
1548 LLVMBuildShl(ctx->builder,
1549 ctx->i32_1,
1550 src3, ""),
1551 ctx->i32_1, ""),
1552 src2, "");
1553 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1554 bfi_args[2] = src0;
1555
1556 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1557
1558 /* Calculate:
1559 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1560 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1561 */
1562 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1563 LLVMBuildAnd(ctx->builder, bfi_args[0],
1564 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1565
1566 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1567 return result;
1568 }
1569
1570 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1571 LLVMValueRef src0)
1572 {
1573 LLVMValueRef comp[2];
1574
1575 src0 = ac_to_float(ctx, src0);
1576 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1577 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1578
1579 return ac_build_cvt_pkrtz_f16(ctx, comp);
1580 }
1581
1582 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1583 LLVMValueRef src0)
1584 {
1585 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1586 LLVMValueRef temps[2], result, val;
1587 int i;
1588
1589 for (i = 0; i < 2; i++) {
1590 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1591 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1592 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1593 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1594 }
1595
1596 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1597 ctx->i32_0, "");
1598 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1599 ctx->i32_1, "");
1600 return result;
1601 }
1602
1603 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1604 nir_op op,
1605 LLVMValueRef src0)
1606 {
1607 unsigned mask;
1608 int idx;
1609 LLVMValueRef result;
1610
1611 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1612 mask = AC_TID_MASK_LEFT;
1613 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1614 mask = AC_TID_MASK_TOP;
1615 else
1616 mask = AC_TID_MASK_TOP_LEFT;
1617
1618 /* for DDX we want to next X pixel, DDY next Y pixel. */
1619 if (op == nir_op_fddx_fine ||
1620 op == nir_op_fddx_coarse ||
1621 op == nir_op_fddx)
1622 idx = 1;
1623 else
1624 idx = 2;
1625
1626 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1627 return result;
1628 }
1629
1630 /*
1631 * this takes an I,J coordinate pair,
1632 * and works out the X and Y derivatives.
1633 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1634 */
1635 static LLVMValueRef emit_ddxy_interp(
1636 struct ac_nir_context *ctx,
1637 LLVMValueRef interp_ij)
1638 {
1639 LLVMValueRef result[4], a;
1640 unsigned i;
1641
1642 for (i = 0; i < 2; i++) {
1643 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1644 LLVMConstInt(ctx->ac.i32, i, false), "");
1645 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1646 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1647 }
1648 return ac_build_gather_values(&ctx->ac, result, 4);
1649 }
1650
1651 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1652 {
1653 LLVMValueRef src[4], result = NULL;
1654 unsigned num_components = instr->dest.dest.ssa.num_components;
1655 unsigned src_components;
1656 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1657
1658 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1659 switch (instr->op) {
1660 case nir_op_vec2:
1661 case nir_op_vec3:
1662 case nir_op_vec4:
1663 src_components = 1;
1664 break;
1665 case nir_op_pack_half_2x16:
1666 src_components = 2;
1667 break;
1668 case nir_op_unpack_half_2x16:
1669 src_components = 1;
1670 break;
1671 default:
1672 src_components = num_components;
1673 break;
1674 }
1675 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1676 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1677
1678 switch (instr->op) {
1679 case nir_op_fmov:
1680 case nir_op_imov:
1681 result = src[0];
1682 break;
1683 case nir_op_fneg:
1684 src[0] = ac_to_float(&ctx->ac, src[0]);
1685 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1686 break;
1687 case nir_op_ineg:
1688 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1689 break;
1690 case nir_op_inot:
1691 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1692 break;
1693 case nir_op_iadd:
1694 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1695 break;
1696 case nir_op_fadd:
1697 src[0] = ac_to_float(&ctx->ac, src[0]);
1698 src[1] = ac_to_float(&ctx->ac, src[1]);
1699 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1700 break;
1701 case nir_op_fsub:
1702 src[0] = ac_to_float(&ctx->ac, src[0]);
1703 src[1] = ac_to_float(&ctx->ac, src[1]);
1704 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_isub:
1707 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1708 break;
1709 case nir_op_imul:
1710 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1711 break;
1712 case nir_op_imod:
1713 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1714 break;
1715 case nir_op_umod:
1716 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1717 break;
1718 case nir_op_fmod:
1719 src[0] = ac_to_float(&ctx->ac, src[0]);
1720 src[1] = ac_to_float(&ctx->ac, src[1]);
1721 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1722 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1723 ac_to_float_type(&ctx->ac, def_type), result);
1724 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1725 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1726 break;
1727 case nir_op_frem:
1728 src[0] = ac_to_float(&ctx->ac, src[0]);
1729 src[1] = ac_to_float(&ctx->ac, src[1]);
1730 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1731 break;
1732 case nir_op_irem:
1733 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1734 break;
1735 case nir_op_idiv:
1736 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1737 break;
1738 case nir_op_udiv:
1739 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1740 break;
1741 case nir_op_fmul:
1742 src[0] = ac_to_float(&ctx->ac, src[0]);
1743 src[1] = ac_to_float(&ctx->ac, src[1]);
1744 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1745 break;
1746 case nir_op_frcp:
1747 src[0] = ac_to_float(&ctx->ac, src[0]);
1748 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1749 src[0]);
1750 break;
1751 case nir_op_iand:
1752 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1753 break;
1754 case nir_op_ior:
1755 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1756 break;
1757 case nir_op_ixor:
1758 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1759 break;
1760 case nir_op_ishl:
1761 result = LLVMBuildShl(ctx->ac.builder, src[0],
1762 LLVMBuildZExt(ctx->ac.builder, src[1],
1763 LLVMTypeOf(src[0]), ""),
1764 "");
1765 break;
1766 case nir_op_ishr:
1767 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1768 LLVMBuildZExt(ctx->ac.builder, src[1],
1769 LLVMTypeOf(src[0]), ""),
1770 "");
1771 break;
1772 case nir_op_ushr:
1773 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1774 LLVMBuildZExt(ctx->ac.builder, src[1],
1775 LLVMTypeOf(src[0]), ""),
1776 "");
1777 break;
1778 case nir_op_ilt:
1779 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1780 break;
1781 case nir_op_ine:
1782 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1783 break;
1784 case nir_op_ieq:
1785 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1786 break;
1787 case nir_op_ige:
1788 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1789 break;
1790 case nir_op_ult:
1791 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1792 break;
1793 case nir_op_uge:
1794 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1795 break;
1796 case nir_op_feq:
1797 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1798 break;
1799 case nir_op_fne:
1800 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1801 break;
1802 case nir_op_flt:
1803 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1804 break;
1805 case nir_op_fge:
1806 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1807 break;
1808 case nir_op_fabs:
1809 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1810 ac_to_float_type(&ctx->ac, def_type), src[0]);
1811 break;
1812 case nir_op_iabs:
1813 result = emit_iabs(&ctx->ac, src[0]);
1814 break;
1815 case nir_op_imax:
1816 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1817 break;
1818 case nir_op_imin:
1819 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1820 break;
1821 case nir_op_umax:
1822 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1823 break;
1824 case nir_op_umin:
1825 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1826 break;
1827 case nir_op_isign:
1828 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1829 break;
1830 case nir_op_fsign:
1831 src[0] = ac_to_float(&ctx->ac, src[0]);
1832 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1833 break;
1834 case nir_op_ffloor:
1835 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1836 ac_to_float_type(&ctx->ac, def_type), src[0]);
1837 break;
1838 case nir_op_ftrunc:
1839 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1840 ac_to_float_type(&ctx->ac, def_type), src[0]);
1841 break;
1842 case nir_op_fceil:
1843 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1844 ac_to_float_type(&ctx->ac, def_type), src[0]);
1845 break;
1846 case nir_op_fround_even:
1847 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1848 ac_to_float_type(&ctx->ac, def_type),src[0]);
1849 break;
1850 case nir_op_ffract:
1851 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1852 break;
1853 case nir_op_fsin:
1854 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1855 ac_to_float_type(&ctx->ac, def_type), src[0]);
1856 break;
1857 case nir_op_fcos:
1858 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1859 ac_to_float_type(&ctx->ac, def_type), src[0]);
1860 break;
1861 case nir_op_fsqrt:
1862 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1863 ac_to_float_type(&ctx->ac, def_type), src[0]);
1864 break;
1865 case nir_op_fexp2:
1866 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1867 ac_to_float_type(&ctx->ac, def_type), src[0]);
1868 break;
1869 case nir_op_flog2:
1870 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1871 ac_to_float_type(&ctx->ac, def_type), src[0]);
1872 break;
1873 case nir_op_frsq:
1874 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1875 ac_to_float_type(&ctx->ac, def_type), src[0]);
1876 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1877 result);
1878 break;
1879 case nir_op_fpow:
1880 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1881 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1882 break;
1883 case nir_op_fmax:
1884 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1885 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1886 if (ctx->ac.chip_class < GFX9 &&
1887 instr->dest.dest.ssa.bit_size == 32) {
1888 /* Only pre-GFX9 chips do not flush denorms. */
1889 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1890 ac_to_float_type(&ctx->ac, def_type),
1891 result);
1892 }
1893 break;
1894 case nir_op_fmin:
1895 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1896 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1897 if (ctx->ac.chip_class < GFX9 &&
1898 instr->dest.dest.ssa.bit_size == 32) {
1899 /* Only pre-GFX9 chips do not flush denorms. */
1900 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1901 ac_to_float_type(&ctx->ac, def_type),
1902 result);
1903 }
1904 break;
1905 case nir_op_ffma:
1906 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1907 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1908 break;
1909 case nir_op_ibitfield_extract:
1910 result = emit_bitfield_extract(&ctx->ac, true, src);
1911 break;
1912 case nir_op_ubitfield_extract:
1913 result = emit_bitfield_extract(&ctx->ac, false, src);
1914 break;
1915 case nir_op_bitfield_insert:
1916 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1917 break;
1918 case nir_op_bitfield_reverse:
1919 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1920 break;
1921 case nir_op_bit_count:
1922 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1923 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1924 else {
1925 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1926 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1927 }
1928 break;
1929 case nir_op_vec2:
1930 case nir_op_vec3:
1931 case nir_op_vec4:
1932 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1933 src[i] = ac_to_integer(&ctx->ac, src[i]);
1934 result = ac_build_gather_values(&ctx->ac, src, num_components);
1935 break;
1936 case nir_op_f2i32:
1937 case nir_op_f2i64:
1938 src[0] = ac_to_float(&ctx->ac, src[0]);
1939 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1940 break;
1941 case nir_op_f2u32:
1942 case nir_op_f2u64:
1943 src[0] = ac_to_float(&ctx->ac, src[0]);
1944 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1945 break;
1946 case nir_op_i2f32:
1947 case nir_op_i2f64:
1948 src[0] = ac_to_integer(&ctx->ac, src[0]);
1949 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1950 break;
1951 case nir_op_u2f32:
1952 case nir_op_u2f64:
1953 src[0] = ac_to_integer(&ctx->ac, src[0]);
1954 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1955 break;
1956 case nir_op_f2f64:
1957 src[0] = ac_to_float(&ctx->ac, src[0]);
1958 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1959 break;
1960 case nir_op_f2f32:
1961 src[0] = ac_to_float(&ctx->ac, src[0]);
1962 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1963 break;
1964 case nir_op_u2u32:
1965 case nir_op_u2u64:
1966 src[0] = ac_to_integer(&ctx->ac, src[0]);
1967 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1968 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1969 else
1970 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1971 break;
1972 case nir_op_i2i32:
1973 case nir_op_i2i64:
1974 src[0] = ac_to_integer(&ctx->ac, src[0]);
1975 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1976 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1977 else
1978 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1979 break;
1980 case nir_op_bcsel:
1981 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1982 break;
1983 case nir_op_find_lsb:
1984 src[0] = ac_to_integer(&ctx->ac, src[0]);
1985 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1986 break;
1987 case nir_op_ufind_msb:
1988 src[0] = ac_to_integer(&ctx->ac, src[0]);
1989 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1990 break;
1991 case nir_op_ifind_msb:
1992 src[0] = ac_to_integer(&ctx->ac, src[0]);
1993 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1994 break;
1995 case nir_op_uadd_carry:
1996 src[0] = ac_to_integer(&ctx->ac, src[0]);
1997 src[1] = ac_to_integer(&ctx->ac, src[1]);
1998 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1999 break;
2000 case nir_op_usub_borrow:
2001 src[0] = ac_to_integer(&ctx->ac, src[0]);
2002 src[1] = ac_to_integer(&ctx->ac, src[1]);
2003 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
2004 break;
2005 case nir_op_b2f:
2006 result = emit_b2f(&ctx->ac, src[0]);
2007 break;
2008 case nir_op_f2b:
2009 result = emit_f2b(&ctx->ac, src[0]);
2010 break;
2011 case nir_op_b2i:
2012 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2013 break;
2014 case nir_op_i2b:
2015 src[0] = ac_to_integer(&ctx->ac, src[0]);
2016 result = emit_i2b(&ctx->ac, src[0]);
2017 break;
2018 case nir_op_fquantize2f16:
2019 result = emit_f2f16(&ctx->ac, src[0]);
2020 break;
2021 case nir_op_umul_high:
2022 src[0] = ac_to_integer(&ctx->ac, src[0]);
2023 src[1] = ac_to_integer(&ctx->ac, src[1]);
2024 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2025 break;
2026 case nir_op_imul_high:
2027 src[0] = ac_to_integer(&ctx->ac, src[0]);
2028 src[1] = ac_to_integer(&ctx->ac, src[1]);
2029 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2030 break;
2031 case nir_op_pack_half_2x16:
2032 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2033 break;
2034 case nir_op_unpack_half_2x16:
2035 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2036 break;
2037 case nir_op_fddx:
2038 case nir_op_fddy:
2039 case nir_op_fddx_fine:
2040 case nir_op_fddy_fine:
2041 case nir_op_fddx_coarse:
2042 case nir_op_fddy_coarse:
2043 result = emit_ddxy(ctx, instr->op, src[0]);
2044 break;
2045
2046 case nir_op_unpack_64_2x32_split_x: {
2047 assert(ac_get_llvm_num_components(src[0]) == 1);
2048 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2049 ctx->ac.v2i32,
2050 "");
2051 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2052 ctx->ac.i32_0, "");
2053 break;
2054 }
2055
2056 case nir_op_unpack_64_2x32_split_y: {
2057 assert(ac_get_llvm_num_components(src[0]) == 1);
2058 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2059 ctx->ac.v2i32,
2060 "");
2061 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2062 ctx->ac.i32_1, "");
2063 break;
2064 }
2065
2066 case nir_op_pack_64_2x32_split: {
2067 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2068 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2069 src[0], ctx->ac.i32_0, "");
2070 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2071 src[1], ctx->ac.i32_1, "");
2072 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2073 break;
2074 }
2075
2076 default:
2077 fprintf(stderr, "Unknown NIR alu instr: ");
2078 nir_print_instr(&instr->instr, stderr);
2079 fprintf(stderr, "\n");
2080 abort();
2081 }
2082
2083 if (result) {
2084 assert(instr->dest.dest.is_ssa);
2085 result = ac_to_integer(&ctx->ac, result);
2086 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2087 result);
2088 }
2089 }
2090
2091 static void visit_load_const(struct ac_nir_context *ctx,
2092 const nir_load_const_instr *instr)
2093 {
2094 LLVMValueRef values[4], value = NULL;
2095 LLVMTypeRef element_type =
2096 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2097
2098 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2099 switch (instr->def.bit_size) {
2100 case 32:
2101 values[i] = LLVMConstInt(element_type,
2102 instr->value.u32[i], false);
2103 break;
2104 case 64:
2105 values[i] = LLVMConstInt(element_type,
2106 instr->value.u64[i], false);
2107 break;
2108 default:
2109 fprintf(stderr,
2110 "unsupported nir load_const bit_size: %d\n",
2111 instr->def.bit_size);
2112 abort();
2113 }
2114 }
2115 if (instr->def.num_components > 1) {
2116 value = LLVMConstVector(values, instr->def.num_components);
2117 } else
2118 value = values[0];
2119
2120 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2121 }
2122
2123 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2124 LLVMTypeRef type)
2125 {
2126 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2127 return LLVMBuildBitCast(ctx->builder, ptr,
2128 LLVMPointerType(type, addr_space), "");
2129 }
2130
2131 static LLVMValueRef
2132 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2133 {
2134 LLVMValueRef size =
2135 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2136 LLVMConstInt(ctx->ac.i32, 2, false), "");
2137
2138 /* VI only */
2139 if (ctx->ac.chip_class == VI && in_elements) {
2140 /* On VI, the descriptor contains the size in bytes,
2141 * but TXQ must return the size in elements.
2142 * The stride is always non-zero for resources using TXQ.
2143 */
2144 LLVMValueRef stride =
2145 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2146 ctx->ac.i32_1, "");
2147 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2148 LLVMConstInt(ctx->ac.i32, 16, false), "");
2149 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2150 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2151
2152 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2153 }
2154 return size;
2155 }
2156
2157 /**
2158 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2159 * intrinsic names).
2160 */
2161 static void build_int_type_name(
2162 LLVMTypeRef type,
2163 char *buf, unsigned bufsize)
2164 {
2165 assert(bufsize >= 6);
2166
2167 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2168 snprintf(buf, bufsize, "v%ui32",
2169 LLVMGetVectorSize(type));
2170 else
2171 strcpy(buf, "i32");
2172 }
2173
2174 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2175 struct ac_image_args *args,
2176 const nir_tex_instr *instr)
2177 {
2178 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2179 LLVMValueRef coord = args->addr;
2180 LLVMValueRef half_texel[2];
2181 LLVMValueRef compare_cube_wa = NULL;
2182 LLVMValueRef result;
2183 int c;
2184 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2185
2186 //TODO Rect
2187 {
2188 struct ac_image_args txq_args = { 0 };
2189
2190 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2191 txq_args.opcode = ac_image_get_resinfo;
2192 txq_args.dmask = 0xf;
2193 txq_args.addr = ctx->i32_0;
2194 txq_args.resource = args->resource;
2195 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2196
2197 for (c = 0; c < 2; c++) {
2198 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2199 LLVMConstInt(ctx->i32, c, false), "");
2200 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2201 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2202 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2203 LLVMConstReal(ctx->f32, -0.5), "");
2204 }
2205 }
2206
2207 LLVMValueRef orig_coords = args->addr;
2208
2209 for (c = 0; c < 2; c++) {
2210 LLVMValueRef tmp;
2211 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2212 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2213 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2214 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2215 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2216 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2217 }
2218
2219
2220 /*
2221 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2222 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2223 * workaround by sampling using a scaled type and converting.
2224 * This is taken from amdgpu-pro shaders.
2225 */
2226 /* NOTE this produces some ugly code compared to amdgpu-pro,
2227 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2228 * and then reads them back. -pro generates two selects,
2229 * one s_cmp for the descriptor rewriting
2230 * one v_cmp for the coordinate and result changes.
2231 */
2232 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2233 LLVMValueRef tmp, tmp2;
2234
2235 /* workaround 8/8/8/8 uint/sint cube gather bug */
2236 /* first detect it then change to a scaled read and f2i */
2237 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2238 tmp2 = tmp;
2239
2240 /* extract the DATA_FORMAT */
2241 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2242 LLVMConstInt(ctx->i32, 6, false), false);
2243
2244 /* is the DATA_FORMAT == 8_8_8_8 */
2245 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2246
2247 if (stype == GLSL_TYPE_UINT)
2248 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2249 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2250 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2251 else
2252 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2253 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2254 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2255
2256 /* replace the NUM FORMAT in the descriptor */
2257 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2258 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2259
2260 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2261
2262 /* don't modify the coordinates for this case */
2263 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2264 }
2265 args->addr = coord;
2266 result = ac_build_image_opcode(ctx, args);
2267
2268 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2269 LLVMValueRef tmp, tmp2;
2270
2271 /* if the cube workaround is in place, f2i the result. */
2272 for (c = 0; c < 4; c++) {
2273 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2274 if (stype == GLSL_TYPE_UINT)
2275 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2276 else
2277 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2278 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2279 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2280 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2281 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2282 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2283 }
2284 }
2285 return result;
2286 }
2287
2288 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2289 const nir_tex_instr *instr,
2290 bool lod_is_zero,
2291 struct ac_image_args *args)
2292 {
2293 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2294 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2295
2296 return ac_build_buffer_load_format(&ctx->ac,
2297 args->resource,
2298 args->addr,
2299 ctx->ac.i32_0,
2300 util_last_bit(mask),
2301 false, true);
2302 }
2303
2304 args->opcode = ac_image_sample;
2305 args->compare = instr->is_shadow;
2306
2307 switch (instr->op) {
2308 case nir_texop_txf:
2309 case nir_texop_txf_ms:
2310 case nir_texop_samples_identical:
2311 args->opcode = lod_is_zero ||
2312 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2313 ac_image_load : ac_image_load_mip;
2314 args->compare = false;
2315 args->offset = false;
2316 break;
2317 case nir_texop_txb:
2318 args->bias = true;
2319 break;
2320 case nir_texop_txl:
2321 if (lod_is_zero)
2322 args->level_zero = true;
2323 else
2324 args->lod = true;
2325 break;
2326 case nir_texop_txs:
2327 case nir_texop_query_levels:
2328 args->opcode = ac_image_get_resinfo;
2329 break;
2330 case nir_texop_tex:
2331 if (ctx->stage != MESA_SHADER_FRAGMENT)
2332 args->level_zero = true;
2333 break;
2334 case nir_texop_txd:
2335 args->deriv = true;
2336 break;
2337 case nir_texop_tg4:
2338 args->opcode = ac_image_gather4;
2339 args->level_zero = true;
2340 break;
2341 case nir_texop_lod:
2342 args->opcode = ac_image_get_lod;
2343 args->compare = false;
2344 args->offset = false;
2345 break;
2346 default:
2347 break;
2348 }
2349
2350 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2351 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2352 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2353 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2354 }
2355 }
2356 return ac_build_image_opcode(&ctx->ac, args);
2357 }
2358
2359 static LLVMValueRef
2360 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2361 unsigned desc_set, unsigned binding)
2362 {
2363 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2364 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2365 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2366 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2367 unsigned base_offset = layout->binding[binding].offset;
2368 LLVMValueRef offset, stride;
2369
2370 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2371 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2372 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2373 layout->binding[binding].dynamic_offset_offset;
2374 desc_ptr = ctx->abi.push_constants;
2375 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2376 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2377 } else
2378 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2379
2380 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2381 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2382 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2383
2384 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2385 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2386 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2387
2388 return desc_ptr;
2389 }
2390
2391 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2392 nir_intrinsic_instr *instr)
2393 {
2394 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2395 LLVMValueRef index = get_src(ctx, instr->src[1]);
2396
2397 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2398 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2399 return result;
2400 }
2401
2402 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2403 nir_intrinsic_instr *instr)
2404 {
2405 LLVMValueRef ptr, addr;
2406
2407 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2408 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2409 get_src(ctx, instr->src[0]), "");
2410
2411 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2412 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2413
2414 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2415 }
2416
2417 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2418 const nir_intrinsic_instr *instr)
2419 {
2420 LLVMValueRef index = get_src(ctx, instr->src[0]);
2421
2422 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2423 }
2424
2425 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2426 {
2427 uint32_t new_mask = 0;
2428 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2429 if (mask & (1u << i))
2430 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2431 return new_mask;
2432 }
2433
2434 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2435 unsigned start, unsigned count)
2436 {
2437 LLVMTypeRef type = LLVMTypeOf(src);
2438
2439 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2440 assert(start == 0);
2441 assert(count == 1);
2442 return src;
2443 }
2444
2445 unsigned src_elements = LLVMGetVectorSize(type);
2446 assert(start < src_elements);
2447 assert(start + count <= src_elements);
2448
2449 if (start == 0 && count == src_elements)
2450 return src;
2451
2452 if (count == 1)
2453 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2454
2455 assert(count <= 8);
2456 LLVMValueRef indices[8];
2457 for (unsigned i = 0; i < count; ++i)
2458 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2459
2460 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2461 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2462 }
2463
2464 static void visit_store_ssbo(struct ac_nir_context *ctx,
2465 nir_intrinsic_instr *instr)
2466 {
2467 const char *store_name;
2468 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2469 LLVMTypeRef data_type = ctx->ac.f32;
2470 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2471 int components_32bit = elem_size_mult * instr->num_components;
2472 unsigned writemask = nir_intrinsic_write_mask(instr);
2473 LLVMValueRef base_data, base_offset;
2474 LLVMValueRef params[6];
2475
2476 params[1] = ctx->abi->load_ssbo(ctx->abi,
2477 get_src(ctx, instr->src[1]), true);
2478 params[2] = ctx->ac.i32_0; /* vindex */
2479 params[4] = ctx->ac.i1false; /* glc */
2480 params[5] = ctx->ac.i1false; /* slc */
2481
2482 if (components_32bit > 1)
2483 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2484
2485 writemask = widen_mask(writemask, elem_size_mult);
2486
2487 base_data = ac_to_float(&ctx->ac, src_data);
2488 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2489 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2490 data_type, "");
2491 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2492 while (writemask) {
2493 int start, count;
2494 LLVMValueRef data;
2495 LLVMValueRef offset;
2496
2497 u_bit_scan_consecutive_range(&writemask, &start, &count);
2498
2499 /* Due to an LLVM limitation, split 3-element writes
2500 * into a 2-element and a 1-element write. */
2501 if (count == 3) {
2502 writemask |= 1 << (start + 2);
2503 count = 2;
2504 }
2505
2506 if (count > 4) {
2507 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2508 count = 4;
2509 }
2510
2511 if (count == 4) {
2512 store_name = "llvm.amdgcn.buffer.store.v4f32";
2513 } else if (count == 2) {
2514 store_name = "llvm.amdgcn.buffer.store.v2f32";
2515
2516 } else {
2517 assert(count == 1);
2518 store_name = "llvm.amdgcn.buffer.store.f32";
2519 }
2520 data = extract_vector_range(&ctx->ac, base_data, start, count);
2521
2522 offset = base_offset;
2523 if (start != 0) {
2524 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2525 }
2526 params[0] = data;
2527 params[3] = offset;
2528 ac_build_intrinsic(&ctx->ac, store_name,
2529 ctx->ac.voidt, params, 6, 0);
2530 }
2531 }
2532
2533 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2534 const nir_intrinsic_instr *instr)
2535 {
2536 const char *name;
2537 LLVMValueRef params[6];
2538 int arg_count = 0;
2539
2540 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2541 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2542 }
2543 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2544 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2545 get_src(ctx, instr->src[0]),
2546 true);
2547 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2548 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2549 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2550
2551 switch (instr->intrinsic) {
2552 case nir_intrinsic_ssbo_atomic_add:
2553 name = "llvm.amdgcn.buffer.atomic.add";
2554 break;
2555 case nir_intrinsic_ssbo_atomic_imin:
2556 name = "llvm.amdgcn.buffer.atomic.smin";
2557 break;
2558 case nir_intrinsic_ssbo_atomic_umin:
2559 name = "llvm.amdgcn.buffer.atomic.umin";
2560 break;
2561 case nir_intrinsic_ssbo_atomic_imax:
2562 name = "llvm.amdgcn.buffer.atomic.smax";
2563 break;
2564 case nir_intrinsic_ssbo_atomic_umax:
2565 name = "llvm.amdgcn.buffer.atomic.umax";
2566 break;
2567 case nir_intrinsic_ssbo_atomic_and:
2568 name = "llvm.amdgcn.buffer.atomic.and";
2569 break;
2570 case nir_intrinsic_ssbo_atomic_or:
2571 name = "llvm.amdgcn.buffer.atomic.or";
2572 break;
2573 case nir_intrinsic_ssbo_atomic_xor:
2574 name = "llvm.amdgcn.buffer.atomic.xor";
2575 break;
2576 case nir_intrinsic_ssbo_atomic_exchange:
2577 name = "llvm.amdgcn.buffer.atomic.swap";
2578 break;
2579 case nir_intrinsic_ssbo_atomic_comp_swap:
2580 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2581 break;
2582 default:
2583 abort();
2584 }
2585
2586 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2587 }
2588
2589 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2590 const nir_intrinsic_instr *instr)
2591 {
2592 LLVMValueRef results[2];
2593 int load_components;
2594 int num_components = instr->num_components;
2595 if (instr->dest.ssa.bit_size == 64)
2596 num_components *= 2;
2597
2598 for (int i = 0; i < num_components; i += load_components) {
2599 load_components = MIN2(num_components - i, 4);
2600 const char *load_name;
2601 LLVMTypeRef data_type = ctx->ac.f32;
2602 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2603 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2604
2605 if (load_components == 3)
2606 data_type = LLVMVectorType(ctx->ac.f32, 4);
2607 else if (load_components > 1)
2608 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2609
2610 if (load_components >= 3)
2611 load_name = "llvm.amdgcn.buffer.load.v4f32";
2612 else if (load_components == 2)
2613 load_name = "llvm.amdgcn.buffer.load.v2f32";
2614 else if (load_components == 1)
2615 load_name = "llvm.amdgcn.buffer.load.f32";
2616 else
2617 unreachable("unhandled number of components");
2618
2619 LLVMValueRef params[] = {
2620 ctx->abi->load_ssbo(ctx->abi,
2621 get_src(ctx, instr->src[0]),
2622 false),
2623 ctx->ac.i32_0,
2624 offset,
2625 ctx->ac.i1false,
2626 ctx->ac.i1false,
2627 };
2628
2629 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2630 }
2631
2632 assume(results[0]);
2633 LLVMValueRef ret = results[0];
2634 if (num_components > 4 || num_components == 3) {
2635 LLVMValueRef masks[] = {
2636 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2637 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2638 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2639 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2640 };
2641
2642 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2643 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2644 results[num_components > 4 ? 1 : 0], swizzle, "");
2645 }
2646
2647 return LLVMBuildBitCast(ctx->ac.builder, ret,
2648 get_def_type(ctx, &instr->dest.ssa), "");
2649 }
2650
2651 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2652 const nir_intrinsic_instr *instr)
2653 {
2654 LLVMValueRef ret;
2655 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2656 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2657 int num_components = instr->num_components;
2658
2659 if (ctx->abi->load_ubo)
2660 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2661
2662 if (instr->dest.ssa.bit_size == 64)
2663 num_components *= 2;
2664
2665 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2666 NULL, 0, false, false, true, true);
2667 ret = trim_vector(&ctx->ac, ret, num_components);
2668 return LLVMBuildBitCast(ctx->ac.builder, ret,
2669 get_def_type(ctx, &instr->dest.ssa), "");
2670 }
2671
2672 static void
2673 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2674 bool vs_in, unsigned *vertex_index_out,
2675 LLVMValueRef *vertex_index_ref,
2676 unsigned *const_out, LLVMValueRef *indir_out)
2677 {
2678 unsigned const_offset = 0;
2679 nir_deref *tail = &deref->deref;
2680 LLVMValueRef offset = NULL;
2681
2682 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2683 tail = tail->child;
2684 nir_deref_array *deref_array = nir_deref_as_array(tail);
2685 if (vertex_index_out)
2686 *vertex_index_out = deref_array->base_offset;
2687
2688 if (vertex_index_ref) {
2689 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2690 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2691 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2692 }
2693 *vertex_index_ref = vtx;
2694 }
2695 }
2696
2697 if (deref->var->data.compact) {
2698 assert(tail->child->deref_type == nir_deref_type_array);
2699 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2700 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2701 /* We always lower indirect dereferences for "compact" array vars. */
2702 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2703
2704 const_offset = deref_array->base_offset;
2705 goto out;
2706 }
2707
2708 while (tail->child != NULL) {
2709 const struct glsl_type *parent_type = tail->type;
2710 tail = tail->child;
2711
2712 if (tail->deref_type == nir_deref_type_array) {
2713 nir_deref_array *deref_array = nir_deref_as_array(tail);
2714 LLVMValueRef index, stride, local_offset;
2715 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2716
2717 const_offset += size * deref_array->base_offset;
2718 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2719 continue;
2720
2721 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2722 index = get_src(ctx, deref_array->indirect);
2723 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2724 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2725
2726 if (offset)
2727 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2728 else
2729 offset = local_offset;
2730 } else if (tail->deref_type == nir_deref_type_struct) {
2731 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2732
2733 for (unsigned i = 0; i < deref_struct->index; i++) {
2734 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2735 const_offset += glsl_count_attribute_slots(ft, vs_in);
2736 }
2737 } else
2738 unreachable("unsupported deref type");
2739
2740 }
2741 out:
2742 if (const_offset && offset)
2743 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2744 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2745 "");
2746
2747 *const_out = const_offset;
2748 *indir_out = offset;
2749 }
2750
2751
2752 /* The offchip buffer layout for TCS->TES is
2753 *
2754 * - attribute 0 of patch 0 vertex 0
2755 * - attribute 0 of patch 0 vertex 1
2756 * - attribute 0 of patch 0 vertex 2
2757 * ...
2758 * - attribute 0 of patch 1 vertex 0
2759 * - attribute 0 of patch 1 vertex 1
2760 * ...
2761 * - attribute 1 of patch 0 vertex 0
2762 * - attribute 1 of patch 0 vertex 1
2763 * ...
2764 * - per patch attribute 0 of patch 0
2765 * - per patch attribute 0 of patch 1
2766 * ...
2767 *
2768 * Note that every attribute has 4 components.
2769 */
2770 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
2771 LLVMValueRef vertex_index,
2772 LLVMValueRef param_index)
2773 {
2774 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2775 LLVMValueRef param_stride, constant16;
2776 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2777
2778 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2779 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2780 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2781 num_patches, "");
2782
2783 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2784 if (vertex_index) {
2785 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2786 vertices_per_patch, "");
2787
2788 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2789 vertex_index, "");
2790
2791 param_stride = total_vertices;
2792 } else {
2793 base_addr = rel_patch_id;
2794 param_stride = num_patches;
2795 }
2796
2797 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2798 LLVMBuildMul(ctx->ac.builder, param_index,
2799 param_stride, ""), "");
2800
2801 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2802
2803 if (!vertex_index) {
2804 LLVMValueRef patch_data_offset =
2805 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2806
2807 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2808 patch_data_offset, "");
2809 }
2810 return base_addr;
2811 }
2812
2813 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
2814 unsigned param,
2815 unsigned const_index,
2816 bool is_compact,
2817 LLVMValueRef vertex_index,
2818 LLVMValueRef indir_index)
2819 {
2820 LLVMValueRef param_index;
2821
2822 if (indir_index)
2823 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2824 indir_index, "");
2825 else {
2826 if (const_index && !is_compact)
2827 param += const_index;
2828 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2829 }
2830 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2831 }
2832
2833 static void
2834 mark_tess_output(struct radv_shader_context *ctx,
2835 bool is_patch, uint32_t param)
2836
2837 {
2838 if (is_patch) {
2839 ctx->tess_patch_outputs_written |= (1ull << param);
2840 } else
2841 ctx->tess_outputs_written |= (1ull << param);
2842 }
2843
2844 static LLVMValueRef
2845 get_dw_address(struct radv_shader_context *ctx,
2846 LLVMValueRef dw_addr,
2847 unsigned param,
2848 unsigned const_index,
2849 bool compact_const_index,
2850 LLVMValueRef vertex_index,
2851 LLVMValueRef stride,
2852 LLVMValueRef indir_index)
2853
2854 {
2855
2856 if (vertex_index) {
2857 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2858 LLVMBuildMul(ctx->ac.builder,
2859 vertex_index,
2860 stride, ""), "");
2861 }
2862
2863 if (indir_index)
2864 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2865 LLVMBuildMul(ctx->ac.builder, indir_index,
2866 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2867 else if (const_index && !compact_const_index)
2868 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2869 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2870
2871 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2872 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2873
2874 if (const_index && compact_const_index)
2875 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2876 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2877 return dw_addr;
2878 }
2879
2880 static LLVMValueRef
2881 load_tcs_varyings(struct ac_shader_abi *abi,
2882 LLVMValueRef vertex_index,
2883 LLVMValueRef indir_index,
2884 unsigned const_index,
2885 unsigned location,
2886 unsigned driver_location,
2887 unsigned component,
2888 unsigned num_components,
2889 bool is_patch,
2890 bool is_compact,
2891 bool load_input)
2892 {
2893 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2894 LLVMValueRef dw_addr, stride;
2895 LLVMValueRef value[4], result;
2896 unsigned param = shader_io_get_unique_index(location);
2897
2898 if (load_input) {
2899 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2900 dw_addr = get_tcs_in_current_patch_offset(ctx);
2901 } else {
2902 if (!is_patch) {
2903 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2904 dw_addr = get_tcs_out_current_patch_offset(ctx);
2905 } else {
2906 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2907 stride = NULL;
2908 }
2909 }
2910
2911 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2912 indir_index);
2913
2914 for (unsigned i = 0; i < num_components + component; i++) {
2915 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2916 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2917 ctx->ac.i32_1, "");
2918 }
2919 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2920 return result;
2921 }
2922
2923 static void
2924 store_tcs_output(struct ac_shader_abi *abi,
2925 LLVMValueRef vertex_index,
2926 LLVMValueRef param_index,
2927 unsigned const_index,
2928 unsigned location,
2929 unsigned driver_location,
2930 LLVMValueRef src,
2931 unsigned component,
2932 bool is_patch,
2933 bool is_compact,
2934 unsigned writemask)
2935 {
2936 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
2937 LLVMValueRef dw_addr;
2938 LLVMValueRef stride = NULL;
2939 LLVMValueRef buf_addr = NULL;
2940 unsigned param;
2941 bool store_lds = true;
2942
2943 if (is_patch) {
2944 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2945 store_lds = false;
2946 } else {
2947 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2948 store_lds = false;
2949 }
2950
2951 param = shader_io_get_unique_index(location);
2952 if (location == VARYING_SLOT_CLIP_DIST0 &&
2953 is_compact && const_index > 3) {
2954 const_index -= 3;
2955 param++;
2956 }
2957
2958 if (!is_patch) {
2959 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2960 dw_addr = get_tcs_out_current_patch_offset(ctx);
2961 } else {
2962 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2963 }
2964
2965 mark_tess_output(ctx, is_patch, param);
2966
2967 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2968 param_index);
2969 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2970 vertex_index, param_index);
2971
2972 bool is_tess_factor = false;
2973 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2974 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2975 is_tess_factor = true;
2976
2977 unsigned base = is_compact ? const_index : 0;
2978 for (unsigned chan = 0; chan < 8; chan++) {
2979 if (!(writemask & (1 << chan)))
2980 continue;
2981 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2982
2983 if (store_lds || is_tess_factor) {
2984 LLVMValueRef dw_addr_chan =
2985 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2986 LLVMConstInt(ctx->ac.i32, chan, false), "");
2987 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2988 }
2989
2990 if (!is_tess_factor && writemask != 0xF)
2991 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2992 buf_addr, ctx->oc_lds,
2993 4 * (base + chan), 1, 0, true, false);
2994 }
2995
2996 if (writemask == 0xF) {
2997 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2998 buf_addr, ctx->oc_lds,
2999 (base * 4), 1, 0, true, false);
3000 }
3001 }
3002
3003 static LLVMValueRef
3004 load_tes_input(struct ac_shader_abi *abi,
3005 LLVMValueRef vertex_index,
3006 LLVMValueRef param_index,
3007 unsigned const_index,
3008 unsigned location,
3009 unsigned driver_location,
3010 unsigned component,
3011 unsigned num_components,
3012 bool is_patch,
3013 bool is_compact,
3014 bool load_input)
3015 {
3016 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3017 LLVMValueRef buf_addr;
3018 LLVMValueRef result;
3019 unsigned param = shader_io_get_unique_index(location);
3020
3021 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3022 const_index -= 3;
3023 param++;
3024 }
3025
3026 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3027 is_compact, vertex_index, param_index);
3028
3029 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3030 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3031
3032 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3033 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3034 result = trim_vector(&ctx->ac, result, num_components);
3035 return result;
3036 }
3037
3038 static LLVMValueRef
3039 load_gs_input(struct ac_shader_abi *abi,
3040 unsigned location,
3041 unsigned driver_location,
3042 unsigned component,
3043 unsigned num_components,
3044 unsigned vertex_index,
3045 unsigned const_index,
3046 LLVMTypeRef type)
3047 {
3048 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3049 LLVMValueRef vtx_offset;
3050 unsigned param, vtx_offset_param;
3051 LLVMValueRef value[4], result;
3052
3053 vtx_offset_param = vertex_index;
3054 assert(vtx_offset_param < 6);
3055 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3056 LLVMConstInt(ctx->ac.i32, 4, false), "");
3057
3058 param = shader_io_get_unique_index(location);
3059
3060 for (unsigned i = component; i < num_components + component; i++) {
3061 if (ctx->ac.chip_class >= GFX9) {
3062 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3063 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3064 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3065 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3066 } else {
3067 LLVMValueRef soffset =
3068 LLVMConstInt(ctx->ac.i32,
3069 (param * 4 + i + const_index) * 256,
3070 false);
3071
3072 value[i] = ac_build_buffer_load(&ctx->ac,
3073 ctx->esgs_ring, 1,
3074 ctx->ac.i32_0,
3075 vtx_offset, soffset,
3076 0, 1, 0, true, false);
3077
3078 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3079 type, "");
3080 }
3081 }
3082 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3083 result = ac_to_integer(&ctx->ac, result);
3084 return result;
3085 }
3086
3087 static LLVMValueRef
3088 build_gep_for_deref(struct ac_nir_context *ctx,
3089 nir_deref_var *deref)
3090 {
3091 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3092 assert(entry->data);
3093 LLVMValueRef val = entry->data;
3094 nir_deref *tail = deref->deref.child;
3095 while (tail != NULL) {
3096 LLVMValueRef offset;
3097 switch (tail->deref_type) {
3098 case nir_deref_type_array: {
3099 nir_deref_array *array = nir_deref_as_array(tail);
3100 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3101 if (array->deref_array_type ==
3102 nir_deref_array_type_indirect) {
3103 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3104 get_src(ctx,
3105 array->indirect),
3106 "");
3107 }
3108 break;
3109 }
3110 case nir_deref_type_struct: {
3111 nir_deref_struct *deref_struct =
3112 nir_deref_as_struct(tail);
3113 offset = LLVMConstInt(ctx->ac.i32,
3114 deref_struct->index, 0);
3115 break;
3116 }
3117 default:
3118 unreachable("bad deref type");
3119 }
3120 val = ac_build_gep0(&ctx->ac, val, offset);
3121 tail = tail->child;
3122 }
3123 return val;
3124 }
3125
3126 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3127 nir_intrinsic_instr *instr,
3128 bool load_inputs)
3129 {
3130 LLVMValueRef result;
3131 LLVMValueRef vertex_index = NULL;
3132 LLVMValueRef indir_index = NULL;
3133 unsigned const_index = 0;
3134 unsigned location = instr->variables[0]->var->data.location;
3135 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3136 const bool is_patch = instr->variables[0]->var->data.patch;
3137 const bool is_compact = instr->variables[0]->var->data.compact;
3138
3139 get_deref_offset(ctx, instr->variables[0],
3140 false, NULL, is_patch ? NULL : &vertex_index,
3141 &const_index, &indir_index);
3142
3143 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3144 const_index, location, driver_location,
3145 instr->variables[0]->var->data.location_frac,
3146 instr->num_components,
3147 is_patch, is_compact, load_inputs);
3148 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3149 }
3150
3151 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3152 nir_intrinsic_instr *instr)
3153 {
3154 LLVMValueRef values[8];
3155 int idx = instr->variables[0]->var->data.driver_location;
3156 int ve = instr->dest.ssa.num_components;
3157 unsigned comp = instr->variables[0]->var->data.location_frac;
3158 LLVMValueRef indir_index;
3159 LLVMValueRef ret;
3160 unsigned const_index;
3161 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3162 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3163 instr->variables[0]->var->data.mode == nir_var_shader_in;
3164 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3165 &const_index, &indir_index);
3166
3167 if (instr->dest.ssa.bit_size == 64)
3168 ve *= 2;
3169
3170 switch (instr->variables[0]->var->data.mode) {
3171 case nir_var_shader_in:
3172 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3173 ctx->stage == MESA_SHADER_TESS_EVAL) {
3174 return load_tess_varyings(ctx, instr, true);
3175 }
3176
3177 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3178 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3179 LLVMValueRef indir_index;
3180 unsigned const_index, vertex_index;
3181 get_deref_offset(ctx, instr->variables[0],
3182 false, &vertex_index, NULL,
3183 &const_index, &indir_index);
3184
3185 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3186 instr->variables[0]->var->data.driver_location,
3187 instr->variables[0]->var->data.location_frac, ve,
3188 vertex_index, const_index, type);
3189 }
3190
3191 for (unsigned chan = comp; chan < ve + comp; chan++) {
3192 if (indir_index) {
3193 unsigned count = glsl_count_attribute_slots(
3194 instr->variables[0]->var->type,
3195 ctx->stage == MESA_SHADER_VERTEX);
3196 count -= chan / 4;
3197 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3198 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3199 stride, false, true);
3200
3201 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3202 tmp_vec,
3203 indir_index, "");
3204 } else
3205 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3206 }
3207 break;
3208 case nir_var_local:
3209 for (unsigned chan = 0; chan < ve; chan++) {
3210 if (indir_index) {
3211 unsigned count = glsl_count_attribute_slots(
3212 instr->variables[0]->var->type, false);
3213 count -= chan / 4;
3214 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3215 &ctx->ac, ctx->locals + idx + chan, count,
3216 stride, true, true);
3217
3218 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3219 tmp_vec,
3220 indir_index, "");
3221 } else {
3222 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3223 }
3224 }
3225 break;
3226 case nir_var_shared: {
3227 LLVMValueRef address = build_gep_for_deref(ctx,
3228 instr->variables[0]);
3229 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3230 return LLVMBuildBitCast(ctx->ac.builder, val,
3231 get_def_type(ctx, &instr->dest.ssa),
3232 "");
3233 }
3234 case nir_var_shader_out:
3235 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3236 return load_tess_varyings(ctx, instr, false);
3237 }
3238
3239 for (unsigned chan = comp; chan < ve + comp; chan++) {
3240 if (indir_index) {
3241 unsigned count = glsl_count_attribute_slots(
3242 instr->variables[0]->var->type, false);
3243 count -= chan / 4;
3244 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3245 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3246 stride, true, true);
3247
3248 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3249 tmp_vec,
3250 indir_index, "");
3251 } else {
3252 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3253 ctx->abi->outputs[idx + chan + const_index * stride],
3254 "");
3255 }
3256 }
3257 break;
3258 default:
3259 unreachable("unhandle variable mode");
3260 }
3261 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3262 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3263 }
3264
3265 static void
3266 visit_store_var(struct ac_nir_context *ctx,
3267 nir_intrinsic_instr *instr)
3268 {
3269 LLVMValueRef temp_ptr, value;
3270 int idx = instr->variables[0]->var->data.driver_location;
3271 unsigned comp = instr->variables[0]->var->data.location_frac;
3272 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3273 int writemask = instr->const_index[0] << comp;
3274 LLVMValueRef indir_index;
3275 unsigned const_index;
3276 get_deref_offset(ctx, instr->variables[0], false,
3277 NULL, NULL, &const_index, &indir_index);
3278
3279 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3280
3281 src = LLVMBuildBitCast(ctx->ac.builder, src,
3282 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3283 "");
3284
3285 writemask = widen_mask(writemask, 2);
3286 }
3287
3288 switch (instr->variables[0]->var->data.mode) {
3289 case nir_var_shader_out:
3290
3291 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3292 LLVMValueRef vertex_index = NULL;
3293 LLVMValueRef indir_index = NULL;
3294 unsigned const_index = 0;
3295 const unsigned location = instr->variables[0]->var->data.location;
3296 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3297 const unsigned comp = instr->variables[0]->var->data.location_frac;
3298 const bool is_patch = instr->variables[0]->var->data.patch;
3299 const bool is_compact = instr->variables[0]->var->data.compact;
3300
3301 get_deref_offset(ctx, instr->variables[0],
3302 false, NULL, is_patch ? NULL : &vertex_index,
3303 &const_index, &indir_index);
3304
3305 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3306 const_index, location, driver_location,
3307 src, comp, is_patch, is_compact, writemask);
3308 return;
3309 }
3310
3311 for (unsigned chan = 0; chan < 8; chan++) {
3312 int stride = 4;
3313 if (!(writemask & (1 << chan)))
3314 continue;
3315
3316 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3317
3318 if (instr->variables[0]->var->data.compact)
3319 stride = 1;
3320 if (indir_index) {
3321 unsigned count = glsl_count_attribute_slots(
3322 instr->variables[0]->var->type, false);
3323 count -= chan / 4;
3324 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3325 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3326 stride, true, true);
3327
3328 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3329 value, indir_index, "");
3330 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3331 count, stride, tmp_vec);
3332
3333 } else {
3334 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3335
3336 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3337 }
3338 }
3339 break;
3340 case nir_var_local:
3341 for (unsigned chan = 0; chan < 8; chan++) {
3342 if (!(writemask & (1 << chan)))
3343 continue;
3344
3345 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3346 if (indir_index) {
3347 unsigned count = glsl_count_attribute_slots(
3348 instr->variables[0]->var->type, false);
3349 count -= chan / 4;
3350 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3351 &ctx->ac, ctx->locals + idx + chan, count,
3352 4, true, true);
3353
3354 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3355 value, indir_index, "");
3356 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3357 count, 4, tmp_vec);
3358 } else {
3359 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3360
3361 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3362 }
3363 }
3364 break;
3365 case nir_var_shared: {
3366 int writemask = instr->const_index[0];
3367 LLVMValueRef address = build_gep_for_deref(ctx,
3368 instr->variables[0]);
3369 LLVMValueRef val = get_src(ctx, instr->src[0]);
3370 unsigned components =
3371 glsl_get_vector_elements(
3372 nir_deref_tail(&instr->variables[0]->deref)->type);
3373 if (writemask == (1 << components) - 1) {
3374 val = LLVMBuildBitCast(
3375 ctx->ac.builder, val,
3376 LLVMGetElementType(LLVMTypeOf(address)), "");
3377 LLVMBuildStore(ctx->ac.builder, val, address);
3378 } else {
3379 for (unsigned chan = 0; chan < 4; chan++) {
3380 if (!(writemask & (1 << chan)))
3381 continue;
3382 LLVMValueRef ptr =
3383 LLVMBuildStructGEP(ctx->ac.builder,
3384 address, chan, "");
3385 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3386 chan);
3387 src = LLVMBuildBitCast(
3388 ctx->ac.builder, src,
3389 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3390 LLVMBuildStore(ctx->ac.builder, src, ptr);
3391 }
3392 }
3393 break;
3394 }
3395 default:
3396 break;
3397 }
3398 }
3399
3400 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3401 {
3402 switch (dim) {
3403 case GLSL_SAMPLER_DIM_BUF:
3404 return 1;
3405 case GLSL_SAMPLER_DIM_1D:
3406 return array ? 2 : 1;
3407 case GLSL_SAMPLER_DIM_2D:
3408 return array ? 3 : 2;
3409 case GLSL_SAMPLER_DIM_MS:
3410 return array ? 4 : 3;
3411 case GLSL_SAMPLER_DIM_3D:
3412 case GLSL_SAMPLER_DIM_CUBE:
3413 return 3;
3414 case GLSL_SAMPLER_DIM_RECT:
3415 case GLSL_SAMPLER_DIM_SUBPASS:
3416 return 2;
3417 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3418 return 3;
3419 default:
3420 break;
3421 }
3422 return 0;
3423 }
3424
3425
3426
3427 /* Adjust the sample index according to FMASK.
3428 *
3429 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3430 * which is the identity mapping. Each nibble says which physical sample
3431 * should be fetched to get that sample.
3432 *
3433 * For example, 0x11111100 means there are only 2 samples stored and
3434 * the second sample covers 3/4 of the pixel. When reading samples 0
3435 * and 1, return physical sample 0 (determined by the first two 0s
3436 * in FMASK), otherwise return physical sample 1.
3437 *
3438 * The sample index should be adjusted as follows:
3439 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3440 */
3441 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3442 LLVMValueRef coord_x, LLVMValueRef coord_y,
3443 LLVMValueRef coord_z,
3444 LLVMValueRef sample_index,
3445 LLVMValueRef fmask_desc_ptr)
3446 {
3447 LLVMValueRef fmask_load_address[4];
3448 LLVMValueRef res;
3449
3450 fmask_load_address[0] = coord_x;
3451 fmask_load_address[1] = coord_y;
3452 if (coord_z) {
3453 fmask_load_address[2] = coord_z;
3454 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3455 }
3456
3457 struct ac_image_args args = {0};
3458
3459 args.opcode = ac_image_load;
3460 args.da = coord_z ? true : false;
3461 args.resource = fmask_desc_ptr;
3462 args.dmask = 0xf;
3463 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3464
3465 res = ac_build_image_opcode(ctx, &args);
3466
3467 res = ac_to_integer(ctx, res);
3468 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3469 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3470
3471 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3472 res,
3473 ctx->i32_0, "");
3474
3475 LLVMValueRef sample_index4 =
3476 LLVMBuildMul(ctx->builder, sample_index, four, "");
3477 LLVMValueRef shifted_fmask =
3478 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3479 LLVMValueRef final_sample =
3480 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3481
3482 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3483 * resource descriptor is 0 (invalid),
3484 */
3485 LLVMValueRef fmask_desc =
3486 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3487 ctx->v8i32, "");
3488
3489 LLVMValueRef fmask_word1 =
3490 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3491 ctx->i32_1, "");
3492
3493 LLVMValueRef word1_is_nonzero =
3494 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3495 fmask_word1, ctx->i32_0, "");
3496
3497 /* Replace the MSAA sample index. */
3498 sample_index =
3499 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3500 final_sample, sample_index, "");
3501 return sample_index;
3502 }
3503
3504 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3505 const nir_intrinsic_instr *instr)
3506 {
3507 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3508
3509 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3510 LLVMValueRef coords[4];
3511 LLVMValueRef masks[] = {
3512 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3513 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3514 };
3515 LLVMValueRef res;
3516 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3517
3518 int count;
3519 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3520 bool is_array = glsl_sampler_type_is_array(type);
3521 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3522 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3523 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3524 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3525 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3526 count = image_type_to_components_count(dim, is_array);
3527
3528 if (is_ms) {
3529 LLVMValueRef fmask_load_address[3];
3530 int chan;
3531
3532 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3533 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3534 if (is_array)
3535 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3536 else
3537 fmask_load_address[2] = NULL;
3538 if (add_frag_pos) {
3539 for (chan = 0; chan < 2; ++chan)
3540 fmask_load_address[chan] =
3541 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3542 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3543 ctx->ac.i32, ""), "");
3544 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3545 }
3546 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3547 fmask_load_address[0],
3548 fmask_load_address[1],
3549 fmask_load_address[2],
3550 sample_index,
3551 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3552 }
3553 if (count == 1 && !gfx9_1d) {
3554 if (instr->src[0].ssa->num_components)
3555 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3556 else
3557 res = src0;
3558 } else {
3559 int chan;
3560 if (is_ms)
3561 count--;
3562 for (chan = 0; chan < count; ++chan) {
3563 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3564 }
3565 if (add_frag_pos) {
3566 for (chan = 0; chan < 2; ++chan)
3567 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3568 ctx->ac.i32, ""), "");
3569 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3570 count++;
3571 }
3572
3573 if (gfx9_1d) {
3574 if (is_array) {
3575 coords[2] = coords[1];
3576 coords[1] = ctx->ac.i32_0;
3577 } else
3578 coords[1] = ctx->ac.i32_0;
3579 count++;
3580 }
3581
3582 if (is_ms) {
3583 coords[count] = sample_index;
3584 count++;
3585 }
3586
3587 if (count == 3) {
3588 coords[3] = LLVMGetUndef(ctx->ac.i32);
3589 count = 4;
3590 }
3591 res = ac_build_gather_values(&ctx->ac, coords, count);
3592 }
3593 return res;
3594 }
3595
3596 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3597 const nir_intrinsic_instr *instr)
3598 {
3599 LLVMValueRef params[7];
3600 LLVMValueRef res;
3601 char intrinsic_name[64];
3602 const nir_variable *var = instr->variables[0]->var;
3603 const struct glsl_type *type = var->type;
3604
3605 if(instr->variables[0]->deref.child)
3606 type = instr->variables[0]->deref.child->type;
3607
3608 type = glsl_without_array(type);
3609
3610 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3611 if (dim == GLSL_SAMPLER_DIM_BUF) {
3612 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3613 unsigned num_channels = util_last_bit(mask);
3614 LLVMValueRef rsrc, vindex;
3615
3616 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3617 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3618 ctx->ac.i32_0, "");
3619
3620 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3621 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3622 ctx->ac.i32_0, num_channels,
3623 false, false);
3624 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3625
3626 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3627 res = ac_to_integer(&ctx->ac, res);
3628 } else {
3629 bool is_da = glsl_sampler_type_is_array(type) ||
3630 dim == GLSL_SAMPLER_DIM_CUBE ||
3631 dim == GLSL_SAMPLER_DIM_3D ||
3632 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3633 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3634 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3635 LLVMValueRef glc = ctx->ac.i1false;
3636 LLVMValueRef slc = ctx->ac.i1false;
3637
3638 params[0] = get_image_coords(ctx, instr);
3639 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3640 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3641 params[3] = glc;
3642 params[4] = slc;
3643 params[5] = ctx->ac.i1false;
3644 params[6] = da;
3645
3646 ac_get_image_intr_name("llvm.amdgcn.image.load",
3647 ctx->ac.v4f32, /* vdata */
3648 LLVMTypeOf(params[0]), /* coords */
3649 LLVMTypeOf(params[1]), /* rsrc */
3650 intrinsic_name, sizeof(intrinsic_name));
3651
3652 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3653 params, 7, AC_FUNC_ATTR_READONLY);
3654 }
3655 return ac_to_integer(&ctx->ac, res);
3656 }
3657
3658 static void visit_image_store(struct ac_nir_context *ctx,
3659 nir_intrinsic_instr *instr)
3660 {
3661 LLVMValueRef params[8];
3662 char intrinsic_name[64];
3663 const nir_variable *var = instr->variables[0]->var;
3664 const struct glsl_type *type = glsl_without_array(var->type);
3665 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3666 LLVMValueRef glc = ctx->ac.i1false;
3667 bool force_glc = ctx->ac.chip_class == SI;
3668 if (force_glc)
3669 glc = ctx->ac.i1true;
3670
3671 if (dim == GLSL_SAMPLER_DIM_BUF) {
3672 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3673 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3674 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3675 ctx->ac.i32_0, ""); /* vindex */
3676 params[3] = ctx->ac.i32_0; /* voffset */
3677 params[4] = glc; /* glc */
3678 params[5] = ctx->ac.i1false; /* slc */
3679 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3680 params, 6, 0);
3681 } else {
3682 bool is_da = glsl_sampler_type_is_array(type) ||
3683 dim == GLSL_SAMPLER_DIM_CUBE ||
3684 dim == GLSL_SAMPLER_DIM_3D;
3685 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3686 LLVMValueRef slc = ctx->ac.i1false;
3687
3688 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3689 params[1] = get_image_coords(ctx, instr); /* coords */
3690 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3691 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3692 params[4] = glc;
3693 params[5] = slc;
3694 params[6] = ctx->ac.i1false;
3695 params[7] = da;
3696
3697 ac_get_image_intr_name("llvm.amdgcn.image.store",
3698 LLVMTypeOf(params[0]), /* vdata */
3699 LLVMTypeOf(params[1]), /* coords */
3700 LLVMTypeOf(params[2]), /* rsrc */
3701 intrinsic_name, sizeof(intrinsic_name));
3702
3703 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3704 params, 8, 0);
3705 }
3706
3707 }
3708
3709 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3710 const nir_intrinsic_instr *instr)
3711 {
3712 LLVMValueRef params[7];
3713 int param_count = 0;
3714 const nir_variable *var = instr->variables[0]->var;
3715
3716 const char *atomic_name;
3717 char intrinsic_name[41];
3718 const struct glsl_type *type = glsl_without_array(var->type);
3719 MAYBE_UNUSED int length;
3720
3721 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3722
3723 switch (instr->intrinsic) {
3724 case nir_intrinsic_image_atomic_add:
3725 atomic_name = "add";
3726 break;
3727 case nir_intrinsic_image_atomic_min:
3728 atomic_name = is_unsigned ? "umin" : "smin";
3729 break;
3730 case nir_intrinsic_image_atomic_max:
3731 atomic_name = is_unsigned ? "umax" : "smax";
3732 break;
3733 case nir_intrinsic_image_atomic_and:
3734 atomic_name = "and";
3735 break;
3736 case nir_intrinsic_image_atomic_or:
3737 atomic_name = "or";
3738 break;
3739 case nir_intrinsic_image_atomic_xor:
3740 atomic_name = "xor";
3741 break;
3742 case nir_intrinsic_image_atomic_exchange:
3743 atomic_name = "swap";
3744 break;
3745 case nir_intrinsic_image_atomic_comp_swap:
3746 atomic_name = "cmpswap";
3747 break;
3748 default:
3749 abort();
3750 }
3751
3752 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3753 params[param_count++] = get_src(ctx, instr->src[3]);
3754 params[param_count++] = get_src(ctx, instr->src[2]);
3755
3756 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3757 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3758 NULL, true, true);
3759 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3760 ctx->ac.i32_0, ""); /* vindex */
3761 params[param_count++] = ctx->ac.i32_0; /* voffset */
3762 params[param_count++] = ctx->ac.i1false; /* slc */
3763
3764 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3765 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3766 } else {
3767 char coords_type[8];
3768
3769 bool da = glsl_sampler_type_is_array(type) ||
3770 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3771
3772 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3773 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3774 NULL, true, true);
3775 params[param_count++] = ctx->ac.i1false; /* r128 */
3776 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3777 params[param_count++] = ctx->ac.i1false; /* slc */
3778
3779 build_int_type_name(LLVMTypeOf(coords),
3780 coords_type, sizeof(coords_type));
3781
3782 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3783 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3784 }
3785
3786 assert(length < sizeof(intrinsic_name));
3787 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3788 }
3789
3790 static LLVMValueRef visit_image_samples(struct ac_nir_context *ctx,
3791 const nir_intrinsic_instr *instr)
3792 {
3793 const nir_variable *var = instr->variables[0]->var;
3794 const struct glsl_type *type = glsl_without_array(var->type);
3795 bool da = glsl_sampler_type_is_array(type) ||
3796 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3797 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3798
3799 struct ac_image_args args = { 0 };
3800 args.da = da;
3801 args.dmask = 0xf;
3802 args.resource = get_sampler_desc(ctx, instr->variables[0],
3803 AC_DESC_IMAGE, NULL, true, false);
3804 args.opcode = ac_image_get_resinfo;
3805 args.addr = ctx->ac.i32_0;
3806
3807 return ac_build_image_opcode(&ctx->ac, &args);
3808 }
3809
3810 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3811 const nir_intrinsic_instr *instr)
3812 {
3813 LLVMValueRef res;
3814 const nir_variable *var = instr->variables[0]->var;
3815 const struct glsl_type *type = glsl_without_array(var->type);
3816 bool da = glsl_sampler_type_is_array(type) ||
3817 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3818 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_3D;
3819
3820 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3821 return get_buffer_size(ctx,
3822 get_sampler_desc(ctx, instr->variables[0],
3823 AC_DESC_BUFFER, NULL, true, false), true);
3824
3825 struct ac_image_args args = { 0 };
3826
3827 args.da = da;
3828 args.dmask = 0xf;
3829 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3830 args.opcode = ac_image_get_resinfo;
3831 args.addr = ctx->ac.i32_0;
3832
3833 res = ac_build_image_opcode(&ctx->ac, &args);
3834
3835 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3836
3837 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3838 glsl_sampler_type_is_array(type)) {
3839 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3840 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3841 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3842 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3843 }
3844 if (ctx->ac.chip_class >= GFX9 &&
3845 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3846 glsl_sampler_type_is_array(type)) {
3847 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3848 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3849 ctx->ac.i32_1, "");
3850
3851 }
3852 return res;
3853 }
3854
3855 #define NOOP_WAITCNT 0xf7f
3856 #define LGKM_CNT 0x07f
3857 #define VM_CNT 0xf70
3858
3859 static void emit_membar(struct ac_llvm_context *ac,
3860 const nir_intrinsic_instr *instr)
3861 {
3862 unsigned waitcnt = NOOP_WAITCNT;
3863
3864 switch (instr->intrinsic) {
3865 case nir_intrinsic_memory_barrier:
3866 case nir_intrinsic_group_memory_barrier:
3867 waitcnt &= VM_CNT & LGKM_CNT;
3868 break;
3869 case nir_intrinsic_memory_barrier_atomic_counter:
3870 case nir_intrinsic_memory_barrier_buffer:
3871 case nir_intrinsic_memory_barrier_image:
3872 waitcnt &= VM_CNT;
3873 break;
3874 case nir_intrinsic_memory_barrier_shared:
3875 waitcnt &= LGKM_CNT;
3876 break;
3877 default:
3878 break;
3879 }
3880 if (waitcnt != NOOP_WAITCNT)
3881 ac_build_waitcnt(ac, waitcnt);
3882 }
3883
3884 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3885 {
3886 /* SI only (thanks to a hw bug workaround):
3887 * The real barrier instruction isn’t needed, because an entire patch
3888 * always fits into a single wave.
3889 */
3890 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3891 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3892 return;
3893 }
3894 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3895 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3896 }
3897
3898 static void emit_discard(struct ac_nir_context *ctx,
3899 const nir_intrinsic_instr *instr)
3900 {
3901 LLVMValueRef cond;
3902
3903 if (instr->intrinsic == nir_intrinsic_discard_if) {
3904 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3905 get_src(ctx, instr->src[0]),
3906 ctx->ac.i32_0, "");
3907 } else {
3908 assert(instr->intrinsic == nir_intrinsic_discard);
3909 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3910 }
3911
3912 ac_build_kill_if_false(&ctx->ac, cond);
3913 }
3914
3915 static LLVMValueRef
3916 visit_load_helper_invocation(struct ac_nir_context *ctx)
3917 {
3918 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3919 "llvm.amdgcn.ps.live",
3920 ctx->ac.i1, NULL, 0,
3921 AC_FUNC_ATTR_READNONE);
3922 result = LLVMBuildNot(ctx->ac.builder, result, "");
3923 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3924 }
3925
3926 static LLVMValueRef
3927 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3928 {
3929 LLVMValueRef result;
3930 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3931 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3932 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3933
3934 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3935 }
3936
3937 static LLVMValueRef
3938 visit_load_shared(struct ac_nir_context *ctx,
3939 const nir_intrinsic_instr *instr)
3940 {
3941 LLVMValueRef values[4], derived_ptr, index, ret;
3942
3943 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3944
3945 for (int chan = 0; chan < instr->num_components; chan++) {
3946 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3947 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3948 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3949 }
3950
3951 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3952 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3953 }
3954
3955 static void
3956 visit_store_shared(struct ac_nir_context *ctx,
3957 const nir_intrinsic_instr *instr)
3958 {
3959 LLVMValueRef derived_ptr, data,index;
3960 LLVMBuilderRef builder = ctx->ac.builder;
3961
3962 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3963 LLVMValueRef src = get_src(ctx, instr->src[0]);
3964
3965 int writemask = nir_intrinsic_write_mask(instr);
3966 for (int chan = 0; chan < 4; chan++) {
3967 if (!(writemask & (1 << chan))) {
3968 continue;
3969 }
3970 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3971 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3972 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3973 LLVMBuildStore(builder, data, derived_ptr);
3974 }
3975 }
3976
3977 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3978 const nir_intrinsic_instr *instr,
3979 LLVMValueRef ptr)
3980 {
3981 LLVMValueRef result;
3982 LLVMValueRef src = get_src(ctx, instr->src[0]);
3983
3984 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3985 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3986 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3987 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3988 ptr, src, src1,
3989 LLVMAtomicOrderingSequentiallyConsistent,
3990 LLVMAtomicOrderingSequentiallyConsistent,
3991 false);
3992 } else {
3993 LLVMAtomicRMWBinOp op;
3994 switch (instr->intrinsic) {
3995 case nir_intrinsic_var_atomic_add:
3996 case nir_intrinsic_shared_atomic_add:
3997 op = LLVMAtomicRMWBinOpAdd;
3998 break;
3999 case nir_intrinsic_var_atomic_umin:
4000 case nir_intrinsic_shared_atomic_umin:
4001 op = LLVMAtomicRMWBinOpUMin;
4002 break;
4003 case nir_intrinsic_var_atomic_umax:
4004 case nir_intrinsic_shared_atomic_umax:
4005 op = LLVMAtomicRMWBinOpUMax;
4006 break;
4007 case nir_intrinsic_var_atomic_imin:
4008 case nir_intrinsic_shared_atomic_imin:
4009 op = LLVMAtomicRMWBinOpMin;
4010 break;
4011 case nir_intrinsic_var_atomic_imax:
4012 case nir_intrinsic_shared_atomic_imax:
4013 op = LLVMAtomicRMWBinOpMax;
4014 break;
4015 case nir_intrinsic_var_atomic_and:
4016 case nir_intrinsic_shared_atomic_and:
4017 op = LLVMAtomicRMWBinOpAnd;
4018 break;
4019 case nir_intrinsic_var_atomic_or:
4020 case nir_intrinsic_shared_atomic_or:
4021 op = LLVMAtomicRMWBinOpOr;
4022 break;
4023 case nir_intrinsic_var_atomic_xor:
4024 case nir_intrinsic_shared_atomic_xor:
4025 op = LLVMAtomicRMWBinOpXor;
4026 break;
4027 case nir_intrinsic_var_atomic_exchange:
4028 case nir_intrinsic_shared_atomic_exchange:
4029 op = LLVMAtomicRMWBinOpXchg;
4030 break;
4031 default:
4032 return NULL;
4033 }
4034
4035 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4036 LLVMAtomicOrderingSequentiallyConsistent,
4037 false);
4038 }
4039 return result;
4040 }
4041
4042 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4043 enum glsl_interp_mode interp, unsigned location)
4044 {
4045 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4046
4047 switch (interp) {
4048 case INTERP_MODE_FLAT:
4049 default:
4050 return NULL;
4051 case INTERP_MODE_SMOOTH:
4052 case INTERP_MODE_NONE:
4053 if (location == INTERP_CENTER)
4054 return ctx->persp_center;
4055 else if (location == INTERP_CENTROID)
4056 return ctx->persp_centroid;
4057 else if (location == INTERP_SAMPLE)
4058 return ctx->persp_sample;
4059 break;
4060 case INTERP_MODE_NOPERSPECTIVE:
4061 if (location == INTERP_CENTER)
4062 return ctx->linear_center;
4063 else if (location == INTERP_CENTROID)
4064 return ctx->linear_centroid;
4065 else if (location == INTERP_SAMPLE)
4066 return ctx->linear_sample;
4067 break;
4068 }
4069 return NULL;
4070 }
4071
4072 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4073 LLVMValueRef sample_id)
4074 {
4075 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4076
4077 LLVMValueRef result;
4078 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4079
4080 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4081 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4082
4083 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4084 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4085
4086 return result;
4087 }
4088
4089 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4090 {
4091 LLVMValueRef values[2];
4092
4093 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4094 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4095 return ac_build_gather_values(&ctx->ac, values, 2);
4096 }
4097
4098 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4099 {
4100 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4101 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4102 ctx->options->key.fs.log2_num_samples :
4103 ctx->options->key.fs.log2_ps_iter_samples;
4104
4105 /* The bit pattern matches that used by fixed function fragment
4106 * processing. */
4107 static const uint16_t ps_iter_masks[] = {
4108 0xffff, /* not used */
4109 0x5555,
4110 0x1111,
4111 0x0101,
4112 0x0001,
4113 };
4114 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4115
4116 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4117
4118 LLVMValueRef result, sample_id;
4119 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4120 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4121 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4122 return result;
4123 }
4124
4125 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4126 const nir_intrinsic_instr *instr)
4127 {
4128 LLVMValueRef result[4];
4129 LLVMValueRef interp_param, attr_number;
4130 unsigned location;
4131 unsigned chan;
4132 LLVMValueRef src_c0 = NULL;
4133 LLVMValueRef src_c1 = NULL;
4134 LLVMValueRef src0 = NULL;
4135 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4136 switch (instr->intrinsic) {
4137 case nir_intrinsic_interp_var_at_centroid:
4138 location = INTERP_CENTROID;
4139 break;
4140 case nir_intrinsic_interp_var_at_sample:
4141 case nir_intrinsic_interp_var_at_offset:
4142 location = INTERP_CENTER;
4143 src0 = get_src(ctx, instr->src[0]);
4144 break;
4145 default:
4146 break;
4147 }
4148
4149 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4150 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4151 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4152 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4153 LLVMValueRef sample_position;
4154 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4155
4156 /* fetch sample ID */
4157 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4158
4159 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4160 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4161 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4162 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4163 }
4164 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4165 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4166
4167 if (location == INTERP_CENTER) {
4168 LLVMValueRef ij_out[2];
4169 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4170
4171 /*
4172 * take the I then J parameters, and the DDX/Y for it, and
4173 * calculate the IJ inputs for the interpolator.
4174 * temp1 = ddx * offset/sample.x + I;
4175 * interp_param.I = ddy * offset/sample.y + temp1;
4176 * temp1 = ddx * offset/sample.x + J;
4177 * interp_param.J = ddy * offset/sample.y + temp1;
4178 */
4179 for (unsigned i = 0; i < 2; i++) {
4180 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4181 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4182 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4183 ddxy_out, ix_ll, "");
4184 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4185 ddxy_out, iy_ll, "");
4186 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4187 interp_param, ix_ll, "");
4188 LLVMValueRef temp1, temp2;
4189
4190 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4191 ctx->ac.f32, "");
4192
4193 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4194 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4195
4196 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4197 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4198
4199 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4200 temp2, ctx->ac.i32, "");
4201 }
4202 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4203
4204 }
4205
4206 for (chan = 0; chan < 4; chan++) {
4207 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4208
4209 if (interp_param) {
4210 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4211 interp_param, ctx->ac.v2f32, "");
4212 LLVMValueRef i = LLVMBuildExtractElement(
4213 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4214 LLVMValueRef j = LLVMBuildExtractElement(
4215 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4216
4217 result[chan] = ac_build_fs_interp(&ctx->ac,
4218 llvm_chan, attr_number,
4219 ctx->abi->prim_mask, i, j);
4220 } else {
4221 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4222 LLVMConstInt(ctx->ac.i32, 2, false),
4223 llvm_chan, attr_number,
4224 ctx->abi->prim_mask);
4225 }
4226 }
4227 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4228 instr->variables[0]->var->data.location_frac);
4229 }
4230
4231 static void
4232 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4233 {
4234 LLVMValueRef gs_next_vertex;
4235 LLVMValueRef can_emit;
4236 int idx;
4237 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4238
4239 assert(stream == 0);
4240
4241 /* Write vertex attribute values to GSVS ring */
4242 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4243 ctx->gs_next_vertex,
4244 "");
4245
4246 /* If this thread has already emitted the declared maximum number of
4247 * vertices, kill it: excessive vertex emissions are not supposed to
4248 * have any effect, and GS threads have no externally observable
4249 * effects other than emitting vertices.
4250 */
4251 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4252 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4253 ac_build_kill_if_false(&ctx->ac, can_emit);
4254
4255 /* loop num outputs */
4256 idx = 0;
4257 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4258 LLVMValueRef *out_ptr = &addrs[i * 4];
4259 int length = 4;
4260 int slot = idx;
4261 int slot_inc = 1;
4262
4263 if (!(ctx->output_mask & (1ull << i)))
4264 continue;
4265
4266 if (i == VARYING_SLOT_CLIP_DIST0) {
4267 /* pack clip and cull into a single set of slots */
4268 length = ctx->num_output_clips + ctx->num_output_culls;
4269 if (length > 4)
4270 slot_inc = 2;
4271 }
4272 for (unsigned j = 0; j < length; j++) {
4273 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4274 out_ptr[j], "");
4275 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4276 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4277 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4278
4279 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4280
4281 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4282 out_val, 1,
4283 voffset, ctx->gs2vs_offset, 0,
4284 1, 1, true, true);
4285 }
4286 idx += slot_inc;
4287 }
4288
4289 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4290 ctx->ac.i32_1, "");
4291 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4292
4293 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4294 }
4295
4296 static void
4297 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4298 {
4299 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4300 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4301 }
4302
4303 static LLVMValueRef
4304 load_tess_coord(struct ac_shader_abi *abi)
4305 {
4306 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4307
4308 LLVMValueRef coord[4] = {
4309 ctx->tes_u,
4310 ctx->tes_v,
4311 ctx->ac.f32_0,
4312 ctx->ac.f32_0,
4313 };
4314
4315 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4316 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4317 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4318
4319 return ac_build_gather_values(&ctx->ac, coord, 3);
4320 }
4321
4322 static LLVMValueRef
4323 load_patch_vertices_in(struct ac_shader_abi *abi)
4324 {
4325 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4326 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4327 }
4328
4329 static void visit_intrinsic(struct ac_nir_context *ctx,
4330 nir_intrinsic_instr *instr)
4331 {
4332 LLVMValueRef result = NULL;
4333
4334 switch (instr->intrinsic) {
4335 case nir_intrinsic_ballot:
4336 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4337 break;
4338 case nir_intrinsic_read_invocation:
4339 case nir_intrinsic_read_first_invocation: {
4340 LLVMValueRef args[2];
4341
4342 /* Value */
4343 args[0] = get_src(ctx, instr->src[0]);
4344
4345 unsigned num_args;
4346 const char *intr_name;
4347 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4348 num_args = 2;
4349 intr_name = "llvm.amdgcn.readlane";
4350
4351 /* Invocation */
4352 args[1] = get_src(ctx, instr->src[1]);
4353 } else {
4354 num_args = 1;
4355 intr_name = "llvm.amdgcn.readfirstlane";
4356 }
4357
4358 /* We currently have no other way to prevent LLVM from lifting the icmp
4359 * calls to a dominating basic block.
4360 */
4361 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4362
4363 result = ac_build_intrinsic(&ctx->ac, intr_name,
4364 ctx->ac.i32, args, num_args,
4365 AC_FUNC_ATTR_READNONE |
4366 AC_FUNC_ATTR_CONVERGENT);
4367 break;
4368 }
4369 case nir_intrinsic_load_subgroup_invocation:
4370 result = ac_get_thread_id(&ctx->ac);
4371 break;
4372 case nir_intrinsic_load_work_group_id: {
4373 LLVMValueRef values[3];
4374
4375 for (int i = 0; i < 3; i++) {
4376 values[i] = ctx->abi->workgroup_ids[i] ?
4377 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4378 }
4379
4380 result = ac_build_gather_values(&ctx->ac, values, 3);
4381 break;
4382 }
4383 case nir_intrinsic_load_base_vertex: {
4384 result = ctx->abi->base_vertex;
4385 break;
4386 }
4387 case nir_intrinsic_load_local_group_size:
4388 result = ctx->abi->load_local_group_size(ctx->abi);
4389 break;
4390 case nir_intrinsic_load_vertex_id_zero_base: {
4391 result = ctx->abi->vertex_id;
4392 break;
4393 }
4394 case nir_intrinsic_load_local_invocation_id: {
4395 result = ctx->abi->local_invocation_ids;
4396 break;
4397 }
4398 case nir_intrinsic_load_base_instance:
4399 result = ctx->abi->start_instance;
4400 break;
4401 case nir_intrinsic_load_draw_id:
4402 result = ctx->abi->draw_id;
4403 break;
4404 case nir_intrinsic_load_view_index:
4405 result = ctx->abi->view_index;
4406 break;
4407 case nir_intrinsic_load_invocation_id:
4408 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4409 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4410 else
4411 result = ctx->abi->gs_invocation_id;
4412 break;
4413 case nir_intrinsic_load_primitive_id:
4414 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4415 result = ctx->abi->gs_prim_id;
4416 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4417 result = ctx->abi->tcs_patch_id;
4418 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4419 result = ctx->abi->tes_patch_id;
4420 } else
4421 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4422 break;
4423 case nir_intrinsic_load_sample_id:
4424 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4425 break;
4426 case nir_intrinsic_load_sample_pos:
4427 result = load_sample_pos(ctx);
4428 break;
4429 case nir_intrinsic_load_sample_mask_in:
4430 result = ctx->abi->load_sample_mask_in(ctx->abi);
4431 break;
4432 case nir_intrinsic_load_frag_coord: {
4433 LLVMValueRef values[4] = {
4434 ctx->abi->frag_pos[0],
4435 ctx->abi->frag_pos[1],
4436 ctx->abi->frag_pos[2],
4437 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4438 };
4439 result = ac_build_gather_values(&ctx->ac, values, 4);
4440 break;
4441 }
4442 case nir_intrinsic_load_front_face:
4443 result = ctx->abi->front_face;
4444 break;
4445 case nir_intrinsic_load_helper_invocation:
4446 result = visit_load_helper_invocation(ctx);
4447 break;
4448 case nir_intrinsic_load_instance_id:
4449 result = ctx->abi->instance_id;
4450 break;
4451 case nir_intrinsic_load_num_work_groups:
4452 result = ctx->abi->num_work_groups;
4453 break;
4454 case nir_intrinsic_load_local_invocation_index:
4455 result = visit_load_local_invocation_index(ctx);
4456 break;
4457 case nir_intrinsic_load_push_constant:
4458 result = visit_load_push_constant(ctx, instr);
4459 break;
4460 case nir_intrinsic_vulkan_resource_index: {
4461 LLVMValueRef index = get_src(ctx, instr->src[0]);
4462 unsigned desc_set = nir_intrinsic_desc_set(instr);
4463 unsigned binding = nir_intrinsic_binding(instr);
4464
4465 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4466 binding);
4467 break;
4468 }
4469 case nir_intrinsic_vulkan_resource_reindex:
4470 result = visit_vulkan_resource_reindex(ctx, instr);
4471 break;
4472 case nir_intrinsic_store_ssbo:
4473 visit_store_ssbo(ctx, instr);
4474 break;
4475 case nir_intrinsic_load_ssbo:
4476 result = visit_load_buffer(ctx, instr);
4477 break;
4478 case nir_intrinsic_ssbo_atomic_add:
4479 case nir_intrinsic_ssbo_atomic_imin:
4480 case nir_intrinsic_ssbo_atomic_umin:
4481 case nir_intrinsic_ssbo_atomic_imax:
4482 case nir_intrinsic_ssbo_atomic_umax:
4483 case nir_intrinsic_ssbo_atomic_and:
4484 case nir_intrinsic_ssbo_atomic_or:
4485 case nir_intrinsic_ssbo_atomic_xor:
4486 case nir_intrinsic_ssbo_atomic_exchange:
4487 case nir_intrinsic_ssbo_atomic_comp_swap:
4488 result = visit_atomic_ssbo(ctx, instr);
4489 break;
4490 case nir_intrinsic_load_ubo:
4491 result = visit_load_ubo_buffer(ctx, instr);
4492 break;
4493 case nir_intrinsic_get_buffer_size:
4494 result = visit_get_buffer_size(ctx, instr);
4495 break;
4496 case nir_intrinsic_load_var:
4497 result = visit_load_var(ctx, instr);
4498 break;
4499 case nir_intrinsic_store_var:
4500 visit_store_var(ctx, instr);
4501 break;
4502 case nir_intrinsic_load_shared:
4503 result = visit_load_shared(ctx, instr);
4504 break;
4505 case nir_intrinsic_store_shared:
4506 visit_store_shared(ctx, instr);
4507 break;
4508 case nir_intrinsic_image_samples:
4509 result = visit_image_samples(ctx, instr);
4510 break;
4511 case nir_intrinsic_image_load:
4512 result = visit_image_load(ctx, instr);
4513 break;
4514 case nir_intrinsic_image_store:
4515 visit_image_store(ctx, instr);
4516 break;
4517 case nir_intrinsic_image_atomic_add:
4518 case nir_intrinsic_image_atomic_min:
4519 case nir_intrinsic_image_atomic_max:
4520 case nir_intrinsic_image_atomic_and:
4521 case nir_intrinsic_image_atomic_or:
4522 case nir_intrinsic_image_atomic_xor:
4523 case nir_intrinsic_image_atomic_exchange:
4524 case nir_intrinsic_image_atomic_comp_swap:
4525 result = visit_image_atomic(ctx, instr);
4526 break;
4527 case nir_intrinsic_image_size:
4528 result = visit_image_size(ctx, instr);
4529 break;
4530 case nir_intrinsic_shader_clock:
4531 result = ac_build_shader_clock(&ctx->ac);
4532 break;
4533 case nir_intrinsic_discard:
4534 case nir_intrinsic_discard_if:
4535 emit_discard(ctx, instr);
4536 break;
4537 case nir_intrinsic_memory_barrier:
4538 case nir_intrinsic_group_memory_barrier:
4539 case nir_intrinsic_memory_barrier_atomic_counter:
4540 case nir_intrinsic_memory_barrier_buffer:
4541 case nir_intrinsic_memory_barrier_image:
4542 case nir_intrinsic_memory_barrier_shared:
4543 emit_membar(&ctx->ac, instr);
4544 break;
4545 case nir_intrinsic_barrier:
4546 emit_barrier(&ctx->ac, ctx->stage);
4547 break;
4548 case nir_intrinsic_shared_atomic_add:
4549 case nir_intrinsic_shared_atomic_imin:
4550 case nir_intrinsic_shared_atomic_umin:
4551 case nir_intrinsic_shared_atomic_imax:
4552 case nir_intrinsic_shared_atomic_umax:
4553 case nir_intrinsic_shared_atomic_and:
4554 case nir_intrinsic_shared_atomic_or:
4555 case nir_intrinsic_shared_atomic_xor:
4556 case nir_intrinsic_shared_atomic_exchange:
4557 case nir_intrinsic_shared_atomic_comp_swap: {
4558 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
4559 result = visit_var_atomic(ctx, instr, ptr);
4560 break;
4561 }
4562 case nir_intrinsic_var_atomic_add:
4563 case nir_intrinsic_var_atomic_imin:
4564 case nir_intrinsic_var_atomic_umin:
4565 case nir_intrinsic_var_atomic_imax:
4566 case nir_intrinsic_var_atomic_umax:
4567 case nir_intrinsic_var_atomic_and:
4568 case nir_intrinsic_var_atomic_or:
4569 case nir_intrinsic_var_atomic_xor:
4570 case nir_intrinsic_var_atomic_exchange:
4571 case nir_intrinsic_var_atomic_comp_swap: {
4572 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4573 result = visit_var_atomic(ctx, instr, ptr);
4574 break;
4575 }
4576 case nir_intrinsic_interp_var_at_centroid:
4577 case nir_intrinsic_interp_var_at_sample:
4578 case nir_intrinsic_interp_var_at_offset:
4579 result = visit_interp(ctx, instr);
4580 break;
4581 case nir_intrinsic_emit_vertex:
4582 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4583 break;
4584 case nir_intrinsic_end_primitive:
4585 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4586 break;
4587 case nir_intrinsic_load_tess_coord:
4588 result = ctx->abi->load_tess_coord(ctx->abi);
4589 break;
4590 case nir_intrinsic_load_tess_level_outer:
4591 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4592 break;
4593 case nir_intrinsic_load_tess_level_inner:
4594 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4595 break;
4596 case nir_intrinsic_load_patch_vertices_in:
4597 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4598 break;
4599 case nir_intrinsic_vote_all: {
4600 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4601 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4602 break;
4603 }
4604 case nir_intrinsic_vote_any: {
4605 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4606 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4607 break;
4608 }
4609 case nir_intrinsic_vote_eq: {
4610 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4611 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4612 break;
4613 }
4614 default:
4615 fprintf(stderr, "Unknown intrinsic: ");
4616 nir_print_instr(&instr->instr, stderr);
4617 fprintf(stderr, "\n");
4618 break;
4619 }
4620 if (result) {
4621 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4622 }
4623 }
4624
4625 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4626 LLVMValueRef buffer_ptr, bool write)
4627 {
4628 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4629 LLVMValueRef result;
4630
4631 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4632
4633 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4634 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4635
4636 return result;
4637 }
4638
4639 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4640 {
4641 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4642 LLVMValueRef result;
4643
4644 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4645
4646 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4647 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4648
4649 return result;
4650 }
4651
4652 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4653 unsigned descriptor_set,
4654 unsigned base_index,
4655 unsigned constant_index,
4656 LLVMValueRef index,
4657 enum ac_descriptor_type desc_type,
4658 bool image, bool write)
4659 {
4660 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4661 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4662 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4663 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4664 unsigned offset = binding->offset;
4665 unsigned stride = binding->size;
4666 unsigned type_size;
4667 LLVMBuilderRef builder = ctx->ac.builder;
4668 LLVMTypeRef type;
4669
4670 assert(base_index < layout->binding_count);
4671
4672 switch (desc_type) {
4673 case AC_DESC_IMAGE:
4674 type = ctx->ac.v8i32;
4675 type_size = 32;
4676 break;
4677 case AC_DESC_FMASK:
4678 type = ctx->ac.v8i32;
4679 offset += 32;
4680 type_size = 32;
4681 break;
4682 case AC_DESC_SAMPLER:
4683 type = ctx->ac.v4i32;
4684 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4685 offset += 64;
4686
4687 type_size = 16;
4688 break;
4689 case AC_DESC_BUFFER:
4690 type = ctx->ac.v4i32;
4691 type_size = 16;
4692 break;
4693 default:
4694 unreachable("invalid desc_type\n");
4695 }
4696
4697 offset += constant_index * stride;
4698
4699 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4700 (!index || binding->immutable_samplers_equal)) {
4701 if (binding->immutable_samplers_equal)
4702 constant_index = 0;
4703
4704 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4705
4706 LLVMValueRef constants[] = {
4707 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4708 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4709 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4710 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4711 };
4712 return ac_build_gather_values(&ctx->ac, constants, 4);
4713 }
4714
4715 assert(stride % type_size == 0);
4716
4717 if (!index)
4718 index = ctx->ac.i32_0;
4719
4720 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4721
4722 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4723 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4724
4725 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4726 }
4727
4728 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4729 const nir_deref_var *deref,
4730 enum ac_descriptor_type desc_type,
4731 const nir_tex_instr *tex_instr,
4732 bool image, bool write)
4733 {
4734 LLVMValueRef index = NULL;
4735 unsigned constant_index = 0;
4736 unsigned descriptor_set;
4737 unsigned base_index;
4738
4739 if (!deref) {
4740 assert(tex_instr && !image);
4741 descriptor_set = 0;
4742 base_index = tex_instr->sampler_index;
4743 } else {
4744 const nir_deref *tail = &deref->deref;
4745 while (tail->child) {
4746 const nir_deref_array *child = nir_deref_as_array(tail->child);
4747 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4748
4749 if (!array_size)
4750 array_size = 1;
4751
4752 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4753
4754 if (child->deref_array_type == nir_deref_array_type_indirect) {
4755 LLVMValueRef indirect = get_src(ctx, child->indirect);
4756
4757 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4758 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4759
4760 if (!index)
4761 index = indirect;
4762 else
4763 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4764 }
4765
4766 constant_index += child->base_offset * array_size;
4767
4768 tail = &child->deref;
4769 }
4770 descriptor_set = deref->var->data.descriptor_set;
4771 base_index = deref->var->data.binding;
4772 }
4773
4774 return ctx->abi->load_sampler_desc(ctx->abi,
4775 descriptor_set,
4776 base_index,
4777 constant_index, index,
4778 desc_type, image, write);
4779 }
4780
4781 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4782 struct ac_image_args *args,
4783 const nir_tex_instr *instr,
4784 nir_texop op,
4785 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4786 LLVMValueRef *param, unsigned count,
4787 unsigned dmask)
4788 {
4789 unsigned is_rect = 0;
4790 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4791
4792 if (op == nir_texop_lod)
4793 da = false;
4794 /* Pad to power of two vector */
4795 while (count < util_next_power_of_two(count))
4796 param[count++] = LLVMGetUndef(ctx->i32);
4797
4798 if (count > 1)
4799 args->addr = ac_build_gather_values(ctx, param, count);
4800 else
4801 args->addr = param[0];
4802
4803 args->resource = res_ptr;
4804 args->sampler = samp_ptr;
4805
4806 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4807 args->addr = param[0];
4808 return;
4809 }
4810
4811 args->dmask = dmask;
4812 args->unorm = is_rect;
4813 args->da = da;
4814 }
4815
4816 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4817 *
4818 * SI-CI:
4819 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4820 * filtering manually. The driver sets img7 to a mask clearing
4821 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4822 * s_and_b32 samp0, samp0, img7
4823 *
4824 * VI:
4825 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4826 */
4827 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4828 LLVMValueRef res, LLVMValueRef samp)
4829 {
4830 LLVMBuilderRef builder = ctx->ac.builder;
4831 LLVMValueRef img7, samp0;
4832
4833 if (ctx->ac.chip_class >= VI)
4834 return samp;
4835
4836 img7 = LLVMBuildExtractElement(builder, res,
4837 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4838 samp0 = LLVMBuildExtractElement(builder, samp,
4839 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4840 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4841 return LLVMBuildInsertElement(builder, samp, samp0,
4842 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4843 }
4844
4845 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4846 nir_tex_instr *instr,
4847 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4848 LLVMValueRef *fmask_ptr)
4849 {
4850 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4851 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4852 else
4853 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4854 if (samp_ptr) {
4855 if (instr->sampler)
4856 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4857 else
4858 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4859 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4860 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4861 }
4862 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4863 instr->op == nir_texop_samples_identical))
4864 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4865 }
4866
4867 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4868 LLVMValueRef coord)
4869 {
4870 coord = ac_to_float(ctx, coord);
4871 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4872 coord = ac_to_integer(ctx, coord);
4873 return coord;
4874 }
4875
4876 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4877 {
4878 LLVMValueRef result = NULL;
4879 struct ac_image_args args = { 0 };
4880 unsigned dmask = 0xf;
4881 LLVMValueRef address[16];
4882 LLVMValueRef coords[5];
4883 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4884 LLVMValueRef bias = NULL, offsets = NULL;
4885 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4886 LLVMValueRef ddx = NULL, ddy = NULL;
4887 LLVMValueRef derivs[6];
4888 unsigned chan, count = 0;
4889 unsigned const_src = 0, num_deriv_comp = 0;
4890 bool lod_is_zero = false;
4891
4892 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4893
4894 for (unsigned i = 0; i < instr->num_srcs; i++) {
4895 switch (instr->src[i].src_type) {
4896 case nir_tex_src_coord:
4897 coord = get_src(ctx, instr->src[i].src);
4898 break;
4899 case nir_tex_src_projector:
4900 break;
4901 case nir_tex_src_comparator:
4902 comparator = get_src(ctx, instr->src[i].src);
4903 break;
4904 case nir_tex_src_offset:
4905 offsets = get_src(ctx, instr->src[i].src);
4906 const_src = i;
4907 break;
4908 case nir_tex_src_bias:
4909 bias = get_src(ctx, instr->src[i].src);
4910 break;
4911 case nir_tex_src_lod: {
4912 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4913
4914 if (val && val->i32[0] == 0)
4915 lod_is_zero = true;
4916 lod = get_src(ctx, instr->src[i].src);
4917 break;
4918 }
4919 case nir_tex_src_ms_index:
4920 sample_index = get_src(ctx, instr->src[i].src);
4921 break;
4922 case nir_tex_src_ms_mcs:
4923 break;
4924 case nir_tex_src_ddx:
4925 ddx = get_src(ctx, instr->src[i].src);
4926 num_deriv_comp = instr->src[i].src.ssa->num_components;
4927 break;
4928 case nir_tex_src_ddy:
4929 ddy = get_src(ctx, instr->src[i].src);
4930 break;
4931 case nir_tex_src_texture_offset:
4932 case nir_tex_src_sampler_offset:
4933 case nir_tex_src_plane:
4934 default:
4935 break;
4936 }
4937 }
4938
4939 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4940 result = get_buffer_size(ctx, res_ptr, true);
4941 goto write_result;
4942 }
4943
4944 if (instr->op == nir_texop_texture_samples) {
4945 LLVMValueRef res, samples, is_msaa;
4946 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4947 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4948 LLVMConstInt(ctx->ac.i32, 3, false), "");
4949 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4950 LLVMConstInt(ctx->ac.i32, 28, false), "");
4951 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4952 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4953 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4954 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4955
4956 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4957 LLVMConstInt(ctx->ac.i32, 16, false), "");
4958 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4959 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4960 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4961 samples, "");
4962 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4963 ctx->ac.i32_1, "");
4964 result = samples;
4965 goto write_result;
4966 }
4967
4968 if (coord)
4969 for (chan = 0; chan < instr->coord_components; chan++)
4970 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4971
4972 if (offsets && instr->op != nir_texop_txf) {
4973 LLVMValueRef offset[3], pack;
4974 for (chan = 0; chan < 3; ++chan)
4975 offset[chan] = ctx->ac.i32_0;
4976
4977 args.offset = true;
4978 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4979 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4980 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4981 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4982 if (chan)
4983 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4984 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4985 }
4986 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4987 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4988 address[count++] = pack;
4989
4990 }
4991 /* pack LOD bias value */
4992 if (instr->op == nir_texop_txb && bias) {
4993 address[count++] = bias;
4994 }
4995
4996 /* Pack depth comparison value */
4997 if (instr->is_shadow && comparator) {
4998 LLVMValueRef z = ac_to_float(&ctx->ac,
4999 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
5000
5001 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
5002 * so the depth comparison value isn't clamped for Z16 and
5003 * Z24 anymore. Do it manually here.
5004 *
5005 * It's unnecessary if the original texture format was
5006 * Z32_FLOAT, but we don't know that here.
5007 */
5008 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
5009 z = ac_build_clamp(&ctx->ac, z);
5010
5011 address[count++] = z;
5012 }
5013
5014 /* pack derivatives */
5015 if (ddx || ddy) {
5016 int num_src_deriv_channels, num_dest_deriv_channels;
5017 switch (instr->sampler_dim) {
5018 case GLSL_SAMPLER_DIM_3D:
5019 case GLSL_SAMPLER_DIM_CUBE:
5020 num_deriv_comp = 3;
5021 num_src_deriv_channels = 3;
5022 num_dest_deriv_channels = 3;
5023 break;
5024 case GLSL_SAMPLER_DIM_2D:
5025 default:
5026 num_src_deriv_channels = 2;
5027 num_dest_deriv_channels = 2;
5028 num_deriv_comp = 2;
5029 break;
5030 case GLSL_SAMPLER_DIM_1D:
5031 num_src_deriv_channels = 1;
5032 if (ctx->ac.chip_class >= GFX9) {
5033 num_dest_deriv_channels = 2;
5034 num_deriv_comp = 2;
5035 } else {
5036 num_dest_deriv_channels = 1;
5037 num_deriv_comp = 1;
5038 }
5039 break;
5040 }
5041
5042 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5043 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5044 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5045 }
5046 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5047 derivs[i] = ctx->ac.f32_0;
5048 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5049 }
5050 }
5051
5052 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5053 for (chan = 0; chan < instr->coord_components; chan++)
5054 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5055 if (instr->coord_components == 3)
5056 coords[3] = LLVMGetUndef(ctx->ac.f32);
5057 ac_prepare_cube_coords(&ctx->ac,
5058 instr->op == nir_texop_txd, instr->is_array,
5059 instr->op == nir_texop_lod, coords, derivs);
5060 if (num_deriv_comp)
5061 num_deriv_comp--;
5062 }
5063
5064 if (ddx || ddy) {
5065 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5066 address[count++] = derivs[i];
5067 }
5068
5069 /* Pack texture coordinates */
5070 if (coord) {
5071 address[count++] = coords[0];
5072 if (instr->coord_components > 1) {
5073 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5074 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5075 }
5076 address[count++] = coords[1];
5077 }
5078 if (instr->coord_components > 2) {
5079 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5080 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
5081 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
5082 instr->op != nir_texop_txf) {
5083 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5084 }
5085 address[count++] = coords[2];
5086 }
5087
5088 if (ctx->ac.chip_class >= GFX9) {
5089 LLVMValueRef filler;
5090 if (instr->op == nir_texop_txf)
5091 filler = ctx->ac.i32_0;
5092 else
5093 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5094
5095 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5096 /* No nir_texop_lod, because it does not take a slice
5097 * even with array textures. */
5098 if (instr->is_array && instr->op != nir_texop_lod ) {
5099 address[count] = address[count - 1];
5100 address[count - 1] = filler;
5101 count++;
5102 } else
5103 address[count++] = filler;
5104 }
5105 }
5106 }
5107
5108 /* Pack LOD */
5109 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5110 instr->op == nir_texop_txf)) {
5111 address[count++] = lod;
5112 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5113 address[count++] = sample_index;
5114 } else if(instr->op == nir_texop_txs) {
5115 count = 0;
5116 if (lod)
5117 address[count++] = lod;
5118 else
5119 address[count++] = ctx->ac.i32_0;
5120 }
5121
5122 for (chan = 0; chan < count; chan++) {
5123 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5124 address[chan], ctx->ac.i32, "");
5125 }
5126
5127 if (instr->op == nir_texop_samples_identical) {
5128 LLVMValueRef txf_address[4];
5129 struct ac_image_args txf_args = { 0 };
5130 unsigned txf_count = count;
5131 memcpy(txf_address, address, sizeof(txf_address));
5132
5133 if (!instr->is_array)
5134 txf_address[2] = ctx->ac.i32_0;
5135 txf_address[3] = ctx->ac.i32_0;
5136
5137 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5138 fmask_ptr, NULL,
5139 txf_address, txf_count, 0xf);
5140
5141 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5142
5143 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5144 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5145 goto write_result;
5146 }
5147
5148 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5149 instr->op != nir_texop_txs) {
5150 unsigned sample_chan = instr->is_array ? 3 : 2;
5151 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5152 address[0],
5153 address[1],
5154 instr->is_array ? address[2] : NULL,
5155 address[sample_chan],
5156 fmask_ptr);
5157 }
5158
5159 if (offsets && instr->op == nir_texop_txf) {
5160 nir_const_value *const_offset =
5161 nir_src_as_const_value(instr->src[const_src].src);
5162 int num_offsets = instr->src[const_src].src.ssa->num_components;
5163 assert(const_offset);
5164 num_offsets = MIN2(num_offsets, instr->coord_components);
5165 if (num_offsets > 2)
5166 address[2] = LLVMBuildAdd(ctx->ac.builder,
5167 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5168 if (num_offsets > 1)
5169 address[1] = LLVMBuildAdd(ctx->ac.builder,
5170 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5171 address[0] = LLVMBuildAdd(ctx->ac.builder,
5172 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5173
5174 }
5175
5176 /* TODO TG4 support */
5177 if (instr->op == nir_texop_tg4) {
5178 if (instr->is_shadow)
5179 dmask = 1;
5180 else
5181 dmask = 1 << instr->component;
5182 }
5183 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5184 res_ptr, samp_ptr, address, count, dmask);
5185
5186 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5187
5188 if (instr->op == nir_texop_query_levels)
5189 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5190 else if (instr->is_shadow && instr->is_new_style_shadow &&
5191 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5192 instr->op != nir_texop_tg4)
5193 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5194 else if (instr->op == nir_texop_txs &&
5195 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5196 instr->is_array) {
5197 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5198 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5199 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5200 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5201 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5202 } else if (ctx->ac.chip_class >= GFX9 &&
5203 instr->op == nir_texop_txs &&
5204 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5205 instr->is_array) {
5206 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5207 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5208 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5209 ctx->ac.i32_1, "");
5210 } else if (instr->dest.ssa.num_components != 4)
5211 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5212
5213 write_result:
5214 if (result) {
5215 assert(instr->dest.is_ssa);
5216 result = ac_to_integer(&ctx->ac, result);
5217 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5218 }
5219 }
5220
5221
5222 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5223 {
5224 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5225 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5226
5227 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5228 _mesa_hash_table_insert(ctx->phis, instr, result);
5229 }
5230
5231 static void visit_post_phi(struct ac_nir_context *ctx,
5232 nir_phi_instr *instr,
5233 LLVMValueRef llvm_phi)
5234 {
5235 nir_foreach_phi_src(src, instr) {
5236 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5237 LLVMValueRef llvm_src = get_src(ctx, src->src);
5238
5239 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5240 }
5241 }
5242
5243 static void phi_post_pass(struct ac_nir_context *ctx)
5244 {
5245 struct hash_entry *entry;
5246 hash_table_foreach(ctx->phis, entry) {
5247 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5248 (LLVMValueRef)entry->data);
5249 }
5250 }
5251
5252
5253 static void visit_ssa_undef(struct ac_nir_context *ctx,
5254 const nir_ssa_undef_instr *instr)
5255 {
5256 unsigned num_components = instr->def.num_components;
5257 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5258 LLVMValueRef undef;
5259
5260 if (num_components == 1)
5261 undef = LLVMGetUndef(type);
5262 else {
5263 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5264 }
5265 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5266 }
5267
5268 static void visit_jump(struct ac_nir_context *ctx,
5269 const nir_jump_instr *instr)
5270 {
5271 switch (instr->type) {
5272 case nir_jump_break:
5273 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5274 LLVMClearInsertionPosition(ctx->ac.builder);
5275 break;
5276 case nir_jump_continue:
5277 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5278 LLVMClearInsertionPosition(ctx->ac.builder);
5279 break;
5280 default:
5281 fprintf(stderr, "Unknown NIR jump instr: ");
5282 nir_print_instr(&instr->instr, stderr);
5283 fprintf(stderr, "\n");
5284 abort();
5285 }
5286 }
5287
5288 static void visit_cf_list(struct ac_nir_context *ctx,
5289 struct exec_list *list);
5290
5291 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5292 {
5293 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5294 nir_foreach_instr(instr, block)
5295 {
5296 switch (instr->type) {
5297 case nir_instr_type_alu:
5298 visit_alu(ctx, nir_instr_as_alu(instr));
5299 break;
5300 case nir_instr_type_load_const:
5301 visit_load_const(ctx, nir_instr_as_load_const(instr));
5302 break;
5303 case nir_instr_type_intrinsic:
5304 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5305 break;
5306 case nir_instr_type_tex:
5307 visit_tex(ctx, nir_instr_as_tex(instr));
5308 break;
5309 case nir_instr_type_phi:
5310 visit_phi(ctx, nir_instr_as_phi(instr));
5311 break;
5312 case nir_instr_type_ssa_undef:
5313 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5314 break;
5315 case nir_instr_type_jump:
5316 visit_jump(ctx, nir_instr_as_jump(instr));
5317 break;
5318 default:
5319 fprintf(stderr, "Unknown NIR instr type: ");
5320 nir_print_instr(instr, stderr);
5321 fprintf(stderr, "\n");
5322 abort();
5323 }
5324 }
5325
5326 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5327 }
5328
5329 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5330 {
5331 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5332
5333 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5334 LLVMBasicBlockRef merge_block =
5335 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5336 LLVMBasicBlockRef if_block =
5337 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5338 LLVMBasicBlockRef else_block = merge_block;
5339 if (!exec_list_is_empty(&if_stmt->else_list))
5340 else_block = LLVMAppendBasicBlockInContext(
5341 ctx->ac.context, fn, "");
5342
5343 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5344 ctx->ac.i32_0, "");
5345 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5346
5347 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5348 visit_cf_list(ctx, &if_stmt->then_list);
5349 if (LLVMGetInsertBlock(ctx->ac.builder))
5350 LLVMBuildBr(ctx->ac.builder, merge_block);
5351
5352 if (!exec_list_is_empty(&if_stmt->else_list)) {
5353 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5354 visit_cf_list(ctx, &if_stmt->else_list);
5355 if (LLVMGetInsertBlock(ctx->ac.builder))
5356 LLVMBuildBr(ctx->ac.builder, merge_block);
5357 }
5358
5359 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5360 }
5361
5362 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5363 {
5364 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5365 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5366 LLVMBasicBlockRef break_parent = ctx->break_block;
5367
5368 ctx->continue_block =
5369 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5370 ctx->break_block =
5371 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5372
5373 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5374 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5375 visit_cf_list(ctx, &loop->body);
5376
5377 if (LLVMGetInsertBlock(ctx->ac.builder))
5378 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5379 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5380
5381 ctx->continue_block = continue_parent;
5382 ctx->break_block = break_parent;
5383 }
5384
5385 static void visit_cf_list(struct ac_nir_context *ctx,
5386 struct exec_list *list)
5387 {
5388 foreach_list_typed(nir_cf_node, node, node, list)
5389 {
5390 switch (node->type) {
5391 case nir_cf_node_block:
5392 visit_block(ctx, nir_cf_node_as_block(node));
5393 break;
5394
5395 case nir_cf_node_if:
5396 visit_if(ctx, nir_cf_node_as_if(node));
5397 break;
5398
5399 case nir_cf_node_loop:
5400 visit_loop(ctx, nir_cf_node_as_loop(node));
5401 break;
5402
5403 default:
5404 assert(0);
5405 }
5406 }
5407 }
5408
5409 static void
5410 handle_vs_input_decl(struct radv_shader_context *ctx,
5411 struct nir_variable *variable)
5412 {
5413 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5414 LLVMValueRef t_offset;
5415 LLVMValueRef t_list;
5416 LLVMValueRef input;
5417 LLVMValueRef buffer_index;
5418 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5419 int idx = variable->data.location;
5420 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5421 uint8_t input_usage_mask =
5422 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5423 unsigned num_channels = util_last_bit(input_usage_mask);
5424
5425 variable->data.driver_location = idx * 4;
5426
5427 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5428 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5429 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5430 ctx->abi.start_instance, "");
5431 if (ctx->options->key.vs.as_ls) {
5432 ctx->shader_info->vs.vgpr_comp_cnt =
5433 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5434 } else {
5435 ctx->shader_info->vs.vgpr_comp_cnt =
5436 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5437 }
5438 } else
5439 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5440 ctx->abi.base_vertex, "");
5441 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5442
5443 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5444
5445 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5446 buffer_index,
5447 ctx->ac.i32_0,
5448 num_channels, false, true);
5449
5450 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5451
5452 for (unsigned chan = 0; chan < 4; chan++) {
5453 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5454 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5455 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5456 input, llvm_chan, ""));
5457 }
5458 }
5459 }
5460
5461 static void interp_fs_input(struct radv_shader_context *ctx,
5462 unsigned attr,
5463 LLVMValueRef interp_param,
5464 LLVMValueRef prim_mask,
5465 LLVMValueRef result[4])
5466 {
5467 LLVMValueRef attr_number;
5468 unsigned chan;
5469 LLVMValueRef i, j;
5470 bool interp = interp_param != NULL;
5471
5472 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5473
5474 /* fs.constant returns the param from the middle vertex, so it's not
5475 * really useful for flat shading. It's meant to be used for custom
5476 * interpolation (but the intrinsic can't fetch from the other two
5477 * vertices).
5478 *
5479 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5480 * to do the right thing. The only reason we use fs.constant is that
5481 * fs.interp cannot be used on integers, because they can be equal
5482 * to NaN.
5483 */
5484 if (interp) {
5485 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5486 ctx->ac.v2f32, "");
5487
5488 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5489 ctx->ac.i32_0, "");
5490 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5491 ctx->ac.i32_1, "");
5492 }
5493
5494 for (chan = 0; chan < 4; chan++) {
5495 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5496
5497 if (interp) {
5498 result[chan] = ac_build_fs_interp(&ctx->ac,
5499 llvm_chan,
5500 attr_number,
5501 prim_mask, i, j);
5502 } else {
5503 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5504 LLVMConstInt(ctx->ac.i32, 2, false),
5505 llvm_chan,
5506 attr_number,
5507 prim_mask);
5508 }
5509 }
5510 }
5511
5512 static void
5513 handle_fs_input_decl(struct radv_shader_context *ctx,
5514 struct nir_variable *variable)
5515 {
5516 int idx = variable->data.location;
5517 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5518 LLVMValueRef interp;
5519
5520 variable->data.driver_location = idx * 4;
5521 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5522
5523 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5524 unsigned interp_type;
5525 if (variable->data.sample)
5526 interp_type = INTERP_SAMPLE;
5527 else if (variable->data.centroid)
5528 interp_type = INTERP_CENTROID;
5529 else
5530 interp_type = INTERP_CENTER;
5531
5532 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5533 } else
5534 interp = NULL;
5535
5536 for (unsigned i = 0; i < attrib_count; ++i)
5537 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5538
5539 }
5540
5541 static void
5542 handle_vs_inputs(struct radv_shader_context *ctx,
5543 struct nir_shader *nir) {
5544 nir_foreach_variable(variable, &nir->inputs)
5545 handle_vs_input_decl(ctx, variable);
5546 }
5547
5548 static void
5549 prepare_interp_optimize(struct radv_shader_context *ctx,
5550 struct nir_shader *nir)
5551 {
5552 if (!ctx->options->key.fs.multisample)
5553 return;
5554
5555 bool uses_center = false;
5556 bool uses_centroid = false;
5557 nir_foreach_variable(variable, &nir->inputs) {
5558 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5559 variable->data.sample)
5560 continue;
5561
5562 if (variable->data.centroid)
5563 uses_centroid = true;
5564 else
5565 uses_center = true;
5566 }
5567
5568 if (uses_center && uses_centroid) {
5569 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5570 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5571 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5572 }
5573 }
5574
5575 static void
5576 handle_fs_inputs(struct radv_shader_context *ctx,
5577 struct nir_shader *nir)
5578 {
5579 prepare_interp_optimize(ctx, nir);
5580
5581 nir_foreach_variable(variable, &nir->inputs)
5582 handle_fs_input_decl(ctx, variable);
5583
5584 unsigned index = 0;
5585
5586 if (ctx->shader_info->info.ps.uses_input_attachments ||
5587 ctx->shader_info->info.needs_multiview_view_index)
5588 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5589
5590 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5591 LLVMValueRef interp_param;
5592 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5593
5594 if (!(ctx->input_mask & (1ull << i)))
5595 continue;
5596
5597 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5598 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5599 interp_param = *inputs;
5600 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5601 inputs);
5602
5603 if (!interp_param)
5604 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5605 ++index;
5606 } else if (i == VARYING_SLOT_POS) {
5607 for(int i = 0; i < 3; ++i)
5608 inputs[i] = ctx->abi.frag_pos[i];
5609
5610 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5611 ctx->abi.frag_pos[3]);
5612 }
5613 }
5614 ctx->shader_info->fs.num_interp = index;
5615 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5616 ctx->shader_info->fs.has_pcoord = true;
5617 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5618 ctx->shader_info->fs.prim_id_input = true;
5619 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5620 ctx->shader_info->fs.layer_input = true;
5621 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5622
5623 if (ctx->shader_info->info.needs_multiview_view_index)
5624 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5625 }
5626
5627 static LLVMValueRef
5628 ac_build_alloca(struct ac_llvm_context *ac,
5629 LLVMTypeRef type,
5630 const char *name)
5631 {
5632 LLVMBuilderRef builder = ac->builder;
5633 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5634 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5635 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5636 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5637 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5638 LLVMValueRef res;
5639
5640 if (first_instr) {
5641 LLVMPositionBuilderBefore(first_builder, first_instr);
5642 } else {
5643 LLVMPositionBuilderAtEnd(first_builder, first_block);
5644 }
5645
5646 res = LLVMBuildAlloca(first_builder, type, name);
5647 LLVMBuildStore(builder, LLVMConstNull(type), res);
5648
5649 LLVMDisposeBuilder(first_builder);
5650
5651 return res;
5652 }
5653
5654 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5655 LLVMTypeRef type,
5656 const char *name)
5657 {
5658 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5659 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5660 return ptr;
5661 }
5662
5663 static void
5664 scan_shader_output_decl(struct radv_shader_context *ctx,
5665 struct nir_variable *variable,
5666 struct nir_shader *shader,
5667 gl_shader_stage stage)
5668 {
5669 int idx = variable->data.location + variable->data.index;
5670 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5671 uint64_t mask_attribs;
5672
5673 variable->data.driver_location = idx * 4;
5674
5675 /* tess ctrl has it's own load/store paths for outputs */
5676 if (stage == MESA_SHADER_TESS_CTRL)
5677 return;
5678
5679 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5680 if (stage == MESA_SHADER_VERTEX ||
5681 stage == MESA_SHADER_TESS_EVAL ||
5682 stage == MESA_SHADER_GEOMETRY) {
5683 if (idx == VARYING_SLOT_CLIP_DIST0) {
5684 int length = shader->info.clip_distance_array_size +
5685 shader->info.cull_distance_array_size;
5686 if (stage == MESA_SHADER_VERTEX) {
5687 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5688 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5689 }
5690 if (stage == MESA_SHADER_TESS_EVAL) {
5691 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5692 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5693 }
5694
5695 if (length > 4)
5696 attrib_count = 2;
5697 else
5698 attrib_count = 1;
5699 mask_attribs = 1ull << idx;
5700 }
5701 }
5702
5703 ctx->output_mask |= mask_attribs;
5704 }
5705
5706 static void
5707 handle_shader_output_decl(struct ac_nir_context *ctx,
5708 struct nir_shader *nir,
5709 struct nir_variable *variable)
5710 {
5711 unsigned output_loc = variable->data.driver_location / 4;
5712 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5713
5714 /* tess ctrl has it's own load/store paths for outputs */
5715 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5716 return;
5717
5718 if (ctx->stage == MESA_SHADER_VERTEX ||
5719 ctx->stage == MESA_SHADER_TESS_EVAL ||
5720 ctx->stage == MESA_SHADER_GEOMETRY) {
5721 int idx = variable->data.location + variable->data.index;
5722 if (idx == VARYING_SLOT_CLIP_DIST0) {
5723 int length = nir->info.clip_distance_array_size +
5724 nir->info.cull_distance_array_size;
5725
5726 if (length > 4)
5727 attrib_count = 2;
5728 else
5729 attrib_count = 1;
5730 }
5731 }
5732
5733 for (unsigned i = 0; i < attrib_count; ++i) {
5734 for (unsigned chan = 0; chan < 4; chan++) {
5735 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5736 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5737 }
5738 }
5739 }
5740
5741 static LLVMTypeRef
5742 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5743 enum glsl_base_type type)
5744 {
5745 switch (type) {
5746 case GLSL_TYPE_INT:
5747 case GLSL_TYPE_UINT:
5748 case GLSL_TYPE_BOOL:
5749 case GLSL_TYPE_SUBROUTINE:
5750 return ac->i32;
5751 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5752 return ac->f32;
5753 case GLSL_TYPE_INT64:
5754 case GLSL_TYPE_UINT64:
5755 return ac->i64;
5756 case GLSL_TYPE_DOUBLE:
5757 return ac->f64;
5758 default:
5759 unreachable("unknown GLSL type");
5760 }
5761 }
5762
5763 static LLVMTypeRef
5764 glsl_to_llvm_type(struct ac_llvm_context *ac,
5765 const struct glsl_type *type)
5766 {
5767 if (glsl_type_is_scalar(type)) {
5768 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5769 }
5770
5771 if (glsl_type_is_vector(type)) {
5772 return LLVMVectorType(
5773 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5774 glsl_get_vector_elements(type));
5775 }
5776
5777 if (glsl_type_is_matrix(type)) {
5778 return LLVMArrayType(
5779 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5780 glsl_get_matrix_columns(type));
5781 }
5782
5783 if (glsl_type_is_array(type)) {
5784 return LLVMArrayType(
5785 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5786 glsl_get_length(type));
5787 }
5788
5789 assert(glsl_type_is_struct(type));
5790
5791 LLVMTypeRef member_types[glsl_get_length(type)];
5792
5793 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5794 member_types[i] =
5795 glsl_to_llvm_type(ac,
5796 glsl_get_struct_field(type, i));
5797 }
5798
5799 return LLVMStructTypeInContext(ac->context, member_types,
5800 glsl_get_length(type), false);
5801 }
5802
5803 static void
5804 setup_locals(struct ac_nir_context *ctx,
5805 struct nir_function *func)
5806 {
5807 int i, j;
5808 ctx->num_locals = 0;
5809 nir_foreach_variable(variable, &func->impl->locals) {
5810 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5811 variable->data.driver_location = ctx->num_locals * 4;
5812 variable->data.location_frac = 0;
5813 ctx->num_locals += attrib_count;
5814 }
5815 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5816 if (!ctx->locals)
5817 return;
5818
5819 for (i = 0; i < ctx->num_locals; i++) {
5820 for (j = 0; j < 4; j++) {
5821 ctx->locals[i * 4 + j] =
5822 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5823 }
5824 }
5825 }
5826
5827 static void
5828 setup_shared(struct ac_nir_context *ctx,
5829 struct nir_shader *nir)
5830 {
5831 nir_foreach_variable(variable, &nir->shared) {
5832 LLVMValueRef shared =
5833 LLVMAddGlobalInAddressSpace(
5834 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5835 variable->name ? variable->name : "",
5836 AC_LOCAL_ADDR_SPACE);
5837 _mesa_hash_table_insert(ctx->vars, variable, shared);
5838 }
5839 }
5840
5841 /* Initialize arguments for the shader export intrinsic */
5842 static void
5843 si_llvm_init_export_args(struct radv_shader_context *ctx,
5844 LLVMValueRef *values,
5845 unsigned target,
5846 struct ac_export_args *args)
5847 {
5848 /* Default is 0xf. Adjusted below depending on the format. */
5849 args->enabled_channels = 0xf;
5850
5851 /* Specify whether the EXEC mask represents the valid mask */
5852 args->valid_mask = 0;
5853
5854 /* Specify whether this is the last export */
5855 args->done = 0;
5856
5857 /* Specify the target we are exporting */
5858 args->target = target;
5859
5860 args->compr = false;
5861 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5862 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5863 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5864 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5865
5866 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5867 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5868 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5869 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5870 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5871 unsigned chan;
5872
5873 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5874 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5875 unsigned bits, bool hi) = NULL;
5876
5877 switch(col_format) {
5878 case V_028714_SPI_SHADER_ZERO:
5879 args->enabled_channels = 0; /* writemask */
5880 args->target = V_008DFC_SQ_EXP_NULL;
5881 break;
5882
5883 case V_028714_SPI_SHADER_32_R:
5884 args->enabled_channels = 1;
5885 args->out[0] = values[0];
5886 break;
5887
5888 case V_028714_SPI_SHADER_32_GR:
5889 args->enabled_channels = 0x3;
5890 args->out[0] = values[0];
5891 args->out[1] = values[1];
5892 break;
5893
5894 case V_028714_SPI_SHADER_32_AR:
5895 args->enabled_channels = 0x9;
5896 args->out[0] = values[0];
5897 args->out[3] = values[3];
5898 break;
5899
5900 case V_028714_SPI_SHADER_FP16_ABGR:
5901 packf = ac_build_cvt_pkrtz_f16;
5902 break;
5903
5904 case V_028714_SPI_SHADER_UNORM16_ABGR:
5905 packf = ac_build_cvt_pknorm_u16;
5906 break;
5907
5908 case V_028714_SPI_SHADER_SNORM16_ABGR:
5909 packf = ac_build_cvt_pknorm_i16;
5910 break;
5911
5912 case V_028714_SPI_SHADER_UINT16_ABGR:
5913 packi = ac_build_cvt_pk_u16;
5914 break;
5915
5916 case V_028714_SPI_SHADER_SINT16_ABGR:
5917 packi = ac_build_cvt_pk_i16;
5918 break;
5919
5920 default:
5921 case V_028714_SPI_SHADER_32_ABGR:
5922 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5923 break;
5924 }
5925
5926 /* Pack f16 or norm_i16/u16. */
5927 if (packf) {
5928 for (chan = 0; chan < 2; chan++) {
5929 LLVMValueRef pack_args[2] = {
5930 values[2 * chan],
5931 values[2 * chan + 1]
5932 };
5933 LLVMValueRef packed;
5934
5935 packed = packf(&ctx->ac, pack_args);
5936 args->out[chan] = ac_to_float(&ctx->ac, packed);
5937 }
5938 args->compr = 1; /* COMPR flag */
5939 }
5940
5941 /* Pack i16/u16. */
5942 if (packi) {
5943 for (chan = 0; chan < 2; chan++) {
5944 LLVMValueRef pack_args[2] = {
5945 ac_to_integer(&ctx->ac, values[2 * chan]),
5946 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5947 };
5948 LLVMValueRef packed;
5949
5950 packed = packi(&ctx->ac, pack_args,
5951 is_int8 ? 8 : is_int10 ? 10 : 16,
5952 chan == 1);
5953 args->out[chan] = ac_to_float(&ctx->ac, packed);
5954 }
5955 args->compr = 1; /* COMPR flag */
5956 }
5957 return;
5958 }
5959
5960 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5961
5962 for (unsigned i = 0; i < 4; ++i)
5963 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5964 }
5965
5966 static void
5967 radv_export_param(struct radv_shader_context *ctx, unsigned index,
5968 LLVMValueRef *values)
5969 {
5970 struct ac_export_args args;
5971
5972 si_llvm_init_export_args(ctx, values,
5973 V_008DFC_SQ_EXP_PARAM + index, &args);
5974 ac_build_export(&ctx->ac, &args);
5975 }
5976
5977 static LLVMValueRef
5978 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
5979 {
5980 LLVMValueRef output =
5981 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5982
5983 return LLVMBuildLoad(ctx->ac.builder, output, "");
5984 }
5985
5986 static void
5987 handle_vs_outputs_post(struct radv_shader_context *ctx,
5988 bool export_prim_id,
5989 struct ac_vs_output_info *outinfo)
5990 {
5991 uint32_t param_count = 0;
5992 unsigned target;
5993 unsigned pos_idx, num_pos_exports = 0;
5994 struct ac_export_args args, pos_args[4] = {};
5995 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5996 int i;
5997
5998 if (ctx->options->key.has_multiview_view_index) {
5999 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
6000 if(!*tmp_out) {
6001 for(unsigned i = 0; i < 4; ++i)
6002 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
6003 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
6004 }
6005
6006 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
6007 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
6008 }
6009
6010 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6011 sizeof(outinfo->vs_output_param_offset));
6012
6013 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
6014 LLVMValueRef slots[8];
6015 unsigned j;
6016
6017 if (outinfo->cull_dist_mask)
6018 outinfo->cull_dist_mask <<= ctx->num_output_clips;
6019
6020 i = VARYING_SLOT_CLIP_DIST0;
6021 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
6022 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6023
6024 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
6025 slots[i] = LLVMGetUndef(ctx->ac.f32);
6026
6027 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6028 target = V_008DFC_SQ_EXP_POS + 3;
6029 si_llvm_init_export_args(ctx, &slots[4], target, &args);
6030 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6031 &args, sizeof(args));
6032 }
6033
6034 target = V_008DFC_SQ_EXP_POS + 2;
6035 si_llvm_init_export_args(ctx, &slots[0], target, &args);
6036 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6037 &args, sizeof(args));
6038
6039 }
6040
6041 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6042 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6043 for (unsigned j = 0; j < 4; j++)
6044 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6045 }
6046 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6047
6048 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6049 outinfo->writes_pointsize = true;
6050 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6051 }
6052
6053 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6054 outinfo->writes_layer = true;
6055 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6056 }
6057
6058 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6059 outinfo->writes_viewport_index = true;
6060 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6061 }
6062
6063 if (outinfo->writes_pointsize ||
6064 outinfo->writes_layer ||
6065 outinfo->writes_viewport_index) {
6066 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6067 (outinfo->writes_layer == true ? 4 : 0));
6068 pos_args[1].valid_mask = 0;
6069 pos_args[1].done = 0;
6070 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6071 pos_args[1].compr = 0;
6072 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6073 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6074 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6075 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6076
6077 if (outinfo->writes_pointsize == true)
6078 pos_args[1].out[0] = psize_value;
6079 if (outinfo->writes_layer == true)
6080 pos_args[1].out[2] = layer_value;
6081 if (outinfo->writes_viewport_index == true) {
6082 if (ctx->options->chip_class >= GFX9) {
6083 /* GFX9 has the layer in out.z[10:0] and the viewport
6084 * index in out.z[19:16].
6085 */
6086 LLVMValueRef v = viewport_index_value;
6087 v = ac_to_integer(&ctx->ac, v);
6088 v = LLVMBuildShl(ctx->ac.builder, v,
6089 LLVMConstInt(ctx->ac.i32, 16, false),
6090 "");
6091 v = LLVMBuildOr(ctx->ac.builder, v,
6092 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6093
6094 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6095 pos_args[1].enabled_channels |= 1 << 2;
6096 } else {
6097 pos_args[1].out[3] = viewport_index_value;
6098 pos_args[1].enabled_channels |= 1 << 3;
6099 }
6100 }
6101 }
6102 for (i = 0; i < 4; i++) {
6103 if (pos_args[i].out[0])
6104 num_pos_exports++;
6105 }
6106
6107 pos_idx = 0;
6108 for (i = 0; i < 4; i++) {
6109 if (!pos_args[i].out[0])
6110 continue;
6111
6112 /* Specify the target we are exporting */
6113 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6114 if (pos_idx == num_pos_exports)
6115 pos_args[i].done = 1;
6116 ac_build_export(&ctx->ac, &pos_args[i]);
6117 }
6118
6119 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6120 LLVMValueRef values[4];
6121 if (!(ctx->output_mask & (1ull << i)))
6122 continue;
6123
6124 if (i != VARYING_SLOT_LAYER &&
6125 i != VARYING_SLOT_PRIMITIVE_ID &&
6126 i < VARYING_SLOT_VAR0)
6127 continue;
6128
6129 for (unsigned j = 0; j < 4; j++)
6130 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6131
6132 radv_export_param(ctx, param_count, values);
6133
6134 outinfo->vs_output_param_offset[i] = param_count++;
6135 }
6136
6137 if (export_prim_id) {
6138 LLVMValueRef values[4];
6139
6140 values[0] = ctx->vs_prim_id;
6141 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6142 ctx->shader_info->vs.vgpr_comp_cnt);
6143 for (unsigned j = 1; j < 4; j++)
6144 values[j] = ctx->ac.f32_0;
6145
6146 radv_export_param(ctx, param_count, values);
6147
6148 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6149 outinfo->export_prim_id = true;
6150 }
6151
6152 outinfo->pos_exports = num_pos_exports;
6153 outinfo->param_exports = param_count;
6154 }
6155
6156 static void
6157 handle_es_outputs_post(struct radv_shader_context *ctx,
6158 struct ac_es_output_info *outinfo)
6159 {
6160 int j;
6161 uint64_t max_output_written = 0;
6162 LLVMValueRef lds_base = NULL;
6163
6164 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6165 int param_index;
6166 int length = 4;
6167
6168 if (!(ctx->output_mask & (1ull << i)))
6169 continue;
6170
6171 if (i == VARYING_SLOT_CLIP_DIST0)
6172 length = ctx->num_output_clips + ctx->num_output_culls;
6173
6174 param_index = shader_io_get_unique_index(i);
6175
6176 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6177 }
6178
6179 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6180
6181 if (ctx->ac.chip_class >= GFX9) {
6182 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6183 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6184 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6185 LLVMConstInt(ctx->ac.i32, 24, false),
6186 LLVMConstInt(ctx->ac.i32, 4, false), false);
6187 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6188 LLVMBuildMul(ctx->ac.builder, wave_idx,
6189 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6190 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6191 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6192 }
6193
6194 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6195 LLVMValueRef dw_addr = NULL;
6196 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6197 int param_index;
6198 int length = 4;
6199
6200 if (!(ctx->output_mask & (1ull << i)))
6201 continue;
6202
6203 if (i == VARYING_SLOT_CLIP_DIST0)
6204 length = ctx->num_output_clips + ctx->num_output_culls;
6205
6206 param_index = shader_io_get_unique_index(i);
6207
6208 if (lds_base) {
6209 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6210 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6211 "");
6212 }
6213 for (j = 0; j < length; j++) {
6214 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6215 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6216
6217 if (ctx->ac.chip_class >= GFX9) {
6218 ac_lds_store(&ctx->ac, dw_addr,
6219 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6220 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6221 } else {
6222 ac_build_buffer_store_dword(&ctx->ac,
6223 ctx->esgs_ring,
6224 out_val, 1,
6225 NULL, ctx->es2gs_offset,
6226 (4 * param_index + j) * 4,
6227 1, 1, true, true);
6228 }
6229 }
6230 }
6231 }
6232
6233 static void
6234 handle_ls_outputs_post(struct radv_shader_context *ctx)
6235 {
6236 LLVMValueRef vertex_id = ctx->rel_auto_id;
6237 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6238 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6239 vertex_dw_stride, "");
6240
6241 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6242 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6243 int length = 4;
6244
6245 if (!(ctx->output_mask & (1ull << i)))
6246 continue;
6247
6248 if (i == VARYING_SLOT_CLIP_DIST0)
6249 length = ctx->num_output_clips + ctx->num_output_culls;
6250 int param = shader_io_get_unique_index(i);
6251 mark_tess_output(ctx, false, param);
6252 if (length > 4)
6253 mark_tess_output(ctx, false, param + 1);
6254 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6255 LLVMConstInt(ctx->ac.i32, param * 4, false),
6256 "");
6257 for (unsigned j = 0; j < length; j++) {
6258 ac_lds_store(&ctx->ac, dw_addr,
6259 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6260 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6261 }
6262 }
6263 }
6264
6265 struct ac_build_if_state
6266 {
6267 struct radv_shader_context *ctx;
6268 LLVMValueRef condition;
6269 LLVMBasicBlockRef entry_block;
6270 LLVMBasicBlockRef true_block;
6271 LLVMBasicBlockRef false_block;
6272 LLVMBasicBlockRef merge_block;
6273 };
6274
6275 static LLVMBasicBlockRef
6276 ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
6277 {
6278 LLVMBasicBlockRef current_block;
6279 LLVMBasicBlockRef next_block;
6280 LLVMBasicBlockRef new_block;
6281
6282 /* get current basic block */
6283 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6284
6285 /* chqeck if there's another block after this one */
6286 next_block = LLVMGetNextBasicBlock(current_block);
6287 if (next_block) {
6288 /* insert the new block before the next block */
6289 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6290 }
6291 else {
6292 /* append new block after current block */
6293 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6294 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6295 }
6296 return new_block;
6297 }
6298
6299 static void
6300 ac_nir_build_if(struct ac_build_if_state *ifthen,
6301 struct radv_shader_context *ctx,
6302 LLVMValueRef condition)
6303 {
6304 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6305
6306 memset(ifthen, 0, sizeof *ifthen);
6307 ifthen->ctx = ctx;
6308 ifthen->condition = condition;
6309 ifthen->entry_block = block;
6310
6311 /* create endif/merge basic block for the phi functions */
6312 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6313
6314 /* create/insert true_block before merge_block */
6315 ifthen->true_block =
6316 LLVMInsertBasicBlockInContext(ctx->context,
6317 ifthen->merge_block,
6318 "if-true-block");
6319
6320 /* successive code goes into the true block */
6321 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6322 }
6323
6324 /**
6325 * End a conditional.
6326 */
6327 static void
6328 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6329 {
6330 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6331
6332 /* Insert branch to the merge block from current block */
6333 LLVMBuildBr(builder, ifthen->merge_block);
6334
6335 /*
6336 * Now patch in the various branch instructions.
6337 */
6338
6339 /* Insert the conditional branch instruction at the end of entry_block */
6340 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6341 if (ifthen->false_block) {
6342 /* we have an else clause */
6343 LLVMBuildCondBr(builder, ifthen->condition,
6344 ifthen->true_block, ifthen->false_block);
6345 }
6346 else {
6347 /* no else clause */
6348 LLVMBuildCondBr(builder, ifthen->condition,
6349 ifthen->true_block, ifthen->merge_block);
6350 }
6351
6352 /* Resume building code at end of the ifthen->merge_block */
6353 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6354 }
6355
6356 static void
6357 write_tess_factors(struct radv_shader_context *ctx)
6358 {
6359 unsigned stride, outer_comps, inner_comps;
6360 struct ac_build_if_state if_ctx, inner_if_ctx;
6361 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6362 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6363 unsigned tess_inner_index = 0, tess_outer_index;
6364 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
6365 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6366 int i;
6367 emit_barrier(&ctx->ac, ctx->stage);
6368
6369 switch (ctx->options->key.tcs.primitive_mode) {
6370 case GL_ISOLINES:
6371 stride = 2;
6372 outer_comps = 2;
6373 inner_comps = 0;
6374 break;
6375 case GL_TRIANGLES:
6376 stride = 4;
6377 outer_comps = 3;
6378 inner_comps = 1;
6379 break;
6380 case GL_QUADS:
6381 stride = 6;
6382 outer_comps = 4;
6383 inner_comps = 2;
6384 break;
6385 default:
6386 return;
6387 }
6388
6389 ac_nir_build_if(&if_ctx, ctx,
6390 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6391 invocation_id, ctx->ac.i32_0, ""));
6392
6393 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6394
6395 if (inner_comps) {
6396 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6397 mark_tess_output(ctx, true, tess_inner_index);
6398 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6399 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6400 }
6401
6402 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6403 mark_tess_output(ctx, true, tess_outer_index);
6404 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6405 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6406
6407 for (i = 0; i < 4; i++) {
6408 inner[i] = LLVMGetUndef(ctx->ac.i32);
6409 outer[i] = LLVMGetUndef(ctx->ac.i32);
6410 }
6411
6412 // LINES reverseal
6413 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6414 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6415 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6416 ctx->ac.i32_1, "");
6417 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6418 } else {
6419 for (i = 0; i < outer_comps; i++) {
6420 outer[i] = out[i] =
6421 ac_lds_load(&ctx->ac, lds_outer);
6422 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6423 ctx->ac.i32_1, "");
6424 }
6425 for (i = 0; i < inner_comps; i++) {
6426 inner[i] = out[outer_comps+i] =
6427 ac_lds_load(&ctx->ac, lds_inner);
6428 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6429 ctx->ac.i32_1, "");
6430 }
6431 }
6432
6433 /* Convert the outputs to vectors for stores. */
6434 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6435 vec1 = NULL;
6436
6437 if (stride > 4)
6438 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6439
6440
6441 buffer = ctx->hs_ring_tess_factor;
6442 tf_base = ctx->tess_factor_offset;
6443 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6444 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6445 unsigned tf_offset = 0;
6446
6447 if (ctx->options->chip_class <= VI) {
6448 ac_nir_build_if(&inner_if_ctx, ctx,
6449 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6450 rel_patch_id, ctx->ac.i32_0, ""));
6451
6452 /* Store the dynamic HS control word. */
6453 ac_build_buffer_store_dword(&ctx->ac, buffer,
6454 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6455 1, ctx->ac.i32_0, tf_base,
6456 0, 1, 0, true, false);
6457 tf_offset += 4;
6458
6459 ac_nir_build_endif(&inner_if_ctx);
6460 }
6461
6462 /* Store the tessellation factors. */
6463 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6464 MIN2(stride, 4), byteoffset, tf_base,
6465 tf_offset, 1, 0, true, false);
6466 if (vec1)
6467 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6468 stride - 4, byteoffset, tf_base,
6469 16 + tf_offset, 1, 0, true, false);
6470
6471 //store to offchip for TES to read - only if TES reads them
6472 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6473 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6474 LLVMValueRef tf_inner_offset;
6475 unsigned param_outer, param_inner;
6476
6477 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6478 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6479 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6480
6481 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6482 util_next_power_of_two(outer_comps));
6483
6484 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6485 outer_comps, tf_outer_offset,
6486 ctx->oc_lds, 0, 1, 0, true, false);
6487 if (inner_comps) {
6488 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6489 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6490 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6491
6492 inner_vec = inner_comps == 1 ? inner[0] :
6493 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6494 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6495 inner_comps, tf_inner_offset,
6496 ctx->oc_lds, 0, 1, 0, true, false);
6497 }
6498 }
6499 ac_nir_build_endif(&if_ctx);
6500 }
6501
6502 static void
6503 handle_tcs_outputs_post(struct radv_shader_context *ctx)
6504 {
6505 write_tess_factors(ctx);
6506 }
6507
6508 static bool
6509 si_export_mrt_color(struct radv_shader_context *ctx,
6510 LLVMValueRef *color, unsigned index, bool is_last,
6511 struct ac_export_args *args)
6512 {
6513 /* Export */
6514 si_llvm_init_export_args(ctx, color,
6515 V_008DFC_SQ_EXP_MRT + index, args);
6516
6517 if (is_last) {
6518 args->valid_mask = 1; /* whether the EXEC mask is valid */
6519 args->done = 1; /* DONE bit */
6520 } else if (!args->enabled_channels)
6521 return false; /* unnecessary NULL export */
6522
6523 return true;
6524 }
6525
6526 static void
6527 radv_export_mrt_z(struct radv_shader_context *ctx,
6528 LLVMValueRef depth, LLVMValueRef stencil,
6529 LLVMValueRef samplemask)
6530 {
6531 struct ac_export_args args;
6532
6533 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6534
6535 ac_build_export(&ctx->ac, &args);
6536 }
6537
6538 static void
6539 handle_fs_outputs_post(struct radv_shader_context *ctx)
6540 {
6541 unsigned index = 0;
6542 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6543 struct ac_export_args color_args[8];
6544
6545 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6546 LLVMValueRef values[4];
6547 bool last = false;
6548
6549 if (!(ctx->output_mask & (1ull << i)))
6550 continue;
6551
6552 if (i < FRAG_RESULT_DATA0)
6553 continue;
6554
6555 for (unsigned j = 0; j < 4; j++)
6556 values[j] = ac_to_float(&ctx->ac,
6557 radv_load_output(ctx, i, j));
6558
6559 if (!ctx->shader_info->info.ps.writes_z &&
6560 !ctx->shader_info->info.ps.writes_stencil &&
6561 !ctx->shader_info->info.ps.writes_sample_mask)
6562 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6563
6564 bool ret = si_export_mrt_color(ctx, values,
6565 i - FRAG_RESULT_DATA0,
6566 last, &color_args[index]);
6567 if (ret)
6568 index++;
6569 }
6570
6571 /* Process depth, stencil, samplemask. */
6572 if (ctx->shader_info->info.ps.writes_z) {
6573 depth = ac_to_float(&ctx->ac,
6574 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6575 }
6576 if (ctx->shader_info->info.ps.writes_stencil) {
6577 stencil = ac_to_float(&ctx->ac,
6578 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6579 }
6580 if (ctx->shader_info->info.ps.writes_sample_mask) {
6581 samplemask = ac_to_float(&ctx->ac,
6582 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6583 }
6584
6585 /* Export PS outputs. */
6586 for (unsigned i = 0; i < index; i++)
6587 ac_build_export(&ctx->ac, &color_args[i]);
6588
6589 if (depth || stencil || samplemask)
6590 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6591 else if (!index)
6592 ac_build_export_null(&ctx->ac);
6593 }
6594
6595 static void
6596 emit_gs_epilogue(struct radv_shader_context *ctx)
6597 {
6598 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6599 }
6600
6601 static void
6602 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6603 LLVMValueRef *addrs)
6604 {
6605 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
6606
6607 switch (ctx->stage) {
6608 case MESA_SHADER_VERTEX:
6609 if (ctx->options->key.vs.as_ls)
6610 handle_ls_outputs_post(ctx);
6611 else if (ctx->options->key.vs.as_es)
6612 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6613 else
6614 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6615 &ctx->shader_info->vs.outinfo);
6616 break;
6617 case MESA_SHADER_FRAGMENT:
6618 handle_fs_outputs_post(ctx);
6619 break;
6620 case MESA_SHADER_GEOMETRY:
6621 emit_gs_epilogue(ctx);
6622 break;
6623 case MESA_SHADER_TESS_CTRL:
6624 handle_tcs_outputs_post(ctx);
6625 break;
6626 case MESA_SHADER_TESS_EVAL:
6627 if (ctx->options->key.tes.as_es)
6628 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6629 else
6630 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6631 &ctx->shader_info->tes.outinfo);
6632 break;
6633 default:
6634 break;
6635 }
6636 }
6637
6638 static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
6639 {
6640 LLVMPassManagerRef passmgr;
6641 /* Create the pass manager */
6642 passmgr = LLVMCreateFunctionPassManagerForModule(
6643 ctx->ac.module);
6644
6645 /* This pass should eliminate all the load and store instructions */
6646 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6647
6648 /* Add some optimization passes */
6649 LLVMAddScalarReplAggregatesPass(passmgr);
6650 LLVMAddLICMPass(passmgr);
6651 LLVMAddAggressiveDCEPass(passmgr);
6652 LLVMAddCFGSimplificationPass(passmgr);
6653 LLVMAddInstructionCombiningPass(passmgr);
6654
6655 /* Run the pass */
6656 LLVMInitializeFunctionPassManager(passmgr);
6657 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6658 LLVMFinalizeFunctionPassManager(passmgr);
6659
6660 LLVMDisposeBuilder(ctx->ac.builder);
6661 LLVMDisposePassManager(passmgr);
6662 }
6663
6664 static void
6665 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
6666 {
6667 struct ac_vs_output_info *outinfo;
6668
6669 switch (ctx->stage) {
6670 case MESA_SHADER_FRAGMENT:
6671 case MESA_SHADER_COMPUTE:
6672 case MESA_SHADER_TESS_CTRL:
6673 case MESA_SHADER_GEOMETRY:
6674 return;
6675 case MESA_SHADER_VERTEX:
6676 if (ctx->options->key.vs.as_ls ||
6677 ctx->options->key.vs.as_es)
6678 return;
6679 outinfo = &ctx->shader_info->vs.outinfo;
6680 break;
6681 case MESA_SHADER_TESS_EVAL:
6682 if (ctx->options->key.vs.as_es)
6683 return;
6684 outinfo = &ctx->shader_info->tes.outinfo;
6685 break;
6686 default:
6687 unreachable("Unhandled shader type");
6688 }
6689
6690 ac_optimize_vs_outputs(&ctx->ac,
6691 ctx->main_function,
6692 outinfo->vs_output_param_offset,
6693 VARYING_SLOT_MAX,
6694 &outinfo->param_exports);
6695 }
6696
6697 static void
6698 ac_setup_rings(struct radv_shader_context *ctx)
6699 {
6700 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6701 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6702 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6703 }
6704
6705 if (ctx->is_gs_copy_shader) {
6706 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6707 }
6708 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6709 LLVMValueRef tmp;
6710 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6711 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6712
6713 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6714
6715 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6716 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6717 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6718 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6719 }
6720
6721 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6722 ctx->stage == MESA_SHADER_TESS_EVAL) {
6723 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6724 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6725 }
6726 }
6727
6728 static unsigned
6729 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6730 const struct nir_shader *nir)
6731 {
6732 switch (nir->info.stage) {
6733 case MESA_SHADER_TESS_CTRL:
6734 return chip_class >= CIK ? 128 : 64;
6735 case MESA_SHADER_GEOMETRY:
6736 return chip_class >= GFX9 ? 128 : 64;
6737 case MESA_SHADER_COMPUTE:
6738 break;
6739 default:
6740 return 0;
6741 }
6742
6743 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6744 nir->info.cs.local_size[1] *
6745 nir->info.cs.local_size[2];
6746 return max_workgroup_size;
6747 }
6748
6749 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6750 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
6751 {
6752 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6753 LLVMConstInt(ctx->ac.i32, 8, false),
6754 LLVMConstInt(ctx->ac.i32, 8, false), false);
6755 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6756 ctx->ac.i32_0, "");
6757 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6758 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6759 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6760 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6761 }
6762
6763 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
6764 {
6765 for(int i = 5; i >= 0; --i) {
6766 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6767 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6768 LLVMConstInt(ctx->ac.i32, 16, false), false);
6769 }
6770
6771 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6772 LLVMConstInt(ctx->ac.i32, 16, false),
6773 LLVMConstInt(ctx->ac.i32, 8, false), false);
6774 }
6775
6776 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6777 struct nir_shader *nir)
6778 {
6779 struct ac_nir_context ctx = {};
6780 struct nir_function *func;
6781
6782 ctx.ac = *ac;
6783 ctx.abi = abi;
6784
6785 ctx.stage = nir->info.stage;
6786
6787 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6788
6789 nir_foreach_variable(variable, &nir->outputs)
6790 handle_shader_output_decl(&ctx, nir, variable);
6791
6792 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6793 _mesa_key_pointer_equal);
6794 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6795 _mesa_key_pointer_equal);
6796 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6797 _mesa_key_pointer_equal);
6798
6799 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6800
6801 setup_locals(&ctx, func);
6802
6803 if (nir->info.stage == MESA_SHADER_COMPUTE)
6804 setup_shared(&ctx, nir);
6805
6806 visit_cf_list(&ctx, &func->impl->body);
6807 phi_post_pass(&ctx);
6808
6809 if (nir->info.stage != MESA_SHADER_COMPUTE)
6810 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6811 ctx.abi->outputs);
6812
6813 free(ctx.locals);
6814 ralloc_free(ctx.defs);
6815 ralloc_free(ctx.phis);
6816 ralloc_free(ctx.vars);
6817 }
6818
6819 static
6820 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6821 struct nir_shader *const *shaders,
6822 int shader_count,
6823 struct ac_shader_variant_info *shader_info,
6824 const struct ac_nir_compiler_options *options)
6825 {
6826 struct radv_shader_context ctx = {0};
6827 unsigned i;
6828 ctx.options = options;
6829 ctx.shader_info = shader_info;
6830 ctx.context = LLVMContextCreate();
6831
6832 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6833 options->family);
6834 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6835 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6836
6837 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6838 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6839 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6840 LLVMDisposeTargetData(data_layout);
6841 LLVMDisposeMessage(data_layout_str);
6842
6843 enum ac_float_mode float_mode =
6844 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6845 AC_FLOAT_MODE_DEFAULT;
6846
6847 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6848
6849 memset(shader_info, 0, sizeof(*shader_info));
6850
6851 for(int i = 0; i < shader_count; ++i)
6852 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6853
6854 for (i = 0; i < AC_UD_MAX_SETS; i++)
6855 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6856 for (i = 0; i < AC_UD_MAX_UD; i++)
6857 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6858
6859 ctx.max_workgroup_size = 0;
6860 for (int i = 0; i < shader_count; ++i) {
6861 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6862 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6863 shaders[i]));
6864 }
6865
6866 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6867 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6868
6869 ctx.abi.inputs = &ctx.inputs[0];
6870 ctx.abi.emit_outputs = handle_shader_outputs_post;
6871 ctx.abi.emit_vertex = visit_emit_vertex;
6872 ctx.abi.load_ubo = radv_load_ubo;
6873 ctx.abi.load_ssbo = radv_load_ssbo;
6874 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6875 ctx.abi.load_resource = radv_load_resource;
6876 ctx.abi.clamp_shadow_reference = false;
6877
6878 if (shader_count >= 2)
6879 ac_init_exec_full_mask(&ctx.ac);
6880
6881 if (ctx.ac.chip_class == GFX9 &&
6882 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6883 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6884
6885 for(int i = 0; i < shader_count; ++i) {
6886 ctx.stage = shaders[i]->info.stage;
6887 ctx.output_mask = 0;
6888 ctx.tess_outputs_written = 0;
6889 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6890 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6891
6892 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6893 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6894 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6895 ctx.abi.load_inputs = load_gs_input;
6896 ctx.abi.emit_primitive = visit_end_primitive;
6897 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6898 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6899 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6900 ctx.abi.load_tess_varyings = load_tcs_varyings;
6901 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6902 ctx.abi.store_tcs_outputs = store_tcs_output;
6903 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6904 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6905 ctx.abi.load_tess_varyings = load_tes_input;
6906 ctx.abi.load_tess_coord = load_tess_coord;
6907 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6908 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6909 if (shader_info->info.vs.needs_instance_id) {
6910 if (ctx.options->key.vs.as_ls) {
6911 ctx.shader_info->vs.vgpr_comp_cnt =
6912 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6913 } else {
6914 ctx.shader_info->vs.vgpr_comp_cnt =
6915 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6916 }
6917 }
6918 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6919 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6920 ctx.abi.lookup_interp_param = lookup_interp_param;
6921 ctx.abi.load_sample_position = load_sample_position;
6922 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6923 }
6924
6925 if (i)
6926 emit_barrier(&ctx.ac, ctx.stage);
6927
6928 ac_setup_rings(&ctx);
6929
6930 LLVMBasicBlockRef merge_block;
6931 if (shader_count >= 2) {
6932 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6933 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6934 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6935
6936 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6937 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6938 LLVMConstInt(ctx.ac.i32, 8, false), false);
6939 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6940 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6941 thread_id, count, "");
6942 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6943
6944 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6945 }
6946
6947 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6948 handle_fs_inputs(&ctx, shaders[i]);
6949 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6950 handle_vs_inputs(&ctx, shaders[i]);
6951 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6952 prepare_gs_input_vgprs(&ctx);
6953
6954 nir_foreach_variable(variable, &shaders[i]->outputs)
6955 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6956
6957 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
6958
6959 if (shader_count >= 2) {
6960 LLVMBuildBr(ctx.ac.builder, merge_block);
6961 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6962 }
6963
6964 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6965 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6966 shaders[i]->info.cull_distance_array_size > 4;
6967 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6968 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6969 shaders[i]->info.gs.vertices_out;
6970 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6971 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6972 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6973 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6974 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6975 }
6976 }
6977
6978 LLVMBuildRetVoid(ctx.ac.builder);
6979
6980 if (options->dump_preoptir)
6981 ac_dump_module(ctx.ac.module);
6982
6983 ac_llvm_finalize_module(&ctx);
6984
6985 if (shader_count == 1)
6986 ac_nir_eliminate_const_vs_outputs(&ctx);
6987
6988 return ctx.ac.module;
6989 }
6990
6991 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6992 {
6993 unsigned *retval = (unsigned *)context;
6994 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6995 char *description = LLVMGetDiagInfoDescription(di);
6996
6997 if (severity == LLVMDSError) {
6998 *retval = 1;
6999 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
7000 description);
7001 }
7002
7003 LLVMDisposeMessage(description);
7004 }
7005
7006 static unsigned ac_llvm_compile(LLVMModuleRef M,
7007 struct ac_shader_binary *binary,
7008 LLVMTargetMachineRef tm)
7009 {
7010 unsigned retval = 0;
7011 char *err;
7012 LLVMContextRef llvm_ctx;
7013 LLVMMemoryBufferRef out_buffer;
7014 unsigned buffer_size;
7015 const char *buffer_data;
7016 LLVMBool mem_err;
7017
7018 /* Setup Diagnostic Handler*/
7019 llvm_ctx = LLVMGetModuleContext(M);
7020
7021 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
7022 &retval);
7023
7024 /* Compile IR*/
7025 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
7026 &err, &out_buffer);
7027
7028 /* Process Errors/Warnings */
7029 if (mem_err) {
7030 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7031 free(err);
7032 retval = 1;
7033 goto out;
7034 }
7035
7036 /* Extract Shader Code*/
7037 buffer_size = LLVMGetBufferSize(out_buffer);
7038 buffer_data = LLVMGetBufferStart(out_buffer);
7039
7040 ac_elf_read(buffer_data, buffer_size, binary);
7041
7042 /* Clean up */
7043 LLVMDisposeMemoryBuffer(out_buffer);
7044
7045 out:
7046 return retval;
7047 }
7048
7049 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7050 LLVMModuleRef llvm_module,
7051 struct ac_shader_binary *binary,
7052 struct ac_shader_config *config,
7053 struct ac_shader_variant_info *shader_info,
7054 gl_shader_stage stage,
7055 bool dump_shader, bool supports_spill)
7056 {
7057 if (dump_shader)
7058 ac_dump_module(llvm_module);
7059
7060 memset(binary, 0, sizeof(*binary));
7061 int v = ac_llvm_compile(llvm_module, binary, tm);
7062 if (v) {
7063 fprintf(stderr, "compile failed\n");
7064 }
7065
7066 if (dump_shader)
7067 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7068
7069 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7070
7071 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7072 LLVMDisposeModule(llvm_module);
7073 LLVMContextDispose(ctx);
7074
7075 if (stage == MESA_SHADER_FRAGMENT) {
7076 shader_info->num_input_vgprs = 0;
7077 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7078 shader_info->num_input_vgprs += 2;
7079 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7080 shader_info->num_input_vgprs += 2;
7081 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7082 shader_info->num_input_vgprs += 2;
7083 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7084 shader_info->num_input_vgprs += 3;
7085 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7086 shader_info->num_input_vgprs += 2;
7087 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7088 shader_info->num_input_vgprs += 2;
7089 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7090 shader_info->num_input_vgprs += 2;
7091 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7092 shader_info->num_input_vgprs += 1;
7093 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7094 shader_info->num_input_vgprs += 1;
7095 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7096 shader_info->num_input_vgprs += 1;
7097 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7098 shader_info->num_input_vgprs += 1;
7099 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7100 shader_info->num_input_vgprs += 1;
7101 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7102 shader_info->num_input_vgprs += 1;
7103 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7104 shader_info->num_input_vgprs += 1;
7105 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7106 shader_info->num_input_vgprs += 1;
7107 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7108 shader_info->num_input_vgprs += 1;
7109 }
7110 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7111
7112 /* +3 for scratch wave offset and VCC */
7113 config->num_sgprs = MAX2(config->num_sgprs,
7114 shader_info->num_input_sgprs + 3);
7115
7116 /* Enable 64-bit and 16-bit denormals, because there is no performance
7117 * cost.
7118 *
7119 * If denormals are enabled, all floating-point output modifiers are
7120 * ignored.
7121 *
7122 * Don't enable denormals for 32-bit floats, because:
7123 * - Floating-point output modifiers would be ignored by the hw.
7124 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7125 * have to stop using those.
7126 * - SI & CI would be very slow.
7127 */
7128 config->float_mode |= V_00B028_FP_64_DENORMS;
7129 }
7130
7131 static void
7132 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7133 {
7134 switch (nir->info.stage) {
7135 case MESA_SHADER_COMPUTE:
7136 for (int i = 0; i < 3; ++i)
7137 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7138 break;
7139 case MESA_SHADER_FRAGMENT:
7140 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7141 break;
7142 case MESA_SHADER_GEOMETRY:
7143 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7144 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7145 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7146 shader_info->gs.invocations = nir->info.gs.invocations;
7147 break;
7148 case MESA_SHADER_TESS_EVAL:
7149 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7150 shader_info->tes.spacing = nir->info.tess.spacing;
7151 shader_info->tes.ccw = nir->info.tess.ccw;
7152 shader_info->tes.point_mode = nir->info.tess.point_mode;
7153 shader_info->tes.as_es = options->key.tes.as_es;
7154 break;
7155 case MESA_SHADER_TESS_CTRL:
7156 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7157 break;
7158 case MESA_SHADER_VERTEX:
7159 shader_info->vs.as_es = options->key.vs.as_es;
7160 shader_info->vs.as_ls = options->key.vs.as_ls;
7161 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7162 if (options->key.vs.as_ls)
7163 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7164 break;
7165 default:
7166 break;
7167 }
7168 }
7169
7170 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7171 struct ac_shader_binary *binary,
7172 struct ac_shader_config *config,
7173 struct ac_shader_variant_info *shader_info,
7174 struct nir_shader *const *nir,
7175 int nir_count,
7176 const struct ac_nir_compiler_options *options,
7177 bool dump_shader)
7178 {
7179
7180 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7181 options);
7182
7183 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7184 for (int i = 0; i < nir_count; ++i)
7185 ac_fill_shader_info(shader_info, nir[i], options);
7186
7187 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7188 if (options->chip_class == GFX9) {
7189 if (nir_count == 2 &&
7190 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7191 shader_info->gs.es_type = nir[0]->info.stage;
7192 }
7193 }
7194 }
7195
7196 static void
7197 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
7198 {
7199 LLVMValueRef vtx_offset =
7200 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7201 LLVMConstInt(ctx->ac.i32, 4, false), "");
7202 int idx = 0;
7203
7204 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7205 int length = 4;
7206 int slot = idx;
7207 int slot_inc = 1;
7208 if (!(ctx->output_mask & (1ull << i)))
7209 continue;
7210
7211 if (i == VARYING_SLOT_CLIP_DIST0) {
7212 /* unpack clip and cull from a single set of slots */
7213 length = ctx->num_output_clips + ctx->num_output_culls;
7214 if (length > 4)
7215 slot_inc = 2;
7216 }
7217
7218 for (unsigned j = 0; j < length; j++) {
7219 LLVMValueRef value, soffset;
7220
7221 soffset = LLVMConstInt(ctx->ac.i32,
7222 (slot * 4 + j) *
7223 ctx->gs_max_out_vertices * 16 * 4, false);
7224
7225 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7226 1, ctx->ac.i32_0,
7227 vtx_offset, soffset,
7228 0, 1, 1, true, false);
7229
7230 LLVMBuildStore(ctx->ac.builder,
7231 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7232 }
7233 idx += slot_inc;
7234 }
7235 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7236 }
7237
7238 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7239 struct nir_shader *geom_shader,
7240 struct ac_shader_binary *binary,
7241 struct ac_shader_config *config,
7242 struct ac_shader_variant_info *shader_info,
7243 const struct ac_nir_compiler_options *options,
7244 bool dump_shader)
7245 {
7246 struct radv_shader_context ctx = {0};
7247 ctx.context = LLVMContextCreate();
7248 ctx.options = options;
7249 ctx.shader_info = shader_info;
7250
7251 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7252 options->family);
7253 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7254
7255 ctx.is_gs_copy_shader = true;
7256 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7257
7258 enum ac_float_mode float_mode =
7259 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7260 AC_FLOAT_MODE_DEFAULT;
7261
7262 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7263 ctx.stage = MESA_SHADER_VERTEX;
7264
7265 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7266
7267 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7268 ac_setup_rings(&ctx);
7269
7270 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7271 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7272
7273 struct ac_nir_context nir_ctx = {};
7274 nir_ctx.ac = ctx.ac;
7275 nir_ctx.abi = &ctx.abi;
7276
7277 nir_foreach_variable(variable, &geom_shader->outputs) {
7278 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7279 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7280 }
7281
7282 ac_gs_copy_shader_emit(&ctx);
7283
7284 LLVMBuildRetVoid(ctx.ac.builder);
7285
7286 ac_llvm_finalize_module(&ctx);
7287
7288 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7289 MESA_SHADER_VERTEX,
7290 dump_shader, options->supports_spill);
7291 }