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radv: optimise compute shader grid size emission.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83 LLVMValueRef ls_out_layout;
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef tcs_offchip_layout;
87 LLVMValueRef tcs_out_offsets;
88 LLVMValueRef tcs_out_layout;
89 LLVMValueRef tcs_in_layout;
90 LLVMValueRef oc_lds;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tcs_patch_id;
93 LLVMValueRef tcs_rel_ids;
94 LLVMValueRef tes_rel_patch_id;
95 LLVMValueRef tes_patch_id;
96 LLVMValueRef tes_u;
97 LLVMValueRef tes_v;
98
99 LLVMValueRef gsvs_ring_stride;
100 LLVMValueRef gsvs_num_entries;
101 LLVMValueRef gs2vs_offset;
102 LLVMValueRef gs_wave_id;
103 LLVMValueRef gs_vtx_offset[6];
104 LLVMValueRef gs_prim_id, gs_invocation_id;
105
106 LLVMValueRef esgs_ring;
107 LLVMValueRef gsvs_ring;
108 LLVMValueRef hs_ring_tess_offchip;
109 LLVMValueRef hs_ring_tess_factor;
110
111 LLVMValueRef prim_mask;
112 LLVMValueRef sample_pos_offset;
113 LLVMValueRef persp_sample, persp_center, persp_centroid;
114 LLVMValueRef linear_sample, linear_center, linear_centroid;
115 LLVMValueRef front_face;
116 LLVMValueRef ancillary;
117 LLVMValueRef sample_coverage;
118 LLVMValueRef frag_pos[4];
119
120 LLVMBasicBlockRef continue_block;
121 LLVMBasicBlockRef break_block;
122
123 LLVMTypeRef i1;
124 LLVMTypeRef i8;
125 LLVMTypeRef i16;
126 LLVMTypeRef i32;
127 LLVMTypeRef i64;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v3i32;
130 LLVMTypeRef v4i32;
131 LLVMTypeRef v8i32;
132 LLVMTypeRef f64;
133 LLVMTypeRef f32;
134 LLVMTypeRef f16;
135 LLVMTypeRef v2f32;
136 LLVMTypeRef v4f32;
137 LLVMTypeRef v16i8;
138 LLVMTypeRef voidt;
139
140 LLVMValueRef i1true;
141 LLVMValueRef i1false;
142 LLVMValueRef i32zero;
143 LLVMValueRef i32one;
144 LLVMValueRef f32zero;
145 LLVMValueRef f32one;
146 LLVMValueRef v4f32empty;
147
148 unsigned uniform_md_kind;
149 LLVMValueRef empty_md;
150 gl_shader_stage stage;
151
152 LLVMValueRef lds;
153 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
154 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
155
156 LLVMValueRef shared_memory;
157 uint64_t input_mask;
158 uint64_t output_mask;
159 int num_locals;
160 LLVMValueRef *locals;
161 bool has_ddxy;
162 uint8_t num_output_clips;
163 uint8_t num_output_culls;
164
165 bool has_ds_bpermute;
166
167 bool is_gs_copy_shader;
168 LLVMValueRef gs_next_vertex;
169 unsigned gs_max_out_vertices;
170
171 unsigned tes_primitive_mode;
172 uint64_t tess_outputs_written;
173 uint64_t tess_patch_outputs_written;
174 };
175
176 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
177 nir_deref_var *deref,
178 enum desc_type desc_type);
179 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
180 {
181 return (index * 4) + chan;
182 }
183
184 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
185 {
186 /* handle patch indices separate */
187 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
188 return 0;
189 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
190 return 1;
191 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
192 return 2 + (slot - VARYING_SLOT_PATCH0);
193
194 if (slot == VARYING_SLOT_POS)
195 return 0;
196 if (slot == VARYING_SLOT_PSIZ)
197 return 1;
198 if (slot == VARYING_SLOT_CLIP_DIST0)
199 return 2;
200 /* 3 is reserved for clip dist as well */
201 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
202 return 4 + (slot - VARYING_SLOT_VAR0);
203 unreachable("illegal slot in get unique index\n");
204 }
205
206 static unsigned llvm_get_type_size(LLVMTypeRef type)
207 {
208 LLVMTypeKind kind = LLVMGetTypeKind(type);
209
210 switch (kind) {
211 case LLVMIntegerTypeKind:
212 return LLVMGetIntTypeWidth(type) / 8;
213 case LLVMFloatTypeKind:
214 return 4;
215 case LLVMPointerTypeKind:
216 return 8;
217 case LLVMVectorTypeKind:
218 return LLVMGetVectorSize(type) *
219 llvm_get_type_size(LLVMGetElementType(type));
220 default:
221 assert(0);
222 return 0;
223 }
224 }
225
226 static void set_llvm_calling_convention(LLVMValueRef func,
227 gl_shader_stage stage)
228 {
229 enum radeon_llvm_calling_convention calling_conv;
230
231 switch (stage) {
232 case MESA_SHADER_VERTEX:
233 case MESA_SHADER_TESS_CTRL:
234 case MESA_SHADER_TESS_EVAL:
235 calling_conv = RADEON_LLVM_AMDGPU_VS;
236 break;
237 case MESA_SHADER_GEOMETRY:
238 calling_conv = RADEON_LLVM_AMDGPU_GS;
239 break;
240 case MESA_SHADER_FRAGMENT:
241 calling_conv = RADEON_LLVM_AMDGPU_PS;
242 break;
243 case MESA_SHADER_COMPUTE:
244 calling_conv = RADEON_LLVM_AMDGPU_CS;
245 break;
246 default:
247 unreachable("Unhandle shader type");
248 }
249
250 LLVMSetFunctionCallConv(func, calling_conv);
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems, LLVMTypeRef *param_types,
257 unsigned param_count, unsigned array_params_mask,
258 unsigned sgpr_params, bool unsafe_math)
259 {
260 LLVMTypeRef main_function_type, ret_type;
261 LLVMBasicBlockRef main_function_body;
262
263 if (num_return_elems)
264 ret_type = LLVMStructTypeInContext(ctx, return_types,
265 num_return_elems, true);
266 else
267 ret_type = LLVMVoidTypeInContext(ctx);
268
269 /* Setup the function */
270 main_function_type =
271 LLVMFunctionType(ret_type, param_types, param_count, 0);
272 LLVMValueRef main_function =
273 LLVMAddFunction(module, "main", main_function_type);
274 main_function_body =
275 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
276 LLVMPositionBuilderAtEnd(builder, main_function_body);
277
278 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
279 for (unsigned i = 0; i < sgpr_params; ++i) {
280 if (array_params_mask & (1 << i)) {
281 LLVMValueRef P = LLVMGetParam(main_function, i);
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
283 ac_add_attr_dereferenceable(P, UINT64_MAX);
284 }
285 else {
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
287 }
288 }
289
290 if (unsafe_math) {
291 /* These were copied from some LLVM test. */
292 LLVMAddTargetDependentFunctionAttr(main_function,
293 "less-precise-fpmad",
294 "true");
295 LLVMAddTargetDependentFunctionAttr(main_function,
296 "no-infs-fp-math",
297 "true");
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "no-nans-fp-math",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "unsafe-fp-math",
303 "true");
304 }
305 return main_function;
306 }
307
308 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
309 {
310 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
311 CONST_ADDR_SPACE);
312 }
313
314 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
315 int idx,
316 LLVMTypeRef type)
317 {
318 LLVMValueRef offset;
319 LLVMValueRef ptr;
320 int addr_space;
321
322 offset = LLVMConstInt(ctx->i32, idx * 16, false);
323
324 ptr = ctx->shared_memory;
325 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
326 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
327 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
328 return ptr;
329 }
330
331 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
332 {
333 if (t == ctx->f16 || t == ctx->i16)
334 return ctx->i16;
335 else if (t == ctx->f32 || t == ctx->i32)
336 return ctx->i32;
337 else if (t == ctx->f64 || t == ctx->i64)
338 return ctx->i64;
339 else
340 unreachable("Unhandled integer size");
341 }
342
343 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
344 {
345 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
346 LLVMTypeRef elem_type = LLVMGetElementType(t);
347 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
348 LLVMGetVectorSize(t));
349 }
350 return to_integer_type_scalar(ctx, t);
351 }
352
353 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
354 {
355 LLVMTypeRef type = LLVMTypeOf(v);
356 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
357 }
358
359 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
360 {
361 if (t == ctx->i16 || t == ctx->f16)
362 return ctx->f16;
363 else if (t == ctx->i32 || t == ctx->f32)
364 return ctx->f32;
365 else if (t == ctx->i64 || t == ctx->f64)
366 return ctx->f64;
367 else
368 unreachable("Unhandled float size");
369 }
370
371 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
372 {
373 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
374 LLVMTypeRef elem_type = LLVMGetElementType(t);
375 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
376 LLVMGetVectorSize(t));
377 }
378 return to_float_type_scalar(ctx, t);
379 }
380
381 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
382 {
383 LLVMTypeRef type = LLVMTypeOf(v);
384 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
385 }
386
387 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
388 {
389 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
390 type = LLVMGetElementType(type);
391
392 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
393 return LLVMGetIntTypeWidth(type);
394
395 if (type == ctx->f16)
396 return 16;
397 if (type == ctx->f32)
398 return 32;
399 if (type == ctx->f64)
400 return 64;
401
402 unreachable("Unhandled type kind in get_elem_bits");
403 }
404
405 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
406 LLVMValueRef param, unsigned rshift,
407 unsigned bitwidth)
408 {
409 LLVMValueRef value = param;
410 if (rshift)
411 value = LLVMBuildLShr(ctx->builder, value,
412 LLVMConstInt(ctx->i32, rshift, false), "");
413
414 if (rshift + bitwidth < 32) {
415 unsigned mask = (1 << bitwidth) - 1;
416 value = LLVMBuildAnd(ctx->builder, value,
417 LLVMConstInt(ctx->i32, mask, false), "");
418 }
419 return value;
420 }
421
422 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
423 {
424 switch (ctx->stage) {
425 case MESA_SHADER_TESS_CTRL:
426 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
427 case MESA_SHADER_TESS_EVAL:
428 return ctx->tes_rel_patch_id;
429 break;
430 default:
431 unreachable("Illegal stage");
432 }
433 }
434
435 /* Tessellation shaders pass outputs to the next shader using LDS.
436 *
437 * LS outputs = TCS inputs
438 * TCS outputs = TES inputs
439 *
440 * The LDS layout is:
441 * - TCS inputs for patch 0
442 * - TCS inputs for patch 1
443 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - ...
445 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
446 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
447 * - TCS outputs for patch 1
448 * - Per-patch TCS outputs for patch 1
449 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
450 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
451 * - ...
452 *
453 * All three shaders VS(LS), TCS, TES share the same LDS space.
454 */
455 static LLVMValueRef
456 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
457 {
458 if (ctx->stage == MESA_SHADER_VERTEX)
459 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
460 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
461 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
462 else {
463 assert(0);
464 return NULL;
465 }
466 }
467
468 static LLVMValueRef
469 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
470 {
471 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
472 }
473
474 static LLVMValueRef
475 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
476 {
477 return LLVMBuildMul(ctx->builder,
478 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
479 LLVMConstInt(ctx->i32, 4, false), "");
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
494 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
495
496 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
497 }
498
499 static LLVMValueRef
500 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
501 {
502 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
503 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
504 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
505
506 return LLVMBuildAdd(ctx->builder, patch0_offset,
507 LLVMBuildMul(ctx->builder, patch_stride,
508 rel_patch_id, ""),
509 "");
510 }
511
512 static LLVMValueRef
513 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
514 {
515 LLVMValueRef patch0_patch_data_offset =
516 get_tcs_out_patch0_patch_data_offset(ctx);
517 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
518 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
519
520 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
521 LLVMBuildMul(ctx->builder, patch_stride,
522 rel_patch_id, ""),
523 "");
524 }
525
526 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
527 {
528 ud_info->sgpr_idx = sgpr_idx;
529 ud_info->num_sgprs = num_sgprs;
530 ud_info->indirect = false;
531 ud_info->indirect_offset = 0;
532 }
533
534 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
535 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
536 {
537 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
538 }
539
540 #if 0
541 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
542 uint32_t indirect_offset)
543 {
544 ud_info->sgpr_idx = sgpr_idx;
545 ud_info->num_sgprs = num_sgprs;
546 ud_info->indirect = true;
547 ud_info->indirect_offset = indirect_offset;
548 }
549 #endif
550
551 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
552 {
553 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
554 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
555 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
556 "tess_lds");
557 }
558
559 static void create_function(struct nir_to_llvm_context *ctx)
560 {
561 LLVMTypeRef arg_types[23];
562 unsigned arg_idx = 0;
563 unsigned array_params_mask = 0;
564 unsigned sgpr_count = 0, user_sgpr_count;
565 unsigned i;
566 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
567 unsigned user_sgpr_idx;
568 bool need_push_constants;
569 bool need_ring_offsets = false;
570
571 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
572 if (ctx->stage == MESA_SHADER_GEOMETRY ||
573 ctx->stage == MESA_SHADER_VERTEX ||
574 ctx->stage == MESA_SHADER_TESS_CTRL ||
575 ctx->stage == MESA_SHADER_TESS_EVAL ||
576 ctx->stage == MESA_SHADER_FRAGMENT ||
577 ctx->is_gs_copy_shader)
578 need_ring_offsets = true;
579
580 need_push_constants = true;
581 if (!ctx->options->layout)
582 need_push_constants = false;
583 else if (!ctx->options->layout->push_constant_size &&
584 !ctx->options->layout->dynamic_offset_count)
585 need_push_constants = false;
586
587 if (need_ring_offsets && !ctx->options->supports_spill) {
588 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address of rings */
589 }
590
591 /* 1 for each descriptor set */
592 for (unsigned i = 0; i < num_sets; ++i) {
593 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
594 array_params_mask |= (1 << arg_idx);
595 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
596 }
597 }
598
599 if (need_push_constants) {
600 /* 1 for push constants and dynamic descriptors */
601 array_params_mask |= (1 << arg_idx);
602 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
603 }
604
605 switch (ctx->stage) {
606 case MESA_SHADER_COMPUTE:
607 if (ctx->shader_info->info.cs.grid_components_used)
608 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used); /* grid size */
609 user_sgpr_count = arg_idx;
610 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
611 arg_types[arg_idx++] = ctx->i32;
612 sgpr_count = arg_idx;
613
614 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
615 break;
616 case MESA_SHADER_VERTEX:
617 if (!ctx->is_gs_copy_shader) {
618 if (ctx->shader_info->info.vs.has_vertex_buffers)
619 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
620 arg_types[arg_idx++] = ctx->i32; // base vertex
621 arg_types[arg_idx++] = ctx->i32; // start instance
622 if (ctx->shader_info->info.vs.needs_draw_id)
623 arg_types[arg_idx++] = ctx->i32; // draw index
624 }
625 user_sgpr_count = arg_idx;
626 if (ctx->options->key.vs.as_es)
627 arg_types[arg_idx++] = ctx->i32; //es2gs offset
628 else if (ctx->options->key.vs.as_ls) {
629 arg_types[arg_idx++] = ctx->i32; //ls out layout
630 user_sgpr_count++;
631 }
632 sgpr_count = arg_idx;
633 arg_types[arg_idx++] = ctx->i32; // vertex id
634 if (!ctx->is_gs_copy_shader) {
635 arg_types[arg_idx++] = ctx->i32; // rel auto id
636 arg_types[arg_idx++] = ctx->i32; // vs prim id
637 arg_types[arg_idx++] = ctx->i32; // instance id
638 }
639 break;
640 case MESA_SHADER_TESS_CTRL:
641 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
642 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
643 arg_types[arg_idx++] = ctx->i32; // tcs out layout
644 arg_types[arg_idx++] = ctx->i32; // tcs in layout
645 user_sgpr_count = arg_idx;
646 arg_types[arg_idx++] = ctx->i32; // param oc lds
647 arg_types[arg_idx++] = ctx->i32; // tess factor offset
648 sgpr_count = arg_idx;
649 arg_types[arg_idx++] = ctx->i32; // patch id
650 arg_types[arg_idx++] = ctx->i32; // rel ids;
651 break;
652 case MESA_SHADER_TESS_EVAL:
653 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
654 user_sgpr_count = arg_idx;
655 if (ctx->options->key.tes.as_es) {
656 arg_types[arg_idx++] = ctx->i32; // OC LDS
657 arg_types[arg_idx++] = ctx->i32; //
658 arg_types[arg_idx++] = ctx->i32; // es2gs offset
659 } else {
660 arg_types[arg_idx++] = ctx->i32; //
661 arg_types[arg_idx++] = ctx->i32; // OC LDS
662 }
663 sgpr_count = arg_idx;
664 arg_types[arg_idx++] = ctx->f32; // tes_u
665 arg_types[arg_idx++] = ctx->f32; // tes_v
666 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
667 arg_types[arg_idx++] = ctx->i32; // tes patch id
668 break;
669 case MESA_SHADER_GEOMETRY:
670 arg_types[arg_idx++] = ctx->i32; // gsvs stride
671 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
672 user_sgpr_count = arg_idx;
673 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
674 arg_types[arg_idx++] = ctx->i32; // wave id
675 sgpr_count = arg_idx;
676 arg_types[arg_idx++] = ctx->i32; // vtx0
677 arg_types[arg_idx++] = ctx->i32; // vtx1
678 arg_types[arg_idx++] = ctx->i32; // prim id
679 arg_types[arg_idx++] = ctx->i32; // vtx2
680 arg_types[arg_idx++] = ctx->i32; // vtx3
681 arg_types[arg_idx++] = ctx->i32; // vtx4
682 arg_types[arg_idx++] = ctx->i32; // vtx5
683 arg_types[arg_idx++] = ctx->i32; // GS instance id
684 break;
685 case MESA_SHADER_FRAGMENT:
686 if (ctx->shader_info->info.ps.needs_sample_positions)
687 arg_types[arg_idx++] = ctx->i32; /* sample position offset */
688 user_sgpr_count = arg_idx;
689 arg_types[arg_idx++] = ctx->i32; /* prim mask */
690 sgpr_count = arg_idx;
691 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
692 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
693 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
694 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
695 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
696 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
697 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
698 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
699 arg_types[arg_idx++] = ctx->f32; /* pos x float */
700 arg_types[arg_idx++] = ctx->f32; /* pos y float */
701 arg_types[arg_idx++] = ctx->f32; /* pos z float */
702 arg_types[arg_idx++] = ctx->f32; /* pos w float */
703 arg_types[arg_idx++] = ctx->i32; /* front face */
704 arg_types[arg_idx++] = ctx->i32; /* ancillary */
705 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
706 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
707 break;
708 default:
709 unreachable("Shader stage not implemented");
710 }
711
712 ctx->main_function = create_llvm_function(
713 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
714 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
715 set_llvm_calling_convention(ctx->main_function, ctx->stage);
716
717 ctx->shader_info->num_input_sgprs = 0;
718 ctx->shader_info->num_input_vgprs = 0;
719
720 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
721 for (i = 0; i < user_sgpr_count; i++)
722 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
723
724 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
725 for (; i < sgpr_count; i++)
726 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
727
728 if (ctx->stage != MESA_SHADER_FRAGMENT)
729 for (; i < arg_idx; ++i)
730 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
731
732 arg_idx = 0;
733 user_sgpr_idx = 0;
734
735 if (ctx->options->supports_spill || need_ring_offsets) {
736 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
737 user_sgpr_idx += 2;
738 if (ctx->options->supports_spill) {
739 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
740 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
741 NULL, 0, AC_FUNC_ATTR_READNONE);
742 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
743 const_array(ctx->v16i8, 16), "");
744 } else
745 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
746 }
747
748 for (unsigned i = 0; i < num_sets; ++i) {
749 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
750 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
751 user_sgpr_idx += 2;
752 ctx->descriptor_sets[i] =
753 LLVMGetParam(ctx->main_function, arg_idx++);
754 } else
755 ctx->descriptor_sets[i] = NULL;
756 }
757
758 if (need_push_constants) {
759 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
760 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
761 user_sgpr_idx += 2;
762 }
763
764 switch (ctx->stage) {
765 case MESA_SHADER_COMPUTE:
766 if (ctx->shader_info->info.cs.grid_components_used) {
767 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
768 user_sgpr_idx += ctx->shader_info->info.cs.grid_components_used;
769 ctx->num_work_groups =
770 LLVMGetParam(ctx->main_function, arg_idx++);
771 }
772 ctx->workgroup_ids =
773 LLVMGetParam(ctx->main_function, arg_idx++);
774 ctx->tg_size =
775 LLVMGetParam(ctx->main_function, arg_idx++);
776 ctx->local_invocation_ids =
777 LLVMGetParam(ctx->main_function, arg_idx++);
778 break;
779 case MESA_SHADER_VERTEX:
780 if (!ctx->is_gs_copy_shader) {
781 if (ctx->shader_info->info.vs.has_vertex_buffers) {
782 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
783 user_sgpr_idx += 2;
784 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
785 }
786 unsigned vs_num = 2;
787 if (ctx->shader_info->info.vs.needs_draw_id)
788 vs_num++;
789
790 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
791 user_sgpr_idx += vs_num;
792
793 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
794 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
795 if (ctx->shader_info->info.vs.needs_draw_id)
796 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
797 }
798 if (ctx->options->key.vs.as_es)
799 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
800 else if (ctx->options->key.vs.as_ls) {
801 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
802 user_sgpr_idx += 1;
803 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
804 }
805 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
806 if (!ctx->is_gs_copy_shader) {
807 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
808 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
809 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
810 }
811 if (ctx->options->key.vs.as_ls)
812 declare_tess_lds(ctx);
813 break;
814 case MESA_SHADER_TESS_CTRL:
815 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
816 user_sgpr_idx += 4;
817 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
818 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
819 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
820 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
821 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
822 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
823 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
824 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
825
826 declare_tess_lds(ctx);
827 break;
828 case MESA_SHADER_TESS_EVAL:
829 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
830 user_sgpr_idx += 1;
831 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
832 if (ctx->options->key.tes.as_es) {
833 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
834 arg_idx++;
835 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
836 } else {
837 arg_idx++;
838 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
839 }
840 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
841 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
842 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
843 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
844 break;
845 case MESA_SHADER_GEOMETRY:
846 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
847 user_sgpr_idx += 2;
848 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
849 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
850 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
851 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
852 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
853 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
854 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
855 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
856 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
857 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
858 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
859 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
860 break;
861 case MESA_SHADER_FRAGMENT:
862 if (ctx->shader_info->info.ps.needs_sample_positions) {
863 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, user_sgpr_idx, 1);
864 user_sgpr_idx += 1;
865 ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, arg_idx++);
866 }
867 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
868 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
869 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
870 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
871 arg_idx++;
872 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
873 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
874 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
875 arg_idx++; /* line stipple */
876 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
877 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
878 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
879 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
880 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
881 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
882 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
883 break;
884 default:
885 unreachable("Shader stage not implemented");
886 }
887 }
888
889 static void setup_types(struct nir_to_llvm_context *ctx)
890 {
891 LLVMValueRef args[4];
892
893 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
894 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
895 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
896 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
897 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
898 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
899 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
900 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
901 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
902 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
903 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
904 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
905 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
906 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
907 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
908 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
909
910 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
911 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
912 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
913 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
914 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
915 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
916
917 args[0] = ctx->f32zero;
918 args[1] = ctx->f32zero;
919 args[2] = ctx->f32zero;
920 args[3] = ctx->f32one;
921 ctx->v4f32empty = LLVMConstVector(args, 4);
922
923 ctx->uniform_md_kind =
924 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
925 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
926
927 args[0] = LLVMConstReal(ctx->f32, 2.5);
928 }
929
930 static int get_llvm_num_components(LLVMValueRef value)
931 {
932 LLVMTypeRef type = LLVMTypeOf(value);
933 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
934 ? LLVMGetVectorSize(type)
935 : 1;
936 return num_components;
937 }
938
939 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
940 LLVMValueRef value,
941 int index)
942 {
943 int count = get_llvm_num_components(value);
944
945 assert(index < count);
946 if (count == 1)
947 return value;
948
949 return LLVMBuildExtractElement(ctx->builder, value,
950 LLVMConstInt(ctx->i32, index, false), "");
951 }
952
953 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
954 LLVMValueRef value, unsigned count)
955 {
956 unsigned num_components = get_llvm_num_components(value);
957 if (count == num_components)
958 return value;
959
960 LLVMValueRef masks[] = {
961 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
962 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
963
964 if (count == 1)
965 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
966 "");
967
968 LLVMValueRef swizzle = LLVMConstVector(masks, count);
969 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
970 }
971
972 static void
973 build_store_values_extended(struct nir_to_llvm_context *ctx,
974 LLVMValueRef *values,
975 unsigned value_count,
976 unsigned value_stride,
977 LLVMValueRef vec)
978 {
979 LLVMBuilderRef builder = ctx->builder;
980 unsigned i;
981
982 if (value_count == 1) {
983 LLVMBuildStore(builder, vec, values[0]);
984 return;
985 }
986
987 for (i = 0; i < value_count; i++) {
988 LLVMValueRef ptr = values[i * value_stride];
989 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
990 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
991 LLVMBuildStore(builder, value, ptr);
992 }
993 }
994
995 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
996 nir_ssa_def *def)
997 {
998 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
999 if (def->num_components > 1) {
1000 type = LLVMVectorType(type, def->num_components);
1001 }
1002 return type;
1003 }
1004
1005 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1006 {
1007 assert(src.is_ssa);
1008 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1009 return (LLVMValueRef)entry->data;
1010 }
1011
1012
1013 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1014 struct nir_block *b)
1015 {
1016 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1017 return (LLVMBasicBlockRef)entry->data;
1018 }
1019
1020 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1021 nir_alu_src src,
1022 unsigned num_components)
1023 {
1024 LLVMValueRef value = get_src(ctx, src.src);
1025 bool need_swizzle = false;
1026
1027 assert(value);
1028 LLVMTypeRef type = LLVMTypeOf(value);
1029 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1030 ? LLVMGetVectorSize(type)
1031 : 1;
1032
1033 for (unsigned i = 0; i < num_components; ++i) {
1034 assert(src.swizzle[i] < src_components);
1035 if (src.swizzle[i] != i)
1036 need_swizzle = true;
1037 }
1038
1039 if (need_swizzle || num_components != src_components) {
1040 LLVMValueRef masks[] = {
1041 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1042 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1043 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1044 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1045
1046 if (src_components > 1 && num_components == 1) {
1047 value = LLVMBuildExtractElement(ctx->builder, value,
1048 masks[0], "");
1049 } else if (src_components == 1 && num_components > 1) {
1050 LLVMValueRef values[] = {value, value, value, value};
1051 value = ac_build_gather_values(&ctx->ac, values, num_components);
1052 } else {
1053 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1054 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1055 swizzle, "");
1056 }
1057 }
1058 assert(!src.negate);
1059 assert(!src.abs);
1060 return value;
1061 }
1062
1063 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1064 LLVMIntPredicate pred, LLVMValueRef src0,
1065 LLVMValueRef src1)
1066 {
1067 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1068 return LLVMBuildSelect(ctx->builder, result,
1069 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1070 LLVMConstInt(ctx->i32, 0, false), "");
1071 }
1072
1073 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1074 LLVMRealPredicate pred, LLVMValueRef src0,
1075 LLVMValueRef src1)
1076 {
1077 LLVMValueRef result;
1078 src0 = to_float(ctx, src0);
1079 src1 = to_float(ctx, src1);
1080 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1081 return LLVMBuildSelect(ctx->builder, result,
1082 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1083 LLVMConstInt(ctx->i32, 0, false), "");
1084 }
1085
1086 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1087 const char *intrin,
1088 LLVMTypeRef result_type,
1089 LLVMValueRef src0)
1090 {
1091 char name[64];
1092 LLVMValueRef params[] = {
1093 to_float(ctx, src0),
1094 };
1095
1096 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1097 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1098 }
1099
1100 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1101 const char *intrin,
1102 LLVMTypeRef result_type,
1103 LLVMValueRef src0, LLVMValueRef src1)
1104 {
1105 char name[64];
1106 LLVMValueRef params[] = {
1107 to_float(ctx, src0),
1108 to_float(ctx, src1),
1109 };
1110
1111 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1112 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1113 }
1114
1115 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1116 const char *intrin,
1117 LLVMTypeRef result_type,
1118 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1119 {
1120 char name[64];
1121 LLVMValueRef params[] = {
1122 to_float(ctx, src0),
1123 to_float(ctx, src1),
1124 to_float(ctx, src2),
1125 };
1126
1127 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1128 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1129 }
1130
1131 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1132 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1133 {
1134 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1135 ctx->i32zero, "");
1136 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1137 }
1138
1139 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1140 LLVMValueRef src0)
1141 {
1142 LLVMValueRef params[2] = {
1143 src0,
1144
1145 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1146 * add special code to check for x=0. The reason is that
1147 * the LLVM behavior for x=0 is different from what we
1148 * need here.
1149 *
1150 * The hardware already implements the correct behavior.
1151 */
1152 LLVMConstInt(ctx->i32, 1, false),
1153 };
1154 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1155 }
1156
1157 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1158 LLVMValueRef src0)
1159 {
1160 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1161 }
1162
1163 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1164 LLVMValueRef src0)
1165 {
1166 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1167 }
1168
1169 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1170 LLVMIntPredicate pred,
1171 LLVMValueRef src0, LLVMValueRef src1)
1172 {
1173 return LLVMBuildSelect(ctx->builder,
1174 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1175 src0,
1176 src1, "");
1177
1178 }
1179 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1180 LLVMValueRef src0)
1181 {
1182 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1183 LLVMBuildNeg(ctx->builder, src0, ""));
1184 }
1185
1186 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1187 LLVMValueRef src0)
1188 {
1189 LLVMValueRef cmp, val;
1190
1191 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1192 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1193 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1194 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1195 return val;
1196 }
1197
1198 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1199 LLVMValueRef src0)
1200 {
1201 LLVMValueRef cmp, val;
1202
1203 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1204 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1205 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1206 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1207 return val;
1208 }
1209
1210 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1211 LLVMValueRef src0)
1212 {
1213 const char *intr = "llvm.floor.f32";
1214 LLVMValueRef fsrc0 = to_float(ctx, src0);
1215 LLVMValueRef params[] = {
1216 fsrc0,
1217 };
1218 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1219 ctx->f32, params, 1,
1220 AC_FUNC_ATTR_READNONE);
1221 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1222 }
1223
1224 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1225 const char *intrin,
1226 LLVMValueRef src0, LLVMValueRef src1)
1227 {
1228 LLVMTypeRef ret_type;
1229 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1230 LLVMValueRef res;
1231 LLVMValueRef params[] = { src0, src1 };
1232 ret_type = LLVMStructTypeInContext(ctx->context, types,
1233 2, true);
1234
1235 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1236 params, 2, AC_FUNC_ATTR_READNONE);
1237
1238 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1239 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1240 return res;
1241 }
1242
1243 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1244 LLVMValueRef src0)
1245 {
1246 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1247 }
1248
1249 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1250 LLVMValueRef src0, LLVMValueRef src1)
1251 {
1252 LLVMValueRef dst64, result;
1253 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1254 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1255
1256 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1257 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1258 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1259 return result;
1260 }
1261
1262 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1263 LLVMValueRef src0, LLVMValueRef src1)
1264 {
1265 LLVMValueRef dst64, result;
1266 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1267 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1268
1269 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1270 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1271 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1272 return result;
1273 }
1274
1275 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1276 bool is_signed,
1277 LLVMValueRef srcs[3])
1278 {
1279 LLVMValueRef result;
1280 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1281
1282 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1283 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1284 return result;
1285 }
1286
1287 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1288 LLVMValueRef src0, LLVMValueRef src1,
1289 LLVMValueRef src2, LLVMValueRef src3)
1290 {
1291 LLVMValueRef bfi_args[3], result;
1292
1293 bfi_args[0] = LLVMBuildShl(ctx->builder,
1294 LLVMBuildSub(ctx->builder,
1295 LLVMBuildShl(ctx->builder,
1296 ctx->i32one,
1297 src3, ""),
1298 ctx->i32one, ""),
1299 src2, "");
1300 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1301 bfi_args[2] = src0;
1302
1303 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1304
1305 /* Calculate:
1306 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1307 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1308 */
1309 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1310 LLVMBuildAnd(ctx->builder, bfi_args[0],
1311 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1312
1313 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1314 return result;
1315 }
1316
1317 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1318 LLVMValueRef src0)
1319 {
1320 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1321 int i;
1322 LLVMValueRef comp[2];
1323
1324 src0 = to_float(ctx, src0);
1325 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1326 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1327 for (i = 0; i < 2; i++) {
1328 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1329 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1330 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1331 }
1332
1333 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1334 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1335
1336 return comp[0];
1337 }
1338
1339 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1340 LLVMValueRef src0)
1341 {
1342 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1343 LLVMValueRef temps[2], result, val;
1344 int i;
1345
1346 for (i = 0; i < 2; i++) {
1347 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1348 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1349 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1350 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1351 }
1352
1353 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1354 ctx->i32zero, "");
1355 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1356 ctx->i32one, "");
1357 return result;
1358 }
1359
1360 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1361 nir_op op,
1362 LLVMValueRef src0)
1363 {
1364 unsigned mask;
1365 int idx;
1366 LLVMValueRef result;
1367 ctx->has_ddxy = true;
1368
1369 if (!ctx->lds && !ctx->has_ds_bpermute)
1370 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1371 LLVMArrayType(ctx->i32, 64),
1372 "ddxy_lds", LOCAL_ADDR_SPACE);
1373
1374 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1375 mask = AC_TID_MASK_LEFT;
1376 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1377 mask = AC_TID_MASK_TOP;
1378 else
1379 mask = AC_TID_MASK_TOP_LEFT;
1380
1381 /* for DDX we want to next X pixel, DDY next Y pixel. */
1382 if (op == nir_op_fddx_fine ||
1383 op == nir_op_fddx_coarse ||
1384 op == nir_op_fddx)
1385 idx = 1;
1386 else
1387 idx = 2;
1388
1389 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1390 mask, idx, ctx->lds,
1391 src0);
1392 return result;
1393 }
1394
1395 /*
1396 * this takes an I,J coordinate pair,
1397 * and works out the X and Y derivatives.
1398 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1399 */
1400 static LLVMValueRef emit_ddxy_interp(
1401 struct nir_to_llvm_context *ctx,
1402 LLVMValueRef interp_ij)
1403 {
1404 LLVMValueRef result[4], a;
1405 unsigned i;
1406
1407 for (i = 0; i < 2; i++) {
1408 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1409 LLVMConstInt(ctx->i32, i, false), "");
1410 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1411 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1412 }
1413 return ac_build_gather_values(&ctx->ac, result, 4);
1414 }
1415
1416 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1417 {
1418 LLVMValueRef src[4], result = NULL;
1419 unsigned num_components = instr->dest.dest.ssa.num_components;
1420 unsigned src_components;
1421 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1422
1423 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1424 switch (instr->op) {
1425 case nir_op_vec2:
1426 case nir_op_vec3:
1427 case nir_op_vec4:
1428 src_components = 1;
1429 break;
1430 case nir_op_pack_half_2x16:
1431 src_components = 2;
1432 break;
1433 case nir_op_unpack_half_2x16:
1434 src_components = 1;
1435 break;
1436 default:
1437 src_components = num_components;
1438 break;
1439 }
1440 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1441 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1442
1443 switch (instr->op) {
1444 case nir_op_fmov:
1445 case nir_op_imov:
1446 result = src[0];
1447 break;
1448 case nir_op_fneg:
1449 src[0] = to_float(ctx, src[0]);
1450 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1451 break;
1452 case nir_op_ineg:
1453 result = LLVMBuildNeg(ctx->builder, src[0], "");
1454 break;
1455 case nir_op_inot:
1456 result = LLVMBuildNot(ctx->builder, src[0], "");
1457 break;
1458 case nir_op_iadd:
1459 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1460 break;
1461 case nir_op_fadd:
1462 src[0] = to_float(ctx, src[0]);
1463 src[1] = to_float(ctx, src[1]);
1464 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1465 break;
1466 case nir_op_fsub:
1467 src[0] = to_float(ctx, src[0]);
1468 src[1] = to_float(ctx, src[1]);
1469 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1470 break;
1471 case nir_op_isub:
1472 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1473 break;
1474 case nir_op_imul:
1475 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1476 break;
1477 case nir_op_imod:
1478 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1479 break;
1480 case nir_op_umod:
1481 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1482 break;
1483 case nir_op_fmod:
1484 src[0] = to_float(ctx, src[0]);
1485 src[1] = to_float(ctx, src[1]);
1486 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1487 result = emit_intrin_1f_param(ctx, "llvm.floor",
1488 to_float_type(ctx, def_type), result);
1489 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1490 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1491 break;
1492 case nir_op_frem:
1493 src[0] = to_float(ctx, src[0]);
1494 src[1] = to_float(ctx, src[1]);
1495 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1496 break;
1497 case nir_op_irem:
1498 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1499 break;
1500 case nir_op_idiv:
1501 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1502 break;
1503 case nir_op_udiv:
1504 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1505 break;
1506 case nir_op_fmul:
1507 src[0] = to_float(ctx, src[0]);
1508 src[1] = to_float(ctx, src[1]);
1509 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1510 break;
1511 case nir_op_fdiv:
1512 src[0] = to_float(ctx, src[0]);
1513 src[1] = to_float(ctx, src[1]);
1514 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1515 break;
1516 case nir_op_frcp:
1517 src[0] = to_float(ctx, src[0]);
1518 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1519 break;
1520 case nir_op_iand:
1521 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1522 break;
1523 case nir_op_ior:
1524 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1525 break;
1526 case nir_op_ixor:
1527 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1528 break;
1529 case nir_op_ishl:
1530 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1531 break;
1532 case nir_op_ishr:
1533 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1534 break;
1535 case nir_op_ushr:
1536 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1537 break;
1538 case nir_op_ilt:
1539 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1540 break;
1541 case nir_op_ine:
1542 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1543 break;
1544 case nir_op_ieq:
1545 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1546 break;
1547 case nir_op_ige:
1548 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1549 break;
1550 case nir_op_ult:
1551 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1552 break;
1553 case nir_op_uge:
1554 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1555 break;
1556 case nir_op_feq:
1557 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1558 break;
1559 case nir_op_fne:
1560 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1561 break;
1562 case nir_op_flt:
1563 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1564 break;
1565 case nir_op_fge:
1566 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1567 break;
1568 case nir_op_fabs:
1569 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1570 to_float_type(ctx, def_type), src[0]);
1571 break;
1572 case nir_op_iabs:
1573 result = emit_iabs(ctx, src[0]);
1574 break;
1575 case nir_op_imax:
1576 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1577 break;
1578 case nir_op_imin:
1579 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1580 break;
1581 case nir_op_umax:
1582 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1583 break;
1584 case nir_op_umin:
1585 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1586 break;
1587 case nir_op_isign:
1588 result = emit_isign(ctx, src[0]);
1589 break;
1590 case nir_op_fsign:
1591 src[0] = to_float(ctx, src[0]);
1592 result = emit_fsign(ctx, src[0]);
1593 break;
1594 case nir_op_ffloor:
1595 result = emit_intrin_1f_param(ctx, "llvm.floor",
1596 to_float_type(ctx, def_type), src[0]);
1597 break;
1598 case nir_op_ftrunc:
1599 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1600 to_float_type(ctx, def_type), src[0]);
1601 break;
1602 case nir_op_fceil:
1603 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1604 to_float_type(ctx, def_type), src[0]);
1605 break;
1606 case nir_op_fround_even:
1607 result = emit_intrin_1f_param(ctx, "llvm.rint",
1608 to_float_type(ctx, def_type),src[0]);
1609 break;
1610 case nir_op_ffract:
1611 result = emit_ffract(ctx, src[0]);
1612 break;
1613 case nir_op_fsin:
1614 result = emit_intrin_1f_param(ctx, "llvm.sin",
1615 to_float_type(ctx, def_type), src[0]);
1616 break;
1617 case nir_op_fcos:
1618 result = emit_intrin_1f_param(ctx, "llvm.cos",
1619 to_float_type(ctx, def_type), src[0]);
1620 break;
1621 case nir_op_fsqrt:
1622 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1623 to_float_type(ctx, def_type), src[0]);
1624 break;
1625 case nir_op_fexp2:
1626 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1627 to_float_type(ctx, def_type), src[0]);
1628 break;
1629 case nir_op_flog2:
1630 result = emit_intrin_1f_param(ctx, "llvm.log2",
1631 to_float_type(ctx, def_type), src[0]);
1632 break;
1633 case nir_op_frsq:
1634 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1635 to_float_type(ctx, def_type), src[0]);
1636 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1637 break;
1638 case nir_op_fpow:
1639 result = emit_intrin_2f_param(ctx, "llvm.pow",
1640 to_float_type(ctx, def_type), src[0], src[1]);
1641 break;
1642 case nir_op_fmax:
1643 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1644 to_float_type(ctx, def_type), src[0], src[1]);
1645 break;
1646 case nir_op_fmin:
1647 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1648 to_float_type(ctx, def_type), src[0], src[1]);
1649 break;
1650 case nir_op_ffma:
1651 result = emit_intrin_3f_param(ctx, "llvm.fma",
1652 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1653 break;
1654 case nir_op_ibitfield_extract:
1655 result = emit_bitfield_extract(ctx, true, src);
1656 break;
1657 case nir_op_ubitfield_extract:
1658 result = emit_bitfield_extract(ctx, false, src);
1659 break;
1660 case nir_op_bitfield_insert:
1661 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1662 break;
1663 case nir_op_bitfield_reverse:
1664 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1665 break;
1666 case nir_op_bit_count:
1667 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1668 break;
1669 case nir_op_vec2:
1670 case nir_op_vec3:
1671 case nir_op_vec4:
1672 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1673 src[i] = to_integer(ctx, src[i]);
1674 result = ac_build_gather_values(&ctx->ac, src, num_components);
1675 break;
1676 case nir_op_f2i32:
1677 case nir_op_f2i64:
1678 src[0] = to_float(ctx, src[0]);
1679 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1680 break;
1681 case nir_op_f2u32:
1682 case nir_op_f2u64:
1683 src[0] = to_float(ctx, src[0]);
1684 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1685 break;
1686 case nir_op_i2f32:
1687 case nir_op_i2f64:
1688 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1689 break;
1690 case nir_op_u2f32:
1691 case nir_op_u2f64:
1692 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1693 break;
1694 case nir_op_f2f64:
1695 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1696 break;
1697 case nir_op_f2f32:
1698 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1699 break;
1700 case nir_op_u2u32:
1701 case nir_op_u2u64:
1702 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1703 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1704 else
1705 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1706 break;
1707 case nir_op_i2i32:
1708 case nir_op_i2i64:
1709 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1710 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1711 else
1712 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1713 break;
1714 case nir_op_bcsel:
1715 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1716 break;
1717 case nir_op_find_lsb:
1718 result = emit_find_lsb(ctx, src[0]);
1719 break;
1720 case nir_op_ufind_msb:
1721 result = emit_ufind_msb(ctx, src[0]);
1722 break;
1723 case nir_op_ifind_msb:
1724 result = emit_ifind_msb(ctx, src[0]);
1725 break;
1726 case nir_op_uadd_carry:
1727 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1728 break;
1729 case nir_op_usub_borrow:
1730 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1731 break;
1732 case nir_op_b2f:
1733 result = emit_b2f(ctx, src[0]);
1734 break;
1735 case nir_op_fquantize2f16:
1736 src[0] = to_float(ctx, src[0]);
1737 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1738 /* need to convert back up to f32 */
1739 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1740 break;
1741 case nir_op_umul_high:
1742 result = emit_umul_high(ctx, src[0], src[1]);
1743 break;
1744 case nir_op_imul_high:
1745 result = emit_imul_high(ctx, src[0], src[1]);
1746 break;
1747 case nir_op_pack_half_2x16:
1748 result = emit_pack_half_2x16(ctx, src[0]);
1749 break;
1750 case nir_op_unpack_half_2x16:
1751 result = emit_unpack_half_2x16(ctx, src[0]);
1752 break;
1753 case nir_op_fddx:
1754 case nir_op_fddy:
1755 case nir_op_fddx_fine:
1756 case nir_op_fddy_fine:
1757 case nir_op_fddx_coarse:
1758 case nir_op_fddy_coarse:
1759 result = emit_ddxy(ctx, instr->op, src[0]);
1760 break;
1761 default:
1762 fprintf(stderr, "Unknown NIR alu instr: ");
1763 nir_print_instr(&instr->instr, stderr);
1764 fprintf(stderr, "\n");
1765 abort();
1766 }
1767
1768 if (result) {
1769 assert(instr->dest.dest.is_ssa);
1770 result = to_integer(ctx, result);
1771 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1772 result);
1773 }
1774 }
1775
1776 static void visit_load_const(struct nir_to_llvm_context *ctx,
1777 nir_load_const_instr *instr)
1778 {
1779 LLVMValueRef values[4], value = NULL;
1780 LLVMTypeRef element_type =
1781 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1782
1783 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1784 switch (instr->def.bit_size) {
1785 case 32:
1786 values[i] = LLVMConstInt(element_type,
1787 instr->value.u32[i], false);
1788 break;
1789 case 64:
1790 values[i] = LLVMConstInt(element_type,
1791 instr->value.u64[i], false);
1792 break;
1793 default:
1794 fprintf(stderr,
1795 "unsupported nir load_const bit_size: %d\n",
1796 instr->def.bit_size);
1797 abort();
1798 }
1799 }
1800 if (instr->def.num_components > 1) {
1801 value = LLVMConstVector(values, instr->def.num_components);
1802 } else
1803 value = values[0];
1804
1805 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1806 }
1807
1808 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1809 LLVMTypeRef type)
1810 {
1811 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1812 return LLVMBuildBitCast(ctx->builder, ptr,
1813 LLVMPointerType(type, addr_space), "");
1814 }
1815
1816 static LLVMValueRef
1817 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1818 {
1819 LLVMValueRef size =
1820 LLVMBuildExtractElement(ctx->builder, descriptor,
1821 LLVMConstInt(ctx->i32, 2, false), "");
1822
1823 /* VI only */
1824 if (ctx->options->chip_class >= VI && in_elements) {
1825 /* On VI, the descriptor contains the size in bytes,
1826 * but TXQ must return the size in elements.
1827 * The stride is always non-zero for resources using TXQ.
1828 */
1829 LLVMValueRef stride =
1830 LLVMBuildExtractElement(ctx->builder, descriptor,
1831 LLVMConstInt(ctx->i32, 1, false), "");
1832 stride = LLVMBuildLShr(ctx->builder, stride,
1833 LLVMConstInt(ctx->i32, 16, false), "");
1834 stride = LLVMBuildAnd(ctx->builder, stride,
1835 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1836
1837 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1838 }
1839 return size;
1840 }
1841
1842 /**
1843 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1844 * intrinsic names).
1845 */
1846 static void build_int_type_name(
1847 LLVMTypeRef type,
1848 char *buf, unsigned bufsize)
1849 {
1850 assert(bufsize >= 6);
1851
1852 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1853 snprintf(buf, bufsize, "v%ui32",
1854 LLVMGetVectorSize(type));
1855 else
1856 strcpy(buf, "i32");
1857 }
1858
1859 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1860 struct ac_image_args *args,
1861 nir_tex_instr *instr)
1862 {
1863 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1864 LLVMValueRef coord = args->addr;
1865 LLVMValueRef half_texel[2];
1866 LLVMValueRef compare_cube_wa;
1867 LLVMValueRef result;
1868 int c;
1869 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1870
1871 //TODO Rect
1872 {
1873 struct ac_image_args txq_args = { 0 };
1874
1875 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1876 txq_args.opcode = ac_image_get_resinfo;
1877 txq_args.dmask = 0xf;
1878 txq_args.addr = ctx->i32zero;
1879 txq_args.resource = args->resource;
1880 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1881
1882 for (c = 0; c < 2; c++) {
1883 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1884 LLVMConstInt(ctx->i32, c, false), "");
1885 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1886 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1887 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1888 LLVMConstReal(ctx->f32, -0.5), "");
1889 }
1890 }
1891
1892 LLVMValueRef orig_coords = args->addr;
1893
1894 for (c = 0; c < 2; c++) {
1895 LLVMValueRef tmp;
1896 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1897 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1898 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1899 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1900 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1901 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1902 }
1903
1904
1905 /*
1906 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1907 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1908 * workaround by sampling using a scaled type and converting.
1909 * This is taken from amdgpu-pro shaders.
1910 */
1911 /* NOTE this produces some ugly code compared to amdgpu-pro,
1912 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1913 * and then reads them back. -pro generates two selects,
1914 * one s_cmp for the descriptor rewriting
1915 * one v_cmp for the coordinate and result changes.
1916 */
1917 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1918 LLVMValueRef tmp, tmp2;
1919
1920 /* workaround 8/8/8/8 uint/sint cube gather bug */
1921 /* first detect it then change to a scaled read and f2i */
1922 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
1923 tmp2 = tmp;
1924
1925 /* extract the DATA_FORMAT */
1926 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
1927 LLVMConstInt(ctx->i32, 6, false), false);
1928
1929 /* is the DATA_FORMAT == 8_8_8_8 */
1930 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
1931
1932 if (stype == GLSL_TYPE_UINT)
1933 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
1934 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
1935 LLVMConstInt(ctx->i32, 0x10000000, false), "");
1936 else
1937 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
1938 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
1939 LLVMConstInt(ctx->i32, 0x14000000, false), "");
1940
1941 /* replace the NUM FORMAT in the descriptor */
1942 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
1943 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
1944
1945 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
1946
1947 /* don't modify the coordinates for this case */
1948 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
1949 }
1950 args->addr = coord;
1951 result = ac_build_image_opcode(&ctx->ac, args);
1952
1953 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1954 LLVMValueRef tmp, tmp2;
1955
1956 /* if the cube workaround is in place, f2i the result. */
1957 for (c = 0; c < 4; c++) {
1958 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
1959 if (stype == GLSL_TYPE_UINT)
1960 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
1961 else
1962 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
1963 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1964 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
1965 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
1966 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1967 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
1968 }
1969 }
1970 return result;
1971 }
1972
1973 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1974 nir_tex_instr *instr,
1975 struct ac_image_args *args)
1976 {
1977 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
1978 return ac_build_buffer_load_format(&ctx->ac,
1979 args->resource,
1980 args->addr,
1981 LLVMConstInt(ctx->i32, 0, false),
1982 true);
1983 }
1984
1985 args->opcode = ac_image_sample;
1986 args->compare = instr->is_shadow;
1987
1988 switch (instr->op) {
1989 case nir_texop_txf:
1990 case nir_texop_txf_ms:
1991 case nir_texop_samples_identical:
1992 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
1993 args->compare = false;
1994 args->offset = false;
1995 break;
1996 case nir_texop_txb:
1997 args->bias = true;
1998 break;
1999 case nir_texop_txl:
2000 args->lod = true;
2001 break;
2002 case nir_texop_txs:
2003 case nir_texop_query_levels:
2004 args->opcode = ac_image_get_resinfo;
2005 break;
2006 case nir_texop_tex:
2007 if (ctx->stage != MESA_SHADER_FRAGMENT)
2008 args->level_zero = true;
2009 break;
2010 case nir_texop_txd:
2011 args->deriv = true;
2012 break;
2013 case nir_texop_tg4:
2014 args->opcode = ac_image_gather4;
2015 args->level_zero = true;
2016 break;
2017 case nir_texop_lod:
2018 args->opcode = ac_image_get_lod;
2019 args->compare = false;
2020 args->offset = false;
2021 break;
2022 default:
2023 break;
2024 }
2025
2026 if (instr->op == nir_texop_tg4) {
2027 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2028 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2029 return radv_lower_gather4_integer(ctx, args, instr);
2030 }
2031 }
2032 return ac_build_image_opcode(&ctx->ac, args);
2033 }
2034
2035 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2036 nir_intrinsic_instr *instr)
2037 {
2038 LLVMValueRef index = get_src(ctx, instr->src[0]);
2039 unsigned desc_set = nir_intrinsic_desc_set(instr);
2040 unsigned binding = nir_intrinsic_binding(instr);
2041 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2042 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2043 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2044 unsigned base_offset = layout->binding[binding].offset;
2045 LLVMValueRef offset, stride;
2046
2047 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2048 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2049 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2050 layout->binding[binding].dynamic_offset_offset;
2051 desc_ptr = ctx->push_constants;
2052 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2053 stride = LLVMConstInt(ctx->i32, 16, false);
2054 } else
2055 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2056
2057 offset = LLVMConstInt(ctx->i32, base_offset, false);
2058 index = LLVMBuildMul(ctx->builder, index, stride, "");
2059 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2060
2061 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2062 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2063 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2064
2065 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2066 }
2067
2068 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2069 nir_intrinsic_instr *instr)
2070 {
2071 LLVMValueRef ptr, addr;
2072
2073 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2074 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2075
2076 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2077 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2078
2079 return LLVMBuildLoad(ctx->builder, ptr, "");
2080 }
2081
2082 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2083 nir_intrinsic_instr *instr)
2084 {
2085 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2086
2087 return get_buffer_size(ctx, desc, false);
2088 }
2089 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2090 nir_intrinsic_instr *instr)
2091 {
2092 const char *store_name;
2093 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2094 LLVMTypeRef data_type = ctx->f32;
2095 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2096 int components_32bit = elem_size_mult * instr->num_components;
2097 unsigned writemask = nir_intrinsic_write_mask(instr);
2098 LLVMValueRef base_data, base_offset;
2099 LLVMValueRef params[6];
2100
2101 if (ctx->stage == MESA_SHADER_FRAGMENT)
2102 ctx->shader_info->fs.writes_memory = true;
2103
2104 params[1] = get_src(ctx, instr->src[1]);
2105 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2106 params[4] = ctx->i1false; /* glc */
2107 params[5] = ctx->i1false; /* slc */
2108
2109 if (components_32bit > 1)
2110 data_type = LLVMVectorType(ctx->f32, components_32bit);
2111
2112 base_data = to_float(ctx, src_data);
2113 base_data = trim_vector(ctx, base_data, instr->num_components);
2114 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2115 data_type, "");
2116 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2117 while (writemask) {
2118 int start, count;
2119 LLVMValueRef data;
2120 LLVMValueRef offset;
2121 LLVMValueRef tmp;
2122 u_bit_scan_consecutive_range(&writemask, &start, &count);
2123
2124 /* Due to an LLVM limitation, split 3-element writes
2125 * into a 2-element and a 1-element write. */
2126 if (count == 3) {
2127 writemask |= 1 << (start + 2);
2128 count = 2;
2129 }
2130
2131 start *= elem_size_mult;
2132 count *= elem_size_mult;
2133
2134 if (count > 4) {
2135 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2136 count = 4;
2137 }
2138
2139 if (count == 4) {
2140 store_name = "llvm.amdgcn.buffer.store.v4f32";
2141 data = base_data;
2142 } else if (count == 2) {
2143 tmp = LLVMBuildExtractElement(ctx->builder,
2144 base_data, LLVMConstInt(ctx->i32, start, false), "");
2145 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2146 ctx->i32zero, "");
2147
2148 tmp = LLVMBuildExtractElement(ctx->builder,
2149 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2150 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2151 ctx->i32one, "");
2152 store_name = "llvm.amdgcn.buffer.store.v2f32";
2153
2154 } else {
2155 assert(count == 1);
2156 if (get_llvm_num_components(base_data) > 1)
2157 data = LLVMBuildExtractElement(ctx->builder, base_data,
2158 LLVMConstInt(ctx->i32, start, false), "");
2159 else
2160 data = base_data;
2161 store_name = "llvm.amdgcn.buffer.store.f32";
2162 }
2163
2164 offset = base_offset;
2165 if (start != 0) {
2166 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2167 }
2168 params[0] = data;
2169 params[3] = offset;
2170 ac_build_intrinsic(&ctx->ac, store_name,
2171 ctx->voidt, params, 6, 0);
2172 }
2173 }
2174
2175 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2176 nir_intrinsic_instr *instr)
2177 {
2178 const char *name;
2179 LLVMValueRef params[6];
2180 int arg_count = 0;
2181 if (ctx->stage == MESA_SHADER_FRAGMENT)
2182 ctx->shader_info->fs.writes_memory = true;
2183
2184 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2185 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2186 }
2187 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2188 params[arg_count++] = get_src(ctx, instr->src[0]);
2189 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2190 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2191 params[arg_count++] = ctx->i1false; /* slc */
2192
2193 switch (instr->intrinsic) {
2194 case nir_intrinsic_ssbo_atomic_add:
2195 name = "llvm.amdgcn.buffer.atomic.add";
2196 break;
2197 case nir_intrinsic_ssbo_atomic_imin:
2198 name = "llvm.amdgcn.buffer.atomic.smin";
2199 break;
2200 case nir_intrinsic_ssbo_atomic_umin:
2201 name = "llvm.amdgcn.buffer.atomic.umin";
2202 break;
2203 case nir_intrinsic_ssbo_atomic_imax:
2204 name = "llvm.amdgcn.buffer.atomic.smax";
2205 break;
2206 case nir_intrinsic_ssbo_atomic_umax:
2207 name = "llvm.amdgcn.buffer.atomic.umax";
2208 break;
2209 case nir_intrinsic_ssbo_atomic_and:
2210 name = "llvm.amdgcn.buffer.atomic.and";
2211 break;
2212 case nir_intrinsic_ssbo_atomic_or:
2213 name = "llvm.amdgcn.buffer.atomic.or";
2214 break;
2215 case nir_intrinsic_ssbo_atomic_xor:
2216 name = "llvm.amdgcn.buffer.atomic.xor";
2217 break;
2218 case nir_intrinsic_ssbo_atomic_exchange:
2219 name = "llvm.amdgcn.buffer.atomic.swap";
2220 break;
2221 case nir_intrinsic_ssbo_atomic_comp_swap:
2222 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2223 break;
2224 default:
2225 abort();
2226 }
2227
2228 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2229 }
2230
2231 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2232 nir_intrinsic_instr *instr)
2233 {
2234 LLVMValueRef results[2];
2235 int load_components;
2236 int num_components = instr->num_components;
2237 if (instr->dest.ssa.bit_size == 64)
2238 num_components *= 2;
2239
2240 for (int i = 0; i < num_components; i += load_components) {
2241 load_components = MIN2(num_components - i, 4);
2242 const char *load_name;
2243 LLVMTypeRef data_type = ctx->f32;
2244 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2245 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2246
2247 if (load_components == 3)
2248 data_type = LLVMVectorType(ctx->f32, 4);
2249 else if (load_components > 1)
2250 data_type = LLVMVectorType(ctx->f32, load_components);
2251
2252 if (load_components >= 3)
2253 load_name = "llvm.amdgcn.buffer.load.v4f32";
2254 else if (load_components == 2)
2255 load_name = "llvm.amdgcn.buffer.load.v2f32";
2256 else if (load_components == 1)
2257 load_name = "llvm.amdgcn.buffer.load.f32";
2258 else
2259 unreachable("unhandled number of components");
2260
2261 LLVMValueRef params[] = {
2262 get_src(ctx, instr->src[0]),
2263 LLVMConstInt(ctx->i32, 0, false),
2264 offset,
2265 ctx->i1false,
2266 ctx->i1false,
2267 };
2268
2269 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2270
2271 }
2272
2273 LLVMValueRef ret = results[0];
2274 if (num_components > 4 || num_components == 3) {
2275 LLVMValueRef masks[] = {
2276 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2277 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2278 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2279 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2280 };
2281
2282 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2283 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2284 results[num_components > 4 ? 1 : 0], swizzle, "");
2285 }
2286
2287 return LLVMBuildBitCast(ctx->builder, ret,
2288 get_def_type(ctx, &instr->dest.ssa), "");
2289 }
2290
2291 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2292 nir_intrinsic_instr *instr)
2293 {
2294 LLVMValueRef results[8], ret;
2295 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2296 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2297 int num_components = instr->num_components;
2298
2299 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2300
2301 if (instr->dest.ssa.bit_size == 64)
2302 num_components *= 2;
2303
2304 for (unsigned i = 0; i < num_components; ++i) {
2305 LLVMValueRef params[] = {
2306 rsrc,
2307 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2308 offset, "")
2309 };
2310 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2311 params, 2,
2312 AC_FUNC_ATTR_READNONE |
2313 AC_FUNC_ATTR_LEGACY);
2314 }
2315
2316
2317 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2318 return LLVMBuildBitCast(ctx->builder, ret,
2319 get_def_type(ctx, &instr->dest.ssa), "");
2320 }
2321
2322 static void
2323 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2324 bool vs_in, unsigned *vertex_index_out,
2325 LLVMValueRef *vertex_index_ref,
2326 unsigned *const_out, LLVMValueRef *indir_out)
2327 {
2328 unsigned const_offset = 0;
2329 nir_deref *tail = &deref->deref;
2330 LLVMValueRef offset = NULL;
2331
2332 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2333 tail = tail->child;
2334 nir_deref_array *deref_array = nir_deref_as_array(tail);
2335 if (vertex_index_out)
2336 *vertex_index_out = deref_array->base_offset;
2337
2338 if (vertex_index_ref) {
2339 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2340 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2341 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2342 }
2343 *vertex_index_ref = vtx;
2344 }
2345 }
2346
2347 if (deref->var->data.compact) {
2348 assert(tail->child->deref_type == nir_deref_type_array);
2349 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2350 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2351 /* We always lower indirect dereferences for "compact" array vars. */
2352 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2353
2354 const_offset = deref_array->base_offset;
2355 goto out;
2356 }
2357
2358 while (tail->child != NULL) {
2359 const struct glsl_type *parent_type = tail->type;
2360 tail = tail->child;
2361
2362 if (tail->deref_type == nir_deref_type_array) {
2363 nir_deref_array *deref_array = nir_deref_as_array(tail);
2364 LLVMValueRef index, stride, local_offset;
2365 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2366
2367 const_offset += size * deref_array->base_offset;
2368 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2369 continue;
2370
2371 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2372 index = get_src(ctx, deref_array->indirect);
2373 stride = LLVMConstInt(ctx->i32, size, 0);
2374 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2375
2376 if (offset)
2377 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2378 else
2379 offset = local_offset;
2380 } else if (tail->deref_type == nir_deref_type_struct) {
2381 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2382
2383 for (unsigned i = 0; i < deref_struct->index; i++) {
2384 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2385 const_offset += glsl_count_attribute_slots(ft, vs_in);
2386 }
2387 } else
2388 unreachable("unsupported deref type");
2389
2390 }
2391 out:
2392 if (const_offset && offset)
2393 offset = LLVMBuildAdd(ctx->builder, offset,
2394 LLVMConstInt(ctx->i32, const_offset, 0),
2395 "");
2396
2397 *const_out = const_offset;
2398 *indir_out = offset;
2399 }
2400
2401 static LLVMValueRef
2402 lds_load(struct nir_to_llvm_context *ctx,
2403 LLVMValueRef dw_addr)
2404 {
2405 LLVMValueRef value;
2406 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2407 return value;
2408 }
2409
2410 static void
2411 lds_store(struct nir_to_llvm_context *ctx,
2412 LLVMValueRef dw_addr, LLVMValueRef value)
2413 {
2414 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2415 ac_build_indexed_store(&ctx->ac, ctx->lds,
2416 dw_addr, value);
2417 }
2418
2419 /* The offchip buffer layout for TCS->TES is
2420 *
2421 * - attribute 0 of patch 0 vertex 0
2422 * - attribute 0 of patch 0 vertex 1
2423 * - attribute 0 of patch 0 vertex 2
2424 * ...
2425 * - attribute 0 of patch 1 vertex 0
2426 * - attribute 0 of patch 1 vertex 1
2427 * ...
2428 * - attribute 1 of patch 0 vertex 0
2429 * - attribute 1 of patch 0 vertex 1
2430 * ...
2431 * - per patch attribute 0 of patch 0
2432 * - per patch attribute 0 of patch 1
2433 * ...
2434 *
2435 * Note that every attribute has 4 components.
2436 */
2437 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2438 LLVMValueRef vertex_index,
2439 LLVMValueRef param_index)
2440 {
2441 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2442 LLVMValueRef param_stride, constant16;
2443 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2444
2445 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2446 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2447 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2448 num_patches, "");
2449
2450 constant16 = LLVMConstInt(ctx->i32, 16, false);
2451 if (vertex_index) {
2452 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2453 vertices_per_patch, "");
2454
2455 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2456 vertex_index, "");
2457
2458 param_stride = total_vertices;
2459 } else {
2460 base_addr = rel_patch_id;
2461 param_stride = num_patches;
2462 }
2463
2464 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2465 LLVMBuildMul(ctx->builder, param_index,
2466 param_stride, ""), "");
2467
2468 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2469
2470 if (!vertex_index) {
2471 LLVMValueRef patch_data_offset =
2472 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2473
2474 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2475 patch_data_offset, "");
2476 }
2477 return base_addr;
2478 }
2479
2480 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2481 unsigned param,
2482 unsigned const_index,
2483 bool is_compact,
2484 LLVMValueRef vertex_index,
2485 LLVMValueRef indir_index)
2486 {
2487 LLVMValueRef param_index;
2488
2489 if (indir_index)
2490 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2491 indir_index, "");
2492 else {
2493 if (const_index && !is_compact)
2494 param += const_index;
2495 param_index = LLVMConstInt(ctx->i32, param, false);
2496 }
2497 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2498 }
2499
2500 static void
2501 mark_tess_output(struct nir_to_llvm_context *ctx,
2502 bool is_patch, uint32_t param)
2503
2504 {
2505 if (is_patch) {
2506 ctx->tess_patch_outputs_written |= (1ull << param);
2507 } else
2508 ctx->tess_outputs_written |= (1ull << param);
2509 }
2510
2511 static LLVMValueRef
2512 get_dw_address(struct nir_to_llvm_context *ctx,
2513 LLVMValueRef dw_addr,
2514 unsigned param,
2515 unsigned const_index,
2516 bool compact_const_index,
2517 LLVMValueRef vertex_index,
2518 LLVMValueRef stride,
2519 LLVMValueRef indir_index)
2520
2521 {
2522
2523 if (vertex_index) {
2524 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2525 LLVMBuildMul(ctx->builder,
2526 vertex_index,
2527 stride, ""), "");
2528 }
2529
2530 if (indir_index)
2531 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2532 LLVMBuildMul(ctx->builder, indir_index,
2533 LLVMConstInt(ctx->i32, 4, false), ""), "");
2534 else if (const_index && !compact_const_index)
2535 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2536 LLVMConstInt(ctx->i32, const_index, false), "");
2537
2538 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2539 LLVMConstInt(ctx->i32, param * 4, false), "");
2540
2541 if (const_index && compact_const_index)
2542 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2543 LLVMConstInt(ctx->i32, const_index, false), "");
2544 return dw_addr;
2545 }
2546
2547 static LLVMValueRef
2548 load_tcs_input(struct nir_to_llvm_context *ctx,
2549 nir_intrinsic_instr *instr)
2550 {
2551 LLVMValueRef dw_addr, stride;
2552 unsigned const_index;
2553 LLVMValueRef vertex_index;
2554 LLVMValueRef indir_index;
2555 unsigned param;
2556 LLVMValueRef value[4], result;
2557 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2558 const bool is_compact = instr->variables[0]->var->data.compact;
2559 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2560 radv_get_deref_offset(ctx, instr->variables[0],
2561 false, NULL, per_vertex ? &vertex_index : NULL,
2562 &const_index, &indir_index);
2563
2564 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2565 dw_addr = get_tcs_in_current_patch_offset(ctx);
2566 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2567 indir_index);
2568
2569 for (unsigned i = 0; i < instr->num_components; i++) {
2570 value[i] = lds_load(ctx, dw_addr);
2571 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2572 ctx->i32one, "");
2573 }
2574 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2575 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2576 return result;
2577 }
2578
2579 static LLVMValueRef
2580 load_tcs_output(struct nir_to_llvm_context *ctx,
2581 nir_intrinsic_instr *instr)
2582 {
2583 LLVMValueRef dw_addr, stride;
2584 LLVMValueRef value[4], result;
2585 LLVMValueRef vertex_index = NULL;
2586 LLVMValueRef indir_index = NULL;
2587 unsigned const_index = 0;
2588 unsigned param;
2589 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2590 const bool is_compact = instr->variables[0]->var->data.compact;
2591 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2592 radv_get_deref_offset(ctx, instr->variables[0],
2593 false, NULL, per_vertex ? &vertex_index : NULL,
2594 &const_index, &indir_index);
2595
2596 if (!instr->variables[0]->var->data.patch) {
2597 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2598 dw_addr = get_tcs_out_current_patch_offset(ctx);
2599 } else {
2600 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2601 }
2602
2603 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2604 indir_index);
2605
2606 for (unsigned i = 0; i < instr->num_components; i++) {
2607 value[i] = lds_load(ctx, dw_addr);
2608 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2609 ctx->i32one, "");
2610 }
2611 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2612 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2613 return result;
2614 }
2615
2616 static void
2617 store_tcs_output(struct nir_to_llvm_context *ctx,
2618 nir_intrinsic_instr *instr,
2619 LLVMValueRef src,
2620 unsigned writemask)
2621 {
2622 LLVMValueRef stride, dw_addr;
2623 LLVMValueRef buf_addr = NULL;
2624 LLVMValueRef vertex_index = NULL;
2625 LLVMValueRef indir_index = NULL;
2626 unsigned const_index = 0;
2627 unsigned param;
2628 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2629 const bool is_compact = instr->variables[0]->var->data.compact;
2630
2631 radv_get_deref_offset(ctx, instr->variables[0],
2632 false, NULL, per_vertex ? &vertex_index : NULL,
2633 &const_index, &indir_index);
2634
2635 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2636 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2637 is_compact && const_index > 3) {
2638 const_index -= 3;
2639 param++;
2640 }
2641
2642 if (!instr->variables[0]->var->data.patch) {
2643 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2644 dw_addr = get_tcs_out_current_patch_offset(ctx);
2645 } else {
2646 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2647 }
2648
2649 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2650
2651 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2652 indir_index);
2653 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2654 vertex_index, indir_index);
2655
2656 unsigned base = is_compact ? const_index : 0;
2657 for (unsigned chan = 0; chan < 8; chan++) {
2658 bool is_tess_factor = false;
2659 if (!(writemask & (1 << chan)))
2660 continue;
2661 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2662
2663 lds_store(ctx, dw_addr, value);
2664
2665 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2666 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2667 is_tess_factor = true;
2668
2669 if (!is_tess_factor && writemask != 0xF)
2670 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2671 buf_addr, ctx->oc_lds,
2672 4 * (base + chan), 1, 0, true, false);
2673
2674 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2675 ctx->i32one, "");
2676 }
2677
2678 if (writemask == 0xF) {
2679 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2680 buf_addr, ctx->oc_lds,
2681 (base * 4), 1, 0, true, false);
2682 }
2683 }
2684
2685 static LLVMValueRef
2686 load_tes_input(struct nir_to_llvm_context *ctx,
2687 nir_intrinsic_instr *instr)
2688 {
2689 LLVMValueRef buf_addr;
2690 LLVMValueRef result;
2691 LLVMValueRef vertex_index = NULL;
2692 LLVMValueRef indir_index = NULL;
2693 unsigned const_index = 0;
2694 unsigned param;
2695 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2696 const bool is_compact = instr->variables[0]->var->data.compact;
2697
2698 radv_get_deref_offset(ctx, instr->variables[0],
2699 false, NULL, per_vertex ? &vertex_index : NULL,
2700 &const_index, &indir_index);
2701 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2702 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2703 is_compact && const_index > 3) {
2704 const_index -= 3;
2705 param++;
2706 }
2707 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2708 is_compact, vertex_index, indir_index);
2709
2710 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2711 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true);
2712 result = trim_vector(ctx, result, instr->num_components);
2713 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2714 return result;
2715 }
2716
2717 static LLVMValueRef
2718 load_gs_input(struct nir_to_llvm_context *ctx,
2719 nir_intrinsic_instr *instr)
2720 {
2721 LLVMValueRef indir_index, vtx_offset;
2722 unsigned const_index;
2723 LLVMValueRef args[9];
2724 unsigned param, vtx_offset_param;
2725 LLVMValueRef value[4], result;
2726 unsigned vertex_index;
2727 radv_get_deref_offset(ctx, instr->variables[0],
2728 false, &vertex_index, NULL,
2729 &const_index, &indir_index);
2730 vtx_offset_param = vertex_index;
2731 assert(vtx_offset_param < 6);
2732 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2733 LLVMConstInt(ctx->i32, 4, false), "");
2734
2735 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2736 for (unsigned i = 0; i < instr->num_components; i++) {
2737
2738 args[0] = ctx->esgs_ring;
2739 args[1] = vtx_offset;
2740 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2741 args[3] = ctx->i32zero;
2742 args[4] = ctx->i32one; /* OFFEN */
2743 args[5] = ctx->i32zero; /* IDXEN */
2744 args[6] = ctx->i32one; /* GLC */
2745 args[7] = ctx->i32zero; /* SLC */
2746 args[8] = ctx->i32zero; /* TFE */
2747
2748 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2749 ctx->i32, args, 9,
2750 AC_FUNC_ATTR_READONLY |
2751 AC_FUNC_ATTR_LEGACY);
2752 }
2753 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2754
2755 return result;
2756 }
2757
2758 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2759 nir_intrinsic_instr *instr)
2760 {
2761 LLVMValueRef values[8];
2762 int idx = instr->variables[0]->var->data.driver_location;
2763 int ve = instr->dest.ssa.num_components;
2764 LLVMValueRef indir_index;
2765 LLVMValueRef ret;
2766 unsigned const_index;
2767 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2768 instr->variables[0]->var->data.mode == nir_var_shader_in;
2769 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2770 &const_index, &indir_index);
2771
2772 if (instr->dest.ssa.bit_size == 64)
2773 ve *= 2;
2774
2775 switch (instr->variables[0]->var->data.mode) {
2776 case nir_var_shader_in:
2777 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2778 return load_tcs_input(ctx, instr);
2779 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2780 return load_tes_input(ctx, instr);
2781 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2782 return load_gs_input(ctx, instr);
2783 }
2784 for (unsigned chan = 0; chan < ve; chan++) {
2785 if (indir_index) {
2786 unsigned count = glsl_count_attribute_slots(
2787 instr->variables[0]->var->type,
2788 ctx->stage == MESA_SHADER_VERTEX);
2789 count -= chan / 4;
2790 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2791 &ctx->ac, ctx->inputs + idx + chan, count,
2792 4, false);
2793
2794 values[chan] = LLVMBuildExtractElement(ctx->builder,
2795 tmp_vec,
2796 indir_index, "");
2797 } else
2798 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2799 }
2800 break;
2801 case nir_var_local:
2802 for (unsigned chan = 0; chan < ve; chan++) {
2803 if (indir_index) {
2804 unsigned count = glsl_count_attribute_slots(
2805 instr->variables[0]->var->type, false);
2806 count -= chan / 4;
2807 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2808 &ctx->ac, ctx->locals + idx + chan, count,
2809 4, true);
2810
2811 values[chan] = LLVMBuildExtractElement(ctx->builder,
2812 tmp_vec,
2813 indir_index, "");
2814 } else {
2815 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2816 }
2817 }
2818 break;
2819 case nir_var_shader_out:
2820 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2821 return load_tcs_output(ctx, instr);
2822 for (unsigned chan = 0; chan < ve; chan++) {
2823 if (indir_index) {
2824 unsigned count = glsl_count_attribute_slots(
2825 instr->variables[0]->var->type, false);
2826 count -= chan / 4;
2827 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2828 &ctx->ac, ctx->outputs + idx + chan, count,
2829 4, true);
2830
2831 values[chan] = LLVMBuildExtractElement(ctx->builder,
2832 tmp_vec,
2833 indir_index, "");
2834 } else {
2835 values[chan] = LLVMBuildLoad(ctx->builder,
2836 ctx->outputs[idx + chan + const_index * 4],
2837 "");
2838 }
2839 }
2840 break;
2841 case nir_var_shared: {
2842 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2843 LLVMValueRef derived_ptr;
2844
2845 if (indir_index)
2846 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2847
2848 for (unsigned chan = 0; chan < ve; chan++) {
2849 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2850 if (indir_index)
2851 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2852 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2853
2854 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2855 }
2856 break;
2857 }
2858 default:
2859 unreachable("unhandle variable mode");
2860 }
2861 ret = ac_build_gather_values(&ctx->ac, values, ve);
2862 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2863 }
2864
2865 static void
2866 visit_store_var(struct nir_to_llvm_context *ctx,
2867 nir_intrinsic_instr *instr)
2868 {
2869 LLVMValueRef temp_ptr, value;
2870 int idx = instr->variables[0]->var->data.driver_location;
2871 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2872 int writemask = instr->const_index[0];
2873 LLVMValueRef indir_index;
2874 unsigned const_index;
2875 radv_get_deref_offset(ctx, instr->variables[0], false,
2876 NULL, NULL, &const_index, &indir_index);
2877
2878 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2879 int old_writemask = writemask;
2880
2881 src = LLVMBuildBitCast(ctx->builder, src,
2882 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2883 "");
2884
2885 writemask = 0;
2886 for (unsigned chan = 0; chan < 4; chan++) {
2887 if (old_writemask & (1 << chan))
2888 writemask |= 3u << (2 * chan);
2889 }
2890 }
2891
2892 switch (instr->variables[0]->var->data.mode) {
2893 case nir_var_shader_out:
2894
2895 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
2896 store_tcs_output(ctx, instr, src, writemask);
2897 return;
2898 }
2899
2900 for (unsigned chan = 0; chan < 8; chan++) {
2901 int stride = 4;
2902 if (!(writemask & (1 << chan)))
2903 continue;
2904
2905 value = llvm_extract_elem(ctx, src, chan);
2906
2907 if (instr->variables[0]->var->data.compact)
2908 stride = 1;
2909 if (indir_index) {
2910 unsigned count = glsl_count_attribute_slots(
2911 instr->variables[0]->var->type, false);
2912 count -= chan / 4;
2913 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2914 &ctx->ac, ctx->outputs + idx + chan, count,
2915 stride, true);
2916
2917 if (get_llvm_num_components(tmp_vec) > 1) {
2918 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2919 value, indir_index, "");
2920 } else
2921 tmp_vec = value;
2922 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2923 count, stride, tmp_vec);
2924
2925 } else {
2926 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2927
2928 LLVMBuildStore(ctx->builder, value, temp_ptr);
2929 }
2930 }
2931 break;
2932 case nir_var_local:
2933 for (unsigned chan = 0; chan < 8; chan++) {
2934 if (!(writemask & (1 << chan)))
2935 continue;
2936
2937 value = llvm_extract_elem(ctx, src, chan);
2938 if (indir_index) {
2939 unsigned count = glsl_count_attribute_slots(
2940 instr->variables[0]->var->type, false);
2941 count -= chan / 4;
2942 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2943 &ctx->ac, ctx->locals + idx + chan, count,
2944 4, true);
2945
2946 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2947 value, indir_index, "");
2948 build_store_values_extended(ctx, ctx->locals + idx + chan,
2949 count, 4, tmp_vec);
2950 } else {
2951 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2952
2953 LLVMBuildStore(ctx->builder, value, temp_ptr);
2954 }
2955 }
2956 break;
2957 case nir_var_shared: {
2958 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2959
2960 if (indir_index)
2961 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2962
2963 for (unsigned chan = 0; chan < 8; chan++) {
2964 if (!(writemask & (1 << chan)))
2965 continue;
2966 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2967 LLVMValueRef derived_ptr;
2968
2969 if (indir_index)
2970 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2971
2972 value = llvm_extract_elem(ctx, src, chan);
2973 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2974 LLVMBuildStore(ctx->builder,
2975 to_integer(ctx, value), derived_ptr);
2976 }
2977 break;
2978 }
2979 default:
2980 break;
2981 }
2982 }
2983
2984 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2985 {
2986 switch (dim) {
2987 case GLSL_SAMPLER_DIM_BUF:
2988 return 1;
2989 case GLSL_SAMPLER_DIM_1D:
2990 return array ? 2 : 1;
2991 case GLSL_SAMPLER_DIM_2D:
2992 return array ? 3 : 2;
2993 case GLSL_SAMPLER_DIM_MS:
2994 return array ? 4 : 3;
2995 case GLSL_SAMPLER_DIM_3D:
2996 case GLSL_SAMPLER_DIM_CUBE:
2997 return 3;
2998 case GLSL_SAMPLER_DIM_RECT:
2999 case GLSL_SAMPLER_DIM_SUBPASS:
3000 return 2;
3001 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3002 return 3;
3003 default:
3004 break;
3005 }
3006 return 0;
3007 }
3008
3009
3010
3011 /* Adjust the sample index according to FMASK.
3012 *
3013 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3014 * which is the identity mapping. Each nibble says which physical sample
3015 * should be fetched to get that sample.
3016 *
3017 * For example, 0x11111100 means there are only 2 samples stored and
3018 * the second sample covers 3/4 of the pixel. When reading samples 0
3019 * and 1, return physical sample 0 (determined by the first two 0s
3020 * in FMASK), otherwise return physical sample 1.
3021 *
3022 * The sample index should be adjusted as follows:
3023 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3024 */
3025 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3026 LLVMValueRef coord_x, LLVMValueRef coord_y,
3027 LLVMValueRef coord_z,
3028 LLVMValueRef sample_index,
3029 LLVMValueRef fmask_desc_ptr)
3030 {
3031 LLVMValueRef fmask_load_address[4];
3032 LLVMValueRef res;
3033
3034 fmask_load_address[0] = coord_x;
3035 fmask_load_address[1] = coord_y;
3036 if (coord_z) {
3037 fmask_load_address[2] = coord_z;
3038 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3039 }
3040
3041 struct ac_image_args args = {0};
3042
3043 args.opcode = ac_image_load;
3044 args.da = coord_z ? true : false;
3045 args.resource = fmask_desc_ptr;
3046 args.dmask = 0xf;
3047 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3048
3049 res = ac_build_image_opcode(&ctx->ac, &args);
3050
3051 res = to_integer(ctx, res);
3052 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3053 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3054
3055 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3056 res,
3057 ctx->i32zero, "");
3058
3059 LLVMValueRef sample_index4 =
3060 LLVMBuildMul(ctx->builder, sample_index, four, "");
3061 LLVMValueRef shifted_fmask =
3062 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3063 LLVMValueRef final_sample =
3064 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3065
3066 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3067 * resource descriptor is 0 (invalid),
3068 */
3069 LLVMValueRef fmask_desc =
3070 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3071 ctx->v8i32, "");
3072
3073 LLVMValueRef fmask_word1 =
3074 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3075 ctx->i32one, "");
3076
3077 LLVMValueRef word1_is_nonzero =
3078 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3079 fmask_word1, ctx->i32zero, "");
3080
3081 /* Replace the MSAA sample index. */
3082 sample_index =
3083 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3084 final_sample, sample_index, "");
3085 return sample_index;
3086 }
3087
3088 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3089 nir_intrinsic_instr *instr)
3090 {
3091 const struct glsl_type *type = instr->variables[0]->var->type;
3092 if(instr->variables[0]->deref.child)
3093 type = instr->variables[0]->deref.child->type;
3094
3095 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3096 LLVMValueRef coords[4];
3097 LLVMValueRef masks[] = {
3098 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3099 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3100 };
3101 LLVMValueRef res;
3102 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3103
3104 int count;
3105 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3106 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3107 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3108 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3109 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3110
3111 count = image_type_to_components_count(dim,
3112 glsl_sampler_type_is_array(type));
3113
3114 if (is_ms) {
3115 LLVMValueRef fmask_load_address[3];
3116 int chan;
3117
3118 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3119 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3120 if (glsl_sampler_type_is_array(type))
3121 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3122 else
3123 fmask_load_address[2] = NULL;
3124 if (add_frag_pos) {
3125 for (chan = 0; chan < 2; ++chan)
3126 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3127 }
3128 sample_index = adjust_sample_index_using_fmask(ctx,
3129 fmask_load_address[0],
3130 fmask_load_address[1],
3131 fmask_load_address[2],
3132 sample_index,
3133 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3134 }
3135 if (count == 1) {
3136 if (instr->src[0].ssa->num_components)
3137 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3138 else
3139 res = src0;
3140 } else {
3141 int chan;
3142 if (is_ms)
3143 count--;
3144 for (chan = 0; chan < count; ++chan) {
3145 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3146 }
3147
3148 if (add_frag_pos) {
3149 for (chan = 0; chan < count; ++chan)
3150 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3151 }
3152 if (is_ms) {
3153 coords[count] = sample_index;
3154 count++;
3155 }
3156
3157 if (count == 3) {
3158 coords[3] = LLVMGetUndef(ctx->i32);
3159 count = 4;
3160 }
3161 res = ac_build_gather_values(&ctx->ac, coords, count);
3162 }
3163 return res;
3164 }
3165
3166 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3167 nir_intrinsic_instr *instr)
3168 {
3169 LLVMValueRef params[7];
3170 LLVMValueRef res;
3171 char intrinsic_name[64];
3172 const nir_variable *var = instr->variables[0]->var;
3173 const struct glsl_type *type = var->type;
3174 if(instr->variables[0]->deref.child)
3175 type = instr->variables[0]->deref.child->type;
3176
3177 type = glsl_without_array(type);
3178 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3179 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3180 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3181 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3182 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3183 params[3] = ctx->i1false; /* glc */
3184 params[4] = ctx->i1false; /* slc */
3185 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3186 params, 5, 0);
3187
3188 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3189 res = to_integer(ctx, res);
3190 } else {
3191 bool is_da = glsl_sampler_type_is_array(type) ||
3192 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3193 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3194 LLVMValueRef glc = ctx->i1false;
3195 LLVMValueRef slc = ctx->i1false;
3196
3197 params[0] = get_image_coords(ctx, instr);
3198 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3199 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3200 if (HAVE_LLVM <= 0x0309) {
3201 params[3] = ctx->i1false; /* r128 */
3202 params[4] = da;
3203 params[5] = glc;
3204 params[6] = slc;
3205 } else {
3206 LLVMValueRef lwe = ctx->i1false;
3207 params[3] = glc;
3208 params[4] = slc;
3209 params[5] = lwe;
3210 params[6] = da;
3211 }
3212
3213 ac_get_image_intr_name("llvm.amdgcn.image.load",
3214 ctx->v4f32, /* vdata */
3215 LLVMTypeOf(params[0]), /* coords */
3216 LLVMTypeOf(params[1]), /* rsrc */
3217 intrinsic_name, sizeof(intrinsic_name));
3218
3219 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3220 params, 7, AC_FUNC_ATTR_READONLY);
3221 }
3222 return to_integer(ctx, res);
3223 }
3224
3225 static void visit_image_store(struct nir_to_llvm_context *ctx,
3226 nir_intrinsic_instr *instr)
3227 {
3228 LLVMValueRef params[8];
3229 char intrinsic_name[64];
3230 const nir_variable *var = instr->variables[0]->var;
3231 const struct glsl_type *type = glsl_without_array(var->type);
3232
3233 if (ctx->stage == MESA_SHADER_FRAGMENT)
3234 ctx->shader_info->fs.writes_memory = true;
3235
3236 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3237 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3238 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3239 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3240 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3241 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3242 params[4] = ctx->i1false; /* glc */
3243 params[5] = ctx->i1false; /* slc */
3244 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3245 params, 6, 0);
3246 } else {
3247 bool is_da = glsl_sampler_type_is_array(type) ||
3248 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3249 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3250 LLVMValueRef glc = ctx->i1false;
3251 LLVMValueRef slc = ctx->i1false;
3252
3253 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3254 params[1] = get_image_coords(ctx, instr); /* coords */
3255 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3256 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3257 if (HAVE_LLVM <= 0x0309) {
3258 params[4] = ctx->i1false; /* r128 */
3259 params[5] = da;
3260 params[6] = glc;
3261 params[7] = slc;
3262 } else {
3263 LLVMValueRef lwe = ctx->i1false;
3264 params[4] = glc;
3265 params[5] = slc;
3266 params[6] = lwe;
3267 params[7] = da;
3268 }
3269
3270 ac_get_image_intr_name("llvm.amdgcn.image.store",
3271 LLVMTypeOf(params[0]), /* vdata */
3272 LLVMTypeOf(params[1]), /* coords */
3273 LLVMTypeOf(params[2]), /* rsrc */
3274 intrinsic_name, sizeof(intrinsic_name));
3275
3276 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3277 params, 8, 0);
3278 }
3279
3280 }
3281
3282 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3283 nir_intrinsic_instr *instr)
3284 {
3285 LLVMValueRef params[6];
3286 int param_count = 0;
3287 const nir_variable *var = instr->variables[0]->var;
3288
3289 const char *base_name = "llvm.amdgcn.image.atomic";
3290 const char *atomic_name;
3291 LLVMValueRef coords;
3292 char intrinsic_name[32], coords_type[8];
3293 const struct glsl_type *type = glsl_without_array(var->type);
3294
3295 if (ctx->stage == MESA_SHADER_FRAGMENT)
3296 ctx->shader_info->fs.writes_memory = true;
3297
3298 params[param_count++] = get_src(ctx, instr->src[2]);
3299 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3300 params[param_count++] = get_src(ctx, instr->src[3]);
3301
3302 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3303 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3304 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3305 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3306 params[param_count++] = ctx->i32zero; /* voffset */
3307 params[param_count++] = ctx->i1false; /* glc */
3308 params[param_count++] = ctx->i1false; /* slc */
3309 } else {
3310 bool da = glsl_sampler_type_is_array(type) ||
3311 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3312
3313 coords = params[param_count++] = get_image_coords(ctx, instr);
3314 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3315 params[param_count++] = ctx->i1false; /* r128 */
3316 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3317 params[param_count++] = ctx->i1false; /* slc */
3318 }
3319
3320 switch (instr->intrinsic) {
3321 case nir_intrinsic_image_atomic_add:
3322 atomic_name = "add";
3323 break;
3324 case nir_intrinsic_image_atomic_min:
3325 atomic_name = "smin";
3326 break;
3327 case nir_intrinsic_image_atomic_max:
3328 atomic_name = "smax";
3329 break;
3330 case nir_intrinsic_image_atomic_and:
3331 atomic_name = "and";
3332 break;
3333 case nir_intrinsic_image_atomic_or:
3334 atomic_name = "or";
3335 break;
3336 case nir_intrinsic_image_atomic_xor:
3337 atomic_name = "xor";
3338 break;
3339 case nir_intrinsic_image_atomic_exchange:
3340 atomic_name = "swap";
3341 break;
3342 case nir_intrinsic_image_atomic_comp_swap:
3343 atomic_name = "cmpswap";
3344 break;
3345 default:
3346 abort();
3347 }
3348 build_int_type_name(LLVMTypeOf(coords),
3349 coords_type, sizeof(coords_type));
3350
3351 snprintf(intrinsic_name, sizeof(intrinsic_name),
3352 "%s.%s.%s", base_name, atomic_name, coords_type);
3353 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3354 }
3355
3356 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3357 nir_intrinsic_instr *instr)
3358 {
3359 LLVMValueRef res;
3360 const nir_variable *var = instr->variables[0]->var;
3361 const struct glsl_type *type = instr->variables[0]->var->type;
3362 bool da = glsl_sampler_type_is_array(var->type) ||
3363 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3364 if(instr->variables[0]->deref.child)
3365 type = instr->variables[0]->deref.child->type;
3366
3367 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3368 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3369
3370 struct ac_image_args args = { 0 };
3371
3372 args.da = da;
3373 args.dmask = 0xf;
3374 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3375 args.opcode = ac_image_get_resinfo;
3376 args.addr = ctx->i32zero;
3377
3378 res = ac_build_image_opcode(&ctx->ac, &args);
3379
3380 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3381 glsl_sampler_type_is_array(type)) {
3382 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3383 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3384 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3385 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3386 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3387 }
3388 return res;
3389 }
3390
3391 #define NOOP_WAITCNT 0xf7f
3392 #define LGKM_CNT 0x07f
3393 #define VM_CNT 0xf70
3394
3395 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3396 unsigned simm16)
3397 {
3398 LLVMValueRef args[1] = {
3399 LLVMConstInt(ctx->i32, simm16, false),
3400 };
3401 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3402 ctx->voidt, args, 1, 0);
3403 }
3404
3405 static void emit_barrier(struct nir_to_llvm_context *ctx)
3406 {
3407 /* SI only (thanks to a hw bug workaround):
3408 * The real barrier instruction isn’t needed, because an entire patch
3409 * always fits into a single wave.
3410 */
3411 if (ctx->options->chip_class == SI &&
3412 ctx->stage == MESA_SHADER_TESS_CTRL) {
3413 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3414 return;
3415 }
3416 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3417 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3418 }
3419
3420 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3421 nir_intrinsic_instr *instr)
3422 {
3423 LLVMValueRef cond;
3424 ctx->shader_info->fs.can_discard = true;
3425
3426 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3427 get_src(ctx, instr->src[0]),
3428 ctx->i32zero, "");
3429
3430 cond = LLVMBuildSelect(ctx->builder, cond,
3431 LLVMConstReal(ctx->f32, -1.0f),
3432 ctx->f32zero, "");
3433 ac_build_kill(&ctx->ac, cond);
3434 }
3435
3436 static LLVMValueRef
3437 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3438 {
3439 LLVMValueRef result;
3440 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3441 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3442 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3443
3444 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3445 }
3446
3447 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3448 nir_intrinsic_instr *instr)
3449 {
3450 LLVMValueRef ptr, result;
3451 int idx = instr->variables[0]->var->data.driver_location;
3452 LLVMValueRef src = get_src(ctx, instr->src[0]);
3453 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3454
3455 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3456 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3457 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3458 ptr, src, src1,
3459 LLVMAtomicOrderingSequentiallyConsistent,
3460 LLVMAtomicOrderingSequentiallyConsistent,
3461 false);
3462 } else {
3463 LLVMAtomicRMWBinOp op;
3464 switch (instr->intrinsic) {
3465 case nir_intrinsic_var_atomic_add:
3466 op = LLVMAtomicRMWBinOpAdd;
3467 break;
3468 case nir_intrinsic_var_atomic_umin:
3469 op = LLVMAtomicRMWBinOpUMin;
3470 break;
3471 case nir_intrinsic_var_atomic_umax:
3472 op = LLVMAtomicRMWBinOpUMax;
3473 break;
3474 case nir_intrinsic_var_atomic_imin:
3475 op = LLVMAtomicRMWBinOpMin;
3476 break;
3477 case nir_intrinsic_var_atomic_imax:
3478 op = LLVMAtomicRMWBinOpMax;
3479 break;
3480 case nir_intrinsic_var_atomic_and:
3481 op = LLVMAtomicRMWBinOpAnd;
3482 break;
3483 case nir_intrinsic_var_atomic_or:
3484 op = LLVMAtomicRMWBinOpOr;
3485 break;
3486 case nir_intrinsic_var_atomic_xor:
3487 op = LLVMAtomicRMWBinOpXor;
3488 break;
3489 case nir_intrinsic_var_atomic_exchange:
3490 op = LLVMAtomicRMWBinOpXchg;
3491 break;
3492 default:
3493 return NULL;
3494 }
3495
3496 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3497 LLVMAtomicOrderingSequentiallyConsistent,
3498 false);
3499 }
3500 return result;
3501 }
3502
3503 #define INTERP_CENTER 0
3504 #define INTERP_CENTROID 1
3505 #define INTERP_SAMPLE 2
3506
3507 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3508 enum glsl_interp_mode interp, unsigned location)
3509 {
3510 switch (interp) {
3511 case INTERP_MODE_FLAT:
3512 default:
3513 return NULL;
3514 case INTERP_MODE_SMOOTH:
3515 case INTERP_MODE_NONE:
3516 if (location == INTERP_CENTER)
3517 return ctx->persp_center;
3518 else if (location == INTERP_CENTROID)
3519 return ctx->persp_centroid;
3520 else if (location == INTERP_SAMPLE)
3521 return ctx->persp_sample;
3522 break;
3523 case INTERP_MODE_NOPERSPECTIVE:
3524 if (location == INTERP_CENTER)
3525 return ctx->linear_center;
3526 else if (location == INTERP_CENTROID)
3527 return ctx->linear_centroid;
3528 else if (location == INTERP_SAMPLE)
3529 return ctx->linear_sample;
3530 break;
3531 }
3532 return NULL;
3533 }
3534
3535 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3536 LLVMValueRef sample_id)
3537 {
3538 LLVMValueRef result;
3539 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3540
3541 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3542 const_array(ctx->v2f32, 64), "");
3543
3544 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3545 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3546
3547 return result;
3548 }
3549
3550 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3551 {
3552 LLVMValueRef values[2];
3553
3554 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3555 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3556 return ac_build_gather_values(&ctx->ac, values, 2);
3557 }
3558
3559 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3560 nir_intrinsic_instr *instr)
3561 {
3562 LLVMValueRef result[2];
3563 LLVMValueRef interp_param, attr_number;
3564 unsigned location;
3565 unsigned chan;
3566 LLVMValueRef src_c0, src_c1;
3567 LLVMValueRef src0;
3568 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3569 switch (instr->intrinsic) {
3570 case nir_intrinsic_interp_var_at_centroid:
3571 location = INTERP_CENTROID;
3572 break;
3573 case nir_intrinsic_interp_var_at_sample:
3574 case nir_intrinsic_interp_var_at_offset:
3575 location = INTERP_CENTER;
3576 src0 = get_src(ctx, instr->src[0]);
3577 break;
3578 default:
3579 break;
3580 }
3581
3582 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3583 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3584 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3585 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3586 LLVMValueRef sample_position;
3587 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3588
3589 /* fetch sample ID */
3590 sample_position = load_sample_position(ctx, src0);
3591
3592 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3593 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3594 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3595 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3596 }
3597 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3598 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3599
3600 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3601 LLVMValueRef ij_out[2];
3602 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3603
3604 /*
3605 * take the I then J parameters, and the DDX/Y for it, and
3606 * calculate the IJ inputs for the interpolator.
3607 * temp1 = ddx * offset/sample.x + I;
3608 * interp_param.I = ddy * offset/sample.y + temp1;
3609 * temp1 = ddx * offset/sample.x + J;
3610 * interp_param.J = ddy * offset/sample.y + temp1;
3611 */
3612 for (unsigned i = 0; i < 2; i++) {
3613 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3614 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3615 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3616 ddxy_out, ix_ll, "");
3617 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3618 ddxy_out, iy_ll, "");
3619 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3620 interp_param, ix_ll, "");
3621 LLVMValueRef temp1, temp2;
3622
3623 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3624 ctx->f32, "");
3625
3626 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3627 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3628
3629 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3630 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3631
3632 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3633 temp2, ctx->i32, "");
3634 }
3635 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3636
3637 }
3638
3639 for (chan = 0; chan < 2; chan++) {
3640 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3641
3642 if (interp_param) {
3643 interp_param = LLVMBuildBitCast(ctx->builder,
3644 interp_param, LLVMVectorType(ctx->f32, 2), "");
3645 LLVMValueRef i = LLVMBuildExtractElement(
3646 ctx->builder, interp_param, ctx->i32zero, "");
3647 LLVMValueRef j = LLVMBuildExtractElement(
3648 ctx->builder, interp_param, ctx->i32one, "");
3649
3650 result[chan] = ac_build_fs_interp(&ctx->ac,
3651 llvm_chan, attr_number,
3652 ctx->prim_mask, i, j);
3653 } else {
3654 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3655 LLVMConstInt(ctx->i32, 2, false),
3656 llvm_chan, attr_number,
3657 ctx->prim_mask);
3658 }
3659 }
3660 return ac_build_gather_values(&ctx->ac, result, 2);
3661 }
3662
3663 static void
3664 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3665 nir_intrinsic_instr *instr)
3666 {
3667 LLVMValueRef gs_next_vertex;
3668 LLVMValueRef can_emit, kill;
3669 int idx;
3670
3671 assert(instr->const_index[0] == 0);
3672 /* Write vertex attribute values to GSVS ring */
3673 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3674 ctx->gs_next_vertex,
3675 "");
3676
3677 /* If this thread has already emitted the declared maximum number of
3678 * vertices, kill it: excessive vertex emissions are not supposed to
3679 * have any effect, and GS threads have no externally observable
3680 * effects other than emitting vertices.
3681 */
3682 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3683 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3684
3685 kill = LLVMBuildSelect(ctx->builder, can_emit,
3686 LLVMConstReal(ctx->f32, 1.0f),
3687 LLVMConstReal(ctx->f32, -1.0f), "");
3688 ac_build_kill(&ctx->ac, kill);
3689
3690 /* loop num outputs */
3691 idx = 0;
3692 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3693 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3694 int length = 4;
3695 int slot = idx;
3696 int slot_inc = 1;
3697
3698 if (!(ctx->output_mask & (1ull << i)))
3699 continue;
3700
3701 if (i == VARYING_SLOT_CLIP_DIST0) {
3702 /* pack clip and cull into a single set of slots */
3703 length = ctx->num_output_clips + ctx->num_output_culls;
3704 if (length > 4)
3705 slot_inc = 2;
3706 }
3707 for (unsigned j = 0; j < length; j++) {
3708 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3709 out_ptr[j], "");
3710 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3711 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3712 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3713
3714 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3715
3716 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3717 out_val, 1,
3718 voffset, ctx->gs2vs_offset, 0,
3719 1, 1, true, true);
3720 }
3721 idx += slot_inc;
3722 }
3723
3724 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3725 ctx->i32one, "");
3726 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3727
3728 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3729 }
3730
3731 static void
3732 visit_end_primitive(struct nir_to_llvm_context *ctx,
3733 nir_intrinsic_instr *instr)
3734 {
3735 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3736 }
3737
3738 static LLVMValueRef
3739 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3740 nir_intrinsic_instr *instr)
3741 {
3742 LLVMValueRef coord[4] = {
3743 ctx->tes_u,
3744 ctx->tes_v,
3745 ctx->f32zero,
3746 ctx->f32zero,
3747 };
3748
3749 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3750 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3751 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3752
3753 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3754 return LLVMBuildBitCast(ctx->builder, result,
3755 get_def_type(ctx, &instr->dest.ssa), "");
3756 }
3757
3758 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3759 nir_intrinsic_instr *instr)
3760 {
3761 LLVMValueRef result = NULL;
3762
3763 switch (instr->intrinsic) {
3764 case nir_intrinsic_load_work_group_id: {
3765 result = ctx->workgroup_ids;
3766 break;
3767 }
3768 case nir_intrinsic_load_base_vertex: {
3769 result = ctx->base_vertex;
3770 break;
3771 }
3772 case nir_intrinsic_load_vertex_id_zero_base: {
3773 result = ctx->vertex_id;
3774 break;
3775 }
3776 case nir_intrinsic_load_local_invocation_id: {
3777 result = ctx->local_invocation_ids;
3778 break;
3779 }
3780 case nir_intrinsic_load_base_instance:
3781 result = ctx->start_instance;
3782 break;
3783 case nir_intrinsic_load_draw_id:
3784 result = ctx->draw_index;
3785 break;
3786 case nir_intrinsic_load_invocation_id:
3787 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3788 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3789 else
3790 result = ctx->gs_invocation_id;
3791 break;
3792 case nir_intrinsic_load_primitive_id:
3793 if (ctx->stage == MESA_SHADER_GEOMETRY)
3794 result = ctx->gs_prim_id;
3795 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3796 result = ctx->tcs_patch_id;
3797 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3798 result = ctx->tes_patch_id;
3799 else
3800 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3801 break;
3802 case nir_intrinsic_load_sample_id:
3803 ctx->shader_info->fs.force_persample = true;
3804 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3805 break;
3806 case nir_intrinsic_load_sample_pos:
3807 ctx->shader_info->fs.force_persample = true;
3808 result = load_sample_pos(ctx);
3809 break;
3810 case nir_intrinsic_load_sample_mask_in:
3811 result = ctx->sample_coverage;
3812 break;
3813 case nir_intrinsic_load_front_face:
3814 result = ctx->front_face;
3815 break;
3816 case nir_intrinsic_load_instance_id:
3817 result = ctx->instance_id;
3818 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3819 ctx->shader_info->vs.vgpr_comp_cnt);
3820 break;
3821 case nir_intrinsic_load_num_work_groups:
3822 result = ctx->num_work_groups;
3823 break;
3824 case nir_intrinsic_load_local_invocation_index:
3825 result = visit_load_local_invocation_index(ctx);
3826 break;
3827 case nir_intrinsic_load_push_constant:
3828 result = visit_load_push_constant(ctx, instr);
3829 break;
3830 case nir_intrinsic_vulkan_resource_index:
3831 result = visit_vulkan_resource_index(ctx, instr);
3832 break;
3833 case nir_intrinsic_store_ssbo:
3834 visit_store_ssbo(ctx, instr);
3835 break;
3836 case nir_intrinsic_load_ssbo:
3837 result = visit_load_buffer(ctx, instr);
3838 break;
3839 case nir_intrinsic_ssbo_atomic_add:
3840 case nir_intrinsic_ssbo_atomic_imin:
3841 case nir_intrinsic_ssbo_atomic_umin:
3842 case nir_intrinsic_ssbo_atomic_imax:
3843 case nir_intrinsic_ssbo_atomic_umax:
3844 case nir_intrinsic_ssbo_atomic_and:
3845 case nir_intrinsic_ssbo_atomic_or:
3846 case nir_intrinsic_ssbo_atomic_xor:
3847 case nir_intrinsic_ssbo_atomic_exchange:
3848 case nir_intrinsic_ssbo_atomic_comp_swap:
3849 result = visit_atomic_ssbo(ctx, instr);
3850 break;
3851 case nir_intrinsic_load_ubo:
3852 result = visit_load_ubo_buffer(ctx, instr);
3853 break;
3854 case nir_intrinsic_get_buffer_size:
3855 result = visit_get_buffer_size(ctx, instr);
3856 break;
3857 case nir_intrinsic_load_var:
3858 result = visit_load_var(ctx, instr);
3859 break;
3860 case nir_intrinsic_store_var:
3861 visit_store_var(ctx, instr);
3862 break;
3863 case nir_intrinsic_image_load:
3864 result = visit_image_load(ctx, instr);
3865 break;
3866 case nir_intrinsic_image_store:
3867 visit_image_store(ctx, instr);
3868 break;
3869 case nir_intrinsic_image_atomic_add:
3870 case nir_intrinsic_image_atomic_min:
3871 case nir_intrinsic_image_atomic_max:
3872 case nir_intrinsic_image_atomic_and:
3873 case nir_intrinsic_image_atomic_or:
3874 case nir_intrinsic_image_atomic_xor:
3875 case nir_intrinsic_image_atomic_exchange:
3876 case nir_intrinsic_image_atomic_comp_swap:
3877 result = visit_image_atomic(ctx, instr);
3878 break;
3879 case nir_intrinsic_image_size:
3880 result = visit_image_size(ctx, instr);
3881 break;
3882 case nir_intrinsic_discard:
3883 ctx->shader_info->fs.can_discard = true;
3884 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3885 ctx->voidt,
3886 NULL, 0, AC_FUNC_ATTR_LEGACY);
3887 break;
3888 case nir_intrinsic_discard_if:
3889 emit_discard_if(ctx, instr);
3890 break;
3891 case nir_intrinsic_memory_barrier:
3892 emit_waitcnt(ctx, VM_CNT);
3893 break;
3894 case nir_intrinsic_barrier:
3895 emit_barrier(ctx);
3896 break;
3897 case nir_intrinsic_var_atomic_add:
3898 case nir_intrinsic_var_atomic_imin:
3899 case nir_intrinsic_var_atomic_umin:
3900 case nir_intrinsic_var_atomic_imax:
3901 case nir_intrinsic_var_atomic_umax:
3902 case nir_intrinsic_var_atomic_and:
3903 case nir_intrinsic_var_atomic_or:
3904 case nir_intrinsic_var_atomic_xor:
3905 case nir_intrinsic_var_atomic_exchange:
3906 case nir_intrinsic_var_atomic_comp_swap:
3907 result = visit_var_atomic(ctx, instr);
3908 break;
3909 case nir_intrinsic_interp_var_at_centroid:
3910 case nir_intrinsic_interp_var_at_sample:
3911 case nir_intrinsic_interp_var_at_offset:
3912 result = visit_interp(ctx, instr);
3913 break;
3914 case nir_intrinsic_emit_vertex:
3915 visit_emit_vertex(ctx, instr);
3916 break;
3917 case nir_intrinsic_end_primitive:
3918 visit_end_primitive(ctx, instr);
3919 break;
3920 case nir_intrinsic_load_tess_coord:
3921 result = visit_load_tess_coord(ctx, instr);
3922 break;
3923 case nir_intrinsic_load_patch_vertices_in:
3924 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
3925 break;
3926 default:
3927 fprintf(stderr, "Unknown intrinsic: ");
3928 nir_print_instr(&instr->instr, stderr);
3929 fprintf(stderr, "\n");
3930 break;
3931 }
3932 if (result) {
3933 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3934 }
3935 }
3936
3937 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3938 nir_deref_var *deref,
3939 enum desc_type desc_type)
3940 {
3941 unsigned desc_set = deref->var->data.descriptor_set;
3942 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3943 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3944 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3945 unsigned offset = binding->offset;
3946 unsigned stride = binding->size;
3947 unsigned type_size;
3948 LLVMBuilderRef builder = ctx->builder;
3949 LLVMTypeRef type;
3950 LLVMValueRef index = NULL;
3951 unsigned constant_index = 0;
3952
3953 assert(deref->var->data.binding < layout->binding_count);
3954
3955 switch (desc_type) {
3956 case DESC_IMAGE:
3957 type = ctx->v8i32;
3958 type_size = 32;
3959 break;
3960 case DESC_FMASK:
3961 type = ctx->v8i32;
3962 offset += 32;
3963 type_size = 32;
3964 break;
3965 case DESC_SAMPLER:
3966 type = ctx->v4i32;
3967 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3968 offset += 64;
3969
3970 type_size = 16;
3971 break;
3972 case DESC_BUFFER:
3973 type = ctx->v4i32;
3974 type_size = 16;
3975 break;
3976 default:
3977 unreachable("invalid desc_type\n");
3978 }
3979
3980 if (deref->deref.child) {
3981 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3982
3983 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3984 offset += child->base_offset * stride;
3985 if (child->deref_array_type == nir_deref_array_type_indirect) {
3986 index = get_src(ctx, child->indirect);
3987 }
3988
3989 constant_index = child->base_offset;
3990 }
3991 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
3992 (!index || binding->immutable_samplers_equal)) {
3993 if (binding->immutable_samplers_equal)
3994 constant_index = 0;
3995
3996 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
3997
3998 LLVMValueRef constants[] = {
3999 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4000 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4001 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4002 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4003 };
4004 return ac_build_gather_values(&ctx->ac, constants, 4);
4005 }
4006
4007 assert(stride % type_size == 0);
4008
4009 if (!index)
4010 index = ctx->i32zero;
4011
4012 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4013
4014 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4015 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4016
4017 return ac_build_indexed_load_const(&ctx->ac, list, index);
4018 }
4019
4020 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4021 struct ac_image_args *args,
4022 nir_tex_instr *instr,
4023 nir_texop op,
4024 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4025 LLVMValueRef *param, unsigned count,
4026 unsigned dmask)
4027 {
4028 unsigned is_rect = 0;
4029 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4030
4031 if (op == nir_texop_lod)
4032 da = false;
4033 /* Pad to power of two vector */
4034 while (count < util_next_power_of_two(count))
4035 param[count++] = LLVMGetUndef(ctx->i32);
4036
4037 if (count > 1)
4038 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4039 else
4040 args->addr = param[0];
4041
4042 args->resource = res_ptr;
4043 args->sampler = samp_ptr;
4044
4045 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4046 args->addr = param[0];
4047 return;
4048 }
4049
4050 args->dmask = dmask;
4051 args->unorm = is_rect;
4052 args->da = da;
4053 }
4054
4055 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4056 *
4057 * SI-CI:
4058 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4059 * filtering manually. The driver sets img7 to a mask clearing
4060 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4061 * s_and_b32 samp0, samp0, img7
4062 *
4063 * VI:
4064 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4065 */
4066 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4067 LLVMValueRef res, LLVMValueRef samp)
4068 {
4069 LLVMBuilderRef builder = ctx->builder;
4070 LLVMValueRef img7, samp0;
4071
4072 if (ctx->options->chip_class >= VI)
4073 return samp;
4074
4075 img7 = LLVMBuildExtractElement(builder, res,
4076 LLVMConstInt(ctx->i32, 7, 0), "");
4077 samp0 = LLVMBuildExtractElement(builder, samp,
4078 LLVMConstInt(ctx->i32, 0, 0), "");
4079 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4080 return LLVMBuildInsertElement(builder, samp, samp0,
4081 LLVMConstInt(ctx->i32, 0, 0), "");
4082 }
4083
4084 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4085 nir_tex_instr *instr,
4086 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4087 LLVMValueRef *fmask_ptr)
4088 {
4089 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4090 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4091 else
4092 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4093 if (samp_ptr) {
4094 if (instr->sampler)
4095 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4096 else
4097 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4098 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4099 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4100 }
4101 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4102 instr->op == nir_texop_samples_identical))
4103 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4104 }
4105
4106 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4107 LLVMValueRef coord)
4108 {
4109 coord = to_float(ctx, coord);
4110 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4111 coord = to_integer(ctx, coord);
4112 return coord;
4113 }
4114
4115 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4116 {
4117 LLVMValueRef result = NULL;
4118 struct ac_image_args args = { 0 };
4119 unsigned dmask = 0xf;
4120 LLVMValueRef address[16];
4121 LLVMValueRef coords[5];
4122 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4123 LLVMValueRef bias = NULL, offsets = NULL;
4124 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4125 LLVMValueRef ddx = NULL, ddy = NULL;
4126 LLVMValueRef derivs[6];
4127 unsigned chan, count = 0;
4128 unsigned const_src = 0, num_deriv_comp = 0;
4129
4130 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4131
4132 for (unsigned i = 0; i < instr->num_srcs; i++) {
4133 switch (instr->src[i].src_type) {
4134 case nir_tex_src_coord:
4135 coord = get_src(ctx, instr->src[i].src);
4136 break;
4137 case nir_tex_src_projector:
4138 break;
4139 case nir_tex_src_comparator:
4140 comparator = get_src(ctx, instr->src[i].src);
4141 break;
4142 case nir_tex_src_offset:
4143 offsets = get_src(ctx, instr->src[i].src);
4144 const_src = i;
4145 break;
4146 case nir_tex_src_bias:
4147 bias = get_src(ctx, instr->src[i].src);
4148 break;
4149 case nir_tex_src_lod:
4150 lod = get_src(ctx, instr->src[i].src);
4151 break;
4152 case nir_tex_src_ms_index:
4153 sample_index = get_src(ctx, instr->src[i].src);
4154 break;
4155 case nir_tex_src_ms_mcs:
4156 break;
4157 case nir_tex_src_ddx:
4158 ddx = get_src(ctx, instr->src[i].src);
4159 num_deriv_comp = instr->src[i].src.ssa->num_components;
4160 break;
4161 case nir_tex_src_ddy:
4162 ddy = get_src(ctx, instr->src[i].src);
4163 break;
4164 case nir_tex_src_texture_offset:
4165 case nir_tex_src_sampler_offset:
4166 case nir_tex_src_plane:
4167 default:
4168 break;
4169 }
4170 }
4171
4172 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4173 result = get_buffer_size(ctx, res_ptr, true);
4174 goto write_result;
4175 }
4176
4177 if (instr->op == nir_texop_texture_samples) {
4178 LLVMValueRef res, samples, is_msaa;
4179 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4180 samples = LLVMBuildExtractElement(ctx->builder, res,
4181 LLVMConstInt(ctx->i32, 3, false), "");
4182 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4183 LLVMConstInt(ctx->i32, 28, false), "");
4184 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4185 LLVMConstInt(ctx->i32, 0xe, false), "");
4186 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4187 LLVMConstInt(ctx->i32, 0xe, false), "");
4188
4189 samples = LLVMBuildLShr(ctx->builder, samples,
4190 LLVMConstInt(ctx->i32, 16, false), "");
4191 samples = LLVMBuildAnd(ctx->builder, samples,
4192 LLVMConstInt(ctx->i32, 0xf, false), "");
4193 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4194 samples, "");
4195 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4196 ctx->i32one, "");
4197 result = samples;
4198 goto write_result;
4199 }
4200
4201 if (coord)
4202 for (chan = 0; chan < instr->coord_components; chan++)
4203 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4204
4205 if (offsets && instr->op != nir_texop_txf) {
4206 LLVMValueRef offset[3], pack;
4207 for (chan = 0; chan < 3; ++chan)
4208 offset[chan] = ctx->i32zero;
4209
4210 args.offset = true;
4211 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4212 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4213 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4214 LLVMConstInt(ctx->i32, 0x3f, false), "");
4215 if (chan)
4216 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4217 LLVMConstInt(ctx->i32, chan * 8, false), "");
4218 }
4219 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4220 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4221 address[count++] = pack;
4222
4223 }
4224 /* pack LOD bias value */
4225 if (instr->op == nir_texop_txb && bias) {
4226 address[count++] = bias;
4227 }
4228
4229 /* Pack depth comparison value */
4230 if (instr->is_shadow && comparator) {
4231 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4232 }
4233
4234 /* pack derivatives */
4235 if (ddx || ddy) {
4236 switch (instr->sampler_dim) {
4237 case GLSL_SAMPLER_DIM_3D:
4238 case GLSL_SAMPLER_DIM_CUBE:
4239 num_deriv_comp = 3;
4240 break;
4241 case GLSL_SAMPLER_DIM_2D:
4242 default:
4243 num_deriv_comp = 2;
4244 break;
4245 case GLSL_SAMPLER_DIM_1D:
4246 num_deriv_comp = 1;
4247 break;
4248 }
4249
4250 for (unsigned i = 0; i < num_deriv_comp; i++) {
4251 derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4252 derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4253 }
4254 }
4255
4256 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4257 if (instr->is_array && instr->op != nir_texop_lod)
4258 coords[3] = apply_round_slice(ctx, coords[3]);
4259 for (chan = 0; chan < instr->coord_components; chan++)
4260 coords[chan] = to_float(ctx, coords[chan]);
4261 if (instr->coord_components == 3)
4262 coords[3] = LLVMGetUndef(ctx->f32);
4263 ac_prepare_cube_coords(&ctx->ac,
4264 instr->op == nir_texop_txd, instr->is_array,
4265 coords, derivs);
4266 if (num_deriv_comp)
4267 num_deriv_comp--;
4268 }
4269
4270 if (ddx || ddy) {
4271 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4272 address[count++] = derivs[i];
4273 }
4274
4275 /* Pack texture coordinates */
4276 if (coord) {
4277 address[count++] = coords[0];
4278 if (instr->coord_components > 1) {
4279 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4280 coords[1] = apply_round_slice(ctx, coords[1]);
4281 }
4282 address[count++] = coords[1];
4283 }
4284 if (instr->coord_components > 2) {
4285 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4286 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4287 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4288 instr->op != nir_texop_txf) {
4289 coords[2] = apply_round_slice(ctx, coords[2]);
4290 }
4291 address[count++] = coords[2];
4292 }
4293 }
4294
4295 /* Pack LOD */
4296 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
4297 address[count++] = lod;
4298 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4299 address[count++] = sample_index;
4300 } else if(instr->op == nir_texop_txs) {
4301 count = 0;
4302 if (lod)
4303 address[count++] = lod;
4304 else
4305 address[count++] = ctx->i32zero;
4306 }
4307
4308 for (chan = 0; chan < count; chan++) {
4309 address[chan] = LLVMBuildBitCast(ctx->builder,
4310 address[chan], ctx->i32, "");
4311 }
4312
4313 if (instr->op == nir_texop_samples_identical) {
4314 LLVMValueRef txf_address[4];
4315 struct ac_image_args txf_args = { 0 };
4316 unsigned txf_count = count;
4317 memcpy(txf_address, address, sizeof(txf_address));
4318
4319 if (!instr->is_array)
4320 txf_address[2] = ctx->i32zero;
4321 txf_address[3] = ctx->i32zero;
4322
4323 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4324 fmask_ptr, NULL,
4325 txf_address, txf_count, 0xf);
4326
4327 result = build_tex_intrinsic(ctx, instr, &txf_args);
4328
4329 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4330 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4331 goto write_result;
4332 }
4333
4334 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4335 instr->op != nir_texop_txs) {
4336 unsigned sample_chan = instr->is_array ? 3 : 2;
4337 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4338 address[0],
4339 address[1],
4340 instr->is_array ? address[2] : NULL,
4341 address[sample_chan],
4342 fmask_ptr);
4343 }
4344
4345 if (offsets && instr->op == nir_texop_txf) {
4346 nir_const_value *const_offset =
4347 nir_src_as_const_value(instr->src[const_src].src);
4348 int num_offsets = instr->src[const_src].src.ssa->num_components;
4349 assert(const_offset);
4350 num_offsets = MIN2(num_offsets, instr->coord_components);
4351 if (num_offsets > 2)
4352 address[2] = LLVMBuildAdd(ctx->builder,
4353 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4354 if (num_offsets > 1)
4355 address[1] = LLVMBuildAdd(ctx->builder,
4356 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4357 address[0] = LLVMBuildAdd(ctx->builder,
4358 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4359
4360 }
4361
4362 /* TODO TG4 support */
4363 if (instr->op == nir_texop_tg4) {
4364 if (instr->is_shadow)
4365 dmask = 1;
4366 else
4367 dmask = 1 << instr->component;
4368 }
4369 set_tex_fetch_args(ctx, &args, instr, instr->op,
4370 res_ptr, samp_ptr, address, count, dmask);
4371
4372 result = build_tex_intrinsic(ctx, instr, &args);
4373
4374 if (instr->op == nir_texop_query_levels)
4375 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4376 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4377 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4378 else if (instr->op == nir_texop_txs &&
4379 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4380 instr->is_array) {
4381 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4382 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4383 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4384 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4385 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4386 } else if (instr->dest.ssa.num_components != 4)
4387 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4388
4389 write_result:
4390 if (result) {
4391 assert(instr->dest.is_ssa);
4392 result = to_integer(ctx, result);
4393 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4394 }
4395 }
4396
4397
4398 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4399 {
4400 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4401 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4402
4403 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4404 _mesa_hash_table_insert(ctx->phis, instr, result);
4405 }
4406
4407 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4408 nir_phi_instr *instr,
4409 LLVMValueRef llvm_phi)
4410 {
4411 nir_foreach_phi_src(src, instr) {
4412 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4413 LLVMValueRef llvm_src = get_src(ctx, src->src);
4414
4415 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4416 }
4417 }
4418
4419 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4420 {
4421 struct hash_entry *entry;
4422 hash_table_foreach(ctx->phis, entry) {
4423 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4424 (LLVMValueRef)entry->data);
4425 }
4426 }
4427
4428
4429 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4430 nir_ssa_undef_instr *instr)
4431 {
4432 unsigned num_components = instr->def.num_components;
4433 LLVMValueRef undef;
4434
4435 if (num_components == 1)
4436 undef = LLVMGetUndef(ctx->i32);
4437 else {
4438 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4439 }
4440 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4441 }
4442
4443 static void visit_jump(struct nir_to_llvm_context *ctx,
4444 nir_jump_instr *instr)
4445 {
4446 switch (instr->type) {
4447 case nir_jump_break:
4448 LLVMBuildBr(ctx->builder, ctx->break_block);
4449 LLVMClearInsertionPosition(ctx->builder);
4450 break;
4451 case nir_jump_continue:
4452 LLVMBuildBr(ctx->builder, ctx->continue_block);
4453 LLVMClearInsertionPosition(ctx->builder);
4454 break;
4455 default:
4456 fprintf(stderr, "Unknown NIR jump instr: ");
4457 nir_print_instr(&instr->instr, stderr);
4458 fprintf(stderr, "\n");
4459 abort();
4460 }
4461 }
4462
4463 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4464 struct exec_list *list);
4465
4466 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4467 {
4468 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4469 nir_foreach_instr(instr, block)
4470 {
4471 switch (instr->type) {
4472 case nir_instr_type_alu:
4473 visit_alu(ctx, nir_instr_as_alu(instr));
4474 break;
4475 case nir_instr_type_load_const:
4476 visit_load_const(ctx, nir_instr_as_load_const(instr));
4477 break;
4478 case nir_instr_type_intrinsic:
4479 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4480 break;
4481 case nir_instr_type_tex:
4482 visit_tex(ctx, nir_instr_as_tex(instr));
4483 break;
4484 case nir_instr_type_phi:
4485 visit_phi(ctx, nir_instr_as_phi(instr));
4486 break;
4487 case nir_instr_type_ssa_undef:
4488 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4489 break;
4490 case nir_instr_type_jump:
4491 visit_jump(ctx, nir_instr_as_jump(instr));
4492 break;
4493 default:
4494 fprintf(stderr, "Unknown NIR instr type: ");
4495 nir_print_instr(instr, stderr);
4496 fprintf(stderr, "\n");
4497 abort();
4498 }
4499 }
4500
4501 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4502 }
4503
4504 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4505 {
4506 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4507
4508 LLVMBasicBlockRef merge_block =
4509 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4510 LLVMBasicBlockRef if_block =
4511 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4512 LLVMBasicBlockRef else_block = merge_block;
4513 if (!exec_list_is_empty(&if_stmt->else_list))
4514 else_block = LLVMAppendBasicBlockInContext(
4515 ctx->context, ctx->main_function, "");
4516
4517 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4518 LLVMConstInt(ctx->i32, 0, false), "");
4519 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4520
4521 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4522 visit_cf_list(ctx, &if_stmt->then_list);
4523 if (LLVMGetInsertBlock(ctx->builder))
4524 LLVMBuildBr(ctx->builder, merge_block);
4525
4526 if (!exec_list_is_empty(&if_stmt->else_list)) {
4527 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4528 visit_cf_list(ctx, &if_stmt->else_list);
4529 if (LLVMGetInsertBlock(ctx->builder))
4530 LLVMBuildBr(ctx->builder, merge_block);
4531 }
4532
4533 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4534 }
4535
4536 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4537 {
4538 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4539 LLVMBasicBlockRef break_parent = ctx->break_block;
4540
4541 ctx->continue_block =
4542 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4543 ctx->break_block =
4544 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4545
4546 LLVMBuildBr(ctx->builder, ctx->continue_block);
4547 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4548 visit_cf_list(ctx, &loop->body);
4549
4550 if (LLVMGetInsertBlock(ctx->builder))
4551 LLVMBuildBr(ctx->builder, ctx->continue_block);
4552 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4553
4554 ctx->continue_block = continue_parent;
4555 ctx->break_block = break_parent;
4556 }
4557
4558 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4559 struct exec_list *list)
4560 {
4561 foreach_list_typed(nir_cf_node, node, node, list)
4562 {
4563 switch (node->type) {
4564 case nir_cf_node_block:
4565 visit_block(ctx, nir_cf_node_as_block(node));
4566 break;
4567
4568 case nir_cf_node_if:
4569 visit_if(ctx, nir_cf_node_as_if(node));
4570 break;
4571
4572 case nir_cf_node_loop:
4573 visit_loop(ctx, nir_cf_node_as_loop(node));
4574 break;
4575
4576 default:
4577 assert(0);
4578 }
4579 }
4580 }
4581
4582 static void
4583 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4584 struct nir_variable *variable)
4585 {
4586 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4587 LLVMValueRef t_offset;
4588 LLVMValueRef t_list;
4589 LLVMValueRef input;
4590 LLVMValueRef buffer_index;
4591 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4592 int idx = variable->data.location;
4593 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4594
4595 variable->data.driver_location = idx * 4;
4596
4597 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4598 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4599 ctx->start_instance, "");
4600 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4601 ctx->shader_info->vs.vgpr_comp_cnt);
4602 } else
4603 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4604 ctx->base_vertex, "");
4605
4606 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4607 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4608
4609 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4610
4611 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4612 buffer_index,
4613 LLVMConstInt(ctx->i32, 0, false),
4614 true);
4615
4616 for (unsigned chan = 0; chan < 4; chan++) {
4617 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4618 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4619 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4620 input, llvm_chan, ""));
4621 }
4622 }
4623 }
4624
4625 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4626 unsigned attr,
4627 LLVMValueRef interp_param,
4628 LLVMValueRef prim_mask,
4629 LLVMValueRef result[4])
4630 {
4631 LLVMValueRef attr_number;
4632 unsigned chan;
4633 LLVMValueRef i, j;
4634 bool interp = interp_param != NULL;
4635
4636 attr_number = LLVMConstInt(ctx->i32, attr, false);
4637
4638 /* fs.constant returns the param from the middle vertex, so it's not
4639 * really useful for flat shading. It's meant to be used for custom
4640 * interpolation (but the intrinsic can't fetch from the other two
4641 * vertices).
4642 *
4643 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4644 * to do the right thing. The only reason we use fs.constant is that
4645 * fs.interp cannot be used on integers, because they can be equal
4646 * to NaN.
4647 */
4648 if (interp) {
4649 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4650 LLVMVectorType(ctx->f32, 2), "");
4651
4652 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4653 ctx->i32zero, "");
4654 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4655 ctx->i32one, "");
4656 }
4657
4658 for (chan = 0; chan < 4; chan++) {
4659 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4660
4661 if (interp) {
4662 result[chan] = ac_build_fs_interp(&ctx->ac,
4663 llvm_chan,
4664 attr_number,
4665 prim_mask, i, j);
4666 } else {
4667 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4668 LLVMConstInt(ctx->i32, 2, false),
4669 llvm_chan,
4670 attr_number,
4671 prim_mask);
4672 }
4673 }
4674 }
4675
4676 static void
4677 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4678 struct nir_variable *variable)
4679 {
4680 int idx = variable->data.location;
4681 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4682 LLVMValueRef interp;
4683
4684 variable->data.driver_location = idx * 4;
4685 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4686
4687 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4688 unsigned interp_type;
4689 if (variable->data.sample) {
4690 interp_type = INTERP_SAMPLE;
4691 ctx->shader_info->fs.force_persample = true;
4692 } else if (variable->data.centroid)
4693 interp_type = INTERP_CENTROID;
4694 else
4695 interp_type = INTERP_CENTER;
4696
4697 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4698 } else
4699 interp = NULL;
4700
4701 for (unsigned i = 0; i < attrib_count; ++i)
4702 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4703
4704 }
4705
4706 static void
4707 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4708 struct nir_variable *variable)
4709 {
4710 switch (ctx->stage) {
4711 case MESA_SHADER_VERTEX:
4712 handle_vs_input_decl(ctx, variable);
4713 break;
4714 case MESA_SHADER_FRAGMENT:
4715 handle_fs_input_decl(ctx, variable);
4716 break;
4717 default:
4718 break;
4719 }
4720
4721 }
4722
4723 static void
4724 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4725 struct nir_shader *nir)
4726 {
4727 unsigned index = 0;
4728 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4729 LLVMValueRef interp_param;
4730 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4731
4732 if (!(ctx->input_mask & (1ull << i)))
4733 continue;
4734
4735 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4736 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4737 interp_param = *inputs;
4738 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4739 inputs);
4740
4741 if (!interp_param)
4742 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4743 ++index;
4744 } else if (i == VARYING_SLOT_POS) {
4745 for(int i = 0; i < 3; ++i)
4746 inputs[i] = ctx->frag_pos[i];
4747
4748 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4749 }
4750 }
4751 ctx->shader_info->fs.num_interp = index;
4752 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4753 ctx->shader_info->fs.has_pcoord = true;
4754 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4755 ctx->shader_info->fs.prim_id_input = true;
4756 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4757 ctx->shader_info->fs.layer_input = true;
4758 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4759 }
4760
4761 static LLVMValueRef
4762 ac_build_alloca(struct nir_to_llvm_context *ctx,
4763 LLVMTypeRef type,
4764 const char *name)
4765 {
4766 LLVMBuilderRef builder = ctx->builder;
4767 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4768 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4769 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4770 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4771 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4772 LLVMValueRef res;
4773
4774 if (first_instr) {
4775 LLVMPositionBuilderBefore(first_builder, first_instr);
4776 } else {
4777 LLVMPositionBuilderAtEnd(first_builder, first_block);
4778 }
4779
4780 res = LLVMBuildAlloca(first_builder, type, name);
4781 LLVMBuildStore(builder, LLVMConstNull(type), res);
4782
4783 LLVMDisposeBuilder(first_builder);
4784
4785 return res;
4786 }
4787
4788 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4789 LLVMTypeRef type,
4790 const char *name)
4791 {
4792 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4793 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4794 return ptr;
4795 }
4796
4797 static void
4798 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4799 struct nir_variable *variable)
4800 {
4801 int idx = variable->data.location + variable->data.index;
4802 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4803 uint64_t mask_attribs;
4804 variable->data.driver_location = idx * 4;
4805
4806 /* tess ctrl has it's own load/store paths for outputs */
4807 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4808 return;
4809
4810 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4811 if (ctx->stage == MESA_SHADER_VERTEX ||
4812 ctx->stage == MESA_SHADER_TESS_EVAL ||
4813 ctx->stage == MESA_SHADER_GEOMETRY) {
4814 if (idx == VARYING_SLOT_CLIP_DIST0) {
4815 int length = ctx->num_output_clips + ctx->num_output_culls;
4816 if (ctx->stage == MESA_SHADER_VERTEX) {
4817 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4818 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4819 }
4820 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4821 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4822 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4823 }
4824
4825 if (length > 4)
4826 attrib_count = 2;
4827 else
4828 attrib_count = 1;
4829 mask_attribs = 1ull << idx;
4830 }
4831 }
4832
4833 for (unsigned i = 0; i < attrib_count; ++i) {
4834 for (unsigned chan = 0; chan < 4; chan++) {
4835 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4836 si_build_alloca_undef(ctx, ctx->f32, "");
4837 }
4838 }
4839 ctx->output_mask |= mask_attribs;
4840 }
4841
4842 static void
4843 setup_locals(struct nir_to_llvm_context *ctx,
4844 struct nir_function *func)
4845 {
4846 int i, j;
4847 ctx->num_locals = 0;
4848 nir_foreach_variable(variable, &func->impl->locals) {
4849 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4850 variable->data.driver_location = ctx->num_locals * 4;
4851 ctx->num_locals += attrib_count;
4852 }
4853 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4854 if (!ctx->locals)
4855 return;
4856
4857 for (i = 0; i < ctx->num_locals; i++) {
4858 for (j = 0; j < 4; j++) {
4859 ctx->locals[i * 4 + j] =
4860 si_build_alloca_undef(ctx, ctx->f32, "temp");
4861 }
4862 }
4863 }
4864
4865 static LLVMValueRef
4866 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4867 {
4868 v = to_float(ctx, v);
4869 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4870 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4871 }
4872
4873
4874 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4875 LLVMValueRef src0, LLVMValueRef src1)
4876 {
4877 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4878 LLVMValueRef comp[2];
4879
4880 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4881 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4882 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4883 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4884 }
4885
4886 /* Initialize arguments for the shader export intrinsic */
4887 static void
4888 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4889 LLVMValueRef *values,
4890 unsigned target,
4891 struct ac_export_args *args)
4892 {
4893 /* Default is 0xf. Adjusted below depending on the format. */
4894 args->enabled_channels = 0xf;
4895
4896 /* Specify whether the EXEC mask represents the valid mask */
4897 args->valid_mask = 0;
4898
4899 /* Specify whether this is the last export */
4900 args->done = 0;
4901
4902 /* Specify the target we are exporting */
4903 args->target = target;
4904
4905 args->compr = false;
4906 args->out[0] = LLVMGetUndef(ctx->f32);
4907 args->out[1] = LLVMGetUndef(ctx->f32);
4908 args->out[2] = LLVMGetUndef(ctx->f32);
4909 args->out[3] = LLVMGetUndef(ctx->f32);
4910
4911 if (!values)
4912 return;
4913
4914 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4915 LLVMValueRef val[4];
4916 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4917 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4918 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4919
4920 switch(col_format) {
4921 case V_028714_SPI_SHADER_ZERO:
4922 args->enabled_channels = 0; /* writemask */
4923 args->target = V_008DFC_SQ_EXP_NULL;
4924 break;
4925
4926 case V_028714_SPI_SHADER_32_R:
4927 args->enabled_channels = 1;
4928 args->out[0] = values[0];
4929 break;
4930
4931 case V_028714_SPI_SHADER_32_GR:
4932 args->enabled_channels = 0x3;
4933 args->out[0] = values[0];
4934 args->out[1] = values[1];
4935 break;
4936
4937 case V_028714_SPI_SHADER_32_AR:
4938 args->enabled_channels = 0x9;
4939 args->out[0] = values[0];
4940 args->out[3] = values[3];
4941 break;
4942
4943 case V_028714_SPI_SHADER_FP16_ABGR:
4944 args->compr = 1;
4945
4946 for (unsigned chan = 0; chan < 2; chan++) {
4947 LLVMValueRef pack_args[2] = {
4948 values[2 * chan],
4949 values[2 * chan + 1]
4950 };
4951 LLVMValueRef packed;
4952
4953 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
4954 args->out[chan] = packed;
4955 }
4956 break;
4957
4958 case V_028714_SPI_SHADER_UNORM16_ABGR:
4959 for (unsigned chan = 0; chan < 4; chan++) {
4960 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
4961 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4962 LLVMConstReal(ctx->f32, 65535), "");
4963 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4964 LLVMConstReal(ctx->f32, 0.5), "");
4965 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4966 ctx->i32, "");
4967 }
4968
4969 args->compr = 1;
4970 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4971 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4972 break;
4973
4974 case V_028714_SPI_SHADER_SNORM16_ABGR:
4975 for (unsigned chan = 0; chan < 4; chan++) {
4976 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4977 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4978 LLVMConstReal(ctx->f32, 32767), "");
4979
4980 /* If positive, add 0.5, else add -0.5. */
4981 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4982 LLVMBuildSelect(ctx->builder,
4983 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4984 val[chan], ctx->f32zero, ""),
4985 LLVMConstReal(ctx->f32, 0.5),
4986 LLVMConstReal(ctx->f32, -0.5), ""), "");
4987 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4988 }
4989
4990 args->compr = 1;
4991 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4992 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4993 break;
4994
4995 case V_028714_SPI_SHADER_UINT16_ABGR: {
4996 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4997
4998 for (unsigned chan = 0; chan < 4; chan++) {
4999 val[chan] = to_integer(ctx, values[chan]);
5000 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
5001 }
5002
5003 args->compr = 1;
5004 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5005 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5006 break;
5007 }
5008
5009 case V_028714_SPI_SHADER_SINT16_ABGR: {
5010 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5011 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5012
5013 /* Clamp. */
5014 for (unsigned chan = 0; chan < 4; chan++) {
5015 val[chan] = to_integer(ctx, values[chan]);
5016 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
5017 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
5018 }
5019
5020 args->compr = 1;
5021 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5022 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5023 break;
5024 }
5025
5026 default:
5027 case V_028714_SPI_SHADER_32_ABGR:
5028 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5029 break;
5030 }
5031 } else
5032 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5033
5034 for (unsigned i = 0; i < 4; ++i)
5035 args->out[i] = to_float(ctx, args->out[i]);
5036 }
5037
5038 static void
5039 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5040 struct ac_vs_output_info *outinfo)
5041 {
5042 uint32_t param_count = 0;
5043 unsigned target;
5044 unsigned pos_idx, num_pos_exports = 0;
5045 struct ac_export_args args, pos_args[4] = {};
5046 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5047 int i;
5048
5049 outinfo->prim_id_output = 0xffffffff;
5050 outinfo->layer_output = 0xffffffff;
5051 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5052 LLVMValueRef slots[8];
5053 unsigned j;
5054
5055 if (outinfo->cull_dist_mask)
5056 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5057
5058 i = VARYING_SLOT_CLIP_DIST0;
5059 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5060 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5061 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5062
5063 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5064 slots[i] = LLVMGetUndef(ctx->f32);
5065
5066 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5067 target = V_008DFC_SQ_EXP_POS + 3;
5068 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5069 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5070 &args, sizeof(args));
5071 }
5072
5073 target = V_008DFC_SQ_EXP_POS + 2;
5074 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5075 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5076 &args, sizeof(args));
5077
5078 }
5079
5080 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5081 LLVMValueRef values[4];
5082 if (!(ctx->output_mask & (1ull << i)))
5083 continue;
5084
5085 for (unsigned j = 0; j < 4; j++)
5086 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5087 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5088
5089 if (i == VARYING_SLOT_POS) {
5090 target = V_008DFC_SQ_EXP_POS;
5091 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5092 continue;
5093 } else if (i == VARYING_SLOT_PSIZ) {
5094 outinfo->writes_pointsize = true;
5095 psize_value = values[0];
5096 continue;
5097 } else if (i == VARYING_SLOT_LAYER) {
5098 outinfo->writes_layer = true;
5099 layer_value = values[0];
5100 outinfo->layer_output = param_count;
5101 target = V_008DFC_SQ_EXP_PARAM + param_count;
5102 param_count++;
5103 } else if (i == VARYING_SLOT_VIEWPORT) {
5104 outinfo->writes_viewport_index = true;
5105 viewport_index_value = values[0];
5106 continue;
5107 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5108 outinfo->prim_id_output = param_count;
5109 target = V_008DFC_SQ_EXP_PARAM + param_count;
5110 param_count++;
5111 } else if (i >= VARYING_SLOT_VAR0) {
5112 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5113 target = V_008DFC_SQ_EXP_PARAM + param_count;
5114 param_count++;
5115 }
5116
5117 si_llvm_init_export_args(ctx, values, target, &args);
5118
5119 if (target >= V_008DFC_SQ_EXP_POS &&
5120 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5121 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5122 &args, sizeof(args));
5123 } else {
5124 ac_build_export(&ctx->ac, &args);
5125 }
5126 }
5127
5128 /* We need to add the position output manually if it's missing. */
5129 if (!pos_args[0].out[0]) {
5130 pos_args[0].enabled_channels = 0xf;
5131 pos_args[0].valid_mask = 0;
5132 pos_args[0].done = 0;
5133 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5134 pos_args[0].compr = 0;
5135 pos_args[0].out[0] = ctx->f32zero; /* X */
5136 pos_args[0].out[1] = ctx->f32zero; /* Y */
5137 pos_args[0].out[2] = ctx->f32zero; /* Z */
5138 pos_args[0].out[3] = ctx->f32one; /* W */
5139 }
5140
5141 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5142 (outinfo->writes_layer == true ? 4 : 0) |
5143 (outinfo->writes_viewport_index == true ? 8 : 0));
5144 if (mask) {
5145 pos_args[1].enabled_channels = mask;
5146 pos_args[1].valid_mask = 0;
5147 pos_args[1].done = 0;
5148 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5149 pos_args[1].compr = 0;
5150 pos_args[1].out[0] = ctx->f32zero; /* X */
5151 pos_args[1].out[1] = ctx->f32zero; /* Y */
5152 pos_args[1].out[2] = ctx->f32zero; /* Z */
5153 pos_args[1].out[3] = ctx->f32zero; /* W */
5154
5155 if (outinfo->writes_pointsize == true)
5156 pos_args[1].out[0] = psize_value;
5157 if (outinfo->writes_layer == true)
5158 pos_args[1].out[2] = layer_value;
5159 if (outinfo->writes_viewport_index == true)
5160 pos_args[1].out[3] = viewport_index_value;
5161 }
5162 for (i = 0; i < 4; i++) {
5163 if (pos_args[i].out[0])
5164 num_pos_exports++;
5165 }
5166
5167 pos_idx = 0;
5168 for (i = 0; i < 4; i++) {
5169 if (!pos_args[i].out[0])
5170 continue;
5171
5172 /* Specify the target we are exporting */
5173 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5174 if (pos_idx == num_pos_exports)
5175 pos_args[i].done = 1;
5176 ac_build_export(&ctx->ac, &pos_args[i]);
5177 }
5178
5179 outinfo->pos_exports = num_pos_exports;
5180 outinfo->param_exports = param_count;
5181 }
5182
5183 static void
5184 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5185 struct ac_es_output_info *outinfo)
5186 {
5187 int j;
5188 uint64_t max_output_written = 0;
5189 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5190 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5191 int param_index;
5192 int length = 4;
5193
5194 if (!(ctx->output_mask & (1ull << i)))
5195 continue;
5196
5197 if (i == VARYING_SLOT_CLIP_DIST0)
5198 length = ctx->num_output_clips + ctx->num_output_culls;
5199
5200 param_index = shader_io_get_unique_index(i);
5201
5202 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5203
5204 for (j = 0; j < length; j++) {
5205 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5206 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5207
5208 ac_build_buffer_store_dword(&ctx->ac,
5209 ctx->esgs_ring,
5210 out_val, 1,
5211 NULL, ctx->es2gs_offset,
5212 (4 * param_index + j) * 4,
5213 1, 1, true, true);
5214 }
5215 }
5216 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5217 }
5218
5219 static void
5220 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5221 {
5222 LLVMValueRef vertex_id = ctx->rel_auto_id;
5223 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5224 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5225 vertex_dw_stride, "");
5226
5227 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5228 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5229 int length = 4;
5230
5231 if (!(ctx->output_mask & (1ull << i)))
5232 continue;
5233
5234 if (i == VARYING_SLOT_CLIP_DIST0)
5235 length = ctx->num_output_clips + ctx->num_output_culls;
5236 int param = shader_io_get_unique_index(i);
5237 mark_tess_output(ctx, false, param);
5238 if (length > 4)
5239 mark_tess_output(ctx, false, param + 1);
5240 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5241 LLVMConstInt(ctx->i32, param * 4, false),
5242 "");
5243 for (unsigned j = 0; j < length; j++) {
5244 lds_store(ctx, dw_addr,
5245 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5246 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5247 }
5248 }
5249 }
5250
5251 struct ac_build_if_state
5252 {
5253 struct nir_to_llvm_context *ctx;
5254 LLVMValueRef condition;
5255 LLVMBasicBlockRef entry_block;
5256 LLVMBasicBlockRef true_block;
5257 LLVMBasicBlockRef false_block;
5258 LLVMBasicBlockRef merge_block;
5259 };
5260
5261 static LLVMBasicBlockRef
5262 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5263 {
5264 LLVMBasicBlockRef current_block;
5265 LLVMBasicBlockRef next_block;
5266 LLVMBasicBlockRef new_block;
5267
5268 /* get current basic block */
5269 current_block = LLVMGetInsertBlock(ctx->builder);
5270
5271 /* chqeck if there's another block after this one */
5272 next_block = LLVMGetNextBasicBlock(current_block);
5273 if (next_block) {
5274 /* insert the new block before the next block */
5275 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5276 }
5277 else {
5278 /* append new block after current block */
5279 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5280 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5281 }
5282 return new_block;
5283 }
5284
5285 static void
5286 ac_nir_build_if(struct ac_build_if_state *ifthen,
5287 struct nir_to_llvm_context *ctx,
5288 LLVMValueRef condition)
5289 {
5290 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5291
5292 memset(ifthen, 0, sizeof *ifthen);
5293 ifthen->ctx = ctx;
5294 ifthen->condition = condition;
5295 ifthen->entry_block = block;
5296
5297 /* create endif/merge basic block for the phi functions */
5298 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5299
5300 /* create/insert true_block before merge_block */
5301 ifthen->true_block =
5302 LLVMInsertBasicBlockInContext(ctx->context,
5303 ifthen->merge_block,
5304 "if-true-block");
5305
5306 /* successive code goes into the true block */
5307 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5308 }
5309
5310 /**
5311 * End a conditional.
5312 */
5313 static void
5314 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5315 {
5316 LLVMBuilderRef builder = ifthen->ctx->builder;
5317
5318 /* Insert branch to the merge block from current block */
5319 LLVMBuildBr(builder, ifthen->merge_block);
5320
5321 /*
5322 * Now patch in the various branch instructions.
5323 */
5324
5325 /* Insert the conditional branch instruction at the end of entry_block */
5326 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5327 if (ifthen->false_block) {
5328 /* we have an else clause */
5329 LLVMBuildCondBr(builder, ifthen->condition,
5330 ifthen->true_block, ifthen->false_block);
5331 }
5332 else {
5333 /* no else clause */
5334 LLVMBuildCondBr(builder, ifthen->condition,
5335 ifthen->true_block, ifthen->merge_block);
5336 }
5337
5338 /* Resume building code at end of the ifthen->merge_block */
5339 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5340 }
5341
5342 static void
5343 write_tess_factors(struct nir_to_llvm_context *ctx)
5344 {
5345 unsigned stride, outer_comps, inner_comps;
5346 struct ac_build_if_state if_ctx, inner_if_ctx;
5347 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5348 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5349 unsigned tess_inner_index, tess_outer_index;
5350 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5351 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5352 int i;
5353 emit_barrier(ctx);
5354
5355 switch (ctx->options->key.tcs.primitive_mode) {
5356 case GL_ISOLINES:
5357 stride = 2;
5358 outer_comps = 2;
5359 inner_comps = 0;
5360 break;
5361 case GL_TRIANGLES:
5362 stride = 4;
5363 outer_comps = 3;
5364 inner_comps = 1;
5365 break;
5366 case GL_QUADS:
5367 stride = 6;
5368 outer_comps = 4;
5369 inner_comps = 2;
5370 break;
5371 default:
5372 return;
5373 }
5374
5375 ac_nir_build_if(&if_ctx, ctx,
5376 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5377 invocation_id, ctx->i32zero, ""));
5378
5379 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5380 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5381
5382 mark_tess_output(ctx, true, tess_inner_index);
5383 mark_tess_output(ctx, true, tess_outer_index);
5384 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5385 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5386 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5387 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5388 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5389
5390 for (i = 0; i < 4; i++) {
5391 inner[i] = LLVMGetUndef(ctx->i32);
5392 outer[i] = LLVMGetUndef(ctx->i32);
5393 }
5394
5395 // LINES reverseal
5396 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5397 outer[0] = out[1] = lds_load(ctx, lds_outer);
5398 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5399 LLVMConstInt(ctx->i32, 1, false), "");
5400 outer[1] = out[0] = lds_load(ctx, lds_outer);
5401 } else {
5402 for (i = 0; i < outer_comps; i++) {
5403 outer[i] = out[i] =
5404 lds_load(ctx, lds_outer);
5405 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5406 LLVMConstInt(ctx->i32, 1, false), "");
5407 }
5408 for (i = 0; i < inner_comps; i++) {
5409 inner[i] = out[outer_comps+i] =
5410 lds_load(ctx, lds_inner);
5411 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5412 LLVMConstInt(ctx->i32, 1, false), "");
5413 }
5414 }
5415
5416 /* Convert the outputs to vectors for stores. */
5417 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5418 vec1 = NULL;
5419
5420 if (stride > 4)
5421 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5422
5423
5424 buffer = ctx->hs_ring_tess_factor;
5425 tf_base = ctx->tess_factor_offset;
5426 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5427 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5428
5429 ac_nir_build_if(&inner_if_ctx, ctx,
5430 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5431 rel_patch_id, ctx->i32zero, ""));
5432
5433 /* Store the dynamic HS control word. */
5434 ac_build_buffer_store_dword(&ctx->ac, buffer,
5435 LLVMConstInt(ctx->i32, 0x80000000, false),
5436 1, ctx->i32zero, tf_base,
5437 0, 1, 0, true, false);
5438 ac_nir_build_endif(&inner_if_ctx);
5439
5440 /* Store the tessellation factors. */
5441 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5442 MIN2(stride, 4), byteoffset, tf_base,
5443 4, 1, 0, true, false);
5444 if (vec1)
5445 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5446 stride - 4, byteoffset, tf_base,
5447 20, 1, 0, true, false);
5448
5449 //TODO store to offchip for TES to read - only if TES reads them
5450 if (1) {
5451 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5452 LLVMValueRef tf_inner_offset;
5453 unsigned param_outer, param_inner;
5454
5455 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5456 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5457 LLVMConstInt(ctx->i32, param_outer, 0));
5458
5459 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5460 util_next_power_of_two(outer_comps));
5461
5462 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5463 outer_comps, tf_outer_offset,
5464 ctx->oc_lds, 0, 1, 0, true, false);
5465 if (inner_comps) {
5466 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5467 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5468 LLVMConstInt(ctx->i32, param_inner, 0));
5469
5470 inner_vec = inner_comps == 1 ? inner[0] :
5471 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5472 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5473 inner_comps, tf_inner_offset,
5474 ctx->oc_lds, 0, 1, 0, true, false);
5475 }
5476 }
5477 ac_nir_build_endif(&if_ctx);
5478 }
5479
5480 static void
5481 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5482 {
5483 write_tess_factors(ctx);
5484 }
5485
5486 static void
5487 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5488 LLVMValueRef *color, unsigned param, bool is_last)
5489 {
5490
5491 struct ac_export_args args;
5492
5493 /* Export */
5494 si_llvm_init_export_args(ctx, color, param,
5495 &args);
5496
5497 if (is_last) {
5498 args.valid_mask = 1; /* whether the EXEC mask is valid */
5499 args.done = 1; /* DONE bit */
5500 } else if (!args.enabled_channels)
5501 return; /* unnecessary NULL export */
5502
5503 ac_build_export(&ctx->ac, &args);
5504 }
5505
5506 static void
5507 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5508 LLVMValueRef depth, LLVMValueRef stencil,
5509 LLVMValueRef samplemask)
5510 {
5511 struct ac_export_args args;
5512
5513 args.enabled_channels = 0;
5514 args.valid_mask = 1;
5515 args.done = 1;
5516 args.target = V_008DFC_SQ_EXP_MRTZ;
5517 args.compr = false;
5518
5519 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5520 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5521 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5522 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5523
5524 if (depth) {
5525 args.out[0] = depth;
5526 args.enabled_channels |= 0x1;
5527 }
5528
5529 if (stencil) {
5530 args.out[1] = stencil;
5531 args.enabled_channels |= 0x2;
5532 }
5533
5534 if (samplemask) {
5535 args.out[2] = samplemask;
5536 args.enabled_channels |= 0x4;
5537 }
5538
5539 /* SI (except OLAND) has a bug that it only looks
5540 * at the X writemask component. */
5541 if (ctx->options->chip_class == SI &&
5542 ctx->options->family != CHIP_OLAND)
5543 args.enabled_channels |= 0x1;
5544
5545 ac_build_export(&ctx->ac, &args);
5546 }
5547
5548 static void
5549 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5550 {
5551 unsigned index = 0;
5552 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5553
5554 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5555 LLVMValueRef values[4];
5556
5557 if (!(ctx->output_mask & (1ull << i)))
5558 continue;
5559
5560 if (i == FRAG_RESULT_DEPTH) {
5561 ctx->shader_info->fs.writes_z = true;
5562 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5563 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5564 } else if (i == FRAG_RESULT_STENCIL) {
5565 ctx->shader_info->fs.writes_stencil = true;
5566 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5567 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5568 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5569 ctx->shader_info->fs.writes_sample_mask = true;
5570 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5571 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5572 } else {
5573 bool last = false;
5574 for (unsigned j = 0; j < 4; j++)
5575 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5576 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5577
5578 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5579 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5580
5581 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
5582 index++;
5583 }
5584 }
5585
5586 if (depth || stencil || samplemask)
5587 si_export_mrt_z(ctx, depth, stencil, samplemask);
5588 else if (!index)
5589 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
5590
5591 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5592 }
5593
5594 static void
5595 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5596 {
5597 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5598 }
5599
5600 static void
5601 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5602 {
5603 switch (ctx->stage) {
5604 case MESA_SHADER_VERTEX:
5605 if (ctx->options->key.vs.as_ls)
5606 handle_ls_outputs_post(ctx);
5607 else if (ctx->options->key.vs.as_es)
5608 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5609 else
5610 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5611 break;
5612 case MESA_SHADER_FRAGMENT:
5613 handle_fs_outputs_post(ctx);
5614 break;
5615 case MESA_SHADER_GEOMETRY:
5616 emit_gs_epilogue(ctx);
5617 break;
5618 case MESA_SHADER_TESS_CTRL:
5619 handle_tcs_outputs_post(ctx);
5620 break;
5621 case MESA_SHADER_TESS_EVAL:
5622 if (ctx->options->key.tes.as_es)
5623 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5624 else
5625 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5626 break;
5627 default:
5628 break;
5629 }
5630 }
5631
5632 static void
5633 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5634 struct nir_variable *variable, uint32_t *offset, int idx)
5635 {
5636 unsigned size = glsl_count_attribute_slots(variable->type, false);
5637 variable->data.driver_location = *offset;
5638 *offset += size;
5639 }
5640
5641 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5642 {
5643 LLVMPassManagerRef passmgr;
5644 /* Create the pass manager */
5645 passmgr = LLVMCreateFunctionPassManagerForModule(
5646 ctx->module);
5647
5648 /* This pass should eliminate all the load and store instructions */
5649 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5650
5651 /* Add some optimization passes */
5652 LLVMAddScalarReplAggregatesPass(passmgr);
5653 LLVMAddLICMPass(passmgr);
5654 LLVMAddAggressiveDCEPass(passmgr);
5655 LLVMAddCFGSimplificationPass(passmgr);
5656 LLVMAddInstructionCombiningPass(passmgr);
5657
5658 /* Run the pass */
5659 LLVMInitializeFunctionPassManager(passmgr);
5660 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5661 LLVMFinalizeFunctionPassManager(passmgr);
5662
5663 LLVMDisposeBuilder(ctx->builder);
5664 LLVMDisposePassManager(passmgr);
5665 }
5666
5667 static void
5668 ac_setup_rings(struct nir_to_llvm_context *ctx)
5669 {
5670 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5671 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5672 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5673 }
5674
5675 if (ctx->is_gs_copy_shader) {
5676 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5677 }
5678 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5679 LLVMValueRef tmp;
5680 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5681 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5682
5683 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5684
5685 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5686 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5687 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5688 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5689
5690 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5691 }
5692
5693 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5694 ctx->stage == MESA_SHADER_TESS_EVAL) {
5695 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5696 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5697 }
5698 }
5699
5700 static
5701 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5702 struct nir_shader *nir,
5703 struct ac_shader_variant_info *shader_info,
5704 const struct ac_nir_compiler_options *options)
5705 {
5706 struct nir_to_llvm_context ctx = {0};
5707 struct nir_function *func;
5708 unsigned i;
5709 ctx.options = options;
5710 ctx.shader_info = shader_info;
5711 ctx.context = LLVMContextCreate();
5712 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5713
5714 ac_llvm_context_init(&ctx.ac, ctx.context);
5715 ctx.ac.module = ctx.module;
5716
5717 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5718
5719 memset(shader_info, 0, sizeof(*shader_info));
5720
5721 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5722
5723 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5724
5725 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5726 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5727 LLVMSetDataLayout(ctx.module, data_layout_str);
5728 LLVMDisposeTargetData(data_layout);
5729 LLVMDisposeMessage(data_layout_str);
5730
5731 setup_types(&ctx);
5732
5733 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5734 ctx.ac.builder = ctx.builder;
5735 ctx.stage = nir->stage;
5736
5737 for (i = 0; i < AC_UD_MAX_SETS; i++)
5738 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5739 for (i = 0; i < AC_UD_MAX_UD; i++)
5740 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5741
5742 create_function(&ctx);
5743
5744 if (nir->stage == MESA_SHADER_COMPUTE) {
5745 int num_shared = 0;
5746 nir_foreach_variable(variable, &nir->shared)
5747 num_shared++;
5748 if (num_shared) {
5749 int idx = 0;
5750 uint32_t shared_size = 0;
5751 LLVMValueRef var;
5752 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5753 nir_foreach_variable(variable, &nir->shared) {
5754 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5755 idx++;
5756 }
5757
5758 shared_size *= 16;
5759 var = LLVMAddGlobalInAddressSpace(ctx.module,
5760 LLVMArrayType(ctx.i8, shared_size),
5761 "compute_lds",
5762 LOCAL_ADDR_SPACE);
5763 LLVMSetAlignment(var, 4);
5764 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5765 }
5766 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5767 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5768
5769 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
5770 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5771 ctx.tes_primitive_mode = nir->info->tess.primitive_mode;
5772 }
5773
5774 ac_setup_rings(&ctx);
5775
5776 nir_foreach_variable(variable, &nir->inputs)
5777 handle_shader_input_decl(&ctx, variable);
5778
5779 if (nir->stage == MESA_SHADER_FRAGMENT)
5780 handle_fs_inputs_pre(&ctx, nir);
5781
5782 ctx.num_output_clips = nir->info->clip_distance_array_size;
5783 ctx.num_output_culls = nir->info->cull_distance_array_size;
5784
5785 nir_foreach_variable(variable, &nir->outputs)
5786 handle_shader_output_decl(&ctx, variable);
5787
5788 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5789 _mesa_key_pointer_equal);
5790 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5791 _mesa_key_pointer_equal);
5792
5793 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5794
5795 setup_locals(&ctx, func);
5796
5797 visit_cf_list(&ctx, &func->impl->body);
5798 phi_post_pass(&ctx);
5799
5800 handle_shader_outputs_post(&ctx);
5801 LLVMBuildRetVoid(ctx.builder);
5802
5803 ac_llvm_finalize_module(&ctx);
5804 free(ctx.locals);
5805 ralloc_free(ctx.defs);
5806 ralloc_free(ctx.phis);
5807
5808 if (nir->stage == MESA_SHADER_GEOMETRY) {
5809 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5810 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
5811 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5812 nir->info->gs.vertices_out;
5813 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
5814 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
5815 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
5816 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
5817 shader_info->vs.outputs_written = ctx.tess_outputs_written;
5818 }
5819
5820 return ctx.module;
5821 }
5822
5823 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5824 {
5825 unsigned *retval = (unsigned *)context;
5826 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5827 char *description = LLVMGetDiagInfoDescription(di);
5828
5829 if (severity == LLVMDSError) {
5830 *retval = 1;
5831 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5832 description);
5833 }
5834
5835 LLVMDisposeMessage(description);
5836 }
5837
5838 static unsigned ac_llvm_compile(LLVMModuleRef M,
5839 struct ac_shader_binary *binary,
5840 LLVMTargetMachineRef tm)
5841 {
5842 unsigned retval = 0;
5843 char *err;
5844 LLVMContextRef llvm_ctx;
5845 LLVMMemoryBufferRef out_buffer;
5846 unsigned buffer_size;
5847 const char *buffer_data;
5848 LLVMBool mem_err;
5849
5850 /* Setup Diagnostic Handler*/
5851 llvm_ctx = LLVMGetModuleContext(M);
5852
5853 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5854 &retval);
5855
5856 /* Compile IR*/
5857 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5858 &err, &out_buffer);
5859
5860 /* Process Errors/Warnings */
5861 if (mem_err) {
5862 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5863 free(err);
5864 retval = 1;
5865 goto out;
5866 }
5867
5868 /* Extract Shader Code*/
5869 buffer_size = LLVMGetBufferSize(out_buffer);
5870 buffer_data = LLVMGetBufferStart(out_buffer);
5871
5872 ac_elf_read(buffer_data, buffer_size, binary);
5873
5874 /* Clean up */
5875 LLVMDisposeMemoryBuffer(out_buffer);
5876
5877 out:
5878 return retval;
5879 }
5880
5881 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5882 LLVMModuleRef llvm_module,
5883 struct ac_shader_binary *binary,
5884 struct ac_shader_config *config,
5885 struct ac_shader_variant_info *shader_info,
5886 gl_shader_stage stage,
5887 bool dump_shader, bool supports_spill)
5888 {
5889 if (dump_shader)
5890 ac_dump_module(llvm_module);
5891
5892 memset(binary, 0, sizeof(*binary));
5893 int v = ac_llvm_compile(llvm_module, binary, tm);
5894 if (v) {
5895 fprintf(stderr, "compile failed\n");
5896 }
5897
5898 if (dump_shader)
5899 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5900
5901 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5902
5903 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5904 LLVMDisposeModule(llvm_module);
5905 LLVMContextDispose(ctx);
5906
5907 if (stage == MESA_SHADER_FRAGMENT) {
5908 shader_info->num_input_vgprs = 0;
5909 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5910 shader_info->num_input_vgprs += 2;
5911 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5912 shader_info->num_input_vgprs += 2;
5913 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5914 shader_info->num_input_vgprs += 2;
5915 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5916 shader_info->num_input_vgprs += 3;
5917 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5918 shader_info->num_input_vgprs += 2;
5919 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5920 shader_info->num_input_vgprs += 2;
5921 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5922 shader_info->num_input_vgprs += 2;
5923 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5924 shader_info->num_input_vgprs += 1;
5925 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5926 shader_info->num_input_vgprs += 1;
5927 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5928 shader_info->num_input_vgprs += 1;
5929 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5930 shader_info->num_input_vgprs += 1;
5931 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5932 shader_info->num_input_vgprs += 1;
5933 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5934 shader_info->num_input_vgprs += 1;
5935 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5936 shader_info->num_input_vgprs += 1;
5937 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5938 shader_info->num_input_vgprs += 1;
5939 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5940 shader_info->num_input_vgprs += 1;
5941 }
5942 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5943
5944 /* +3 for scratch wave offset and VCC */
5945 config->num_sgprs = MAX2(config->num_sgprs,
5946 shader_info->num_input_sgprs + 3);
5947 }
5948
5949 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5950 struct ac_shader_binary *binary,
5951 struct ac_shader_config *config,
5952 struct ac_shader_variant_info *shader_info,
5953 struct nir_shader *nir,
5954 const struct ac_nir_compiler_options *options,
5955 bool dump_shader)
5956 {
5957
5958 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5959 options);
5960
5961 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5962 switch (nir->stage) {
5963 case MESA_SHADER_COMPUTE:
5964 for (int i = 0; i < 3; ++i)
5965 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5966 break;
5967 case MESA_SHADER_FRAGMENT:
5968 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5969 break;
5970 case MESA_SHADER_GEOMETRY:
5971 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5972 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5973 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5974 shader_info->gs.invocations = nir->info->gs.invocations;
5975 break;
5976 case MESA_SHADER_TESS_EVAL:
5977 shader_info->tes.primitive_mode = nir->info->tess.primitive_mode;
5978 shader_info->tes.spacing = nir->info->tess.spacing;
5979 shader_info->tes.ccw = nir->info->tess.ccw;
5980 shader_info->tes.point_mode = nir->info->tess.point_mode;
5981 shader_info->tes.as_es = options->key.tes.as_es;
5982 break;
5983 case MESA_SHADER_TESS_CTRL:
5984 shader_info->tcs.tcs_vertices_out = nir->info->tess.tcs_vertices_out;
5985 break;
5986 case MESA_SHADER_VERTEX:
5987 shader_info->vs.as_es = options->key.vs.as_es;
5988 shader_info->vs.as_ls = options->key.vs.as_ls;
5989 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
5990 if (options->key.vs.as_ls)
5991 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
5992 break;
5993 default:
5994 break;
5995 }
5996 }
5997
5998 static void
5999 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6000 {
6001 LLVMValueRef args[9];
6002 args[0] = ctx->gsvs_ring;
6003 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6004 args[3] = ctx->i32zero;
6005 args[4] = ctx->i32one; /* OFFEN */
6006 args[5] = ctx->i32zero; /* IDXEN */
6007 args[6] = ctx->i32one; /* GLC */
6008 args[7] = ctx->i32one; /* SLC */
6009 args[8] = ctx->i32zero; /* TFE */
6010
6011 int idx = 0;
6012
6013 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6014 int length = 4;
6015 int slot = idx;
6016 int slot_inc = 1;
6017 if (!(ctx->output_mask & (1ull << i)))
6018 continue;
6019
6020 if (i == VARYING_SLOT_CLIP_DIST0) {
6021 /* unpack clip and cull from a single set of slots */
6022 length = ctx->num_output_clips + ctx->num_output_culls;
6023 if (length > 4)
6024 slot_inc = 2;
6025 }
6026
6027 for (unsigned j = 0; j < length; j++) {
6028 LLVMValueRef value;
6029 args[2] = LLVMConstInt(ctx->i32,
6030 (slot * 4 + j) *
6031 ctx->gs_max_out_vertices * 16 * 4, false);
6032
6033 value = ac_build_intrinsic(&ctx->ac,
6034 "llvm.SI.buffer.load.dword.i32.i32",
6035 ctx->i32, args, 9,
6036 AC_FUNC_ATTR_READONLY |
6037 AC_FUNC_ATTR_LEGACY);
6038
6039 LLVMBuildStore(ctx->builder,
6040 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6041 }
6042 idx += slot_inc;
6043 }
6044 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6045 }
6046
6047 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6048 struct nir_shader *geom_shader,
6049 struct ac_shader_binary *binary,
6050 struct ac_shader_config *config,
6051 struct ac_shader_variant_info *shader_info,
6052 const struct ac_nir_compiler_options *options,
6053 bool dump_shader)
6054 {
6055 struct nir_to_llvm_context ctx = {0};
6056 ctx.context = LLVMContextCreate();
6057 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6058 ctx.options = options;
6059 ctx.shader_info = shader_info;
6060
6061 ac_llvm_context_init(&ctx.ac, ctx.context);
6062 ctx.ac.module = ctx.module;
6063
6064 ctx.is_gs_copy_shader = true;
6065 LLVMSetTarget(ctx.module, "amdgcn--");
6066 setup_types(&ctx);
6067
6068 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6069 ctx.ac.builder = ctx.builder;
6070 ctx.stage = MESA_SHADER_VERTEX;
6071
6072 create_function(&ctx);
6073
6074 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
6075 ac_setup_rings(&ctx);
6076
6077 ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
6078 ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
6079
6080 nir_foreach_variable(variable, &geom_shader->outputs)
6081 handle_shader_output_decl(&ctx, variable);
6082
6083 ac_gs_copy_shader_emit(&ctx);
6084
6085 LLVMBuildRetVoid(ctx.builder);
6086
6087 ac_llvm_finalize_module(&ctx);
6088
6089 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6090 MESA_SHADER_VERTEX,
6091 dump_shader, options->supports_spill);
6092 }