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radv/ac: move needs_push_constants to shader info.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83 LLVMValueRef ls_out_layout;
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef tcs_offchip_layout;
87 LLVMValueRef tcs_out_offsets;
88 LLVMValueRef tcs_out_layout;
89 LLVMValueRef tcs_in_layout;
90 LLVMValueRef oc_lds;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tcs_patch_id;
93 LLVMValueRef tcs_rel_ids;
94 LLVMValueRef tes_rel_patch_id;
95 LLVMValueRef tes_patch_id;
96 LLVMValueRef tes_u;
97 LLVMValueRef tes_v;
98
99 LLVMValueRef gsvs_ring_stride;
100 LLVMValueRef gsvs_num_entries;
101 LLVMValueRef gs2vs_offset;
102 LLVMValueRef gs_wave_id;
103 LLVMValueRef gs_vtx_offset[6];
104 LLVMValueRef gs_prim_id, gs_invocation_id;
105
106 LLVMValueRef esgs_ring;
107 LLVMValueRef gsvs_ring;
108 LLVMValueRef hs_ring_tess_offchip;
109 LLVMValueRef hs_ring_tess_factor;
110
111 LLVMValueRef prim_mask;
112 LLVMValueRef sample_pos_offset;
113 LLVMValueRef persp_sample, persp_center, persp_centroid;
114 LLVMValueRef linear_sample, linear_center, linear_centroid;
115 LLVMValueRef front_face;
116 LLVMValueRef ancillary;
117 LLVMValueRef sample_coverage;
118 LLVMValueRef frag_pos[4];
119
120 LLVMBasicBlockRef continue_block;
121 LLVMBasicBlockRef break_block;
122
123 LLVMTypeRef i1;
124 LLVMTypeRef i8;
125 LLVMTypeRef i16;
126 LLVMTypeRef i32;
127 LLVMTypeRef i64;
128 LLVMTypeRef v2i32;
129 LLVMTypeRef v3i32;
130 LLVMTypeRef v4i32;
131 LLVMTypeRef v8i32;
132 LLVMTypeRef f64;
133 LLVMTypeRef f32;
134 LLVMTypeRef f16;
135 LLVMTypeRef v2f32;
136 LLVMTypeRef v4f32;
137 LLVMTypeRef v16i8;
138 LLVMTypeRef voidt;
139
140 LLVMValueRef i1true;
141 LLVMValueRef i1false;
142 LLVMValueRef i32zero;
143 LLVMValueRef i32one;
144 LLVMValueRef f32zero;
145 LLVMValueRef f32one;
146 LLVMValueRef v4f32empty;
147
148 unsigned uniform_md_kind;
149 LLVMValueRef empty_md;
150 gl_shader_stage stage;
151
152 LLVMValueRef lds;
153 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
154 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
155
156 LLVMValueRef shared_memory;
157 uint64_t input_mask;
158 uint64_t output_mask;
159 int num_locals;
160 LLVMValueRef *locals;
161 bool has_ddxy;
162 uint8_t num_output_clips;
163 uint8_t num_output_culls;
164
165 bool has_ds_bpermute;
166
167 bool is_gs_copy_shader;
168 LLVMValueRef gs_next_vertex;
169 unsigned gs_max_out_vertices;
170
171 unsigned tes_primitive_mode;
172 uint64_t tess_outputs_written;
173 uint64_t tess_patch_outputs_written;
174 };
175
176 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
177 nir_deref_var *deref,
178 enum desc_type desc_type);
179 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
180 {
181 return (index * 4) + chan;
182 }
183
184 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
185 {
186 /* handle patch indices separate */
187 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
188 return 0;
189 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
190 return 1;
191 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
192 return 2 + (slot - VARYING_SLOT_PATCH0);
193
194 if (slot == VARYING_SLOT_POS)
195 return 0;
196 if (slot == VARYING_SLOT_PSIZ)
197 return 1;
198 if (slot == VARYING_SLOT_CLIP_DIST0)
199 return 2;
200 /* 3 is reserved for clip dist as well */
201 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
202 return 4 + (slot - VARYING_SLOT_VAR0);
203 unreachable("illegal slot in get unique index\n");
204 }
205
206 static unsigned llvm_get_type_size(LLVMTypeRef type)
207 {
208 LLVMTypeKind kind = LLVMGetTypeKind(type);
209
210 switch (kind) {
211 case LLVMIntegerTypeKind:
212 return LLVMGetIntTypeWidth(type) / 8;
213 case LLVMFloatTypeKind:
214 return 4;
215 case LLVMPointerTypeKind:
216 return 8;
217 case LLVMVectorTypeKind:
218 return LLVMGetVectorSize(type) *
219 llvm_get_type_size(LLVMGetElementType(type));
220 default:
221 assert(0);
222 return 0;
223 }
224 }
225
226 static void set_llvm_calling_convention(LLVMValueRef func,
227 gl_shader_stage stage)
228 {
229 enum radeon_llvm_calling_convention calling_conv;
230
231 switch (stage) {
232 case MESA_SHADER_VERTEX:
233 case MESA_SHADER_TESS_CTRL:
234 case MESA_SHADER_TESS_EVAL:
235 calling_conv = RADEON_LLVM_AMDGPU_VS;
236 break;
237 case MESA_SHADER_GEOMETRY:
238 calling_conv = RADEON_LLVM_AMDGPU_GS;
239 break;
240 case MESA_SHADER_FRAGMENT:
241 calling_conv = RADEON_LLVM_AMDGPU_PS;
242 break;
243 case MESA_SHADER_COMPUTE:
244 calling_conv = RADEON_LLVM_AMDGPU_CS;
245 break;
246 default:
247 unreachable("Unhandle shader type");
248 }
249
250 LLVMSetFunctionCallConv(func, calling_conv);
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems, LLVMTypeRef *param_types,
257 unsigned param_count, unsigned array_params_mask,
258 unsigned sgpr_params, bool unsafe_math)
259 {
260 LLVMTypeRef main_function_type, ret_type;
261 LLVMBasicBlockRef main_function_body;
262
263 if (num_return_elems)
264 ret_type = LLVMStructTypeInContext(ctx, return_types,
265 num_return_elems, true);
266 else
267 ret_type = LLVMVoidTypeInContext(ctx);
268
269 /* Setup the function */
270 main_function_type =
271 LLVMFunctionType(ret_type, param_types, param_count, 0);
272 LLVMValueRef main_function =
273 LLVMAddFunction(module, "main", main_function_type);
274 main_function_body =
275 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
276 LLVMPositionBuilderAtEnd(builder, main_function_body);
277
278 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
279 for (unsigned i = 0; i < sgpr_params; ++i) {
280 if (array_params_mask & (1 << i)) {
281 LLVMValueRef P = LLVMGetParam(main_function, i);
282 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
283 ac_add_attr_dereferenceable(P, UINT64_MAX);
284 }
285 else {
286 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
287 }
288 }
289
290 if (unsafe_math) {
291 /* These were copied from some LLVM test. */
292 LLVMAddTargetDependentFunctionAttr(main_function,
293 "less-precise-fpmad",
294 "true");
295 LLVMAddTargetDependentFunctionAttr(main_function,
296 "no-infs-fp-math",
297 "true");
298 LLVMAddTargetDependentFunctionAttr(main_function,
299 "no-nans-fp-math",
300 "true");
301 LLVMAddTargetDependentFunctionAttr(main_function,
302 "unsafe-fp-math",
303 "true");
304 }
305 return main_function;
306 }
307
308 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
309 {
310 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
311 CONST_ADDR_SPACE);
312 }
313
314 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
315 int idx,
316 LLVMTypeRef type)
317 {
318 LLVMValueRef offset;
319 LLVMValueRef ptr;
320 int addr_space;
321
322 offset = LLVMConstInt(ctx->i32, idx * 16, false);
323
324 ptr = ctx->shared_memory;
325 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
326 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
327 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
328 return ptr;
329 }
330
331 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
332 {
333 if (t == ctx->f16 || t == ctx->i16)
334 return ctx->i16;
335 else if (t == ctx->f32 || t == ctx->i32)
336 return ctx->i32;
337 else if (t == ctx->f64 || t == ctx->i64)
338 return ctx->i64;
339 else
340 unreachable("Unhandled integer size");
341 }
342
343 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
344 {
345 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
346 LLVMTypeRef elem_type = LLVMGetElementType(t);
347 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
348 LLVMGetVectorSize(t));
349 }
350 return to_integer_type_scalar(ctx, t);
351 }
352
353 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
354 {
355 LLVMTypeRef type = LLVMTypeOf(v);
356 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
357 }
358
359 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
360 {
361 if (t == ctx->i16 || t == ctx->f16)
362 return ctx->f16;
363 else if (t == ctx->i32 || t == ctx->f32)
364 return ctx->f32;
365 else if (t == ctx->i64 || t == ctx->f64)
366 return ctx->f64;
367 else
368 unreachable("Unhandled float size");
369 }
370
371 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
372 {
373 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
374 LLVMTypeRef elem_type = LLVMGetElementType(t);
375 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
376 LLVMGetVectorSize(t));
377 }
378 return to_float_type_scalar(ctx, t);
379 }
380
381 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
382 {
383 LLVMTypeRef type = LLVMTypeOf(v);
384 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
385 }
386
387 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
388 {
389 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
390 type = LLVMGetElementType(type);
391
392 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
393 return LLVMGetIntTypeWidth(type);
394
395 if (type == ctx->f16)
396 return 16;
397 if (type == ctx->f32)
398 return 32;
399 if (type == ctx->f64)
400 return 64;
401
402 unreachable("Unhandled type kind in get_elem_bits");
403 }
404
405 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
406 LLVMValueRef param, unsigned rshift,
407 unsigned bitwidth)
408 {
409 LLVMValueRef value = param;
410 if (rshift)
411 value = LLVMBuildLShr(ctx->builder, value,
412 LLVMConstInt(ctx->i32, rshift, false), "");
413
414 if (rshift + bitwidth < 32) {
415 unsigned mask = (1 << bitwidth) - 1;
416 value = LLVMBuildAnd(ctx->builder, value,
417 LLVMConstInt(ctx->i32, mask, false), "");
418 }
419 return value;
420 }
421
422 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
423 {
424 switch (ctx->stage) {
425 case MESA_SHADER_TESS_CTRL:
426 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
427 case MESA_SHADER_TESS_EVAL:
428 return ctx->tes_rel_patch_id;
429 break;
430 default:
431 unreachable("Illegal stage");
432 }
433 }
434
435 /* Tessellation shaders pass outputs to the next shader using LDS.
436 *
437 * LS outputs = TCS inputs
438 * TCS outputs = TES inputs
439 *
440 * The LDS layout is:
441 * - TCS inputs for patch 0
442 * - TCS inputs for patch 1
443 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
444 * - ...
445 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
446 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
447 * - TCS outputs for patch 1
448 * - Per-patch TCS outputs for patch 1
449 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
450 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
451 * - ...
452 *
453 * All three shaders VS(LS), TCS, TES share the same LDS space.
454 */
455 static LLVMValueRef
456 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
457 {
458 if (ctx->stage == MESA_SHADER_VERTEX)
459 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
460 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
461 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
462 else {
463 assert(0);
464 return NULL;
465 }
466 }
467
468 static LLVMValueRef
469 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
470 {
471 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
472 }
473
474 static LLVMValueRef
475 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
476 {
477 return LLVMBuildMul(ctx->builder,
478 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
479 LLVMConstInt(ctx->i32, 4, false), "");
480 }
481
482 static LLVMValueRef
483 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
484 {
485 return LLVMBuildMul(ctx->builder,
486 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
487 LLVMConstInt(ctx->i32, 4, false), "");
488 }
489
490 static LLVMValueRef
491 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
492 {
493 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
494 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
495
496 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
497 }
498
499 static LLVMValueRef
500 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
501 {
502 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
503 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
504 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
505
506 return LLVMBuildAdd(ctx->builder, patch0_offset,
507 LLVMBuildMul(ctx->builder, patch_stride,
508 rel_patch_id, ""),
509 "");
510 }
511
512 static LLVMValueRef
513 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
514 {
515 LLVMValueRef patch0_patch_data_offset =
516 get_tcs_out_patch0_patch_data_offset(ctx);
517 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
518 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
519
520 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
521 LLVMBuildMul(ctx->builder, patch_stride,
522 rel_patch_id, ""),
523 "");
524 }
525
526 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
527 {
528 ud_info->sgpr_idx = sgpr_idx;
529 ud_info->num_sgprs = num_sgprs;
530 ud_info->indirect = false;
531 ud_info->indirect_offset = 0;
532 }
533
534 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
535 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
536 {
537 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
538 }
539
540 #if 0
541 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
542 uint32_t indirect_offset)
543 {
544 ud_info->sgpr_idx = sgpr_idx;
545 ud_info->num_sgprs = num_sgprs;
546 ud_info->indirect = true;
547 ud_info->indirect_offset = indirect_offset;
548 }
549 #endif
550
551 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
552 {
553 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
554 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
555 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
556 "tess_lds");
557 }
558
559 static void create_function(struct nir_to_llvm_context *ctx)
560 {
561 LLVMTypeRef arg_types[23];
562 unsigned arg_idx = 0;
563 unsigned array_params_mask = 0;
564 unsigned sgpr_count = 0, user_sgpr_count;
565 unsigned i;
566 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
567 unsigned user_sgpr_idx;
568 bool need_ring_offsets = false;
569
570 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
571 if (ctx->stage == MESA_SHADER_GEOMETRY ||
572 ctx->stage == MESA_SHADER_VERTEX ||
573 ctx->stage == MESA_SHADER_TESS_CTRL ||
574 ctx->stage == MESA_SHADER_TESS_EVAL ||
575 ctx->stage == MESA_SHADER_FRAGMENT ||
576 ctx->is_gs_copy_shader)
577 need_ring_offsets = true;
578
579 if (need_ring_offsets && !ctx->options->supports_spill) {
580 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address of rings */
581 }
582
583 /* 1 for each descriptor set */
584 for (unsigned i = 0; i < num_sets; ++i) {
585 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
586 array_params_mask |= (1 << arg_idx);
587 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
588 }
589 }
590
591 if (ctx->shader_info->info.needs_push_constants) {
592 /* 1 for push constants and dynamic descriptors */
593 array_params_mask |= (1 << arg_idx);
594 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
595 }
596
597 switch (ctx->stage) {
598 case MESA_SHADER_COMPUTE:
599 if (ctx->shader_info->info.cs.grid_components_used)
600 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used); /* grid size */
601 user_sgpr_count = arg_idx;
602 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
603 arg_types[arg_idx++] = ctx->i32;
604 sgpr_count = arg_idx;
605
606 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
607 break;
608 case MESA_SHADER_VERTEX:
609 if (!ctx->is_gs_copy_shader) {
610 if (ctx->shader_info->info.vs.has_vertex_buffers)
611 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
612 arg_types[arg_idx++] = ctx->i32; // base vertex
613 arg_types[arg_idx++] = ctx->i32; // start instance
614 if (ctx->shader_info->info.vs.needs_draw_id)
615 arg_types[arg_idx++] = ctx->i32; // draw index
616 }
617 user_sgpr_count = arg_idx;
618 if (ctx->options->key.vs.as_es)
619 arg_types[arg_idx++] = ctx->i32; //es2gs offset
620 else if (ctx->options->key.vs.as_ls) {
621 arg_types[arg_idx++] = ctx->i32; //ls out layout
622 user_sgpr_count++;
623 }
624 sgpr_count = arg_idx;
625 arg_types[arg_idx++] = ctx->i32; // vertex id
626 if (!ctx->is_gs_copy_shader) {
627 arg_types[arg_idx++] = ctx->i32; // rel auto id
628 arg_types[arg_idx++] = ctx->i32; // vs prim id
629 arg_types[arg_idx++] = ctx->i32; // instance id
630 }
631 break;
632 case MESA_SHADER_TESS_CTRL:
633 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
634 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
635 arg_types[arg_idx++] = ctx->i32; // tcs out layout
636 arg_types[arg_idx++] = ctx->i32; // tcs in layout
637 user_sgpr_count = arg_idx;
638 arg_types[arg_idx++] = ctx->i32; // param oc lds
639 arg_types[arg_idx++] = ctx->i32; // tess factor offset
640 sgpr_count = arg_idx;
641 arg_types[arg_idx++] = ctx->i32; // patch id
642 arg_types[arg_idx++] = ctx->i32; // rel ids;
643 break;
644 case MESA_SHADER_TESS_EVAL:
645 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
646 user_sgpr_count = arg_idx;
647 if (ctx->options->key.tes.as_es) {
648 arg_types[arg_idx++] = ctx->i32; // OC LDS
649 arg_types[arg_idx++] = ctx->i32; //
650 arg_types[arg_idx++] = ctx->i32; // es2gs offset
651 } else {
652 arg_types[arg_idx++] = ctx->i32; //
653 arg_types[arg_idx++] = ctx->i32; // OC LDS
654 }
655 sgpr_count = arg_idx;
656 arg_types[arg_idx++] = ctx->f32; // tes_u
657 arg_types[arg_idx++] = ctx->f32; // tes_v
658 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
659 arg_types[arg_idx++] = ctx->i32; // tes patch id
660 break;
661 case MESA_SHADER_GEOMETRY:
662 arg_types[arg_idx++] = ctx->i32; // gsvs stride
663 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
664 user_sgpr_count = arg_idx;
665 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
666 arg_types[arg_idx++] = ctx->i32; // wave id
667 sgpr_count = arg_idx;
668 arg_types[arg_idx++] = ctx->i32; // vtx0
669 arg_types[arg_idx++] = ctx->i32; // vtx1
670 arg_types[arg_idx++] = ctx->i32; // prim id
671 arg_types[arg_idx++] = ctx->i32; // vtx2
672 arg_types[arg_idx++] = ctx->i32; // vtx3
673 arg_types[arg_idx++] = ctx->i32; // vtx4
674 arg_types[arg_idx++] = ctx->i32; // vtx5
675 arg_types[arg_idx++] = ctx->i32; // GS instance id
676 break;
677 case MESA_SHADER_FRAGMENT:
678 if (ctx->shader_info->info.ps.needs_sample_positions)
679 arg_types[arg_idx++] = ctx->i32; /* sample position offset */
680 user_sgpr_count = arg_idx;
681 arg_types[arg_idx++] = ctx->i32; /* prim mask */
682 sgpr_count = arg_idx;
683 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
684 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
685 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
686 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
687 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
688 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
689 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
690 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
691 arg_types[arg_idx++] = ctx->f32; /* pos x float */
692 arg_types[arg_idx++] = ctx->f32; /* pos y float */
693 arg_types[arg_idx++] = ctx->f32; /* pos z float */
694 arg_types[arg_idx++] = ctx->f32; /* pos w float */
695 arg_types[arg_idx++] = ctx->i32; /* front face */
696 arg_types[arg_idx++] = ctx->i32; /* ancillary */
697 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
698 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
699 break;
700 default:
701 unreachable("Shader stage not implemented");
702 }
703
704 ctx->main_function = create_llvm_function(
705 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
706 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
707 set_llvm_calling_convention(ctx->main_function, ctx->stage);
708
709 ctx->shader_info->num_input_sgprs = 0;
710 ctx->shader_info->num_input_vgprs = 0;
711
712 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
713 for (i = 0; i < user_sgpr_count; i++)
714 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
715
716 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
717 for (; i < sgpr_count; i++)
718 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
719
720 if (ctx->stage != MESA_SHADER_FRAGMENT)
721 for (; i < arg_idx; ++i)
722 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
723
724 arg_idx = 0;
725 user_sgpr_idx = 0;
726
727 if (ctx->options->supports_spill || need_ring_offsets) {
728 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
729 user_sgpr_idx += 2;
730 if (ctx->options->supports_spill) {
731 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
732 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
733 NULL, 0, AC_FUNC_ATTR_READNONE);
734 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
735 const_array(ctx->v16i8, 16), "");
736 } else
737 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
738 }
739
740 for (unsigned i = 0; i < num_sets; ++i) {
741 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
742 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
743 user_sgpr_idx += 2;
744 ctx->descriptor_sets[i] =
745 LLVMGetParam(ctx->main_function, arg_idx++);
746 } else
747 ctx->descriptor_sets[i] = NULL;
748 }
749
750 if (ctx->shader_info->info.needs_push_constants) {
751 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
752 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
753 user_sgpr_idx += 2;
754 }
755
756 switch (ctx->stage) {
757 case MESA_SHADER_COMPUTE:
758 if (ctx->shader_info->info.cs.grid_components_used) {
759 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
760 user_sgpr_idx += ctx->shader_info->info.cs.grid_components_used;
761 ctx->num_work_groups =
762 LLVMGetParam(ctx->main_function, arg_idx++);
763 }
764 ctx->workgroup_ids =
765 LLVMGetParam(ctx->main_function, arg_idx++);
766 ctx->tg_size =
767 LLVMGetParam(ctx->main_function, arg_idx++);
768 ctx->local_invocation_ids =
769 LLVMGetParam(ctx->main_function, arg_idx++);
770 break;
771 case MESA_SHADER_VERTEX:
772 if (!ctx->is_gs_copy_shader) {
773 if (ctx->shader_info->info.vs.has_vertex_buffers) {
774 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
775 user_sgpr_idx += 2;
776 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
777 }
778 unsigned vs_num = 2;
779 if (ctx->shader_info->info.vs.needs_draw_id)
780 vs_num++;
781
782 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
783 user_sgpr_idx += vs_num;
784
785 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
786 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
787 if (ctx->shader_info->info.vs.needs_draw_id)
788 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
789 }
790 if (ctx->options->key.vs.as_es)
791 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
792 else if (ctx->options->key.vs.as_ls) {
793 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
794 user_sgpr_idx += 1;
795 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
796 }
797 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
798 if (!ctx->is_gs_copy_shader) {
799 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
800 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
801 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
802 }
803 if (ctx->options->key.vs.as_ls)
804 declare_tess_lds(ctx);
805 break;
806 case MESA_SHADER_TESS_CTRL:
807 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
808 user_sgpr_idx += 4;
809 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
810 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
811 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
812 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
813 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
814 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
815 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
816 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
817
818 declare_tess_lds(ctx);
819 break;
820 case MESA_SHADER_TESS_EVAL:
821 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
822 user_sgpr_idx += 1;
823 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
824 if (ctx->options->key.tes.as_es) {
825 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
826 arg_idx++;
827 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
828 } else {
829 arg_idx++;
830 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
831 }
832 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
833 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
834 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
835 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
836 break;
837 case MESA_SHADER_GEOMETRY:
838 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
839 user_sgpr_idx += 2;
840 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
841 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
842 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
843 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
844 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
845 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
846 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
847 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
848 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
849 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
850 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
851 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
852 break;
853 case MESA_SHADER_FRAGMENT:
854 if (ctx->shader_info->info.ps.needs_sample_positions) {
855 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, user_sgpr_idx, 1);
856 user_sgpr_idx += 1;
857 ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, arg_idx++);
858 }
859 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
860 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
861 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
862 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
863 arg_idx++;
864 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
865 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
866 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
867 arg_idx++; /* line stipple */
868 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
869 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
870 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
871 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
872 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
873 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
874 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
875 break;
876 default:
877 unreachable("Shader stage not implemented");
878 }
879 }
880
881 static void setup_types(struct nir_to_llvm_context *ctx)
882 {
883 LLVMValueRef args[4];
884
885 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
886 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
887 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
888 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
889 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
890 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
891 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
892 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
893 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
894 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
895 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
896 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
897 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
898 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
899 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
900 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
901
902 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
903 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
904 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
905 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
906 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
907 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
908
909 args[0] = ctx->f32zero;
910 args[1] = ctx->f32zero;
911 args[2] = ctx->f32zero;
912 args[3] = ctx->f32one;
913 ctx->v4f32empty = LLVMConstVector(args, 4);
914
915 ctx->uniform_md_kind =
916 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
917 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
918
919 args[0] = LLVMConstReal(ctx->f32, 2.5);
920 }
921
922 static int get_llvm_num_components(LLVMValueRef value)
923 {
924 LLVMTypeRef type = LLVMTypeOf(value);
925 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
926 ? LLVMGetVectorSize(type)
927 : 1;
928 return num_components;
929 }
930
931 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
932 LLVMValueRef value,
933 int index)
934 {
935 int count = get_llvm_num_components(value);
936
937 assert(index < count);
938 if (count == 1)
939 return value;
940
941 return LLVMBuildExtractElement(ctx->builder, value,
942 LLVMConstInt(ctx->i32, index, false), "");
943 }
944
945 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
946 LLVMValueRef value, unsigned count)
947 {
948 unsigned num_components = get_llvm_num_components(value);
949 if (count == num_components)
950 return value;
951
952 LLVMValueRef masks[] = {
953 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
954 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
955
956 if (count == 1)
957 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
958 "");
959
960 LLVMValueRef swizzle = LLVMConstVector(masks, count);
961 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
962 }
963
964 static void
965 build_store_values_extended(struct nir_to_llvm_context *ctx,
966 LLVMValueRef *values,
967 unsigned value_count,
968 unsigned value_stride,
969 LLVMValueRef vec)
970 {
971 LLVMBuilderRef builder = ctx->builder;
972 unsigned i;
973
974 if (value_count == 1) {
975 LLVMBuildStore(builder, vec, values[0]);
976 return;
977 }
978
979 for (i = 0; i < value_count; i++) {
980 LLVMValueRef ptr = values[i * value_stride];
981 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
982 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
983 LLVMBuildStore(builder, value, ptr);
984 }
985 }
986
987 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
988 nir_ssa_def *def)
989 {
990 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
991 if (def->num_components > 1) {
992 type = LLVMVectorType(type, def->num_components);
993 }
994 return type;
995 }
996
997 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
998 {
999 assert(src.is_ssa);
1000 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1001 return (LLVMValueRef)entry->data;
1002 }
1003
1004
1005 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1006 struct nir_block *b)
1007 {
1008 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1009 return (LLVMBasicBlockRef)entry->data;
1010 }
1011
1012 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1013 nir_alu_src src,
1014 unsigned num_components)
1015 {
1016 LLVMValueRef value = get_src(ctx, src.src);
1017 bool need_swizzle = false;
1018
1019 assert(value);
1020 LLVMTypeRef type = LLVMTypeOf(value);
1021 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1022 ? LLVMGetVectorSize(type)
1023 : 1;
1024
1025 for (unsigned i = 0; i < num_components; ++i) {
1026 assert(src.swizzle[i] < src_components);
1027 if (src.swizzle[i] != i)
1028 need_swizzle = true;
1029 }
1030
1031 if (need_swizzle || num_components != src_components) {
1032 LLVMValueRef masks[] = {
1033 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1034 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1035 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1036 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1037
1038 if (src_components > 1 && num_components == 1) {
1039 value = LLVMBuildExtractElement(ctx->builder, value,
1040 masks[0], "");
1041 } else if (src_components == 1 && num_components > 1) {
1042 LLVMValueRef values[] = {value, value, value, value};
1043 value = ac_build_gather_values(&ctx->ac, values, num_components);
1044 } else {
1045 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1046 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1047 swizzle, "");
1048 }
1049 }
1050 assert(!src.negate);
1051 assert(!src.abs);
1052 return value;
1053 }
1054
1055 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1056 LLVMIntPredicate pred, LLVMValueRef src0,
1057 LLVMValueRef src1)
1058 {
1059 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1060 return LLVMBuildSelect(ctx->builder, result,
1061 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1062 LLVMConstInt(ctx->i32, 0, false), "");
1063 }
1064
1065 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1066 LLVMRealPredicate pred, LLVMValueRef src0,
1067 LLVMValueRef src1)
1068 {
1069 LLVMValueRef result;
1070 src0 = to_float(ctx, src0);
1071 src1 = to_float(ctx, src1);
1072 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1073 return LLVMBuildSelect(ctx->builder, result,
1074 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1075 LLVMConstInt(ctx->i32, 0, false), "");
1076 }
1077
1078 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1079 const char *intrin,
1080 LLVMTypeRef result_type,
1081 LLVMValueRef src0)
1082 {
1083 char name[64];
1084 LLVMValueRef params[] = {
1085 to_float(ctx, src0),
1086 };
1087
1088 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1089 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1090 }
1091
1092 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1093 const char *intrin,
1094 LLVMTypeRef result_type,
1095 LLVMValueRef src0, LLVMValueRef src1)
1096 {
1097 char name[64];
1098 LLVMValueRef params[] = {
1099 to_float(ctx, src0),
1100 to_float(ctx, src1),
1101 };
1102
1103 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1104 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1105 }
1106
1107 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1108 const char *intrin,
1109 LLVMTypeRef result_type,
1110 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1111 {
1112 char name[64];
1113 LLVMValueRef params[] = {
1114 to_float(ctx, src0),
1115 to_float(ctx, src1),
1116 to_float(ctx, src2),
1117 };
1118
1119 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1120 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1121 }
1122
1123 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1124 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1125 {
1126 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1127 ctx->i32zero, "");
1128 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1129 }
1130
1131 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1132 LLVMValueRef src0)
1133 {
1134 LLVMValueRef params[2] = {
1135 src0,
1136
1137 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1138 * add special code to check for x=0. The reason is that
1139 * the LLVM behavior for x=0 is different from what we
1140 * need here.
1141 *
1142 * The hardware already implements the correct behavior.
1143 */
1144 LLVMConstInt(ctx->i32, 1, false),
1145 };
1146 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1147 }
1148
1149 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1150 LLVMValueRef src0)
1151 {
1152 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1153 }
1154
1155 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1156 LLVMValueRef src0)
1157 {
1158 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1159 }
1160
1161 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1162 LLVMIntPredicate pred,
1163 LLVMValueRef src0, LLVMValueRef src1)
1164 {
1165 return LLVMBuildSelect(ctx->builder,
1166 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1167 src0,
1168 src1, "");
1169
1170 }
1171 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1172 LLVMValueRef src0)
1173 {
1174 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1175 LLVMBuildNeg(ctx->builder, src0, ""));
1176 }
1177
1178 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1179 LLVMValueRef src0)
1180 {
1181 LLVMValueRef cmp, val;
1182
1183 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1184 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1185 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1186 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1187 return val;
1188 }
1189
1190 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1191 LLVMValueRef src0)
1192 {
1193 LLVMValueRef cmp, val;
1194
1195 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1196 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1197 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1198 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1199 return val;
1200 }
1201
1202 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1203 LLVMValueRef src0)
1204 {
1205 const char *intr = "llvm.floor.f32";
1206 LLVMValueRef fsrc0 = to_float(ctx, src0);
1207 LLVMValueRef params[] = {
1208 fsrc0,
1209 };
1210 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1211 ctx->f32, params, 1,
1212 AC_FUNC_ATTR_READNONE);
1213 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1214 }
1215
1216 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1217 const char *intrin,
1218 LLVMValueRef src0, LLVMValueRef src1)
1219 {
1220 LLVMTypeRef ret_type;
1221 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1222 LLVMValueRef res;
1223 LLVMValueRef params[] = { src0, src1 };
1224 ret_type = LLVMStructTypeInContext(ctx->context, types,
1225 2, true);
1226
1227 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1228 params, 2, AC_FUNC_ATTR_READNONE);
1229
1230 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1231 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1232 return res;
1233 }
1234
1235 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1236 LLVMValueRef src0)
1237 {
1238 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1239 }
1240
1241 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1242 LLVMValueRef src0, LLVMValueRef src1)
1243 {
1244 LLVMValueRef dst64, result;
1245 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1246 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1247
1248 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1249 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1250 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1251 return result;
1252 }
1253
1254 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1255 LLVMValueRef src0, LLVMValueRef src1)
1256 {
1257 LLVMValueRef dst64, result;
1258 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1259 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1260
1261 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1262 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1263 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1264 return result;
1265 }
1266
1267 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1268 bool is_signed,
1269 LLVMValueRef srcs[3])
1270 {
1271 LLVMValueRef result;
1272 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1273
1274 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1275 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1276 return result;
1277 }
1278
1279 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1280 LLVMValueRef src0, LLVMValueRef src1,
1281 LLVMValueRef src2, LLVMValueRef src3)
1282 {
1283 LLVMValueRef bfi_args[3], result;
1284
1285 bfi_args[0] = LLVMBuildShl(ctx->builder,
1286 LLVMBuildSub(ctx->builder,
1287 LLVMBuildShl(ctx->builder,
1288 ctx->i32one,
1289 src3, ""),
1290 ctx->i32one, ""),
1291 src2, "");
1292 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1293 bfi_args[2] = src0;
1294
1295 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1296
1297 /* Calculate:
1298 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1299 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1300 */
1301 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1302 LLVMBuildAnd(ctx->builder, bfi_args[0],
1303 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1304
1305 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1306 return result;
1307 }
1308
1309 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1310 LLVMValueRef src0)
1311 {
1312 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1313 int i;
1314 LLVMValueRef comp[2];
1315
1316 src0 = to_float(ctx, src0);
1317 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1318 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1319 for (i = 0; i < 2; i++) {
1320 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1321 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1322 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1323 }
1324
1325 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1326 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1327
1328 return comp[0];
1329 }
1330
1331 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1332 LLVMValueRef src0)
1333 {
1334 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1335 LLVMValueRef temps[2], result, val;
1336 int i;
1337
1338 for (i = 0; i < 2; i++) {
1339 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1340 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1341 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1342 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1343 }
1344
1345 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1346 ctx->i32zero, "");
1347 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1348 ctx->i32one, "");
1349 return result;
1350 }
1351
1352 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1353 nir_op op,
1354 LLVMValueRef src0)
1355 {
1356 unsigned mask;
1357 int idx;
1358 LLVMValueRef result;
1359 ctx->has_ddxy = true;
1360
1361 if (!ctx->lds && !ctx->has_ds_bpermute)
1362 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1363 LLVMArrayType(ctx->i32, 64),
1364 "ddxy_lds", LOCAL_ADDR_SPACE);
1365
1366 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1367 mask = AC_TID_MASK_LEFT;
1368 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1369 mask = AC_TID_MASK_TOP;
1370 else
1371 mask = AC_TID_MASK_TOP_LEFT;
1372
1373 /* for DDX we want to next X pixel, DDY next Y pixel. */
1374 if (op == nir_op_fddx_fine ||
1375 op == nir_op_fddx_coarse ||
1376 op == nir_op_fddx)
1377 idx = 1;
1378 else
1379 idx = 2;
1380
1381 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1382 mask, idx, ctx->lds,
1383 src0);
1384 return result;
1385 }
1386
1387 /*
1388 * this takes an I,J coordinate pair,
1389 * and works out the X and Y derivatives.
1390 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1391 */
1392 static LLVMValueRef emit_ddxy_interp(
1393 struct nir_to_llvm_context *ctx,
1394 LLVMValueRef interp_ij)
1395 {
1396 LLVMValueRef result[4], a;
1397 unsigned i;
1398
1399 for (i = 0; i < 2; i++) {
1400 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1401 LLVMConstInt(ctx->i32, i, false), "");
1402 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1403 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1404 }
1405 return ac_build_gather_values(&ctx->ac, result, 4);
1406 }
1407
1408 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1409 {
1410 LLVMValueRef src[4], result = NULL;
1411 unsigned num_components = instr->dest.dest.ssa.num_components;
1412 unsigned src_components;
1413 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1414
1415 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1416 switch (instr->op) {
1417 case nir_op_vec2:
1418 case nir_op_vec3:
1419 case nir_op_vec4:
1420 src_components = 1;
1421 break;
1422 case nir_op_pack_half_2x16:
1423 src_components = 2;
1424 break;
1425 case nir_op_unpack_half_2x16:
1426 src_components = 1;
1427 break;
1428 default:
1429 src_components = num_components;
1430 break;
1431 }
1432 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1433 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1434
1435 switch (instr->op) {
1436 case nir_op_fmov:
1437 case nir_op_imov:
1438 result = src[0];
1439 break;
1440 case nir_op_fneg:
1441 src[0] = to_float(ctx, src[0]);
1442 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1443 break;
1444 case nir_op_ineg:
1445 result = LLVMBuildNeg(ctx->builder, src[0], "");
1446 break;
1447 case nir_op_inot:
1448 result = LLVMBuildNot(ctx->builder, src[0], "");
1449 break;
1450 case nir_op_iadd:
1451 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1452 break;
1453 case nir_op_fadd:
1454 src[0] = to_float(ctx, src[0]);
1455 src[1] = to_float(ctx, src[1]);
1456 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1457 break;
1458 case nir_op_fsub:
1459 src[0] = to_float(ctx, src[0]);
1460 src[1] = to_float(ctx, src[1]);
1461 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1462 break;
1463 case nir_op_isub:
1464 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1465 break;
1466 case nir_op_imul:
1467 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1468 break;
1469 case nir_op_imod:
1470 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1471 break;
1472 case nir_op_umod:
1473 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1474 break;
1475 case nir_op_fmod:
1476 src[0] = to_float(ctx, src[0]);
1477 src[1] = to_float(ctx, src[1]);
1478 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1479 result = emit_intrin_1f_param(ctx, "llvm.floor",
1480 to_float_type(ctx, def_type), result);
1481 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1482 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1483 break;
1484 case nir_op_frem:
1485 src[0] = to_float(ctx, src[0]);
1486 src[1] = to_float(ctx, src[1]);
1487 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1488 break;
1489 case nir_op_irem:
1490 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1491 break;
1492 case nir_op_idiv:
1493 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1494 break;
1495 case nir_op_udiv:
1496 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1497 break;
1498 case nir_op_fmul:
1499 src[0] = to_float(ctx, src[0]);
1500 src[1] = to_float(ctx, src[1]);
1501 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1502 break;
1503 case nir_op_fdiv:
1504 src[0] = to_float(ctx, src[0]);
1505 src[1] = to_float(ctx, src[1]);
1506 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1507 break;
1508 case nir_op_frcp:
1509 src[0] = to_float(ctx, src[0]);
1510 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1511 break;
1512 case nir_op_iand:
1513 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1514 break;
1515 case nir_op_ior:
1516 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1517 break;
1518 case nir_op_ixor:
1519 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1520 break;
1521 case nir_op_ishl:
1522 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1523 break;
1524 case nir_op_ishr:
1525 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1526 break;
1527 case nir_op_ushr:
1528 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1529 break;
1530 case nir_op_ilt:
1531 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1532 break;
1533 case nir_op_ine:
1534 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1535 break;
1536 case nir_op_ieq:
1537 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1538 break;
1539 case nir_op_ige:
1540 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1541 break;
1542 case nir_op_ult:
1543 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1544 break;
1545 case nir_op_uge:
1546 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1547 break;
1548 case nir_op_feq:
1549 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1550 break;
1551 case nir_op_fne:
1552 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1553 break;
1554 case nir_op_flt:
1555 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1556 break;
1557 case nir_op_fge:
1558 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1559 break;
1560 case nir_op_fabs:
1561 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1562 to_float_type(ctx, def_type), src[0]);
1563 break;
1564 case nir_op_iabs:
1565 result = emit_iabs(ctx, src[0]);
1566 break;
1567 case nir_op_imax:
1568 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1569 break;
1570 case nir_op_imin:
1571 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1572 break;
1573 case nir_op_umax:
1574 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1575 break;
1576 case nir_op_umin:
1577 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1578 break;
1579 case nir_op_isign:
1580 result = emit_isign(ctx, src[0]);
1581 break;
1582 case nir_op_fsign:
1583 src[0] = to_float(ctx, src[0]);
1584 result = emit_fsign(ctx, src[0]);
1585 break;
1586 case nir_op_ffloor:
1587 result = emit_intrin_1f_param(ctx, "llvm.floor",
1588 to_float_type(ctx, def_type), src[0]);
1589 break;
1590 case nir_op_ftrunc:
1591 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1592 to_float_type(ctx, def_type), src[0]);
1593 break;
1594 case nir_op_fceil:
1595 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1596 to_float_type(ctx, def_type), src[0]);
1597 break;
1598 case nir_op_fround_even:
1599 result = emit_intrin_1f_param(ctx, "llvm.rint",
1600 to_float_type(ctx, def_type),src[0]);
1601 break;
1602 case nir_op_ffract:
1603 result = emit_ffract(ctx, src[0]);
1604 break;
1605 case nir_op_fsin:
1606 result = emit_intrin_1f_param(ctx, "llvm.sin",
1607 to_float_type(ctx, def_type), src[0]);
1608 break;
1609 case nir_op_fcos:
1610 result = emit_intrin_1f_param(ctx, "llvm.cos",
1611 to_float_type(ctx, def_type), src[0]);
1612 break;
1613 case nir_op_fsqrt:
1614 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1615 to_float_type(ctx, def_type), src[0]);
1616 break;
1617 case nir_op_fexp2:
1618 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1619 to_float_type(ctx, def_type), src[0]);
1620 break;
1621 case nir_op_flog2:
1622 result = emit_intrin_1f_param(ctx, "llvm.log2",
1623 to_float_type(ctx, def_type), src[0]);
1624 break;
1625 case nir_op_frsq:
1626 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1627 to_float_type(ctx, def_type), src[0]);
1628 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1629 break;
1630 case nir_op_fpow:
1631 result = emit_intrin_2f_param(ctx, "llvm.pow",
1632 to_float_type(ctx, def_type), src[0], src[1]);
1633 break;
1634 case nir_op_fmax:
1635 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1636 to_float_type(ctx, def_type), src[0], src[1]);
1637 break;
1638 case nir_op_fmin:
1639 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1640 to_float_type(ctx, def_type), src[0], src[1]);
1641 break;
1642 case nir_op_ffma:
1643 result = emit_intrin_3f_param(ctx, "llvm.fma",
1644 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1645 break;
1646 case nir_op_ibitfield_extract:
1647 result = emit_bitfield_extract(ctx, true, src);
1648 break;
1649 case nir_op_ubitfield_extract:
1650 result = emit_bitfield_extract(ctx, false, src);
1651 break;
1652 case nir_op_bitfield_insert:
1653 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1654 break;
1655 case nir_op_bitfield_reverse:
1656 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1657 break;
1658 case nir_op_bit_count:
1659 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1660 break;
1661 case nir_op_vec2:
1662 case nir_op_vec3:
1663 case nir_op_vec4:
1664 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1665 src[i] = to_integer(ctx, src[i]);
1666 result = ac_build_gather_values(&ctx->ac, src, num_components);
1667 break;
1668 case nir_op_f2i32:
1669 case nir_op_f2i64:
1670 src[0] = to_float(ctx, src[0]);
1671 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1672 break;
1673 case nir_op_f2u32:
1674 case nir_op_f2u64:
1675 src[0] = to_float(ctx, src[0]);
1676 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1677 break;
1678 case nir_op_i2f32:
1679 case nir_op_i2f64:
1680 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1681 break;
1682 case nir_op_u2f32:
1683 case nir_op_u2f64:
1684 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1685 break;
1686 case nir_op_f2f64:
1687 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1688 break;
1689 case nir_op_f2f32:
1690 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1691 break;
1692 case nir_op_u2u32:
1693 case nir_op_u2u64:
1694 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1695 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1696 else
1697 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1698 break;
1699 case nir_op_i2i32:
1700 case nir_op_i2i64:
1701 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1702 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1703 else
1704 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1705 break;
1706 case nir_op_bcsel:
1707 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1708 break;
1709 case nir_op_find_lsb:
1710 result = emit_find_lsb(ctx, src[0]);
1711 break;
1712 case nir_op_ufind_msb:
1713 result = emit_ufind_msb(ctx, src[0]);
1714 break;
1715 case nir_op_ifind_msb:
1716 result = emit_ifind_msb(ctx, src[0]);
1717 break;
1718 case nir_op_uadd_carry:
1719 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1720 break;
1721 case nir_op_usub_borrow:
1722 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1723 break;
1724 case nir_op_b2f:
1725 result = emit_b2f(ctx, src[0]);
1726 break;
1727 case nir_op_fquantize2f16:
1728 src[0] = to_float(ctx, src[0]);
1729 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1730 /* need to convert back up to f32 */
1731 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1732 break;
1733 case nir_op_umul_high:
1734 result = emit_umul_high(ctx, src[0], src[1]);
1735 break;
1736 case nir_op_imul_high:
1737 result = emit_imul_high(ctx, src[0], src[1]);
1738 break;
1739 case nir_op_pack_half_2x16:
1740 result = emit_pack_half_2x16(ctx, src[0]);
1741 break;
1742 case nir_op_unpack_half_2x16:
1743 result = emit_unpack_half_2x16(ctx, src[0]);
1744 break;
1745 case nir_op_fddx:
1746 case nir_op_fddy:
1747 case nir_op_fddx_fine:
1748 case nir_op_fddy_fine:
1749 case nir_op_fddx_coarse:
1750 case nir_op_fddy_coarse:
1751 result = emit_ddxy(ctx, instr->op, src[0]);
1752 break;
1753 default:
1754 fprintf(stderr, "Unknown NIR alu instr: ");
1755 nir_print_instr(&instr->instr, stderr);
1756 fprintf(stderr, "\n");
1757 abort();
1758 }
1759
1760 if (result) {
1761 assert(instr->dest.dest.is_ssa);
1762 result = to_integer(ctx, result);
1763 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1764 result);
1765 }
1766 }
1767
1768 static void visit_load_const(struct nir_to_llvm_context *ctx,
1769 nir_load_const_instr *instr)
1770 {
1771 LLVMValueRef values[4], value = NULL;
1772 LLVMTypeRef element_type =
1773 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1774
1775 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1776 switch (instr->def.bit_size) {
1777 case 32:
1778 values[i] = LLVMConstInt(element_type,
1779 instr->value.u32[i], false);
1780 break;
1781 case 64:
1782 values[i] = LLVMConstInt(element_type,
1783 instr->value.u64[i], false);
1784 break;
1785 default:
1786 fprintf(stderr,
1787 "unsupported nir load_const bit_size: %d\n",
1788 instr->def.bit_size);
1789 abort();
1790 }
1791 }
1792 if (instr->def.num_components > 1) {
1793 value = LLVMConstVector(values, instr->def.num_components);
1794 } else
1795 value = values[0];
1796
1797 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1798 }
1799
1800 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1801 LLVMTypeRef type)
1802 {
1803 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1804 return LLVMBuildBitCast(ctx->builder, ptr,
1805 LLVMPointerType(type, addr_space), "");
1806 }
1807
1808 static LLVMValueRef
1809 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1810 {
1811 LLVMValueRef size =
1812 LLVMBuildExtractElement(ctx->builder, descriptor,
1813 LLVMConstInt(ctx->i32, 2, false), "");
1814
1815 /* VI only */
1816 if (ctx->options->chip_class >= VI && in_elements) {
1817 /* On VI, the descriptor contains the size in bytes,
1818 * but TXQ must return the size in elements.
1819 * The stride is always non-zero for resources using TXQ.
1820 */
1821 LLVMValueRef stride =
1822 LLVMBuildExtractElement(ctx->builder, descriptor,
1823 LLVMConstInt(ctx->i32, 1, false), "");
1824 stride = LLVMBuildLShr(ctx->builder, stride,
1825 LLVMConstInt(ctx->i32, 16, false), "");
1826 stride = LLVMBuildAnd(ctx->builder, stride,
1827 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1828
1829 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1830 }
1831 return size;
1832 }
1833
1834 /**
1835 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1836 * intrinsic names).
1837 */
1838 static void build_int_type_name(
1839 LLVMTypeRef type,
1840 char *buf, unsigned bufsize)
1841 {
1842 assert(bufsize >= 6);
1843
1844 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1845 snprintf(buf, bufsize, "v%ui32",
1846 LLVMGetVectorSize(type));
1847 else
1848 strcpy(buf, "i32");
1849 }
1850
1851 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1852 struct ac_image_args *args,
1853 nir_tex_instr *instr)
1854 {
1855 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1856 LLVMValueRef coord = args->addr;
1857 LLVMValueRef half_texel[2];
1858 LLVMValueRef compare_cube_wa;
1859 LLVMValueRef result;
1860 int c;
1861 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1862
1863 //TODO Rect
1864 {
1865 struct ac_image_args txq_args = { 0 };
1866
1867 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1868 txq_args.opcode = ac_image_get_resinfo;
1869 txq_args.dmask = 0xf;
1870 txq_args.addr = ctx->i32zero;
1871 txq_args.resource = args->resource;
1872 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1873
1874 for (c = 0; c < 2; c++) {
1875 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1876 LLVMConstInt(ctx->i32, c, false), "");
1877 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1878 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1879 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1880 LLVMConstReal(ctx->f32, -0.5), "");
1881 }
1882 }
1883
1884 LLVMValueRef orig_coords = args->addr;
1885
1886 for (c = 0; c < 2; c++) {
1887 LLVMValueRef tmp;
1888 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1889 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1890 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1891 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1892 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1893 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1894 }
1895
1896
1897 /*
1898 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1899 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1900 * workaround by sampling using a scaled type and converting.
1901 * This is taken from amdgpu-pro shaders.
1902 */
1903 /* NOTE this produces some ugly code compared to amdgpu-pro,
1904 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1905 * and then reads them back. -pro generates two selects,
1906 * one s_cmp for the descriptor rewriting
1907 * one v_cmp for the coordinate and result changes.
1908 */
1909 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1910 LLVMValueRef tmp, tmp2;
1911
1912 /* workaround 8/8/8/8 uint/sint cube gather bug */
1913 /* first detect it then change to a scaled read and f2i */
1914 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
1915 tmp2 = tmp;
1916
1917 /* extract the DATA_FORMAT */
1918 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
1919 LLVMConstInt(ctx->i32, 6, false), false);
1920
1921 /* is the DATA_FORMAT == 8_8_8_8 */
1922 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
1923
1924 if (stype == GLSL_TYPE_UINT)
1925 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
1926 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
1927 LLVMConstInt(ctx->i32, 0x10000000, false), "");
1928 else
1929 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
1930 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
1931 LLVMConstInt(ctx->i32, 0x14000000, false), "");
1932
1933 /* replace the NUM FORMAT in the descriptor */
1934 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
1935 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
1936
1937 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
1938
1939 /* don't modify the coordinates for this case */
1940 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
1941 }
1942 args->addr = coord;
1943 result = ac_build_image_opcode(&ctx->ac, args);
1944
1945 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1946 LLVMValueRef tmp, tmp2;
1947
1948 /* if the cube workaround is in place, f2i the result. */
1949 for (c = 0; c < 4; c++) {
1950 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
1951 if (stype == GLSL_TYPE_UINT)
1952 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
1953 else
1954 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
1955 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1956 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
1957 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
1958 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1959 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
1960 }
1961 }
1962 return result;
1963 }
1964
1965 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1966 nir_tex_instr *instr,
1967 struct ac_image_args *args)
1968 {
1969 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
1970 return ac_build_buffer_load_format(&ctx->ac,
1971 args->resource,
1972 args->addr,
1973 LLVMConstInt(ctx->i32, 0, false),
1974 true);
1975 }
1976
1977 args->opcode = ac_image_sample;
1978 args->compare = instr->is_shadow;
1979
1980 switch (instr->op) {
1981 case nir_texop_txf:
1982 case nir_texop_txf_ms:
1983 case nir_texop_samples_identical:
1984 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
1985 args->compare = false;
1986 args->offset = false;
1987 break;
1988 case nir_texop_txb:
1989 args->bias = true;
1990 break;
1991 case nir_texop_txl:
1992 args->lod = true;
1993 break;
1994 case nir_texop_txs:
1995 case nir_texop_query_levels:
1996 args->opcode = ac_image_get_resinfo;
1997 break;
1998 case nir_texop_tex:
1999 if (ctx->stage != MESA_SHADER_FRAGMENT)
2000 args->level_zero = true;
2001 break;
2002 case nir_texop_txd:
2003 args->deriv = true;
2004 break;
2005 case nir_texop_tg4:
2006 args->opcode = ac_image_gather4;
2007 args->level_zero = true;
2008 break;
2009 case nir_texop_lod:
2010 args->opcode = ac_image_get_lod;
2011 args->compare = false;
2012 args->offset = false;
2013 break;
2014 default:
2015 break;
2016 }
2017
2018 if (instr->op == nir_texop_tg4) {
2019 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2020 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2021 return radv_lower_gather4_integer(ctx, args, instr);
2022 }
2023 }
2024 return ac_build_image_opcode(&ctx->ac, args);
2025 }
2026
2027 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2028 nir_intrinsic_instr *instr)
2029 {
2030 LLVMValueRef index = get_src(ctx, instr->src[0]);
2031 unsigned desc_set = nir_intrinsic_desc_set(instr);
2032 unsigned binding = nir_intrinsic_binding(instr);
2033 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2034 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2035 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2036 unsigned base_offset = layout->binding[binding].offset;
2037 LLVMValueRef offset, stride;
2038
2039 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2040 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2041 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2042 layout->binding[binding].dynamic_offset_offset;
2043 desc_ptr = ctx->push_constants;
2044 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2045 stride = LLVMConstInt(ctx->i32, 16, false);
2046 } else
2047 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2048
2049 offset = LLVMConstInt(ctx->i32, base_offset, false);
2050 index = LLVMBuildMul(ctx->builder, index, stride, "");
2051 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2052
2053 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2054 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2055 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2056
2057 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2058 }
2059
2060 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2061 nir_intrinsic_instr *instr)
2062 {
2063 LLVMValueRef ptr, addr;
2064
2065 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2066 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2067
2068 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2069 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2070
2071 return LLVMBuildLoad(ctx->builder, ptr, "");
2072 }
2073
2074 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2075 nir_intrinsic_instr *instr)
2076 {
2077 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2078
2079 return get_buffer_size(ctx, desc, false);
2080 }
2081 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2082 nir_intrinsic_instr *instr)
2083 {
2084 const char *store_name;
2085 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2086 LLVMTypeRef data_type = ctx->f32;
2087 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2088 int components_32bit = elem_size_mult * instr->num_components;
2089 unsigned writemask = nir_intrinsic_write_mask(instr);
2090 LLVMValueRef base_data, base_offset;
2091 LLVMValueRef params[6];
2092
2093 if (ctx->stage == MESA_SHADER_FRAGMENT)
2094 ctx->shader_info->fs.writes_memory = true;
2095
2096 params[1] = get_src(ctx, instr->src[1]);
2097 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2098 params[4] = ctx->i1false; /* glc */
2099 params[5] = ctx->i1false; /* slc */
2100
2101 if (components_32bit > 1)
2102 data_type = LLVMVectorType(ctx->f32, components_32bit);
2103
2104 base_data = to_float(ctx, src_data);
2105 base_data = trim_vector(ctx, base_data, instr->num_components);
2106 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2107 data_type, "");
2108 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2109 while (writemask) {
2110 int start, count;
2111 LLVMValueRef data;
2112 LLVMValueRef offset;
2113 LLVMValueRef tmp;
2114 u_bit_scan_consecutive_range(&writemask, &start, &count);
2115
2116 /* Due to an LLVM limitation, split 3-element writes
2117 * into a 2-element and a 1-element write. */
2118 if (count == 3) {
2119 writemask |= 1 << (start + 2);
2120 count = 2;
2121 }
2122
2123 start *= elem_size_mult;
2124 count *= elem_size_mult;
2125
2126 if (count > 4) {
2127 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2128 count = 4;
2129 }
2130
2131 if (count == 4) {
2132 store_name = "llvm.amdgcn.buffer.store.v4f32";
2133 data = base_data;
2134 } else if (count == 2) {
2135 tmp = LLVMBuildExtractElement(ctx->builder,
2136 base_data, LLVMConstInt(ctx->i32, start, false), "");
2137 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2138 ctx->i32zero, "");
2139
2140 tmp = LLVMBuildExtractElement(ctx->builder,
2141 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2142 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2143 ctx->i32one, "");
2144 store_name = "llvm.amdgcn.buffer.store.v2f32";
2145
2146 } else {
2147 assert(count == 1);
2148 if (get_llvm_num_components(base_data) > 1)
2149 data = LLVMBuildExtractElement(ctx->builder, base_data,
2150 LLVMConstInt(ctx->i32, start, false), "");
2151 else
2152 data = base_data;
2153 store_name = "llvm.amdgcn.buffer.store.f32";
2154 }
2155
2156 offset = base_offset;
2157 if (start != 0) {
2158 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2159 }
2160 params[0] = data;
2161 params[3] = offset;
2162 ac_build_intrinsic(&ctx->ac, store_name,
2163 ctx->voidt, params, 6, 0);
2164 }
2165 }
2166
2167 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2168 nir_intrinsic_instr *instr)
2169 {
2170 const char *name;
2171 LLVMValueRef params[6];
2172 int arg_count = 0;
2173 if (ctx->stage == MESA_SHADER_FRAGMENT)
2174 ctx->shader_info->fs.writes_memory = true;
2175
2176 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2177 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2178 }
2179 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2180 params[arg_count++] = get_src(ctx, instr->src[0]);
2181 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2182 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2183 params[arg_count++] = ctx->i1false; /* slc */
2184
2185 switch (instr->intrinsic) {
2186 case nir_intrinsic_ssbo_atomic_add:
2187 name = "llvm.amdgcn.buffer.atomic.add";
2188 break;
2189 case nir_intrinsic_ssbo_atomic_imin:
2190 name = "llvm.amdgcn.buffer.atomic.smin";
2191 break;
2192 case nir_intrinsic_ssbo_atomic_umin:
2193 name = "llvm.amdgcn.buffer.atomic.umin";
2194 break;
2195 case nir_intrinsic_ssbo_atomic_imax:
2196 name = "llvm.amdgcn.buffer.atomic.smax";
2197 break;
2198 case nir_intrinsic_ssbo_atomic_umax:
2199 name = "llvm.amdgcn.buffer.atomic.umax";
2200 break;
2201 case nir_intrinsic_ssbo_atomic_and:
2202 name = "llvm.amdgcn.buffer.atomic.and";
2203 break;
2204 case nir_intrinsic_ssbo_atomic_or:
2205 name = "llvm.amdgcn.buffer.atomic.or";
2206 break;
2207 case nir_intrinsic_ssbo_atomic_xor:
2208 name = "llvm.amdgcn.buffer.atomic.xor";
2209 break;
2210 case nir_intrinsic_ssbo_atomic_exchange:
2211 name = "llvm.amdgcn.buffer.atomic.swap";
2212 break;
2213 case nir_intrinsic_ssbo_atomic_comp_swap:
2214 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2215 break;
2216 default:
2217 abort();
2218 }
2219
2220 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2221 }
2222
2223 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2224 nir_intrinsic_instr *instr)
2225 {
2226 LLVMValueRef results[2];
2227 int load_components;
2228 int num_components = instr->num_components;
2229 if (instr->dest.ssa.bit_size == 64)
2230 num_components *= 2;
2231
2232 for (int i = 0; i < num_components; i += load_components) {
2233 load_components = MIN2(num_components - i, 4);
2234 const char *load_name;
2235 LLVMTypeRef data_type = ctx->f32;
2236 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2237 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2238
2239 if (load_components == 3)
2240 data_type = LLVMVectorType(ctx->f32, 4);
2241 else if (load_components > 1)
2242 data_type = LLVMVectorType(ctx->f32, load_components);
2243
2244 if (load_components >= 3)
2245 load_name = "llvm.amdgcn.buffer.load.v4f32";
2246 else if (load_components == 2)
2247 load_name = "llvm.amdgcn.buffer.load.v2f32";
2248 else if (load_components == 1)
2249 load_name = "llvm.amdgcn.buffer.load.f32";
2250 else
2251 unreachable("unhandled number of components");
2252
2253 LLVMValueRef params[] = {
2254 get_src(ctx, instr->src[0]),
2255 LLVMConstInt(ctx->i32, 0, false),
2256 offset,
2257 ctx->i1false,
2258 ctx->i1false,
2259 };
2260
2261 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2262
2263 }
2264
2265 LLVMValueRef ret = results[0];
2266 if (num_components > 4 || num_components == 3) {
2267 LLVMValueRef masks[] = {
2268 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2269 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2270 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2271 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2272 };
2273
2274 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2275 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2276 results[num_components > 4 ? 1 : 0], swizzle, "");
2277 }
2278
2279 return LLVMBuildBitCast(ctx->builder, ret,
2280 get_def_type(ctx, &instr->dest.ssa), "");
2281 }
2282
2283 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2284 nir_intrinsic_instr *instr)
2285 {
2286 LLVMValueRef results[8], ret;
2287 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2288 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2289 int num_components = instr->num_components;
2290
2291 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2292
2293 if (instr->dest.ssa.bit_size == 64)
2294 num_components *= 2;
2295
2296 for (unsigned i = 0; i < num_components; ++i) {
2297 LLVMValueRef params[] = {
2298 rsrc,
2299 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2300 offset, "")
2301 };
2302 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2303 params, 2,
2304 AC_FUNC_ATTR_READNONE |
2305 AC_FUNC_ATTR_LEGACY);
2306 }
2307
2308
2309 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2310 return LLVMBuildBitCast(ctx->builder, ret,
2311 get_def_type(ctx, &instr->dest.ssa), "");
2312 }
2313
2314 static void
2315 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2316 bool vs_in, unsigned *vertex_index_out,
2317 LLVMValueRef *vertex_index_ref,
2318 unsigned *const_out, LLVMValueRef *indir_out)
2319 {
2320 unsigned const_offset = 0;
2321 nir_deref *tail = &deref->deref;
2322 LLVMValueRef offset = NULL;
2323
2324 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2325 tail = tail->child;
2326 nir_deref_array *deref_array = nir_deref_as_array(tail);
2327 if (vertex_index_out)
2328 *vertex_index_out = deref_array->base_offset;
2329
2330 if (vertex_index_ref) {
2331 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2332 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2333 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2334 }
2335 *vertex_index_ref = vtx;
2336 }
2337 }
2338
2339 if (deref->var->data.compact) {
2340 assert(tail->child->deref_type == nir_deref_type_array);
2341 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2342 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2343 /* We always lower indirect dereferences for "compact" array vars. */
2344 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2345
2346 const_offset = deref_array->base_offset;
2347 goto out;
2348 }
2349
2350 while (tail->child != NULL) {
2351 const struct glsl_type *parent_type = tail->type;
2352 tail = tail->child;
2353
2354 if (tail->deref_type == nir_deref_type_array) {
2355 nir_deref_array *deref_array = nir_deref_as_array(tail);
2356 LLVMValueRef index, stride, local_offset;
2357 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2358
2359 const_offset += size * deref_array->base_offset;
2360 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2361 continue;
2362
2363 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2364 index = get_src(ctx, deref_array->indirect);
2365 stride = LLVMConstInt(ctx->i32, size, 0);
2366 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2367
2368 if (offset)
2369 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2370 else
2371 offset = local_offset;
2372 } else if (tail->deref_type == nir_deref_type_struct) {
2373 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2374
2375 for (unsigned i = 0; i < deref_struct->index; i++) {
2376 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2377 const_offset += glsl_count_attribute_slots(ft, vs_in);
2378 }
2379 } else
2380 unreachable("unsupported deref type");
2381
2382 }
2383 out:
2384 if (const_offset && offset)
2385 offset = LLVMBuildAdd(ctx->builder, offset,
2386 LLVMConstInt(ctx->i32, const_offset, 0),
2387 "");
2388
2389 *const_out = const_offset;
2390 *indir_out = offset;
2391 }
2392
2393 static LLVMValueRef
2394 lds_load(struct nir_to_llvm_context *ctx,
2395 LLVMValueRef dw_addr)
2396 {
2397 LLVMValueRef value;
2398 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2399 return value;
2400 }
2401
2402 static void
2403 lds_store(struct nir_to_llvm_context *ctx,
2404 LLVMValueRef dw_addr, LLVMValueRef value)
2405 {
2406 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2407 ac_build_indexed_store(&ctx->ac, ctx->lds,
2408 dw_addr, value);
2409 }
2410
2411 /* The offchip buffer layout for TCS->TES is
2412 *
2413 * - attribute 0 of patch 0 vertex 0
2414 * - attribute 0 of patch 0 vertex 1
2415 * - attribute 0 of patch 0 vertex 2
2416 * ...
2417 * - attribute 0 of patch 1 vertex 0
2418 * - attribute 0 of patch 1 vertex 1
2419 * ...
2420 * - attribute 1 of patch 0 vertex 0
2421 * - attribute 1 of patch 0 vertex 1
2422 * ...
2423 * - per patch attribute 0 of patch 0
2424 * - per patch attribute 0 of patch 1
2425 * ...
2426 *
2427 * Note that every attribute has 4 components.
2428 */
2429 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2430 LLVMValueRef vertex_index,
2431 LLVMValueRef param_index)
2432 {
2433 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2434 LLVMValueRef param_stride, constant16;
2435 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2436
2437 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2438 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2439 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2440 num_patches, "");
2441
2442 constant16 = LLVMConstInt(ctx->i32, 16, false);
2443 if (vertex_index) {
2444 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2445 vertices_per_patch, "");
2446
2447 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2448 vertex_index, "");
2449
2450 param_stride = total_vertices;
2451 } else {
2452 base_addr = rel_patch_id;
2453 param_stride = num_patches;
2454 }
2455
2456 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2457 LLVMBuildMul(ctx->builder, param_index,
2458 param_stride, ""), "");
2459
2460 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2461
2462 if (!vertex_index) {
2463 LLVMValueRef patch_data_offset =
2464 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2465
2466 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2467 patch_data_offset, "");
2468 }
2469 return base_addr;
2470 }
2471
2472 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2473 unsigned param,
2474 unsigned const_index,
2475 bool is_compact,
2476 LLVMValueRef vertex_index,
2477 LLVMValueRef indir_index)
2478 {
2479 LLVMValueRef param_index;
2480
2481 if (indir_index)
2482 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2483 indir_index, "");
2484 else {
2485 if (const_index && !is_compact)
2486 param += const_index;
2487 param_index = LLVMConstInt(ctx->i32, param, false);
2488 }
2489 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2490 }
2491
2492 static void
2493 mark_tess_output(struct nir_to_llvm_context *ctx,
2494 bool is_patch, uint32_t param)
2495
2496 {
2497 if (is_patch) {
2498 ctx->tess_patch_outputs_written |= (1ull << param);
2499 } else
2500 ctx->tess_outputs_written |= (1ull << param);
2501 }
2502
2503 static LLVMValueRef
2504 get_dw_address(struct nir_to_llvm_context *ctx,
2505 LLVMValueRef dw_addr,
2506 unsigned param,
2507 unsigned const_index,
2508 bool compact_const_index,
2509 LLVMValueRef vertex_index,
2510 LLVMValueRef stride,
2511 LLVMValueRef indir_index)
2512
2513 {
2514
2515 if (vertex_index) {
2516 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2517 LLVMBuildMul(ctx->builder,
2518 vertex_index,
2519 stride, ""), "");
2520 }
2521
2522 if (indir_index)
2523 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2524 LLVMBuildMul(ctx->builder, indir_index,
2525 LLVMConstInt(ctx->i32, 4, false), ""), "");
2526 else if (const_index && !compact_const_index)
2527 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2528 LLVMConstInt(ctx->i32, const_index, false), "");
2529
2530 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2531 LLVMConstInt(ctx->i32, param * 4, false), "");
2532
2533 if (const_index && compact_const_index)
2534 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2535 LLVMConstInt(ctx->i32, const_index, false), "");
2536 return dw_addr;
2537 }
2538
2539 static LLVMValueRef
2540 load_tcs_input(struct nir_to_llvm_context *ctx,
2541 nir_intrinsic_instr *instr)
2542 {
2543 LLVMValueRef dw_addr, stride;
2544 unsigned const_index;
2545 LLVMValueRef vertex_index;
2546 LLVMValueRef indir_index;
2547 unsigned param;
2548 LLVMValueRef value[4], result;
2549 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2550 const bool is_compact = instr->variables[0]->var->data.compact;
2551 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2552 radv_get_deref_offset(ctx, instr->variables[0],
2553 false, NULL, per_vertex ? &vertex_index : NULL,
2554 &const_index, &indir_index);
2555
2556 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2557 dw_addr = get_tcs_in_current_patch_offset(ctx);
2558 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2559 indir_index);
2560
2561 for (unsigned i = 0; i < instr->num_components; i++) {
2562 value[i] = lds_load(ctx, dw_addr);
2563 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2564 ctx->i32one, "");
2565 }
2566 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2567 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2568 return result;
2569 }
2570
2571 static LLVMValueRef
2572 load_tcs_output(struct nir_to_llvm_context *ctx,
2573 nir_intrinsic_instr *instr)
2574 {
2575 LLVMValueRef dw_addr, stride;
2576 LLVMValueRef value[4], result;
2577 LLVMValueRef vertex_index = NULL;
2578 LLVMValueRef indir_index = NULL;
2579 unsigned const_index = 0;
2580 unsigned param;
2581 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2582 const bool is_compact = instr->variables[0]->var->data.compact;
2583 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2584 radv_get_deref_offset(ctx, instr->variables[0],
2585 false, NULL, per_vertex ? &vertex_index : NULL,
2586 &const_index, &indir_index);
2587
2588 if (!instr->variables[0]->var->data.patch) {
2589 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2590 dw_addr = get_tcs_out_current_patch_offset(ctx);
2591 } else {
2592 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2593 }
2594
2595 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2596 indir_index);
2597
2598 for (unsigned i = 0; i < instr->num_components; i++) {
2599 value[i] = lds_load(ctx, dw_addr);
2600 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2601 ctx->i32one, "");
2602 }
2603 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2604 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2605 return result;
2606 }
2607
2608 static void
2609 store_tcs_output(struct nir_to_llvm_context *ctx,
2610 nir_intrinsic_instr *instr,
2611 LLVMValueRef src,
2612 unsigned writemask)
2613 {
2614 LLVMValueRef stride, dw_addr;
2615 LLVMValueRef buf_addr = NULL;
2616 LLVMValueRef vertex_index = NULL;
2617 LLVMValueRef indir_index = NULL;
2618 unsigned const_index = 0;
2619 unsigned param;
2620 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2621 const bool is_compact = instr->variables[0]->var->data.compact;
2622
2623 radv_get_deref_offset(ctx, instr->variables[0],
2624 false, NULL, per_vertex ? &vertex_index : NULL,
2625 &const_index, &indir_index);
2626
2627 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2628 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2629 is_compact && const_index > 3) {
2630 const_index -= 3;
2631 param++;
2632 }
2633
2634 if (!instr->variables[0]->var->data.patch) {
2635 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2636 dw_addr = get_tcs_out_current_patch_offset(ctx);
2637 } else {
2638 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2639 }
2640
2641 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2642
2643 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2644 indir_index);
2645 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2646 vertex_index, indir_index);
2647
2648 unsigned base = is_compact ? const_index : 0;
2649 for (unsigned chan = 0; chan < 8; chan++) {
2650 bool is_tess_factor = false;
2651 if (!(writemask & (1 << chan)))
2652 continue;
2653 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2654
2655 lds_store(ctx, dw_addr, value);
2656
2657 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2658 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2659 is_tess_factor = true;
2660
2661 if (!is_tess_factor && writemask != 0xF)
2662 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2663 buf_addr, ctx->oc_lds,
2664 4 * (base + chan), 1, 0, true, false);
2665
2666 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2667 ctx->i32one, "");
2668 }
2669
2670 if (writemask == 0xF) {
2671 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2672 buf_addr, ctx->oc_lds,
2673 (base * 4), 1, 0, true, false);
2674 }
2675 }
2676
2677 static LLVMValueRef
2678 load_tes_input(struct nir_to_llvm_context *ctx,
2679 nir_intrinsic_instr *instr)
2680 {
2681 LLVMValueRef buf_addr;
2682 LLVMValueRef result;
2683 LLVMValueRef vertex_index = NULL;
2684 LLVMValueRef indir_index = NULL;
2685 unsigned const_index = 0;
2686 unsigned param;
2687 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2688 const bool is_compact = instr->variables[0]->var->data.compact;
2689
2690 radv_get_deref_offset(ctx, instr->variables[0],
2691 false, NULL, per_vertex ? &vertex_index : NULL,
2692 &const_index, &indir_index);
2693 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2694 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2695 is_compact && const_index > 3) {
2696 const_index -= 3;
2697 param++;
2698 }
2699 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2700 is_compact, vertex_index, indir_index);
2701
2702 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2703 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true);
2704 result = trim_vector(ctx, result, instr->num_components);
2705 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2706 return result;
2707 }
2708
2709 static LLVMValueRef
2710 load_gs_input(struct nir_to_llvm_context *ctx,
2711 nir_intrinsic_instr *instr)
2712 {
2713 LLVMValueRef indir_index, vtx_offset;
2714 unsigned const_index;
2715 LLVMValueRef args[9];
2716 unsigned param, vtx_offset_param;
2717 LLVMValueRef value[4], result;
2718 unsigned vertex_index;
2719 radv_get_deref_offset(ctx, instr->variables[0],
2720 false, &vertex_index, NULL,
2721 &const_index, &indir_index);
2722 vtx_offset_param = vertex_index;
2723 assert(vtx_offset_param < 6);
2724 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2725 LLVMConstInt(ctx->i32, 4, false), "");
2726
2727 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2728 for (unsigned i = 0; i < instr->num_components; i++) {
2729
2730 args[0] = ctx->esgs_ring;
2731 args[1] = vtx_offset;
2732 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2733 args[3] = ctx->i32zero;
2734 args[4] = ctx->i32one; /* OFFEN */
2735 args[5] = ctx->i32zero; /* IDXEN */
2736 args[6] = ctx->i32one; /* GLC */
2737 args[7] = ctx->i32zero; /* SLC */
2738 args[8] = ctx->i32zero; /* TFE */
2739
2740 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2741 ctx->i32, args, 9,
2742 AC_FUNC_ATTR_READONLY |
2743 AC_FUNC_ATTR_LEGACY);
2744 }
2745 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2746
2747 return result;
2748 }
2749
2750 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2751 nir_intrinsic_instr *instr)
2752 {
2753 LLVMValueRef values[8];
2754 int idx = instr->variables[0]->var->data.driver_location;
2755 int ve = instr->dest.ssa.num_components;
2756 LLVMValueRef indir_index;
2757 LLVMValueRef ret;
2758 unsigned const_index;
2759 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2760 instr->variables[0]->var->data.mode == nir_var_shader_in;
2761 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2762 &const_index, &indir_index);
2763
2764 if (instr->dest.ssa.bit_size == 64)
2765 ve *= 2;
2766
2767 switch (instr->variables[0]->var->data.mode) {
2768 case nir_var_shader_in:
2769 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2770 return load_tcs_input(ctx, instr);
2771 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2772 return load_tes_input(ctx, instr);
2773 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2774 return load_gs_input(ctx, instr);
2775 }
2776 for (unsigned chan = 0; chan < ve; chan++) {
2777 if (indir_index) {
2778 unsigned count = glsl_count_attribute_slots(
2779 instr->variables[0]->var->type,
2780 ctx->stage == MESA_SHADER_VERTEX);
2781 count -= chan / 4;
2782 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2783 &ctx->ac, ctx->inputs + idx + chan, count,
2784 4, false);
2785
2786 values[chan] = LLVMBuildExtractElement(ctx->builder,
2787 tmp_vec,
2788 indir_index, "");
2789 } else
2790 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2791 }
2792 break;
2793 case nir_var_local:
2794 for (unsigned chan = 0; chan < ve; chan++) {
2795 if (indir_index) {
2796 unsigned count = glsl_count_attribute_slots(
2797 instr->variables[0]->var->type, false);
2798 count -= chan / 4;
2799 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2800 &ctx->ac, ctx->locals + idx + chan, count,
2801 4, true);
2802
2803 values[chan] = LLVMBuildExtractElement(ctx->builder,
2804 tmp_vec,
2805 indir_index, "");
2806 } else {
2807 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2808 }
2809 }
2810 break;
2811 case nir_var_shader_out:
2812 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2813 return load_tcs_output(ctx, instr);
2814 for (unsigned chan = 0; chan < ve; chan++) {
2815 if (indir_index) {
2816 unsigned count = glsl_count_attribute_slots(
2817 instr->variables[0]->var->type, false);
2818 count -= chan / 4;
2819 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2820 &ctx->ac, ctx->outputs + idx + chan, count,
2821 4, true);
2822
2823 values[chan] = LLVMBuildExtractElement(ctx->builder,
2824 tmp_vec,
2825 indir_index, "");
2826 } else {
2827 values[chan] = LLVMBuildLoad(ctx->builder,
2828 ctx->outputs[idx + chan + const_index * 4],
2829 "");
2830 }
2831 }
2832 break;
2833 case nir_var_shared: {
2834 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2835 LLVMValueRef derived_ptr;
2836
2837 if (indir_index)
2838 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2839
2840 for (unsigned chan = 0; chan < ve; chan++) {
2841 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2842 if (indir_index)
2843 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2844 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2845
2846 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2847 }
2848 break;
2849 }
2850 default:
2851 unreachable("unhandle variable mode");
2852 }
2853 ret = ac_build_gather_values(&ctx->ac, values, ve);
2854 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2855 }
2856
2857 static void
2858 visit_store_var(struct nir_to_llvm_context *ctx,
2859 nir_intrinsic_instr *instr)
2860 {
2861 LLVMValueRef temp_ptr, value;
2862 int idx = instr->variables[0]->var->data.driver_location;
2863 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2864 int writemask = instr->const_index[0];
2865 LLVMValueRef indir_index;
2866 unsigned const_index;
2867 radv_get_deref_offset(ctx, instr->variables[0], false,
2868 NULL, NULL, &const_index, &indir_index);
2869
2870 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2871 int old_writemask = writemask;
2872
2873 src = LLVMBuildBitCast(ctx->builder, src,
2874 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2875 "");
2876
2877 writemask = 0;
2878 for (unsigned chan = 0; chan < 4; chan++) {
2879 if (old_writemask & (1 << chan))
2880 writemask |= 3u << (2 * chan);
2881 }
2882 }
2883
2884 switch (instr->variables[0]->var->data.mode) {
2885 case nir_var_shader_out:
2886
2887 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
2888 store_tcs_output(ctx, instr, src, writemask);
2889 return;
2890 }
2891
2892 for (unsigned chan = 0; chan < 8; chan++) {
2893 int stride = 4;
2894 if (!(writemask & (1 << chan)))
2895 continue;
2896
2897 value = llvm_extract_elem(ctx, src, chan);
2898
2899 if (instr->variables[0]->var->data.compact)
2900 stride = 1;
2901 if (indir_index) {
2902 unsigned count = glsl_count_attribute_slots(
2903 instr->variables[0]->var->type, false);
2904 count -= chan / 4;
2905 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2906 &ctx->ac, ctx->outputs + idx + chan, count,
2907 stride, true);
2908
2909 if (get_llvm_num_components(tmp_vec) > 1) {
2910 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2911 value, indir_index, "");
2912 } else
2913 tmp_vec = value;
2914 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2915 count, stride, tmp_vec);
2916
2917 } else {
2918 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2919
2920 LLVMBuildStore(ctx->builder, value, temp_ptr);
2921 }
2922 }
2923 break;
2924 case nir_var_local:
2925 for (unsigned chan = 0; chan < 8; chan++) {
2926 if (!(writemask & (1 << chan)))
2927 continue;
2928
2929 value = llvm_extract_elem(ctx, src, chan);
2930 if (indir_index) {
2931 unsigned count = glsl_count_attribute_slots(
2932 instr->variables[0]->var->type, false);
2933 count -= chan / 4;
2934 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2935 &ctx->ac, ctx->locals + idx + chan, count,
2936 4, true);
2937
2938 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2939 value, indir_index, "");
2940 build_store_values_extended(ctx, ctx->locals + idx + chan,
2941 count, 4, tmp_vec);
2942 } else {
2943 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2944
2945 LLVMBuildStore(ctx->builder, value, temp_ptr);
2946 }
2947 }
2948 break;
2949 case nir_var_shared: {
2950 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2951
2952 if (indir_index)
2953 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2954
2955 for (unsigned chan = 0; chan < 8; chan++) {
2956 if (!(writemask & (1 << chan)))
2957 continue;
2958 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2959 LLVMValueRef derived_ptr;
2960
2961 if (indir_index)
2962 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2963
2964 value = llvm_extract_elem(ctx, src, chan);
2965 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2966 LLVMBuildStore(ctx->builder,
2967 to_integer(ctx, value), derived_ptr);
2968 }
2969 break;
2970 }
2971 default:
2972 break;
2973 }
2974 }
2975
2976 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2977 {
2978 switch (dim) {
2979 case GLSL_SAMPLER_DIM_BUF:
2980 return 1;
2981 case GLSL_SAMPLER_DIM_1D:
2982 return array ? 2 : 1;
2983 case GLSL_SAMPLER_DIM_2D:
2984 return array ? 3 : 2;
2985 case GLSL_SAMPLER_DIM_MS:
2986 return array ? 4 : 3;
2987 case GLSL_SAMPLER_DIM_3D:
2988 case GLSL_SAMPLER_DIM_CUBE:
2989 return 3;
2990 case GLSL_SAMPLER_DIM_RECT:
2991 case GLSL_SAMPLER_DIM_SUBPASS:
2992 return 2;
2993 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2994 return 3;
2995 default:
2996 break;
2997 }
2998 return 0;
2999 }
3000
3001
3002
3003 /* Adjust the sample index according to FMASK.
3004 *
3005 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3006 * which is the identity mapping. Each nibble says which physical sample
3007 * should be fetched to get that sample.
3008 *
3009 * For example, 0x11111100 means there are only 2 samples stored and
3010 * the second sample covers 3/4 of the pixel. When reading samples 0
3011 * and 1, return physical sample 0 (determined by the first two 0s
3012 * in FMASK), otherwise return physical sample 1.
3013 *
3014 * The sample index should be adjusted as follows:
3015 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3016 */
3017 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3018 LLVMValueRef coord_x, LLVMValueRef coord_y,
3019 LLVMValueRef coord_z,
3020 LLVMValueRef sample_index,
3021 LLVMValueRef fmask_desc_ptr)
3022 {
3023 LLVMValueRef fmask_load_address[4];
3024 LLVMValueRef res;
3025
3026 fmask_load_address[0] = coord_x;
3027 fmask_load_address[1] = coord_y;
3028 if (coord_z) {
3029 fmask_load_address[2] = coord_z;
3030 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3031 }
3032
3033 struct ac_image_args args = {0};
3034
3035 args.opcode = ac_image_load;
3036 args.da = coord_z ? true : false;
3037 args.resource = fmask_desc_ptr;
3038 args.dmask = 0xf;
3039 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3040
3041 res = ac_build_image_opcode(&ctx->ac, &args);
3042
3043 res = to_integer(ctx, res);
3044 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3045 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3046
3047 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3048 res,
3049 ctx->i32zero, "");
3050
3051 LLVMValueRef sample_index4 =
3052 LLVMBuildMul(ctx->builder, sample_index, four, "");
3053 LLVMValueRef shifted_fmask =
3054 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3055 LLVMValueRef final_sample =
3056 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3057
3058 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3059 * resource descriptor is 0 (invalid),
3060 */
3061 LLVMValueRef fmask_desc =
3062 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3063 ctx->v8i32, "");
3064
3065 LLVMValueRef fmask_word1 =
3066 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3067 ctx->i32one, "");
3068
3069 LLVMValueRef word1_is_nonzero =
3070 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3071 fmask_word1, ctx->i32zero, "");
3072
3073 /* Replace the MSAA sample index. */
3074 sample_index =
3075 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3076 final_sample, sample_index, "");
3077 return sample_index;
3078 }
3079
3080 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3081 nir_intrinsic_instr *instr)
3082 {
3083 const struct glsl_type *type = instr->variables[0]->var->type;
3084 if(instr->variables[0]->deref.child)
3085 type = instr->variables[0]->deref.child->type;
3086
3087 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3088 LLVMValueRef coords[4];
3089 LLVMValueRef masks[] = {
3090 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3091 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3092 };
3093 LLVMValueRef res;
3094 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3095
3096 int count;
3097 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3098 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3099 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3100 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3101 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3102
3103 count = image_type_to_components_count(dim,
3104 glsl_sampler_type_is_array(type));
3105
3106 if (is_ms) {
3107 LLVMValueRef fmask_load_address[3];
3108 int chan;
3109
3110 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3111 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3112 if (glsl_sampler_type_is_array(type))
3113 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3114 else
3115 fmask_load_address[2] = NULL;
3116 if (add_frag_pos) {
3117 for (chan = 0; chan < 2; ++chan)
3118 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3119 }
3120 sample_index = adjust_sample_index_using_fmask(ctx,
3121 fmask_load_address[0],
3122 fmask_load_address[1],
3123 fmask_load_address[2],
3124 sample_index,
3125 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3126 }
3127 if (count == 1) {
3128 if (instr->src[0].ssa->num_components)
3129 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3130 else
3131 res = src0;
3132 } else {
3133 int chan;
3134 if (is_ms)
3135 count--;
3136 for (chan = 0; chan < count; ++chan) {
3137 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3138 }
3139
3140 if (add_frag_pos) {
3141 for (chan = 0; chan < count; ++chan)
3142 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3143 }
3144 if (is_ms) {
3145 coords[count] = sample_index;
3146 count++;
3147 }
3148
3149 if (count == 3) {
3150 coords[3] = LLVMGetUndef(ctx->i32);
3151 count = 4;
3152 }
3153 res = ac_build_gather_values(&ctx->ac, coords, count);
3154 }
3155 return res;
3156 }
3157
3158 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3159 nir_intrinsic_instr *instr)
3160 {
3161 LLVMValueRef params[7];
3162 LLVMValueRef res;
3163 char intrinsic_name[64];
3164 const nir_variable *var = instr->variables[0]->var;
3165 const struct glsl_type *type = var->type;
3166 if(instr->variables[0]->deref.child)
3167 type = instr->variables[0]->deref.child->type;
3168
3169 type = glsl_without_array(type);
3170 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3171 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3172 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3173 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3174 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3175 params[3] = ctx->i1false; /* glc */
3176 params[4] = ctx->i1false; /* slc */
3177 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3178 params, 5, 0);
3179
3180 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3181 res = to_integer(ctx, res);
3182 } else {
3183 bool is_da = glsl_sampler_type_is_array(type) ||
3184 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3185 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3186 LLVMValueRef glc = ctx->i1false;
3187 LLVMValueRef slc = ctx->i1false;
3188
3189 params[0] = get_image_coords(ctx, instr);
3190 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3191 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3192 if (HAVE_LLVM <= 0x0309) {
3193 params[3] = ctx->i1false; /* r128 */
3194 params[4] = da;
3195 params[5] = glc;
3196 params[6] = slc;
3197 } else {
3198 LLVMValueRef lwe = ctx->i1false;
3199 params[3] = glc;
3200 params[4] = slc;
3201 params[5] = lwe;
3202 params[6] = da;
3203 }
3204
3205 ac_get_image_intr_name("llvm.amdgcn.image.load",
3206 ctx->v4f32, /* vdata */
3207 LLVMTypeOf(params[0]), /* coords */
3208 LLVMTypeOf(params[1]), /* rsrc */
3209 intrinsic_name, sizeof(intrinsic_name));
3210
3211 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3212 params, 7, AC_FUNC_ATTR_READONLY);
3213 }
3214 return to_integer(ctx, res);
3215 }
3216
3217 static void visit_image_store(struct nir_to_llvm_context *ctx,
3218 nir_intrinsic_instr *instr)
3219 {
3220 LLVMValueRef params[8];
3221 char intrinsic_name[64];
3222 const nir_variable *var = instr->variables[0]->var;
3223 const struct glsl_type *type = glsl_without_array(var->type);
3224
3225 if (ctx->stage == MESA_SHADER_FRAGMENT)
3226 ctx->shader_info->fs.writes_memory = true;
3227
3228 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3229 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3230 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3231 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3232 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3233 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3234 params[4] = ctx->i1false; /* glc */
3235 params[5] = ctx->i1false; /* slc */
3236 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3237 params, 6, 0);
3238 } else {
3239 bool is_da = glsl_sampler_type_is_array(type) ||
3240 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3241 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3242 LLVMValueRef glc = ctx->i1false;
3243 LLVMValueRef slc = ctx->i1false;
3244
3245 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3246 params[1] = get_image_coords(ctx, instr); /* coords */
3247 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3248 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3249 if (HAVE_LLVM <= 0x0309) {
3250 params[4] = ctx->i1false; /* r128 */
3251 params[5] = da;
3252 params[6] = glc;
3253 params[7] = slc;
3254 } else {
3255 LLVMValueRef lwe = ctx->i1false;
3256 params[4] = glc;
3257 params[5] = slc;
3258 params[6] = lwe;
3259 params[7] = da;
3260 }
3261
3262 ac_get_image_intr_name("llvm.amdgcn.image.store",
3263 LLVMTypeOf(params[0]), /* vdata */
3264 LLVMTypeOf(params[1]), /* coords */
3265 LLVMTypeOf(params[2]), /* rsrc */
3266 intrinsic_name, sizeof(intrinsic_name));
3267
3268 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3269 params, 8, 0);
3270 }
3271
3272 }
3273
3274 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3275 nir_intrinsic_instr *instr)
3276 {
3277 LLVMValueRef params[6];
3278 int param_count = 0;
3279 const nir_variable *var = instr->variables[0]->var;
3280
3281 const char *base_name = "llvm.amdgcn.image.atomic";
3282 const char *atomic_name;
3283 LLVMValueRef coords;
3284 char intrinsic_name[32], coords_type[8];
3285 const struct glsl_type *type = glsl_without_array(var->type);
3286
3287 if (ctx->stage == MESA_SHADER_FRAGMENT)
3288 ctx->shader_info->fs.writes_memory = true;
3289
3290 params[param_count++] = get_src(ctx, instr->src[2]);
3291 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3292 params[param_count++] = get_src(ctx, instr->src[3]);
3293
3294 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3295 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3296 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3297 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3298 params[param_count++] = ctx->i32zero; /* voffset */
3299 params[param_count++] = ctx->i1false; /* glc */
3300 params[param_count++] = ctx->i1false; /* slc */
3301 } else {
3302 bool da = glsl_sampler_type_is_array(type) ||
3303 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3304
3305 coords = params[param_count++] = get_image_coords(ctx, instr);
3306 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3307 params[param_count++] = ctx->i1false; /* r128 */
3308 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3309 params[param_count++] = ctx->i1false; /* slc */
3310 }
3311
3312 switch (instr->intrinsic) {
3313 case nir_intrinsic_image_atomic_add:
3314 atomic_name = "add";
3315 break;
3316 case nir_intrinsic_image_atomic_min:
3317 atomic_name = "smin";
3318 break;
3319 case nir_intrinsic_image_atomic_max:
3320 atomic_name = "smax";
3321 break;
3322 case nir_intrinsic_image_atomic_and:
3323 atomic_name = "and";
3324 break;
3325 case nir_intrinsic_image_atomic_or:
3326 atomic_name = "or";
3327 break;
3328 case nir_intrinsic_image_atomic_xor:
3329 atomic_name = "xor";
3330 break;
3331 case nir_intrinsic_image_atomic_exchange:
3332 atomic_name = "swap";
3333 break;
3334 case nir_intrinsic_image_atomic_comp_swap:
3335 atomic_name = "cmpswap";
3336 break;
3337 default:
3338 abort();
3339 }
3340 build_int_type_name(LLVMTypeOf(coords),
3341 coords_type, sizeof(coords_type));
3342
3343 snprintf(intrinsic_name, sizeof(intrinsic_name),
3344 "%s.%s.%s", base_name, atomic_name, coords_type);
3345 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3346 }
3347
3348 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3349 nir_intrinsic_instr *instr)
3350 {
3351 LLVMValueRef res;
3352 const nir_variable *var = instr->variables[0]->var;
3353 const struct glsl_type *type = instr->variables[0]->var->type;
3354 bool da = glsl_sampler_type_is_array(var->type) ||
3355 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3356 if(instr->variables[0]->deref.child)
3357 type = instr->variables[0]->deref.child->type;
3358
3359 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3360 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3361
3362 struct ac_image_args args = { 0 };
3363
3364 args.da = da;
3365 args.dmask = 0xf;
3366 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3367 args.opcode = ac_image_get_resinfo;
3368 args.addr = ctx->i32zero;
3369
3370 res = ac_build_image_opcode(&ctx->ac, &args);
3371
3372 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3373 glsl_sampler_type_is_array(type)) {
3374 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3375 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3376 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3377 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3378 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3379 }
3380 return res;
3381 }
3382
3383 #define NOOP_WAITCNT 0xf7f
3384 #define LGKM_CNT 0x07f
3385 #define VM_CNT 0xf70
3386
3387 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3388 unsigned simm16)
3389 {
3390 LLVMValueRef args[1] = {
3391 LLVMConstInt(ctx->i32, simm16, false),
3392 };
3393 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3394 ctx->voidt, args, 1, 0);
3395 }
3396
3397 static void emit_barrier(struct nir_to_llvm_context *ctx)
3398 {
3399 /* SI only (thanks to a hw bug workaround):
3400 * The real barrier instruction isn’t needed, because an entire patch
3401 * always fits into a single wave.
3402 */
3403 if (ctx->options->chip_class == SI &&
3404 ctx->stage == MESA_SHADER_TESS_CTRL) {
3405 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3406 return;
3407 }
3408 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3409 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3410 }
3411
3412 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3413 nir_intrinsic_instr *instr)
3414 {
3415 LLVMValueRef cond;
3416 ctx->shader_info->fs.can_discard = true;
3417
3418 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3419 get_src(ctx, instr->src[0]),
3420 ctx->i32zero, "");
3421
3422 cond = LLVMBuildSelect(ctx->builder, cond,
3423 LLVMConstReal(ctx->f32, -1.0f),
3424 ctx->f32zero, "");
3425 ac_build_kill(&ctx->ac, cond);
3426 }
3427
3428 static LLVMValueRef
3429 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3430 {
3431 LLVMValueRef result;
3432 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3433 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3434 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3435
3436 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3437 }
3438
3439 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3440 nir_intrinsic_instr *instr)
3441 {
3442 LLVMValueRef ptr, result;
3443 int idx = instr->variables[0]->var->data.driver_location;
3444 LLVMValueRef src = get_src(ctx, instr->src[0]);
3445 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3446
3447 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3448 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3449 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3450 ptr, src, src1,
3451 LLVMAtomicOrderingSequentiallyConsistent,
3452 LLVMAtomicOrderingSequentiallyConsistent,
3453 false);
3454 } else {
3455 LLVMAtomicRMWBinOp op;
3456 switch (instr->intrinsic) {
3457 case nir_intrinsic_var_atomic_add:
3458 op = LLVMAtomicRMWBinOpAdd;
3459 break;
3460 case nir_intrinsic_var_atomic_umin:
3461 op = LLVMAtomicRMWBinOpUMin;
3462 break;
3463 case nir_intrinsic_var_atomic_umax:
3464 op = LLVMAtomicRMWBinOpUMax;
3465 break;
3466 case nir_intrinsic_var_atomic_imin:
3467 op = LLVMAtomicRMWBinOpMin;
3468 break;
3469 case nir_intrinsic_var_atomic_imax:
3470 op = LLVMAtomicRMWBinOpMax;
3471 break;
3472 case nir_intrinsic_var_atomic_and:
3473 op = LLVMAtomicRMWBinOpAnd;
3474 break;
3475 case nir_intrinsic_var_atomic_or:
3476 op = LLVMAtomicRMWBinOpOr;
3477 break;
3478 case nir_intrinsic_var_atomic_xor:
3479 op = LLVMAtomicRMWBinOpXor;
3480 break;
3481 case nir_intrinsic_var_atomic_exchange:
3482 op = LLVMAtomicRMWBinOpXchg;
3483 break;
3484 default:
3485 return NULL;
3486 }
3487
3488 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3489 LLVMAtomicOrderingSequentiallyConsistent,
3490 false);
3491 }
3492 return result;
3493 }
3494
3495 #define INTERP_CENTER 0
3496 #define INTERP_CENTROID 1
3497 #define INTERP_SAMPLE 2
3498
3499 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3500 enum glsl_interp_mode interp, unsigned location)
3501 {
3502 switch (interp) {
3503 case INTERP_MODE_FLAT:
3504 default:
3505 return NULL;
3506 case INTERP_MODE_SMOOTH:
3507 case INTERP_MODE_NONE:
3508 if (location == INTERP_CENTER)
3509 return ctx->persp_center;
3510 else if (location == INTERP_CENTROID)
3511 return ctx->persp_centroid;
3512 else if (location == INTERP_SAMPLE)
3513 return ctx->persp_sample;
3514 break;
3515 case INTERP_MODE_NOPERSPECTIVE:
3516 if (location == INTERP_CENTER)
3517 return ctx->linear_center;
3518 else if (location == INTERP_CENTROID)
3519 return ctx->linear_centroid;
3520 else if (location == INTERP_SAMPLE)
3521 return ctx->linear_sample;
3522 break;
3523 }
3524 return NULL;
3525 }
3526
3527 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3528 LLVMValueRef sample_id)
3529 {
3530 LLVMValueRef result;
3531 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3532
3533 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3534 const_array(ctx->v2f32, 64), "");
3535
3536 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3537 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3538
3539 return result;
3540 }
3541
3542 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3543 {
3544 LLVMValueRef values[2];
3545
3546 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3547 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3548 return ac_build_gather_values(&ctx->ac, values, 2);
3549 }
3550
3551 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3552 nir_intrinsic_instr *instr)
3553 {
3554 LLVMValueRef result[2];
3555 LLVMValueRef interp_param, attr_number;
3556 unsigned location;
3557 unsigned chan;
3558 LLVMValueRef src_c0, src_c1;
3559 LLVMValueRef src0;
3560 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3561 switch (instr->intrinsic) {
3562 case nir_intrinsic_interp_var_at_centroid:
3563 location = INTERP_CENTROID;
3564 break;
3565 case nir_intrinsic_interp_var_at_sample:
3566 case nir_intrinsic_interp_var_at_offset:
3567 location = INTERP_CENTER;
3568 src0 = get_src(ctx, instr->src[0]);
3569 break;
3570 default:
3571 break;
3572 }
3573
3574 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3575 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3576 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3577 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3578 LLVMValueRef sample_position;
3579 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3580
3581 /* fetch sample ID */
3582 sample_position = load_sample_position(ctx, src0);
3583
3584 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3585 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3586 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3587 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3588 }
3589 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3590 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3591
3592 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3593 LLVMValueRef ij_out[2];
3594 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3595
3596 /*
3597 * take the I then J parameters, and the DDX/Y for it, and
3598 * calculate the IJ inputs for the interpolator.
3599 * temp1 = ddx * offset/sample.x + I;
3600 * interp_param.I = ddy * offset/sample.y + temp1;
3601 * temp1 = ddx * offset/sample.x + J;
3602 * interp_param.J = ddy * offset/sample.y + temp1;
3603 */
3604 for (unsigned i = 0; i < 2; i++) {
3605 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3606 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3607 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3608 ddxy_out, ix_ll, "");
3609 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3610 ddxy_out, iy_ll, "");
3611 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3612 interp_param, ix_ll, "");
3613 LLVMValueRef temp1, temp2;
3614
3615 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3616 ctx->f32, "");
3617
3618 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3619 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3620
3621 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3622 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3623
3624 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3625 temp2, ctx->i32, "");
3626 }
3627 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3628
3629 }
3630
3631 for (chan = 0; chan < 2; chan++) {
3632 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3633
3634 if (interp_param) {
3635 interp_param = LLVMBuildBitCast(ctx->builder,
3636 interp_param, LLVMVectorType(ctx->f32, 2), "");
3637 LLVMValueRef i = LLVMBuildExtractElement(
3638 ctx->builder, interp_param, ctx->i32zero, "");
3639 LLVMValueRef j = LLVMBuildExtractElement(
3640 ctx->builder, interp_param, ctx->i32one, "");
3641
3642 result[chan] = ac_build_fs_interp(&ctx->ac,
3643 llvm_chan, attr_number,
3644 ctx->prim_mask, i, j);
3645 } else {
3646 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3647 LLVMConstInt(ctx->i32, 2, false),
3648 llvm_chan, attr_number,
3649 ctx->prim_mask);
3650 }
3651 }
3652 return ac_build_gather_values(&ctx->ac, result, 2);
3653 }
3654
3655 static void
3656 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3657 nir_intrinsic_instr *instr)
3658 {
3659 LLVMValueRef gs_next_vertex;
3660 LLVMValueRef can_emit, kill;
3661 int idx;
3662
3663 assert(instr->const_index[0] == 0);
3664 /* Write vertex attribute values to GSVS ring */
3665 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3666 ctx->gs_next_vertex,
3667 "");
3668
3669 /* If this thread has already emitted the declared maximum number of
3670 * vertices, kill it: excessive vertex emissions are not supposed to
3671 * have any effect, and GS threads have no externally observable
3672 * effects other than emitting vertices.
3673 */
3674 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3675 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3676
3677 kill = LLVMBuildSelect(ctx->builder, can_emit,
3678 LLVMConstReal(ctx->f32, 1.0f),
3679 LLVMConstReal(ctx->f32, -1.0f), "");
3680 ac_build_kill(&ctx->ac, kill);
3681
3682 /* loop num outputs */
3683 idx = 0;
3684 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3685 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3686 int length = 4;
3687 int slot = idx;
3688 int slot_inc = 1;
3689
3690 if (!(ctx->output_mask & (1ull << i)))
3691 continue;
3692
3693 if (i == VARYING_SLOT_CLIP_DIST0) {
3694 /* pack clip and cull into a single set of slots */
3695 length = ctx->num_output_clips + ctx->num_output_culls;
3696 if (length > 4)
3697 slot_inc = 2;
3698 }
3699 for (unsigned j = 0; j < length; j++) {
3700 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3701 out_ptr[j], "");
3702 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3703 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3704 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3705
3706 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3707
3708 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3709 out_val, 1,
3710 voffset, ctx->gs2vs_offset, 0,
3711 1, 1, true, true);
3712 }
3713 idx += slot_inc;
3714 }
3715
3716 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3717 ctx->i32one, "");
3718 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3719
3720 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3721 }
3722
3723 static void
3724 visit_end_primitive(struct nir_to_llvm_context *ctx,
3725 nir_intrinsic_instr *instr)
3726 {
3727 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3728 }
3729
3730 static LLVMValueRef
3731 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3732 nir_intrinsic_instr *instr)
3733 {
3734 LLVMValueRef coord[4] = {
3735 ctx->tes_u,
3736 ctx->tes_v,
3737 ctx->f32zero,
3738 ctx->f32zero,
3739 };
3740
3741 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3742 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3743 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3744
3745 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3746 return LLVMBuildBitCast(ctx->builder, result,
3747 get_def_type(ctx, &instr->dest.ssa), "");
3748 }
3749
3750 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3751 nir_intrinsic_instr *instr)
3752 {
3753 LLVMValueRef result = NULL;
3754
3755 switch (instr->intrinsic) {
3756 case nir_intrinsic_load_work_group_id: {
3757 result = ctx->workgroup_ids;
3758 break;
3759 }
3760 case nir_intrinsic_load_base_vertex: {
3761 result = ctx->base_vertex;
3762 break;
3763 }
3764 case nir_intrinsic_load_vertex_id_zero_base: {
3765 result = ctx->vertex_id;
3766 break;
3767 }
3768 case nir_intrinsic_load_local_invocation_id: {
3769 result = ctx->local_invocation_ids;
3770 break;
3771 }
3772 case nir_intrinsic_load_base_instance:
3773 result = ctx->start_instance;
3774 break;
3775 case nir_intrinsic_load_draw_id:
3776 result = ctx->draw_index;
3777 break;
3778 case nir_intrinsic_load_invocation_id:
3779 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3780 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3781 else
3782 result = ctx->gs_invocation_id;
3783 break;
3784 case nir_intrinsic_load_primitive_id:
3785 if (ctx->stage == MESA_SHADER_GEOMETRY)
3786 result = ctx->gs_prim_id;
3787 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3788 result = ctx->tcs_patch_id;
3789 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3790 result = ctx->tes_patch_id;
3791 else
3792 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3793 break;
3794 case nir_intrinsic_load_sample_id:
3795 ctx->shader_info->fs.force_persample = true;
3796 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3797 break;
3798 case nir_intrinsic_load_sample_pos:
3799 ctx->shader_info->fs.force_persample = true;
3800 result = load_sample_pos(ctx);
3801 break;
3802 case nir_intrinsic_load_sample_mask_in:
3803 result = ctx->sample_coverage;
3804 break;
3805 case nir_intrinsic_load_front_face:
3806 result = ctx->front_face;
3807 break;
3808 case nir_intrinsic_load_instance_id:
3809 result = ctx->instance_id;
3810 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3811 ctx->shader_info->vs.vgpr_comp_cnt);
3812 break;
3813 case nir_intrinsic_load_num_work_groups:
3814 result = ctx->num_work_groups;
3815 break;
3816 case nir_intrinsic_load_local_invocation_index:
3817 result = visit_load_local_invocation_index(ctx);
3818 break;
3819 case nir_intrinsic_load_push_constant:
3820 result = visit_load_push_constant(ctx, instr);
3821 break;
3822 case nir_intrinsic_vulkan_resource_index:
3823 result = visit_vulkan_resource_index(ctx, instr);
3824 break;
3825 case nir_intrinsic_store_ssbo:
3826 visit_store_ssbo(ctx, instr);
3827 break;
3828 case nir_intrinsic_load_ssbo:
3829 result = visit_load_buffer(ctx, instr);
3830 break;
3831 case nir_intrinsic_ssbo_atomic_add:
3832 case nir_intrinsic_ssbo_atomic_imin:
3833 case nir_intrinsic_ssbo_atomic_umin:
3834 case nir_intrinsic_ssbo_atomic_imax:
3835 case nir_intrinsic_ssbo_atomic_umax:
3836 case nir_intrinsic_ssbo_atomic_and:
3837 case nir_intrinsic_ssbo_atomic_or:
3838 case nir_intrinsic_ssbo_atomic_xor:
3839 case nir_intrinsic_ssbo_atomic_exchange:
3840 case nir_intrinsic_ssbo_atomic_comp_swap:
3841 result = visit_atomic_ssbo(ctx, instr);
3842 break;
3843 case nir_intrinsic_load_ubo:
3844 result = visit_load_ubo_buffer(ctx, instr);
3845 break;
3846 case nir_intrinsic_get_buffer_size:
3847 result = visit_get_buffer_size(ctx, instr);
3848 break;
3849 case nir_intrinsic_load_var:
3850 result = visit_load_var(ctx, instr);
3851 break;
3852 case nir_intrinsic_store_var:
3853 visit_store_var(ctx, instr);
3854 break;
3855 case nir_intrinsic_image_load:
3856 result = visit_image_load(ctx, instr);
3857 break;
3858 case nir_intrinsic_image_store:
3859 visit_image_store(ctx, instr);
3860 break;
3861 case nir_intrinsic_image_atomic_add:
3862 case nir_intrinsic_image_atomic_min:
3863 case nir_intrinsic_image_atomic_max:
3864 case nir_intrinsic_image_atomic_and:
3865 case nir_intrinsic_image_atomic_or:
3866 case nir_intrinsic_image_atomic_xor:
3867 case nir_intrinsic_image_atomic_exchange:
3868 case nir_intrinsic_image_atomic_comp_swap:
3869 result = visit_image_atomic(ctx, instr);
3870 break;
3871 case nir_intrinsic_image_size:
3872 result = visit_image_size(ctx, instr);
3873 break;
3874 case nir_intrinsic_discard:
3875 ctx->shader_info->fs.can_discard = true;
3876 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3877 ctx->voidt,
3878 NULL, 0, AC_FUNC_ATTR_LEGACY);
3879 break;
3880 case nir_intrinsic_discard_if:
3881 emit_discard_if(ctx, instr);
3882 break;
3883 case nir_intrinsic_memory_barrier:
3884 emit_waitcnt(ctx, VM_CNT);
3885 break;
3886 case nir_intrinsic_barrier:
3887 emit_barrier(ctx);
3888 break;
3889 case nir_intrinsic_var_atomic_add:
3890 case nir_intrinsic_var_atomic_imin:
3891 case nir_intrinsic_var_atomic_umin:
3892 case nir_intrinsic_var_atomic_imax:
3893 case nir_intrinsic_var_atomic_umax:
3894 case nir_intrinsic_var_atomic_and:
3895 case nir_intrinsic_var_atomic_or:
3896 case nir_intrinsic_var_atomic_xor:
3897 case nir_intrinsic_var_atomic_exchange:
3898 case nir_intrinsic_var_atomic_comp_swap:
3899 result = visit_var_atomic(ctx, instr);
3900 break;
3901 case nir_intrinsic_interp_var_at_centroid:
3902 case nir_intrinsic_interp_var_at_sample:
3903 case nir_intrinsic_interp_var_at_offset:
3904 result = visit_interp(ctx, instr);
3905 break;
3906 case nir_intrinsic_emit_vertex:
3907 visit_emit_vertex(ctx, instr);
3908 break;
3909 case nir_intrinsic_end_primitive:
3910 visit_end_primitive(ctx, instr);
3911 break;
3912 case nir_intrinsic_load_tess_coord:
3913 result = visit_load_tess_coord(ctx, instr);
3914 break;
3915 case nir_intrinsic_load_patch_vertices_in:
3916 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
3917 break;
3918 default:
3919 fprintf(stderr, "Unknown intrinsic: ");
3920 nir_print_instr(&instr->instr, stderr);
3921 fprintf(stderr, "\n");
3922 break;
3923 }
3924 if (result) {
3925 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3926 }
3927 }
3928
3929 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3930 nir_deref_var *deref,
3931 enum desc_type desc_type)
3932 {
3933 unsigned desc_set = deref->var->data.descriptor_set;
3934 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3935 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3936 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3937 unsigned offset = binding->offset;
3938 unsigned stride = binding->size;
3939 unsigned type_size;
3940 LLVMBuilderRef builder = ctx->builder;
3941 LLVMTypeRef type;
3942 LLVMValueRef index = NULL;
3943 unsigned constant_index = 0;
3944
3945 assert(deref->var->data.binding < layout->binding_count);
3946
3947 switch (desc_type) {
3948 case DESC_IMAGE:
3949 type = ctx->v8i32;
3950 type_size = 32;
3951 break;
3952 case DESC_FMASK:
3953 type = ctx->v8i32;
3954 offset += 32;
3955 type_size = 32;
3956 break;
3957 case DESC_SAMPLER:
3958 type = ctx->v4i32;
3959 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3960 offset += 64;
3961
3962 type_size = 16;
3963 break;
3964 case DESC_BUFFER:
3965 type = ctx->v4i32;
3966 type_size = 16;
3967 break;
3968 default:
3969 unreachable("invalid desc_type\n");
3970 }
3971
3972 if (deref->deref.child) {
3973 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3974
3975 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3976 offset += child->base_offset * stride;
3977 if (child->deref_array_type == nir_deref_array_type_indirect) {
3978 index = get_src(ctx, child->indirect);
3979 }
3980
3981 constant_index = child->base_offset;
3982 }
3983 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
3984 (!index || binding->immutable_samplers_equal)) {
3985 if (binding->immutable_samplers_equal)
3986 constant_index = 0;
3987
3988 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
3989
3990 LLVMValueRef constants[] = {
3991 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
3992 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
3993 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
3994 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
3995 };
3996 return ac_build_gather_values(&ctx->ac, constants, 4);
3997 }
3998
3999 assert(stride % type_size == 0);
4000
4001 if (!index)
4002 index = ctx->i32zero;
4003
4004 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4005
4006 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4007 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4008
4009 return ac_build_indexed_load_const(&ctx->ac, list, index);
4010 }
4011
4012 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4013 struct ac_image_args *args,
4014 nir_tex_instr *instr,
4015 nir_texop op,
4016 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4017 LLVMValueRef *param, unsigned count,
4018 unsigned dmask)
4019 {
4020 unsigned is_rect = 0;
4021 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4022
4023 if (op == nir_texop_lod)
4024 da = false;
4025 /* Pad to power of two vector */
4026 while (count < util_next_power_of_two(count))
4027 param[count++] = LLVMGetUndef(ctx->i32);
4028
4029 if (count > 1)
4030 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4031 else
4032 args->addr = param[0];
4033
4034 args->resource = res_ptr;
4035 args->sampler = samp_ptr;
4036
4037 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4038 args->addr = param[0];
4039 return;
4040 }
4041
4042 args->dmask = dmask;
4043 args->unorm = is_rect;
4044 args->da = da;
4045 }
4046
4047 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4048 *
4049 * SI-CI:
4050 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4051 * filtering manually. The driver sets img7 to a mask clearing
4052 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4053 * s_and_b32 samp0, samp0, img7
4054 *
4055 * VI:
4056 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4057 */
4058 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4059 LLVMValueRef res, LLVMValueRef samp)
4060 {
4061 LLVMBuilderRef builder = ctx->builder;
4062 LLVMValueRef img7, samp0;
4063
4064 if (ctx->options->chip_class >= VI)
4065 return samp;
4066
4067 img7 = LLVMBuildExtractElement(builder, res,
4068 LLVMConstInt(ctx->i32, 7, 0), "");
4069 samp0 = LLVMBuildExtractElement(builder, samp,
4070 LLVMConstInt(ctx->i32, 0, 0), "");
4071 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4072 return LLVMBuildInsertElement(builder, samp, samp0,
4073 LLVMConstInt(ctx->i32, 0, 0), "");
4074 }
4075
4076 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4077 nir_tex_instr *instr,
4078 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4079 LLVMValueRef *fmask_ptr)
4080 {
4081 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4082 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4083 else
4084 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4085 if (samp_ptr) {
4086 if (instr->sampler)
4087 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4088 else
4089 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4090 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4091 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4092 }
4093 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4094 instr->op == nir_texop_samples_identical))
4095 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4096 }
4097
4098 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4099 LLVMValueRef coord)
4100 {
4101 coord = to_float(ctx, coord);
4102 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4103 coord = to_integer(ctx, coord);
4104 return coord;
4105 }
4106
4107 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4108 {
4109 LLVMValueRef result = NULL;
4110 struct ac_image_args args = { 0 };
4111 unsigned dmask = 0xf;
4112 LLVMValueRef address[16];
4113 LLVMValueRef coords[5];
4114 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4115 LLVMValueRef bias = NULL, offsets = NULL;
4116 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4117 LLVMValueRef ddx = NULL, ddy = NULL;
4118 LLVMValueRef derivs[6];
4119 unsigned chan, count = 0;
4120 unsigned const_src = 0, num_deriv_comp = 0;
4121
4122 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4123
4124 for (unsigned i = 0; i < instr->num_srcs; i++) {
4125 switch (instr->src[i].src_type) {
4126 case nir_tex_src_coord:
4127 coord = get_src(ctx, instr->src[i].src);
4128 break;
4129 case nir_tex_src_projector:
4130 break;
4131 case nir_tex_src_comparator:
4132 comparator = get_src(ctx, instr->src[i].src);
4133 break;
4134 case nir_tex_src_offset:
4135 offsets = get_src(ctx, instr->src[i].src);
4136 const_src = i;
4137 break;
4138 case nir_tex_src_bias:
4139 bias = get_src(ctx, instr->src[i].src);
4140 break;
4141 case nir_tex_src_lod:
4142 lod = get_src(ctx, instr->src[i].src);
4143 break;
4144 case nir_tex_src_ms_index:
4145 sample_index = get_src(ctx, instr->src[i].src);
4146 break;
4147 case nir_tex_src_ms_mcs:
4148 break;
4149 case nir_tex_src_ddx:
4150 ddx = get_src(ctx, instr->src[i].src);
4151 num_deriv_comp = instr->src[i].src.ssa->num_components;
4152 break;
4153 case nir_tex_src_ddy:
4154 ddy = get_src(ctx, instr->src[i].src);
4155 break;
4156 case nir_tex_src_texture_offset:
4157 case nir_tex_src_sampler_offset:
4158 case nir_tex_src_plane:
4159 default:
4160 break;
4161 }
4162 }
4163
4164 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4165 result = get_buffer_size(ctx, res_ptr, true);
4166 goto write_result;
4167 }
4168
4169 if (instr->op == nir_texop_texture_samples) {
4170 LLVMValueRef res, samples, is_msaa;
4171 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4172 samples = LLVMBuildExtractElement(ctx->builder, res,
4173 LLVMConstInt(ctx->i32, 3, false), "");
4174 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4175 LLVMConstInt(ctx->i32, 28, false), "");
4176 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4177 LLVMConstInt(ctx->i32, 0xe, false), "");
4178 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4179 LLVMConstInt(ctx->i32, 0xe, false), "");
4180
4181 samples = LLVMBuildLShr(ctx->builder, samples,
4182 LLVMConstInt(ctx->i32, 16, false), "");
4183 samples = LLVMBuildAnd(ctx->builder, samples,
4184 LLVMConstInt(ctx->i32, 0xf, false), "");
4185 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4186 samples, "");
4187 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4188 ctx->i32one, "");
4189 result = samples;
4190 goto write_result;
4191 }
4192
4193 if (coord)
4194 for (chan = 0; chan < instr->coord_components; chan++)
4195 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4196
4197 if (offsets && instr->op != nir_texop_txf) {
4198 LLVMValueRef offset[3], pack;
4199 for (chan = 0; chan < 3; ++chan)
4200 offset[chan] = ctx->i32zero;
4201
4202 args.offset = true;
4203 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4204 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4205 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4206 LLVMConstInt(ctx->i32, 0x3f, false), "");
4207 if (chan)
4208 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4209 LLVMConstInt(ctx->i32, chan * 8, false), "");
4210 }
4211 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4212 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4213 address[count++] = pack;
4214
4215 }
4216 /* pack LOD bias value */
4217 if (instr->op == nir_texop_txb && bias) {
4218 address[count++] = bias;
4219 }
4220
4221 /* Pack depth comparison value */
4222 if (instr->is_shadow && comparator) {
4223 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4224 }
4225
4226 /* pack derivatives */
4227 if (ddx || ddy) {
4228 switch (instr->sampler_dim) {
4229 case GLSL_SAMPLER_DIM_3D:
4230 case GLSL_SAMPLER_DIM_CUBE:
4231 num_deriv_comp = 3;
4232 break;
4233 case GLSL_SAMPLER_DIM_2D:
4234 default:
4235 num_deriv_comp = 2;
4236 break;
4237 case GLSL_SAMPLER_DIM_1D:
4238 num_deriv_comp = 1;
4239 break;
4240 }
4241
4242 for (unsigned i = 0; i < num_deriv_comp; i++) {
4243 derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4244 derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4245 }
4246 }
4247
4248 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4249 if (instr->is_array && instr->op != nir_texop_lod)
4250 coords[3] = apply_round_slice(ctx, coords[3]);
4251 for (chan = 0; chan < instr->coord_components; chan++)
4252 coords[chan] = to_float(ctx, coords[chan]);
4253 if (instr->coord_components == 3)
4254 coords[3] = LLVMGetUndef(ctx->f32);
4255 ac_prepare_cube_coords(&ctx->ac,
4256 instr->op == nir_texop_txd, instr->is_array,
4257 coords, derivs);
4258 if (num_deriv_comp)
4259 num_deriv_comp--;
4260 }
4261
4262 if (ddx || ddy) {
4263 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4264 address[count++] = derivs[i];
4265 }
4266
4267 /* Pack texture coordinates */
4268 if (coord) {
4269 address[count++] = coords[0];
4270 if (instr->coord_components > 1) {
4271 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4272 coords[1] = apply_round_slice(ctx, coords[1]);
4273 }
4274 address[count++] = coords[1];
4275 }
4276 if (instr->coord_components > 2) {
4277 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4278 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4279 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4280 instr->op != nir_texop_txf) {
4281 coords[2] = apply_round_slice(ctx, coords[2]);
4282 }
4283 address[count++] = coords[2];
4284 }
4285 }
4286
4287 /* Pack LOD */
4288 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
4289 address[count++] = lod;
4290 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4291 address[count++] = sample_index;
4292 } else if(instr->op == nir_texop_txs) {
4293 count = 0;
4294 if (lod)
4295 address[count++] = lod;
4296 else
4297 address[count++] = ctx->i32zero;
4298 }
4299
4300 for (chan = 0; chan < count; chan++) {
4301 address[chan] = LLVMBuildBitCast(ctx->builder,
4302 address[chan], ctx->i32, "");
4303 }
4304
4305 if (instr->op == nir_texop_samples_identical) {
4306 LLVMValueRef txf_address[4];
4307 struct ac_image_args txf_args = { 0 };
4308 unsigned txf_count = count;
4309 memcpy(txf_address, address, sizeof(txf_address));
4310
4311 if (!instr->is_array)
4312 txf_address[2] = ctx->i32zero;
4313 txf_address[3] = ctx->i32zero;
4314
4315 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4316 fmask_ptr, NULL,
4317 txf_address, txf_count, 0xf);
4318
4319 result = build_tex_intrinsic(ctx, instr, &txf_args);
4320
4321 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4322 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4323 goto write_result;
4324 }
4325
4326 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4327 instr->op != nir_texop_txs) {
4328 unsigned sample_chan = instr->is_array ? 3 : 2;
4329 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4330 address[0],
4331 address[1],
4332 instr->is_array ? address[2] : NULL,
4333 address[sample_chan],
4334 fmask_ptr);
4335 }
4336
4337 if (offsets && instr->op == nir_texop_txf) {
4338 nir_const_value *const_offset =
4339 nir_src_as_const_value(instr->src[const_src].src);
4340 int num_offsets = instr->src[const_src].src.ssa->num_components;
4341 assert(const_offset);
4342 num_offsets = MIN2(num_offsets, instr->coord_components);
4343 if (num_offsets > 2)
4344 address[2] = LLVMBuildAdd(ctx->builder,
4345 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4346 if (num_offsets > 1)
4347 address[1] = LLVMBuildAdd(ctx->builder,
4348 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4349 address[0] = LLVMBuildAdd(ctx->builder,
4350 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4351
4352 }
4353
4354 /* TODO TG4 support */
4355 if (instr->op == nir_texop_tg4) {
4356 if (instr->is_shadow)
4357 dmask = 1;
4358 else
4359 dmask = 1 << instr->component;
4360 }
4361 set_tex_fetch_args(ctx, &args, instr, instr->op,
4362 res_ptr, samp_ptr, address, count, dmask);
4363
4364 result = build_tex_intrinsic(ctx, instr, &args);
4365
4366 if (instr->op == nir_texop_query_levels)
4367 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4368 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4369 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4370 else if (instr->op == nir_texop_txs &&
4371 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4372 instr->is_array) {
4373 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4374 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4375 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4376 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4377 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4378 } else if (instr->dest.ssa.num_components != 4)
4379 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4380
4381 write_result:
4382 if (result) {
4383 assert(instr->dest.is_ssa);
4384 result = to_integer(ctx, result);
4385 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4386 }
4387 }
4388
4389
4390 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4391 {
4392 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4393 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4394
4395 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4396 _mesa_hash_table_insert(ctx->phis, instr, result);
4397 }
4398
4399 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4400 nir_phi_instr *instr,
4401 LLVMValueRef llvm_phi)
4402 {
4403 nir_foreach_phi_src(src, instr) {
4404 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4405 LLVMValueRef llvm_src = get_src(ctx, src->src);
4406
4407 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4408 }
4409 }
4410
4411 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4412 {
4413 struct hash_entry *entry;
4414 hash_table_foreach(ctx->phis, entry) {
4415 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4416 (LLVMValueRef)entry->data);
4417 }
4418 }
4419
4420
4421 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4422 nir_ssa_undef_instr *instr)
4423 {
4424 unsigned num_components = instr->def.num_components;
4425 LLVMValueRef undef;
4426
4427 if (num_components == 1)
4428 undef = LLVMGetUndef(ctx->i32);
4429 else {
4430 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4431 }
4432 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4433 }
4434
4435 static void visit_jump(struct nir_to_llvm_context *ctx,
4436 nir_jump_instr *instr)
4437 {
4438 switch (instr->type) {
4439 case nir_jump_break:
4440 LLVMBuildBr(ctx->builder, ctx->break_block);
4441 LLVMClearInsertionPosition(ctx->builder);
4442 break;
4443 case nir_jump_continue:
4444 LLVMBuildBr(ctx->builder, ctx->continue_block);
4445 LLVMClearInsertionPosition(ctx->builder);
4446 break;
4447 default:
4448 fprintf(stderr, "Unknown NIR jump instr: ");
4449 nir_print_instr(&instr->instr, stderr);
4450 fprintf(stderr, "\n");
4451 abort();
4452 }
4453 }
4454
4455 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4456 struct exec_list *list);
4457
4458 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4459 {
4460 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4461 nir_foreach_instr(instr, block)
4462 {
4463 switch (instr->type) {
4464 case nir_instr_type_alu:
4465 visit_alu(ctx, nir_instr_as_alu(instr));
4466 break;
4467 case nir_instr_type_load_const:
4468 visit_load_const(ctx, nir_instr_as_load_const(instr));
4469 break;
4470 case nir_instr_type_intrinsic:
4471 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4472 break;
4473 case nir_instr_type_tex:
4474 visit_tex(ctx, nir_instr_as_tex(instr));
4475 break;
4476 case nir_instr_type_phi:
4477 visit_phi(ctx, nir_instr_as_phi(instr));
4478 break;
4479 case nir_instr_type_ssa_undef:
4480 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4481 break;
4482 case nir_instr_type_jump:
4483 visit_jump(ctx, nir_instr_as_jump(instr));
4484 break;
4485 default:
4486 fprintf(stderr, "Unknown NIR instr type: ");
4487 nir_print_instr(instr, stderr);
4488 fprintf(stderr, "\n");
4489 abort();
4490 }
4491 }
4492
4493 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4494 }
4495
4496 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4497 {
4498 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4499
4500 LLVMBasicBlockRef merge_block =
4501 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4502 LLVMBasicBlockRef if_block =
4503 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4504 LLVMBasicBlockRef else_block = merge_block;
4505 if (!exec_list_is_empty(&if_stmt->else_list))
4506 else_block = LLVMAppendBasicBlockInContext(
4507 ctx->context, ctx->main_function, "");
4508
4509 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4510 LLVMConstInt(ctx->i32, 0, false), "");
4511 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4512
4513 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4514 visit_cf_list(ctx, &if_stmt->then_list);
4515 if (LLVMGetInsertBlock(ctx->builder))
4516 LLVMBuildBr(ctx->builder, merge_block);
4517
4518 if (!exec_list_is_empty(&if_stmt->else_list)) {
4519 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4520 visit_cf_list(ctx, &if_stmt->else_list);
4521 if (LLVMGetInsertBlock(ctx->builder))
4522 LLVMBuildBr(ctx->builder, merge_block);
4523 }
4524
4525 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4526 }
4527
4528 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4529 {
4530 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4531 LLVMBasicBlockRef break_parent = ctx->break_block;
4532
4533 ctx->continue_block =
4534 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4535 ctx->break_block =
4536 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4537
4538 LLVMBuildBr(ctx->builder, ctx->continue_block);
4539 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4540 visit_cf_list(ctx, &loop->body);
4541
4542 if (LLVMGetInsertBlock(ctx->builder))
4543 LLVMBuildBr(ctx->builder, ctx->continue_block);
4544 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4545
4546 ctx->continue_block = continue_parent;
4547 ctx->break_block = break_parent;
4548 }
4549
4550 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4551 struct exec_list *list)
4552 {
4553 foreach_list_typed(nir_cf_node, node, node, list)
4554 {
4555 switch (node->type) {
4556 case nir_cf_node_block:
4557 visit_block(ctx, nir_cf_node_as_block(node));
4558 break;
4559
4560 case nir_cf_node_if:
4561 visit_if(ctx, nir_cf_node_as_if(node));
4562 break;
4563
4564 case nir_cf_node_loop:
4565 visit_loop(ctx, nir_cf_node_as_loop(node));
4566 break;
4567
4568 default:
4569 assert(0);
4570 }
4571 }
4572 }
4573
4574 static void
4575 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4576 struct nir_variable *variable)
4577 {
4578 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4579 LLVMValueRef t_offset;
4580 LLVMValueRef t_list;
4581 LLVMValueRef input;
4582 LLVMValueRef buffer_index;
4583 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4584 int idx = variable->data.location;
4585 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4586
4587 variable->data.driver_location = idx * 4;
4588
4589 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4590 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4591 ctx->start_instance, "");
4592 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4593 ctx->shader_info->vs.vgpr_comp_cnt);
4594 } else
4595 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4596 ctx->base_vertex, "");
4597
4598 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4599 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4600
4601 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4602
4603 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4604 buffer_index,
4605 LLVMConstInt(ctx->i32, 0, false),
4606 true);
4607
4608 for (unsigned chan = 0; chan < 4; chan++) {
4609 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4610 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4611 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4612 input, llvm_chan, ""));
4613 }
4614 }
4615 }
4616
4617 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4618 unsigned attr,
4619 LLVMValueRef interp_param,
4620 LLVMValueRef prim_mask,
4621 LLVMValueRef result[4])
4622 {
4623 LLVMValueRef attr_number;
4624 unsigned chan;
4625 LLVMValueRef i, j;
4626 bool interp = interp_param != NULL;
4627
4628 attr_number = LLVMConstInt(ctx->i32, attr, false);
4629
4630 /* fs.constant returns the param from the middle vertex, so it's not
4631 * really useful for flat shading. It's meant to be used for custom
4632 * interpolation (but the intrinsic can't fetch from the other two
4633 * vertices).
4634 *
4635 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4636 * to do the right thing. The only reason we use fs.constant is that
4637 * fs.interp cannot be used on integers, because they can be equal
4638 * to NaN.
4639 */
4640 if (interp) {
4641 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4642 LLVMVectorType(ctx->f32, 2), "");
4643
4644 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4645 ctx->i32zero, "");
4646 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4647 ctx->i32one, "");
4648 }
4649
4650 for (chan = 0; chan < 4; chan++) {
4651 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4652
4653 if (interp) {
4654 result[chan] = ac_build_fs_interp(&ctx->ac,
4655 llvm_chan,
4656 attr_number,
4657 prim_mask, i, j);
4658 } else {
4659 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4660 LLVMConstInt(ctx->i32, 2, false),
4661 llvm_chan,
4662 attr_number,
4663 prim_mask);
4664 }
4665 }
4666 }
4667
4668 static void
4669 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4670 struct nir_variable *variable)
4671 {
4672 int idx = variable->data.location;
4673 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4674 LLVMValueRef interp;
4675
4676 variable->data.driver_location = idx * 4;
4677 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4678
4679 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4680 unsigned interp_type;
4681 if (variable->data.sample) {
4682 interp_type = INTERP_SAMPLE;
4683 ctx->shader_info->fs.force_persample = true;
4684 } else if (variable->data.centroid)
4685 interp_type = INTERP_CENTROID;
4686 else
4687 interp_type = INTERP_CENTER;
4688
4689 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4690 } else
4691 interp = NULL;
4692
4693 for (unsigned i = 0; i < attrib_count; ++i)
4694 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4695
4696 }
4697
4698 static void
4699 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4700 struct nir_variable *variable)
4701 {
4702 switch (ctx->stage) {
4703 case MESA_SHADER_VERTEX:
4704 handle_vs_input_decl(ctx, variable);
4705 break;
4706 case MESA_SHADER_FRAGMENT:
4707 handle_fs_input_decl(ctx, variable);
4708 break;
4709 default:
4710 break;
4711 }
4712
4713 }
4714
4715 static void
4716 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4717 struct nir_shader *nir)
4718 {
4719 unsigned index = 0;
4720 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4721 LLVMValueRef interp_param;
4722 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4723
4724 if (!(ctx->input_mask & (1ull << i)))
4725 continue;
4726
4727 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4728 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4729 interp_param = *inputs;
4730 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4731 inputs);
4732
4733 if (!interp_param)
4734 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4735 ++index;
4736 } else if (i == VARYING_SLOT_POS) {
4737 for(int i = 0; i < 3; ++i)
4738 inputs[i] = ctx->frag_pos[i];
4739
4740 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4741 }
4742 }
4743 ctx->shader_info->fs.num_interp = index;
4744 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4745 ctx->shader_info->fs.has_pcoord = true;
4746 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4747 ctx->shader_info->fs.prim_id_input = true;
4748 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4749 ctx->shader_info->fs.layer_input = true;
4750 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4751 }
4752
4753 static LLVMValueRef
4754 ac_build_alloca(struct nir_to_llvm_context *ctx,
4755 LLVMTypeRef type,
4756 const char *name)
4757 {
4758 LLVMBuilderRef builder = ctx->builder;
4759 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4760 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4761 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4762 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4763 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4764 LLVMValueRef res;
4765
4766 if (first_instr) {
4767 LLVMPositionBuilderBefore(first_builder, first_instr);
4768 } else {
4769 LLVMPositionBuilderAtEnd(first_builder, first_block);
4770 }
4771
4772 res = LLVMBuildAlloca(first_builder, type, name);
4773 LLVMBuildStore(builder, LLVMConstNull(type), res);
4774
4775 LLVMDisposeBuilder(first_builder);
4776
4777 return res;
4778 }
4779
4780 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4781 LLVMTypeRef type,
4782 const char *name)
4783 {
4784 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4785 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4786 return ptr;
4787 }
4788
4789 static void
4790 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4791 struct nir_variable *variable)
4792 {
4793 int idx = variable->data.location + variable->data.index;
4794 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4795 uint64_t mask_attribs;
4796 variable->data.driver_location = idx * 4;
4797
4798 /* tess ctrl has it's own load/store paths for outputs */
4799 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4800 return;
4801
4802 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4803 if (ctx->stage == MESA_SHADER_VERTEX ||
4804 ctx->stage == MESA_SHADER_TESS_EVAL ||
4805 ctx->stage == MESA_SHADER_GEOMETRY) {
4806 if (idx == VARYING_SLOT_CLIP_DIST0) {
4807 int length = ctx->num_output_clips + ctx->num_output_culls;
4808 if (ctx->stage == MESA_SHADER_VERTEX) {
4809 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4810 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4811 }
4812 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4813 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4814 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4815 }
4816
4817 if (length > 4)
4818 attrib_count = 2;
4819 else
4820 attrib_count = 1;
4821 mask_attribs = 1ull << idx;
4822 }
4823 }
4824
4825 for (unsigned i = 0; i < attrib_count; ++i) {
4826 for (unsigned chan = 0; chan < 4; chan++) {
4827 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4828 si_build_alloca_undef(ctx, ctx->f32, "");
4829 }
4830 }
4831 ctx->output_mask |= mask_attribs;
4832 }
4833
4834 static void
4835 setup_locals(struct nir_to_llvm_context *ctx,
4836 struct nir_function *func)
4837 {
4838 int i, j;
4839 ctx->num_locals = 0;
4840 nir_foreach_variable(variable, &func->impl->locals) {
4841 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4842 variable->data.driver_location = ctx->num_locals * 4;
4843 ctx->num_locals += attrib_count;
4844 }
4845 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4846 if (!ctx->locals)
4847 return;
4848
4849 for (i = 0; i < ctx->num_locals; i++) {
4850 for (j = 0; j < 4; j++) {
4851 ctx->locals[i * 4 + j] =
4852 si_build_alloca_undef(ctx, ctx->f32, "temp");
4853 }
4854 }
4855 }
4856
4857 static LLVMValueRef
4858 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4859 {
4860 v = to_float(ctx, v);
4861 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4862 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4863 }
4864
4865
4866 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4867 LLVMValueRef src0, LLVMValueRef src1)
4868 {
4869 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4870 LLVMValueRef comp[2];
4871
4872 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4873 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4874 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4875 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4876 }
4877
4878 /* Initialize arguments for the shader export intrinsic */
4879 static void
4880 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4881 LLVMValueRef *values,
4882 unsigned target,
4883 struct ac_export_args *args)
4884 {
4885 /* Default is 0xf. Adjusted below depending on the format. */
4886 args->enabled_channels = 0xf;
4887
4888 /* Specify whether the EXEC mask represents the valid mask */
4889 args->valid_mask = 0;
4890
4891 /* Specify whether this is the last export */
4892 args->done = 0;
4893
4894 /* Specify the target we are exporting */
4895 args->target = target;
4896
4897 args->compr = false;
4898 args->out[0] = LLVMGetUndef(ctx->f32);
4899 args->out[1] = LLVMGetUndef(ctx->f32);
4900 args->out[2] = LLVMGetUndef(ctx->f32);
4901 args->out[3] = LLVMGetUndef(ctx->f32);
4902
4903 if (!values)
4904 return;
4905
4906 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4907 LLVMValueRef val[4];
4908 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4909 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4910 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4911
4912 switch(col_format) {
4913 case V_028714_SPI_SHADER_ZERO:
4914 args->enabled_channels = 0; /* writemask */
4915 args->target = V_008DFC_SQ_EXP_NULL;
4916 break;
4917
4918 case V_028714_SPI_SHADER_32_R:
4919 args->enabled_channels = 1;
4920 args->out[0] = values[0];
4921 break;
4922
4923 case V_028714_SPI_SHADER_32_GR:
4924 args->enabled_channels = 0x3;
4925 args->out[0] = values[0];
4926 args->out[1] = values[1];
4927 break;
4928
4929 case V_028714_SPI_SHADER_32_AR:
4930 args->enabled_channels = 0x9;
4931 args->out[0] = values[0];
4932 args->out[3] = values[3];
4933 break;
4934
4935 case V_028714_SPI_SHADER_FP16_ABGR:
4936 args->compr = 1;
4937
4938 for (unsigned chan = 0; chan < 2; chan++) {
4939 LLVMValueRef pack_args[2] = {
4940 values[2 * chan],
4941 values[2 * chan + 1]
4942 };
4943 LLVMValueRef packed;
4944
4945 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
4946 args->out[chan] = packed;
4947 }
4948 break;
4949
4950 case V_028714_SPI_SHADER_UNORM16_ABGR:
4951 for (unsigned chan = 0; chan < 4; chan++) {
4952 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
4953 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4954 LLVMConstReal(ctx->f32, 65535), "");
4955 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4956 LLVMConstReal(ctx->f32, 0.5), "");
4957 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4958 ctx->i32, "");
4959 }
4960
4961 args->compr = 1;
4962 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4963 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4964 break;
4965
4966 case V_028714_SPI_SHADER_SNORM16_ABGR:
4967 for (unsigned chan = 0; chan < 4; chan++) {
4968 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4969 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4970 LLVMConstReal(ctx->f32, 32767), "");
4971
4972 /* If positive, add 0.5, else add -0.5. */
4973 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4974 LLVMBuildSelect(ctx->builder,
4975 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4976 val[chan], ctx->f32zero, ""),
4977 LLVMConstReal(ctx->f32, 0.5),
4978 LLVMConstReal(ctx->f32, -0.5), ""), "");
4979 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4980 }
4981
4982 args->compr = 1;
4983 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4984 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4985 break;
4986
4987 case V_028714_SPI_SHADER_UINT16_ABGR: {
4988 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4989
4990 for (unsigned chan = 0; chan < 4; chan++) {
4991 val[chan] = to_integer(ctx, values[chan]);
4992 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4993 }
4994
4995 args->compr = 1;
4996 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
4997 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
4998 break;
4999 }
5000
5001 case V_028714_SPI_SHADER_SINT16_ABGR: {
5002 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5003 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5004
5005 /* Clamp. */
5006 for (unsigned chan = 0; chan < 4; chan++) {
5007 val[chan] = to_integer(ctx, values[chan]);
5008 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
5009 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
5010 }
5011
5012 args->compr = 1;
5013 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5014 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5015 break;
5016 }
5017
5018 default:
5019 case V_028714_SPI_SHADER_32_ABGR:
5020 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5021 break;
5022 }
5023 } else
5024 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5025
5026 for (unsigned i = 0; i < 4; ++i)
5027 args->out[i] = to_float(ctx, args->out[i]);
5028 }
5029
5030 static void
5031 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5032 struct ac_vs_output_info *outinfo)
5033 {
5034 uint32_t param_count = 0;
5035 unsigned target;
5036 unsigned pos_idx, num_pos_exports = 0;
5037 struct ac_export_args args, pos_args[4] = {};
5038 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5039 int i;
5040
5041 outinfo->prim_id_output = 0xffffffff;
5042 outinfo->layer_output = 0xffffffff;
5043 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5044 LLVMValueRef slots[8];
5045 unsigned j;
5046
5047 if (outinfo->cull_dist_mask)
5048 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5049
5050 i = VARYING_SLOT_CLIP_DIST0;
5051 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5052 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5053 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5054
5055 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5056 slots[i] = LLVMGetUndef(ctx->f32);
5057
5058 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5059 target = V_008DFC_SQ_EXP_POS + 3;
5060 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5061 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5062 &args, sizeof(args));
5063 }
5064
5065 target = V_008DFC_SQ_EXP_POS + 2;
5066 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5067 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5068 &args, sizeof(args));
5069
5070 }
5071
5072 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5073 LLVMValueRef values[4];
5074 if (!(ctx->output_mask & (1ull << i)))
5075 continue;
5076
5077 for (unsigned j = 0; j < 4; j++)
5078 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5079 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5080
5081 if (i == VARYING_SLOT_POS) {
5082 target = V_008DFC_SQ_EXP_POS;
5083 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5084 continue;
5085 } else if (i == VARYING_SLOT_PSIZ) {
5086 outinfo->writes_pointsize = true;
5087 psize_value = values[0];
5088 continue;
5089 } else if (i == VARYING_SLOT_LAYER) {
5090 outinfo->writes_layer = true;
5091 layer_value = values[0];
5092 outinfo->layer_output = param_count;
5093 target = V_008DFC_SQ_EXP_PARAM + param_count;
5094 param_count++;
5095 } else if (i == VARYING_SLOT_VIEWPORT) {
5096 outinfo->writes_viewport_index = true;
5097 viewport_index_value = values[0];
5098 continue;
5099 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5100 outinfo->prim_id_output = param_count;
5101 target = V_008DFC_SQ_EXP_PARAM + param_count;
5102 param_count++;
5103 } else if (i >= VARYING_SLOT_VAR0) {
5104 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5105 target = V_008DFC_SQ_EXP_PARAM + param_count;
5106 param_count++;
5107 }
5108
5109 si_llvm_init_export_args(ctx, values, target, &args);
5110
5111 if (target >= V_008DFC_SQ_EXP_POS &&
5112 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5113 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5114 &args, sizeof(args));
5115 } else {
5116 ac_build_export(&ctx->ac, &args);
5117 }
5118 }
5119
5120 /* We need to add the position output manually if it's missing. */
5121 if (!pos_args[0].out[0]) {
5122 pos_args[0].enabled_channels = 0xf;
5123 pos_args[0].valid_mask = 0;
5124 pos_args[0].done = 0;
5125 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5126 pos_args[0].compr = 0;
5127 pos_args[0].out[0] = ctx->f32zero; /* X */
5128 pos_args[0].out[1] = ctx->f32zero; /* Y */
5129 pos_args[0].out[2] = ctx->f32zero; /* Z */
5130 pos_args[0].out[3] = ctx->f32one; /* W */
5131 }
5132
5133 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5134 (outinfo->writes_layer == true ? 4 : 0) |
5135 (outinfo->writes_viewport_index == true ? 8 : 0));
5136 if (mask) {
5137 pos_args[1].enabled_channels = mask;
5138 pos_args[1].valid_mask = 0;
5139 pos_args[1].done = 0;
5140 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5141 pos_args[1].compr = 0;
5142 pos_args[1].out[0] = ctx->f32zero; /* X */
5143 pos_args[1].out[1] = ctx->f32zero; /* Y */
5144 pos_args[1].out[2] = ctx->f32zero; /* Z */
5145 pos_args[1].out[3] = ctx->f32zero; /* W */
5146
5147 if (outinfo->writes_pointsize == true)
5148 pos_args[1].out[0] = psize_value;
5149 if (outinfo->writes_layer == true)
5150 pos_args[1].out[2] = layer_value;
5151 if (outinfo->writes_viewport_index == true)
5152 pos_args[1].out[3] = viewport_index_value;
5153 }
5154 for (i = 0; i < 4; i++) {
5155 if (pos_args[i].out[0])
5156 num_pos_exports++;
5157 }
5158
5159 pos_idx = 0;
5160 for (i = 0; i < 4; i++) {
5161 if (!pos_args[i].out[0])
5162 continue;
5163
5164 /* Specify the target we are exporting */
5165 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5166 if (pos_idx == num_pos_exports)
5167 pos_args[i].done = 1;
5168 ac_build_export(&ctx->ac, &pos_args[i]);
5169 }
5170
5171 outinfo->pos_exports = num_pos_exports;
5172 outinfo->param_exports = param_count;
5173 }
5174
5175 static void
5176 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5177 struct ac_es_output_info *outinfo)
5178 {
5179 int j;
5180 uint64_t max_output_written = 0;
5181 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5182 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5183 int param_index;
5184 int length = 4;
5185
5186 if (!(ctx->output_mask & (1ull << i)))
5187 continue;
5188
5189 if (i == VARYING_SLOT_CLIP_DIST0)
5190 length = ctx->num_output_clips + ctx->num_output_culls;
5191
5192 param_index = shader_io_get_unique_index(i);
5193
5194 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5195
5196 for (j = 0; j < length; j++) {
5197 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5198 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5199
5200 ac_build_buffer_store_dword(&ctx->ac,
5201 ctx->esgs_ring,
5202 out_val, 1,
5203 NULL, ctx->es2gs_offset,
5204 (4 * param_index + j) * 4,
5205 1, 1, true, true);
5206 }
5207 }
5208 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5209 }
5210
5211 static void
5212 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5213 {
5214 LLVMValueRef vertex_id = ctx->rel_auto_id;
5215 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5216 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5217 vertex_dw_stride, "");
5218
5219 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5220 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5221 int length = 4;
5222
5223 if (!(ctx->output_mask & (1ull << i)))
5224 continue;
5225
5226 if (i == VARYING_SLOT_CLIP_DIST0)
5227 length = ctx->num_output_clips + ctx->num_output_culls;
5228 int param = shader_io_get_unique_index(i);
5229 mark_tess_output(ctx, false, param);
5230 if (length > 4)
5231 mark_tess_output(ctx, false, param + 1);
5232 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5233 LLVMConstInt(ctx->i32, param * 4, false),
5234 "");
5235 for (unsigned j = 0; j < length; j++) {
5236 lds_store(ctx, dw_addr,
5237 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5238 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5239 }
5240 }
5241 }
5242
5243 struct ac_build_if_state
5244 {
5245 struct nir_to_llvm_context *ctx;
5246 LLVMValueRef condition;
5247 LLVMBasicBlockRef entry_block;
5248 LLVMBasicBlockRef true_block;
5249 LLVMBasicBlockRef false_block;
5250 LLVMBasicBlockRef merge_block;
5251 };
5252
5253 static LLVMBasicBlockRef
5254 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5255 {
5256 LLVMBasicBlockRef current_block;
5257 LLVMBasicBlockRef next_block;
5258 LLVMBasicBlockRef new_block;
5259
5260 /* get current basic block */
5261 current_block = LLVMGetInsertBlock(ctx->builder);
5262
5263 /* chqeck if there's another block after this one */
5264 next_block = LLVMGetNextBasicBlock(current_block);
5265 if (next_block) {
5266 /* insert the new block before the next block */
5267 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5268 }
5269 else {
5270 /* append new block after current block */
5271 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5272 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5273 }
5274 return new_block;
5275 }
5276
5277 static void
5278 ac_nir_build_if(struct ac_build_if_state *ifthen,
5279 struct nir_to_llvm_context *ctx,
5280 LLVMValueRef condition)
5281 {
5282 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5283
5284 memset(ifthen, 0, sizeof *ifthen);
5285 ifthen->ctx = ctx;
5286 ifthen->condition = condition;
5287 ifthen->entry_block = block;
5288
5289 /* create endif/merge basic block for the phi functions */
5290 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5291
5292 /* create/insert true_block before merge_block */
5293 ifthen->true_block =
5294 LLVMInsertBasicBlockInContext(ctx->context,
5295 ifthen->merge_block,
5296 "if-true-block");
5297
5298 /* successive code goes into the true block */
5299 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5300 }
5301
5302 /**
5303 * End a conditional.
5304 */
5305 static void
5306 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5307 {
5308 LLVMBuilderRef builder = ifthen->ctx->builder;
5309
5310 /* Insert branch to the merge block from current block */
5311 LLVMBuildBr(builder, ifthen->merge_block);
5312
5313 /*
5314 * Now patch in the various branch instructions.
5315 */
5316
5317 /* Insert the conditional branch instruction at the end of entry_block */
5318 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5319 if (ifthen->false_block) {
5320 /* we have an else clause */
5321 LLVMBuildCondBr(builder, ifthen->condition,
5322 ifthen->true_block, ifthen->false_block);
5323 }
5324 else {
5325 /* no else clause */
5326 LLVMBuildCondBr(builder, ifthen->condition,
5327 ifthen->true_block, ifthen->merge_block);
5328 }
5329
5330 /* Resume building code at end of the ifthen->merge_block */
5331 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5332 }
5333
5334 static void
5335 write_tess_factors(struct nir_to_llvm_context *ctx)
5336 {
5337 unsigned stride, outer_comps, inner_comps;
5338 struct ac_build_if_state if_ctx, inner_if_ctx;
5339 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5340 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5341 unsigned tess_inner_index, tess_outer_index;
5342 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5343 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5344 int i;
5345 emit_barrier(ctx);
5346
5347 switch (ctx->options->key.tcs.primitive_mode) {
5348 case GL_ISOLINES:
5349 stride = 2;
5350 outer_comps = 2;
5351 inner_comps = 0;
5352 break;
5353 case GL_TRIANGLES:
5354 stride = 4;
5355 outer_comps = 3;
5356 inner_comps = 1;
5357 break;
5358 case GL_QUADS:
5359 stride = 6;
5360 outer_comps = 4;
5361 inner_comps = 2;
5362 break;
5363 default:
5364 return;
5365 }
5366
5367 ac_nir_build_if(&if_ctx, ctx,
5368 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5369 invocation_id, ctx->i32zero, ""));
5370
5371 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5372 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5373
5374 mark_tess_output(ctx, true, tess_inner_index);
5375 mark_tess_output(ctx, true, tess_outer_index);
5376 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5377 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5378 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5379 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5380 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5381
5382 for (i = 0; i < 4; i++) {
5383 inner[i] = LLVMGetUndef(ctx->i32);
5384 outer[i] = LLVMGetUndef(ctx->i32);
5385 }
5386
5387 // LINES reverseal
5388 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5389 outer[0] = out[1] = lds_load(ctx, lds_outer);
5390 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5391 LLVMConstInt(ctx->i32, 1, false), "");
5392 outer[1] = out[0] = lds_load(ctx, lds_outer);
5393 } else {
5394 for (i = 0; i < outer_comps; i++) {
5395 outer[i] = out[i] =
5396 lds_load(ctx, lds_outer);
5397 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5398 LLVMConstInt(ctx->i32, 1, false), "");
5399 }
5400 for (i = 0; i < inner_comps; i++) {
5401 inner[i] = out[outer_comps+i] =
5402 lds_load(ctx, lds_inner);
5403 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5404 LLVMConstInt(ctx->i32, 1, false), "");
5405 }
5406 }
5407
5408 /* Convert the outputs to vectors for stores. */
5409 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5410 vec1 = NULL;
5411
5412 if (stride > 4)
5413 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5414
5415
5416 buffer = ctx->hs_ring_tess_factor;
5417 tf_base = ctx->tess_factor_offset;
5418 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5419 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5420
5421 ac_nir_build_if(&inner_if_ctx, ctx,
5422 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5423 rel_patch_id, ctx->i32zero, ""));
5424
5425 /* Store the dynamic HS control word. */
5426 ac_build_buffer_store_dword(&ctx->ac, buffer,
5427 LLVMConstInt(ctx->i32, 0x80000000, false),
5428 1, ctx->i32zero, tf_base,
5429 0, 1, 0, true, false);
5430 ac_nir_build_endif(&inner_if_ctx);
5431
5432 /* Store the tessellation factors. */
5433 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5434 MIN2(stride, 4), byteoffset, tf_base,
5435 4, 1, 0, true, false);
5436 if (vec1)
5437 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5438 stride - 4, byteoffset, tf_base,
5439 20, 1, 0, true, false);
5440
5441 //TODO store to offchip for TES to read - only if TES reads them
5442 if (1) {
5443 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5444 LLVMValueRef tf_inner_offset;
5445 unsigned param_outer, param_inner;
5446
5447 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5448 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5449 LLVMConstInt(ctx->i32, param_outer, 0));
5450
5451 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5452 util_next_power_of_two(outer_comps));
5453
5454 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5455 outer_comps, tf_outer_offset,
5456 ctx->oc_lds, 0, 1, 0, true, false);
5457 if (inner_comps) {
5458 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5459 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5460 LLVMConstInt(ctx->i32, param_inner, 0));
5461
5462 inner_vec = inner_comps == 1 ? inner[0] :
5463 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5464 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5465 inner_comps, tf_inner_offset,
5466 ctx->oc_lds, 0, 1, 0, true, false);
5467 }
5468 }
5469 ac_nir_build_endif(&if_ctx);
5470 }
5471
5472 static void
5473 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5474 {
5475 write_tess_factors(ctx);
5476 }
5477
5478 static void
5479 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5480 LLVMValueRef *color, unsigned param, bool is_last)
5481 {
5482
5483 struct ac_export_args args;
5484
5485 /* Export */
5486 si_llvm_init_export_args(ctx, color, param,
5487 &args);
5488
5489 if (is_last) {
5490 args.valid_mask = 1; /* whether the EXEC mask is valid */
5491 args.done = 1; /* DONE bit */
5492 } else if (!args.enabled_channels)
5493 return; /* unnecessary NULL export */
5494
5495 ac_build_export(&ctx->ac, &args);
5496 }
5497
5498 static void
5499 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5500 LLVMValueRef depth, LLVMValueRef stencil,
5501 LLVMValueRef samplemask)
5502 {
5503 struct ac_export_args args;
5504
5505 args.enabled_channels = 0;
5506 args.valid_mask = 1;
5507 args.done = 1;
5508 args.target = V_008DFC_SQ_EXP_MRTZ;
5509 args.compr = false;
5510
5511 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5512 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5513 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5514 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5515
5516 if (depth) {
5517 args.out[0] = depth;
5518 args.enabled_channels |= 0x1;
5519 }
5520
5521 if (stencil) {
5522 args.out[1] = stencil;
5523 args.enabled_channels |= 0x2;
5524 }
5525
5526 if (samplemask) {
5527 args.out[2] = samplemask;
5528 args.enabled_channels |= 0x4;
5529 }
5530
5531 /* SI (except OLAND) has a bug that it only looks
5532 * at the X writemask component. */
5533 if (ctx->options->chip_class == SI &&
5534 ctx->options->family != CHIP_OLAND)
5535 args.enabled_channels |= 0x1;
5536
5537 ac_build_export(&ctx->ac, &args);
5538 }
5539
5540 static void
5541 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5542 {
5543 unsigned index = 0;
5544 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5545
5546 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5547 LLVMValueRef values[4];
5548
5549 if (!(ctx->output_mask & (1ull << i)))
5550 continue;
5551
5552 if (i == FRAG_RESULT_DEPTH) {
5553 ctx->shader_info->fs.writes_z = true;
5554 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5555 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5556 } else if (i == FRAG_RESULT_STENCIL) {
5557 ctx->shader_info->fs.writes_stencil = true;
5558 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5559 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5560 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5561 ctx->shader_info->fs.writes_sample_mask = true;
5562 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5563 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5564 } else {
5565 bool last = false;
5566 for (unsigned j = 0; j < 4; j++)
5567 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5568 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5569
5570 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5571 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5572
5573 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
5574 index++;
5575 }
5576 }
5577
5578 if (depth || stencil || samplemask)
5579 si_export_mrt_z(ctx, depth, stencil, samplemask);
5580 else if (!index)
5581 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
5582
5583 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5584 }
5585
5586 static void
5587 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5588 {
5589 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5590 }
5591
5592 static void
5593 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5594 {
5595 switch (ctx->stage) {
5596 case MESA_SHADER_VERTEX:
5597 if (ctx->options->key.vs.as_ls)
5598 handle_ls_outputs_post(ctx);
5599 else if (ctx->options->key.vs.as_es)
5600 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5601 else
5602 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5603 break;
5604 case MESA_SHADER_FRAGMENT:
5605 handle_fs_outputs_post(ctx);
5606 break;
5607 case MESA_SHADER_GEOMETRY:
5608 emit_gs_epilogue(ctx);
5609 break;
5610 case MESA_SHADER_TESS_CTRL:
5611 handle_tcs_outputs_post(ctx);
5612 break;
5613 case MESA_SHADER_TESS_EVAL:
5614 if (ctx->options->key.tes.as_es)
5615 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5616 else
5617 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5618 break;
5619 default:
5620 break;
5621 }
5622 }
5623
5624 static void
5625 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5626 struct nir_variable *variable, uint32_t *offset, int idx)
5627 {
5628 unsigned size = glsl_count_attribute_slots(variable->type, false);
5629 variable->data.driver_location = *offset;
5630 *offset += size;
5631 }
5632
5633 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5634 {
5635 LLVMPassManagerRef passmgr;
5636 /* Create the pass manager */
5637 passmgr = LLVMCreateFunctionPassManagerForModule(
5638 ctx->module);
5639
5640 /* This pass should eliminate all the load and store instructions */
5641 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5642
5643 /* Add some optimization passes */
5644 LLVMAddScalarReplAggregatesPass(passmgr);
5645 LLVMAddLICMPass(passmgr);
5646 LLVMAddAggressiveDCEPass(passmgr);
5647 LLVMAddCFGSimplificationPass(passmgr);
5648 LLVMAddInstructionCombiningPass(passmgr);
5649
5650 /* Run the pass */
5651 LLVMInitializeFunctionPassManager(passmgr);
5652 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5653 LLVMFinalizeFunctionPassManager(passmgr);
5654
5655 LLVMDisposeBuilder(ctx->builder);
5656 LLVMDisposePassManager(passmgr);
5657 }
5658
5659 static void
5660 ac_setup_rings(struct nir_to_llvm_context *ctx)
5661 {
5662 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5663 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5664 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5665 }
5666
5667 if (ctx->is_gs_copy_shader) {
5668 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5669 }
5670 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5671 LLVMValueRef tmp;
5672 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5673 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5674
5675 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5676
5677 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5678 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5679 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5680 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5681
5682 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5683 }
5684
5685 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5686 ctx->stage == MESA_SHADER_TESS_EVAL) {
5687 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5688 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5689 }
5690 }
5691
5692 static
5693 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5694 struct nir_shader *nir,
5695 struct ac_shader_variant_info *shader_info,
5696 const struct ac_nir_compiler_options *options)
5697 {
5698 struct nir_to_llvm_context ctx = {0};
5699 struct nir_function *func;
5700 unsigned i;
5701 ctx.options = options;
5702 ctx.shader_info = shader_info;
5703 ctx.context = LLVMContextCreate();
5704 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5705
5706 ac_llvm_context_init(&ctx.ac, ctx.context);
5707 ctx.ac.module = ctx.module;
5708
5709 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5710
5711 memset(shader_info, 0, sizeof(*shader_info));
5712
5713 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5714
5715 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5716
5717 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5718 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5719 LLVMSetDataLayout(ctx.module, data_layout_str);
5720 LLVMDisposeTargetData(data_layout);
5721 LLVMDisposeMessage(data_layout_str);
5722
5723 setup_types(&ctx);
5724
5725 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5726 ctx.ac.builder = ctx.builder;
5727 ctx.stage = nir->stage;
5728
5729 for (i = 0; i < AC_UD_MAX_SETS; i++)
5730 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5731 for (i = 0; i < AC_UD_MAX_UD; i++)
5732 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5733
5734 create_function(&ctx);
5735
5736 if (nir->stage == MESA_SHADER_COMPUTE) {
5737 int num_shared = 0;
5738 nir_foreach_variable(variable, &nir->shared)
5739 num_shared++;
5740 if (num_shared) {
5741 int idx = 0;
5742 uint32_t shared_size = 0;
5743 LLVMValueRef var;
5744 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5745 nir_foreach_variable(variable, &nir->shared) {
5746 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5747 idx++;
5748 }
5749
5750 shared_size *= 16;
5751 var = LLVMAddGlobalInAddressSpace(ctx.module,
5752 LLVMArrayType(ctx.i8, shared_size),
5753 "compute_lds",
5754 LOCAL_ADDR_SPACE);
5755 LLVMSetAlignment(var, 4);
5756 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5757 }
5758 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5759 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5760
5761 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
5762 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5763 ctx.tes_primitive_mode = nir->info->tess.primitive_mode;
5764 }
5765
5766 ac_setup_rings(&ctx);
5767
5768 nir_foreach_variable(variable, &nir->inputs)
5769 handle_shader_input_decl(&ctx, variable);
5770
5771 if (nir->stage == MESA_SHADER_FRAGMENT)
5772 handle_fs_inputs_pre(&ctx, nir);
5773
5774 ctx.num_output_clips = nir->info->clip_distance_array_size;
5775 ctx.num_output_culls = nir->info->cull_distance_array_size;
5776
5777 nir_foreach_variable(variable, &nir->outputs)
5778 handle_shader_output_decl(&ctx, variable);
5779
5780 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5781 _mesa_key_pointer_equal);
5782 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5783 _mesa_key_pointer_equal);
5784
5785 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5786
5787 setup_locals(&ctx, func);
5788
5789 visit_cf_list(&ctx, &func->impl->body);
5790 phi_post_pass(&ctx);
5791
5792 handle_shader_outputs_post(&ctx);
5793 LLVMBuildRetVoid(ctx.builder);
5794
5795 ac_llvm_finalize_module(&ctx);
5796 free(ctx.locals);
5797 ralloc_free(ctx.defs);
5798 ralloc_free(ctx.phis);
5799
5800 if (nir->stage == MESA_SHADER_GEOMETRY) {
5801 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5802 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
5803 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5804 nir->info->gs.vertices_out;
5805 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
5806 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
5807 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
5808 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
5809 shader_info->vs.outputs_written = ctx.tess_outputs_written;
5810 }
5811
5812 return ctx.module;
5813 }
5814
5815 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5816 {
5817 unsigned *retval = (unsigned *)context;
5818 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5819 char *description = LLVMGetDiagInfoDescription(di);
5820
5821 if (severity == LLVMDSError) {
5822 *retval = 1;
5823 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5824 description);
5825 }
5826
5827 LLVMDisposeMessage(description);
5828 }
5829
5830 static unsigned ac_llvm_compile(LLVMModuleRef M,
5831 struct ac_shader_binary *binary,
5832 LLVMTargetMachineRef tm)
5833 {
5834 unsigned retval = 0;
5835 char *err;
5836 LLVMContextRef llvm_ctx;
5837 LLVMMemoryBufferRef out_buffer;
5838 unsigned buffer_size;
5839 const char *buffer_data;
5840 LLVMBool mem_err;
5841
5842 /* Setup Diagnostic Handler*/
5843 llvm_ctx = LLVMGetModuleContext(M);
5844
5845 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5846 &retval);
5847
5848 /* Compile IR*/
5849 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5850 &err, &out_buffer);
5851
5852 /* Process Errors/Warnings */
5853 if (mem_err) {
5854 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5855 free(err);
5856 retval = 1;
5857 goto out;
5858 }
5859
5860 /* Extract Shader Code*/
5861 buffer_size = LLVMGetBufferSize(out_buffer);
5862 buffer_data = LLVMGetBufferStart(out_buffer);
5863
5864 ac_elf_read(buffer_data, buffer_size, binary);
5865
5866 /* Clean up */
5867 LLVMDisposeMemoryBuffer(out_buffer);
5868
5869 out:
5870 return retval;
5871 }
5872
5873 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
5874 LLVMModuleRef llvm_module,
5875 struct ac_shader_binary *binary,
5876 struct ac_shader_config *config,
5877 struct ac_shader_variant_info *shader_info,
5878 gl_shader_stage stage,
5879 bool dump_shader, bool supports_spill)
5880 {
5881 if (dump_shader)
5882 ac_dump_module(llvm_module);
5883
5884 memset(binary, 0, sizeof(*binary));
5885 int v = ac_llvm_compile(llvm_module, binary, tm);
5886 if (v) {
5887 fprintf(stderr, "compile failed\n");
5888 }
5889
5890 if (dump_shader)
5891 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
5892
5893 ac_shader_binary_read_config(binary, config, 0, supports_spill);
5894
5895 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5896 LLVMDisposeModule(llvm_module);
5897 LLVMContextDispose(ctx);
5898
5899 if (stage == MESA_SHADER_FRAGMENT) {
5900 shader_info->num_input_vgprs = 0;
5901 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
5902 shader_info->num_input_vgprs += 2;
5903 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
5904 shader_info->num_input_vgprs += 2;
5905 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
5906 shader_info->num_input_vgprs += 2;
5907 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
5908 shader_info->num_input_vgprs += 3;
5909 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
5910 shader_info->num_input_vgprs += 2;
5911 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
5912 shader_info->num_input_vgprs += 2;
5913 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
5914 shader_info->num_input_vgprs += 2;
5915 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
5916 shader_info->num_input_vgprs += 1;
5917 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
5918 shader_info->num_input_vgprs += 1;
5919 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
5920 shader_info->num_input_vgprs += 1;
5921 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
5922 shader_info->num_input_vgprs += 1;
5923 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
5924 shader_info->num_input_vgprs += 1;
5925 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
5926 shader_info->num_input_vgprs += 1;
5927 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
5928 shader_info->num_input_vgprs += 1;
5929 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
5930 shader_info->num_input_vgprs += 1;
5931 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
5932 shader_info->num_input_vgprs += 1;
5933 }
5934 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
5935
5936 /* +3 for scratch wave offset and VCC */
5937 config->num_sgprs = MAX2(config->num_sgprs,
5938 shader_info->num_input_sgprs + 3);
5939 }
5940
5941 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
5942 struct ac_shader_binary *binary,
5943 struct ac_shader_config *config,
5944 struct ac_shader_variant_info *shader_info,
5945 struct nir_shader *nir,
5946 const struct ac_nir_compiler_options *options,
5947 bool dump_shader)
5948 {
5949
5950 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
5951 options);
5952
5953 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
5954 switch (nir->stage) {
5955 case MESA_SHADER_COMPUTE:
5956 for (int i = 0; i < 3; ++i)
5957 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5958 break;
5959 case MESA_SHADER_FRAGMENT:
5960 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5961 break;
5962 case MESA_SHADER_GEOMETRY:
5963 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5964 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5965 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5966 shader_info->gs.invocations = nir->info->gs.invocations;
5967 break;
5968 case MESA_SHADER_TESS_EVAL:
5969 shader_info->tes.primitive_mode = nir->info->tess.primitive_mode;
5970 shader_info->tes.spacing = nir->info->tess.spacing;
5971 shader_info->tes.ccw = nir->info->tess.ccw;
5972 shader_info->tes.point_mode = nir->info->tess.point_mode;
5973 shader_info->tes.as_es = options->key.tes.as_es;
5974 break;
5975 case MESA_SHADER_TESS_CTRL:
5976 shader_info->tcs.tcs_vertices_out = nir->info->tess.tcs_vertices_out;
5977 break;
5978 case MESA_SHADER_VERTEX:
5979 shader_info->vs.as_es = options->key.vs.as_es;
5980 shader_info->vs.as_ls = options->key.vs.as_ls;
5981 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
5982 if (options->key.vs.as_ls)
5983 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
5984 break;
5985 default:
5986 break;
5987 }
5988 }
5989
5990 static void
5991 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5992 {
5993 LLVMValueRef args[9];
5994 args[0] = ctx->gsvs_ring;
5995 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5996 args[3] = ctx->i32zero;
5997 args[4] = ctx->i32one; /* OFFEN */
5998 args[5] = ctx->i32zero; /* IDXEN */
5999 args[6] = ctx->i32one; /* GLC */
6000 args[7] = ctx->i32one; /* SLC */
6001 args[8] = ctx->i32zero; /* TFE */
6002
6003 int idx = 0;
6004
6005 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6006 int length = 4;
6007 int slot = idx;
6008 int slot_inc = 1;
6009 if (!(ctx->output_mask & (1ull << i)))
6010 continue;
6011
6012 if (i == VARYING_SLOT_CLIP_DIST0) {
6013 /* unpack clip and cull from a single set of slots */
6014 length = ctx->num_output_clips + ctx->num_output_culls;
6015 if (length > 4)
6016 slot_inc = 2;
6017 }
6018
6019 for (unsigned j = 0; j < length; j++) {
6020 LLVMValueRef value;
6021 args[2] = LLVMConstInt(ctx->i32,
6022 (slot * 4 + j) *
6023 ctx->gs_max_out_vertices * 16 * 4, false);
6024
6025 value = ac_build_intrinsic(&ctx->ac,
6026 "llvm.SI.buffer.load.dword.i32.i32",
6027 ctx->i32, args, 9,
6028 AC_FUNC_ATTR_READONLY |
6029 AC_FUNC_ATTR_LEGACY);
6030
6031 LLVMBuildStore(ctx->builder,
6032 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6033 }
6034 idx += slot_inc;
6035 }
6036 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6037 }
6038
6039 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6040 struct nir_shader *geom_shader,
6041 struct ac_shader_binary *binary,
6042 struct ac_shader_config *config,
6043 struct ac_shader_variant_info *shader_info,
6044 const struct ac_nir_compiler_options *options,
6045 bool dump_shader)
6046 {
6047 struct nir_to_llvm_context ctx = {0};
6048 ctx.context = LLVMContextCreate();
6049 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6050 ctx.options = options;
6051 ctx.shader_info = shader_info;
6052
6053 ac_llvm_context_init(&ctx.ac, ctx.context);
6054 ctx.ac.module = ctx.module;
6055
6056 ctx.is_gs_copy_shader = true;
6057 LLVMSetTarget(ctx.module, "amdgcn--");
6058 setup_types(&ctx);
6059
6060 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6061 ctx.ac.builder = ctx.builder;
6062 ctx.stage = MESA_SHADER_VERTEX;
6063
6064 create_function(&ctx);
6065
6066 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
6067 ac_setup_rings(&ctx);
6068
6069 ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
6070 ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
6071
6072 nir_foreach_variable(variable, &geom_shader->outputs)
6073 handle_shader_output_decl(&ctx, variable);
6074
6075 ac_gs_copy_shader_emit(&ctx);
6076
6077 LLVMBuildRetVoid(ctx.builder);
6078
6079 ac_llvm_finalize_module(&ctx);
6080
6081 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6082 MESA_SHADER_VERTEX,
6083 dump_shader, options->supports_spill);
6084 }