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radv/ac: start setting up the geom shader rings (v2)
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_util.h"
26 #include "ac_binary.h"
27 #include "sid.h"
28 #include "nir/nir.h"
29 #include "../vulkan/radv_descriptor_set.h"
30 #include "util/bitscan.h"
31 #include <llvm-c/Transforms/Scalar.h>
32
33 enum radeon_llvm_calling_convention {
34 RADEON_LLVM_AMDGPU_VS = 87,
35 RADEON_LLVM_AMDGPU_GS = 88,
36 RADEON_LLVM_AMDGPU_PS = 89,
37 RADEON_LLVM_AMDGPU_CS = 90,
38 };
39
40 #define CONST_ADDR_SPACE 2
41 #define LOCAL_ADDR_SPACE 3
42
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
44 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
45
46 #define SENDMSG_GS 2
47 #define SENDMSG_GS_DONE 3
48
49 #define SENDMSG_GS_OP_NOP (0 << 4)
50 #define SENDMSG_GS_OP_CUT (1 << 4)
51 #define SENDMSG_GS_OP_EMIT (2 << 4)
52 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
53
54 enum desc_type {
55 DESC_IMAGE,
56 DESC_FMASK,
57 DESC_SAMPLER,
58 DESC_BUFFER,
59 };
60
61 struct nir_to_llvm_context {
62 struct ac_llvm_context ac;
63 const struct ac_nir_compiler_options *options;
64 struct ac_shader_variant_info *shader_info;
65
66 LLVMContextRef context;
67 LLVMModuleRef module;
68 LLVMBuilderRef builder;
69 LLVMValueRef main_function;
70
71 struct hash_table *defs;
72 struct hash_table *phis;
73
74 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
75 LLVMValueRef ring_offsets;
76 LLVMValueRef push_constants;
77 LLVMValueRef num_work_groups;
78 LLVMValueRef workgroup_ids;
79 LLVMValueRef local_invocation_ids;
80 LLVMValueRef tg_size;
81
82 LLVMValueRef vertex_buffers;
83 LLVMValueRef base_vertex;
84 LLVMValueRef start_instance;
85 LLVMValueRef vertex_id;
86 LLVMValueRef rel_auto_id;
87 LLVMValueRef vs_prim_id;
88 LLVMValueRef instance_id;
89
90 LLVMValueRef gsvs_ring_stride;
91 LLVMValueRef gsvs_num_entries;
92 LLVMValueRef gs2vs_offset;
93 LLVMValueRef gs_wave_id;
94 LLVMValueRef gs_vtx_offset[6];
95 LLVMValueRef gs_prim_id, gs_invocation_id;
96
97 LLVMValueRef esgs_ring;
98 LLVMValueRef gsvs_ring;
99
100 LLVMValueRef prim_mask;
101 LLVMValueRef sample_positions;
102 LLVMValueRef persp_sample, persp_center, persp_centroid;
103 LLVMValueRef linear_sample, linear_center, linear_centroid;
104 LLVMValueRef front_face;
105 LLVMValueRef ancillary;
106 LLVMValueRef frag_pos[4];
107
108 LLVMBasicBlockRef continue_block;
109 LLVMBasicBlockRef break_block;
110
111 LLVMTypeRef i1;
112 LLVMTypeRef i8;
113 LLVMTypeRef i16;
114 LLVMTypeRef i32;
115 LLVMTypeRef i64;
116 LLVMTypeRef v2i32;
117 LLVMTypeRef v3i32;
118 LLVMTypeRef v4i32;
119 LLVMTypeRef v8i32;
120 LLVMTypeRef f32;
121 LLVMTypeRef f16;
122 LLVMTypeRef v2f32;
123 LLVMTypeRef v4f32;
124 LLVMTypeRef v16i8;
125 LLVMTypeRef voidt;
126
127 LLVMValueRef i32zero;
128 LLVMValueRef i32one;
129 LLVMValueRef f32zero;
130 LLVMValueRef f32one;
131 LLVMValueRef v4f32empty;
132
133 unsigned range_md_kind;
134 unsigned uniform_md_kind;
135 unsigned invariant_load_md_kind;
136 LLVMValueRef empty_md;
137 gl_shader_stage stage;
138
139 LLVMValueRef lds;
140 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
141 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
142
143 LLVMValueRef shared_memory;
144 uint64_t input_mask;
145 uint64_t output_mask;
146 int num_locals;
147 LLVMValueRef *locals;
148 bool has_ddxy;
149 unsigned num_clips;
150 unsigned num_culls;
151
152 bool has_ds_bpermute;
153
154 bool is_gs_copy_shader;
155 LLVMValueRef gs_next_vertex;
156 unsigned gs_max_out_vertices;
157 };
158
159 struct ac_tex_info {
160 LLVMValueRef args[12];
161 int arg_count;
162 LLVMTypeRef dst_type;
163 bool has_offset;
164 };
165
166 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
167 nir_deref_var *deref,
168 enum desc_type desc_type);
169 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
170 {
171 return (index * 4) + chan;
172 }
173
174 static unsigned llvm_get_type_size(LLVMTypeRef type)
175 {
176 LLVMTypeKind kind = LLVMGetTypeKind(type);
177
178 switch (kind) {
179 case LLVMIntegerTypeKind:
180 return LLVMGetIntTypeWidth(type) / 8;
181 case LLVMFloatTypeKind:
182 return 4;
183 case LLVMPointerTypeKind:
184 return 8;
185 case LLVMVectorTypeKind:
186 return LLVMGetVectorSize(type) *
187 llvm_get_type_size(LLVMGetElementType(type));
188 default:
189 assert(0);
190 return 0;
191 }
192 }
193
194 static void set_llvm_calling_convention(LLVMValueRef func,
195 gl_shader_stage stage)
196 {
197 enum radeon_llvm_calling_convention calling_conv;
198
199 switch (stage) {
200 case MESA_SHADER_VERTEX:
201 case MESA_SHADER_TESS_CTRL:
202 case MESA_SHADER_TESS_EVAL:
203 calling_conv = RADEON_LLVM_AMDGPU_VS;
204 break;
205 case MESA_SHADER_GEOMETRY:
206 calling_conv = RADEON_LLVM_AMDGPU_GS;
207 break;
208 case MESA_SHADER_FRAGMENT:
209 calling_conv = RADEON_LLVM_AMDGPU_PS;
210 break;
211 case MESA_SHADER_COMPUTE:
212 calling_conv = RADEON_LLVM_AMDGPU_CS;
213 break;
214 default:
215 unreachable("Unhandle shader type");
216 }
217
218 LLVMSetFunctionCallConv(func, calling_conv);
219 }
220
221 static LLVMValueRef
222 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
223 LLVMBuilderRef builder, LLVMTypeRef *return_types,
224 unsigned num_return_elems, LLVMTypeRef *param_types,
225 unsigned param_count, unsigned array_params_mask,
226 unsigned sgpr_params, bool unsafe_math)
227 {
228 LLVMTypeRef main_function_type, ret_type;
229 LLVMBasicBlockRef main_function_body;
230
231 if (num_return_elems)
232 ret_type = LLVMStructTypeInContext(ctx, return_types,
233 num_return_elems, true);
234 else
235 ret_type = LLVMVoidTypeInContext(ctx);
236
237 /* Setup the function */
238 main_function_type =
239 LLVMFunctionType(ret_type, param_types, param_count, 0);
240 LLVMValueRef main_function =
241 LLVMAddFunction(module, "main", main_function_type);
242 main_function_body =
243 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
244 LLVMPositionBuilderAtEnd(builder, main_function_body);
245
246 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
247 for (unsigned i = 0; i < sgpr_params; ++i) {
248 if (array_params_mask & (1 << i)) {
249 LLVMValueRef P = LLVMGetParam(main_function, i);
250 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
251 ac_add_attr_dereferenceable(P, UINT64_MAX);
252 }
253 else {
254 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
255 }
256 }
257
258 if (unsafe_math) {
259 /* These were copied from some LLVM test. */
260 LLVMAddTargetDependentFunctionAttr(main_function,
261 "less-precise-fpmad",
262 "true");
263 LLVMAddTargetDependentFunctionAttr(main_function,
264 "no-infs-fp-math",
265 "true");
266 LLVMAddTargetDependentFunctionAttr(main_function,
267 "no-nans-fp-math",
268 "true");
269 LLVMAddTargetDependentFunctionAttr(main_function,
270 "unsafe-fp-math",
271 "true");
272 }
273 return main_function;
274 }
275
276 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
277 {
278 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
279 CONST_ADDR_SPACE);
280 }
281
282 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
283 int idx,
284 LLVMTypeRef type)
285 {
286 LLVMValueRef offset;
287 LLVMValueRef ptr;
288 int addr_space;
289
290 offset = LLVMConstInt(ctx->i32, idx, false);
291
292 ptr = ctx->shared_memory;
293 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
294 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
295 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
296 return ptr;
297 }
298
299 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
300 {
301 LLVMTypeRef type = LLVMTypeOf(v);
302 if (type == ctx->f32) {
303 return LLVMBuildBitCast(ctx->builder, v, ctx->i32, "");
304 } else if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
305 LLVMTypeRef elem_type = LLVMGetElementType(type);
306 if (elem_type == ctx->f32) {
307 LLVMTypeRef nt = LLVMVectorType(ctx->i32, LLVMGetVectorSize(type));
308 return LLVMBuildBitCast(ctx->builder, v, nt, "");
309 }
310 }
311 return v;
312 }
313
314 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
315 {
316 LLVMTypeRef type = LLVMTypeOf(v);
317 if (type == ctx->i32) {
318 return LLVMBuildBitCast(ctx->builder, v, ctx->f32, "");
319 } else if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
320 LLVMTypeRef elem_type = LLVMGetElementType(type);
321 if (elem_type == ctx->i32) {
322 LLVMTypeRef nt = LLVMVectorType(ctx->f32, LLVMGetVectorSize(type));
323 return LLVMBuildBitCast(ctx->builder, v, nt, "");
324 }
325 }
326 return v;
327 }
328
329 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
330 LLVMValueRef param, unsigned rshift,
331 unsigned bitwidth)
332 {
333 LLVMValueRef value = param;
334 if (rshift)
335 value = LLVMBuildLShr(ctx->builder, value,
336 LLVMConstInt(ctx->i32, rshift, false), "");
337
338 if (rshift + bitwidth < 32) {
339 unsigned mask = (1 << bitwidth) - 1;
340 value = LLVMBuildAnd(ctx->builder, value,
341 LLVMConstInt(ctx->i32, mask, false), "");
342 }
343 return value;
344 }
345
346 static LLVMValueRef build_gep0(struct nir_to_llvm_context *ctx,
347 LLVMValueRef base_ptr, LLVMValueRef index)
348 {
349 LLVMValueRef indices[2] = {
350 ctx->i32zero,
351 index,
352 };
353 return LLVMBuildGEP(ctx->builder, base_ptr,
354 indices, 2, "");
355 }
356
357 static LLVMValueRef build_indexed_load(struct nir_to_llvm_context *ctx,
358 LLVMValueRef base_ptr, LLVMValueRef index,
359 bool uniform)
360 {
361 LLVMValueRef pointer;
362 pointer = build_gep0(ctx, base_ptr, index);
363 if (uniform)
364 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
365 return LLVMBuildLoad(ctx->builder, pointer, "");
366 }
367
368 static LLVMValueRef build_indexed_load_const(struct nir_to_llvm_context *ctx,
369 LLVMValueRef base_ptr, LLVMValueRef index)
370 {
371 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
372 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
373 return result;
374 }
375
376 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
377 {
378 ud_info->sgpr_idx = sgpr_idx;
379 ud_info->num_sgprs = num_sgprs;
380 ud_info->indirect = false;
381 ud_info->indirect_offset = 0;
382 }
383
384 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
385 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
386 {
387 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
388 }
389
390 #if 0
391 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
392 uint32_t indirect_offset)
393 {
394 ud_info->sgpr_idx = sgpr_idx;
395 ud_info->num_sgprs = num_sgprs;
396 ud_info->indirect = true;
397 ud_info->indirect_offset = indirect_offset;
398 }
399 #endif
400
401 static void create_function(struct nir_to_llvm_context *ctx)
402 {
403 LLVMTypeRef arg_types[23];
404 unsigned arg_idx = 0;
405 unsigned array_params_mask = 0;
406 unsigned sgpr_count = 0, user_sgpr_count;
407 unsigned i;
408 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
409 unsigned user_sgpr_idx;
410 bool need_push_constants;
411 bool need_ring_offsets = false;
412
413 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
414 if (ctx->stage == MESA_SHADER_GEOMETRY ||
415 ctx->stage == MESA_SHADER_VERTEX ||
416 ctx->is_gs_copy_shader)
417 need_ring_offsets = true;
418
419 need_push_constants = true;
420 if (!ctx->options->layout)
421 need_push_constants = false;
422 else if (!ctx->options->layout->push_constant_size &&
423 !ctx->options->layout->dynamic_offset_count)
424 need_push_constants = false;
425
426 if (need_ring_offsets && !ctx->options->supports_spill) {
427 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
428 }
429
430 /* 1 for each descriptor set */
431 for (unsigned i = 0; i < num_sets; ++i) {
432 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
433 array_params_mask |= (1 << arg_idx);
434 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
435 }
436 }
437
438 if (need_push_constants) {
439 /* 1 for push constants and dynamic descriptors */
440 array_params_mask |= (1 << arg_idx);
441 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
442 }
443
444 switch (ctx->stage) {
445 case MESA_SHADER_COMPUTE:
446 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
447 user_sgpr_count = arg_idx;
448 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
449 arg_types[arg_idx++] = ctx->i32;
450 sgpr_count = arg_idx;
451
452 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
453 break;
454 case MESA_SHADER_VERTEX:
455 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
456 arg_types[arg_idx++] = ctx->i32; // base vertex
457 arg_types[arg_idx++] = ctx->i32; // start instance
458 user_sgpr_count = sgpr_count = arg_idx;
459 arg_types[arg_idx++] = ctx->i32; // vertex id
460 arg_types[arg_idx++] = ctx->i32; // rel auto id
461 arg_types[arg_idx++] = ctx->i32; // vs prim id
462 arg_types[arg_idx++] = ctx->i32; // instance id
463 break;
464 case MESA_SHADER_GEOMETRY:
465 arg_types[arg_idx++] = ctx->i32; // gsvs stride
466 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
467 user_sgpr_count = arg_idx;
468 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
469 arg_types[arg_idx++] = ctx->i32; // wave id
470 sgpr_count = arg_idx;
471 arg_types[arg_idx++] = ctx->i32; // vtx0
472 arg_types[arg_idx++] = ctx->i32; // vtx1
473 arg_types[arg_idx++] = ctx->i32; // prim id
474 arg_types[arg_idx++] = ctx->i32; // vtx2
475 arg_types[arg_idx++] = ctx->i32; // vtx3
476 arg_types[arg_idx++] = ctx->i32; // vtx4
477 arg_types[arg_idx++] = ctx->i32; // vtx5
478 arg_types[arg_idx++] = ctx->i32; // GS instance id
479 break;
480 case MESA_SHADER_FRAGMENT:
481 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
482 user_sgpr_count = arg_idx;
483 arg_types[arg_idx++] = ctx->i32; /* prim mask */
484 sgpr_count = arg_idx;
485 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
486 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
487 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
488 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
489 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
490 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
491 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
492 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
493 arg_types[arg_idx++] = ctx->f32; /* pos x float */
494 arg_types[arg_idx++] = ctx->f32; /* pos y float */
495 arg_types[arg_idx++] = ctx->f32; /* pos z float */
496 arg_types[arg_idx++] = ctx->f32; /* pos w float */
497 arg_types[arg_idx++] = ctx->i32; /* front face */
498 arg_types[arg_idx++] = ctx->i32; /* ancillary */
499 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
500 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
501 break;
502 default:
503 unreachable("Shader stage not implemented");
504 }
505
506 ctx->main_function = create_llvm_function(
507 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
508 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
509 set_llvm_calling_convention(ctx->main_function, ctx->stage);
510
511 ctx->shader_info->num_input_sgprs = 0;
512 ctx->shader_info->num_input_vgprs = 0;
513
514 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
515 for (i = 0; i < user_sgpr_count; i++)
516 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
517
518 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
519 for (; i < sgpr_count; i++)
520 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
521
522 if (ctx->stage != MESA_SHADER_FRAGMENT)
523 for (; i < arg_idx; ++i)
524 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
525
526 arg_idx = 0;
527 user_sgpr_idx = 0;
528
529 if (ctx->options->supports_spill || need_ring_offsets) {
530 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
531 user_sgpr_idx += 2;
532 if (ctx->options->supports_spill) {
533 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
534 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
535 NULL, 0, AC_FUNC_ATTR_READNONE);
536 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
537 const_array(ctx->v16i8, 8), "");
538 } else
539 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
540 }
541
542 for (unsigned i = 0; i < num_sets; ++i) {
543 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
544 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
545 user_sgpr_idx += 2;
546 ctx->descriptor_sets[i] =
547 LLVMGetParam(ctx->main_function, arg_idx++);
548 } else
549 ctx->descriptor_sets[i] = NULL;
550 }
551
552 if (need_push_constants) {
553 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
554 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
555 user_sgpr_idx += 2;
556 }
557
558 switch (ctx->stage) {
559 case MESA_SHADER_COMPUTE:
560 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
561 user_sgpr_idx += 3;
562 ctx->num_work_groups =
563 LLVMGetParam(ctx->main_function, arg_idx++);
564 ctx->workgroup_ids =
565 LLVMGetParam(ctx->main_function, arg_idx++);
566 ctx->tg_size =
567 LLVMGetParam(ctx->main_function, arg_idx++);
568 ctx->local_invocation_ids =
569 LLVMGetParam(ctx->main_function, arg_idx++);
570 break;
571 case MESA_SHADER_VERTEX:
572 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
573 user_sgpr_idx += 2;
574 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
575 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 2);
576 user_sgpr_idx += 2;
577 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
578 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
579 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
580 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
581 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
582 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
583 break;
584 case MESA_SHADER_GEOMETRY:
585 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
586 user_sgpr_idx += 2;
587 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
588 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
589 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
590 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
591 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
592 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
593 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
594 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
595 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
596 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
597 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
598 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
599 break;
600 case MESA_SHADER_FRAGMENT:
601 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
602 user_sgpr_idx += 2;
603 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
604 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
605 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
606 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
607 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
608 arg_idx++;
609 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
610 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
611 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
612 arg_idx++; /* line stipple */
613 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
614 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
615 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
616 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
617 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
618 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
619 break;
620 default:
621 unreachable("Shader stage not implemented");
622 }
623 }
624
625 static void setup_types(struct nir_to_llvm_context *ctx)
626 {
627 LLVMValueRef args[4];
628
629 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
630 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
631 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
632 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
633 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
634 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
635 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
636 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
637 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
638 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
639 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
640 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
641 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
642 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
643 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
644
645 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
646 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
647 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
648 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
649
650 args[0] = ctx->f32zero;
651 args[1] = ctx->f32zero;
652 args[2] = ctx->f32zero;
653 args[3] = ctx->f32one;
654 ctx->v4f32empty = LLVMConstVector(args, 4);
655
656 ctx->range_md_kind = LLVMGetMDKindIDInContext(ctx->context,
657 "range", 5);
658 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(ctx->context,
659 "invariant.load", 14);
660 ctx->uniform_md_kind =
661 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
662 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
663
664 args[0] = LLVMConstReal(ctx->f32, 2.5);
665 }
666
667 static int get_llvm_num_components(LLVMValueRef value)
668 {
669 LLVMTypeRef type = LLVMTypeOf(value);
670 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
671 ? LLVMGetVectorSize(type)
672 : 1;
673 return num_components;
674 }
675
676 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
677 LLVMValueRef value,
678 int index)
679 {
680 int count = get_llvm_num_components(value);
681
682 assert(index < count);
683 if (count == 1)
684 return value;
685
686 return LLVMBuildExtractElement(ctx->builder, value,
687 LLVMConstInt(ctx->i32, index, false), "");
688 }
689
690 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
691 LLVMValueRef value, unsigned count)
692 {
693 unsigned num_components = get_llvm_num_components(value);
694 if (count == num_components)
695 return value;
696
697 LLVMValueRef masks[] = {
698 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
699 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
700
701 if (count == 1)
702 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
703 "");
704
705 LLVMValueRef swizzle = LLVMConstVector(masks, count);
706 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
707 }
708
709 static void
710 build_store_values_extended(struct nir_to_llvm_context *ctx,
711 LLVMValueRef *values,
712 unsigned value_count,
713 unsigned value_stride,
714 LLVMValueRef vec)
715 {
716 LLVMBuilderRef builder = ctx->builder;
717 unsigned i;
718
719 if (value_count == 1) {
720 LLVMBuildStore(builder, vec, values[0]);
721 return;
722 }
723
724 for (i = 0; i < value_count; i++) {
725 LLVMValueRef ptr = values[i * value_stride];
726 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
727 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
728 LLVMBuildStore(builder, value, ptr);
729 }
730 }
731
732 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
733 nir_ssa_def *def)
734 {
735 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
736 if (def->num_components > 1) {
737 type = LLVMVectorType(type, def->num_components);
738 }
739 return type;
740 }
741
742 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
743 {
744 assert(src.is_ssa);
745 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
746 return (LLVMValueRef)entry->data;
747 }
748
749
750 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
751 struct nir_block *b)
752 {
753 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
754 return (LLVMBasicBlockRef)entry->data;
755 }
756
757 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
758 nir_alu_src src,
759 unsigned num_components)
760 {
761 LLVMValueRef value = get_src(ctx, src.src);
762 bool need_swizzle = false;
763
764 assert(value);
765 LLVMTypeRef type = LLVMTypeOf(value);
766 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
767 ? LLVMGetVectorSize(type)
768 : 1;
769
770 for (unsigned i = 0; i < num_components; ++i) {
771 assert(src.swizzle[i] < src_components);
772 if (src.swizzle[i] != i)
773 need_swizzle = true;
774 }
775
776 if (need_swizzle || num_components != src_components) {
777 LLVMValueRef masks[] = {
778 LLVMConstInt(ctx->i32, src.swizzle[0], false),
779 LLVMConstInt(ctx->i32, src.swizzle[1], false),
780 LLVMConstInt(ctx->i32, src.swizzle[2], false),
781 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
782
783 if (src_components > 1 && num_components == 1) {
784 value = LLVMBuildExtractElement(ctx->builder, value,
785 masks[0], "");
786 } else if (src_components == 1 && num_components > 1) {
787 LLVMValueRef values[] = {value, value, value, value};
788 value = ac_build_gather_values(&ctx->ac, values, num_components);
789 } else {
790 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
791 value = LLVMBuildShuffleVector(ctx->builder, value, value,
792 swizzle, "");
793 }
794 }
795 assert(!src.negate);
796 assert(!src.abs);
797 return value;
798 }
799
800 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
801 LLVMIntPredicate pred, LLVMValueRef src0,
802 LLVMValueRef src1)
803 {
804 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
805 return LLVMBuildSelect(ctx->builder, result,
806 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
807 LLVMConstInt(ctx->i32, 0, false), "");
808 }
809
810 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
811 LLVMRealPredicate pred, LLVMValueRef src0,
812 LLVMValueRef src1)
813 {
814 LLVMValueRef result;
815 src0 = to_float(ctx, src0);
816 src1 = to_float(ctx, src1);
817 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
818 return LLVMBuildSelect(ctx->builder, result,
819 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
820 LLVMConstInt(ctx->i32, 0, false), "");
821 }
822
823 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
824 const char *intrin,
825 LLVMValueRef src0)
826 {
827 LLVMValueRef params[] = {
828 to_float(ctx, src0),
829 };
830 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 1, AC_FUNC_ATTR_READNONE);
831 }
832
833 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
834 const char *intrin,
835 LLVMValueRef src0, LLVMValueRef src1)
836 {
837 LLVMValueRef params[] = {
838 to_float(ctx, src0),
839 to_float(ctx, src1),
840 };
841 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 2, AC_FUNC_ATTR_READNONE);
842 }
843
844 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
845 const char *intrin,
846 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
847 {
848 LLVMValueRef params[] = {
849 to_float(ctx, src0),
850 to_float(ctx, src1),
851 to_float(ctx, src2),
852 };
853 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 3, AC_FUNC_ATTR_READNONE);
854 }
855
856 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
857 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
858 {
859 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
860 ctx->i32zero, "");
861 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
862 }
863
864 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
865 LLVMValueRef src0)
866 {
867 LLVMValueRef params[2] = {
868 src0,
869
870 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
871 * add special code to check for x=0. The reason is that
872 * the LLVM behavior for x=0 is different from what we
873 * need here.
874 *
875 * The hardware already implements the correct behavior.
876 */
877 LLVMConstInt(ctx->i32, 1, false),
878 };
879 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
880 }
881
882 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
883 LLVMValueRef src0)
884 {
885 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.flbit.i32",
886 ctx->i32, &src0, 1,
887 AC_FUNC_ATTR_READNONE);
888
889 /* The HW returns the last bit index from MSB, but NIR wants
890 * the index from LSB. Invert it by doing "31 - msb". */
891 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
892 msb, "");
893
894 LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true);
895 LLVMValueRef cond = LLVMBuildOr(ctx->builder,
896 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
897 src0, ctx->i32zero, ""),
898 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
899 src0, all_ones, ""), "");
900
901 return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, "");
902 }
903
904 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
905 LLVMValueRef src0)
906 {
907 LLVMValueRef args[2] = {
908 src0,
909 ctx->i32one,
910 };
911 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
912 ctx->i32, args, ARRAY_SIZE(args),
913 AC_FUNC_ATTR_READNONE);
914
915 /* The HW returns the last bit index from MSB, but NIR wants
916 * the index from LSB. Invert it by doing "31 - msb". */
917 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
918 msb, "");
919
920 return LLVMBuildSelect(ctx->builder,
921 LLVMBuildICmp(ctx->builder, LLVMIntEQ, src0,
922 ctx->i32zero, ""),
923 LLVMConstInt(ctx->i32, -1, true), msb, "");
924 }
925
926 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
927 LLVMIntPredicate pred,
928 LLVMValueRef src0, LLVMValueRef src1)
929 {
930 return LLVMBuildSelect(ctx->builder,
931 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
932 src0,
933 src1, "");
934
935 }
936 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
937 LLVMValueRef src0)
938 {
939 return emit_minmax_int(ctx, LLVMIntSGT, src0,
940 LLVMBuildNeg(ctx->builder, src0, ""));
941 }
942
943 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
944 LLVMValueRef src0)
945 {
946 LLVMValueRef cmp, val;
947
948 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
949 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
950 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
951 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
952 return val;
953 }
954
955 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
956 LLVMValueRef src0)
957 {
958 LLVMValueRef cmp, val;
959
960 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
961 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
962 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
963 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
964 return val;
965 }
966
967 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
968 LLVMValueRef src0)
969 {
970 const char *intr = "llvm.floor.f32";
971 LLVMValueRef fsrc0 = to_float(ctx, src0);
972 LLVMValueRef params[] = {
973 fsrc0,
974 };
975 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
976 ctx->f32, params, 1,
977 AC_FUNC_ATTR_READNONE);
978 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
979 }
980
981 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
982 const char *intrin,
983 LLVMValueRef src0, LLVMValueRef src1)
984 {
985 LLVMTypeRef ret_type;
986 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
987 LLVMValueRef res;
988 LLVMValueRef params[] = { src0, src1 };
989 ret_type = LLVMStructTypeInContext(ctx->context, types,
990 2, true);
991
992 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
993 params, 2, AC_FUNC_ATTR_READNONE);
994
995 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
996 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
997 return res;
998 }
999
1000 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1001 LLVMValueRef src0)
1002 {
1003 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1004 }
1005
1006 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1007 LLVMValueRef src0, LLVMValueRef src1)
1008 {
1009 LLVMValueRef dst64, result;
1010 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1011 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1012
1013 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1014 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1015 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1016 return result;
1017 }
1018
1019 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1020 LLVMValueRef src0, LLVMValueRef src1)
1021 {
1022 LLVMValueRef dst64, result;
1023 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1024 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1025
1026 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1027 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1028 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1029 return result;
1030 }
1031
1032 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1033 const char *intrin,
1034 LLVMValueRef srcs[3])
1035 {
1036 LLVMValueRef result;
1037 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1038 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1039
1040 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1041 return result;
1042 }
1043
1044 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1045 LLVMValueRef src0, LLVMValueRef src1,
1046 LLVMValueRef src2, LLVMValueRef src3)
1047 {
1048 LLVMValueRef bfi_args[3], result;
1049
1050 bfi_args[0] = LLVMBuildShl(ctx->builder,
1051 LLVMBuildSub(ctx->builder,
1052 LLVMBuildShl(ctx->builder,
1053 ctx->i32one,
1054 src3, ""),
1055 ctx->i32one, ""),
1056 src2, "");
1057 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1058 bfi_args[2] = src0;
1059
1060 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1061
1062 /* Calculate:
1063 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1064 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1065 */
1066 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1067 LLVMBuildAnd(ctx->builder, bfi_args[0],
1068 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1069
1070 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1071 return result;
1072 }
1073
1074 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1075 LLVMValueRef src0)
1076 {
1077 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1078 int i;
1079 LLVMValueRef comp[2];
1080
1081 src0 = to_float(ctx, src0);
1082 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1083 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1084 for (i = 0; i < 2; i++) {
1085 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1086 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1087 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1088 }
1089
1090 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1091 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1092
1093 return comp[0];
1094 }
1095
1096 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1097 LLVMValueRef src0)
1098 {
1099 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1100 LLVMValueRef temps[2], result, val;
1101 int i;
1102
1103 for (i = 0; i < 2; i++) {
1104 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1105 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1106 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1107 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1108 }
1109
1110 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1111 ctx->i32zero, "");
1112 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1113 ctx->i32one, "");
1114 return result;
1115 }
1116
1117 /**
1118 * Set range metadata on an instruction. This can only be used on load and
1119 * call instructions. If you know an instruction can only produce the values
1120 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1121 * \p lo is the minimum value inclusive.
1122 * \p hi is the maximum value exclusive.
1123 */
1124 static void set_range_metadata(struct nir_to_llvm_context *ctx,
1125 LLVMValueRef value, unsigned lo, unsigned hi)
1126 {
1127 LLVMValueRef range_md, md_args[2];
1128 LLVMTypeRef type = LLVMTypeOf(value);
1129 LLVMContextRef context = LLVMGetTypeContext(type);
1130
1131 md_args[0] = LLVMConstInt(type, lo, false);
1132 md_args[1] = LLVMConstInt(type, hi, false);
1133 range_md = LLVMMDNodeInContext(context, md_args, 2);
1134 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1135 }
1136
1137 static LLVMValueRef get_thread_id(struct nir_to_llvm_context *ctx)
1138 {
1139 LLVMValueRef tid;
1140 LLVMValueRef tid_args[2];
1141 tid_args[0] = LLVMConstInt(ctx->i32, 0xffffffff, false);
1142 tid_args[1] = ctx->i32zero;
1143 tid_args[1] = ac_emit_llvm_intrinsic(&ctx->ac,
1144 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1145 tid_args, 2, AC_FUNC_ATTR_READNONE);
1146
1147 tid = ac_emit_llvm_intrinsic(&ctx->ac,
1148 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1149 tid_args, 2, AC_FUNC_ATTR_READNONE);
1150 set_range_metadata(ctx, tid, 0, 64);
1151 return tid;
1152 }
1153
1154 /*
1155 * SI implements derivatives using the local data store (LDS)
1156 * All writes to the LDS happen in all executing threads at
1157 * the same time. TID is the Thread ID for the current
1158 * thread and is a value between 0 and 63, representing
1159 * the thread's position in the wavefront.
1160 *
1161 * For the pixel shader threads are grouped into quads of four pixels.
1162 * The TIDs of the pixels of a quad are:
1163 *
1164 * +------+------+
1165 * |4n + 0|4n + 1|
1166 * +------+------+
1167 * |4n + 2|4n + 3|
1168 * +------+------+
1169 *
1170 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
1171 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
1172 * the current pixel's column, and masking with 0xfffffffe yields the TID
1173 * of the left pixel of the current pixel's row.
1174 *
1175 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
1176 * adding 2 yields the TID of the pixel below the top pixel.
1177 */
1178 /* masks for thread ID. */
1179 #define TID_MASK_TOP_LEFT 0xfffffffc
1180 #define TID_MASK_TOP 0xfffffffd
1181 #define TID_MASK_LEFT 0xfffffffe
1182 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1183 nir_op op,
1184 LLVMValueRef src0)
1185 {
1186 LLVMValueRef tl, trbl, result;
1187 LLVMValueRef tl_tid, trbl_tid;
1188 LLVMValueRef args[2];
1189 LLVMValueRef thread_id;
1190 unsigned mask;
1191 int idx;
1192 ctx->has_ddxy = true;
1193
1194 if (!ctx->lds && !ctx->has_ds_bpermute)
1195 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1196 LLVMArrayType(ctx->i32, 64),
1197 "ddxy_lds", LOCAL_ADDR_SPACE);
1198
1199 thread_id = get_thread_id(ctx);
1200 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1201 mask = TID_MASK_LEFT;
1202 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1203 mask = TID_MASK_TOP;
1204 else
1205 mask = TID_MASK_TOP_LEFT;
1206
1207 tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
1208 LLVMConstInt(ctx->i32, mask, false), "");
1209 /* for DDX we want to next X pixel, DDY next Y pixel. */
1210 if (op == nir_op_fddx_fine ||
1211 op == nir_op_fddx_coarse ||
1212 op == nir_op_fddx)
1213 idx = 1;
1214 else
1215 idx = 2;
1216
1217 trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
1218 LLVMConstInt(ctx->i32, idx, false), "");
1219
1220 if (ctx->has_ds_bpermute) {
1221 args[0] = LLVMBuildMul(ctx->builder, tl_tid,
1222 LLVMConstInt(ctx->i32, 4, false), "");
1223 args[1] = src0;
1224 tl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1225 ctx->i32, args, 2,
1226 AC_FUNC_ATTR_READNONE);
1227
1228 args[0] = LLVMBuildMul(ctx->builder, trbl_tid,
1229 LLVMConstInt(ctx->i32, 4, false), "");
1230 trbl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1231 ctx->i32, args, 2,
1232 AC_FUNC_ATTR_READNONE);
1233 } else {
1234 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1235
1236 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
1237 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
1238 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
1239
1240 LLVMBuildStore(ctx->builder, src0, store_ptr);
1241 tl = LLVMBuildLoad(ctx->builder, load_ptr0, "");
1242 trbl = LLVMBuildLoad(ctx->builder, load_ptr1, "");
1243 }
1244 tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
1245 trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
1246 result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
1247 return result;
1248 }
1249
1250 /*
1251 * this takes an I,J coordinate pair,
1252 * and works out the X and Y derivatives.
1253 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1254 */
1255 static LLVMValueRef emit_ddxy_interp(
1256 struct nir_to_llvm_context *ctx,
1257 LLVMValueRef interp_ij)
1258 {
1259 LLVMValueRef result[4], a;
1260 unsigned i;
1261
1262 for (i = 0; i < 2; i++) {
1263 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1264 LLVMConstInt(ctx->i32, i, false), "");
1265 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1266 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1267 }
1268 return ac_build_gather_values(&ctx->ac, result, 4);
1269 }
1270
1271 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1272 {
1273 LLVMValueRef src[4], result = NULL;
1274 unsigned num_components = instr->dest.dest.ssa.num_components;
1275 unsigned src_components;
1276
1277 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1278 switch (instr->op) {
1279 case nir_op_vec2:
1280 case nir_op_vec3:
1281 case nir_op_vec4:
1282 src_components = 1;
1283 break;
1284 case nir_op_pack_half_2x16:
1285 src_components = 2;
1286 break;
1287 case nir_op_unpack_half_2x16:
1288 src_components = 1;
1289 break;
1290 default:
1291 src_components = num_components;
1292 break;
1293 }
1294 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1295 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1296
1297 switch (instr->op) {
1298 case nir_op_fmov:
1299 case nir_op_imov:
1300 result = src[0];
1301 break;
1302 case nir_op_fneg:
1303 src[0] = to_float(ctx, src[0]);
1304 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1305 break;
1306 case nir_op_ineg:
1307 result = LLVMBuildNeg(ctx->builder, src[0], "");
1308 break;
1309 case nir_op_inot:
1310 result = LLVMBuildNot(ctx->builder, src[0], "");
1311 break;
1312 case nir_op_iadd:
1313 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1314 break;
1315 case nir_op_fadd:
1316 src[0] = to_float(ctx, src[0]);
1317 src[1] = to_float(ctx, src[1]);
1318 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1319 break;
1320 case nir_op_fsub:
1321 src[0] = to_float(ctx, src[0]);
1322 src[1] = to_float(ctx, src[1]);
1323 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1324 break;
1325 case nir_op_isub:
1326 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1327 break;
1328 case nir_op_imul:
1329 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1330 break;
1331 case nir_op_imod:
1332 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1333 break;
1334 case nir_op_umod:
1335 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1336 break;
1337 case nir_op_fmod:
1338 src[0] = to_float(ctx, src[0]);
1339 src[1] = to_float(ctx, src[1]);
1340 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1341 result = emit_intrin_1f_param(ctx, "llvm.floor.f32", result);
1342 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1343 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1344 break;
1345 case nir_op_frem:
1346 src[0] = to_float(ctx, src[0]);
1347 src[1] = to_float(ctx, src[1]);
1348 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1349 break;
1350 case nir_op_irem:
1351 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1352 break;
1353 case nir_op_idiv:
1354 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1355 break;
1356 case nir_op_udiv:
1357 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1358 break;
1359 case nir_op_fmul:
1360 src[0] = to_float(ctx, src[0]);
1361 src[1] = to_float(ctx, src[1]);
1362 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1363 break;
1364 case nir_op_fdiv:
1365 src[0] = to_float(ctx, src[0]);
1366 src[1] = to_float(ctx, src[1]);
1367 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1368 break;
1369 case nir_op_frcp:
1370 src[0] = to_float(ctx, src[0]);
1371 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1372 break;
1373 case nir_op_iand:
1374 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1375 break;
1376 case nir_op_ior:
1377 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1378 break;
1379 case nir_op_ixor:
1380 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1381 break;
1382 case nir_op_ishl:
1383 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1384 break;
1385 case nir_op_ishr:
1386 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1387 break;
1388 case nir_op_ushr:
1389 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1390 break;
1391 case nir_op_ilt:
1392 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1393 break;
1394 case nir_op_ine:
1395 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1396 break;
1397 case nir_op_ieq:
1398 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1399 break;
1400 case nir_op_ige:
1401 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1402 break;
1403 case nir_op_ult:
1404 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1405 break;
1406 case nir_op_uge:
1407 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1408 break;
1409 case nir_op_feq:
1410 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1411 break;
1412 case nir_op_fne:
1413 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1414 break;
1415 case nir_op_flt:
1416 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1417 break;
1418 case nir_op_fge:
1419 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1420 break;
1421 case nir_op_fabs:
1422 result = emit_intrin_1f_param(ctx, "llvm.fabs.f32", src[0]);
1423 break;
1424 case nir_op_iabs:
1425 result = emit_iabs(ctx, src[0]);
1426 break;
1427 case nir_op_imax:
1428 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1429 break;
1430 case nir_op_imin:
1431 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1432 break;
1433 case nir_op_umax:
1434 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1435 break;
1436 case nir_op_umin:
1437 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1438 break;
1439 case nir_op_isign:
1440 result = emit_isign(ctx, src[0]);
1441 break;
1442 case nir_op_fsign:
1443 src[0] = to_float(ctx, src[0]);
1444 result = emit_fsign(ctx, src[0]);
1445 break;
1446 case nir_op_ffloor:
1447 result = emit_intrin_1f_param(ctx, "llvm.floor.f32", src[0]);
1448 break;
1449 case nir_op_ftrunc:
1450 result = emit_intrin_1f_param(ctx, "llvm.trunc.f32", src[0]);
1451 break;
1452 case nir_op_fceil:
1453 result = emit_intrin_1f_param(ctx, "llvm.ceil.f32", src[0]);
1454 break;
1455 case nir_op_fround_even:
1456 result = emit_intrin_1f_param(ctx, "llvm.rint.f32", src[0]);
1457 break;
1458 case nir_op_ffract:
1459 result = emit_ffract(ctx, src[0]);
1460 break;
1461 case nir_op_fsin:
1462 result = emit_intrin_1f_param(ctx, "llvm.sin.f32", src[0]);
1463 break;
1464 case nir_op_fcos:
1465 result = emit_intrin_1f_param(ctx, "llvm.cos.f32", src[0]);
1466 break;
1467 case nir_op_fsqrt:
1468 result = emit_intrin_1f_param(ctx, "llvm.sqrt.f32", src[0]);
1469 break;
1470 case nir_op_fexp2:
1471 result = emit_intrin_1f_param(ctx, "llvm.exp2.f32", src[0]);
1472 break;
1473 case nir_op_flog2:
1474 result = emit_intrin_1f_param(ctx, "llvm.log2.f32", src[0]);
1475 break;
1476 case nir_op_frsq:
1477 result = emit_intrin_1f_param(ctx, "llvm.sqrt.f32", src[0]);
1478 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1479 break;
1480 case nir_op_fpow:
1481 result = emit_intrin_2f_param(ctx, "llvm.pow.f32", src[0], src[1]);
1482 break;
1483 case nir_op_fmax:
1484 result = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", src[0], src[1]);
1485 break;
1486 case nir_op_fmin:
1487 result = emit_intrin_2f_param(ctx, "llvm.minnum.f32", src[0], src[1]);
1488 break;
1489 case nir_op_ffma:
1490 result = emit_intrin_3f_param(ctx, "llvm.fma.f32", src[0], src[1], src[2]);
1491 break;
1492 case nir_op_ibitfield_extract:
1493 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1494 break;
1495 case nir_op_ubitfield_extract:
1496 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1497 break;
1498 case nir_op_bitfield_insert:
1499 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1500 break;
1501 case nir_op_bitfield_reverse:
1502 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1503 break;
1504 case nir_op_bit_count:
1505 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1506 break;
1507 case nir_op_vec2:
1508 case nir_op_vec3:
1509 case nir_op_vec4:
1510 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1511 src[i] = to_integer(ctx, src[i]);
1512 result = ac_build_gather_values(&ctx->ac, src, num_components);
1513 break;
1514 case nir_op_f2i:
1515 src[0] = to_float(ctx, src[0]);
1516 result = LLVMBuildFPToSI(ctx->builder, src[0], ctx->i32, "");
1517 break;
1518 case nir_op_f2u:
1519 src[0] = to_float(ctx, src[0]);
1520 result = LLVMBuildFPToUI(ctx->builder, src[0], ctx->i32, "");
1521 break;
1522 case nir_op_i2f:
1523 result = LLVMBuildSIToFP(ctx->builder, src[0], ctx->f32, "");
1524 break;
1525 case nir_op_u2f:
1526 result = LLVMBuildUIToFP(ctx->builder, src[0], ctx->f32, "");
1527 break;
1528 case nir_op_bcsel:
1529 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1530 break;
1531 case nir_op_find_lsb:
1532 result = emit_find_lsb(ctx, src[0]);
1533 break;
1534 case nir_op_ufind_msb:
1535 result = emit_ufind_msb(ctx, src[0]);
1536 break;
1537 case nir_op_ifind_msb:
1538 result = emit_ifind_msb(ctx, src[0]);
1539 break;
1540 case nir_op_uadd_carry:
1541 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1542 break;
1543 case nir_op_usub_borrow:
1544 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1545 break;
1546 case nir_op_b2f:
1547 result = emit_b2f(ctx, src[0]);
1548 break;
1549 case nir_op_fquantize2f16:
1550 src[0] = to_float(ctx, src[0]);
1551 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1552 /* need to convert back up to f32 */
1553 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1554 break;
1555 case nir_op_umul_high:
1556 result = emit_umul_high(ctx, src[0], src[1]);
1557 break;
1558 case nir_op_imul_high:
1559 result = emit_imul_high(ctx, src[0], src[1]);
1560 break;
1561 case nir_op_pack_half_2x16:
1562 result = emit_pack_half_2x16(ctx, src[0]);
1563 break;
1564 case nir_op_unpack_half_2x16:
1565 result = emit_unpack_half_2x16(ctx, src[0]);
1566 break;
1567 case nir_op_fddx:
1568 case nir_op_fddy:
1569 case nir_op_fddx_fine:
1570 case nir_op_fddy_fine:
1571 case nir_op_fddx_coarse:
1572 case nir_op_fddy_coarse:
1573 result = emit_ddxy(ctx, instr->op, src[0]);
1574 break;
1575 default:
1576 fprintf(stderr, "Unknown NIR alu instr: ");
1577 nir_print_instr(&instr->instr, stderr);
1578 fprintf(stderr, "\n");
1579 abort();
1580 }
1581
1582 if (result) {
1583 assert(instr->dest.dest.is_ssa);
1584 result = to_integer(ctx, result);
1585 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1586 result);
1587 }
1588 }
1589
1590 static void visit_load_const(struct nir_to_llvm_context *ctx,
1591 nir_load_const_instr *instr)
1592 {
1593 LLVMValueRef values[4], value = NULL;
1594 LLVMTypeRef element_type =
1595 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1596
1597 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1598 switch (instr->def.bit_size) {
1599 case 32:
1600 values[i] = LLVMConstInt(element_type,
1601 instr->value.u32[i], false);
1602 break;
1603 case 64:
1604 values[i] = LLVMConstInt(element_type,
1605 instr->value.u64[i], false);
1606 break;
1607 default:
1608 fprintf(stderr,
1609 "unsupported nir load_const bit_size: %d\n",
1610 instr->def.bit_size);
1611 abort();
1612 }
1613 }
1614 if (instr->def.num_components > 1) {
1615 value = LLVMConstVector(values, instr->def.num_components);
1616 } else
1617 value = values[0];
1618
1619 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1620 }
1621
1622 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1623 LLVMTypeRef type)
1624 {
1625 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1626 return LLVMBuildBitCast(ctx->builder, ptr,
1627 LLVMPointerType(type, addr_space), "");
1628 }
1629
1630 static LLVMValueRef
1631 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1632 {
1633 LLVMValueRef size =
1634 LLVMBuildExtractElement(ctx->builder, descriptor,
1635 LLVMConstInt(ctx->i32, 2, false), "");
1636
1637 /* VI only */
1638 if (ctx->options->chip_class >= VI && in_elements) {
1639 /* On VI, the descriptor contains the size in bytes,
1640 * but TXQ must return the size in elements.
1641 * The stride is always non-zero for resources using TXQ.
1642 */
1643 LLVMValueRef stride =
1644 LLVMBuildExtractElement(ctx->builder, descriptor,
1645 LLVMConstInt(ctx->i32, 1, false), "");
1646 stride = LLVMBuildLShr(ctx->builder, stride,
1647 LLVMConstInt(ctx->i32, 16, false), "");
1648 stride = LLVMBuildAnd(ctx->builder, stride,
1649 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1650
1651 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1652 }
1653 return size;
1654 }
1655
1656 /**
1657 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1658 * intrinsic names).
1659 */
1660 static void build_int_type_name(
1661 LLVMTypeRef type,
1662 char *buf, unsigned bufsize)
1663 {
1664 assert(bufsize >= 6);
1665
1666 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1667 snprintf(buf, bufsize, "v%ui32",
1668 LLVMGetVectorSize(type));
1669 else
1670 strcpy(buf, "i32");
1671 }
1672
1673 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1674 struct ac_tex_info *tinfo,
1675 nir_tex_instr *instr,
1676 const char *intr_name,
1677 unsigned coord_vgpr_index)
1678 {
1679 LLVMValueRef coord = tinfo->args[0];
1680 LLVMValueRef half_texel[2];
1681 int c;
1682
1683 //TODO Rect
1684 {
1685 LLVMValueRef txq_args[10];
1686 int txq_arg_count = 0;
1687 LLVMValueRef size;
1688 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1689 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1690 txq_args[txq_arg_count++] = tinfo->args[1];
1691 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1692 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1693 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1694 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1695 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1696 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1697 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1698 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1699 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1700 txq_args, txq_arg_count,
1701 AC_FUNC_ATTR_READNONE);
1702
1703 for (c = 0; c < 2; c++) {
1704 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1705 LLVMConstInt(ctx->i32, c, false), "");
1706 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1707 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1708 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1709 LLVMConstReal(ctx->f32, -0.5), "");
1710 }
1711 }
1712
1713 for (c = 0; c < 2; c++) {
1714 LLVMValueRef tmp;
1715 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1716 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1717 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1718 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1719 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1720 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1721 }
1722
1723 tinfo->args[0] = coord;
1724 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1725 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1726
1727 }
1728
1729 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1730 nir_tex_instr *instr,
1731 struct ac_tex_info *tinfo)
1732 {
1733 const char *name = "llvm.SI.image.sample";
1734 const char *infix = "";
1735 char intr_name[127];
1736 char type[64];
1737 bool is_shadow = instr->is_shadow;
1738 bool has_offset = tinfo->has_offset;
1739 switch (instr->op) {
1740 case nir_texop_txf:
1741 case nir_texop_txf_ms:
1742 case nir_texop_samples_identical:
1743 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1744 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1745 "llvm.SI.image.load.mip";
1746 is_shadow = false;
1747 has_offset = false;
1748 break;
1749 case nir_texop_txb:
1750 infix = ".b";
1751 break;
1752 case nir_texop_txl:
1753 infix = ".l";
1754 break;
1755 case nir_texop_txs:
1756 name = "llvm.SI.getresinfo";
1757 break;
1758 case nir_texop_query_levels:
1759 name = "llvm.SI.getresinfo";
1760 break;
1761 case nir_texop_tex:
1762 if (ctx->stage != MESA_SHADER_FRAGMENT)
1763 infix = ".lz";
1764 break;
1765 case nir_texop_txd:
1766 infix = ".d";
1767 break;
1768 case nir_texop_tg4:
1769 name = "llvm.SI.gather4";
1770 infix = ".lz";
1771 break;
1772 case nir_texop_lod:
1773 name = "llvm.SI.getlod";
1774 is_shadow = false;
1775 has_offset = false;
1776 break;
1777 default:
1778 break;
1779 }
1780
1781 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1782 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1783 has_offset ? ".o" : "", type);
1784
1785 if (instr->op == nir_texop_tg4) {
1786 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1787 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1788 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1789 (int)has_offset + (int)is_shadow);
1790 }
1791 }
1792 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1793 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1794
1795 }
1796
1797 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1798 nir_intrinsic_instr *instr)
1799 {
1800 LLVMValueRef index = get_src(ctx, instr->src[0]);
1801 unsigned desc_set = nir_intrinsic_desc_set(instr);
1802 unsigned binding = nir_intrinsic_binding(instr);
1803 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1804 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1805 unsigned base_offset = layout->binding[binding].offset;
1806 LLVMValueRef offset, stride;
1807
1808 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1809 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1810 desc_ptr = ctx->push_constants;
1811 base_offset = ctx->options->layout->push_constant_size;
1812 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1813 stride = LLVMConstInt(ctx->i32, 16, false);
1814 } else
1815 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1816
1817 offset = LLVMConstInt(ctx->i32, base_offset, false);
1818 index = LLVMBuildMul(ctx->builder, index, stride, "");
1819 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1820
1821 desc_ptr = build_gep0(ctx, desc_ptr, offset);
1822 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1823 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1824
1825 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1826 }
1827
1828 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1829 nir_intrinsic_instr *instr)
1830 {
1831 LLVMValueRef ptr, addr;
1832
1833 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1834 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1835
1836 ptr = build_gep0(ctx, ctx->push_constants, addr);
1837 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1838
1839 return LLVMBuildLoad(ctx->builder, ptr, "");
1840 }
1841
1842 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1843 nir_intrinsic_instr *instr)
1844 {
1845 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1846
1847 return get_buffer_size(ctx, desc, false);
1848 }
1849 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1850 nir_intrinsic_instr *instr)
1851 {
1852 const char *store_name;
1853 LLVMTypeRef data_type = ctx->f32;
1854 unsigned writemask = nir_intrinsic_write_mask(instr);
1855 LLVMValueRef base_data, base_offset;
1856 LLVMValueRef params[6];
1857
1858 if (ctx->stage == MESA_SHADER_FRAGMENT)
1859 ctx->shader_info->fs.writes_memory = true;
1860
1861 params[1] = get_src(ctx, instr->src[1]);
1862 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1863 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1864 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1865
1866 if (instr->num_components > 1)
1867 data_type = LLVMVectorType(ctx->f32, instr->num_components);
1868
1869 base_data = to_float(ctx, get_src(ctx, instr->src[0]));
1870 base_data = trim_vector(ctx, base_data, instr->num_components);
1871 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1872 data_type, "");
1873 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1874 while (writemask) {
1875 int start, count;
1876 LLVMValueRef data;
1877 LLVMValueRef offset;
1878 LLVMValueRef tmp;
1879 u_bit_scan_consecutive_range(&writemask, &start, &count);
1880
1881 /* Due to an LLVM limitation, split 3-element writes
1882 * into a 2-element and a 1-element write. */
1883 if (count == 3) {
1884 writemask |= 1 << (start + 2);
1885 count = 2;
1886 }
1887
1888 if (count == 4) {
1889 store_name = "llvm.amdgcn.buffer.store.v4f32";
1890 data = base_data;
1891 } else if (count == 2) {
1892 tmp = LLVMBuildExtractElement(ctx->builder,
1893 base_data, LLVMConstInt(ctx->i32, start, false), "");
1894 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1895 ctx->i32zero, "");
1896
1897 tmp = LLVMBuildExtractElement(ctx->builder,
1898 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1899 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1900 ctx->i32one, "");
1901 store_name = "llvm.amdgcn.buffer.store.v2f32";
1902
1903 } else {
1904 assert(count == 1);
1905 if (get_llvm_num_components(base_data) > 1)
1906 data = LLVMBuildExtractElement(ctx->builder, base_data,
1907 LLVMConstInt(ctx->i32, start, false), "");
1908 else
1909 data = base_data;
1910 store_name = "llvm.amdgcn.buffer.store.f32";
1911 }
1912
1913 offset = base_offset;
1914 if (start != 0) {
1915 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1916 }
1917 params[0] = data;
1918 params[3] = offset;
1919 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1920 ctx->voidt, params, 6, 0);
1921 }
1922 }
1923
1924 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1925 nir_intrinsic_instr *instr)
1926 {
1927 const char *name;
1928 LLVMValueRef params[6];
1929 int arg_count = 0;
1930 if (ctx->stage == MESA_SHADER_FRAGMENT)
1931 ctx->shader_info->fs.writes_memory = true;
1932
1933 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1934 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1935 }
1936 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1937 params[arg_count++] = get_src(ctx, instr->src[0]);
1938 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1939 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1940 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1941
1942 switch (instr->intrinsic) {
1943 case nir_intrinsic_ssbo_atomic_add:
1944 name = "llvm.amdgcn.buffer.atomic.add";
1945 break;
1946 case nir_intrinsic_ssbo_atomic_imin:
1947 name = "llvm.amdgcn.buffer.atomic.smin";
1948 break;
1949 case nir_intrinsic_ssbo_atomic_umin:
1950 name = "llvm.amdgcn.buffer.atomic.umin";
1951 break;
1952 case nir_intrinsic_ssbo_atomic_imax:
1953 name = "llvm.amdgcn.buffer.atomic.smax";
1954 break;
1955 case nir_intrinsic_ssbo_atomic_umax:
1956 name = "llvm.amdgcn.buffer.atomic.umax";
1957 break;
1958 case nir_intrinsic_ssbo_atomic_and:
1959 name = "llvm.amdgcn.buffer.atomic.and";
1960 break;
1961 case nir_intrinsic_ssbo_atomic_or:
1962 name = "llvm.amdgcn.buffer.atomic.or";
1963 break;
1964 case nir_intrinsic_ssbo_atomic_xor:
1965 name = "llvm.amdgcn.buffer.atomic.xor";
1966 break;
1967 case nir_intrinsic_ssbo_atomic_exchange:
1968 name = "llvm.amdgcn.buffer.atomic.swap";
1969 break;
1970 case nir_intrinsic_ssbo_atomic_comp_swap:
1971 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1972 break;
1973 default:
1974 abort();
1975 }
1976
1977 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1978 }
1979
1980 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1981 nir_intrinsic_instr *instr)
1982 {
1983 const char *load_name;
1984 LLVMTypeRef data_type = ctx->f32;
1985 if (instr->num_components == 3)
1986 data_type = LLVMVectorType(ctx->f32, 4);
1987 else if (instr->num_components > 1)
1988 data_type = LLVMVectorType(ctx->f32, instr->num_components);
1989
1990 if (instr->num_components == 4 || instr->num_components == 3)
1991 load_name = "llvm.amdgcn.buffer.load.v4f32";
1992 else if (instr->num_components == 2)
1993 load_name = "llvm.amdgcn.buffer.load.v2f32";
1994 else if (instr->num_components == 1)
1995 load_name = "llvm.amdgcn.buffer.load.f32";
1996 else
1997 abort();
1998
1999 LLVMValueRef params[] = {
2000 get_src(ctx, instr->src[0]),
2001 LLVMConstInt(ctx->i32, 0, false),
2002 get_src(ctx, instr->src[1]),
2003 LLVMConstInt(ctx->i1, 0, false),
2004 LLVMConstInt(ctx->i1, 0, false),
2005 };
2006
2007 LLVMValueRef ret =
2008 ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2009
2010 if (instr->num_components == 3)
2011 ret = trim_vector(ctx, ret, 3);
2012
2013 return LLVMBuildBitCast(ctx->builder, ret,
2014 get_def_type(ctx, &instr->dest.ssa), "");
2015 }
2016
2017 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2018 nir_intrinsic_instr *instr)
2019 {
2020 LLVMValueRef results[4], ret;
2021 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2022 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2023
2024 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2025
2026 for (unsigned i = 0; i < instr->num_components; ++i) {
2027 LLVMValueRef params[] = {
2028 rsrc,
2029 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2030 offset, "")
2031 };
2032 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2033 params, 2, AC_FUNC_ATTR_READNONE);
2034 }
2035
2036
2037 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2038 return LLVMBuildBitCast(ctx->builder, ret,
2039 get_def_type(ctx, &instr->dest.ssa), "");
2040 }
2041
2042 static void
2043 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2044 bool vs_in, unsigned *const_out, LLVMValueRef *indir_out)
2045 {
2046 unsigned const_offset = 0;
2047 LLVMValueRef offset = NULL;
2048
2049
2050 while (tail->child != NULL) {
2051 const struct glsl_type *parent_type = tail->type;
2052 tail = tail->child;
2053
2054 if (tail->deref_type == nir_deref_type_array) {
2055 nir_deref_array *deref_array = nir_deref_as_array(tail);
2056 LLVMValueRef index, stride, local_offset;
2057 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2058
2059 const_offset += size * deref_array->base_offset;
2060 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2061 continue;
2062
2063 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2064 index = get_src(ctx, deref_array->indirect);
2065 stride = LLVMConstInt(ctx->i32, size, 0);
2066 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2067
2068 if (offset)
2069 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2070 else
2071 offset = local_offset;
2072 } else if (tail->deref_type == nir_deref_type_struct) {
2073 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2074
2075 for (unsigned i = 0; i < deref_struct->index; i++) {
2076 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2077 const_offset += glsl_count_attribute_slots(ft, vs_in);
2078 }
2079 } else
2080 unreachable("unsupported deref type");
2081
2082 }
2083
2084 if (const_offset && offset)
2085 offset = LLVMBuildAdd(ctx->builder, offset,
2086 LLVMConstInt(ctx->i32, const_offset, 0),
2087 "");
2088
2089 *const_out = const_offset;
2090 *indir_out = offset;
2091 }
2092
2093 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2094 nir_intrinsic_instr *instr)
2095 {
2096 LLVMValueRef values[4];
2097 int idx = instr->variables[0]->var->data.driver_location;
2098 int ve = instr->dest.ssa.num_components;
2099 LLVMValueRef indir_index;
2100 unsigned const_index;
2101 switch (instr->variables[0]->var->data.mode) {
2102 case nir_var_shader_in:
2103 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2104 ctx->stage == MESA_SHADER_VERTEX,
2105 &const_index, &indir_index);
2106 for (unsigned chan = 0; chan < ve; chan++) {
2107 if (indir_index) {
2108 unsigned count = glsl_count_attribute_slots(
2109 instr->variables[0]->var->type,
2110 ctx->stage == MESA_SHADER_VERTEX);
2111 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2112 &ctx->ac, ctx->inputs + idx + chan, count,
2113 4, false);
2114
2115 values[chan] = LLVMBuildExtractElement(ctx->builder,
2116 tmp_vec,
2117 indir_index, "");
2118 } else
2119 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2120 }
2121 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2122 break;
2123 case nir_var_local:
2124 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2125 &const_index, &indir_index);
2126 for (unsigned chan = 0; chan < ve; chan++) {
2127 if (indir_index) {
2128 unsigned count = glsl_count_attribute_slots(
2129 instr->variables[0]->var->type, false);
2130 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2131 &ctx->ac, ctx->locals + idx + chan, count,
2132 4, true);
2133
2134 values[chan] = LLVMBuildExtractElement(ctx->builder,
2135 tmp_vec,
2136 indir_index, "");
2137 } else {
2138 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2139 }
2140 }
2141 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2142 case nir_var_shader_out:
2143 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2144 &const_index, &indir_index);
2145 for (unsigned chan = 0; chan < ve; chan++) {
2146 if (indir_index) {
2147 unsigned count = glsl_count_attribute_slots(
2148 instr->variables[0]->var->type, false);
2149 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2150 &ctx->ac, ctx->outputs + idx + chan, count,
2151 4, true);
2152
2153 values[chan] = LLVMBuildExtractElement(ctx->builder,
2154 tmp_vec,
2155 indir_index, "");
2156 } else {
2157 values[chan] = LLVMBuildLoad(ctx->builder,
2158 ctx->outputs[idx + chan + const_index * 4],
2159 "");
2160 }
2161 }
2162 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2163 case nir_var_shared: {
2164 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2165 &const_index, &indir_index);
2166 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2167 LLVMValueRef derived_ptr;
2168
2169 for (unsigned chan = 0; chan < ve; chan++) {
2170 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2171 if (indir_index)
2172 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2173 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2174 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2175 }
2176 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2177 }
2178 default:
2179 break;
2180 }
2181 return NULL;
2182 }
2183
2184 static void
2185 visit_store_var(struct nir_to_llvm_context *ctx,
2186 nir_intrinsic_instr *instr)
2187 {
2188 LLVMValueRef temp_ptr, value;
2189 int idx = instr->variables[0]->var->data.driver_location;
2190 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2191 int writemask = instr->const_index[0];
2192 LLVMValueRef indir_index;
2193 unsigned const_index;
2194 switch (instr->variables[0]->var->data.mode) {
2195 case nir_var_shader_out:
2196 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2197 &const_index, &indir_index);
2198 for (unsigned chan = 0; chan < 4; chan++) {
2199 int stride = 4;
2200 if (!(writemask & (1 << chan)))
2201 continue;
2202 if (get_llvm_num_components(src) == 1)
2203 value = src;
2204 else
2205 value = LLVMBuildExtractElement(ctx->builder, src,
2206 LLVMConstInt(ctx->i32,
2207 chan, false),
2208 "");
2209
2210 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2211 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2212 stride = 1;
2213 if (indir_index) {
2214 unsigned count = glsl_count_attribute_slots(
2215 instr->variables[0]->var->type, false);
2216 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2217 &ctx->ac, ctx->outputs + idx + chan, count,
2218 stride, true);
2219
2220 if (get_llvm_num_components(tmp_vec) > 1) {
2221 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2222 value, indir_index, "");
2223 } else
2224 tmp_vec = value;
2225 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2226 count, stride, tmp_vec);
2227
2228 } else {
2229 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2230
2231 LLVMBuildStore(ctx->builder, value, temp_ptr);
2232 }
2233 }
2234 break;
2235 case nir_var_local:
2236 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2237 &const_index, &indir_index);
2238 for (unsigned chan = 0; chan < 4; chan++) {
2239 if (!(writemask & (1 << chan)))
2240 continue;
2241
2242 if (get_llvm_num_components(src) == 1)
2243 value = src;
2244 else
2245 value = LLVMBuildExtractElement(ctx->builder, src,
2246 LLVMConstInt(ctx->i32, chan, false), "");
2247 if (indir_index) {
2248 unsigned count = glsl_count_attribute_slots(
2249 instr->variables[0]->var->type, false);
2250 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2251 &ctx->ac, ctx->locals + idx + chan, count,
2252 4, true);
2253
2254 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2255 value, indir_index, "");
2256 build_store_values_extended(ctx, ctx->locals + idx + chan,
2257 count, 4, tmp_vec);
2258 } else {
2259 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2260
2261 LLVMBuildStore(ctx->builder, value, temp_ptr);
2262 }
2263 }
2264 break;
2265 case nir_var_shared: {
2266 LLVMValueRef ptr;
2267 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2268 &const_index, &indir_index);
2269
2270 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2271 LLVMValueRef derived_ptr;
2272
2273 for (unsigned chan = 0; chan < 4; chan++) {
2274 if (!(writemask & (1 << chan)))
2275 continue;
2276
2277 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2278
2279 if (get_llvm_num_components(src) == 1)
2280 value = src;
2281 else
2282 value = LLVMBuildExtractElement(ctx->builder, src,
2283 LLVMConstInt(ctx->i32,
2284 chan, false),
2285 "");
2286
2287 if (indir_index)
2288 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2289
2290 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2291 LLVMBuildStore(ctx->builder,
2292 to_integer(ctx, value), derived_ptr);
2293 }
2294 break;
2295 }
2296 default:
2297 break;
2298 }
2299 }
2300
2301 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2302 {
2303 switch (dim) {
2304 case GLSL_SAMPLER_DIM_BUF:
2305 return 1;
2306 case GLSL_SAMPLER_DIM_1D:
2307 return array ? 2 : 1;
2308 case GLSL_SAMPLER_DIM_2D:
2309 return array ? 3 : 2;
2310 case GLSL_SAMPLER_DIM_MS:
2311 return array ? 4 : 3;
2312 case GLSL_SAMPLER_DIM_3D:
2313 case GLSL_SAMPLER_DIM_CUBE:
2314 return 3;
2315 case GLSL_SAMPLER_DIM_RECT:
2316 case GLSL_SAMPLER_DIM_SUBPASS:
2317 return 2;
2318 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2319 return 3;
2320 default:
2321 break;
2322 }
2323 return 0;
2324 }
2325
2326 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2327 nir_intrinsic_instr *instr)
2328 {
2329 const struct glsl_type *type = instr->variables[0]->var->type;
2330 if(instr->variables[0]->deref.child)
2331 type = instr->variables[0]->deref.child->type;
2332
2333 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2334 LLVMValueRef coords[4];
2335 LLVMValueRef masks[] = {
2336 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2337 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2338 };
2339 LLVMValueRef res;
2340 int count;
2341 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2342 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2343 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2344 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2345 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2346
2347 count = image_type_to_components_count(dim,
2348 glsl_sampler_type_is_array(type));
2349
2350 if (count == 1) {
2351 if (instr->src[0].ssa->num_components)
2352 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2353 else
2354 res = src0;
2355 } else {
2356 int chan;
2357 if (is_ms)
2358 count--;
2359 for (chan = 0; chan < count; ++chan) {
2360 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2361 }
2362
2363 if (add_frag_pos) {
2364 for (chan = 0; chan < count; ++chan)
2365 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2366 }
2367 if (is_ms) {
2368 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2369 count++;
2370 }
2371
2372 if (count == 3) {
2373 coords[3] = LLVMGetUndef(ctx->i32);
2374 count = 4;
2375 }
2376 res = ac_build_gather_values(&ctx->ac, coords, count);
2377 }
2378 return res;
2379 }
2380
2381 static void build_type_name_for_intr(
2382 LLVMTypeRef type,
2383 char *buf, unsigned bufsize)
2384 {
2385 LLVMTypeRef elem_type = type;
2386
2387 assert(bufsize >= 8);
2388
2389 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2390 int ret = snprintf(buf, bufsize, "v%u",
2391 LLVMGetVectorSize(type));
2392 if (ret < 0) {
2393 char *type_name = LLVMPrintTypeToString(type);
2394 fprintf(stderr, "Error building type name for: %s\n",
2395 type_name);
2396 return;
2397 }
2398 elem_type = LLVMGetElementType(type);
2399 buf += ret;
2400 bufsize -= ret;
2401 }
2402 switch (LLVMGetTypeKind(elem_type)) {
2403 default: break;
2404 case LLVMIntegerTypeKind:
2405 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2406 break;
2407 case LLVMFloatTypeKind:
2408 snprintf(buf, bufsize, "f32");
2409 break;
2410 case LLVMDoubleTypeKind:
2411 snprintf(buf, bufsize, "f64");
2412 break;
2413 }
2414 }
2415
2416 static void get_image_intr_name(const char *base_name,
2417 LLVMTypeRef data_type,
2418 LLVMTypeRef coords_type,
2419 LLVMTypeRef rsrc_type,
2420 char *out_name, unsigned out_len)
2421 {
2422 char coords_type_name[8];
2423
2424 build_type_name_for_intr(coords_type, coords_type_name,
2425 sizeof(coords_type_name));
2426
2427 if (HAVE_LLVM <= 0x0309) {
2428 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2429 } else {
2430 char data_type_name[8];
2431 char rsrc_type_name[8];
2432
2433 build_type_name_for_intr(data_type, data_type_name,
2434 sizeof(data_type_name));
2435 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2436 sizeof(rsrc_type_name));
2437 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2438 data_type_name, coords_type_name, rsrc_type_name);
2439 }
2440 }
2441
2442 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2443 nir_intrinsic_instr *instr)
2444 {
2445 LLVMValueRef params[7];
2446 LLVMValueRef res;
2447 char intrinsic_name[64];
2448 const nir_variable *var = instr->variables[0]->var;
2449 const struct glsl_type *type = var->type;
2450 if(instr->variables[0]->deref.child)
2451 type = instr->variables[0]->deref.child->type;
2452
2453 type = glsl_without_array(type);
2454 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2455 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2456 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2457 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2458 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2459 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2460 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2461 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2462 params, 5, 0);
2463
2464 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2465 res = to_integer(ctx, res);
2466 } else {
2467 bool is_da = glsl_sampler_type_is_array(type) ||
2468 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2469 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2470 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2471 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2472
2473 params[0] = get_image_coords(ctx, instr);
2474 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2475 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2476 if (HAVE_LLVM <= 0x0309) {
2477 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2478 params[4] = da;
2479 params[5] = glc;
2480 params[6] = slc;
2481 } else {
2482 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2483 params[3] = glc;
2484 params[4] = slc;
2485 params[5] = lwe;
2486 params[6] = da;
2487 }
2488
2489 get_image_intr_name("llvm.amdgcn.image.load",
2490 ctx->v4f32, /* vdata */
2491 LLVMTypeOf(params[0]), /* coords */
2492 LLVMTypeOf(params[1]), /* rsrc */
2493 intrinsic_name, sizeof(intrinsic_name));
2494
2495 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2496 params, 7, AC_FUNC_ATTR_READONLY);
2497 }
2498 return to_integer(ctx, res);
2499 }
2500
2501 static void visit_image_store(struct nir_to_llvm_context *ctx,
2502 nir_intrinsic_instr *instr)
2503 {
2504 LLVMValueRef params[8];
2505 char intrinsic_name[64];
2506 const nir_variable *var = instr->variables[0]->var;
2507 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2508 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2509 const struct glsl_type *type = glsl_without_array(var->type);
2510
2511 if (ctx->stage == MESA_SHADER_FRAGMENT)
2512 ctx->shader_info->fs.writes_memory = true;
2513
2514 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2515 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2516 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2517 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2518 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2519 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2520 params[4] = i1false; /* glc */
2521 params[5] = i1false; /* slc */
2522 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2523 params, 6, 0);
2524 } else {
2525 bool is_da = glsl_sampler_type_is_array(type) ||
2526 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2527 LLVMValueRef da = is_da ? i1true : i1false;
2528 LLVMValueRef glc = i1false;
2529 LLVMValueRef slc = i1false;
2530
2531 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2532 params[1] = get_image_coords(ctx, instr); /* coords */
2533 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2534 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2535 if (HAVE_LLVM <= 0x0309) {
2536 params[4] = i1false; /* r128 */
2537 params[5] = da;
2538 params[6] = glc;
2539 params[7] = slc;
2540 } else {
2541 LLVMValueRef lwe = i1false;
2542 params[4] = glc;
2543 params[5] = slc;
2544 params[6] = lwe;
2545 params[7] = da;
2546 }
2547
2548 get_image_intr_name("llvm.amdgcn.image.store",
2549 LLVMTypeOf(params[0]), /* vdata */
2550 LLVMTypeOf(params[1]), /* coords */
2551 LLVMTypeOf(params[2]), /* rsrc */
2552 intrinsic_name, sizeof(intrinsic_name));
2553
2554 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2555 params, 8, 0);
2556 }
2557
2558 }
2559
2560 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2561 nir_intrinsic_instr *instr)
2562 {
2563 LLVMValueRef params[6];
2564 int param_count = 0;
2565 const nir_variable *var = instr->variables[0]->var;
2566 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2567 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2568 const char *base_name = "llvm.amdgcn.image.atomic";
2569 const char *atomic_name;
2570 LLVMValueRef coords;
2571 char intrinsic_name[32], coords_type[8];
2572 const struct glsl_type *type = glsl_without_array(var->type);
2573
2574 if (ctx->stage == MESA_SHADER_FRAGMENT)
2575 ctx->shader_info->fs.writes_memory = true;
2576
2577 params[param_count++] = get_src(ctx, instr->src[2]);
2578 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2579 params[param_count++] = get_src(ctx, instr->src[3]);
2580
2581 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2582 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2583 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2584 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2585 params[param_count++] = ctx->i32zero; /* voffset */
2586 params[param_count++] = i1false; /* glc */
2587 params[param_count++] = i1false; /* slc */
2588 } else {
2589 bool da = glsl_sampler_type_is_array(type) ||
2590 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2591
2592 coords = params[param_count++] = get_image_coords(ctx, instr);
2593 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2594 params[param_count++] = i1false; /* r128 */
2595 params[param_count++] = da ? i1true : i1false; /* da */
2596 params[param_count++] = i1false; /* slc */
2597 }
2598
2599 switch (instr->intrinsic) {
2600 case nir_intrinsic_image_atomic_add:
2601 atomic_name = "add";
2602 break;
2603 case nir_intrinsic_image_atomic_min:
2604 atomic_name = "smin";
2605 break;
2606 case nir_intrinsic_image_atomic_max:
2607 atomic_name = "smax";
2608 break;
2609 case nir_intrinsic_image_atomic_and:
2610 atomic_name = "and";
2611 break;
2612 case nir_intrinsic_image_atomic_or:
2613 atomic_name = "or";
2614 break;
2615 case nir_intrinsic_image_atomic_xor:
2616 atomic_name = "xor";
2617 break;
2618 case nir_intrinsic_image_atomic_exchange:
2619 atomic_name = "swap";
2620 break;
2621 case nir_intrinsic_image_atomic_comp_swap:
2622 atomic_name = "cmpswap";
2623 break;
2624 default:
2625 abort();
2626 }
2627 build_int_type_name(LLVMTypeOf(coords),
2628 coords_type, sizeof(coords_type));
2629
2630 snprintf(intrinsic_name, sizeof(intrinsic_name),
2631 "%s.%s.%s", base_name, atomic_name, coords_type);
2632 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2633 }
2634
2635 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2636 nir_intrinsic_instr *instr)
2637 {
2638 LLVMValueRef res;
2639 LLVMValueRef params[10];
2640 const nir_variable *var = instr->variables[0]->var;
2641 const struct glsl_type *type = instr->variables[0]->var->type;
2642 bool da = glsl_sampler_type_is_array(var->type) ||
2643 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2644 if(instr->variables[0]->deref.child)
2645 type = instr->variables[0]->deref.child->type;
2646
2647 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2648 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2649 params[0] = ctx->i32zero;
2650 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2651 params[2] = LLVMConstInt(ctx->i32, 15, false);
2652 params[3] = ctx->i32zero;
2653 params[4] = ctx->i32zero;
2654 params[5] = da ? ctx->i32one : ctx->i32zero;
2655 params[6] = ctx->i32zero;
2656 params[7] = ctx->i32zero;
2657 params[8] = ctx->i32zero;
2658 params[9] = ctx->i32zero;
2659
2660 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2661 params, 10, AC_FUNC_ATTR_READNONE);
2662
2663 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2664 glsl_sampler_type_is_array(type)) {
2665 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2666 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2667 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2668 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2669 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2670 }
2671 return res;
2672 }
2673
2674 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2675 {
2676 LLVMValueRef args[1] = {
2677 LLVMConstInt(ctx->i32, 0xf70, false),
2678 };
2679 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2680 ctx->voidt, args, 1, 0);
2681 }
2682
2683 static void emit_barrier(struct nir_to_llvm_context *ctx)
2684 {
2685 // TODO tess
2686 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2687 ctx->voidt, NULL, 0, 0);
2688 }
2689
2690 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2691 nir_intrinsic_instr *instr)
2692 {
2693 LLVMValueRef cond;
2694 ctx->shader_info->fs.can_discard = true;
2695
2696 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2697 get_src(ctx, instr->src[0]),
2698 ctx->i32zero, "");
2699
2700 cond = LLVMBuildSelect(ctx->builder, cond,
2701 LLVMConstReal(ctx->f32, -1.0f),
2702 ctx->f32zero, "");
2703 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2704 ctx->voidt,
2705 &cond, 1, 0);
2706 }
2707
2708 static LLVMValueRef
2709 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2710 {
2711 LLVMValueRef result;
2712 LLVMValueRef thread_id = get_thread_id(ctx);
2713 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2714 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2715
2716 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2717 }
2718
2719 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2720 nir_intrinsic_instr *instr)
2721 {
2722 LLVMValueRef ptr, result;
2723 int idx = instr->variables[0]->var->data.driver_location;
2724 LLVMValueRef src = get_src(ctx, instr->src[0]);
2725 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2726
2727 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2728 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2729 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2730 ptr, src, src1,
2731 LLVMAtomicOrderingSequentiallyConsistent,
2732 LLVMAtomicOrderingSequentiallyConsistent,
2733 false);
2734 } else {
2735 LLVMAtomicRMWBinOp op;
2736 switch (instr->intrinsic) {
2737 case nir_intrinsic_var_atomic_add:
2738 op = LLVMAtomicRMWBinOpAdd;
2739 break;
2740 case nir_intrinsic_var_atomic_umin:
2741 op = LLVMAtomicRMWBinOpUMin;
2742 break;
2743 case nir_intrinsic_var_atomic_umax:
2744 op = LLVMAtomicRMWBinOpUMax;
2745 break;
2746 case nir_intrinsic_var_atomic_imin:
2747 op = LLVMAtomicRMWBinOpMin;
2748 break;
2749 case nir_intrinsic_var_atomic_imax:
2750 op = LLVMAtomicRMWBinOpMax;
2751 break;
2752 case nir_intrinsic_var_atomic_and:
2753 op = LLVMAtomicRMWBinOpAnd;
2754 break;
2755 case nir_intrinsic_var_atomic_or:
2756 op = LLVMAtomicRMWBinOpOr;
2757 break;
2758 case nir_intrinsic_var_atomic_xor:
2759 op = LLVMAtomicRMWBinOpXor;
2760 break;
2761 case nir_intrinsic_var_atomic_exchange:
2762 op = LLVMAtomicRMWBinOpXchg;
2763 break;
2764 default:
2765 return NULL;
2766 }
2767
2768 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2769 LLVMAtomicOrderingSequentiallyConsistent,
2770 false);
2771 }
2772 return result;
2773 }
2774
2775 #define INTERP_CENTER 0
2776 #define INTERP_CENTROID 1
2777 #define INTERP_SAMPLE 2
2778
2779 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2780 enum glsl_interp_mode interp, unsigned location)
2781 {
2782 switch (interp) {
2783 case INTERP_MODE_FLAT:
2784 default:
2785 return NULL;
2786 case INTERP_MODE_SMOOTH:
2787 case INTERP_MODE_NONE:
2788 if (location == INTERP_CENTER)
2789 return ctx->persp_center;
2790 else if (location == INTERP_CENTROID)
2791 return ctx->persp_centroid;
2792 else if (location == INTERP_SAMPLE)
2793 return ctx->persp_sample;
2794 break;
2795 case INTERP_MODE_NOPERSPECTIVE:
2796 if (location == INTERP_CENTER)
2797 return ctx->linear_center;
2798 else if (location == INTERP_CENTROID)
2799 return ctx->linear_centroid;
2800 else if (location == INTERP_SAMPLE)
2801 return ctx->linear_sample;
2802 break;
2803 }
2804 return NULL;
2805 }
2806
2807 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2808 LLVMValueRef sample_id)
2809 {
2810 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2811 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2812 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2813 LLVMValueRef result[2];
2814
2815 result[0] = build_indexed_load_const(ctx, ctx->sample_positions, offset0);
2816 result[1] = build_indexed_load_const(ctx, ctx->sample_positions, offset1);
2817
2818 return ac_build_gather_values(&ctx->ac, result, 2);
2819 }
2820
2821 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2822 {
2823 LLVMValueRef values[2];
2824
2825 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2826 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2827 return ac_build_gather_values(&ctx->ac, values, 2);
2828 }
2829
2830 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2831 nir_intrinsic_instr *instr)
2832 {
2833 LLVMValueRef result[2];
2834 LLVMValueRef interp_param, attr_number;
2835 unsigned location;
2836 unsigned chan;
2837 LLVMValueRef src_c0, src_c1;
2838 const char *intr_name;
2839 LLVMValueRef src0;
2840 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2841 switch (instr->intrinsic) {
2842 case nir_intrinsic_interp_var_at_centroid:
2843 location = INTERP_CENTROID;
2844 break;
2845 case nir_intrinsic_interp_var_at_sample:
2846 case nir_intrinsic_interp_var_at_offset:
2847 location = INTERP_SAMPLE;
2848 src0 = get_src(ctx, instr->src[0]);
2849 break;
2850 default:
2851 break;
2852 }
2853
2854 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2855 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2856 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2857 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2858 LLVMValueRef sample_position;
2859 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2860
2861 /* fetch sample ID */
2862 sample_position = load_sample_position(ctx, src0);
2863
2864 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2865 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2866 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2867 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2868 }
2869 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2870 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2871
2872 if (location == INTERP_SAMPLE) {
2873 LLVMValueRef ij_out[2];
2874 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2875
2876 /*
2877 * take the I then J parameters, and the DDX/Y for it, and
2878 * calculate the IJ inputs for the interpolator.
2879 * temp1 = ddx * offset/sample.x + I;
2880 * interp_param.I = ddy * offset/sample.y + temp1;
2881 * temp1 = ddx * offset/sample.x + J;
2882 * interp_param.J = ddy * offset/sample.y + temp1;
2883 */
2884 for (unsigned i = 0; i < 2; i++) {
2885 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2886 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2887 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2888 ddxy_out, ix_ll, "");
2889 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2890 ddxy_out, iy_ll, "");
2891 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2892 interp_param, ix_ll, "");
2893 LLVMValueRef temp1, temp2;
2894
2895 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2896 ctx->f32, "");
2897
2898 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2899 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2900
2901 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2902 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2903
2904 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2905 temp2, ctx->i32, "");
2906 }
2907 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2908
2909 }
2910 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
2911 for (chan = 0; chan < 2; chan++) {
2912 LLVMValueRef args[4];
2913 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2914
2915 args[0] = llvm_chan;
2916 args[1] = attr_number;
2917 args[2] = ctx->prim_mask;
2918 args[3] = interp_param;
2919 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
2920 ctx->f32, args, args[3] ? 4 : 3,
2921 AC_FUNC_ATTR_READNONE);
2922 }
2923 return ac_build_gather_values(&ctx->ac, result, 2);
2924 }
2925
2926 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
2927 nir_intrinsic_instr *instr)
2928 {
2929 LLVMValueRef result = NULL;
2930
2931 switch (instr->intrinsic) {
2932 case nir_intrinsic_load_work_group_id: {
2933 result = ctx->workgroup_ids;
2934 break;
2935 }
2936 case nir_intrinsic_load_base_vertex: {
2937 result = ctx->base_vertex;
2938 break;
2939 }
2940 case nir_intrinsic_load_vertex_id_zero_base: {
2941 result = ctx->vertex_id;
2942 break;
2943 }
2944 case nir_intrinsic_load_local_invocation_id: {
2945 result = ctx->local_invocation_ids;
2946 break;
2947 }
2948 case nir_intrinsic_load_base_instance:
2949 result = ctx->start_instance;
2950 break;
2951 case nir_intrinsic_load_sample_id:
2952 ctx->shader_info->fs.force_persample = true;
2953 result = unpack_param(ctx, ctx->ancillary, 8, 4);
2954 break;
2955 case nir_intrinsic_load_sample_pos:
2956 ctx->shader_info->fs.force_persample = true;
2957 result = load_sample_pos(ctx);
2958 break;
2959 case nir_intrinsic_load_front_face:
2960 result = ctx->front_face;
2961 break;
2962 case nir_intrinsic_load_instance_id:
2963 result = ctx->instance_id;
2964 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
2965 ctx->shader_info->vs.vgpr_comp_cnt);
2966 break;
2967 case nir_intrinsic_load_num_work_groups:
2968 result = ctx->num_work_groups;
2969 break;
2970 case nir_intrinsic_load_local_invocation_index:
2971 result = visit_load_local_invocation_index(ctx);
2972 break;
2973 case nir_intrinsic_load_push_constant:
2974 result = visit_load_push_constant(ctx, instr);
2975 break;
2976 case nir_intrinsic_vulkan_resource_index:
2977 result = visit_vulkan_resource_index(ctx, instr);
2978 break;
2979 case nir_intrinsic_store_ssbo:
2980 visit_store_ssbo(ctx, instr);
2981 break;
2982 case nir_intrinsic_load_ssbo:
2983 result = visit_load_buffer(ctx, instr);
2984 break;
2985 case nir_intrinsic_ssbo_atomic_add:
2986 case nir_intrinsic_ssbo_atomic_imin:
2987 case nir_intrinsic_ssbo_atomic_umin:
2988 case nir_intrinsic_ssbo_atomic_imax:
2989 case nir_intrinsic_ssbo_atomic_umax:
2990 case nir_intrinsic_ssbo_atomic_and:
2991 case nir_intrinsic_ssbo_atomic_or:
2992 case nir_intrinsic_ssbo_atomic_xor:
2993 case nir_intrinsic_ssbo_atomic_exchange:
2994 case nir_intrinsic_ssbo_atomic_comp_swap:
2995 result = visit_atomic_ssbo(ctx, instr);
2996 break;
2997 case nir_intrinsic_load_ubo:
2998 result = visit_load_ubo_buffer(ctx, instr);
2999 break;
3000 case nir_intrinsic_get_buffer_size:
3001 result = visit_get_buffer_size(ctx, instr);
3002 break;
3003 case nir_intrinsic_load_var:
3004 result = visit_load_var(ctx, instr);
3005 break;
3006 case nir_intrinsic_store_var:
3007 visit_store_var(ctx, instr);
3008 break;
3009 case nir_intrinsic_image_load:
3010 result = visit_image_load(ctx, instr);
3011 break;
3012 case nir_intrinsic_image_store:
3013 visit_image_store(ctx, instr);
3014 break;
3015 case nir_intrinsic_image_atomic_add:
3016 case nir_intrinsic_image_atomic_min:
3017 case nir_intrinsic_image_atomic_max:
3018 case nir_intrinsic_image_atomic_and:
3019 case nir_intrinsic_image_atomic_or:
3020 case nir_intrinsic_image_atomic_xor:
3021 case nir_intrinsic_image_atomic_exchange:
3022 case nir_intrinsic_image_atomic_comp_swap:
3023 result = visit_image_atomic(ctx, instr);
3024 break;
3025 case nir_intrinsic_image_size:
3026 result = visit_image_size(ctx, instr);
3027 break;
3028 case nir_intrinsic_discard:
3029 ctx->shader_info->fs.can_discard = true;
3030 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3031 ctx->voidt,
3032 NULL, 0, 0);
3033 break;
3034 case nir_intrinsic_discard_if:
3035 emit_discard_if(ctx, instr);
3036 break;
3037 case nir_intrinsic_memory_barrier:
3038 emit_waitcnt(ctx);
3039 break;
3040 case nir_intrinsic_barrier:
3041 emit_barrier(ctx);
3042 break;
3043 case nir_intrinsic_var_atomic_add:
3044 case nir_intrinsic_var_atomic_imin:
3045 case nir_intrinsic_var_atomic_umin:
3046 case nir_intrinsic_var_atomic_imax:
3047 case nir_intrinsic_var_atomic_umax:
3048 case nir_intrinsic_var_atomic_and:
3049 case nir_intrinsic_var_atomic_or:
3050 case nir_intrinsic_var_atomic_xor:
3051 case nir_intrinsic_var_atomic_exchange:
3052 case nir_intrinsic_var_atomic_comp_swap:
3053 result = visit_var_atomic(ctx, instr);
3054 break;
3055 case nir_intrinsic_interp_var_at_centroid:
3056 case nir_intrinsic_interp_var_at_sample:
3057 case nir_intrinsic_interp_var_at_offset:
3058 result = visit_interp(ctx, instr);
3059 break;
3060 default:
3061 fprintf(stderr, "Unknown intrinsic: ");
3062 nir_print_instr(&instr->instr, stderr);
3063 fprintf(stderr, "\n");
3064 break;
3065 }
3066 if (result) {
3067 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3068 }
3069 }
3070
3071 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3072 nir_deref_var *deref,
3073 enum desc_type desc_type)
3074 {
3075 unsigned desc_set = deref->var->data.descriptor_set;
3076 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3077 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3078 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3079 unsigned offset = binding->offset;
3080 unsigned stride = binding->size;
3081 unsigned type_size;
3082 LLVMBuilderRef builder = ctx->builder;
3083 LLVMTypeRef type;
3084 LLVMValueRef index = NULL;
3085
3086 assert(deref->var->data.binding < layout->binding_count);
3087
3088 switch (desc_type) {
3089 case DESC_IMAGE:
3090 type = ctx->v8i32;
3091 type_size = 32;
3092 break;
3093 case DESC_FMASK:
3094 type = ctx->v8i32;
3095 offset += 32;
3096 type_size = 32;
3097 break;
3098 case DESC_SAMPLER:
3099 type = ctx->v4i32;
3100 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3101 offset += 64;
3102
3103 type_size = 16;
3104 break;
3105 case DESC_BUFFER:
3106 type = ctx->v4i32;
3107 type_size = 16;
3108 break;
3109 default:
3110 unreachable("invalid desc_type\n");
3111 }
3112
3113 if (deref->deref.child) {
3114 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3115
3116 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3117 offset += child->base_offset * stride;
3118 if (child->deref_array_type == nir_deref_array_type_indirect) {
3119 index = get_src(ctx, child->indirect);
3120 }
3121 }
3122
3123 assert(stride % type_size == 0);
3124
3125 if (!index)
3126 index = ctx->i32zero;
3127
3128 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3129
3130 list = build_gep0(ctx, list, LLVMConstInt(ctx->i32, offset, 0));
3131 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3132
3133 return build_indexed_load_const(ctx, list, index);
3134 }
3135
3136 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3137 struct ac_tex_info *tinfo,
3138 nir_tex_instr *instr,
3139 nir_texop op,
3140 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3141 LLVMValueRef *param, unsigned count,
3142 unsigned dmask)
3143 {
3144 int num_args;
3145 unsigned is_rect = 0;
3146 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3147
3148 if (op == nir_texop_lod)
3149 da = false;
3150 /* Pad to power of two vector */
3151 while (count < util_next_power_of_two(count))
3152 param[count++] = LLVMGetUndef(ctx->i32);
3153
3154 if (count > 1)
3155 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3156 else
3157 tinfo->args[0] = param[0];
3158
3159 tinfo->args[1] = res_ptr;
3160 num_args = 2;
3161
3162 if (op == nir_texop_txf ||
3163 op == nir_texop_txf_ms ||
3164 op == nir_texop_query_levels ||
3165 op == nir_texop_texture_samples ||
3166 op == nir_texop_txs)
3167 tinfo->dst_type = ctx->v4i32;
3168 else {
3169 tinfo->dst_type = ctx->v4f32;
3170 tinfo->args[num_args++] = samp_ptr;
3171 }
3172
3173 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3174 tinfo->args[0] = res_ptr;
3175 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3176 tinfo->args[2] = param[0];
3177 tinfo->arg_count = 3;
3178 return;
3179 }
3180
3181 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3182 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3183 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3184 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3185 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3186 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3187 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3188 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3189
3190 tinfo->arg_count = num_args;
3191 }
3192
3193 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3194 *
3195 * SI-CI:
3196 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3197 * filtering manually. The driver sets img7 to a mask clearing
3198 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3199 * s_and_b32 samp0, samp0, img7
3200 *
3201 * VI:
3202 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3203 */
3204 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3205 LLVMValueRef res, LLVMValueRef samp)
3206 {
3207 LLVMBuilderRef builder = ctx->builder;
3208 LLVMValueRef img7, samp0;
3209
3210 if (ctx->options->chip_class >= VI)
3211 return samp;
3212
3213 img7 = LLVMBuildExtractElement(builder, res,
3214 LLVMConstInt(ctx->i32, 7, 0), "");
3215 samp0 = LLVMBuildExtractElement(builder, samp,
3216 LLVMConstInt(ctx->i32, 0, 0), "");
3217 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3218 return LLVMBuildInsertElement(builder, samp, samp0,
3219 LLVMConstInt(ctx->i32, 0, 0), "");
3220 }
3221
3222 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3223 nir_tex_instr *instr,
3224 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3225 LLVMValueRef *fmask_ptr)
3226 {
3227 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3228 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3229 else
3230 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3231 if (samp_ptr) {
3232 if (instr->sampler)
3233 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3234 else
3235 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3236 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3237 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3238 }
3239 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3240 instr->op == nir_texop_samples_identical))
3241 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3242 }
3243
3244 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3245 {
3246 LLVMValueRef result = NULL;
3247 struct ac_tex_info tinfo = { 0 };
3248 unsigned dmask = 0xf;
3249 LLVMValueRef address[16];
3250 LLVMValueRef coords[5];
3251 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3252 LLVMValueRef bias = NULL, offsets = NULL;
3253 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3254 LLVMValueRef ddx = NULL, ddy = NULL;
3255 LLVMValueRef derivs[6];
3256 unsigned chan, count = 0;
3257 unsigned const_src = 0, num_deriv_comp = 0;
3258
3259 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3260
3261 for (unsigned i = 0; i < instr->num_srcs; i++) {
3262 switch (instr->src[i].src_type) {
3263 case nir_tex_src_coord:
3264 coord = get_src(ctx, instr->src[i].src);
3265 break;
3266 case nir_tex_src_projector:
3267 break;
3268 case nir_tex_src_comparator:
3269 comparator = get_src(ctx, instr->src[i].src);
3270 break;
3271 case nir_tex_src_offset:
3272 offsets = get_src(ctx, instr->src[i].src);
3273 const_src = i;
3274 break;
3275 case nir_tex_src_bias:
3276 bias = get_src(ctx, instr->src[i].src);
3277 break;
3278 case nir_tex_src_lod:
3279 lod = get_src(ctx, instr->src[i].src);
3280 break;
3281 case nir_tex_src_ms_index:
3282 sample_index = get_src(ctx, instr->src[i].src);
3283 break;
3284 case nir_tex_src_ms_mcs:
3285 break;
3286 case nir_tex_src_ddx:
3287 ddx = get_src(ctx, instr->src[i].src);
3288 num_deriv_comp = instr->src[i].src.ssa->num_components;
3289 break;
3290 case nir_tex_src_ddy:
3291 ddy = get_src(ctx, instr->src[i].src);
3292 break;
3293 case nir_tex_src_texture_offset:
3294 case nir_tex_src_sampler_offset:
3295 case nir_tex_src_plane:
3296 default:
3297 break;
3298 }
3299 }
3300
3301 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3302 result = get_buffer_size(ctx, res_ptr, false);
3303 goto write_result;
3304 }
3305
3306 if (instr->op == nir_texop_texture_samples) {
3307 LLVMValueRef res, samples, is_msaa;
3308 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3309 samples = LLVMBuildExtractElement(ctx->builder, res,
3310 LLVMConstInt(ctx->i32, 3, false), "");
3311 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3312 LLVMConstInt(ctx->i32, 28, false), "");
3313 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3314 LLVMConstInt(ctx->i32, 0xe, false), "");
3315 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3316 LLVMConstInt(ctx->i32, 0xe, false), "");
3317
3318 samples = LLVMBuildLShr(ctx->builder, samples,
3319 LLVMConstInt(ctx->i32, 16, false), "");
3320 samples = LLVMBuildAnd(ctx->builder, samples,
3321 LLVMConstInt(ctx->i32, 0xf, false), "");
3322 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3323 samples, "");
3324 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3325 ctx->i32one, "");
3326 result = samples;
3327 goto write_result;
3328 }
3329
3330 if (coord)
3331 for (chan = 0; chan < instr->coord_components; chan++)
3332 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3333
3334 if (offsets && instr->op != nir_texop_txf) {
3335 LLVMValueRef offset[3], pack;
3336 for (chan = 0; chan < 3; ++chan)
3337 offset[chan] = ctx->i32zero;
3338
3339 tinfo.has_offset = true;
3340 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3341 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3342 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3343 LLVMConstInt(ctx->i32, 0x3f, false), "");
3344 if (chan)
3345 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3346 LLVMConstInt(ctx->i32, chan * 8, false), "");
3347 }
3348 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3349 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3350 address[count++] = pack;
3351
3352 }
3353 /* pack LOD bias value */
3354 if (instr->op == nir_texop_txb && bias) {
3355 address[count++] = bias;
3356 }
3357
3358 /* Pack depth comparison value */
3359 if (instr->is_shadow && comparator) {
3360 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3361 }
3362
3363 /* pack derivatives */
3364 if (ddx || ddy) {
3365 switch (instr->sampler_dim) {
3366 case GLSL_SAMPLER_DIM_3D:
3367 case GLSL_SAMPLER_DIM_CUBE:
3368 num_deriv_comp = 3;
3369 break;
3370 case GLSL_SAMPLER_DIM_2D:
3371 default:
3372 num_deriv_comp = 2;
3373 break;
3374 case GLSL_SAMPLER_DIM_1D:
3375 num_deriv_comp = 1;
3376 break;
3377 }
3378
3379 for (unsigned i = 0; i < num_deriv_comp; i++) {
3380 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3381 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3382 }
3383 }
3384
3385 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3386 for (chan = 0; chan < instr->coord_components; chan++)
3387 coords[chan] = to_float(ctx, coords[chan]);
3388 if (instr->coord_components == 3)
3389 coords[3] = LLVMGetUndef(ctx->f32);
3390 ac_prepare_cube_coords(&ctx->ac,
3391 instr->op == nir_texop_txd, instr->is_array,
3392 coords, derivs);
3393 if (num_deriv_comp)
3394 num_deriv_comp--;
3395 }
3396
3397 if (ddx || ddy) {
3398 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3399 address[count++] = derivs[i];
3400 }
3401
3402 /* Pack texture coordinates */
3403 if (coord) {
3404 address[count++] = coords[0];
3405 if (instr->coord_components > 1)
3406 address[count++] = coords[1];
3407 if (instr->coord_components > 2) {
3408 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3409 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3410 coords[2] = to_float(ctx, coords[2]);
3411 coords[2] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coords[2],
3412 1, 0);
3413 coords[2] = to_integer(ctx, coords[2]);
3414 }
3415 address[count++] = coords[2];
3416 }
3417 }
3418
3419 /* Pack LOD */
3420 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3421 address[count++] = lod;
3422 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3423 address[count++] = sample_index;
3424 } else if(instr->op == nir_texop_txs) {
3425 count = 0;
3426 if (lod)
3427 address[count++] = lod;
3428 else
3429 address[count++] = ctx->i32zero;
3430 }
3431
3432 for (chan = 0; chan < count; chan++) {
3433 address[chan] = LLVMBuildBitCast(ctx->builder,
3434 address[chan], ctx->i32, "");
3435 }
3436
3437 if (instr->op == nir_texop_samples_identical) {
3438 LLVMValueRef txf_address[4];
3439 struct ac_tex_info txf_info = { 0 };
3440 unsigned txf_count = count;
3441 memcpy(txf_address, address, sizeof(txf_address));
3442
3443 if (!instr->is_array)
3444 txf_address[2] = ctx->i32zero;
3445 txf_address[3] = ctx->i32zero;
3446
3447 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3448 fmask_ptr, NULL,
3449 txf_address, txf_count, 0xf);
3450
3451 result = build_tex_intrinsic(ctx, instr, &txf_info);
3452
3453 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3454 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3455 goto write_result;
3456 }
3457
3458 /* Adjust the sample index according to FMASK.
3459 *
3460 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3461 * which is the identity mapping. Each nibble says which physical sample
3462 * should be fetched to get that sample.
3463 *
3464 * For example, 0x11111100 means there are only 2 samples stored and
3465 * the second sample covers 3/4 of the pixel. When reading samples 0
3466 * and 1, return physical sample 0 (determined by the first two 0s
3467 * in FMASK), otherwise return physical sample 1.
3468 *
3469 * The sample index should be adjusted as follows:
3470 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3471 */
3472 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS) {
3473 LLVMValueRef txf_address[4];
3474 struct ac_tex_info txf_info = { 0 };
3475 unsigned txf_count = count;
3476 memcpy(txf_address, address, sizeof(txf_address));
3477
3478 if (!instr->is_array)
3479 txf_address[2] = ctx->i32zero;
3480 txf_address[3] = ctx->i32zero;
3481
3482 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3483 fmask_ptr, NULL,
3484 txf_address, txf_count, 0xf);
3485
3486 result = build_tex_intrinsic(ctx, instr, &txf_info);
3487 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3488 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3489
3490 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3491 result,
3492 ctx->i32zero, "");
3493
3494 unsigned sample_chan = instr->is_array ? 3 : 2;
3495
3496 LLVMValueRef sample_index4 =
3497 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3498 LLVMValueRef shifted_fmask =
3499 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3500 LLVMValueRef final_sample =
3501 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3502
3503 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3504 * resource descriptor is 0 (invalid),
3505 */
3506 LLVMValueRef fmask_desc =
3507 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3508 ctx->v8i32, "");
3509
3510 LLVMValueRef fmask_word1 =
3511 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3512 ctx->i32one, "");
3513
3514 LLVMValueRef word1_is_nonzero =
3515 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3516 fmask_word1, ctx->i32zero, "");
3517
3518 /* Replace the MSAA sample index. */
3519 address[sample_chan] =
3520 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3521 final_sample, address[sample_chan], "");
3522 }
3523
3524 if (offsets && instr->op == nir_texop_txf) {
3525 nir_const_value *const_offset =
3526 nir_src_as_const_value(instr->src[const_src].src);
3527 int num_offsets = instr->src[const_src].src.ssa->num_components;
3528 assert(const_offset);
3529 num_offsets = MIN2(num_offsets, instr->coord_components);
3530 if (num_offsets > 2)
3531 address[2] = LLVMBuildAdd(ctx->builder,
3532 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3533 if (num_offsets > 1)
3534 address[1] = LLVMBuildAdd(ctx->builder,
3535 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3536 address[0] = LLVMBuildAdd(ctx->builder,
3537 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3538
3539 }
3540
3541 /* TODO TG4 support */
3542 if (instr->op == nir_texop_tg4) {
3543 if (instr->is_shadow)
3544 dmask = 1;
3545 else
3546 dmask = 1 << instr->component;
3547 }
3548 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3549 res_ptr, samp_ptr, address, count, dmask);
3550
3551 result = build_tex_intrinsic(ctx, instr, &tinfo);
3552
3553 if (instr->op == nir_texop_query_levels)
3554 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3555 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3556 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3557 else if (instr->op == nir_texop_txs &&
3558 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3559 instr->is_array) {
3560 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3561 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3562 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3563 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3564 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3565 } else if (instr->dest.ssa.num_components != 4)
3566 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3567
3568 write_result:
3569 if (result) {
3570 assert(instr->dest.is_ssa);
3571 result = to_integer(ctx, result);
3572 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3573 }
3574 }
3575
3576
3577 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3578 {
3579 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3580 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3581
3582 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3583 _mesa_hash_table_insert(ctx->phis, instr, result);
3584 }
3585
3586 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3587 nir_phi_instr *instr,
3588 LLVMValueRef llvm_phi)
3589 {
3590 nir_foreach_phi_src(src, instr) {
3591 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3592 LLVMValueRef llvm_src = get_src(ctx, src->src);
3593
3594 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3595 }
3596 }
3597
3598 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3599 {
3600 struct hash_entry *entry;
3601 hash_table_foreach(ctx->phis, entry) {
3602 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3603 (LLVMValueRef)entry->data);
3604 }
3605 }
3606
3607
3608 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3609 nir_ssa_undef_instr *instr)
3610 {
3611 unsigned num_components = instr->def.num_components;
3612 LLVMValueRef undef;
3613
3614 if (num_components == 1)
3615 undef = LLVMGetUndef(ctx->i32);
3616 else {
3617 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3618 }
3619 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3620 }
3621
3622 static void visit_jump(struct nir_to_llvm_context *ctx,
3623 nir_jump_instr *instr)
3624 {
3625 switch (instr->type) {
3626 case nir_jump_break:
3627 LLVMBuildBr(ctx->builder, ctx->break_block);
3628 LLVMClearInsertionPosition(ctx->builder);
3629 break;
3630 case nir_jump_continue:
3631 LLVMBuildBr(ctx->builder, ctx->continue_block);
3632 LLVMClearInsertionPosition(ctx->builder);
3633 break;
3634 default:
3635 fprintf(stderr, "Unknown NIR jump instr: ");
3636 nir_print_instr(&instr->instr, stderr);
3637 fprintf(stderr, "\n");
3638 abort();
3639 }
3640 }
3641
3642 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3643 struct exec_list *list);
3644
3645 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3646 {
3647 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3648 nir_foreach_instr(instr, block)
3649 {
3650 switch (instr->type) {
3651 case nir_instr_type_alu:
3652 visit_alu(ctx, nir_instr_as_alu(instr));
3653 break;
3654 case nir_instr_type_load_const:
3655 visit_load_const(ctx, nir_instr_as_load_const(instr));
3656 break;
3657 case nir_instr_type_intrinsic:
3658 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3659 break;
3660 case nir_instr_type_tex:
3661 visit_tex(ctx, nir_instr_as_tex(instr));
3662 break;
3663 case nir_instr_type_phi:
3664 visit_phi(ctx, nir_instr_as_phi(instr));
3665 break;
3666 case nir_instr_type_ssa_undef:
3667 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3668 break;
3669 case nir_instr_type_jump:
3670 visit_jump(ctx, nir_instr_as_jump(instr));
3671 break;
3672 default:
3673 fprintf(stderr, "Unknown NIR instr type: ");
3674 nir_print_instr(instr, stderr);
3675 fprintf(stderr, "\n");
3676 abort();
3677 }
3678 }
3679
3680 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3681 }
3682
3683 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3684 {
3685 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3686
3687 LLVMBasicBlockRef merge_block =
3688 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3689 LLVMBasicBlockRef if_block =
3690 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3691 LLVMBasicBlockRef else_block = merge_block;
3692 if (!exec_list_is_empty(&if_stmt->else_list))
3693 else_block = LLVMAppendBasicBlockInContext(
3694 ctx->context, ctx->main_function, "");
3695
3696 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3697 LLVMConstInt(ctx->i32, 0, false), "");
3698 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3699
3700 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3701 visit_cf_list(ctx, &if_stmt->then_list);
3702 if (LLVMGetInsertBlock(ctx->builder))
3703 LLVMBuildBr(ctx->builder, merge_block);
3704
3705 if (!exec_list_is_empty(&if_stmt->else_list)) {
3706 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3707 visit_cf_list(ctx, &if_stmt->else_list);
3708 if (LLVMGetInsertBlock(ctx->builder))
3709 LLVMBuildBr(ctx->builder, merge_block);
3710 }
3711
3712 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3713 }
3714
3715 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3716 {
3717 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3718 LLVMBasicBlockRef break_parent = ctx->break_block;
3719
3720 ctx->continue_block =
3721 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3722 ctx->break_block =
3723 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3724
3725 LLVMBuildBr(ctx->builder, ctx->continue_block);
3726 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3727 visit_cf_list(ctx, &loop->body);
3728
3729 if (LLVMGetInsertBlock(ctx->builder))
3730 LLVMBuildBr(ctx->builder, ctx->continue_block);
3731 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3732
3733 ctx->continue_block = continue_parent;
3734 ctx->break_block = break_parent;
3735 }
3736
3737 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3738 struct exec_list *list)
3739 {
3740 foreach_list_typed(nir_cf_node, node, node, list)
3741 {
3742 switch (node->type) {
3743 case nir_cf_node_block:
3744 visit_block(ctx, nir_cf_node_as_block(node));
3745 break;
3746
3747 case nir_cf_node_if:
3748 visit_if(ctx, nir_cf_node_as_if(node));
3749 break;
3750
3751 case nir_cf_node_loop:
3752 visit_loop(ctx, nir_cf_node_as_loop(node));
3753 break;
3754
3755 default:
3756 assert(0);
3757 }
3758 }
3759 }
3760
3761 static void
3762 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3763 struct nir_variable *variable)
3764 {
3765 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3766 LLVMValueRef t_offset;
3767 LLVMValueRef t_list;
3768 LLVMValueRef args[3];
3769 LLVMValueRef input;
3770 LLVMValueRef buffer_index;
3771 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3772 int idx = variable->data.location;
3773 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3774
3775 variable->data.driver_location = idx * 4;
3776
3777 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3778 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3779 ctx->start_instance, "");
3780 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3781 ctx->shader_info->vs.vgpr_comp_cnt);
3782 } else
3783 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3784 ctx->base_vertex, "");
3785
3786 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3787 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3788
3789 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
3790 args[0] = t_list;
3791 args[1] = LLVMConstInt(ctx->i32, 0, false);
3792 args[2] = buffer_index;
3793 input = ac_emit_llvm_intrinsic(&ctx->ac,
3794 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3795 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3796
3797 for (unsigned chan = 0; chan < 4; chan++) {
3798 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3799 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3800 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3801 input, llvm_chan, ""));
3802 }
3803 }
3804 }
3805
3806
3807 static void interp_fs_input(struct nir_to_llvm_context *ctx,
3808 unsigned attr,
3809 LLVMValueRef interp_param,
3810 LLVMValueRef prim_mask,
3811 LLVMValueRef result[4])
3812 {
3813 const char *intr_name;
3814 LLVMValueRef attr_number;
3815 unsigned chan;
3816
3817 attr_number = LLVMConstInt(ctx->i32, attr, false);
3818
3819 /* fs.constant returns the param from the middle vertex, so it's not
3820 * really useful for flat shading. It's meant to be used for custom
3821 * interpolation (but the intrinsic can't fetch from the other two
3822 * vertices).
3823 *
3824 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
3825 * to do the right thing. The only reason we use fs.constant is that
3826 * fs.interp cannot be used on integers, because they can be equal
3827 * to NaN.
3828 */
3829 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3830
3831 for (chan = 0; chan < 4; chan++) {
3832 LLVMValueRef args[4];
3833 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3834
3835 args[0] = llvm_chan;
3836 args[1] = attr_number;
3837 args[2] = prim_mask;
3838 args[3] = interp_param;
3839 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
3840 ctx->f32, args, args[3] ? 4 : 3,
3841 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3842 }
3843 }
3844
3845 static void
3846 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
3847 struct nir_variable *variable)
3848 {
3849 int idx = variable->data.location;
3850 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
3851 LLVMValueRef interp;
3852
3853 variable->data.driver_location = idx * 4;
3854 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
3855
3856 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
3857 unsigned interp_type;
3858 if (variable->data.sample) {
3859 interp_type = INTERP_SAMPLE;
3860 ctx->shader_info->fs.force_persample = true;
3861 } else if (variable->data.centroid)
3862 interp_type = INTERP_CENTROID;
3863 else
3864 interp_type = INTERP_CENTER;
3865
3866 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
3867 } else
3868 interp = NULL;
3869
3870 for (unsigned i = 0; i < attrib_count; ++i)
3871 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
3872
3873 }
3874
3875 static void
3876 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
3877 struct nir_variable *variable)
3878 {
3879 switch (ctx->stage) {
3880 case MESA_SHADER_VERTEX:
3881 handle_vs_input_decl(ctx, variable);
3882 break;
3883 case MESA_SHADER_FRAGMENT:
3884 handle_fs_input_decl(ctx, variable);
3885 break;
3886 default:
3887 break;
3888 }
3889
3890 }
3891
3892 static void
3893 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
3894 struct nir_shader *nir)
3895 {
3896 unsigned index = 0;
3897 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
3898 LLVMValueRef interp_param;
3899 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
3900
3901 if (!(ctx->input_mask & (1ull << i)))
3902 continue;
3903
3904 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC) {
3905 interp_param = *inputs;
3906 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
3907 inputs);
3908
3909 if (!interp_param)
3910 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
3911 ++index;
3912 } else if (i == VARYING_SLOT_POS) {
3913 for(int i = 0; i < 3; ++i)
3914 inputs[i] = ctx->frag_pos[i];
3915
3916 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
3917 }
3918 }
3919 ctx->shader_info->fs.num_interp = index;
3920 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
3921 ctx->shader_info->fs.has_pcoord = true;
3922 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
3923 }
3924
3925 static LLVMValueRef
3926 ac_build_alloca(struct nir_to_llvm_context *ctx,
3927 LLVMTypeRef type,
3928 const char *name)
3929 {
3930 LLVMBuilderRef builder = ctx->builder;
3931 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
3932 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
3933 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
3934 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
3935 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
3936 LLVMValueRef res;
3937
3938 if (first_instr) {
3939 LLVMPositionBuilderBefore(first_builder, first_instr);
3940 } else {
3941 LLVMPositionBuilderAtEnd(first_builder, first_block);
3942 }
3943
3944 res = LLVMBuildAlloca(first_builder, type, name);
3945 LLVMBuildStore(builder, LLVMConstNull(type), res);
3946
3947 LLVMDisposeBuilder(first_builder);
3948
3949 return res;
3950 }
3951
3952 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
3953 LLVMTypeRef type,
3954 const char *name)
3955 {
3956 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
3957 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
3958 return ptr;
3959 }
3960
3961 static void
3962 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
3963 struct nir_variable *variable)
3964 {
3965 int idx = variable->data.location + variable->data.index;
3966 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
3967
3968 variable->data.driver_location = idx * 4;
3969
3970 if (ctx->stage == MESA_SHADER_VERTEX) {
3971
3972 if (idx == VARYING_SLOT_CLIP_DIST0 ||
3973 idx == VARYING_SLOT_CULL_DIST0) {
3974 int length = glsl_get_length(variable->type);
3975 if (idx == VARYING_SLOT_CLIP_DIST0) {
3976 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
3977 ctx->num_clips = length;
3978 } else if (idx == VARYING_SLOT_CULL_DIST0) {
3979 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
3980 ctx->num_culls = length;
3981 }
3982 if (length > 4)
3983 attrib_count = 2;
3984 else
3985 attrib_count = 1;
3986 }
3987 }
3988
3989 for (unsigned i = 0; i < attrib_count; ++i) {
3990 for (unsigned chan = 0; chan < 4; chan++) {
3991 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
3992 si_build_alloca_undef(ctx, ctx->f32, "");
3993 }
3994 }
3995 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
3996 }
3997
3998 static void
3999 setup_locals(struct nir_to_llvm_context *ctx,
4000 struct nir_function *func)
4001 {
4002 int i, j;
4003 ctx->num_locals = 0;
4004 nir_foreach_variable(variable, &func->impl->locals) {
4005 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4006 variable->data.driver_location = ctx->num_locals * 4;
4007 ctx->num_locals += attrib_count;
4008 }
4009 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4010 if (!ctx->locals)
4011 return;
4012
4013 for (i = 0; i < ctx->num_locals; i++) {
4014 for (j = 0; j < 4; j++) {
4015 ctx->locals[i * 4 + j] =
4016 si_build_alloca_undef(ctx, ctx->f32, "temp");
4017 }
4018 }
4019 }
4020
4021 static LLVMValueRef
4022 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4023 {
4024 v = to_float(ctx, v);
4025 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", v, LLVMConstReal(ctx->f32, lo));
4026 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", v, LLVMConstReal(ctx->f32, hi));
4027 }
4028
4029
4030 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4031 LLVMValueRef src0, LLVMValueRef src1)
4032 {
4033 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4034 LLVMValueRef comp[2];
4035
4036 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4037 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4038 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4039 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4040 }
4041
4042 /* Initialize arguments for the shader export intrinsic */
4043 static void
4044 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4045 LLVMValueRef *values,
4046 unsigned target,
4047 LLVMValueRef *args)
4048 {
4049 /* Default is 0xf. Adjusted below depending on the format. */
4050 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4051 /* Specify whether the EXEC mask represents the valid mask */
4052 args[1] = LLVMConstInt(ctx->i32, 0, false);
4053
4054 /* Specify whether this is the last export */
4055 args[2] = LLVMConstInt(ctx->i32, 0, false);
4056 /* Specify the target we are exporting */
4057 args[3] = LLVMConstInt(ctx->i32, target, false);
4058
4059 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4060 args[5] = LLVMGetUndef(ctx->f32);
4061 args[6] = LLVMGetUndef(ctx->f32);
4062 args[7] = LLVMGetUndef(ctx->f32);
4063 args[8] = LLVMGetUndef(ctx->f32);
4064
4065 if (!values)
4066 return;
4067
4068 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4069 LLVMValueRef val[4];
4070 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4071 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4072 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4073
4074 switch(col_format) {
4075 case V_028714_SPI_SHADER_ZERO:
4076 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4077 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4078 break;
4079
4080 case V_028714_SPI_SHADER_32_R:
4081 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4082 args[5] = values[0];
4083 break;
4084
4085 case V_028714_SPI_SHADER_32_GR:
4086 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4087 args[5] = values[0];
4088 args[6] = values[1];
4089 break;
4090
4091 case V_028714_SPI_SHADER_32_AR:
4092 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4093 args[5] = values[0];
4094 args[8] = values[3];
4095 break;
4096
4097 case V_028714_SPI_SHADER_FP16_ABGR:
4098 args[4] = ctx->i32one;
4099
4100 for (unsigned chan = 0; chan < 2; chan++) {
4101 LLVMValueRef pack_args[2] = {
4102 values[2 * chan],
4103 values[2 * chan + 1]
4104 };
4105 LLVMValueRef packed;
4106
4107 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4108 ctx->i32, pack_args, 2,
4109 AC_FUNC_ATTR_READNONE);
4110 args[chan + 5] = packed;
4111 }
4112 break;
4113
4114 case V_028714_SPI_SHADER_UNORM16_ABGR:
4115 for (unsigned chan = 0; chan < 4; chan++) {
4116 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4117 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4118 LLVMConstReal(ctx->f32, 65535), "");
4119 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4120 LLVMConstReal(ctx->f32, 0.5), "");
4121 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4122 ctx->i32, "");
4123 }
4124
4125 args[4] = ctx->i32one;
4126 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4127 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4128 break;
4129
4130 case V_028714_SPI_SHADER_SNORM16_ABGR:
4131 for (unsigned chan = 0; chan < 4; chan++) {
4132 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4133 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4134 LLVMConstReal(ctx->f32, 32767), "");
4135
4136 /* If positive, add 0.5, else add -0.5. */
4137 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4138 LLVMBuildSelect(ctx->builder,
4139 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4140 val[chan], ctx->f32zero, ""),
4141 LLVMConstReal(ctx->f32, 0.5),
4142 LLVMConstReal(ctx->f32, -0.5), ""), "");
4143 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4144 }
4145
4146 args[4] = ctx->i32one;
4147 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4148 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4149 break;
4150
4151 case V_028714_SPI_SHADER_UINT16_ABGR: {
4152 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4153
4154 for (unsigned chan = 0; chan < 4; chan++) {
4155 val[chan] = to_integer(ctx, values[chan]);
4156 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4157 }
4158
4159 args[4] = ctx->i32one;
4160 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4161 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4162 break;
4163 }
4164
4165 case V_028714_SPI_SHADER_SINT16_ABGR: {
4166 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4167 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4168
4169 /* Clamp. */
4170 for (unsigned chan = 0; chan < 4; chan++) {
4171 val[chan] = to_integer(ctx, values[chan]);
4172 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4173 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4174 }
4175
4176 args[4] = ctx->i32one;
4177 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4178 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4179 break;
4180 }
4181
4182 default:
4183 case V_028714_SPI_SHADER_32_ABGR:
4184 memcpy(&args[5], values, sizeof(values[0]) * 4);
4185 break;
4186 }
4187 } else
4188 memcpy(&args[5], values, sizeof(values[0]) * 4);
4189
4190 for (unsigned i = 5; i < 9; ++i)
4191 args[i] = to_float(ctx, args[i]);
4192 }
4193
4194 static void
4195 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4196 {
4197 uint32_t param_count = 0;
4198 unsigned target;
4199 unsigned pos_idx, num_pos_exports = 0;
4200 LLVMValueRef args[9];
4201 LLVMValueRef pos_args[4][9] = { { 0 } };
4202 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4203 int i;
4204 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4205 (1ull << VARYING_SLOT_CLIP_DIST1) |
4206 (1ull << VARYING_SLOT_CULL_DIST0) |
4207 (1ull << VARYING_SLOT_CULL_DIST1));
4208
4209 if (clip_mask) {
4210 LLVMValueRef slots[8];
4211 unsigned j;
4212
4213 if (ctx->shader_info->vs.cull_dist_mask)
4214 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
4215
4216 i = VARYING_SLOT_CLIP_DIST0;
4217 for (j = 0; j < ctx->num_clips; j++)
4218 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4219 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4220 i = VARYING_SLOT_CULL_DIST0;
4221 for (j = 0; j < ctx->num_culls; j++)
4222 slots[ctx->num_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4223 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4224
4225 for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
4226 slots[i] = LLVMGetUndef(ctx->f32);
4227
4228 if (ctx->num_clips + ctx->num_culls > 4) {
4229 target = V_008DFC_SQ_EXP_POS + 3;
4230 si_llvm_init_export_args(ctx, &slots[4], target, args);
4231 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4232 args, sizeof(args));
4233 }
4234
4235 target = V_008DFC_SQ_EXP_POS + 2;
4236 si_llvm_init_export_args(ctx, &slots[0], target, args);
4237 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4238 args, sizeof(args));
4239
4240 }
4241
4242 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4243 LLVMValueRef values[4];
4244 if (!(ctx->output_mask & (1ull << i)))
4245 continue;
4246
4247 for (unsigned j = 0; j < 4; j++)
4248 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4249 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4250
4251 if (i == VARYING_SLOT_POS) {
4252 target = V_008DFC_SQ_EXP_POS;
4253 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4254 i == VARYING_SLOT_CLIP_DIST1 ||
4255 i == VARYING_SLOT_CULL_DIST0 ||
4256 i == VARYING_SLOT_CULL_DIST1) {
4257 continue;
4258 } else if (i == VARYING_SLOT_PSIZ) {
4259 ctx->shader_info->vs.writes_pointsize = true;
4260 psize_value = values[0];
4261 continue;
4262 } else if (i == VARYING_SLOT_LAYER) {
4263 ctx->shader_info->vs.writes_layer = true;
4264 layer_value = values[0];
4265 continue;
4266 } else if (i == VARYING_SLOT_VIEWPORT) {
4267 ctx->shader_info->vs.writes_viewport_index = true;
4268 viewport_index_value = values[0];
4269 continue;
4270 } else if (i >= VARYING_SLOT_VAR0) {
4271 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4272 target = V_008DFC_SQ_EXP_PARAM + param_count;
4273 param_count++;
4274 }
4275
4276 si_llvm_init_export_args(ctx, values, target, args);
4277
4278 if (target >= V_008DFC_SQ_EXP_POS &&
4279 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4280 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4281 args, sizeof(args));
4282 } else {
4283 ac_emit_llvm_intrinsic(&ctx->ac,
4284 "llvm.SI.export",
4285 ctx->voidt,
4286 args, 9, 0);
4287 }
4288 }
4289
4290 /* We need to add the position output manually if it's missing. */
4291 if (!pos_args[0][0]) {
4292 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4293 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4294 pos_args[0][2] = ctx->i32zero; /* last export? */
4295 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4296 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4297 pos_args[0][5] = ctx->f32zero; /* X */
4298 pos_args[0][6] = ctx->f32zero; /* Y */
4299 pos_args[0][7] = ctx->f32zero; /* Z */
4300 pos_args[0][8] = ctx->f32one; /* W */
4301 }
4302
4303 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4304 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4305 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4306 if (mask) {
4307 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4308 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4309 pos_args[1][2] = ctx->i32zero; /* last export? */
4310 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4311 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4312 pos_args[1][5] = ctx->f32zero; /* X */
4313 pos_args[1][6] = ctx->f32zero; /* Y */
4314 pos_args[1][7] = ctx->f32zero; /* Z */
4315 pos_args[1][8] = ctx->f32zero; /* W */
4316
4317 if (ctx->shader_info->vs.writes_pointsize == true)
4318 pos_args[1][5] = psize_value;
4319 if (ctx->shader_info->vs.writes_layer == true)
4320 pos_args[1][7] = layer_value;
4321 if (ctx->shader_info->vs.writes_viewport_index == true)
4322 pos_args[1][8] = viewport_index_value;
4323 }
4324 for (i = 0; i < 4; i++) {
4325 if (pos_args[i][0])
4326 num_pos_exports++;
4327 }
4328
4329 pos_idx = 0;
4330 for (i = 0; i < 4; i++) {
4331 if (!pos_args[i][0])
4332 continue;
4333
4334 /* Specify the target we are exporting */
4335 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4336 if (pos_idx == num_pos_exports)
4337 pos_args[i][2] = ctx->i32one;
4338 ac_emit_llvm_intrinsic(&ctx->ac,
4339 "llvm.SI.export",
4340 ctx->voidt,
4341 pos_args[i], 9, 0);
4342 }
4343
4344 ctx->shader_info->vs.pos_exports = num_pos_exports;
4345 ctx->shader_info->vs.param_exports = param_count;
4346 }
4347
4348 static void
4349 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4350 LLVMValueRef *color, unsigned param, bool is_last)
4351 {
4352 LLVMValueRef args[9];
4353 /* Export */
4354 si_llvm_init_export_args(ctx, color, param,
4355 args);
4356
4357 if (is_last) {
4358 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4359 args[2] = ctx->i32one; /* DONE bit */
4360 } else if (args[0] == ctx->i32zero)
4361 return; /* unnecessary NULL export */
4362
4363 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4364 ctx->voidt, args, 9, 0);
4365 }
4366
4367 static void
4368 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4369 LLVMValueRef depth, LLVMValueRef stencil,
4370 LLVMValueRef samplemask)
4371 {
4372 LLVMValueRef args[9];
4373 unsigned mask = 0;
4374 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4375 args[2] = ctx->i32one; /* DONE bit */
4376 /* Specify the target we are exporting */
4377 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4378
4379 args[4] = ctx->i32zero; /* COMP flag */
4380 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4381 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4382 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4383 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4384
4385 if (depth) {
4386 args[5] = depth;
4387 mask |= 0x1;
4388 }
4389
4390 if (stencil) {
4391 args[6] = stencil;
4392 mask |= 0x2;
4393 }
4394
4395 if (samplemask) {
4396 args[7] = samplemask;
4397 mask |= 0x04;
4398 }
4399
4400 /* SI (except OLAND) has a bug that it only looks
4401 * at the X writemask component. */
4402 if (ctx->options->chip_class == SI &&
4403 ctx->options->family != CHIP_OLAND)
4404 mask |= 0x01;
4405
4406 args[0] = LLVMConstInt(ctx->i32, mask, false);
4407 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4408 ctx->voidt, args, 9, 0);
4409 }
4410
4411 static void
4412 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4413 {
4414 unsigned index = 0;
4415 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4416
4417 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4418 LLVMValueRef values[4];
4419
4420 if (!(ctx->output_mask & (1ull << i)))
4421 continue;
4422
4423 if (i == FRAG_RESULT_DEPTH) {
4424 ctx->shader_info->fs.writes_z = true;
4425 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4426 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4427 } else if (i == FRAG_RESULT_STENCIL) {
4428 ctx->shader_info->fs.writes_stencil = true;
4429 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4430 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4431 } else {
4432 bool last = false;
4433 for (unsigned j = 0; j < 4; j++)
4434 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4435 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4436
4437 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4438 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4439
4440 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4441 index++;
4442 }
4443 }
4444
4445 if (depth || stencil)
4446 si_export_mrt_z(ctx, depth, stencil, samplemask);
4447 else if (!index)
4448 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4449
4450 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4451 }
4452
4453 static void
4454 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4455 {
4456 switch (ctx->stage) {
4457 case MESA_SHADER_VERTEX:
4458 handle_vs_outputs_post(ctx);
4459 break;
4460 case MESA_SHADER_FRAGMENT:
4461 handle_fs_outputs_post(ctx);
4462 break;
4463 default:
4464 break;
4465 }
4466 }
4467
4468 static void
4469 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4470 struct nir_variable *variable, uint32_t *offset, int idx)
4471 {
4472 unsigned size = glsl_count_attribute_slots(variable->type, false);
4473 variable->data.driver_location = *offset;
4474 *offset += size;
4475 }
4476
4477 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4478 {
4479 LLVMPassManagerRef passmgr;
4480 /* Create the pass manager */
4481 passmgr = LLVMCreateFunctionPassManagerForModule(
4482 ctx->module);
4483
4484 /* This pass should eliminate all the load and store instructions */
4485 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4486
4487 /* Add some optimization passes */
4488 LLVMAddScalarReplAggregatesPass(passmgr);
4489 LLVMAddLICMPass(passmgr);
4490 LLVMAddAggressiveDCEPass(passmgr);
4491 LLVMAddCFGSimplificationPass(passmgr);
4492 LLVMAddInstructionCombiningPass(passmgr);
4493
4494 /* Run the pass */
4495 LLVMInitializeFunctionPassManager(passmgr);
4496 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4497 LLVMFinalizeFunctionPassManager(passmgr);
4498
4499 LLVMDisposeBuilder(ctx->builder);
4500 LLVMDisposePassManager(passmgr);
4501 }
4502
4503 static void
4504 ac_setup_rings(struct nir_to_llvm_context *ctx)
4505 {
4506 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4507 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, ctx->i32one);
4508 }
4509
4510 if (ctx->is_gs_copy_shader) {
4511 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4512 }
4513 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4514 LLVMValueRef tmp;
4515 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4516 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4517
4518 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4519
4520 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4521 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4522 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4523 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4524
4525 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4526 }
4527 }
4528
4529 static
4530 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4531 struct nir_shader *nir,
4532 struct ac_shader_variant_info *shader_info,
4533 const struct ac_nir_compiler_options *options)
4534 {
4535 struct nir_to_llvm_context ctx = {0};
4536 struct nir_function *func;
4537 unsigned i;
4538 ctx.options = options;
4539 ctx.shader_info = shader_info;
4540 ctx.context = LLVMContextCreate();
4541 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4542
4543 ac_llvm_context_init(&ctx.ac, ctx.context);
4544 ctx.ac.module = ctx.module;
4545
4546 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4547
4548 memset(shader_info, 0, sizeof(*shader_info));
4549
4550 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4551 setup_types(&ctx);
4552
4553 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4554 ctx.ac.builder = ctx.builder;
4555 ctx.stage = nir->stage;
4556
4557 for (i = 0; i < AC_UD_MAX_SETS; i++)
4558 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4559 for (i = 0; i < AC_UD_MAX_UD; i++)
4560 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4561
4562 create_function(&ctx);
4563
4564 if (nir->stage == MESA_SHADER_COMPUTE) {
4565 int num_shared = 0;
4566 nir_foreach_variable(variable, &nir->shared)
4567 num_shared++;
4568 if (num_shared) {
4569 int idx = 0;
4570 uint32_t shared_size = 0;
4571 LLVMValueRef var;
4572 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4573 nir_foreach_variable(variable, &nir->shared) {
4574 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4575 idx++;
4576 }
4577
4578 shared_size *= 4;
4579 var = LLVMAddGlobalInAddressSpace(ctx.module,
4580 LLVMArrayType(ctx.i8, shared_size),
4581 "compute_lds",
4582 LOCAL_ADDR_SPACE);
4583 LLVMSetAlignment(var, 4);
4584 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4585 }
4586 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4587 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4588
4589 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4590 }
4591
4592 ac_setup_rings(&ctx);
4593
4594 nir_foreach_variable(variable, &nir->inputs)
4595 handle_shader_input_decl(&ctx, variable);
4596
4597 if (nir->stage == MESA_SHADER_FRAGMENT)
4598 handle_fs_inputs_pre(&ctx, nir);
4599
4600 nir_foreach_variable(variable, &nir->outputs)
4601 handle_shader_output_decl(&ctx, variable);
4602
4603 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4604 _mesa_key_pointer_equal);
4605 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4606 _mesa_key_pointer_equal);
4607
4608 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4609
4610 setup_locals(&ctx, func);
4611
4612 visit_cf_list(&ctx, &func->impl->body);
4613 phi_post_pass(&ctx);
4614
4615 handle_shader_outputs_post(&ctx);
4616 LLVMBuildRetVoid(ctx.builder);
4617
4618 ac_llvm_finalize_module(&ctx);
4619 free(ctx.locals);
4620 ralloc_free(ctx.defs);
4621 ralloc_free(ctx.phis);
4622
4623 return ctx.module;
4624 }
4625
4626 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4627 {
4628 unsigned *retval = (unsigned *)context;
4629 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4630 char *description = LLVMGetDiagInfoDescription(di);
4631
4632 if (severity == LLVMDSError) {
4633 *retval = 1;
4634 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4635 description);
4636 }
4637
4638 LLVMDisposeMessage(description);
4639 }
4640
4641 static unsigned ac_llvm_compile(LLVMModuleRef M,
4642 struct ac_shader_binary *binary,
4643 LLVMTargetMachineRef tm)
4644 {
4645 unsigned retval = 0;
4646 char *err;
4647 LLVMContextRef llvm_ctx;
4648 LLVMMemoryBufferRef out_buffer;
4649 unsigned buffer_size;
4650 const char *buffer_data;
4651 LLVMBool mem_err;
4652
4653 /* Setup Diagnostic Handler*/
4654 llvm_ctx = LLVMGetModuleContext(M);
4655
4656 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4657 &retval);
4658
4659 /* Compile IR*/
4660 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4661 &err, &out_buffer);
4662
4663 /* Process Errors/Warnings */
4664 if (mem_err) {
4665 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4666 free(err);
4667 retval = 1;
4668 goto out;
4669 }
4670
4671 /* Extract Shader Code*/
4672 buffer_size = LLVMGetBufferSize(out_buffer);
4673 buffer_data = LLVMGetBufferStart(out_buffer);
4674
4675 ac_elf_read(buffer_data, buffer_size, binary);
4676
4677 /* Clean up */
4678 LLVMDisposeMemoryBuffer(out_buffer);
4679
4680 out:
4681 return retval;
4682 }
4683
4684 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4685 LLVMModuleRef llvm_module,
4686 struct ac_shader_binary *binary,
4687 struct ac_shader_config *config,
4688 struct ac_shader_variant_info *shader_info,
4689 gl_shader_stage stage,
4690 bool dump_shader, bool supports_spill)
4691 {
4692 if (dump_shader)
4693 ac_dump_module(llvm_module);
4694
4695 memset(binary, 0, sizeof(*binary));
4696 int v = ac_llvm_compile(llvm_module, binary, tm);
4697 if (v) {
4698 fprintf(stderr, "compile failed\n");
4699 }
4700
4701 if (dump_shader)
4702 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4703
4704 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4705
4706 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4707 LLVMDisposeModule(llvm_module);
4708 LLVMContextDispose(ctx);
4709
4710 if (stage == MESA_SHADER_FRAGMENT) {
4711 shader_info->num_input_vgprs = 0;
4712 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4713 shader_info->num_input_vgprs += 2;
4714 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4715 shader_info->num_input_vgprs += 2;
4716 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4717 shader_info->num_input_vgprs += 2;
4718 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4719 shader_info->num_input_vgprs += 3;
4720 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4721 shader_info->num_input_vgprs += 2;
4722 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4723 shader_info->num_input_vgprs += 2;
4724 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4725 shader_info->num_input_vgprs += 2;
4726 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4727 shader_info->num_input_vgprs += 1;
4728 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
4729 shader_info->num_input_vgprs += 1;
4730 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
4731 shader_info->num_input_vgprs += 1;
4732 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
4733 shader_info->num_input_vgprs += 1;
4734 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
4735 shader_info->num_input_vgprs += 1;
4736 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
4737 shader_info->num_input_vgprs += 1;
4738 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
4739 shader_info->num_input_vgprs += 1;
4740 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
4741 shader_info->num_input_vgprs += 1;
4742 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
4743 shader_info->num_input_vgprs += 1;
4744 }
4745 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
4746
4747 /* +3 for scratch wave offset and VCC */
4748 config->num_sgprs = MAX2(config->num_sgprs,
4749 shader_info->num_input_sgprs + 3);
4750 }
4751
4752 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
4753 struct ac_shader_binary *binary,
4754 struct ac_shader_config *config,
4755 struct ac_shader_variant_info *shader_info,
4756 struct nir_shader *nir,
4757 const struct ac_nir_compiler_options *options,
4758 bool dump_shader)
4759 {
4760
4761 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
4762 options);
4763
4764 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
4765 switch (nir->stage) {
4766 case MESA_SHADER_COMPUTE:
4767 for (int i = 0; i < 3; ++i)
4768 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
4769 break;
4770 case MESA_SHADER_FRAGMENT:
4771 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
4772 break;
4773 case MESA_SHADER_GEOMETRY:
4774 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
4775 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
4776 shader_info->gs.output_prim = nir->info->gs.output_primitive;
4777 shader_info->gs.invocations = nir->info->gs.invocations;
4778 break;
4779 default:
4780 break;
4781 }
4782 }