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ac: add v3i32 to the common code and make use of it
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 RADEON_LLVM_AMDGPU_HS = 93,
43 };
44
45 #define CONST_ADDR_SPACE 2
46 #define LOCAL_ADDR_SPACE 3
47
48 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
50
51 struct nir_to_llvm_context;
52
53 struct ac_nir_context {
54 struct ac_llvm_context ac;
55 struct ac_shader_abi *abi;
56
57 gl_shader_stage stage;
58
59 struct hash_table *defs;
60 struct hash_table *phis;
61 struct hash_table *vars;
62
63 LLVMValueRef main_function;
64 LLVMBasicBlockRef continue_block;
65 LLVMBasicBlockRef break_block;
66
67 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
68
69 int num_locals;
70 LLVMValueRef *locals;
71
72 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
73 };
74
75 struct nir_to_llvm_context {
76 struct ac_llvm_context ac;
77 const struct ac_nir_compiler_options *options;
78 struct ac_shader_variant_info *shader_info;
79 struct ac_shader_abi abi;
80 struct ac_nir_context *nir;
81
82 unsigned max_workgroup_size;
83 LLVMContextRef context;
84 LLVMModuleRef module;
85 LLVMBuilderRef builder;
86 LLVMValueRef main_function;
87
88 struct hash_table *defs;
89 struct hash_table *phis;
90
91 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
92 LLVMValueRef ring_offsets;
93 LLVMValueRef push_constants;
94 LLVMValueRef view_index;
95 LLVMValueRef num_work_groups;
96 LLVMValueRef workgroup_ids;
97 LLVMValueRef local_invocation_ids;
98 LLVMValueRef tg_size;
99
100 LLVMValueRef vertex_buffers;
101 LLVMValueRef rel_auto_id;
102 LLVMValueRef vs_prim_id;
103 LLVMValueRef ls_out_layout;
104 LLVMValueRef es2gs_offset;
105
106 LLVMValueRef tcs_offchip_layout;
107 LLVMValueRef tcs_out_offsets;
108 LLVMValueRef tcs_out_layout;
109 LLVMValueRef tcs_in_layout;
110 LLVMValueRef oc_lds;
111 LLVMValueRef merged_wave_info;
112 LLVMValueRef tess_factor_offset;
113 LLVMValueRef tcs_patch_id;
114 LLVMValueRef tcs_rel_ids;
115 LLVMValueRef tes_rel_patch_id;
116 LLVMValueRef tes_patch_id;
117 LLVMValueRef tes_u;
118 LLVMValueRef tes_v;
119
120 LLVMValueRef gsvs_ring_stride;
121 LLVMValueRef gsvs_num_entries;
122 LLVMValueRef gs2vs_offset;
123 LLVMValueRef gs_wave_id;
124 LLVMValueRef gs_vtx_offset[6];
125 LLVMValueRef gs_prim_id, gs_invocation_id;
126
127 LLVMValueRef esgs_ring;
128 LLVMValueRef gsvs_ring;
129 LLVMValueRef hs_ring_tess_offchip;
130 LLVMValueRef hs_ring_tess_factor;
131
132 LLVMValueRef prim_mask;
133 LLVMValueRef sample_pos_offset;
134 LLVMValueRef persp_sample, persp_center, persp_centroid;
135 LLVMValueRef linear_sample, linear_center, linear_centroid;
136
137 LLVMTypeRef v4i32;
138 LLVMTypeRef v8i32;
139 LLVMTypeRef f64;
140 LLVMTypeRef f32;
141 LLVMTypeRef f16;
142 LLVMTypeRef v2f32;
143 LLVMTypeRef v4f32;
144
145 unsigned uniform_md_kind;
146 LLVMValueRef empty_md;
147 gl_shader_stage stage;
148
149 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
150
151 uint64_t input_mask;
152 uint64_t output_mask;
153 uint8_t num_output_clips;
154 uint8_t num_output_culls;
155
156 bool is_gs_copy_shader;
157 LLVMValueRef gs_next_vertex;
158 unsigned gs_max_out_vertices;
159
160 unsigned tes_primitive_mode;
161 uint64_t tess_outputs_written;
162 uint64_t tess_patch_outputs_written;
163 };
164
165 static inline struct nir_to_llvm_context *
166 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
167 {
168 struct nir_to_llvm_context *ctx = NULL;
169 return container_of(abi, ctx, abi);
170 }
171
172 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
173 const nir_deref_var *deref,
174 enum ac_descriptor_type desc_type,
175 const nir_tex_instr *instr,
176 bool image, bool write);
177
178 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
179 {
180 return (index * 4) + chan;
181 }
182
183 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
184 {
185 /* handle patch indices separate */
186 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
187 return 0;
188 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
189 return 1;
190 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
191 return 2 + (slot - VARYING_SLOT_PATCH0);
192
193 if (slot == VARYING_SLOT_POS)
194 return 0;
195 if (slot == VARYING_SLOT_PSIZ)
196 return 1;
197 if (slot == VARYING_SLOT_CLIP_DIST0)
198 return 2;
199 /* 3 is reserved for clip dist as well */
200 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
201 return 4 + (slot - VARYING_SLOT_VAR0);
202 unreachable("illegal slot in get unique index\n");
203 }
204
205 static void set_llvm_calling_convention(LLVMValueRef func,
206 gl_shader_stage stage)
207 {
208 enum radeon_llvm_calling_convention calling_conv;
209
210 switch (stage) {
211 case MESA_SHADER_VERTEX:
212 case MESA_SHADER_TESS_EVAL:
213 calling_conv = RADEON_LLVM_AMDGPU_VS;
214 break;
215 case MESA_SHADER_GEOMETRY:
216 calling_conv = RADEON_LLVM_AMDGPU_GS;
217 break;
218 case MESA_SHADER_TESS_CTRL:
219 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
220 break;
221 case MESA_SHADER_FRAGMENT:
222 calling_conv = RADEON_LLVM_AMDGPU_PS;
223 break;
224 case MESA_SHADER_COMPUTE:
225 calling_conv = RADEON_LLVM_AMDGPU_CS;
226 break;
227 default:
228 unreachable("Unhandle shader type");
229 }
230
231 LLVMSetFunctionCallConv(func, calling_conv);
232 }
233
234 #define MAX_ARGS 23
235 struct arg_info {
236 LLVMTypeRef types[MAX_ARGS];
237 LLVMValueRef *assign[MAX_ARGS];
238 unsigned array_params_mask;
239 uint8_t count;
240 uint8_t user_sgpr_count;
241 uint8_t sgpr_count;
242 uint8_t num_user_sgprs_used;
243 uint8_t num_sgprs_used;
244 uint8_t num_vgprs_used;
245 };
246
247 static inline void
248 add_argument(struct arg_info *info,
249 LLVMTypeRef type, LLVMValueRef *param_ptr)
250 {
251 assert(info->count < MAX_ARGS);
252 info->assign[info->count] = param_ptr;
253 info->types[info->count] = type;
254 info->count++;
255 }
256
257 static inline void
258 add_sgpr_argument(struct arg_info *info,
259 LLVMTypeRef type, LLVMValueRef *param_ptr)
260 {
261 add_argument(info, type, param_ptr);
262 info->num_sgprs_used += ac_get_type_size(type) / 4;
263 info->sgpr_count++;
264 }
265
266 static inline void
267 add_user_sgpr_argument(struct arg_info *info,
268 LLVMTypeRef type,
269 LLVMValueRef *param_ptr)
270 {
271 add_sgpr_argument(info, type, param_ptr);
272 info->num_user_sgprs_used += ac_get_type_size(type) / 4;
273 info->user_sgpr_count++;
274 }
275
276 static inline void
277 add_vgpr_argument(struct arg_info *info,
278 LLVMTypeRef type,
279 LLVMValueRef *param_ptr)
280 {
281 add_argument(info, type, param_ptr);
282 info->num_vgprs_used += ac_get_type_size(type) / 4;
283 }
284
285 static inline void
286 add_user_sgpr_array_argument(struct arg_info *info,
287 LLVMTypeRef type,
288 LLVMValueRef *param_ptr)
289 {
290 info->array_params_mask |= (1 << info->count);
291 add_user_sgpr_argument(info, type, param_ptr);
292 }
293
294 static void assign_arguments(LLVMValueRef main_function,
295 struct arg_info *info)
296 {
297 unsigned i;
298 for (i = 0; i < info->count; i++) {
299 if (info->assign[i])
300 *info->assign[i] = LLVMGetParam(main_function, i);
301 }
302 }
303
304 static LLVMValueRef
305 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
306 LLVMBuilderRef builder, LLVMTypeRef *return_types,
307 unsigned num_return_elems,
308 struct arg_info *args,
309 unsigned max_workgroup_size,
310 bool unsafe_math)
311 {
312 LLVMTypeRef main_function_type, ret_type;
313 LLVMBasicBlockRef main_function_body;
314
315 if (num_return_elems)
316 ret_type = LLVMStructTypeInContext(ctx, return_types,
317 num_return_elems, true);
318 else
319 ret_type = LLVMVoidTypeInContext(ctx);
320
321 /* Setup the function */
322 main_function_type =
323 LLVMFunctionType(ret_type, args->types, args->count, 0);
324 LLVMValueRef main_function =
325 LLVMAddFunction(module, "main", main_function_type);
326 main_function_body =
327 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
328 LLVMPositionBuilderAtEnd(builder, main_function_body);
329
330 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
331 for (unsigned i = 0; i < args->sgpr_count; ++i) {
332 if (args->array_params_mask & (1 << i)) {
333 LLVMValueRef P = LLVMGetParam(main_function, i);
334 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
335 ac_add_attr_dereferenceable(P, UINT64_MAX);
336 }
337 else {
338 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
339 }
340 }
341
342 if (max_workgroup_size) {
343 ac_llvm_add_target_dep_function_attr(main_function,
344 "amdgpu-max-work-group-size",
345 max_workgroup_size);
346 }
347 if (unsafe_math) {
348 /* These were copied from some LLVM test. */
349 LLVMAddTargetDependentFunctionAttr(main_function,
350 "less-precise-fpmad",
351 "true");
352 LLVMAddTargetDependentFunctionAttr(main_function,
353 "no-infs-fp-math",
354 "true");
355 LLVMAddTargetDependentFunctionAttr(main_function,
356 "no-nans-fp-math",
357 "true");
358 LLVMAddTargetDependentFunctionAttr(main_function,
359 "unsafe-fp-math",
360 "true");
361 }
362 return main_function;
363 }
364
365 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
366 {
367 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
368 CONST_ADDR_SPACE);
369 }
370
371 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
372 {
373 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
374 type = LLVMGetElementType(type);
375
376 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
377 return LLVMGetIntTypeWidth(type);
378
379 if (type == ctx->f16)
380 return 16;
381 if (type == ctx->f32)
382 return 32;
383 if (type == ctx->f64)
384 return 64;
385
386 unreachable("Unhandled type kind in get_elem_bits");
387 }
388
389 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
390 LLVMValueRef param, unsigned rshift,
391 unsigned bitwidth)
392 {
393 LLVMValueRef value = param;
394 if (rshift)
395 value = LLVMBuildLShr(ctx->builder, value,
396 LLVMConstInt(ctx->i32, rshift, false), "");
397
398 if (rshift + bitwidth < 32) {
399 unsigned mask = (1 << bitwidth) - 1;
400 value = LLVMBuildAnd(ctx->builder, value,
401 LLVMConstInt(ctx->i32, mask, false), "");
402 }
403 return value;
404 }
405
406 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
407 {
408 switch (ctx->stage) {
409 case MESA_SHADER_TESS_CTRL:
410 return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
411 case MESA_SHADER_TESS_EVAL:
412 return ctx->tes_rel_patch_id;
413 break;
414 default:
415 unreachable("Illegal stage");
416 }
417 }
418
419 /* Tessellation shaders pass outputs to the next shader using LDS.
420 *
421 * LS outputs = TCS inputs
422 * TCS outputs = TES inputs
423 *
424 * The LDS layout is:
425 * - TCS inputs for patch 0
426 * - TCS inputs for patch 1
427 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
428 * - ...
429 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
430 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
431 * - TCS outputs for patch 1
432 * - Per-patch TCS outputs for patch 1
433 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
434 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
435 * - ...
436 *
437 * All three shaders VS(LS), TCS, TES share the same LDS space.
438 */
439 static LLVMValueRef
440 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
441 {
442 if (ctx->stage == MESA_SHADER_VERTEX)
443 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
444 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
445 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
446 else {
447 assert(0);
448 return NULL;
449 }
450 }
451
452 static LLVMValueRef
453 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
454 {
455 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
456 }
457
458 static LLVMValueRef
459 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
460 {
461 return LLVMBuildMul(ctx->builder,
462 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
463 LLVMConstInt(ctx->ac.i32, 4, false), "");
464 }
465
466 static LLVMValueRef
467 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
468 {
469 return LLVMBuildMul(ctx->builder,
470 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
471 LLVMConstInt(ctx->ac.i32, 4, false), "");
472 }
473
474 static LLVMValueRef
475 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
476 {
477 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
478 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
479
480 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
481 }
482
483 static LLVMValueRef
484 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
485 {
486 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
487 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
488 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
489
490 return LLVMBuildAdd(ctx->builder, patch0_offset,
491 LLVMBuildMul(ctx->builder, patch_stride,
492 rel_patch_id, ""),
493 "");
494 }
495
496 static LLVMValueRef
497 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
498 {
499 LLVMValueRef patch0_patch_data_offset =
500 get_tcs_out_patch0_patch_data_offset(ctx);
501 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
502 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
503
504 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
505 LLVMBuildMul(ctx->builder, patch_stride,
506 rel_patch_id, ""),
507 "");
508 }
509
510 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
511 {
512 ud_info->sgpr_idx = *sgpr_idx;
513 ud_info->num_sgprs = num_sgprs;
514 ud_info->indirect = false;
515 ud_info->indirect_offset = 0;
516 *sgpr_idx += num_sgprs;
517 }
518
519 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
520 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
521 {
522 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
523 }
524
525
526 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
527 uint32_t indirect_offset)
528 {
529 ud_info->sgpr_idx = sgpr_idx;
530 ud_info->num_sgprs = num_sgprs;
531 ud_info->indirect = true;
532 ud_info->indirect_offset = indirect_offset;
533 }
534
535 struct user_sgpr_info {
536 bool need_ring_offsets;
537 uint8_t sgpr_count;
538 bool indirect_all_descriptor_sets;
539 };
540
541 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
542 struct user_sgpr_info *user_sgpr_info)
543 {
544 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
545
546 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
547 if (ctx->stage == MESA_SHADER_GEOMETRY ||
548 ctx->stage == MESA_SHADER_VERTEX ||
549 ctx->stage == MESA_SHADER_TESS_CTRL ||
550 ctx->stage == MESA_SHADER_TESS_EVAL ||
551 ctx->is_gs_copy_shader)
552 user_sgpr_info->need_ring_offsets = true;
553
554 if (ctx->stage == MESA_SHADER_FRAGMENT &&
555 ctx->shader_info->info.ps.needs_sample_positions)
556 user_sgpr_info->need_ring_offsets = true;
557
558 /* 2 user sgprs will nearly always be allocated for scratch/rings */
559 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
560 user_sgpr_info->sgpr_count += 2;
561 }
562
563 switch (ctx->stage) {
564 case MESA_SHADER_COMPUTE:
565 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
566 break;
567 case MESA_SHADER_FRAGMENT:
568 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
569 break;
570 case MESA_SHADER_VERTEX:
571 if (!ctx->is_gs_copy_shader) {
572 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
573 if (ctx->shader_info->info.vs.needs_draw_id) {
574 user_sgpr_info->sgpr_count += 3;
575 } else {
576 user_sgpr_info->sgpr_count += 2;
577 }
578 }
579 if (ctx->options->key.vs.as_ls)
580 user_sgpr_info->sgpr_count++;
581 break;
582 case MESA_SHADER_TESS_CTRL:
583 user_sgpr_info->sgpr_count += 4;
584 break;
585 case MESA_SHADER_TESS_EVAL:
586 user_sgpr_info->sgpr_count += 1;
587 break;
588 case MESA_SHADER_GEOMETRY:
589 user_sgpr_info->sgpr_count += 2;
590 break;
591 default:
592 break;
593 }
594
595 if (ctx->shader_info->info.needs_push_constants)
596 user_sgpr_info->sgpr_count += 2;
597
598 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
599 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
600 user_sgpr_info->sgpr_count += 2;
601 user_sgpr_info->indirect_all_descriptor_sets = true;
602 } else {
603 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
604 }
605 }
606
607 static void
608 radv_define_common_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
609 gl_shader_stage stage,
610 bool has_previous_stage,
611 gl_shader_stage previous_stage,
612 const struct user_sgpr_info *user_sgpr_info,
613 struct arg_info *args,
614 LLVMValueRef *desc_sets)
615 {
616 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
617 unsigned stage_mask = 1 << stage;
618 if (has_previous_stage)
619 stage_mask |= 1 << previous_stage;
620
621 /* 1 for each descriptor set */
622 if (!user_sgpr_info->indirect_all_descriptor_sets) {
623 for (unsigned i = 0; i < num_sets; ++i) {
624 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
625 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->descriptor_sets[i]);
626 }
627 }
628 } else
629 add_user_sgpr_array_argument(args, const_array(const_array(ctx->ac.i8, 1024 * 1024), 32), desc_sets);
630
631 if (ctx->shader_info->info.needs_push_constants) {
632 /* 1 for push constants and dynamic descriptors */
633 add_user_sgpr_array_argument(args, const_array(ctx->ac.i8, 1024 * 1024), &ctx->push_constants);
634 }
635 }
636
637 static void
638 radv_define_common_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
639 gl_shader_stage stage,
640 bool has_previous_stage,
641 gl_shader_stage previous_stage,
642 const struct user_sgpr_info *user_sgpr_info,
643 LLVMValueRef desc_sets,
644 uint8_t *user_sgpr_idx)
645 {
646 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
647 unsigned stage_mask = 1 << stage;
648 if (has_previous_stage)
649 stage_mask |= 1 << previous_stage;
650
651 if (!user_sgpr_info->indirect_all_descriptor_sets) {
652 for (unsigned i = 0; i < num_sets; ++i) {
653 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
654 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
655 } else
656 ctx->descriptor_sets[i] = NULL;
657 }
658 } else {
659 uint32_t desc_sgpr_idx = *user_sgpr_idx;
660 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
661
662 for (unsigned i = 0; i < num_sets; ++i) {
663 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
664 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
665 ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
666
667 } else
668 ctx->descriptor_sets[i] = NULL;
669 }
670 ctx->shader_info->need_indirect_descriptor_sets = true;
671 }
672
673 if (ctx->shader_info->info.needs_push_constants) {
674 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
675 }
676 }
677
678 static void
679 radv_define_vs_user_sgprs_phase1(struct nir_to_llvm_context *ctx,
680 gl_shader_stage stage,
681 bool has_previous_stage,
682 gl_shader_stage previous_stage,
683 struct arg_info *args)
684 {
685 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
686 if (ctx->shader_info->info.vs.has_vertex_buffers)
687 add_user_sgpr_argument(args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
688 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.base_vertex); // base vertex
689 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.start_instance);// start instance
690 if (ctx->shader_info->info.vs.needs_draw_id)
691 add_user_sgpr_argument(args, ctx->ac.i32, &ctx->abi.draw_id); // draw id
692 }
693 }
694
695 static void
696 radv_define_vs_user_sgprs_phase2(struct nir_to_llvm_context *ctx,
697 gl_shader_stage stage,
698 bool has_previous_stage,
699 gl_shader_stage previous_stage,
700 uint8_t *user_sgpr_idx)
701 {
702 if (!ctx->is_gs_copy_shader && (stage == MESA_SHADER_VERTEX || (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
703 if (ctx->shader_info->info.vs.has_vertex_buffers) {
704 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
705 }
706 unsigned vs_num = 2;
707 if (ctx->shader_info->info.vs.needs_draw_id)
708 vs_num++;
709
710 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
711 }
712 }
713
714
715 static void create_function(struct nir_to_llvm_context *ctx,
716 gl_shader_stage stage,
717 bool has_previous_stage,
718 gl_shader_stage previous_stage)
719 {
720 uint8_t user_sgpr_idx;
721 struct user_sgpr_info user_sgpr_info;
722 struct arg_info args = {};
723 LLVMValueRef desc_sets;
724
725 allocate_user_sgprs(ctx, &user_sgpr_info);
726
727 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
728 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
729 }
730
731 switch (stage) {
732 case MESA_SHADER_COMPUTE:
733 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
734 if (ctx->shader_info->info.cs.grid_components_used)
735 add_user_sgpr_argument(&args, LLVMVectorType(ctx->ac.i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
736 add_sgpr_argument(&args, ctx->ac.v3i32, &ctx->workgroup_ids);
737 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
738 add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
739 break;
740 case MESA_SHADER_VERTEX:
741 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
742 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
743 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
744 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
745 if (ctx->options->key.vs.as_es)
746 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
747 else if (ctx->options->key.vs.as_ls)
748 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
749 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
750 if (!ctx->is_gs_copy_shader) {
751 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
752 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
753 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
754 }
755 break;
756 case MESA_SHADER_TESS_CTRL:
757 if (has_previous_stage) {
758 // First 6 system regs
759 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
760 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
761 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
762
763 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
764 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
765 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
766
767 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
768 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
769 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout
770
771 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
772 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
773 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
774 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
775 if (ctx->shader_info->info.needs_multiview_view_index)
776 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
777
778 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
779 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
780 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
781 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
782 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
783 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
784 } else {
785 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
786 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
787 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_offsets); // tcs out offsets
788 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_out_layout); // tcs out layout
789 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_in_layout); // tcs in layout
790 if (ctx->shader_info->info.needs_multiview_view_index)
791 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
792 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
793 add_sgpr_argument(&args, ctx->ac.i32, &ctx->tess_factor_offset); // tess factor offset
794 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_patch_id); // patch id
795 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tcs_rel_ids); // rel ids;
796 }
797 break;
798 case MESA_SHADER_TESS_EVAL:
799 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
800 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
801 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
802 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
803 if (ctx->options->key.tes.as_es) {
804 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
805 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
806 add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset
807 } else {
808 add_sgpr_argument(&args, ctx->ac.i32, NULL); //
809 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // OC LDS
810 }
811 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
812 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
813 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
814 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
815 break;
816 case MESA_SHADER_GEOMETRY:
817 if (has_previous_stage) {
818 // First 6 system regs
819 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // tess factor offset
820 add_sgpr_argument(&args, ctx->ac.i32, &ctx->merged_wave_info); // merged wave info
821 add_sgpr_argument(&args, ctx->ac.i32, &ctx->oc_lds); // param oc lds
822
823 add_sgpr_argument(&args, ctx->ac.i32, NULL); // scratch offset
824 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
825 add_sgpr_argument(&args, ctx->ac.i32, NULL); // unknown
826
827 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
828 if (previous_stage == MESA_SHADER_TESS_EVAL)
829 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->tcs_offchip_layout); // tcs offchip layout
830 else
831 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
832 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
833 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
834 if (ctx->shader_info->info.needs_multiview_view_index)
835 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
836
837 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx01
838 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]); // vtx23
839 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_prim_id); // prim id
840 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_invocation_id);
841 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
842
843 if (previous_stage == MESA_SHADER_VERTEX) {
844 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.vertex_id); // vertex id
845 add_vgpr_argument(&args, ctx->ac.i32, &ctx->rel_auto_id); // rel auto id
846 add_vgpr_argument(&args, ctx->ac.i32, &ctx->vs_prim_id); // vs prim id
847 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.instance_id); // instance id
848 } else {
849 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
850 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
851 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_rel_patch_id); // tes rel patch id
852 add_vgpr_argument(&args, ctx->ac.i32, &ctx->tes_patch_id); // tes patch id
853 }
854 } else {
855 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
856 radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args);
857 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_ring_stride); // gsvs stride
858 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->gsvs_num_entries); // gsvs num entires
859 if (ctx->shader_info->info.needs_multiview_view_index)
860 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index);
861 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs2vs_offset); // gs2vs offset
862 add_sgpr_argument(&args, ctx->ac.i32, &ctx->gs_wave_id); // wave id
863 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[0]); // vtx0
864 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[1]); // vtx1
865 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_prim_id); // prim id
866 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[2]);
867 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[3]);
868 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[4]);
869 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_vtx_offset[5]);
870 add_vgpr_argument(&args, ctx->ac.i32, &ctx->gs_invocation_id);
871 }
872 break;
873 case MESA_SHADER_FRAGMENT:
874 radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
875 if (ctx->shader_info->info.ps.needs_sample_positions)
876 add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */
877 add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */
878 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */
879 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */
880 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */
881 add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */
882 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */
883 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */
884 add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */
885 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
886 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */
887 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */
888 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */
889 add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */
890 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */
891 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */
892 add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.sample_coverage); /* sample coverage */
893 add_vgpr_argument(&args, ctx->ac.i32, NULL); /* fixed pt */
894 break;
895 default:
896 unreachable("Shader stage not implemented");
897 }
898
899 ctx->main_function = create_llvm_function(
900 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
901 ctx->max_workgroup_size,
902 ctx->options->unsafe_math);
903 set_llvm_calling_convention(ctx->main_function, stage);
904
905
906 ctx->shader_info->num_input_vgprs = 0;
907 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
908
909 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
910
911 if (ctx->stage != MESA_SHADER_FRAGMENT)
912 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
913
914 assign_arguments(ctx->main_function, &args);
915
916 user_sgpr_idx = 0;
917
918 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
919 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
920 if (ctx->options->supports_spill) {
921 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
922 LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
923 NULL, 0, AC_FUNC_ATTR_READNONE);
924 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
925 const_array(ctx->v4i32, 16), "");
926 }
927 }
928
929 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
930 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
931 if (has_previous_stage)
932 user_sgpr_idx = 0;
933
934 radv_define_common_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, desc_sets, &user_sgpr_idx);
935
936 switch (stage) {
937 case MESA_SHADER_COMPUTE:
938 if (ctx->shader_info->info.cs.grid_components_used) {
939 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
940 }
941 break;
942 case MESA_SHADER_VERTEX:
943 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
944 if (ctx->view_index)
945 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
946 if (ctx->options->key.vs.as_ls) {
947 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
948 }
949 if (ctx->options->key.vs.as_ls)
950 ac_declare_lds_as_pointer(&ctx->ac);
951 break;
952 case MESA_SHADER_TESS_CTRL:
953 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
954 if (has_previous_stage)
955 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
956 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
957 if (ctx->view_index)
958 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
959 ac_declare_lds_as_pointer(&ctx->ac);
960 break;
961 case MESA_SHADER_TESS_EVAL:
962 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
963 if (ctx->view_index)
964 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
965 break;
966 case MESA_SHADER_GEOMETRY:
967 if (has_previous_stage) {
968 if (previous_stage == MESA_SHADER_VERTEX)
969 radv_define_vs_user_sgprs_phase2(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_idx);
970 else
971 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
972 }
973 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
974 if (ctx->view_index)
975 set_userdata_location_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
976 if (has_previous_stage)
977 ac_declare_lds_as_pointer(&ctx->ac);
978 break;
979 case MESA_SHADER_FRAGMENT:
980 if (ctx->shader_info->info.ps.needs_sample_positions) {
981 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
982 }
983 break;
984 default:
985 unreachable("Shader stage not implemented");
986 }
987
988 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
989 }
990
991 static void setup_types(struct nir_to_llvm_context *ctx)
992 {
993 ctx->v4i32 = LLVMVectorType(ctx->ac.i32, 4);
994 ctx->v8i32 = LLVMVectorType(ctx->ac.i32, 8);
995 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
996 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
997 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
998 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
999 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
1000
1001 ctx->uniform_md_kind =
1002 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
1003 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
1004 }
1005
1006 static int get_llvm_num_components(LLVMValueRef value)
1007 {
1008 LLVMTypeRef type = LLVMTypeOf(value);
1009 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1010 ? LLVMGetVectorSize(type)
1011 : 1;
1012 return num_components;
1013 }
1014
1015 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
1016 LLVMValueRef value,
1017 int index)
1018 {
1019 int count = get_llvm_num_components(value);
1020
1021 if (count == 1)
1022 return value;
1023
1024 return LLVMBuildExtractElement(ac->builder, value,
1025 LLVMConstInt(ac->i32, index, false), "");
1026 }
1027
1028 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1029 LLVMValueRef value, unsigned count)
1030 {
1031 unsigned num_components = get_llvm_num_components(value);
1032 if (count == num_components)
1033 return value;
1034
1035 LLVMValueRef masks[] = {
1036 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1037 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1038
1039 if (count == 1)
1040 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1041 "");
1042
1043 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1044 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1045 }
1046
1047 static void
1048 build_store_values_extended(struct ac_llvm_context *ac,
1049 LLVMValueRef *values,
1050 unsigned value_count,
1051 unsigned value_stride,
1052 LLVMValueRef vec)
1053 {
1054 LLVMBuilderRef builder = ac->builder;
1055 unsigned i;
1056
1057 for (i = 0; i < value_count; i++) {
1058 LLVMValueRef ptr = values[i * value_stride];
1059 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1060 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1061 LLVMBuildStore(builder, value, ptr);
1062 }
1063 }
1064
1065 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1066 const nir_ssa_def *def)
1067 {
1068 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1069 if (def->num_components > 1) {
1070 type = LLVMVectorType(type, def->num_components);
1071 }
1072 return type;
1073 }
1074
1075 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1076 {
1077 assert(src.is_ssa);
1078 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1079 return (LLVMValueRef)entry->data;
1080 }
1081
1082
1083 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1084 const struct nir_block *b)
1085 {
1086 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1087 return (LLVMBasicBlockRef)entry->data;
1088 }
1089
1090 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1091 nir_alu_src src,
1092 unsigned num_components)
1093 {
1094 LLVMValueRef value = get_src(ctx, src.src);
1095 bool need_swizzle = false;
1096
1097 assert(value);
1098 LLVMTypeRef type = LLVMTypeOf(value);
1099 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1100 ? LLVMGetVectorSize(type)
1101 : 1;
1102
1103 for (unsigned i = 0; i < num_components; ++i) {
1104 assert(src.swizzle[i] < src_components);
1105 if (src.swizzle[i] != i)
1106 need_swizzle = true;
1107 }
1108
1109 if (need_swizzle || num_components != src_components) {
1110 LLVMValueRef masks[] = {
1111 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1112 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1113 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1114 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1115
1116 if (src_components > 1 && num_components == 1) {
1117 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1118 masks[0], "");
1119 } else if (src_components == 1 && num_components > 1) {
1120 LLVMValueRef values[] = {value, value, value, value};
1121 value = ac_build_gather_values(&ctx->ac, values, num_components);
1122 } else {
1123 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1124 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1125 swizzle, "");
1126 }
1127 }
1128 assert(!src.negate);
1129 assert(!src.abs);
1130 return value;
1131 }
1132
1133 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1134 LLVMIntPredicate pred, LLVMValueRef src0,
1135 LLVMValueRef src1)
1136 {
1137 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1138 return LLVMBuildSelect(ctx->builder, result,
1139 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1140 LLVMConstInt(ctx->i32, 0, false), "");
1141 }
1142
1143 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1144 LLVMRealPredicate pred, LLVMValueRef src0,
1145 LLVMValueRef src1)
1146 {
1147 LLVMValueRef result;
1148 src0 = ac_to_float(ctx, src0);
1149 src1 = ac_to_float(ctx, src1);
1150 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1151 return LLVMBuildSelect(ctx->builder, result,
1152 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1153 LLVMConstInt(ctx->i32, 0, false), "");
1154 }
1155
1156 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1157 const char *intrin,
1158 LLVMTypeRef result_type,
1159 LLVMValueRef src0)
1160 {
1161 char name[64];
1162 LLVMValueRef params[] = {
1163 ac_to_float(ctx, src0),
1164 };
1165
1166 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1167 get_elem_bits(ctx, result_type));
1168 assert(length < sizeof(name));
1169 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1170 }
1171
1172 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1173 const char *intrin,
1174 LLVMTypeRef result_type,
1175 LLVMValueRef src0, LLVMValueRef src1)
1176 {
1177 char name[64];
1178 LLVMValueRef params[] = {
1179 ac_to_float(ctx, src0),
1180 ac_to_float(ctx, src1),
1181 };
1182
1183 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1184 get_elem_bits(ctx, result_type));
1185 assert(length < sizeof(name));
1186 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1187 }
1188
1189 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1190 const char *intrin,
1191 LLVMTypeRef result_type,
1192 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1193 {
1194 char name[64];
1195 LLVMValueRef params[] = {
1196 ac_to_float(ctx, src0),
1197 ac_to_float(ctx, src1),
1198 ac_to_float(ctx, src2),
1199 };
1200
1201 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1202 get_elem_bits(ctx, result_type));
1203 assert(length < sizeof(name));
1204 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1205 }
1206
1207 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1208 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1209 {
1210 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1211 ctx->i32_0, "");
1212 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1213 }
1214
1215 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1216 LLVMIntPredicate pred,
1217 LLVMValueRef src0, LLVMValueRef src1)
1218 {
1219 return LLVMBuildSelect(ctx->builder,
1220 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1221 src0,
1222 src1, "");
1223
1224 }
1225 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1226 LLVMValueRef src0)
1227 {
1228 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1229 LLVMBuildNeg(ctx->builder, src0, ""));
1230 }
1231
1232 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1233 LLVMValueRef src0)
1234 {
1235 LLVMValueRef cmp, val;
1236
1237 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1238 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1239 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1240 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1241 return val;
1242 }
1243
1244 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1245 LLVMValueRef src0)
1246 {
1247 LLVMValueRef cmp, val;
1248
1249 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1250 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1251 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1252 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1253 return val;
1254 }
1255
1256 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1257 LLVMValueRef src0)
1258 {
1259 const char *intr = "llvm.floor.f32";
1260 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1261 LLVMValueRef params[] = {
1262 fsrc0,
1263 };
1264 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1265 ctx->f32, params, 1,
1266 AC_FUNC_ATTR_READNONE);
1267 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1268 }
1269
1270 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1271 const char *intrin,
1272 LLVMValueRef src0, LLVMValueRef src1)
1273 {
1274 LLVMTypeRef ret_type;
1275 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1276 LLVMValueRef res;
1277 LLVMValueRef params[] = { src0, src1 };
1278 ret_type = LLVMStructTypeInContext(ctx->context, types,
1279 2, true);
1280
1281 res = ac_build_intrinsic(ctx, intrin, ret_type,
1282 params, 2, AC_FUNC_ATTR_READNONE);
1283
1284 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1285 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1286 return res;
1287 }
1288
1289 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1290 LLVMValueRef src0)
1291 {
1292 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1293 }
1294
1295 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1296 LLVMValueRef src0)
1297 {
1298 src0 = ac_to_float(ctx, src0);
1299 return LLVMBuildSExt(ctx->builder,
1300 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1301 ctx->i32, "");
1302 }
1303
1304 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1305 LLVMValueRef src0)
1306 {
1307 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1308 }
1309
1310 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1311 LLVMValueRef src0)
1312 {
1313 return LLVMBuildSExt(ctx->builder,
1314 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1315 ctx->i32, "");
1316 }
1317
1318 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1319 LLVMValueRef src0)
1320 {
1321 LLVMValueRef result;
1322 LLVMValueRef cond = NULL;
1323
1324 src0 = ac_to_float(&ctx->ac, src0);
1325 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1326
1327 if (ctx->options->chip_class >= VI) {
1328 LLVMValueRef args[2];
1329 /* Check if the result is a denormal - and flush to 0 if so. */
1330 args[0] = result;
1331 args[1] = LLVMConstInt(ctx->ac.i32, N_SUBNORMAL | P_SUBNORMAL, false);
1332 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->ac.i1, args, 2, AC_FUNC_ATTR_READNONE);
1333 }
1334
1335 /* need to convert back up to f32 */
1336 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1337
1338 if (ctx->options->chip_class >= VI)
1339 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1340 else {
1341 /* for SI/CIK */
1342 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1343 * so compare the result and flush to 0 if it's smaller.
1344 */
1345 LLVMValueRef temp, cond2;
1346 temp = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1347 ctx->f32, result);
1348 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1349 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->ac.i32, 0x38800000, false), ctx->f32, ""),
1350 temp, "");
1351 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1352 temp, ctx->ac.f32_0, "");
1353 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1354 result = LLVMBuildSelect(ctx->builder, cond, ctx->ac.f32_0, result, "");
1355 }
1356 return result;
1357 }
1358
1359 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1360 LLVMValueRef src0, LLVMValueRef src1)
1361 {
1362 LLVMValueRef dst64, result;
1363 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1364 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1365
1366 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1367 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1368 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1369 return result;
1370 }
1371
1372 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1373 LLVMValueRef src0, LLVMValueRef src1)
1374 {
1375 LLVMValueRef dst64, result;
1376 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1377 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1378
1379 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1380 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1381 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1382 return result;
1383 }
1384
1385 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1386 bool is_signed,
1387 const LLVMValueRef srcs[3])
1388 {
1389 LLVMValueRef result;
1390 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1391
1392 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1393 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1394 return result;
1395 }
1396
1397 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1398 LLVMValueRef src0, LLVMValueRef src1,
1399 LLVMValueRef src2, LLVMValueRef src3)
1400 {
1401 LLVMValueRef bfi_args[3], result;
1402
1403 bfi_args[0] = LLVMBuildShl(ctx->builder,
1404 LLVMBuildSub(ctx->builder,
1405 LLVMBuildShl(ctx->builder,
1406 ctx->i32_1,
1407 src3, ""),
1408 ctx->i32_1, ""),
1409 src2, "");
1410 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1411 bfi_args[2] = src0;
1412
1413 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1414
1415 /* Calculate:
1416 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1417 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1418 */
1419 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1420 LLVMBuildAnd(ctx->builder, bfi_args[0],
1421 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1422
1423 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1424 return result;
1425 }
1426
1427 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1428 LLVMValueRef src0)
1429 {
1430 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1431 int i;
1432 LLVMValueRef comp[2];
1433
1434 src0 = ac_to_float(ctx, src0);
1435 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1436 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1437 for (i = 0; i < 2; i++) {
1438 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1439 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1440 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1441 }
1442
1443 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1444 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1445
1446 return comp[0];
1447 }
1448
1449 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1450 LLVMValueRef src0)
1451 {
1452 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1453 LLVMValueRef temps[2], result, val;
1454 int i;
1455
1456 for (i = 0; i < 2; i++) {
1457 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1458 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1459 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1460 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1461 }
1462
1463 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1464 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1465 ctx->i32_0, "");
1466 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1467 ctx->i32_1, "");
1468 return result;
1469 }
1470
1471 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1472 nir_op op,
1473 LLVMValueRef src0)
1474 {
1475 unsigned mask;
1476 int idx;
1477 LLVMValueRef result;
1478
1479 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1480 mask = AC_TID_MASK_LEFT;
1481 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1482 mask = AC_TID_MASK_TOP;
1483 else
1484 mask = AC_TID_MASK_TOP_LEFT;
1485
1486 /* for DDX we want to next X pixel, DDY next Y pixel. */
1487 if (op == nir_op_fddx_fine ||
1488 op == nir_op_fddx_coarse ||
1489 op == nir_op_fddx)
1490 idx = 1;
1491 else
1492 idx = 2;
1493
1494 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1495 return result;
1496 }
1497
1498 /*
1499 * this takes an I,J coordinate pair,
1500 * and works out the X and Y derivatives.
1501 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1502 */
1503 static LLVMValueRef emit_ddxy_interp(
1504 struct ac_nir_context *ctx,
1505 LLVMValueRef interp_ij)
1506 {
1507 LLVMValueRef result[4], a;
1508 unsigned i;
1509
1510 for (i = 0; i < 2; i++) {
1511 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1512 LLVMConstInt(ctx->ac.i32, i, false), "");
1513 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1514 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1515 }
1516 return ac_build_gather_values(&ctx->ac, result, 4);
1517 }
1518
1519 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1520 {
1521 LLVMValueRef src[4], result = NULL;
1522 unsigned num_components = instr->dest.dest.ssa.num_components;
1523 unsigned src_components;
1524 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1525
1526 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1527 switch (instr->op) {
1528 case nir_op_vec2:
1529 case nir_op_vec3:
1530 case nir_op_vec4:
1531 src_components = 1;
1532 break;
1533 case nir_op_pack_half_2x16:
1534 src_components = 2;
1535 break;
1536 case nir_op_unpack_half_2x16:
1537 src_components = 1;
1538 break;
1539 default:
1540 src_components = num_components;
1541 break;
1542 }
1543 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1544 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1545
1546 switch (instr->op) {
1547 case nir_op_fmov:
1548 case nir_op_imov:
1549 result = src[0];
1550 break;
1551 case nir_op_fneg:
1552 src[0] = ac_to_float(&ctx->ac, src[0]);
1553 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1554 break;
1555 case nir_op_ineg:
1556 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1557 break;
1558 case nir_op_inot:
1559 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1560 break;
1561 case nir_op_iadd:
1562 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1563 break;
1564 case nir_op_fadd:
1565 src[0] = ac_to_float(&ctx->ac, src[0]);
1566 src[1] = ac_to_float(&ctx->ac, src[1]);
1567 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1568 break;
1569 case nir_op_fsub:
1570 src[0] = ac_to_float(&ctx->ac, src[0]);
1571 src[1] = ac_to_float(&ctx->ac, src[1]);
1572 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1573 break;
1574 case nir_op_isub:
1575 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1576 break;
1577 case nir_op_imul:
1578 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1579 break;
1580 case nir_op_imod:
1581 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1582 break;
1583 case nir_op_umod:
1584 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1585 break;
1586 case nir_op_fmod:
1587 src[0] = ac_to_float(&ctx->ac, src[0]);
1588 src[1] = ac_to_float(&ctx->ac, src[1]);
1589 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1590 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1591 ac_to_float_type(&ctx->ac, def_type), result);
1592 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1593 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1594 break;
1595 case nir_op_frem:
1596 src[0] = ac_to_float(&ctx->ac, src[0]);
1597 src[1] = ac_to_float(&ctx->ac, src[1]);
1598 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1599 break;
1600 case nir_op_irem:
1601 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1602 break;
1603 case nir_op_idiv:
1604 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1605 break;
1606 case nir_op_udiv:
1607 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1608 break;
1609 case nir_op_fmul:
1610 src[0] = ac_to_float(&ctx->ac, src[0]);
1611 src[1] = ac_to_float(&ctx->ac, src[1]);
1612 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1613 break;
1614 case nir_op_fdiv:
1615 src[0] = ac_to_float(&ctx->ac, src[0]);
1616 src[1] = ac_to_float(&ctx->ac, src[1]);
1617 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1618 break;
1619 case nir_op_frcp:
1620 src[0] = ac_to_float(&ctx->ac, src[0]);
1621 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1622 break;
1623 case nir_op_iand:
1624 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1625 break;
1626 case nir_op_ior:
1627 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1628 break;
1629 case nir_op_ixor:
1630 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1631 break;
1632 case nir_op_ishl:
1633 result = LLVMBuildShl(ctx->ac.builder, src[0],
1634 LLVMBuildZExt(ctx->ac.builder, src[1],
1635 LLVMTypeOf(src[0]), ""),
1636 "");
1637 break;
1638 case nir_op_ishr:
1639 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1640 LLVMBuildZExt(ctx->ac.builder, src[1],
1641 LLVMTypeOf(src[0]), ""),
1642 "");
1643 break;
1644 case nir_op_ushr:
1645 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1646 LLVMBuildZExt(ctx->ac.builder, src[1],
1647 LLVMTypeOf(src[0]), ""),
1648 "");
1649 break;
1650 case nir_op_ilt:
1651 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1652 break;
1653 case nir_op_ine:
1654 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1655 break;
1656 case nir_op_ieq:
1657 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1658 break;
1659 case nir_op_ige:
1660 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1661 break;
1662 case nir_op_ult:
1663 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1664 break;
1665 case nir_op_uge:
1666 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1667 break;
1668 case nir_op_feq:
1669 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1670 break;
1671 case nir_op_fne:
1672 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1673 break;
1674 case nir_op_flt:
1675 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1676 break;
1677 case nir_op_fge:
1678 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1679 break;
1680 case nir_op_fabs:
1681 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1682 ac_to_float_type(&ctx->ac, def_type), src[0]);
1683 break;
1684 case nir_op_iabs:
1685 result = emit_iabs(&ctx->ac, src[0]);
1686 break;
1687 case nir_op_imax:
1688 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1689 break;
1690 case nir_op_imin:
1691 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1692 break;
1693 case nir_op_umax:
1694 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1695 break;
1696 case nir_op_umin:
1697 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1698 break;
1699 case nir_op_isign:
1700 result = emit_isign(&ctx->ac, src[0]);
1701 break;
1702 case nir_op_fsign:
1703 src[0] = ac_to_float(&ctx->ac, src[0]);
1704 result = emit_fsign(&ctx->ac, src[0]);
1705 break;
1706 case nir_op_ffloor:
1707 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1708 ac_to_float_type(&ctx->ac, def_type), src[0]);
1709 break;
1710 case nir_op_ftrunc:
1711 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1712 ac_to_float_type(&ctx->ac, def_type), src[0]);
1713 break;
1714 case nir_op_fceil:
1715 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1716 ac_to_float_type(&ctx->ac, def_type), src[0]);
1717 break;
1718 case nir_op_fround_even:
1719 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1720 ac_to_float_type(&ctx->ac, def_type),src[0]);
1721 break;
1722 case nir_op_ffract:
1723 result = emit_ffract(&ctx->ac, src[0]);
1724 break;
1725 case nir_op_fsin:
1726 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1727 ac_to_float_type(&ctx->ac, def_type), src[0]);
1728 break;
1729 case nir_op_fcos:
1730 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1731 ac_to_float_type(&ctx->ac, def_type), src[0]);
1732 break;
1733 case nir_op_fsqrt:
1734 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1735 ac_to_float_type(&ctx->ac, def_type), src[0]);
1736 break;
1737 case nir_op_fexp2:
1738 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1739 ac_to_float_type(&ctx->ac, def_type), src[0]);
1740 break;
1741 case nir_op_flog2:
1742 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1743 ac_to_float_type(&ctx->ac, def_type), src[0]);
1744 break;
1745 case nir_op_frsq:
1746 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1747 ac_to_float_type(&ctx->ac, def_type), src[0]);
1748 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1749 break;
1750 case nir_op_fpow:
1751 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1752 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1753 break;
1754 case nir_op_fmax:
1755 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1756 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1757 if (instr->dest.dest.ssa.bit_size == 32)
1758 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1759 ac_to_float_type(&ctx->ac, def_type),
1760 result);
1761 break;
1762 case nir_op_fmin:
1763 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1764 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1765 if (instr->dest.dest.ssa.bit_size == 32)
1766 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1767 ac_to_float_type(&ctx->ac, def_type),
1768 result);
1769 break;
1770 case nir_op_ffma:
1771 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1772 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1773 break;
1774 case nir_op_ibitfield_extract:
1775 result = emit_bitfield_extract(&ctx->ac, true, src);
1776 break;
1777 case nir_op_ubitfield_extract:
1778 result = emit_bitfield_extract(&ctx->ac, false, src);
1779 break;
1780 case nir_op_bitfield_insert:
1781 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1782 break;
1783 case nir_op_bitfield_reverse:
1784 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1785 break;
1786 case nir_op_bit_count:
1787 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1788 break;
1789 case nir_op_vec2:
1790 case nir_op_vec3:
1791 case nir_op_vec4:
1792 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1793 src[i] = ac_to_integer(&ctx->ac, src[i]);
1794 result = ac_build_gather_values(&ctx->ac, src, num_components);
1795 break;
1796 case nir_op_f2i32:
1797 case nir_op_f2i64:
1798 src[0] = ac_to_float(&ctx->ac, src[0]);
1799 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1800 break;
1801 case nir_op_f2u32:
1802 case nir_op_f2u64:
1803 src[0] = ac_to_float(&ctx->ac, src[0]);
1804 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1805 break;
1806 case nir_op_i2f32:
1807 case nir_op_i2f64:
1808 src[0] = ac_to_integer(&ctx->ac, src[0]);
1809 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1810 break;
1811 case nir_op_u2f32:
1812 case nir_op_u2f64:
1813 src[0] = ac_to_integer(&ctx->ac, src[0]);
1814 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1815 break;
1816 case nir_op_f2f64:
1817 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1818 break;
1819 case nir_op_f2f32:
1820 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1821 break;
1822 case nir_op_u2u32:
1823 case nir_op_u2u64:
1824 src[0] = ac_to_integer(&ctx->ac, src[0]);
1825 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1826 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1827 else
1828 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1829 break;
1830 case nir_op_i2i32:
1831 case nir_op_i2i64:
1832 src[0] = ac_to_integer(&ctx->ac, src[0]);
1833 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1834 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1835 else
1836 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1837 break;
1838 case nir_op_bcsel:
1839 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1840 break;
1841 case nir_op_find_lsb:
1842 src[0] = ac_to_integer(&ctx->ac, src[0]);
1843 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1844 break;
1845 case nir_op_ufind_msb:
1846 src[0] = ac_to_integer(&ctx->ac, src[0]);
1847 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1848 break;
1849 case nir_op_ifind_msb:
1850 src[0] = ac_to_integer(&ctx->ac, src[0]);
1851 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1852 break;
1853 case nir_op_uadd_carry:
1854 src[0] = ac_to_integer(&ctx->ac, src[0]);
1855 src[1] = ac_to_integer(&ctx->ac, src[1]);
1856 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1857 break;
1858 case nir_op_usub_borrow:
1859 src[0] = ac_to_integer(&ctx->ac, src[0]);
1860 src[1] = ac_to_integer(&ctx->ac, src[1]);
1861 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1862 break;
1863 case nir_op_b2f:
1864 result = emit_b2f(&ctx->ac, src[0]);
1865 break;
1866 case nir_op_f2b:
1867 result = emit_f2b(&ctx->ac, src[0]);
1868 break;
1869 case nir_op_b2i:
1870 result = emit_b2i(&ctx->ac, src[0]);
1871 break;
1872 case nir_op_i2b:
1873 src[0] = ac_to_integer(&ctx->ac, src[0]);
1874 result = emit_i2b(&ctx->ac, src[0]);
1875 break;
1876 case nir_op_fquantize2f16:
1877 result = emit_f2f16(ctx->nctx, src[0]);
1878 break;
1879 case nir_op_umul_high:
1880 src[0] = ac_to_integer(&ctx->ac, src[0]);
1881 src[1] = ac_to_integer(&ctx->ac, src[1]);
1882 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1883 break;
1884 case nir_op_imul_high:
1885 src[0] = ac_to_integer(&ctx->ac, src[0]);
1886 src[1] = ac_to_integer(&ctx->ac, src[1]);
1887 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1888 break;
1889 case nir_op_pack_half_2x16:
1890 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1891 break;
1892 case nir_op_unpack_half_2x16:
1893 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1894 break;
1895 case nir_op_fddx:
1896 case nir_op_fddy:
1897 case nir_op_fddx_fine:
1898 case nir_op_fddy_fine:
1899 case nir_op_fddx_coarse:
1900 case nir_op_fddy_coarse:
1901 result = emit_ddxy(ctx, instr->op, src[0]);
1902 break;
1903
1904 case nir_op_unpack_64_2x32_split_x: {
1905 assert(instr->src[0].src.ssa->num_components == 1);
1906 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1907 ctx->ac.v2i32,
1908 "");
1909 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1910 ctx->ac.i32_0, "");
1911 break;
1912 }
1913
1914 case nir_op_unpack_64_2x32_split_y: {
1915 assert(instr->src[0].src.ssa->num_components == 1);
1916 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1917 ctx->ac.v2i32,
1918 "");
1919 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1920 ctx->ac.i32_1, "");
1921 break;
1922 }
1923
1924 case nir_op_pack_64_2x32_split: {
1925 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
1926 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1927 src[0], ctx->ac.i32_0, "");
1928 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1929 src[1], ctx->ac.i32_1, "");
1930 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1931 break;
1932 }
1933
1934 default:
1935 fprintf(stderr, "Unknown NIR alu instr: ");
1936 nir_print_instr(&instr->instr, stderr);
1937 fprintf(stderr, "\n");
1938 abort();
1939 }
1940
1941 if (result) {
1942 assert(instr->dest.dest.is_ssa);
1943 result = ac_to_integer(&ctx->ac, result);
1944 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1945 result);
1946 }
1947 }
1948
1949 static void visit_load_const(struct ac_nir_context *ctx,
1950 const nir_load_const_instr *instr)
1951 {
1952 LLVMValueRef values[4], value = NULL;
1953 LLVMTypeRef element_type =
1954 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1955
1956 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1957 switch (instr->def.bit_size) {
1958 case 32:
1959 values[i] = LLVMConstInt(element_type,
1960 instr->value.u32[i], false);
1961 break;
1962 case 64:
1963 values[i] = LLVMConstInt(element_type,
1964 instr->value.u64[i], false);
1965 break;
1966 default:
1967 fprintf(stderr,
1968 "unsupported nir load_const bit_size: %d\n",
1969 instr->def.bit_size);
1970 abort();
1971 }
1972 }
1973 if (instr->def.num_components > 1) {
1974 value = LLVMConstVector(values, instr->def.num_components);
1975 } else
1976 value = values[0];
1977
1978 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1979 }
1980
1981 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1982 LLVMTypeRef type)
1983 {
1984 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1985 return LLVMBuildBitCast(ctx->builder, ptr,
1986 LLVMPointerType(type, addr_space), "");
1987 }
1988
1989 static LLVMValueRef
1990 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1991 {
1992 LLVMValueRef size =
1993 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1994 LLVMConstInt(ctx->ac.i32, 2, false), "");
1995
1996 /* VI only */
1997 if (ctx->ac.chip_class == VI && in_elements) {
1998 /* On VI, the descriptor contains the size in bytes,
1999 * but TXQ must return the size in elements.
2000 * The stride is always non-zero for resources using TXQ.
2001 */
2002 LLVMValueRef stride =
2003 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2004 LLVMConstInt(ctx->ac.i32, 1, false), "");
2005 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2006 LLVMConstInt(ctx->ac.i32, 16, false), "");
2007 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2008 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2009
2010 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2011 }
2012 return size;
2013 }
2014
2015 /**
2016 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2017 * intrinsic names).
2018 */
2019 static void build_int_type_name(
2020 LLVMTypeRef type,
2021 char *buf, unsigned bufsize)
2022 {
2023 assert(bufsize >= 6);
2024
2025 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2026 snprintf(buf, bufsize, "v%ui32",
2027 LLVMGetVectorSize(type));
2028 else
2029 strcpy(buf, "i32");
2030 }
2031
2032 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2033 struct ac_image_args *args,
2034 const nir_tex_instr *instr)
2035 {
2036 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2037 LLVMValueRef coord = args->addr;
2038 LLVMValueRef half_texel[2];
2039 LLVMValueRef compare_cube_wa = NULL;
2040 LLVMValueRef result;
2041 int c;
2042 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2043
2044 //TODO Rect
2045 {
2046 struct ac_image_args txq_args = { 0 };
2047
2048 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2049 txq_args.opcode = ac_image_get_resinfo;
2050 txq_args.dmask = 0xf;
2051 txq_args.addr = ctx->i32_0;
2052 txq_args.resource = args->resource;
2053 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2054
2055 for (c = 0; c < 2; c++) {
2056 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2057 LLVMConstInt(ctx->i32, c, false), "");
2058 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2059 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2060 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2061 LLVMConstReal(ctx->f32, -0.5), "");
2062 }
2063 }
2064
2065 LLVMValueRef orig_coords = args->addr;
2066
2067 for (c = 0; c < 2; c++) {
2068 LLVMValueRef tmp;
2069 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2070 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2071 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2072 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2073 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2074 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2075 }
2076
2077
2078 /*
2079 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2080 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2081 * workaround by sampling using a scaled type and converting.
2082 * This is taken from amdgpu-pro shaders.
2083 */
2084 /* NOTE this produces some ugly code compared to amdgpu-pro,
2085 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2086 * and then reads them back. -pro generates two selects,
2087 * one s_cmp for the descriptor rewriting
2088 * one v_cmp for the coordinate and result changes.
2089 */
2090 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2091 LLVMValueRef tmp, tmp2;
2092
2093 /* workaround 8/8/8/8 uint/sint cube gather bug */
2094 /* first detect it then change to a scaled read and f2i */
2095 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2096 tmp2 = tmp;
2097
2098 /* extract the DATA_FORMAT */
2099 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2100 LLVMConstInt(ctx->i32, 6, false), false);
2101
2102 /* is the DATA_FORMAT == 8_8_8_8 */
2103 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2104
2105 if (stype == GLSL_TYPE_UINT)
2106 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2107 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2108 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2109 else
2110 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2111 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2112 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2113
2114 /* replace the NUM FORMAT in the descriptor */
2115 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2116 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2117
2118 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2119
2120 /* don't modify the coordinates for this case */
2121 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2122 }
2123 args->addr = coord;
2124 result = ac_build_image_opcode(ctx, args);
2125
2126 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2127 LLVMValueRef tmp, tmp2;
2128
2129 /* if the cube workaround is in place, f2i the result. */
2130 for (c = 0; c < 4; c++) {
2131 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2132 if (stype == GLSL_TYPE_UINT)
2133 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2134 else
2135 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2136 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2137 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2138 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2139 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2140 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2141 }
2142 }
2143 return result;
2144 }
2145
2146 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2147 const nir_tex_instr *instr,
2148 bool lod_is_zero,
2149 struct ac_image_args *args)
2150 {
2151 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2152 return ac_build_buffer_load_format(&ctx->ac,
2153 args->resource,
2154 args->addr,
2155 LLVMConstInt(ctx->ac.i32, 0, false),
2156 true);
2157 }
2158
2159 args->opcode = ac_image_sample;
2160 args->compare = instr->is_shadow;
2161
2162 switch (instr->op) {
2163 case nir_texop_txf:
2164 case nir_texop_txf_ms:
2165 case nir_texop_samples_identical:
2166 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2167 args->compare = false;
2168 args->offset = false;
2169 break;
2170 case nir_texop_txb:
2171 args->bias = true;
2172 break;
2173 case nir_texop_txl:
2174 if (lod_is_zero)
2175 args->level_zero = true;
2176 else
2177 args->lod = true;
2178 break;
2179 case nir_texop_txs:
2180 case nir_texop_query_levels:
2181 args->opcode = ac_image_get_resinfo;
2182 break;
2183 case nir_texop_tex:
2184 if (ctx->stage != MESA_SHADER_FRAGMENT)
2185 args->level_zero = true;
2186 break;
2187 case nir_texop_txd:
2188 args->deriv = true;
2189 break;
2190 case nir_texop_tg4:
2191 args->opcode = ac_image_gather4;
2192 args->level_zero = true;
2193 break;
2194 case nir_texop_lod:
2195 args->opcode = ac_image_get_lod;
2196 args->compare = false;
2197 args->offset = false;
2198 break;
2199 default:
2200 break;
2201 }
2202
2203 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2204 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2205 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2206 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2207 }
2208 }
2209 return ac_build_image_opcode(&ctx->ac, args);
2210 }
2211
2212 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2213 nir_intrinsic_instr *instr)
2214 {
2215 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2216 unsigned desc_set = nir_intrinsic_desc_set(instr);
2217 unsigned binding = nir_intrinsic_binding(instr);
2218 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2219 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2220 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2221 unsigned base_offset = layout->binding[binding].offset;
2222 LLVMValueRef offset, stride;
2223
2224 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2225 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2226 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2227 layout->binding[binding].dynamic_offset_offset;
2228 desc_ptr = ctx->push_constants;
2229 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2230 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2231 } else
2232 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2233
2234 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2235 index = LLVMBuildMul(ctx->builder, index, stride, "");
2236 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2237
2238 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2239 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2240 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2241
2242 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2243 }
2244
2245 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2246 nir_intrinsic_instr *instr)
2247 {
2248 LLVMValueRef ptr, addr;
2249
2250 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2251 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2252
2253 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2254 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2255
2256 return LLVMBuildLoad(ctx->builder, ptr, "");
2257 }
2258
2259 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2260 const nir_intrinsic_instr *instr)
2261 {
2262 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2263
2264 return get_buffer_size(ctx, desc, false);
2265 }
2266 static void visit_store_ssbo(struct ac_nir_context *ctx,
2267 nir_intrinsic_instr *instr)
2268 {
2269 const char *store_name;
2270 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2271 LLVMTypeRef data_type = ctx->ac.f32;
2272 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2273 int components_32bit = elem_size_mult * instr->num_components;
2274 unsigned writemask = nir_intrinsic_write_mask(instr);
2275 LLVMValueRef base_data, base_offset;
2276 LLVMValueRef params[6];
2277
2278 params[1] = ctx->abi->load_ssbo(ctx->abi,
2279 get_src(ctx, instr->src[1]), true);
2280 params[2] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2281 params[4] = ctx->ac.i1false; /* glc */
2282 params[5] = ctx->ac.i1false; /* slc */
2283
2284 if (components_32bit > 1)
2285 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2286
2287 base_data = ac_to_float(&ctx->ac, src_data);
2288 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2289 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2290 data_type, "");
2291 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2292 while (writemask) {
2293 int start, count;
2294 LLVMValueRef data;
2295 LLVMValueRef offset;
2296 LLVMValueRef tmp;
2297 u_bit_scan_consecutive_range(&writemask, &start, &count);
2298
2299 /* Due to an LLVM limitation, split 3-element writes
2300 * into a 2-element and a 1-element write. */
2301 if (count == 3) {
2302 writemask |= 1 << (start + 2);
2303 count = 2;
2304 }
2305
2306 start *= elem_size_mult;
2307 count *= elem_size_mult;
2308
2309 if (count > 4) {
2310 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2311 count = 4;
2312 }
2313
2314 if (count == 4) {
2315 store_name = "llvm.amdgcn.buffer.store.v4f32";
2316 data = base_data;
2317 } else if (count == 2) {
2318 LLVMTypeRef v2f32 = LLVMVectorType(ctx->ac.f32, 2);
2319
2320 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2321 base_data, LLVMConstInt(ctx->ac.i32, start, false), "");
2322 data = LLVMBuildInsertElement(ctx->ac.builder, LLVMGetUndef(v2f32), tmp,
2323 ctx->ac.i32_0, "");
2324
2325 tmp = LLVMBuildExtractElement(ctx->ac.builder,
2326 base_data, LLVMConstInt(ctx->ac.i32, start + 1, false), "");
2327 data = LLVMBuildInsertElement(ctx->ac.builder, data, tmp,
2328 ctx->ac.i32_1, "");
2329 store_name = "llvm.amdgcn.buffer.store.v2f32";
2330
2331 } else {
2332 assert(count == 1);
2333 if (get_llvm_num_components(base_data) > 1)
2334 data = LLVMBuildExtractElement(ctx->ac.builder, base_data,
2335 LLVMConstInt(ctx->ac.i32, start, false), "");
2336 else
2337 data = base_data;
2338 store_name = "llvm.amdgcn.buffer.store.f32";
2339 }
2340
2341 offset = base_offset;
2342 if (start != 0) {
2343 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2344 }
2345 params[0] = data;
2346 params[3] = offset;
2347 ac_build_intrinsic(&ctx->ac, store_name,
2348 ctx->ac.voidt, params, 6, 0);
2349 }
2350 }
2351
2352 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2353 const nir_intrinsic_instr *instr)
2354 {
2355 const char *name;
2356 LLVMValueRef params[6];
2357 int arg_count = 0;
2358
2359 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2360 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2361 }
2362 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2363 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2364 get_src(ctx, instr->src[0]),
2365 true);
2366 params[arg_count++] = LLVMConstInt(ctx->ac.i32, 0, false); /* vindex */
2367 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2368 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2369
2370 switch (instr->intrinsic) {
2371 case nir_intrinsic_ssbo_atomic_add:
2372 name = "llvm.amdgcn.buffer.atomic.add";
2373 break;
2374 case nir_intrinsic_ssbo_atomic_imin:
2375 name = "llvm.amdgcn.buffer.atomic.smin";
2376 break;
2377 case nir_intrinsic_ssbo_atomic_umin:
2378 name = "llvm.amdgcn.buffer.atomic.umin";
2379 break;
2380 case nir_intrinsic_ssbo_atomic_imax:
2381 name = "llvm.amdgcn.buffer.atomic.smax";
2382 break;
2383 case nir_intrinsic_ssbo_atomic_umax:
2384 name = "llvm.amdgcn.buffer.atomic.umax";
2385 break;
2386 case nir_intrinsic_ssbo_atomic_and:
2387 name = "llvm.amdgcn.buffer.atomic.and";
2388 break;
2389 case nir_intrinsic_ssbo_atomic_or:
2390 name = "llvm.amdgcn.buffer.atomic.or";
2391 break;
2392 case nir_intrinsic_ssbo_atomic_xor:
2393 name = "llvm.amdgcn.buffer.atomic.xor";
2394 break;
2395 case nir_intrinsic_ssbo_atomic_exchange:
2396 name = "llvm.amdgcn.buffer.atomic.swap";
2397 break;
2398 case nir_intrinsic_ssbo_atomic_comp_swap:
2399 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2400 break;
2401 default:
2402 abort();
2403 }
2404
2405 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2406 }
2407
2408 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2409 const nir_intrinsic_instr *instr)
2410 {
2411 LLVMValueRef results[2];
2412 int load_components;
2413 int num_components = instr->num_components;
2414 if (instr->dest.ssa.bit_size == 64)
2415 num_components *= 2;
2416
2417 for (int i = 0; i < num_components; i += load_components) {
2418 load_components = MIN2(num_components - i, 4);
2419 const char *load_name;
2420 LLVMTypeRef data_type = ctx->ac.f32;
2421 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2422 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2423
2424 if (load_components == 3)
2425 data_type = LLVMVectorType(ctx->ac.f32, 4);
2426 else if (load_components > 1)
2427 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2428
2429 if (load_components >= 3)
2430 load_name = "llvm.amdgcn.buffer.load.v4f32";
2431 else if (load_components == 2)
2432 load_name = "llvm.amdgcn.buffer.load.v2f32";
2433 else if (load_components == 1)
2434 load_name = "llvm.amdgcn.buffer.load.f32";
2435 else
2436 unreachable("unhandled number of components");
2437
2438 LLVMValueRef params[] = {
2439 ctx->abi->load_ssbo(ctx->abi,
2440 get_src(ctx, instr->src[0]),
2441 false),
2442 LLVMConstInt(ctx->ac.i32, 0, false),
2443 offset,
2444 ctx->ac.i1false,
2445 ctx->ac.i1false,
2446 };
2447
2448 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2449
2450 }
2451
2452 assume(results[0]);
2453 LLVMValueRef ret = results[0];
2454 if (num_components > 4 || num_components == 3) {
2455 LLVMValueRef masks[] = {
2456 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2457 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2458 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2459 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2460 };
2461
2462 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2463 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2464 results[num_components > 4 ? 1 : 0], swizzle, "");
2465 }
2466
2467 return LLVMBuildBitCast(ctx->ac.builder, ret,
2468 get_def_type(ctx, &instr->dest.ssa), "");
2469 }
2470
2471 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2472 const nir_intrinsic_instr *instr)
2473 {
2474 LLVMValueRef results[8], ret;
2475 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2476 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2477 int num_components = instr->num_components;
2478
2479 if (ctx->abi->load_ubo)
2480 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2481
2482 if (instr->dest.ssa.bit_size == 64)
2483 num_components *= 2;
2484
2485 for (unsigned i = 0; i < num_components; ++i) {
2486 LLVMValueRef params[] = {
2487 rsrc,
2488 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2489 offset, "")
2490 };
2491 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2492 params, 2,
2493 AC_FUNC_ATTR_READNONE |
2494 AC_FUNC_ATTR_LEGACY);
2495 }
2496
2497
2498 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2499 return LLVMBuildBitCast(ctx->ac.builder, ret,
2500 get_def_type(ctx, &instr->dest.ssa), "");
2501 }
2502
2503 static void
2504 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2505 bool vs_in, unsigned *vertex_index_out,
2506 LLVMValueRef *vertex_index_ref,
2507 unsigned *const_out, LLVMValueRef *indir_out)
2508 {
2509 unsigned const_offset = 0;
2510 nir_deref *tail = &deref->deref;
2511 LLVMValueRef offset = NULL;
2512
2513 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2514 tail = tail->child;
2515 nir_deref_array *deref_array = nir_deref_as_array(tail);
2516 if (vertex_index_out)
2517 *vertex_index_out = deref_array->base_offset;
2518
2519 if (vertex_index_ref) {
2520 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2521 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2522 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2523 }
2524 *vertex_index_ref = vtx;
2525 }
2526 }
2527
2528 if (deref->var->data.compact) {
2529 assert(tail->child->deref_type == nir_deref_type_array);
2530 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2531 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2532 /* We always lower indirect dereferences for "compact" array vars. */
2533 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2534
2535 const_offset = deref_array->base_offset;
2536 goto out;
2537 }
2538
2539 while (tail->child != NULL) {
2540 const struct glsl_type *parent_type = tail->type;
2541 tail = tail->child;
2542
2543 if (tail->deref_type == nir_deref_type_array) {
2544 nir_deref_array *deref_array = nir_deref_as_array(tail);
2545 LLVMValueRef index, stride, local_offset;
2546 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2547
2548 const_offset += size * deref_array->base_offset;
2549 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2550 continue;
2551
2552 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2553 index = get_src(ctx, deref_array->indirect);
2554 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2555 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2556
2557 if (offset)
2558 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2559 else
2560 offset = local_offset;
2561 } else if (tail->deref_type == nir_deref_type_struct) {
2562 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2563
2564 for (unsigned i = 0; i < deref_struct->index; i++) {
2565 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2566 const_offset += glsl_count_attribute_slots(ft, vs_in);
2567 }
2568 } else
2569 unreachable("unsupported deref type");
2570
2571 }
2572 out:
2573 if (const_offset && offset)
2574 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2575 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2576 "");
2577
2578 *const_out = const_offset;
2579 *indir_out = offset;
2580 }
2581
2582
2583 /* The offchip buffer layout for TCS->TES is
2584 *
2585 * - attribute 0 of patch 0 vertex 0
2586 * - attribute 0 of patch 0 vertex 1
2587 * - attribute 0 of patch 0 vertex 2
2588 * ...
2589 * - attribute 0 of patch 1 vertex 0
2590 * - attribute 0 of patch 1 vertex 1
2591 * ...
2592 * - attribute 1 of patch 0 vertex 0
2593 * - attribute 1 of patch 0 vertex 1
2594 * ...
2595 * - per patch attribute 0 of patch 0
2596 * - per patch attribute 0 of patch 1
2597 * ...
2598 *
2599 * Note that every attribute has 4 components.
2600 */
2601 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2602 LLVMValueRef vertex_index,
2603 LLVMValueRef param_index)
2604 {
2605 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2606 LLVMValueRef param_stride, constant16;
2607 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2608
2609 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2610 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2611 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2612 num_patches, "");
2613
2614 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2615 if (vertex_index) {
2616 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2617 vertices_per_patch, "");
2618
2619 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2620 vertex_index, "");
2621
2622 param_stride = total_vertices;
2623 } else {
2624 base_addr = rel_patch_id;
2625 param_stride = num_patches;
2626 }
2627
2628 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2629 LLVMBuildMul(ctx->builder, param_index,
2630 param_stride, ""), "");
2631
2632 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2633
2634 if (!vertex_index) {
2635 LLVMValueRef patch_data_offset =
2636 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2637
2638 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2639 patch_data_offset, "");
2640 }
2641 return base_addr;
2642 }
2643
2644 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2645 unsigned param,
2646 unsigned const_index,
2647 bool is_compact,
2648 LLVMValueRef vertex_index,
2649 LLVMValueRef indir_index)
2650 {
2651 LLVMValueRef param_index;
2652
2653 if (indir_index)
2654 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->ac.i32, param, false),
2655 indir_index, "");
2656 else {
2657 if (const_index && !is_compact)
2658 param += const_index;
2659 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2660 }
2661 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2662 }
2663
2664 static void
2665 mark_tess_output(struct nir_to_llvm_context *ctx,
2666 bool is_patch, uint32_t param)
2667
2668 {
2669 if (is_patch) {
2670 ctx->tess_patch_outputs_written |= (1ull << param);
2671 } else
2672 ctx->tess_outputs_written |= (1ull << param);
2673 }
2674
2675 static LLVMValueRef
2676 get_dw_address(struct nir_to_llvm_context *ctx,
2677 LLVMValueRef dw_addr,
2678 unsigned param,
2679 unsigned const_index,
2680 bool compact_const_index,
2681 LLVMValueRef vertex_index,
2682 LLVMValueRef stride,
2683 LLVMValueRef indir_index)
2684
2685 {
2686
2687 if (vertex_index) {
2688 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2689 LLVMBuildMul(ctx->builder,
2690 vertex_index,
2691 stride, ""), "");
2692 }
2693
2694 if (indir_index)
2695 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2696 LLVMBuildMul(ctx->builder, indir_index,
2697 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2698 else if (const_index && !compact_const_index)
2699 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2700 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2701
2702 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2703 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2704
2705 if (const_index && compact_const_index)
2706 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2707 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2708 return dw_addr;
2709 }
2710
2711 static LLVMValueRef
2712 build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef *values,
2713 unsigned value_count, unsigned component)
2714 {
2715 LLVMValueRef vec = NULL;
2716
2717 if (value_count == 1) {
2718 return values[component];
2719 } else if (!value_count)
2720 unreachable("value_count is 0");
2721
2722 for (unsigned i = component; i < value_count + component; i++) {
2723 LLVMValueRef value = values[i];
2724
2725 if (!i)
2726 vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value), value_count));
2727 LLVMValueRef index = LLVMConstInt(ctx->i32, i - component, false);
2728 vec = LLVMBuildInsertElement(ctx->builder, vec, value, index, "");
2729 }
2730 return vec;
2731 }
2732
2733 static LLVMValueRef
2734 load_tcs_input(struct nir_to_llvm_context *ctx,
2735 nir_intrinsic_instr *instr)
2736 {
2737 LLVMValueRef dw_addr, stride;
2738 unsigned const_index;
2739 LLVMValueRef vertex_index;
2740 LLVMValueRef indir_index;
2741 unsigned param;
2742 LLVMValueRef value[4], result;
2743 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2744 const bool is_compact = instr->variables[0]->var->data.compact;
2745 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2746 get_deref_offset(ctx->nir, instr->variables[0],
2747 false, NULL, per_vertex ? &vertex_index : NULL,
2748 &const_index, &indir_index);
2749
2750 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2751 dw_addr = get_tcs_in_current_patch_offset(ctx);
2752 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2753 indir_index);
2754
2755 unsigned comp = instr->variables[0]->var->data.location_frac;
2756 for (unsigned i = 0; i < instr->num_components + comp; i++) {
2757 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2758 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2759 ctx->ac.i32_1, "");
2760 }
2761 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2762 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2763 return result;
2764 }
2765
2766 static LLVMValueRef
2767 load_tcs_output(struct nir_to_llvm_context *ctx,
2768 nir_intrinsic_instr *instr)
2769 {
2770 LLVMValueRef dw_addr;
2771 LLVMValueRef stride = NULL;
2772 LLVMValueRef value[4], result;
2773 LLVMValueRef vertex_index = NULL;
2774 LLVMValueRef indir_index = NULL;
2775 unsigned const_index = 0;
2776 unsigned param;
2777 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2778 const bool is_compact = instr->variables[0]->var->data.compact;
2779 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2780 get_deref_offset(ctx->nir, instr->variables[0],
2781 false, NULL, per_vertex ? &vertex_index : NULL,
2782 &const_index, &indir_index);
2783
2784 if (!instr->variables[0]->var->data.patch) {
2785 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2786 dw_addr = get_tcs_out_current_patch_offset(ctx);
2787 } else {
2788 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2789 }
2790
2791 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2792 indir_index);
2793
2794 unsigned comp = instr->variables[0]->var->data.location_frac;
2795 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2796 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2797 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2798 ctx->ac.i32_1, "");
2799 }
2800 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2801 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2802 return result;
2803 }
2804
2805 static void
2806 store_tcs_output(struct nir_to_llvm_context *ctx,
2807 nir_intrinsic_instr *instr,
2808 LLVMValueRef src,
2809 unsigned writemask)
2810 {
2811 LLVMValueRef dw_addr;
2812 LLVMValueRef stride = NULL;
2813 LLVMValueRef buf_addr = NULL;
2814 LLVMValueRef vertex_index = NULL;
2815 LLVMValueRef indir_index = NULL;
2816 unsigned const_index = 0;
2817 unsigned param;
2818 const unsigned comp = instr->variables[0]->var->data.location_frac;
2819 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2820 const bool is_compact = instr->variables[0]->var->data.compact;
2821
2822 get_deref_offset(ctx->nir, instr->variables[0],
2823 false, NULL, per_vertex ? &vertex_index : NULL,
2824 &const_index, &indir_index);
2825
2826 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2827 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2828 is_compact && const_index > 3) {
2829 const_index -= 3;
2830 param++;
2831 }
2832
2833 if (!instr->variables[0]->var->data.patch) {
2834 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2835 dw_addr = get_tcs_out_current_patch_offset(ctx);
2836 } else {
2837 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2838 }
2839
2840 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2841
2842 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2843 indir_index);
2844 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2845 vertex_index, indir_index);
2846
2847 bool is_tess_factor = false;
2848 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2849 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2850 is_tess_factor = true;
2851
2852 unsigned base = is_compact ? const_index : 0;
2853 for (unsigned chan = 0; chan < 8; chan++) {
2854 if (!(writemask & (1 << chan)))
2855 continue;
2856 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan - comp);
2857
2858 ac_lds_store(&ctx->ac, dw_addr, value);
2859
2860 if (!is_tess_factor && writemask != 0xF)
2861 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2862 buf_addr, ctx->oc_lds,
2863 4 * (base + chan), 1, 0, true, false);
2864
2865 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2866 ctx->ac.i32_1, "");
2867 }
2868
2869 if (writemask == 0xF) {
2870 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2871 buf_addr, ctx->oc_lds,
2872 (base * 4), 1, 0, true, false);
2873 }
2874 }
2875
2876 static LLVMValueRef
2877 load_tes_input(struct nir_to_llvm_context *ctx,
2878 const nir_intrinsic_instr *instr)
2879 {
2880 LLVMValueRef buf_addr;
2881 LLVMValueRef result;
2882 LLVMValueRef vertex_index = NULL;
2883 LLVMValueRef indir_index = NULL;
2884 unsigned const_index = 0;
2885 unsigned param;
2886 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2887 const bool is_compact = instr->variables[0]->var->data.compact;
2888
2889 get_deref_offset(ctx->nir, instr->variables[0],
2890 false, NULL, per_vertex ? &vertex_index : NULL,
2891 &const_index, &indir_index);
2892 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2893 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2894 is_compact && const_index > 3) {
2895 const_index -= 3;
2896 param++;
2897 }
2898
2899 unsigned comp = instr->variables[0]->var->data.location_frac;
2900 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2901 is_compact, vertex_index, indir_index);
2902
2903 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
2904 buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
2905
2906 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2907 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2908 result = trim_vector(&ctx->ac, result, instr->num_components);
2909 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2910 return result;
2911 }
2912
2913 static LLVMValueRef
2914 load_gs_input(struct nir_to_llvm_context *ctx,
2915 nir_intrinsic_instr *instr)
2916 {
2917 LLVMValueRef indir_index, vtx_offset;
2918 unsigned const_index;
2919 LLVMValueRef args[9];
2920 unsigned param, vtx_offset_param;
2921 LLVMValueRef value[4], result;
2922 unsigned vertex_index;
2923 get_deref_offset(ctx->nir, instr->variables[0],
2924 false, &vertex_index, NULL,
2925 &const_index, &indir_index);
2926 vtx_offset_param = vertex_index;
2927 assert(vtx_offset_param < 6);
2928 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2929 LLVMConstInt(ctx->ac.i32, 4, false), "");
2930
2931 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2932
2933 unsigned comp = instr->variables[0]->var->data.location_frac;
2934 for (unsigned i = comp; i < instr->num_components + comp; i++) {
2935 if (ctx->ac.chip_class >= GFX9) {
2936 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
2937 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2938 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
2939 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2940 } else {
2941 args[0] = ctx->esgs_ring;
2942 args[1] = vtx_offset;
2943 args[2] = LLVMConstInt(ctx->ac.i32, (param * 4 + i + const_index) * 256, false);
2944 args[3] = ctx->ac.i32_0;
2945 args[4] = ctx->ac.i32_1; /* OFFEN */
2946 args[5] = ctx->ac.i32_0; /* IDXEN */
2947 args[6] = ctx->ac.i32_1; /* GLC */
2948 args[7] = ctx->ac.i32_0; /* SLC */
2949 args[8] = ctx->ac.i32_0; /* TFE */
2950
2951 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2952 ctx->ac.i32, args, 9,
2953 AC_FUNC_ATTR_READONLY |
2954 AC_FUNC_ATTR_LEGACY);
2955 }
2956 }
2957 result = build_varying_gather_values(&ctx->ac, value, instr->num_components, comp);
2958
2959 return result;
2960 }
2961
2962 static LLVMValueRef
2963 build_gep_for_deref(struct ac_nir_context *ctx,
2964 nir_deref_var *deref)
2965 {
2966 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2967 assert(entry->data);
2968 LLVMValueRef val = entry->data;
2969 nir_deref *tail = deref->deref.child;
2970 while (tail != NULL) {
2971 LLVMValueRef offset;
2972 switch (tail->deref_type) {
2973 case nir_deref_type_array: {
2974 nir_deref_array *array = nir_deref_as_array(tail);
2975 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2976 if (array->deref_array_type ==
2977 nir_deref_array_type_indirect) {
2978 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2979 get_src(ctx,
2980 array->indirect),
2981 "");
2982 }
2983 break;
2984 }
2985 case nir_deref_type_struct: {
2986 nir_deref_struct *deref_struct =
2987 nir_deref_as_struct(tail);
2988 offset = LLVMConstInt(ctx->ac.i32,
2989 deref_struct->index, 0);
2990 break;
2991 }
2992 default:
2993 unreachable("bad deref type");
2994 }
2995 val = ac_build_gep0(&ctx->ac, val, offset);
2996 tail = tail->child;
2997 }
2998 return val;
2999 }
3000
3001 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3002 nir_intrinsic_instr *instr)
3003 {
3004 LLVMValueRef values[8];
3005 int idx = instr->variables[0]->var->data.driver_location;
3006 int ve = instr->dest.ssa.num_components;
3007 unsigned comp = instr->variables[0]->var->data.location_frac;
3008 LLVMValueRef indir_index;
3009 LLVMValueRef ret;
3010 unsigned const_index;
3011 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3012 instr->variables[0]->var->data.mode == nir_var_shader_in;
3013 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3014 &const_index, &indir_index);
3015
3016 if (instr->dest.ssa.bit_size == 64)
3017 ve *= 2;
3018
3019 switch (instr->variables[0]->var->data.mode) {
3020 case nir_var_shader_in:
3021 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3022 return load_tcs_input(ctx->nctx, instr);
3023 if (ctx->stage == MESA_SHADER_TESS_EVAL)
3024 return load_tes_input(ctx->nctx, instr);
3025 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3026 return load_gs_input(ctx->nctx, instr);
3027 }
3028
3029 for (unsigned chan = comp; chan < ve + comp; chan++) {
3030 if (indir_index) {
3031 unsigned count = glsl_count_attribute_slots(
3032 instr->variables[0]->var->type,
3033 ctx->stage == MESA_SHADER_VERTEX);
3034 count -= chan / 4;
3035 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3036 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3037 4, false, true);
3038
3039 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3040 tmp_vec,
3041 indir_index, "");
3042 } else
3043 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
3044 }
3045 break;
3046 case nir_var_local:
3047 for (unsigned chan = 0; chan < ve; chan++) {
3048 if (indir_index) {
3049 unsigned count = glsl_count_attribute_slots(
3050 instr->variables[0]->var->type, false);
3051 count -= chan / 4;
3052 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3053 &ctx->ac, ctx->locals + idx + chan, count,
3054 4, true, true);
3055
3056 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3057 tmp_vec,
3058 indir_index, "");
3059 } else {
3060 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3061 }
3062 }
3063 break;
3064 case nir_var_shared: {
3065 LLVMValueRef address = build_gep_for_deref(ctx,
3066 instr->variables[0]);
3067 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3068 return LLVMBuildBitCast(ctx->ac.builder, val,
3069 get_def_type(ctx, &instr->dest.ssa),
3070 "");
3071 }
3072 case nir_var_shader_out:
3073 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3074 return load_tcs_output(ctx->nctx, instr);
3075
3076 for (unsigned chan = comp; chan < ve + comp; chan++) {
3077 if (indir_index) {
3078 unsigned count = glsl_count_attribute_slots(
3079 instr->variables[0]->var->type, false);
3080 count -= chan / 4;
3081 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3082 &ctx->ac, ctx->outputs + idx + chan, count,
3083 4, true, true);
3084
3085 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3086 tmp_vec,
3087 indir_index, "");
3088 } else {
3089 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3090 ctx->outputs[idx + chan + const_index * 4],
3091 "");
3092 }
3093 }
3094 break;
3095 default:
3096 unreachable("unhandle variable mode");
3097 }
3098 ret = build_varying_gather_values(&ctx->ac, values, ve, comp);
3099 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3100 }
3101
3102 static void
3103 visit_store_var(struct ac_nir_context *ctx,
3104 nir_intrinsic_instr *instr)
3105 {
3106 LLVMValueRef temp_ptr, value;
3107 int idx = instr->variables[0]->var->data.driver_location;
3108 unsigned comp = instr->variables[0]->var->data.location_frac;
3109 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3110 int writemask = instr->const_index[0] << comp;
3111 LLVMValueRef indir_index;
3112 unsigned const_index;
3113 get_deref_offset(ctx, instr->variables[0], false,
3114 NULL, NULL, &const_index, &indir_index);
3115
3116 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3117 int old_writemask = writemask;
3118
3119 src = LLVMBuildBitCast(ctx->ac.builder, src,
3120 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3121 "");
3122
3123 writemask = 0;
3124 for (unsigned chan = 0; chan < 4; chan++) {
3125 if (old_writemask & (1 << chan))
3126 writemask |= 3u << (2 * chan);
3127 }
3128 }
3129
3130 switch (instr->variables[0]->var->data.mode) {
3131 case nir_var_shader_out:
3132
3133 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3134 store_tcs_output(ctx->nctx, instr, src, writemask);
3135 return;
3136 }
3137
3138 for (unsigned chan = 0; chan < 8; chan++) {
3139 int stride = 4;
3140 if (!(writemask & (1 << chan)))
3141 continue;
3142
3143 value = llvm_extract_elem(&ctx->ac, src, chan - comp);
3144
3145 if (instr->variables[0]->var->data.compact)
3146 stride = 1;
3147 if (indir_index) {
3148 unsigned count = glsl_count_attribute_slots(
3149 instr->variables[0]->var->type, false);
3150 count -= chan / 4;
3151 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3152 &ctx->ac, ctx->outputs + idx + chan, count,
3153 stride, true, true);
3154
3155 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3156 value, indir_index, "");
3157 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3158 count, stride, tmp_vec);
3159
3160 } else {
3161 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3162
3163 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3164 }
3165 }
3166 break;
3167 case nir_var_local:
3168 for (unsigned chan = 0; chan < 8; chan++) {
3169 if (!(writemask & (1 << chan)))
3170 continue;
3171
3172 value = llvm_extract_elem(&ctx->ac, src, chan);
3173 if (indir_index) {
3174 unsigned count = glsl_count_attribute_slots(
3175 instr->variables[0]->var->type, false);
3176 count -= chan / 4;
3177 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3178 &ctx->ac, ctx->locals + idx + chan, count,
3179 4, true, true);
3180
3181 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3182 value, indir_index, "");
3183 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3184 count, 4, tmp_vec);
3185 } else {
3186 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3187
3188 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3189 }
3190 }
3191 break;
3192 case nir_var_shared: {
3193 int writemask = instr->const_index[0];
3194 LLVMValueRef address = build_gep_for_deref(ctx,
3195 instr->variables[0]);
3196 LLVMValueRef val = get_src(ctx, instr->src[0]);
3197 unsigned components =
3198 glsl_get_vector_elements(
3199 nir_deref_tail(&instr->variables[0]->deref)->type);
3200 if (writemask == (1 << components) - 1) {
3201 val = LLVMBuildBitCast(
3202 ctx->ac.builder, val,
3203 LLVMGetElementType(LLVMTypeOf(address)), "");
3204 LLVMBuildStore(ctx->ac.builder, val, address);
3205 } else {
3206 for (unsigned chan = 0; chan < 4; chan++) {
3207 if (!(writemask & (1 << chan)))
3208 continue;
3209 LLVMValueRef ptr =
3210 LLVMBuildStructGEP(ctx->ac.builder,
3211 address, chan, "");
3212 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3213 chan);
3214 src = LLVMBuildBitCast(
3215 ctx->ac.builder, src,
3216 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3217 LLVMBuildStore(ctx->ac.builder, src, ptr);
3218 }
3219 }
3220 break;
3221 }
3222 default:
3223 break;
3224 }
3225 }
3226
3227 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3228 {
3229 switch (dim) {
3230 case GLSL_SAMPLER_DIM_BUF:
3231 return 1;
3232 case GLSL_SAMPLER_DIM_1D:
3233 return array ? 2 : 1;
3234 case GLSL_SAMPLER_DIM_2D:
3235 return array ? 3 : 2;
3236 case GLSL_SAMPLER_DIM_MS:
3237 return array ? 4 : 3;
3238 case GLSL_SAMPLER_DIM_3D:
3239 case GLSL_SAMPLER_DIM_CUBE:
3240 return 3;
3241 case GLSL_SAMPLER_DIM_RECT:
3242 case GLSL_SAMPLER_DIM_SUBPASS:
3243 return 2;
3244 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3245 return 3;
3246 default:
3247 break;
3248 }
3249 return 0;
3250 }
3251
3252
3253
3254 /* Adjust the sample index according to FMASK.
3255 *
3256 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3257 * which is the identity mapping. Each nibble says which physical sample
3258 * should be fetched to get that sample.
3259 *
3260 * For example, 0x11111100 means there are only 2 samples stored and
3261 * the second sample covers 3/4 of the pixel. When reading samples 0
3262 * and 1, return physical sample 0 (determined by the first two 0s
3263 * in FMASK), otherwise return physical sample 1.
3264 *
3265 * The sample index should be adjusted as follows:
3266 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3267 */
3268 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3269 LLVMValueRef coord_x, LLVMValueRef coord_y,
3270 LLVMValueRef coord_z,
3271 LLVMValueRef sample_index,
3272 LLVMValueRef fmask_desc_ptr)
3273 {
3274 LLVMValueRef fmask_load_address[4];
3275 LLVMValueRef res;
3276
3277 fmask_load_address[0] = coord_x;
3278 fmask_load_address[1] = coord_y;
3279 if (coord_z) {
3280 fmask_load_address[2] = coord_z;
3281 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3282 }
3283
3284 struct ac_image_args args = {0};
3285
3286 args.opcode = ac_image_load;
3287 args.da = coord_z ? true : false;
3288 args.resource = fmask_desc_ptr;
3289 args.dmask = 0xf;
3290 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3291
3292 res = ac_build_image_opcode(ctx, &args);
3293
3294 res = ac_to_integer(ctx, res);
3295 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3296 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3297
3298 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3299 res,
3300 ctx->i32_0, "");
3301
3302 LLVMValueRef sample_index4 =
3303 LLVMBuildMul(ctx->builder, sample_index, four, "");
3304 LLVMValueRef shifted_fmask =
3305 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3306 LLVMValueRef final_sample =
3307 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3308
3309 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3310 * resource descriptor is 0 (invalid),
3311 */
3312 LLVMValueRef fmask_desc =
3313 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3314 ctx->v8i32, "");
3315
3316 LLVMValueRef fmask_word1 =
3317 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3318 ctx->i32_1, "");
3319
3320 LLVMValueRef word1_is_nonzero =
3321 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3322 fmask_word1, ctx->i32_0, "");
3323
3324 /* Replace the MSAA sample index. */
3325 sample_index =
3326 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3327 final_sample, sample_index, "");
3328 return sample_index;
3329 }
3330
3331 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3332 const nir_intrinsic_instr *instr)
3333 {
3334 const struct glsl_type *type = instr->variables[0]->var->type;
3335 if(instr->variables[0]->deref.child)
3336 type = instr->variables[0]->deref.child->type;
3337
3338 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3339 LLVMValueRef coords[4];
3340 LLVMValueRef masks[] = {
3341 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3342 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3343 };
3344 LLVMValueRef res;
3345 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3346
3347 int count;
3348 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3349 bool is_array = glsl_sampler_type_is_array(type);
3350 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3351 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3352 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3353 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3354 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3355 count = image_type_to_components_count(dim, is_array);
3356
3357 if (is_ms) {
3358 LLVMValueRef fmask_load_address[3];
3359 int chan;
3360
3361 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3362 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3363 if (is_array)
3364 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3365 else
3366 fmask_load_address[2] = NULL;
3367 if (add_frag_pos) {
3368 for (chan = 0; chan < 2; ++chan)
3369 fmask_load_address[chan] =
3370 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3371 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3372 ctx->ac.i32, ""), "");
3373 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3374 }
3375 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3376 fmask_load_address[0],
3377 fmask_load_address[1],
3378 fmask_load_address[2],
3379 sample_index,
3380 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3381 }
3382 if (count == 1 && !gfx9_1d) {
3383 if (instr->src[0].ssa->num_components)
3384 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3385 else
3386 res = src0;
3387 } else {
3388 int chan;
3389 if (is_ms)
3390 count--;
3391 for (chan = 0; chan < count; ++chan) {
3392 coords[chan] = llvm_extract_elem(&ctx->ac, src0, chan);
3393 }
3394 if (add_frag_pos) {
3395 for (chan = 0; chan < 2; ++chan)
3396 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3397 ctx->ac.i32, ""), "");
3398 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3399 count++;
3400 }
3401
3402 if (gfx9_1d) {
3403 if (is_array) {
3404 coords[2] = coords[1];
3405 coords[1] = ctx->ac.i32_0;
3406 } else
3407 coords[1] = ctx->ac.i32_0;
3408 count++;
3409 }
3410
3411 if (is_ms) {
3412 coords[count] = sample_index;
3413 count++;
3414 }
3415
3416 if (count == 3) {
3417 coords[3] = LLVMGetUndef(ctx->ac.i32);
3418 count = 4;
3419 }
3420 res = ac_build_gather_values(&ctx->ac, coords, count);
3421 }
3422 return res;
3423 }
3424
3425 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3426 const nir_intrinsic_instr *instr)
3427 {
3428 LLVMValueRef params[7];
3429 LLVMValueRef res;
3430 char intrinsic_name[64];
3431 const nir_variable *var = instr->variables[0]->var;
3432 const struct glsl_type *type = var->type;
3433
3434 if(instr->variables[0]->deref.child)
3435 type = instr->variables[0]->deref.child->type;
3436
3437 type = glsl_without_array(type);
3438 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3439 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3440 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3441 ctx->ac.i32_0, ""); /* vindex */
3442 params[2] = ctx->ac.i32_0; /* voffset */
3443 params[3] = ctx->ac.i1false; /* glc */
3444 params[4] = ctx->ac.i1false; /* slc */
3445 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3446 params, 5, 0);
3447
3448 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3449 res = ac_to_integer(&ctx->ac, res);
3450 } else {
3451 bool is_da = glsl_sampler_type_is_array(type) ||
3452 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE ||
3453 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS ||
3454 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_SUBPASS_MS;
3455 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3456 LLVMValueRef glc = ctx->ac.i1false;
3457 LLVMValueRef slc = ctx->ac.i1false;
3458
3459 params[0] = get_image_coords(ctx, instr);
3460 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3461 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3462 if (HAVE_LLVM <= 0x0309) {
3463 params[3] = ctx->ac.i1false; /* r128 */
3464 params[4] = da;
3465 params[5] = glc;
3466 params[6] = slc;
3467 } else {
3468 LLVMValueRef lwe = ctx->ac.i1false;
3469 params[3] = glc;
3470 params[4] = slc;
3471 params[5] = lwe;
3472 params[6] = da;
3473 }
3474
3475 ac_get_image_intr_name("llvm.amdgcn.image.load",
3476 ctx->ac.v4f32, /* vdata */
3477 LLVMTypeOf(params[0]), /* coords */
3478 LLVMTypeOf(params[1]), /* rsrc */
3479 intrinsic_name, sizeof(intrinsic_name));
3480
3481 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3482 params, 7, AC_FUNC_ATTR_READONLY);
3483 }
3484 return ac_to_integer(&ctx->ac, res);
3485 }
3486
3487 static void visit_image_store(struct ac_nir_context *ctx,
3488 nir_intrinsic_instr *instr)
3489 {
3490 LLVMValueRef params[8];
3491 char intrinsic_name[64];
3492 const nir_variable *var = instr->variables[0]->var;
3493 const struct glsl_type *type = glsl_without_array(var->type);
3494 LLVMValueRef glc = ctx->ac.i1false;
3495 bool force_glc = ctx->ac.chip_class == SI;
3496 if (force_glc)
3497 glc = ctx->ac.i1true;
3498
3499 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3500 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3501 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3502 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3503 ctx->ac.i32_0, ""); /* vindex */
3504 params[3] = ctx->ac.i32_0; /* voffset */
3505 params[4] = glc; /* glc */
3506 params[5] = ctx->ac.i1false; /* slc */
3507 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3508 params, 6, 0);
3509 } else {
3510 bool is_da = glsl_sampler_type_is_array(type) ||
3511 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3512 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3513 LLVMValueRef slc = ctx->ac.i1false;
3514
3515 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3516 params[1] = get_image_coords(ctx, instr); /* coords */
3517 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3518 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3519 if (HAVE_LLVM <= 0x0309) {
3520 params[4] = ctx->ac.i1false; /* r128 */
3521 params[5] = da;
3522 params[6] = glc;
3523 params[7] = slc;
3524 } else {
3525 LLVMValueRef lwe = ctx->ac.i1false;
3526 params[4] = glc;
3527 params[5] = slc;
3528 params[6] = lwe;
3529 params[7] = da;
3530 }
3531
3532 ac_get_image_intr_name("llvm.amdgcn.image.store",
3533 LLVMTypeOf(params[0]), /* vdata */
3534 LLVMTypeOf(params[1]), /* coords */
3535 LLVMTypeOf(params[2]), /* rsrc */
3536 intrinsic_name, sizeof(intrinsic_name));
3537
3538 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3539 params, 8, 0);
3540 }
3541
3542 }
3543
3544 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3545 const nir_intrinsic_instr *instr)
3546 {
3547 LLVMValueRef params[7];
3548 int param_count = 0;
3549 const nir_variable *var = instr->variables[0]->var;
3550
3551 const char *atomic_name;
3552 char intrinsic_name[41];
3553 const struct glsl_type *type = glsl_without_array(var->type);
3554 MAYBE_UNUSED int length;
3555
3556 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3557
3558 switch (instr->intrinsic) {
3559 case nir_intrinsic_image_atomic_add:
3560 atomic_name = "add";
3561 break;
3562 case nir_intrinsic_image_atomic_min:
3563 atomic_name = is_unsigned ? "umin" : "smin";
3564 break;
3565 case nir_intrinsic_image_atomic_max:
3566 atomic_name = is_unsigned ? "umax" : "smax";
3567 break;
3568 case nir_intrinsic_image_atomic_and:
3569 atomic_name = "and";
3570 break;
3571 case nir_intrinsic_image_atomic_or:
3572 atomic_name = "or";
3573 break;
3574 case nir_intrinsic_image_atomic_xor:
3575 atomic_name = "xor";
3576 break;
3577 case nir_intrinsic_image_atomic_exchange:
3578 atomic_name = "swap";
3579 break;
3580 case nir_intrinsic_image_atomic_comp_swap:
3581 atomic_name = "cmpswap";
3582 break;
3583 default:
3584 abort();
3585 }
3586
3587 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3588 params[param_count++] = get_src(ctx, instr->src[3]);
3589 params[param_count++] = get_src(ctx, instr->src[2]);
3590
3591 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3592 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3593 NULL, true, true);
3594 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3595 ctx->ac.i32_0, ""); /* vindex */
3596 params[param_count++] = ctx->ac.i32_0; /* voffset */
3597 params[param_count++] = ctx->ac.i1false; /* slc */
3598
3599 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3600 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3601 } else {
3602 char coords_type[8];
3603
3604 bool da = glsl_sampler_type_is_array(type) ||
3605 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3606
3607 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3608 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3609 NULL, true, true);
3610 params[param_count++] = ctx->ac.i1false; /* r128 */
3611 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3612 params[param_count++] = ctx->ac.i1false; /* slc */
3613
3614 build_int_type_name(LLVMTypeOf(coords),
3615 coords_type, sizeof(coords_type));
3616
3617 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3618 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3619 }
3620
3621 assert(length < sizeof(intrinsic_name));
3622 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3623 }
3624
3625 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3626 const nir_intrinsic_instr *instr)
3627 {
3628 LLVMValueRef res;
3629 const nir_variable *var = instr->variables[0]->var;
3630 const struct glsl_type *type = instr->variables[0]->var->type;
3631 bool da = glsl_sampler_type_is_array(var->type) ||
3632 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3633 if(instr->variables[0]->deref.child)
3634 type = instr->variables[0]->deref.child->type;
3635
3636 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3637 return get_buffer_size(ctx,
3638 get_sampler_desc(ctx, instr->variables[0],
3639 AC_DESC_BUFFER, NULL, true, false), true);
3640
3641 struct ac_image_args args = { 0 };
3642
3643 args.da = da;
3644 args.dmask = 0xf;
3645 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3646 args.opcode = ac_image_get_resinfo;
3647 args.addr = ctx->ac.i32_0;
3648
3649 res = ac_build_image_opcode(&ctx->ac, &args);
3650
3651 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3652
3653 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3654 glsl_sampler_type_is_array(type)) {
3655 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3656 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3657 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3658 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3659 }
3660 if (ctx->ac.chip_class >= GFX9 &&
3661 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3662 glsl_sampler_type_is_array(type)) {
3663 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3664 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3665 ctx->ac.i32_1, "");
3666
3667 }
3668 return res;
3669 }
3670
3671 #define NOOP_WAITCNT 0xf7f
3672 #define LGKM_CNT 0x07f
3673 #define VM_CNT 0xf70
3674
3675 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3676 unsigned simm16)
3677 {
3678 LLVMValueRef args[1] = {
3679 LLVMConstInt(ctx->ac.i32, simm16, false),
3680 };
3681 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3682 ctx->ac.voidt, args, 1, 0);
3683 }
3684
3685 static void emit_barrier(struct nir_to_llvm_context *ctx)
3686 {
3687 /* SI only (thanks to a hw bug workaround):
3688 * The real barrier instruction isn’t needed, because an entire patch
3689 * always fits into a single wave.
3690 */
3691 if (ctx->options->chip_class == SI &&
3692 ctx->stage == MESA_SHADER_TESS_CTRL) {
3693 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3694 return;
3695 }
3696 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3697 ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3698 }
3699
3700 static void emit_discard_if(struct ac_nir_context *ctx,
3701 const nir_intrinsic_instr *instr)
3702 {
3703 LLVMValueRef cond;
3704
3705 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3706 get_src(ctx, instr->src[0]),
3707 ctx->ac.i32_0, "");
3708 ac_build_kill_if_false(&ctx->ac, cond);
3709 }
3710
3711 static LLVMValueRef
3712 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3713 {
3714 LLVMValueRef result;
3715 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3716 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3717 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3718
3719 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3720 }
3721
3722 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3723 const nir_intrinsic_instr *instr)
3724 {
3725 LLVMValueRef ptr, result;
3726 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3727 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3728
3729 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3730 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3731 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3732 ptr, src, src1,
3733 LLVMAtomicOrderingSequentiallyConsistent,
3734 LLVMAtomicOrderingSequentiallyConsistent,
3735 false);
3736 } else {
3737 LLVMAtomicRMWBinOp op;
3738 switch (instr->intrinsic) {
3739 case nir_intrinsic_var_atomic_add:
3740 op = LLVMAtomicRMWBinOpAdd;
3741 break;
3742 case nir_intrinsic_var_atomic_umin:
3743 op = LLVMAtomicRMWBinOpUMin;
3744 break;
3745 case nir_intrinsic_var_atomic_umax:
3746 op = LLVMAtomicRMWBinOpUMax;
3747 break;
3748 case nir_intrinsic_var_atomic_imin:
3749 op = LLVMAtomicRMWBinOpMin;
3750 break;
3751 case nir_intrinsic_var_atomic_imax:
3752 op = LLVMAtomicRMWBinOpMax;
3753 break;
3754 case nir_intrinsic_var_atomic_and:
3755 op = LLVMAtomicRMWBinOpAnd;
3756 break;
3757 case nir_intrinsic_var_atomic_or:
3758 op = LLVMAtomicRMWBinOpOr;
3759 break;
3760 case nir_intrinsic_var_atomic_xor:
3761 op = LLVMAtomicRMWBinOpXor;
3762 break;
3763 case nir_intrinsic_var_atomic_exchange:
3764 op = LLVMAtomicRMWBinOpXchg;
3765 break;
3766 default:
3767 return NULL;
3768 }
3769
3770 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, ac_to_integer(&ctx->ac, src),
3771 LLVMAtomicOrderingSequentiallyConsistent,
3772 false);
3773 }
3774 return result;
3775 }
3776
3777 #define INTERP_CENTER 0
3778 #define INTERP_CENTROID 1
3779 #define INTERP_SAMPLE 2
3780
3781 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3782 enum glsl_interp_mode interp, unsigned location)
3783 {
3784 switch (interp) {
3785 case INTERP_MODE_FLAT:
3786 default:
3787 return NULL;
3788 case INTERP_MODE_SMOOTH:
3789 case INTERP_MODE_NONE:
3790 if (location == INTERP_CENTER)
3791 return ctx->persp_center;
3792 else if (location == INTERP_CENTROID)
3793 return ctx->persp_centroid;
3794 else if (location == INTERP_SAMPLE)
3795 return ctx->persp_sample;
3796 break;
3797 case INTERP_MODE_NOPERSPECTIVE:
3798 if (location == INTERP_CENTER)
3799 return ctx->linear_center;
3800 else if (location == INTERP_CENTROID)
3801 return ctx->linear_centroid;
3802 else if (location == INTERP_SAMPLE)
3803 return ctx->linear_sample;
3804 break;
3805 }
3806 return NULL;
3807 }
3808
3809 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3810 LLVMValueRef sample_id)
3811 {
3812 LLVMValueRef result;
3813 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
3814
3815 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3816 const_array(ctx->v2f32, 64), "");
3817
3818 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3819 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
3820
3821 return result;
3822 }
3823
3824 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
3825 {
3826 LLVMValueRef values[2];
3827
3828 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
3829 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
3830 return ac_build_gather_values(&ctx->ac, values, 2);
3831 }
3832
3833 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3834 const nir_intrinsic_instr *instr)
3835 {
3836 LLVMValueRef result[4];
3837 LLVMValueRef interp_param, attr_number;
3838 unsigned location;
3839 unsigned chan;
3840 LLVMValueRef src_c0 = NULL;
3841 LLVMValueRef src_c1 = NULL;
3842 LLVMValueRef src0 = NULL;
3843 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3844 switch (instr->intrinsic) {
3845 case nir_intrinsic_interp_var_at_centroid:
3846 location = INTERP_CENTROID;
3847 break;
3848 case nir_intrinsic_interp_var_at_sample:
3849 case nir_intrinsic_interp_var_at_offset:
3850 location = INTERP_CENTER;
3851 src0 = get_src(ctx->nir, instr->src[0]);
3852 break;
3853 default:
3854 break;
3855 }
3856
3857 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3858 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_0, ""));
3859 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->ac.i32_1, ""));
3860 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3861 LLVMValueRef sample_position;
3862 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3863
3864 /* fetch sample ID */
3865 sample_position = load_sample_position(ctx, src0);
3866
3867 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_0, "");
3868 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3869 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->ac.i32_1, "");
3870 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3871 }
3872 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3873 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
3874
3875 if (location == INTERP_CENTER) {
3876 LLVMValueRef ij_out[2];
3877 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx->nir, interp_param);
3878
3879 /*
3880 * take the I then J parameters, and the DDX/Y for it, and
3881 * calculate the IJ inputs for the interpolator.
3882 * temp1 = ddx * offset/sample.x + I;
3883 * interp_param.I = ddy * offset/sample.y + temp1;
3884 * temp1 = ddx * offset/sample.x + J;
3885 * interp_param.J = ddy * offset/sample.y + temp1;
3886 */
3887 for (unsigned i = 0; i < 2; i++) {
3888 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
3889 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
3890 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3891 ddxy_out, ix_ll, "");
3892 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3893 ddxy_out, iy_ll, "");
3894 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3895 interp_param, ix_ll, "");
3896 LLVMValueRef temp1, temp2;
3897
3898 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3899 ctx->f32, "");
3900
3901 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3902 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3903
3904 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3905 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3906
3907 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3908 temp2, ctx->ac.i32, "");
3909 }
3910 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3911
3912 }
3913
3914 for (chan = 0; chan < 4; chan++) {
3915 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
3916
3917 if (interp_param) {
3918 interp_param = LLVMBuildBitCast(ctx->builder,
3919 interp_param, LLVMVectorType(ctx->f32, 2), "");
3920 LLVMValueRef i = LLVMBuildExtractElement(
3921 ctx->builder, interp_param, ctx->ac.i32_0, "");
3922 LLVMValueRef j = LLVMBuildExtractElement(
3923 ctx->builder, interp_param, ctx->ac.i32_1, "");
3924
3925 result[chan] = ac_build_fs_interp(&ctx->ac,
3926 llvm_chan, attr_number,
3927 ctx->prim_mask, i, j);
3928 } else {
3929 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3930 LLVMConstInt(ctx->ac.i32, 2, false),
3931 llvm_chan, attr_number,
3932 ctx->prim_mask);
3933 }
3934 }
3935 return build_varying_gather_values(&ctx->ac, result, instr->num_components,
3936 instr->variables[0]->var->data.location_frac);
3937 }
3938
3939 static void
3940 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3941 const nir_intrinsic_instr *instr)
3942 {
3943 LLVMValueRef gs_next_vertex;
3944 LLVMValueRef can_emit;
3945 int idx;
3946
3947 assert(instr->const_index[0] == 0);
3948 /* Write vertex attribute values to GSVS ring */
3949 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3950 ctx->gs_next_vertex,
3951 "");
3952
3953 /* If this thread has already emitted the declared maximum number of
3954 * vertices, kill it: excessive vertex emissions are not supposed to
3955 * have any effect, and GS threads have no externally observable
3956 * effects other than emitting vertices.
3957 */
3958 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3959 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
3960 ac_build_kill_if_false(&ctx->ac, can_emit);
3961
3962 /* loop num outputs */
3963 idx = 0;
3964 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3965 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3966 int length = 4;
3967 int slot = idx;
3968 int slot_inc = 1;
3969
3970 if (!(ctx->output_mask & (1ull << i)))
3971 continue;
3972
3973 if (i == VARYING_SLOT_CLIP_DIST0) {
3974 /* pack clip and cull into a single set of slots */
3975 length = ctx->num_output_clips + ctx->num_output_culls;
3976 if (length > 4)
3977 slot_inc = 2;
3978 }
3979 for (unsigned j = 0; j < length; j++) {
3980 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3981 out_ptr[j], "");
3982 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3983 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3984 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
3985
3986 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
3987
3988 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3989 out_val, 1,
3990 voffset, ctx->gs2vs_offset, 0,
3991 1, 1, true, true);
3992 }
3993 idx += slot_inc;
3994 }
3995
3996 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3997 ctx->ac.i32_1, "");
3998 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3999
4000 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4001 }
4002
4003 static void
4004 visit_end_primitive(struct nir_to_llvm_context *ctx,
4005 const nir_intrinsic_instr *instr)
4006 {
4007 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4008 }
4009
4010 static LLVMValueRef
4011 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
4012 const nir_intrinsic_instr *instr)
4013 {
4014 LLVMValueRef coord[4] = {
4015 ctx->tes_u,
4016 ctx->tes_v,
4017 ctx->ac.f32_0,
4018 ctx->ac.f32_0,
4019 };
4020
4021 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4022 coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
4023 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
4024
4025 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
4026 return LLVMBuildBitCast(ctx->builder, result,
4027 get_def_type(ctx->nir, &instr->dest.ssa), "");
4028 }
4029
4030 static void visit_intrinsic(struct ac_nir_context *ctx,
4031 nir_intrinsic_instr *instr)
4032 {
4033 LLVMValueRef result = NULL;
4034
4035 switch (instr->intrinsic) {
4036 case nir_intrinsic_load_work_group_id: {
4037 result = ctx->nctx->workgroup_ids;
4038 break;
4039 }
4040 case nir_intrinsic_load_base_vertex: {
4041 result = ctx->abi->base_vertex;
4042 break;
4043 }
4044 case nir_intrinsic_load_vertex_id_zero_base: {
4045 result = ctx->abi->vertex_id;
4046 break;
4047 }
4048 case nir_intrinsic_load_local_invocation_id: {
4049 result = ctx->nctx->local_invocation_ids;
4050 break;
4051 }
4052 case nir_intrinsic_load_base_instance:
4053 result = ctx->abi->start_instance;
4054 break;
4055 case nir_intrinsic_load_draw_id:
4056 result = ctx->abi->draw_id;
4057 break;
4058 case nir_intrinsic_load_view_index:
4059 result = ctx->nctx->view_index ? ctx->nctx->view_index : ctx->ac.i32_0;
4060 break;
4061 case nir_intrinsic_load_invocation_id:
4062 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4063 result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
4064 else
4065 result = ctx->nctx->gs_invocation_id;
4066 break;
4067 case nir_intrinsic_load_primitive_id:
4068 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4069 ctx->nctx->shader_info->gs.uses_prim_id = true;
4070 result = ctx->nctx->gs_prim_id;
4071 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4072 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4073 result = ctx->nctx->tcs_patch_id;
4074 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4075 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4076 result = ctx->nctx->tes_patch_id;
4077 } else
4078 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4079 break;
4080 case nir_intrinsic_load_sample_id:
4081 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4082 break;
4083 case nir_intrinsic_load_sample_pos:
4084 result = load_sample_pos(ctx);
4085 break;
4086 case nir_intrinsic_load_sample_mask_in:
4087 result = ctx->abi->sample_coverage;
4088 break;
4089 case nir_intrinsic_load_frag_coord: {
4090 LLVMValueRef values[4] = {
4091 ctx->abi->frag_pos[0],
4092 ctx->abi->frag_pos[1],
4093 ctx->abi->frag_pos[2],
4094 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4095 };
4096 result = ac_build_gather_values(&ctx->ac, values, 4);
4097 break;
4098 }
4099 case nir_intrinsic_load_front_face:
4100 result = ctx->abi->front_face;
4101 break;
4102 case nir_intrinsic_load_instance_id:
4103 result = ctx->abi->instance_id;
4104 break;
4105 case nir_intrinsic_load_num_work_groups:
4106 result = ctx->nctx->num_work_groups;
4107 break;
4108 case nir_intrinsic_load_local_invocation_index:
4109 result = visit_load_local_invocation_index(ctx->nctx);
4110 break;
4111 case nir_intrinsic_load_push_constant:
4112 result = visit_load_push_constant(ctx->nctx, instr);
4113 break;
4114 case nir_intrinsic_vulkan_resource_index:
4115 result = visit_vulkan_resource_index(ctx->nctx, instr);
4116 break;
4117 case nir_intrinsic_store_ssbo:
4118 visit_store_ssbo(ctx, instr);
4119 break;
4120 case nir_intrinsic_load_ssbo:
4121 result = visit_load_buffer(ctx, instr);
4122 break;
4123 case nir_intrinsic_ssbo_atomic_add:
4124 case nir_intrinsic_ssbo_atomic_imin:
4125 case nir_intrinsic_ssbo_atomic_umin:
4126 case nir_intrinsic_ssbo_atomic_imax:
4127 case nir_intrinsic_ssbo_atomic_umax:
4128 case nir_intrinsic_ssbo_atomic_and:
4129 case nir_intrinsic_ssbo_atomic_or:
4130 case nir_intrinsic_ssbo_atomic_xor:
4131 case nir_intrinsic_ssbo_atomic_exchange:
4132 case nir_intrinsic_ssbo_atomic_comp_swap:
4133 result = visit_atomic_ssbo(ctx, instr);
4134 break;
4135 case nir_intrinsic_load_ubo:
4136 result = visit_load_ubo_buffer(ctx, instr);
4137 break;
4138 case nir_intrinsic_get_buffer_size:
4139 result = visit_get_buffer_size(ctx, instr);
4140 break;
4141 case nir_intrinsic_load_var:
4142 result = visit_load_var(ctx, instr);
4143 break;
4144 case nir_intrinsic_store_var:
4145 visit_store_var(ctx, instr);
4146 break;
4147 case nir_intrinsic_image_load:
4148 result = visit_image_load(ctx, instr);
4149 break;
4150 case nir_intrinsic_image_store:
4151 visit_image_store(ctx, instr);
4152 break;
4153 case nir_intrinsic_image_atomic_add:
4154 case nir_intrinsic_image_atomic_min:
4155 case nir_intrinsic_image_atomic_max:
4156 case nir_intrinsic_image_atomic_and:
4157 case nir_intrinsic_image_atomic_or:
4158 case nir_intrinsic_image_atomic_xor:
4159 case nir_intrinsic_image_atomic_exchange:
4160 case nir_intrinsic_image_atomic_comp_swap:
4161 result = visit_image_atomic(ctx, instr);
4162 break;
4163 case nir_intrinsic_image_size:
4164 result = visit_image_size(ctx, instr);
4165 break;
4166 case nir_intrinsic_discard:
4167 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4168 LLVMVoidTypeInContext(ctx->ac.context),
4169 NULL, 0, AC_FUNC_ATTR_LEGACY);
4170 break;
4171 case nir_intrinsic_discard_if:
4172 emit_discard_if(ctx, instr);
4173 break;
4174 case nir_intrinsic_memory_barrier:
4175 emit_waitcnt(ctx->nctx, VM_CNT);
4176 break;
4177 case nir_intrinsic_barrier:
4178 emit_barrier(ctx->nctx);
4179 break;
4180 case nir_intrinsic_var_atomic_add:
4181 case nir_intrinsic_var_atomic_imin:
4182 case nir_intrinsic_var_atomic_umin:
4183 case nir_intrinsic_var_atomic_imax:
4184 case nir_intrinsic_var_atomic_umax:
4185 case nir_intrinsic_var_atomic_and:
4186 case nir_intrinsic_var_atomic_or:
4187 case nir_intrinsic_var_atomic_xor:
4188 case nir_intrinsic_var_atomic_exchange:
4189 case nir_intrinsic_var_atomic_comp_swap:
4190 result = visit_var_atomic(ctx->nctx, instr);
4191 break;
4192 case nir_intrinsic_interp_var_at_centroid:
4193 case nir_intrinsic_interp_var_at_sample:
4194 case nir_intrinsic_interp_var_at_offset:
4195 result = visit_interp(ctx->nctx, instr);
4196 break;
4197 case nir_intrinsic_emit_vertex:
4198 visit_emit_vertex(ctx->nctx, instr);
4199 break;
4200 case nir_intrinsic_end_primitive:
4201 visit_end_primitive(ctx->nctx, instr);
4202 break;
4203 case nir_intrinsic_load_tess_coord:
4204 result = visit_load_tess_coord(ctx->nctx, instr);
4205 break;
4206 case nir_intrinsic_load_patch_vertices_in:
4207 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4208 break;
4209 default:
4210 fprintf(stderr, "Unknown intrinsic: ");
4211 nir_print_instr(&instr->instr, stderr);
4212 fprintf(stderr, "\n");
4213 break;
4214 }
4215 if (result) {
4216 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4217 }
4218 }
4219
4220 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4221 LLVMValueRef buffer, bool write)
4222 {
4223 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4224
4225 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4226 ctx->shader_info->fs.writes_memory = true;
4227
4228 return buffer;
4229 }
4230
4231 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4232 unsigned descriptor_set,
4233 unsigned base_index,
4234 unsigned constant_index,
4235 LLVMValueRef index,
4236 enum ac_descriptor_type desc_type,
4237 bool image, bool write)
4238 {
4239 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4240 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4241 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4242 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4243 unsigned offset = binding->offset;
4244 unsigned stride = binding->size;
4245 unsigned type_size;
4246 LLVMBuilderRef builder = ctx->builder;
4247 LLVMTypeRef type;
4248
4249 assert(base_index < layout->binding_count);
4250
4251 if (write && ctx->stage == MESA_SHADER_FRAGMENT)
4252 ctx->shader_info->fs.writes_memory = true;
4253
4254 switch (desc_type) {
4255 case AC_DESC_IMAGE:
4256 type = ctx->v8i32;
4257 type_size = 32;
4258 break;
4259 case AC_DESC_FMASK:
4260 type = ctx->v8i32;
4261 offset += 32;
4262 type_size = 32;
4263 break;
4264 case AC_DESC_SAMPLER:
4265 type = ctx->v4i32;
4266 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4267 offset += 64;
4268
4269 type_size = 16;
4270 break;
4271 case AC_DESC_BUFFER:
4272 type = ctx->v4i32;
4273 type_size = 16;
4274 break;
4275 default:
4276 unreachable("invalid desc_type\n");
4277 }
4278
4279 offset += constant_index * stride;
4280
4281 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4282 (!index || binding->immutable_samplers_equal)) {
4283 if (binding->immutable_samplers_equal)
4284 constant_index = 0;
4285
4286 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4287
4288 LLVMValueRef constants[] = {
4289 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4290 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4291 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4292 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4293 };
4294 return ac_build_gather_values(&ctx->ac, constants, 4);
4295 }
4296
4297 assert(stride % type_size == 0);
4298
4299 if (!index)
4300 index = ctx->ac.i32_0;
4301
4302 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4303
4304 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4305 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4306
4307 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4308 }
4309
4310 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4311 const nir_deref_var *deref,
4312 enum ac_descriptor_type desc_type,
4313 const nir_tex_instr *tex_instr,
4314 bool image, bool write)
4315 {
4316 LLVMValueRef index = NULL;
4317 unsigned constant_index = 0;
4318 unsigned descriptor_set;
4319 unsigned base_index;
4320
4321 if (!deref) {
4322 assert(tex_instr && !image);
4323 descriptor_set = 0;
4324 base_index = tex_instr->sampler_index;
4325 } else {
4326 const nir_deref *tail = &deref->deref;
4327 while (tail->child) {
4328 const nir_deref_array *child = nir_deref_as_array(tail->child);
4329 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4330
4331 if (!array_size)
4332 array_size = 1;
4333
4334 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4335
4336 if (child->deref_array_type == nir_deref_array_type_indirect) {
4337 LLVMValueRef indirect = get_src(ctx, child->indirect);
4338
4339 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4340 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4341
4342 if (!index)
4343 index = indirect;
4344 else
4345 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4346 }
4347
4348 constant_index += child->base_offset * array_size;
4349
4350 tail = &child->deref;
4351 }
4352 descriptor_set = deref->var->data.descriptor_set;
4353 base_index = deref->var->data.binding;
4354 }
4355
4356 return ctx->abi->load_sampler_desc(ctx->abi,
4357 descriptor_set,
4358 base_index,
4359 constant_index, index,
4360 desc_type, image, write);
4361 }
4362
4363 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4364 struct ac_image_args *args,
4365 const nir_tex_instr *instr,
4366 nir_texop op,
4367 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4368 LLVMValueRef *param, unsigned count,
4369 unsigned dmask)
4370 {
4371 unsigned is_rect = 0;
4372 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4373
4374 if (op == nir_texop_lod)
4375 da = false;
4376 /* Pad to power of two vector */
4377 while (count < util_next_power_of_two(count))
4378 param[count++] = LLVMGetUndef(ctx->i32);
4379
4380 if (count > 1)
4381 args->addr = ac_build_gather_values(ctx, param, count);
4382 else
4383 args->addr = param[0];
4384
4385 args->resource = res_ptr;
4386 args->sampler = samp_ptr;
4387
4388 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4389 args->addr = param[0];
4390 return;
4391 }
4392
4393 args->dmask = dmask;
4394 args->unorm = is_rect;
4395 args->da = da;
4396 }
4397
4398 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4399 *
4400 * SI-CI:
4401 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4402 * filtering manually. The driver sets img7 to a mask clearing
4403 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4404 * s_and_b32 samp0, samp0, img7
4405 *
4406 * VI:
4407 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4408 */
4409 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4410 LLVMValueRef res, LLVMValueRef samp)
4411 {
4412 LLVMBuilderRef builder = ctx->ac.builder;
4413 LLVMValueRef img7, samp0;
4414
4415 if (ctx->ac.chip_class >= VI)
4416 return samp;
4417
4418 img7 = LLVMBuildExtractElement(builder, res,
4419 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4420 samp0 = LLVMBuildExtractElement(builder, samp,
4421 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4422 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4423 return LLVMBuildInsertElement(builder, samp, samp0,
4424 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4425 }
4426
4427 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4428 nir_tex_instr *instr,
4429 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4430 LLVMValueRef *fmask_ptr)
4431 {
4432 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4433 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4434 else
4435 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4436 if (samp_ptr) {
4437 if (instr->sampler)
4438 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4439 else
4440 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4441 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4442 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4443 }
4444 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4445 instr->op == nir_texop_samples_identical))
4446 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4447 }
4448
4449 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4450 LLVMValueRef coord)
4451 {
4452 coord = ac_to_float(ctx, coord);
4453 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4454 coord = ac_to_integer(ctx, coord);
4455 return coord;
4456 }
4457
4458 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4459 {
4460 LLVMValueRef result = NULL;
4461 struct ac_image_args args = { 0 };
4462 unsigned dmask = 0xf;
4463 LLVMValueRef address[16];
4464 LLVMValueRef coords[5];
4465 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4466 LLVMValueRef bias = NULL, offsets = NULL;
4467 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4468 LLVMValueRef ddx = NULL, ddy = NULL;
4469 LLVMValueRef derivs[6];
4470 unsigned chan, count = 0;
4471 unsigned const_src = 0, num_deriv_comp = 0;
4472 bool lod_is_zero = false;
4473
4474 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4475
4476 for (unsigned i = 0; i < instr->num_srcs; i++) {
4477 switch (instr->src[i].src_type) {
4478 case nir_tex_src_coord:
4479 coord = get_src(ctx, instr->src[i].src);
4480 break;
4481 case nir_tex_src_projector:
4482 break;
4483 case nir_tex_src_comparator:
4484 comparator = get_src(ctx, instr->src[i].src);
4485 break;
4486 case nir_tex_src_offset:
4487 offsets = get_src(ctx, instr->src[i].src);
4488 const_src = i;
4489 break;
4490 case nir_tex_src_bias:
4491 bias = get_src(ctx, instr->src[i].src);
4492 break;
4493 case nir_tex_src_lod: {
4494 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4495
4496 if (val && val->i32[0] == 0)
4497 lod_is_zero = true;
4498 lod = get_src(ctx, instr->src[i].src);
4499 break;
4500 }
4501 case nir_tex_src_ms_index:
4502 sample_index = get_src(ctx, instr->src[i].src);
4503 break;
4504 case nir_tex_src_ms_mcs:
4505 break;
4506 case nir_tex_src_ddx:
4507 ddx = get_src(ctx, instr->src[i].src);
4508 num_deriv_comp = instr->src[i].src.ssa->num_components;
4509 break;
4510 case nir_tex_src_ddy:
4511 ddy = get_src(ctx, instr->src[i].src);
4512 break;
4513 case nir_tex_src_texture_offset:
4514 case nir_tex_src_sampler_offset:
4515 case nir_tex_src_plane:
4516 default:
4517 break;
4518 }
4519 }
4520
4521 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4522 result = get_buffer_size(ctx, res_ptr, true);
4523 goto write_result;
4524 }
4525
4526 if (instr->op == nir_texop_texture_samples) {
4527 LLVMValueRef res, samples, is_msaa;
4528 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4529 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4530 LLVMConstInt(ctx->ac.i32, 3, false), "");
4531 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4532 LLVMConstInt(ctx->ac.i32, 28, false), "");
4533 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4534 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4535 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4536 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4537
4538 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4539 LLVMConstInt(ctx->ac.i32, 16, false), "");
4540 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4541 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4542 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4543 samples, "");
4544 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4545 ctx->ac.i32_1, "");
4546 result = samples;
4547 goto write_result;
4548 }
4549
4550 if (coord)
4551 for (chan = 0; chan < instr->coord_components; chan++)
4552 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4553
4554 if (offsets && instr->op != nir_texop_txf) {
4555 LLVMValueRef offset[3], pack;
4556 for (chan = 0; chan < 3; ++chan)
4557 offset[chan] = ctx->ac.i32_0;
4558
4559 args.offset = true;
4560 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4561 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4562 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4563 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4564 if (chan)
4565 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4566 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4567 }
4568 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4569 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4570 address[count++] = pack;
4571
4572 }
4573 /* pack LOD bias value */
4574 if (instr->op == nir_texop_txb && bias) {
4575 address[count++] = bias;
4576 }
4577
4578 /* Pack depth comparison value */
4579 if (instr->is_shadow && comparator) {
4580 LLVMValueRef z = ac_to_float(&ctx->ac,
4581 llvm_extract_elem(&ctx->ac, comparator, 0));
4582
4583 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4584 * so the depth comparison value isn't clamped for Z16 and
4585 * Z24 anymore. Do it manually here.
4586 *
4587 * It's unnecessary if the original texture format was
4588 * Z32_FLOAT, but we don't know that here.
4589 */
4590 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4591 z = ac_build_clamp(&ctx->ac, z);
4592
4593 address[count++] = z;
4594 }
4595
4596 /* pack derivatives */
4597 if (ddx || ddy) {
4598 int num_src_deriv_channels, num_dest_deriv_channels;
4599 switch (instr->sampler_dim) {
4600 case GLSL_SAMPLER_DIM_3D:
4601 case GLSL_SAMPLER_DIM_CUBE:
4602 num_deriv_comp = 3;
4603 num_src_deriv_channels = 3;
4604 num_dest_deriv_channels = 3;
4605 break;
4606 case GLSL_SAMPLER_DIM_2D:
4607 default:
4608 num_src_deriv_channels = 2;
4609 num_dest_deriv_channels = 2;
4610 num_deriv_comp = 2;
4611 break;
4612 case GLSL_SAMPLER_DIM_1D:
4613 num_src_deriv_channels = 1;
4614 if (ctx->ac.chip_class >= GFX9) {
4615 num_dest_deriv_channels = 2;
4616 num_deriv_comp = 2;
4617 } else {
4618 num_dest_deriv_channels = 1;
4619 num_deriv_comp = 1;
4620 }
4621 break;
4622 }
4623
4624 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
4625 derivs[i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4626 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4627 }
4628 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
4629 derivs[i] = ctx->ac.f32_0;
4630 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
4631 }
4632 }
4633
4634 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4635 for (chan = 0; chan < instr->coord_components; chan++)
4636 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
4637 if (instr->coord_components == 3)
4638 coords[3] = LLVMGetUndef(ctx->ac.f32);
4639 ac_prepare_cube_coords(&ctx->ac,
4640 instr->op == nir_texop_txd, instr->is_array,
4641 instr->op == nir_texop_lod, coords, derivs);
4642 if (num_deriv_comp)
4643 num_deriv_comp--;
4644 }
4645
4646 if (ddx || ddy) {
4647 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4648 address[count++] = derivs[i];
4649 }
4650
4651 /* Pack texture coordinates */
4652 if (coord) {
4653 address[count++] = coords[0];
4654 if (instr->coord_components > 1) {
4655 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4656 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4657 }
4658 address[count++] = coords[1];
4659 }
4660 if (instr->coord_components > 2) {
4661 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4662 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4663 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4664 instr->op != nir_texop_txf) {
4665 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4666 }
4667 address[count++] = coords[2];
4668 }
4669
4670 if (ctx->ac.chip_class >= GFX9) {
4671 LLVMValueRef filler;
4672 if (instr->op == nir_texop_txf)
4673 filler = ctx->ac.i32_0;
4674 else
4675 filler = LLVMConstReal(ctx->ac.f32, 0.5);
4676
4677 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
4678 /* No nir_texop_lod, because it does not take a slice
4679 * even with array textures. */
4680 if (instr->is_array && instr->op != nir_texop_lod ) {
4681 address[count] = address[count - 1];
4682 address[count - 1] = filler;
4683 count++;
4684 } else
4685 address[count++] = filler;
4686 }
4687 }
4688 }
4689
4690 /* Pack LOD */
4691 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4692 instr->op == nir_texop_txf)) {
4693 address[count++] = lod;
4694 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4695 address[count++] = sample_index;
4696 } else if(instr->op == nir_texop_txs) {
4697 count = 0;
4698 if (lod)
4699 address[count++] = lod;
4700 else
4701 address[count++] = ctx->ac.i32_0;
4702 }
4703
4704 for (chan = 0; chan < count; chan++) {
4705 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4706 address[chan], ctx->ac.i32, "");
4707 }
4708
4709 if (instr->op == nir_texop_samples_identical) {
4710 LLVMValueRef txf_address[4];
4711 struct ac_image_args txf_args = { 0 };
4712 unsigned txf_count = count;
4713 memcpy(txf_address, address, sizeof(txf_address));
4714
4715 if (!instr->is_array)
4716 txf_address[2] = ctx->ac.i32_0;
4717 txf_address[3] = ctx->ac.i32_0;
4718
4719 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4720 fmask_ptr, NULL,
4721 txf_address, txf_count, 0xf);
4722
4723 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4724
4725 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4726 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4727 goto write_result;
4728 }
4729
4730 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4731 instr->op != nir_texop_txs) {
4732 unsigned sample_chan = instr->is_array ? 3 : 2;
4733 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4734 address[0],
4735 address[1],
4736 instr->is_array ? address[2] : NULL,
4737 address[sample_chan],
4738 fmask_ptr);
4739 }
4740
4741 if (offsets && instr->op == nir_texop_txf) {
4742 nir_const_value *const_offset =
4743 nir_src_as_const_value(instr->src[const_src].src);
4744 int num_offsets = instr->src[const_src].src.ssa->num_components;
4745 assert(const_offset);
4746 num_offsets = MIN2(num_offsets, instr->coord_components);
4747 if (num_offsets > 2)
4748 address[2] = LLVMBuildAdd(ctx->ac.builder,
4749 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4750 if (num_offsets > 1)
4751 address[1] = LLVMBuildAdd(ctx->ac.builder,
4752 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4753 address[0] = LLVMBuildAdd(ctx->ac.builder,
4754 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4755
4756 }
4757
4758 /* TODO TG4 support */
4759 if (instr->op == nir_texop_tg4) {
4760 if (instr->is_shadow)
4761 dmask = 1;
4762 else
4763 dmask = 1 << instr->component;
4764 }
4765 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4766 res_ptr, samp_ptr, address, count, dmask);
4767
4768 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4769
4770 if (instr->op == nir_texop_query_levels)
4771 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4772 else if (instr->is_shadow && instr->is_new_style_shadow &&
4773 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
4774 instr->op != nir_texop_tg4)
4775 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4776 else if (instr->op == nir_texop_txs &&
4777 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4778 instr->is_array) {
4779 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4780 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4781 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4782 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4783 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4784 } else if (ctx->ac.chip_class >= GFX9 &&
4785 instr->op == nir_texop_txs &&
4786 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
4787 instr->is_array) {
4788 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4789 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4790 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
4791 ctx->ac.i32_1, "");
4792 } else if (instr->dest.ssa.num_components != 4)
4793 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4794
4795 write_result:
4796 if (result) {
4797 assert(instr->dest.is_ssa);
4798 result = ac_to_integer(&ctx->ac, result);
4799 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4800 }
4801 }
4802
4803
4804 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4805 {
4806 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4807 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4808
4809 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4810 _mesa_hash_table_insert(ctx->phis, instr, result);
4811 }
4812
4813 static void visit_post_phi(struct ac_nir_context *ctx,
4814 nir_phi_instr *instr,
4815 LLVMValueRef llvm_phi)
4816 {
4817 nir_foreach_phi_src(src, instr) {
4818 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4819 LLVMValueRef llvm_src = get_src(ctx, src->src);
4820
4821 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4822 }
4823 }
4824
4825 static void phi_post_pass(struct ac_nir_context *ctx)
4826 {
4827 struct hash_entry *entry;
4828 hash_table_foreach(ctx->phis, entry) {
4829 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4830 (LLVMValueRef)entry->data);
4831 }
4832 }
4833
4834
4835 static void visit_ssa_undef(struct ac_nir_context *ctx,
4836 const nir_ssa_undef_instr *instr)
4837 {
4838 unsigned num_components = instr->def.num_components;
4839 LLVMValueRef undef;
4840
4841 if (num_components == 1)
4842 undef = LLVMGetUndef(ctx->ac.i32);
4843 else {
4844 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4845 }
4846 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4847 }
4848
4849 static void visit_jump(struct ac_nir_context *ctx,
4850 const nir_jump_instr *instr)
4851 {
4852 switch (instr->type) {
4853 case nir_jump_break:
4854 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4855 LLVMClearInsertionPosition(ctx->ac.builder);
4856 break;
4857 case nir_jump_continue:
4858 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4859 LLVMClearInsertionPosition(ctx->ac.builder);
4860 break;
4861 default:
4862 fprintf(stderr, "Unknown NIR jump instr: ");
4863 nir_print_instr(&instr->instr, stderr);
4864 fprintf(stderr, "\n");
4865 abort();
4866 }
4867 }
4868
4869 static void visit_cf_list(struct ac_nir_context *ctx,
4870 struct exec_list *list);
4871
4872 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4873 {
4874 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4875 nir_foreach_instr(instr, block)
4876 {
4877 switch (instr->type) {
4878 case nir_instr_type_alu:
4879 visit_alu(ctx, nir_instr_as_alu(instr));
4880 break;
4881 case nir_instr_type_load_const:
4882 visit_load_const(ctx, nir_instr_as_load_const(instr));
4883 break;
4884 case nir_instr_type_intrinsic:
4885 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4886 break;
4887 case nir_instr_type_tex:
4888 visit_tex(ctx, nir_instr_as_tex(instr));
4889 break;
4890 case nir_instr_type_phi:
4891 visit_phi(ctx, nir_instr_as_phi(instr));
4892 break;
4893 case nir_instr_type_ssa_undef:
4894 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4895 break;
4896 case nir_instr_type_jump:
4897 visit_jump(ctx, nir_instr_as_jump(instr));
4898 break;
4899 default:
4900 fprintf(stderr, "Unknown NIR instr type: ");
4901 nir_print_instr(instr, stderr);
4902 fprintf(stderr, "\n");
4903 abort();
4904 }
4905 }
4906
4907 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4908 }
4909
4910 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4911 {
4912 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4913
4914 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4915 LLVMBasicBlockRef merge_block =
4916 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4917 LLVMBasicBlockRef if_block =
4918 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4919 LLVMBasicBlockRef else_block = merge_block;
4920 if (!exec_list_is_empty(&if_stmt->else_list))
4921 else_block = LLVMAppendBasicBlockInContext(
4922 ctx->ac.context, fn, "");
4923
4924 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4925 LLVMConstInt(ctx->ac.i32, 0, false), "");
4926 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4927
4928 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4929 visit_cf_list(ctx, &if_stmt->then_list);
4930 if (LLVMGetInsertBlock(ctx->ac.builder))
4931 LLVMBuildBr(ctx->ac.builder, merge_block);
4932
4933 if (!exec_list_is_empty(&if_stmt->else_list)) {
4934 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4935 visit_cf_list(ctx, &if_stmt->else_list);
4936 if (LLVMGetInsertBlock(ctx->ac.builder))
4937 LLVMBuildBr(ctx->ac.builder, merge_block);
4938 }
4939
4940 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4941 }
4942
4943 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4944 {
4945 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4946 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4947 LLVMBasicBlockRef break_parent = ctx->break_block;
4948
4949 ctx->continue_block =
4950 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4951 ctx->break_block =
4952 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4953
4954 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4955 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4956 visit_cf_list(ctx, &loop->body);
4957
4958 if (LLVMGetInsertBlock(ctx->ac.builder))
4959 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4960 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4961
4962 ctx->continue_block = continue_parent;
4963 ctx->break_block = break_parent;
4964 }
4965
4966 static void visit_cf_list(struct ac_nir_context *ctx,
4967 struct exec_list *list)
4968 {
4969 foreach_list_typed(nir_cf_node, node, node, list)
4970 {
4971 switch (node->type) {
4972 case nir_cf_node_block:
4973 visit_block(ctx, nir_cf_node_as_block(node));
4974 break;
4975
4976 case nir_cf_node_if:
4977 visit_if(ctx, nir_cf_node_as_if(node));
4978 break;
4979
4980 case nir_cf_node_loop:
4981 visit_loop(ctx, nir_cf_node_as_loop(node));
4982 break;
4983
4984 default:
4985 assert(0);
4986 }
4987 }
4988 }
4989
4990 static void
4991 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4992 struct nir_variable *variable)
4993 {
4994 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4995 LLVMValueRef t_offset;
4996 LLVMValueRef t_list;
4997 LLVMValueRef input;
4998 LLVMValueRef buffer_index;
4999 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5000 int idx = variable->data.location;
5001 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5002
5003 variable->data.driver_location = idx * 4;
5004
5005 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
5006 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
5007 ctx->abi.start_instance, "");
5008 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
5009 ctx->shader_info->vs.vgpr_comp_cnt);
5010 } else
5011 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
5012 ctx->abi.base_vertex, "");
5013
5014 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5015 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5016
5017 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5018
5019 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5020 buffer_index,
5021 LLVMConstInt(ctx->ac.i32, 0, false),
5022 true);
5023
5024 for (unsigned chan = 0; chan < 4; chan++) {
5025 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5026 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5027 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
5028 input, llvm_chan, ""));
5029 }
5030 }
5031 }
5032
5033 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5034 unsigned attr,
5035 LLVMValueRef interp_param,
5036 LLVMValueRef prim_mask,
5037 LLVMValueRef result[4])
5038 {
5039 LLVMValueRef attr_number;
5040 unsigned chan;
5041 LLVMValueRef i, j;
5042 bool interp = interp_param != NULL;
5043
5044 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5045
5046 /* fs.constant returns the param from the middle vertex, so it's not
5047 * really useful for flat shading. It's meant to be used for custom
5048 * interpolation (but the intrinsic can't fetch from the other two
5049 * vertices).
5050 *
5051 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5052 * to do the right thing. The only reason we use fs.constant is that
5053 * fs.interp cannot be used on integers, because they can be equal
5054 * to NaN.
5055 */
5056 if (interp) {
5057 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
5058 LLVMVectorType(ctx->f32, 2), "");
5059
5060 i = LLVMBuildExtractElement(ctx->builder, interp_param,
5061 ctx->ac.i32_0, "");
5062 j = LLVMBuildExtractElement(ctx->builder, interp_param,
5063 ctx->ac.i32_1, "");
5064 }
5065
5066 for (chan = 0; chan < 4; chan++) {
5067 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5068
5069 if (interp) {
5070 result[chan] = ac_build_fs_interp(&ctx->ac,
5071 llvm_chan,
5072 attr_number,
5073 prim_mask, i, j);
5074 } else {
5075 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5076 LLVMConstInt(ctx->ac.i32, 2, false),
5077 llvm_chan,
5078 attr_number,
5079 prim_mask);
5080 }
5081 }
5082 }
5083
5084 static void
5085 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5086 struct nir_variable *variable)
5087 {
5088 int idx = variable->data.location;
5089 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5090 LLVMValueRef interp;
5091
5092 variable->data.driver_location = idx * 4;
5093 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5094
5095 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5096 unsigned interp_type;
5097 if (variable->data.sample) {
5098 interp_type = INTERP_SAMPLE;
5099 ctx->shader_info->info.ps.force_persample = true;
5100 } else if (variable->data.centroid)
5101 interp_type = INTERP_CENTROID;
5102 else
5103 interp_type = INTERP_CENTER;
5104
5105 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
5106 } else
5107 interp = NULL;
5108
5109 for (unsigned i = 0; i < attrib_count; ++i)
5110 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5111
5112 }
5113
5114 static void
5115 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5116 struct nir_shader *nir) {
5117 nir_foreach_variable(variable, &nir->inputs)
5118 handle_vs_input_decl(ctx, variable);
5119 }
5120
5121 static void
5122 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5123 struct nir_shader *nir)
5124 {
5125 if (!ctx->options->key.fs.multisample)
5126 return;
5127
5128 bool uses_center = false;
5129 bool uses_centroid = false;
5130 nir_foreach_variable(variable, &nir->inputs) {
5131 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5132 variable->data.sample)
5133 continue;
5134
5135 if (variable->data.centroid)
5136 uses_centroid = true;
5137 else
5138 uses_center = true;
5139 }
5140
5141 if (uses_center && uses_centroid) {
5142 LLVMValueRef sel = LLVMBuildICmp(ctx->builder, LLVMIntSLT, ctx->prim_mask, ctx->ac.i32_0, "");
5143 ctx->persp_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5144 ctx->linear_centroid = LLVMBuildSelect(ctx->builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5145 }
5146 }
5147
5148 static void
5149 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5150 struct nir_shader *nir)
5151 {
5152 prepare_interp_optimize(ctx, nir);
5153
5154 nir_foreach_variable(variable, &nir->inputs)
5155 handle_fs_input_decl(ctx, variable);
5156
5157 unsigned index = 0;
5158
5159 if (ctx->shader_info->info.ps.uses_input_attachments ||
5160 ctx->shader_info->info.needs_multiview_view_index)
5161 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5162
5163 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5164 LLVMValueRef interp_param;
5165 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5166
5167 if (!(ctx->input_mask & (1ull << i)))
5168 continue;
5169
5170 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5171 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5172 interp_param = *inputs;
5173 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
5174 inputs);
5175
5176 if (!interp_param)
5177 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5178 ++index;
5179 } else if (i == VARYING_SLOT_POS) {
5180 for(int i = 0; i < 3; ++i)
5181 inputs[i] = ctx->abi.frag_pos[i];
5182
5183 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5184 ctx->abi.frag_pos[3]);
5185 }
5186 }
5187 ctx->shader_info->fs.num_interp = index;
5188 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5189 ctx->shader_info->fs.has_pcoord = true;
5190 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5191 ctx->shader_info->fs.prim_id_input = true;
5192 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5193 ctx->shader_info->fs.layer_input = true;
5194 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5195
5196 if (ctx->shader_info->info.needs_multiview_view_index)
5197 ctx->view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5198 }
5199
5200 static LLVMValueRef
5201 ac_build_alloca(struct ac_llvm_context *ac,
5202 LLVMTypeRef type,
5203 const char *name)
5204 {
5205 LLVMBuilderRef builder = ac->builder;
5206 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5207 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5208 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5209 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5210 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5211 LLVMValueRef res;
5212
5213 if (first_instr) {
5214 LLVMPositionBuilderBefore(first_builder, first_instr);
5215 } else {
5216 LLVMPositionBuilderAtEnd(first_builder, first_block);
5217 }
5218
5219 res = LLVMBuildAlloca(first_builder, type, name);
5220 LLVMBuildStore(builder, LLVMConstNull(type), res);
5221
5222 LLVMDisposeBuilder(first_builder);
5223
5224 return res;
5225 }
5226
5227 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5228 LLVMTypeRef type,
5229 const char *name)
5230 {
5231 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5232 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5233 return ptr;
5234 }
5235
5236 static void
5237 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5238 struct nir_variable *variable,
5239 struct nir_shader *shader,
5240 gl_shader_stage stage)
5241 {
5242 int idx = variable->data.location + variable->data.index;
5243 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5244 uint64_t mask_attribs;
5245
5246 variable->data.driver_location = idx * 4;
5247
5248 /* tess ctrl has it's own load/store paths for outputs */
5249 if (stage == MESA_SHADER_TESS_CTRL)
5250 return;
5251
5252 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5253 if (stage == MESA_SHADER_VERTEX ||
5254 stage == MESA_SHADER_TESS_EVAL ||
5255 stage == MESA_SHADER_GEOMETRY) {
5256 if (idx == VARYING_SLOT_CLIP_DIST0) {
5257 int length = shader->info.clip_distance_array_size +
5258 shader->info.cull_distance_array_size;
5259 if (stage == MESA_SHADER_VERTEX) {
5260 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5261 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5262 }
5263 if (stage == MESA_SHADER_TESS_EVAL) {
5264 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5265 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5266 }
5267
5268 if (length > 4)
5269 attrib_count = 2;
5270 else
5271 attrib_count = 1;
5272 mask_attribs = 1ull << idx;
5273 }
5274 }
5275
5276 ctx->output_mask |= mask_attribs;
5277 }
5278
5279 static void
5280 handle_shader_output_decl(struct ac_nir_context *ctx,
5281 struct nir_shader *nir,
5282 struct nir_variable *variable)
5283 {
5284 unsigned output_loc = variable->data.driver_location / 4;
5285 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5286
5287 /* tess ctrl has it's own load/store paths for outputs */
5288 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5289 return;
5290
5291 if (ctx->stage == MESA_SHADER_VERTEX ||
5292 ctx->stage == MESA_SHADER_TESS_EVAL ||
5293 ctx->stage == MESA_SHADER_GEOMETRY) {
5294 int idx = variable->data.location + variable->data.index;
5295 if (idx == VARYING_SLOT_CLIP_DIST0) {
5296 int length = nir->info.clip_distance_array_size +
5297 nir->info.cull_distance_array_size;
5298
5299 if (length > 4)
5300 attrib_count = 2;
5301 else
5302 attrib_count = 1;
5303 }
5304 }
5305
5306 for (unsigned i = 0; i < attrib_count; ++i) {
5307 for (unsigned chan = 0; chan < 4; chan++) {
5308 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5309 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5310 }
5311 }
5312 }
5313
5314 static LLVMTypeRef
5315 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5316 enum glsl_base_type type)
5317 {
5318 switch (type) {
5319 case GLSL_TYPE_INT:
5320 case GLSL_TYPE_UINT:
5321 case GLSL_TYPE_BOOL:
5322 case GLSL_TYPE_SUBROUTINE:
5323 return ctx->ac.i32;
5324 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5325 return ctx->f32;
5326 case GLSL_TYPE_INT64:
5327 case GLSL_TYPE_UINT64:
5328 return ctx->ac.i64;
5329 case GLSL_TYPE_DOUBLE:
5330 return ctx->f64;
5331 default:
5332 unreachable("unknown GLSL type");
5333 }
5334 }
5335
5336 static LLVMTypeRef
5337 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5338 const struct glsl_type *type)
5339 {
5340 if (glsl_type_is_scalar(type)) {
5341 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5342 }
5343
5344 if (glsl_type_is_vector(type)) {
5345 return LLVMVectorType(
5346 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5347 glsl_get_vector_elements(type));
5348 }
5349
5350 if (glsl_type_is_matrix(type)) {
5351 return LLVMArrayType(
5352 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5353 glsl_get_matrix_columns(type));
5354 }
5355
5356 if (glsl_type_is_array(type)) {
5357 return LLVMArrayType(
5358 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5359 glsl_get_length(type));
5360 }
5361
5362 assert(glsl_type_is_struct(type));
5363
5364 LLVMTypeRef member_types[glsl_get_length(type)];
5365
5366 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5367 member_types[i] =
5368 glsl_to_llvm_type(ctx,
5369 glsl_get_struct_field(type, i));
5370 }
5371
5372 return LLVMStructTypeInContext(ctx->context, member_types,
5373 glsl_get_length(type), false);
5374 }
5375
5376 static void
5377 setup_locals(struct ac_nir_context *ctx,
5378 struct nir_function *func)
5379 {
5380 int i, j;
5381 ctx->num_locals = 0;
5382 nir_foreach_variable(variable, &func->impl->locals) {
5383 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5384 variable->data.driver_location = ctx->num_locals * 4;
5385 ctx->num_locals += attrib_count;
5386 }
5387 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5388 if (!ctx->locals)
5389 return;
5390
5391 for (i = 0; i < ctx->num_locals; i++) {
5392 for (j = 0; j < 4; j++) {
5393 ctx->locals[i * 4 + j] =
5394 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5395 }
5396 }
5397 }
5398
5399 static void
5400 setup_shared(struct ac_nir_context *ctx,
5401 struct nir_shader *nir)
5402 {
5403 nir_foreach_variable(variable, &nir->shared) {
5404 LLVMValueRef shared =
5405 LLVMAddGlobalInAddressSpace(
5406 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5407 variable->name ? variable->name : "",
5408 LOCAL_ADDR_SPACE);
5409 _mesa_hash_table_insert(ctx->vars, variable, shared);
5410 }
5411 }
5412
5413 static LLVMValueRef
5414 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5415 {
5416 v = ac_to_float(ctx, v);
5417 v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5418 return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5419 }
5420
5421
5422 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5423 LLVMValueRef src0, LLVMValueRef src1)
5424 {
5425 LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
5426 LLVMValueRef comp[2];
5427
5428 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5429 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 65535, 0), "");
5430 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5431 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5432 }
5433
5434 /* Initialize arguments for the shader export intrinsic */
5435 static void
5436 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5437 LLVMValueRef *values,
5438 unsigned target,
5439 struct ac_export_args *args)
5440 {
5441 /* Default is 0xf. Adjusted below depending on the format. */
5442 args->enabled_channels = 0xf;
5443
5444 /* Specify whether the EXEC mask represents the valid mask */
5445 args->valid_mask = 0;
5446
5447 /* Specify whether this is the last export */
5448 args->done = 0;
5449
5450 /* Specify the target we are exporting */
5451 args->target = target;
5452
5453 args->compr = false;
5454 args->out[0] = LLVMGetUndef(ctx->f32);
5455 args->out[1] = LLVMGetUndef(ctx->f32);
5456 args->out[2] = LLVMGetUndef(ctx->f32);
5457 args->out[3] = LLVMGetUndef(ctx->f32);
5458
5459 if (!values)
5460 return;
5461
5462 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5463 LLVMValueRef val[4];
5464 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5465 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5466 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5467 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5468
5469 switch(col_format) {
5470 case V_028714_SPI_SHADER_ZERO:
5471 args->enabled_channels = 0; /* writemask */
5472 args->target = V_008DFC_SQ_EXP_NULL;
5473 break;
5474
5475 case V_028714_SPI_SHADER_32_R:
5476 args->enabled_channels = 1;
5477 args->out[0] = values[0];
5478 break;
5479
5480 case V_028714_SPI_SHADER_32_GR:
5481 args->enabled_channels = 0x3;
5482 args->out[0] = values[0];
5483 args->out[1] = values[1];
5484 break;
5485
5486 case V_028714_SPI_SHADER_32_AR:
5487 args->enabled_channels = 0x9;
5488 args->out[0] = values[0];
5489 args->out[3] = values[3];
5490 break;
5491
5492 case V_028714_SPI_SHADER_FP16_ABGR:
5493 args->compr = 1;
5494
5495 for (unsigned chan = 0; chan < 2; chan++) {
5496 LLVMValueRef pack_args[2] = {
5497 values[2 * chan],
5498 values[2 * chan + 1]
5499 };
5500 LLVMValueRef packed;
5501
5502 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5503 args->out[chan] = packed;
5504 }
5505 break;
5506
5507 case V_028714_SPI_SHADER_UNORM16_ABGR:
5508 for (unsigned chan = 0; chan < 4; chan++) {
5509 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5510 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5511 LLVMConstReal(ctx->f32, 65535), "");
5512 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5513 LLVMConstReal(ctx->f32, 0.5), "");
5514 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5515 ctx->ac.i32, "");
5516 }
5517
5518 args->compr = 1;
5519 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5520 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5521 break;
5522
5523 case V_028714_SPI_SHADER_SNORM16_ABGR:
5524 for (unsigned chan = 0; chan < 4; chan++) {
5525 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5526 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5527 LLVMConstReal(ctx->f32, 32767), "");
5528
5529 /* If positive, add 0.5, else add -0.5. */
5530 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5531 LLVMBuildSelect(ctx->builder,
5532 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5533 val[chan], ctx->ac.f32_0, ""),
5534 LLVMConstReal(ctx->f32, 0.5),
5535 LLVMConstReal(ctx->f32, -0.5), ""), "");
5536 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->ac.i32, "");
5537 }
5538
5539 args->compr = 1;
5540 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5541 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5542 break;
5543
5544 case V_028714_SPI_SHADER_UINT16_ABGR: {
5545 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5546 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
5547 LLVMValueRef max_alpha = !is_int10 ? max_rgb : LLVMConstInt(ctx->ac.i32, 3, 0);
5548
5549 for (unsigned chan = 0; chan < 4; chan++) {
5550 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5551 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], chan == 3 ? max_alpha : max_rgb);
5552 }
5553
5554 args->compr = 1;
5555 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5556 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5557 break;
5558 }
5559
5560 case V_028714_SPI_SHADER_SINT16_ABGR: {
5561 LLVMValueRef max_rgb = LLVMConstInt(ctx->ac.i32,
5562 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
5563 LLVMValueRef min_rgb = LLVMConstInt(ctx->ac.i32,
5564 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
5565 LLVMValueRef max_alpha = !is_int10 ? max_rgb : ctx->ac.i32_1;
5566 LLVMValueRef min_alpha = !is_int10 ? min_rgb : LLVMConstInt(ctx->ac.i32, -2, 0);
5567
5568 /* Clamp. */
5569 for (unsigned chan = 0; chan < 4; chan++) {
5570 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
5571 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], chan == 3 ? max_alpha : max_rgb);
5572 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], chan == 3 ? min_alpha : min_rgb);
5573 }
5574
5575 args->compr = 1;
5576 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5577 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5578 break;
5579 }
5580
5581 default:
5582 case V_028714_SPI_SHADER_32_ABGR:
5583 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5584 break;
5585 }
5586 } else
5587 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5588
5589 for (unsigned i = 0; i < 4; ++i)
5590 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5591 }
5592
5593 static void
5594 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5595 bool export_prim_id,
5596 struct ac_vs_output_info *outinfo)
5597 {
5598 uint32_t param_count = 0;
5599 unsigned target;
5600 unsigned pos_idx, num_pos_exports = 0;
5601 struct ac_export_args args, pos_args[4] = {};
5602 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5603 int i;
5604
5605 if (ctx->options->key.has_multiview_view_index) {
5606 LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5607 if(!*tmp_out) {
5608 for(unsigned i = 0; i < 4; ++i)
5609 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5610 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5611 }
5612
5613 LLVMBuildStore(ctx->builder, ac_to_float(&ctx->ac, ctx->view_index), *tmp_out);
5614 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5615 }
5616
5617 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5618 sizeof(outinfo->vs_output_param_offset));
5619
5620 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5621 LLVMValueRef slots[8];
5622 unsigned j;
5623
5624 if (outinfo->cull_dist_mask)
5625 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5626
5627 i = VARYING_SLOT_CLIP_DIST0;
5628 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5629 slots[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5630 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5631
5632 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5633 slots[i] = LLVMGetUndef(ctx->f32);
5634
5635 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5636 target = V_008DFC_SQ_EXP_POS + 3;
5637 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5638 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5639 &args, sizeof(args));
5640 }
5641
5642 target = V_008DFC_SQ_EXP_POS + 2;
5643 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5644 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5645 &args, sizeof(args));
5646
5647 }
5648
5649 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
5650 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5651 for (unsigned j = 0; j < 4; j++)
5652 pos_values[j] = LLVMBuildLoad(ctx->builder,
5653 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5654 }
5655 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5656
5657 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5658 outinfo->writes_pointsize = true;
5659 psize_value = LLVMBuildLoad(ctx->builder,
5660 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5661 }
5662
5663 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5664 outinfo->writes_layer = true;
5665 layer_value = LLVMBuildLoad(ctx->builder,
5666 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5667 }
5668
5669 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5670 outinfo->writes_viewport_index = true;
5671 viewport_index_value = LLVMBuildLoad(ctx->builder,
5672 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5673 }
5674
5675 if (outinfo->writes_pointsize ||
5676 outinfo->writes_layer ||
5677 outinfo->writes_viewport_index) {
5678 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
5679 (outinfo->writes_layer == true ? 4 : 0));
5680 pos_args[1].valid_mask = 0;
5681 pos_args[1].done = 0;
5682 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5683 pos_args[1].compr = 0;
5684 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
5685 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
5686 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
5687 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
5688
5689 if (outinfo->writes_pointsize == true)
5690 pos_args[1].out[0] = psize_value;
5691 if (outinfo->writes_layer == true)
5692 pos_args[1].out[2] = layer_value;
5693 if (outinfo->writes_viewport_index == true) {
5694 if (ctx->options->chip_class >= GFX9) {
5695 /* GFX9 has the layer in out.z[10:0] and the viewport
5696 * index in out.z[19:16].
5697 */
5698 LLVMValueRef v = viewport_index_value;
5699 v = ac_to_integer(&ctx->ac, v);
5700 v = LLVMBuildShl(ctx->builder, v,
5701 LLVMConstInt(ctx->ac.i32, 16, false),
5702 "");
5703 v = LLVMBuildOr(ctx->builder, v,
5704 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
5705
5706 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
5707 pos_args[1].enabled_channels |= 1 << 2;
5708 } else {
5709 pos_args[1].out[3] = viewport_index_value;
5710 pos_args[1].enabled_channels |= 1 << 3;
5711 }
5712 }
5713 }
5714 for (i = 0; i < 4; i++) {
5715 if (pos_args[i].out[0])
5716 num_pos_exports++;
5717 }
5718
5719 pos_idx = 0;
5720 for (i = 0; i < 4; i++) {
5721 if (!pos_args[i].out[0])
5722 continue;
5723
5724 /* Specify the target we are exporting */
5725 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5726 if (pos_idx == num_pos_exports)
5727 pos_args[i].done = 1;
5728 ac_build_export(&ctx->ac, &pos_args[i]);
5729 }
5730
5731 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5732 LLVMValueRef values[4];
5733 if (!(ctx->output_mask & (1ull << i)))
5734 continue;
5735
5736 for (unsigned j = 0; j < 4; j++)
5737 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5738 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5739
5740 if (i == VARYING_SLOT_LAYER) {
5741 target = V_008DFC_SQ_EXP_PARAM + param_count;
5742 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5743 param_count++;
5744 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5745 target = V_008DFC_SQ_EXP_PARAM + param_count;
5746 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5747 param_count++;
5748 } else if (i >= VARYING_SLOT_VAR0) {
5749 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5750 target = V_008DFC_SQ_EXP_PARAM + param_count;
5751 outinfo->vs_output_param_offset[i] = param_count;
5752 param_count++;
5753 } else
5754 continue;
5755
5756 si_llvm_init_export_args(ctx, values, target, &args);
5757
5758 if (target >= V_008DFC_SQ_EXP_POS &&
5759 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5760 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5761 &args, sizeof(args));
5762 } else {
5763 ac_build_export(&ctx->ac, &args);
5764 }
5765 }
5766
5767 if (export_prim_id) {
5768 LLVMValueRef values[4];
5769 target = V_008DFC_SQ_EXP_PARAM + param_count;
5770 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5771 param_count++;
5772
5773 values[0] = ctx->vs_prim_id;
5774 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5775 ctx->shader_info->vs.vgpr_comp_cnt);
5776 for (unsigned j = 1; j < 4; j++)
5777 values[j] = ctx->ac.f32_0;
5778 si_llvm_init_export_args(ctx, values, target, &args);
5779 ac_build_export(&ctx->ac, &args);
5780 outinfo->export_prim_id = true;
5781 }
5782
5783 outinfo->pos_exports = num_pos_exports;
5784 outinfo->param_exports = param_count;
5785 }
5786
5787 static void
5788 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5789 struct ac_es_output_info *outinfo)
5790 {
5791 int j;
5792 uint64_t max_output_written = 0;
5793 LLVMValueRef lds_base = NULL;
5794
5795 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5796 int param_index;
5797 int length = 4;
5798
5799 if (!(ctx->output_mask & (1ull << i)))
5800 continue;
5801
5802 if (i == VARYING_SLOT_CLIP_DIST0)
5803 length = ctx->num_output_clips + ctx->num_output_culls;
5804
5805 param_index = shader_io_get_unique_index(i);
5806
5807 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5808 }
5809
5810 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5811
5812 if (ctx->ac.chip_class >= GFX9) {
5813 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
5814 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
5815 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
5816 LLVMConstInt(ctx->ac.i32, 24, false),
5817 LLVMConstInt(ctx->ac.i32, 4, false), false);
5818 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
5819 LLVMBuildMul(ctx->ac.builder, wave_idx,
5820 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
5821 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
5822 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
5823 }
5824
5825 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5826 LLVMValueRef dw_addr;
5827 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5828 int param_index;
5829 int length = 4;
5830
5831 if (!(ctx->output_mask & (1ull << i)))
5832 continue;
5833
5834 if (i == VARYING_SLOT_CLIP_DIST0)
5835 length = ctx->num_output_clips + ctx->num_output_culls;
5836
5837 param_index = shader_io_get_unique_index(i);
5838
5839 if (lds_base) {
5840 dw_addr = LLVMBuildAdd(ctx->builder, lds_base,
5841 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
5842 "");
5843 }
5844 for (j = 0; j < length; j++) {
5845 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5846 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->ac.i32, "");
5847
5848 if (ctx->ac.chip_class >= GFX9) {
5849 ac_lds_store(&ctx->ac, dw_addr,
5850 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5851 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5852 } else {
5853 ac_build_buffer_store_dword(&ctx->ac,
5854 ctx->esgs_ring,
5855 out_val, 1,
5856 NULL, ctx->es2gs_offset,
5857 (4 * param_index + j) * 4,
5858 1, 1, true, true);
5859 }
5860 }
5861 }
5862 }
5863
5864 static void
5865 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5866 {
5867 LLVMValueRef vertex_id = ctx->rel_auto_id;
5868 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
5869 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5870 vertex_dw_stride, "");
5871
5872 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5873 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5874 int length = 4;
5875
5876 if (!(ctx->output_mask & (1ull << i)))
5877 continue;
5878
5879 if (i == VARYING_SLOT_CLIP_DIST0)
5880 length = ctx->num_output_clips + ctx->num_output_culls;
5881 int param = shader_io_get_unique_index(i);
5882 mark_tess_output(ctx, false, param);
5883 if (length > 4)
5884 mark_tess_output(ctx, false, param + 1);
5885 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5886 LLVMConstInt(ctx->ac.i32, param * 4, false),
5887 "");
5888 for (unsigned j = 0; j < length; j++) {
5889 ac_lds_store(&ctx->ac, dw_addr,
5890 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5891 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->ac.i32_1, "");
5892 }
5893 }
5894 }
5895
5896 struct ac_build_if_state
5897 {
5898 struct nir_to_llvm_context *ctx;
5899 LLVMValueRef condition;
5900 LLVMBasicBlockRef entry_block;
5901 LLVMBasicBlockRef true_block;
5902 LLVMBasicBlockRef false_block;
5903 LLVMBasicBlockRef merge_block;
5904 };
5905
5906 static LLVMBasicBlockRef
5907 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5908 {
5909 LLVMBasicBlockRef current_block;
5910 LLVMBasicBlockRef next_block;
5911 LLVMBasicBlockRef new_block;
5912
5913 /* get current basic block */
5914 current_block = LLVMGetInsertBlock(ctx->builder);
5915
5916 /* chqeck if there's another block after this one */
5917 next_block = LLVMGetNextBasicBlock(current_block);
5918 if (next_block) {
5919 /* insert the new block before the next block */
5920 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5921 }
5922 else {
5923 /* append new block after current block */
5924 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5925 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5926 }
5927 return new_block;
5928 }
5929
5930 static void
5931 ac_nir_build_if(struct ac_build_if_state *ifthen,
5932 struct nir_to_llvm_context *ctx,
5933 LLVMValueRef condition)
5934 {
5935 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5936
5937 memset(ifthen, 0, sizeof *ifthen);
5938 ifthen->ctx = ctx;
5939 ifthen->condition = condition;
5940 ifthen->entry_block = block;
5941
5942 /* create endif/merge basic block for the phi functions */
5943 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5944
5945 /* create/insert true_block before merge_block */
5946 ifthen->true_block =
5947 LLVMInsertBasicBlockInContext(ctx->context,
5948 ifthen->merge_block,
5949 "if-true-block");
5950
5951 /* successive code goes into the true block */
5952 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5953 }
5954
5955 /**
5956 * End a conditional.
5957 */
5958 static void
5959 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5960 {
5961 LLVMBuilderRef builder = ifthen->ctx->builder;
5962
5963 /* Insert branch to the merge block from current block */
5964 LLVMBuildBr(builder, ifthen->merge_block);
5965
5966 /*
5967 * Now patch in the various branch instructions.
5968 */
5969
5970 /* Insert the conditional branch instruction at the end of entry_block */
5971 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5972 if (ifthen->false_block) {
5973 /* we have an else clause */
5974 LLVMBuildCondBr(builder, ifthen->condition,
5975 ifthen->true_block, ifthen->false_block);
5976 }
5977 else {
5978 /* no else clause */
5979 LLVMBuildCondBr(builder, ifthen->condition,
5980 ifthen->true_block, ifthen->merge_block);
5981 }
5982
5983 /* Resume building code at end of the ifthen->merge_block */
5984 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5985 }
5986
5987 static void
5988 write_tess_factors(struct nir_to_llvm_context *ctx)
5989 {
5990 unsigned stride, outer_comps, inner_comps;
5991 struct ac_build_if_state if_ctx, inner_if_ctx;
5992 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
5993 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
5994 unsigned tess_inner_index, tess_outer_index;
5995 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5996 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5997 int i;
5998 emit_barrier(ctx);
5999
6000 switch (ctx->options->key.tcs.primitive_mode) {
6001 case GL_ISOLINES:
6002 stride = 2;
6003 outer_comps = 2;
6004 inner_comps = 0;
6005 break;
6006 case GL_TRIANGLES:
6007 stride = 4;
6008 outer_comps = 3;
6009 inner_comps = 1;
6010 break;
6011 case GL_QUADS:
6012 stride = 6;
6013 outer_comps = 4;
6014 inner_comps = 2;
6015 break;
6016 default:
6017 return;
6018 }
6019
6020 ac_nir_build_if(&if_ctx, ctx,
6021 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6022 invocation_id, ctx->ac.i32_0, ""));
6023
6024 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6025 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6026
6027 mark_tess_output(ctx, true, tess_inner_index);
6028 mark_tess_output(ctx, true, tess_outer_index);
6029 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6030 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
6031 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6032 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
6033 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6034
6035 for (i = 0; i < 4; i++) {
6036 inner[i] = LLVMGetUndef(ctx->ac.i32);
6037 outer[i] = LLVMGetUndef(ctx->ac.i32);
6038 }
6039
6040 // LINES reverseal
6041 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6042 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6043 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6044 LLVMConstInt(ctx->ac.i32, 1, false), "");
6045 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6046 } else {
6047 for (i = 0; i < outer_comps; i++) {
6048 outer[i] = out[i] =
6049 ac_lds_load(&ctx->ac, lds_outer);
6050 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
6051 LLVMConstInt(ctx->ac.i32, 1, false), "");
6052 }
6053 for (i = 0; i < inner_comps; i++) {
6054 inner[i] = out[outer_comps+i] =
6055 ac_lds_load(&ctx->ac, lds_inner);
6056 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
6057 LLVMConstInt(ctx->ac.i32, 1, false), "");
6058 }
6059 }
6060
6061 /* Convert the outputs to vectors for stores. */
6062 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6063 vec1 = NULL;
6064
6065 if (stride > 4)
6066 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6067
6068
6069 buffer = ctx->hs_ring_tess_factor;
6070 tf_base = ctx->tess_factor_offset;
6071 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
6072 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6073 unsigned tf_offset = 0;
6074
6075 if (ctx->options->chip_class <= VI) {
6076 ac_nir_build_if(&inner_if_ctx, ctx,
6077 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
6078 rel_patch_id, ctx->ac.i32_0, ""));
6079
6080 /* Store the dynamic HS control word. */
6081 ac_build_buffer_store_dword(&ctx->ac, buffer,
6082 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6083 1, ctx->ac.i32_0, tf_base,
6084 0, 1, 0, true, false);
6085 tf_offset += 4;
6086
6087 ac_nir_build_endif(&inner_if_ctx);
6088 }
6089
6090 /* Store the tessellation factors. */
6091 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6092 MIN2(stride, 4), byteoffset, tf_base,
6093 tf_offset, 1, 0, true, false);
6094 if (vec1)
6095 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6096 stride - 4, byteoffset, tf_base,
6097 16 + tf_offset, 1, 0, true, false);
6098
6099 //store to offchip for TES to read - only if TES reads them
6100 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6101 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6102 LLVMValueRef tf_inner_offset;
6103 unsigned param_outer, param_inner;
6104
6105 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6106 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6107 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6108
6109 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6110 util_next_power_of_two(outer_comps));
6111
6112 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6113 outer_comps, tf_outer_offset,
6114 ctx->oc_lds, 0, 1, 0, true, false);
6115 if (inner_comps) {
6116 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6117 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6118 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6119
6120 inner_vec = inner_comps == 1 ? inner[0] :
6121 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6122 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6123 inner_comps, tf_inner_offset,
6124 ctx->oc_lds, 0, 1, 0, true, false);
6125 }
6126 }
6127 ac_nir_build_endif(&if_ctx);
6128 }
6129
6130 static void
6131 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6132 {
6133 write_tess_factors(ctx);
6134 }
6135
6136 static bool
6137 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6138 LLVMValueRef *color, unsigned param, bool is_last,
6139 struct ac_export_args *args)
6140 {
6141 /* Export */
6142 si_llvm_init_export_args(ctx, color, param,
6143 args);
6144
6145 if (is_last) {
6146 args->valid_mask = 1; /* whether the EXEC mask is valid */
6147 args->done = 1; /* DONE bit */
6148 } else if (!args->enabled_channels)
6149 return false; /* unnecessary NULL export */
6150
6151 return true;
6152 }
6153
6154 static void
6155 si_export_mrt_z(struct nir_to_llvm_context *ctx,
6156 LLVMValueRef depth, LLVMValueRef stencil,
6157 LLVMValueRef samplemask)
6158 {
6159 struct ac_export_args args;
6160
6161 args.enabled_channels = 0;
6162 args.valid_mask = 1;
6163 args.done = 1;
6164 args.target = V_008DFC_SQ_EXP_MRTZ;
6165 args.compr = false;
6166
6167 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
6168 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
6169 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
6170 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
6171
6172 if (depth) {
6173 args.out[0] = depth;
6174 args.enabled_channels |= 0x1;
6175 }
6176
6177 if (stencil) {
6178 args.out[1] = stencil;
6179 args.enabled_channels |= 0x2;
6180 }
6181
6182 if (samplemask) {
6183 args.out[2] = samplemask;
6184 args.enabled_channels |= 0x4;
6185 }
6186
6187 /* SI (except OLAND and HAINAN) has a bug that it only looks
6188 * at the X writemask component. */
6189 if (ctx->options->chip_class == SI &&
6190 ctx->options->family != CHIP_OLAND &&
6191 ctx->options->family != CHIP_HAINAN)
6192 args.enabled_channels |= 0x1;
6193
6194 ac_build_export(&ctx->ac, &args);
6195 }
6196
6197 static void
6198 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6199 {
6200 unsigned index = 0;
6201 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6202 struct ac_export_args color_args[8];
6203
6204 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6205 LLVMValueRef values[4];
6206
6207 if (!(ctx->output_mask & (1ull << i)))
6208 continue;
6209
6210 if (i == FRAG_RESULT_DEPTH) {
6211 ctx->shader_info->fs.writes_z = true;
6212 depth = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6213 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6214 } else if (i == FRAG_RESULT_STENCIL) {
6215 ctx->shader_info->fs.writes_stencil = true;
6216 stencil = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6217 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6218 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
6219 ctx->shader_info->fs.writes_sample_mask = true;
6220 samplemask = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6221 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
6222 } else {
6223 bool last = false;
6224 for (unsigned j = 0; j < 4; j++)
6225 values[j] = ac_to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
6226 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
6227
6228 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
6229 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6230
6231 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
6232 if (ret)
6233 index++;
6234 }
6235 }
6236
6237 for (unsigned i = 0; i < index; i++)
6238 ac_build_export(&ctx->ac, &color_args[i]);
6239 if (depth || stencil || samplemask)
6240 si_export_mrt_z(ctx, depth, stencil, samplemask);
6241 else if (!index) {
6242 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
6243 ac_build_export(&ctx->ac, &color_args[0]);
6244 }
6245
6246 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
6247 }
6248
6249 static void
6250 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6251 {
6252 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6253 }
6254
6255 static void
6256 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6257 LLVMValueRef *addrs)
6258 {
6259 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6260
6261 switch (ctx->stage) {
6262 case MESA_SHADER_VERTEX:
6263 if (ctx->options->key.vs.as_ls)
6264 handle_ls_outputs_post(ctx);
6265 else if (ctx->options->key.vs.as_es)
6266 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6267 else
6268 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6269 &ctx->shader_info->vs.outinfo);
6270 break;
6271 case MESA_SHADER_FRAGMENT:
6272 handle_fs_outputs_post(ctx);
6273 break;
6274 case MESA_SHADER_GEOMETRY:
6275 emit_gs_epilogue(ctx);
6276 break;
6277 case MESA_SHADER_TESS_CTRL:
6278 handle_tcs_outputs_post(ctx);
6279 break;
6280 case MESA_SHADER_TESS_EVAL:
6281 if (ctx->options->key.tes.as_es)
6282 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6283 else
6284 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6285 &ctx->shader_info->tes.outinfo);
6286 break;
6287 default:
6288 break;
6289 }
6290 }
6291
6292 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6293 {
6294 LLVMPassManagerRef passmgr;
6295 /* Create the pass manager */
6296 passmgr = LLVMCreateFunctionPassManagerForModule(
6297 ctx->module);
6298
6299 /* This pass should eliminate all the load and store instructions */
6300 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6301
6302 /* Add some optimization passes */
6303 LLVMAddScalarReplAggregatesPass(passmgr);
6304 LLVMAddLICMPass(passmgr);
6305 LLVMAddAggressiveDCEPass(passmgr);
6306 LLVMAddCFGSimplificationPass(passmgr);
6307 LLVMAddInstructionCombiningPass(passmgr);
6308
6309 /* Run the pass */
6310 LLVMInitializeFunctionPassManager(passmgr);
6311 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6312 LLVMFinalizeFunctionPassManager(passmgr);
6313
6314 LLVMDisposeBuilder(ctx->builder);
6315 LLVMDisposePassManager(passmgr);
6316 }
6317
6318 static void
6319 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6320 {
6321 struct ac_vs_output_info *outinfo;
6322
6323 switch (ctx->stage) {
6324 case MESA_SHADER_FRAGMENT:
6325 case MESA_SHADER_COMPUTE:
6326 case MESA_SHADER_TESS_CTRL:
6327 case MESA_SHADER_GEOMETRY:
6328 return;
6329 case MESA_SHADER_VERTEX:
6330 if (ctx->options->key.vs.as_ls ||
6331 ctx->options->key.vs.as_es)
6332 return;
6333 outinfo = &ctx->shader_info->vs.outinfo;
6334 break;
6335 case MESA_SHADER_TESS_EVAL:
6336 if (ctx->options->key.vs.as_es)
6337 return;
6338 outinfo = &ctx->shader_info->tes.outinfo;
6339 break;
6340 default:
6341 unreachable("Unhandled shader type");
6342 }
6343
6344 ac_optimize_vs_outputs(&ctx->ac,
6345 ctx->main_function,
6346 outinfo->vs_output_param_offset,
6347 VARYING_SLOT_MAX,
6348 &outinfo->param_exports);
6349 }
6350
6351 static void
6352 ac_setup_rings(struct nir_to_llvm_context *ctx)
6353 {
6354 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6355 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6356 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6357 }
6358
6359 if (ctx->is_gs_copy_shader) {
6360 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6361 }
6362 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6363 LLVMValueRef tmp;
6364 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6365 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6366
6367 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6368
6369 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6370 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6371 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6372 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6373 }
6374
6375 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6376 ctx->stage == MESA_SHADER_TESS_EVAL) {
6377 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6378 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6379 }
6380 }
6381
6382 static unsigned
6383 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6384 const struct nir_shader *nir)
6385 {
6386 switch (nir->info.stage) {
6387 case MESA_SHADER_TESS_CTRL:
6388 return chip_class >= CIK ? 128 : 64;
6389 case MESA_SHADER_GEOMETRY:
6390 return chip_class >= GFX9 ? 128 : 64;
6391 case MESA_SHADER_COMPUTE:
6392 break;
6393 default:
6394 return 0;
6395 }
6396
6397 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6398 nir->info.cs.local_size[1] *
6399 nir->info.cs.local_size[2];
6400 return max_workgroup_size;
6401 }
6402
6403 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6404 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6405 {
6406 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6407 LLVMConstInt(ctx->ac.i32, 8, false),
6408 LLVMConstInt(ctx->ac.i32, 8, false), false);
6409 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6410 LLVMConstInt(ctx->ac.i32, 0, false), "");
6411 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6412 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6413 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
6414 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, "");
6415 }
6416
6417 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6418 {
6419 for(int i = 5; i >= 0; --i) {
6420 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6421 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6422 LLVMConstInt(ctx->ac.i32, 16, false), false);
6423 }
6424
6425 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6426 LLVMConstInt(ctx->ac.i32, 16, false),
6427 LLVMConstInt(ctx->ac.i32, 8, false), false);
6428 }
6429
6430 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6431 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6432 {
6433 struct ac_nir_context ctx = {};
6434 struct nir_function *func;
6435
6436 ctx.ac = *ac;
6437 ctx.abi = abi;
6438
6439 ctx.nctx = nctx;
6440 if (nctx)
6441 nctx->nir = &ctx;
6442
6443 ctx.stage = nir->info.stage;
6444
6445 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6446
6447 nir_foreach_variable(variable, &nir->outputs)
6448 handle_shader_output_decl(&ctx, nir, variable);
6449
6450 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6451 _mesa_key_pointer_equal);
6452 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6453 _mesa_key_pointer_equal);
6454 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6455 _mesa_key_pointer_equal);
6456
6457 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6458
6459 setup_locals(&ctx, func);
6460
6461 if (nir->info.stage == MESA_SHADER_COMPUTE)
6462 setup_shared(&ctx, nir);
6463
6464 visit_cf_list(&ctx, &func->impl->body);
6465 phi_post_pass(&ctx);
6466
6467 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6468 ctx.outputs);
6469
6470 free(ctx.locals);
6471 ralloc_free(ctx.defs);
6472 ralloc_free(ctx.phis);
6473 ralloc_free(ctx.vars);
6474
6475 if (nctx)
6476 nctx->nir = NULL;
6477 }
6478
6479 static
6480 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6481 struct nir_shader *const *shaders,
6482 int shader_count,
6483 struct ac_shader_variant_info *shader_info,
6484 const struct ac_nir_compiler_options *options)
6485 {
6486 struct nir_to_llvm_context ctx = {0};
6487 unsigned i;
6488 ctx.options = options;
6489 ctx.shader_info = shader_info;
6490 ctx.context = LLVMContextCreate();
6491 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6492
6493 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6494 ctx.ac.module = ctx.module;
6495 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6496
6497 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6498 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6499 LLVMSetDataLayout(ctx.module, data_layout_str);
6500 LLVMDisposeTargetData(data_layout);
6501 LLVMDisposeMessage(data_layout_str);
6502
6503 setup_types(&ctx);
6504 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6505 ctx.ac.builder = ctx.builder;
6506
6507 memset(shader_info, 0, sizeof(*shader_info));
6508
6509 for(int i = 0; i < shader_count; ++i)
6510 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6511
6512 for (i = 0; i < AC_UD_MAX_SETS; i++)
6513 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6514 for (i = 0; i < AC_UD_MAX_UD; i++)
6515 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6516
6517 ctx.max_workgroup_size = 0;
6518 for (int i = 0; i < shader_count; ++i) {
6519 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6520 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6521 shaders[i]));
6522 }
6523
6524 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6525 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6526
6527 ctx.abi.inputs = &ctx.inputs[0];
6528 ctx.abi.emit_outputs = handle_shader_outputs_post;
6529 ctx.abi.load_ssbo = radv_load_ssbo;
6530 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6531 ctx.abi.clamp_shadow_reference = false;
6532
6533 if (shader_count >= 2)
6534 ac_init_exec_full_mask(&ctx.ac);
6535
6536 if (ctx.ac.chip_class == GFX9 &&
6537 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6538 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6539
6540 for(int i = 0; i < shader_count; ++i) {
6541 ctx.stage = shaders[i]->info.stage;
6542 ctx.output_mask = 0;
6543 ctx.tess_outputs_written = 0;
6544 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6545 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6546
6547 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6548 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6549
6550 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6551 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6552 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6553 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6554 if (shader_info->info.vs.needs_instance_id) {
6555 ctx.shader_info->vs.vgpr_comp_cnt =
6556 MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
6557 }
6558 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6559 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6560 }
6561
6562 if (i)
6563 emit_barrier(&ctx);
6564
6565 ac_setup_rings(&ctx);
6566
6567 LLVMBasicBlockRef merge_block;
6568 if (shader_count >= 2) {
6569 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6570 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6571 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6572
6573 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6574 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6575 LLVMConstInt(ctx.ac.i32, 8, false), false);
6576 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6577 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6578 thread_id, count, "");
6579 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6580
6581 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6582 }
6583
6584 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6585 handle_fs_inputs(&ctx, shaders[i]);
6586 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6587 handle_vs_inputs(&ctx, shaders[i]);
6588 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6589 prepare_gs_input_vgprs(&ctx);
6590
6591 nir_foreach_variable(variable, &shaders[i]->outputs)
6592 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6593
6594 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6595
6596 if (shader_count >= 2) {
6597 LLVMBuildBr(ctx.ac.builder, merge_block);
6598 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6599 }
6600
6601 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6602 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6603 shaders[i]->info.cull_distance_array_size > 4;
6604 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6605 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6606 shaders[i]->info.gs.vertices_out;
6607 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6608 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6609 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6610 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6611 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6612 }
6613 }
6614
6615 LLVMBuildRetVoid(ctx.builder);
6616
6617 ac_llvm_finalize_module(&ctx);
6618
6619 if (shader_count == 1)
6620 ac_nir_eliminate_const_vs_outputs(&ctx);
6621
6622 return ctx.module;
6623 }
6624
6625 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6626 {
6627 unsigned *retval = (unsigned *)context;
6628 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6629 char *description = LLVMGetDiagInfoDescription(di);
6630
6631 if (severity == LLVMDSError) {
6632 *retval = 1;
6633 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6634 description);
6635 }
6636
6637 LLVMDisposeMessage(description);
6638 }
6639
6640 static unsigned ac_llvm_compile(LLVMModuleRef M,
6641 struct ac_shader_binary *binary,
6642 LLVMTargetMachineRef tm)
6643 {
6644 unsigned retval = 0;
6645 char *err;
6646 LLVMContextRef llvm_ctx;
6647 LLVMMemoryBufferRef out_buffer;
6648 unsigned buffer_size;
6649 const char *buffer_data;
6650 LLVMBool mem_err;
6651
6652 /* Setup Diagnostic Handler*/
6653 llvm_ctx = LLVMGetModuleContext(M);
6654
6655 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6656 &retval);
6657
6658 /* Compile IR*/
6659 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6660 &err, &out_buffer);
6661
6662 /* Process Errors/Warnings */
6663 if (mem_err) {
6664 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6665 free(err);
6666 retval = 1;
6667 goto out;
6668 }
6669
6670 /* Extract Shader Code*/
6671 buffer_size = LLVMGetBufferSize(out_buffer);
6672 buffer_data = LLVMGetBufferStart(out_buffer);
6673
6674 ac_elf_read(buffer_data, buffer_size, binary);
6675
6676 /* Clean up */
6677 LLVMDisposeMemoryBuffer(out_buffer);
6678
6679 out:
6680 return retval;
6681 }
6682
6683 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6684 LLVMModuleRef llvm_module,
6685 struct ac_shader_binary *binary,
6686 struct ac_shader_config *config,
6687 struct ac_shader_variant_info *shader_info,
6688 gl_shader_stage stage,
6689 bool dump_shader, bool supports_spill)
6690 {
6691 if (dump_shader)
6692 ac_dump_module(llvm_module);
6693
6694 memset(binary, 0, sizeof(*binary));
6695 int v = ac_llvm_compile(llvm_module, binary, tm);
6696 if (v) {
6697 fprintf(stderr, "compile failed\n");
6698 }
6699
6700 if (dump_shader)
6701 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6702
6703 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6704
6705 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6706 LLVMDisposeModule(llvm_module);
6707 LLVMContextDispose(ctx);
6708
6709 if (stage == MESA_SHADER_FRAGMENT) {
6710 shader_info->num_input_vgprs = 0;
6711 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6712 shader_info->num_input_vgprs += 2;
6713 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6714 shader_info->num_input_vgprs += 2;
6715 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6716 shader_info->num_input_vgprs += 2;
6717 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6718 shader_info->num_input_vgprs += 3;
6719 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6720 shader_info->num_input_vgprs += 2;
6721 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6722 shader_info->num_input_vgprs += 2;
6723 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6724 shader_info->num_input_vgprs += 2;
6725 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6726 shader_info->num_input_vgprs += 1;
6727 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6728 shader_info->num_input_vgprs += 1;
6729 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6730 shader_info->num_input_vgprs += 1;
6731 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6732 shader_info->num_input_vgprs += 1;
6733 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6734 shader_info->num_input_vgprs += 1;
6735 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6736 shader_info->num_input_vgprs += 1;
6737 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6738 shader_info->num_input_vgprs += 1;
6739 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6740 shader_info->num_input_vgprs += 1;
6741 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6742 shader_info->num_input_vgprs += 1;
6743 }
6744 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6745
6746 /* +3 for scratch wave offset and VCC */
6747 config->num_sgprs = MAX2(config->num_sgprs,
6748 shader_info->num_input_sgprs + 3);
6749 }
6750
6751 static void
6752 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
6753 {
6754 switch (nir->info.stage) {
6755 case MESA_SHADER_COMPUTE:
6756 for (int i = 0; i < 3; ++i)
6757 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6758 break;
6759 case MESA_SHADER_FRAGMENT:
6760 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6761 break;
6762 case MESA_SHADER_GEOMETRY:
6763 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6764 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6765 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6766 shader_info->gs.invocations = nir->info.gs.invocations;
6767 break;
6768 case MESA_SHADER_TESS_EVAL:
6769 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6770 shader_info->tes.spacing = nir->info.tess.spacing;
6771 shader_info->tes.ccw = nir->info.tess.ccw;
6772 shader_info->tes.point_mode = nir->info.tess.point_mode;
6773 shader_info->tes.as_es = options->key.tes.as_es;
6774 break;
6775 case MESA_SHADER_TESS_CTRL:
6776 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6777 break;
6778 case MESA_SHADER_VERTEX:
6779 shader_info->vs.as_es = options->key.vs.as_es;
6780 shader_info->vs.as_ls = options->key.vs.as_ls;
6781 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6782 if (options->key.vs.as_ls)
6783 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6784 break;
6785 default:
6786 break;
6787 }
6788 }
6789
6790 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6791 struct ac_shader_binary *binary,
6792 struct ac_shader_config *config,
6793 struct ac_shader_variant_info *shader_info,
6794 struct nir_shader *const *nir,
6795 int nir_count,
6796 const struct ac_nir_compiler_options *options,
6797 bool dump_shader)
6798 {
6799
6800 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
6801 options);
6802
6803 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
6804 for (int i = 0; i < nir_count; ++i)
6805 ac_fill_shader_info(shader_info, nir[i], options);
6806 }
6807
6808 static void
6809 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6810 {
6811 LLVMValueRef args[9];
6812 args[0] = ctx->gsvs_ring;
6813 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->ac.i32, 4, false), "");
6814 args[3] = ctx->ac.i32_0;
6815 args[4] = ctx->ac.i32_1; /* OFFEN */
6816 args[5] = ctx->ac.i32_0; /* IDXEN */
6817 args[6] = ctx->ac.i32_1; /* GLC */
6818 args[7] = ctx->ac.i32_1; /* SLC */
6819 args[8] = ctx->ac.i32_0; /* TFE */
6820
6821 int idx = 0;
6822
6823 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6824 int length = 4;
6825 int slot = idx;
6826 int slot_inc = 1;
6827 if (!(ctx->output_mask & (1ull << i)))
6828 continue;
6829
6830 if (i == VARYING_SLOT_CLIP_DIST0) {
6831 /* unpack clip and cull from a single set of slots */
6832 length = ctx->num_output_clips + ctx->num_output_culls;
6833 if (length > 4)
6834 slot_inc = 2;
6835 }
6836
6837 for (unsigned j = 0; j < length; j++) {
6838 LLVMValueRef value;
6839 args[2] = LLVMConstInt(ctx->ac.i32,
6840 (slot * 4 + j) *
6841 ctx->gs_max_out_vertices * 16 * 4, false);
6842
6843 value = ac_build_intrinsic(&ctx->ac,
6844 "llvm.SI.buffer.load.dword.i32.i32",
6845 ctx->ac.i32, args, 9,
6846 AC_FUNC_ATTR_READONLY |
6847 AC_FUNC_ATTR_LEGACY);
6848
6849 LLVMBuildStore(ctx->builder,
6850 ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6851 }
6852 idx += slot_inc;
6853 }
6854 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6855 }
6856
6857 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6858 struct nir_shader *geom_shader,
6859 struct ac_shader_binary *binary,
6860 struct ac_shader_config *config,
6861 struct ac_shader_variant_info *shader_info,
6862 const struct ac_nir_compiler_options *options,
6863 bool dump_shader)
6864 {
6865 struct nir_to_llvm_context ctx = {0};
6866 ctx.context = LLVMContextCreate();
6867 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6868 ctx.options = options;
6869 ctx.shader_info = shader_info;
6870
6871 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class);
6872 ctx.ac.module = ctx.module;
6873
6874 ctx.is_gs_copy_shader = true;
6875 LLVMSetTarget(ctx.module, "amdgcn--");
6876 setup_types(&ctx);
6877
6878 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6879 ctx.ac.builder = ctx.builder;
6880 ctx.stage = MESA_SHADER_VERTEX;
6881
6882 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
6883
6884 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6885 ac_setup_rings(&ctx);
6886
6887 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6888 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6889
6890 struct ac_nir_context nir_ctx = {};
6891 nir_ctx.ac = ctx.ac;
6892 nir_ctx.abi = &ctx.abi;
6893
6894 nir_ctx.nctx = &ctx;
6895 ctx.nir = &nir_ctx;
6896
6897 nir_foreach_variable(variable, &geom_shader->outputs) {
6898 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
6899 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6900 }
6901
6902 ac_gs_copy_shader_emit(&ctx);
6903
6904 ctx.nir = NULL;
6905
6906 LLVMBuildRetVoid(ctx.builder);
6907
6908 ac_llvm_finalize_module(&ctx);
6909
6910 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6911 MESA_SHADER_VERTEX,
6912 dump_shader, options->supports_spill);
6913 }