projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv/ac: eliminate unused vertex shader outputs. (v2)
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 #include "ac_exp_param.h"
35
36 enum radeon_llvm_calling_convention {
37 RADEON_LLVM_AMDGPU_VS = 87,
38 RADEON_LLVM_AMDGPU_GS = 88,
39 RADEON_LLVM_AMDGPU_PS = 89,
40 RADEON_LLVM_AMDGPU_CS = 90,
41 };
42
43 #define CONST_ADDR_SPACE 2
44 #define LOCAL_ADDR_SPACE 3
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 enum desc_type {
50 DESC_IMAGE,
51 DESC_FMASK,
52 DESC_SAMPLER,
53 DESC_BUFFER,
54 };
55
56 struct nir_to_llvm_context {
57 struct ac_llvm_context ac;
58 const struct ac_nir_compiler_options *options;
59 struct ac_shader_variant_info *shader_info;
60
61 LLVMContextRef context;
62 LLVMModuleRef module;
63 LLVMBuilderRef builder;
64 LLVMValueRef main_function;
65
66 struct hash_table *defs;
67 struct hash_table *phis;
68
69 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
70 LLVMValueRef ring_offsets;
71 LLVMValueRef push_constants;
72 LLVMValueRef num_work_groups;
73 LLVMValueRef workgroup_ids;
74 LLVMValueRef local_invocation_ids;
75 LLVMValueRef tg_size;
76
77 LLVMValueRef vertex_buffers;
78 LLVMValueRef base_vertex;
79 LLVMValueRef start_instance;
80 LLVMValueRef draw_index;
81 LLVMValueRef vertex_id;
82 LLVMValueRef rel_auto_id;
83 LLVMValueRef vs_prim_id;
84 LLVMValueRef instance_id;
85 LLVMValueRef ls_out_layout;
86 LLVMValueRef es2gs_offset;
87
88 LLVMValueRef tcs_offchip_layout;
89 LLVMValueRef tcs_out_offsets;
90 LLVMValueRef tcs_out_layout;
91 LLVMValueRef tcs_in_layout;
92 LLVMValueRef oc_lds;
93 LLVMValueRef tess_factor_offset;
94 LLVMValueRef tcs_patch_id;
95 LLVMValueRef tcs_rel_ids;
96 LLVMValueRef tes_rel_patch_id;
97 LLVMValueRef tes_patch_id;
98 LLVMValueRef tes_u;
99 LLVMValueRef tes_v;
100
101 LLVMValueRef gsvs_ring_stride;
102 LLVMValueRef gsvs_num_entries;
103 LLVMValueRef gs2vs_offset;
104 LLVMValueRef gs_wave_id;
105 LLVMValueRef gs_vtx_offset[6];
106 LLVMValueRef gs_prim_id, gs_invocation_id;
107
108 LLVMValueRef esgs_ring;
109 LLVMValueRef gsvs_ring;
110 LLVMValueRef hs_ring_tess_offchip;
111 LLVMValueRef hs_ring_tess_factor;
112
113 LLVMValueRef prim_mask;
114 LLVMValueRef sample_pos_offset;
115 LLVMValueRef persp_sample, persp_center, persp_centroid;
116 LLVMValueRef linear_sample, linear_center, linear_centroid;
117 LLVMValueRef front_face;
118 LLVMValueRef ancillary;
119 LLVMValueRef sample_coverage;
120 LLVMValueRef frag_pos[4];
121
122 LLVMBasicBlockRef continue_block;
123 LLVMBasicBlockRef break_block;
124
125 LLVMTypeRef i1;
126 LLVMTypeRef i8;
127 LLVMTypeRef i16;
128 LLVMTypeRef i32;
129 LLVMTypeRef i64;
130 LLVMTypeRef v2i32;
131 LLVMTypeRef v3i32;
132 LLVMTypeRef v4i32;
133 LLVMTypeRef v8i32;
134 LLVMTypeRef f64;
135 LLVMTypeRef f32;
136 LLVMTypeRef f16;
137 LLVMTypeRef v2f32;
138 LLVMTypeRef v4f32;
139 LLVMTypeRef v16i8;
140 LLVMTypeRef voidt;
141
142 LLVMValueRef i1true;
143 LLVMValueRef i1false;
144 LLVMValueRef i32zero;
145 LLVMValueRef i32one;
146 LLVMValueRef f32zero;
147 LLVMValueRef f32one;
148 LLVMValueRef v4f32empty;
149
150 unsigned uniform_md_kind;
151 LLVMValueRef empty_md;
152 gl_shader_stage stage;
153
154 LLVMValueRef lds;
155 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
156 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
157
158 LLVMValueRef shared_memory;
159 uint64_t input_mask;
160 uint64_t output_mask;
161 int num_locals;
162 LLVMValueRef *locals;
163 bool has_ddxy;
164 uint8_t num_output_clips;
165 uint8_t num_output_culls;
166
167 bool has_ds_bpermute;
168
169 bool is_gs_copy_shader;
170 LLVMValueRef gs_next_vertex;
171 unsigned gs_max_out_vertices;
172
173 unsigned tes_primitive_mode;
174 uint64_t tess_outputs_written;
175 uint64_t tess_patch_outputs_written;
176 };
177
178 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
179 nir_deref_var *deref,
180 enum desc_type desc_type);
181 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
182 {
183 return (index * 4) + chan;
184 }
185
186 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
187 {
188 /* handle patch indices separate */
189 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
190 return 0;
191 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
192 return 1;
193 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
194 return 2 + (slot - VARYING_SLOT_PATCH0);
195
196 if (slot == VARYING_SLOT_POS)
197 return 0;
198 if (slot == VARYING_SLOT_PSIZ)
199 return 1;
200 if (slot == VARYING_SLOT_CLIP_DIST0)
201 return 2;
202 /* 3 is reserved for clip dist as well */
203 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
204 return 4 + (slot - VARYING_SLOT_VAR0);
205 unreachable("illegal slot in get unique index\n");
206 }
207
208 static unsigned llvm_get_type_size(LLVMTypeRef type)
209 {
210 LLVMTypeKind kind = LLVMGetTypeKind(type);
211
212 switch (kind) {
213 case LLVMIntegerTypeKind:
214 return LLVMGetIntTypeWidth(type) / 8;
215 case LLVMFloatTypeKind:
216 return 4;
217 case LLVMPointerTypeKind:
218 return 8;
219 case LLVMVectorTypeKind:
220 return LLVMGetVectorSize(type) *
221 llvm_get_type_size(LLVMGetElementType(type));
222 default:
223 assert(0);
224 return 0;
225 }
226 }
227
228 static void set_llvm_calling_convention(LLVMValueRef func,
229 gl_shader_stage stage)
230 {
231 enum radeon_llvm_calling_convention calling_conv;
232
233 switch (stage) {
234 case MESA_SHADER_VERTEX:
235 case MESA_SHADER_TESS_CTRL:
236 case MESA_SHADER_TESS_EVAL:
237 calling_conv = RADEON_LLVM_AMDGPU_VS;
238 break;
239 case MESA_SHADER_GEOMETRY:
240 calling_conv = RADEON_LLVM_AMDGPU_GS;
241 break;
242 case MESA_SHADER_FRAGMENT:
243 calling_conv = RADEON_LLVM_AMDGPU_PS;
244 break;
245 case MESA_SHADER_COMPUTE:
246 calling_conv = RADEON_LLVM_AMDGPU_CS;
247 break;
248 default:
249 unreachable("Unhandle shader type");
250 }
251
252 LLVMSetFunctionCallConv(func, calling_conv);
253 }
254
255 static LLVMValueRef
256 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
257 LLVMBuilderRef builder, LLVMTypeRef *return_types,
258 unsigned num_return_elems, LLVMTypeRef *param_types,
259 unsigned param_count, unsigned array_params_mask,
260 unsigned sgpr_params, bool unsafe_math)
261 {
262 LLVMTypeRef main_function_type, ret_type;
263 LLVMBasicBlockRef main_function_body;
264
265 if (num_return_elems)
266 ret_type = LLVMStructTypeInContext(ctx, return_types,
267 num_return_elems, true);
268 else
269 ret_type = LLVMVoidTypeInContext(ctx);
270
271 /* Setup the function */
272 main_function_type =
273 LLVMFunctionType(ret_type, param_types, param_count, 0);
274 LLVMValueRef main_function =
275 LLVMAddFunction(module, "main", main_function_type);
276 main_function_body =
277 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
278 LLVMPositionBuilderAtEnd(builder, main_function_body);
279
280 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
281 for (unsigned i = 0; i < sgpr_params; ++i) {
282 if (array_params_mask & (1 << i)) {
283 LLVMValueRef P = LLVMGetParam(main_function, i);
284 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
285 ac_add_attr_dereferenceable(P, UINT64_MAX);
286 }
287 else {
288 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
289 }
290 }
291
292 if (unsafe_math) {
293 /* These were copied from some LLVM test. */
294 LLVMAddTargetDependentFunctionAttr(main_function,
295 "less-precise-fpmad",
296 "true");
297 LLVMAddTargetDependentFunctionAttr(main_function,
298 "no-infs-fp-math",
299 "true");
300 LLVMAddTargetDependentFunctionAttr(main_function,
301 "no-nans-fp-math",
302 "true");
303 LLVMAddTargetDependentFunctionAttr(main_function,
304 "unsafe-fp-math",
305 "true");
306 }
307 return main_function;
308 }
309
310 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
311 {
312 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
313 CONST_ADDR_SPACE);
314 }
315
316 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
317 int idx,
318 LLVMTypeRef type)
319 {
320 LLVMValueRef offset;
321 LLVMValueRef ptr;
322 int addr_space;
323
324 offset = LLVMConstInt(ctx->i32, idx * 16, false);
325
326 ptr = ctx->shared_memory;
327 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
328 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
329 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
330 return ptr;
331 }
332
333 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
334 {
335 if (t == ctx->f16 || t == ctx->i16)
336 return ctx->i16;
337 else if (t == ctx->f32 || t == ctx->i32)
338 return ctx->i32;
339 else if (t == ctx->f64 || t == ctx->i64)
340 return ctx->i64;
341 else
342 unreachable("Unhandled integer size");
343 }
344
345 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
346 {
347 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
348 LLVMTypeRef elem_type = LLVMGetElementType(t);
349 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
350 LLVMGetVectorSize(t));
351 }
352 return to_integer_type_scalar(ctx, t);
353 }
354
355 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
356 {
357 LLVMTypeRef type = LLVMTypeOf(v);
358 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
359 }
360
361 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
362 {
363 if (t == ctx->i16 || t == ctx->f16)
364 return ctx->f16;
365 else if (t == ctx->i32 || t == ctx->f32)
366 return ctx->f32;
367 else if (t == ctx->i64 || t == ctx->f64)
368 return ctx->f64;
369 else
370 unreachable("Unhandled float size");
371 }
372
373 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
374 {
375 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
376 LLVMTypeRef elem_type = LLVMGetElementType(t);
377 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
378 LLVMGetVectorSize(t));
379 }
380 return to_float_type_scalar(ctx, t);
381 }
382
383 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
384 {
385 LLVMTypeRef type = LLVMTypeOf(v);
386 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
387 }
388
389 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
390 {
391 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
392 type = LLVMGetElementType(type);
393
394 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
395 return LLVMGetIntTypeWidth(type);
396
397 if (type == ctx->f16)
398 return 16;
399 if (type == ctx->f32)
400 return 32;
401 if (type == ctx->f64)
402 return 64;
403
404 unreachable("Unhandled type kind in get_elem_bits");
405 }
406
407 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
408 LLVMValueRef param, unsigned rshift,
409 unsigned bitwidth)
410 {
411 LLVMValueRef value = param;
412 if (rshift)
413 value = LLVMBuildLShr(ctx->builder, value,
414 LLVMConstInt(ctx->i32, rshift, false), "");
415
416 if (rshift + bitwidth < 32) {
417 unsigned mask = (1 << bitwidth) - 1;
418 value = LLVMBuildAnd(ctx->builder, value,
419 LLVMConstInt(ctx->i32, mask, false), "");
420 }
421 return value;
422 }
423
424 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
425 {
426 switch (ctx->stage) {
427 case MESA_SHADER_TESS_CTRL:
428 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
429 case MESA_SHADER_TESS_EVAL:
430 return ctx->tes_rel_patch_id;
431 break;
432 default:
433 unreachable("Illegal stage");
434 }
435 }
436
437 /* Tessellation shaders pass outputs to the next shader using LDS.
438 *
439 * LS outputs = TCS inputs
440 * TCS outputs = TES inputs
441 *
442 * The LDS layout is:
443 * - TCS inputs for patch 0
444 * - TCS inputs for patch 1
445 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
446 * - ...
447 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
448 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
449 * - TCS outputs for patch 1
450 * - Per-patch TCS outputs for patch 1
451 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
452 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
453 * - ...
454 *
455 * All three shaders VS(LS), TCS, TES share the same LDS space.
456 */
457 static LLVMValueRef
458 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
459 {
460 if (ctx->stage == MESA_SHADER_VERTEX)
461 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
462 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
463 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
464 else {
465 assert(0);
466 return NULL;
467 }
468 }
469
470 static LLVMValueRef
471 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
472 {
473 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
474 }
475
476 static LLVMValueRef
477 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
478 {
479 return LLVMBuildMul(ctx->builder,
480 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
481 LLVMConstInt(ctx->i32, 4, false), "");
482 }
483
484 static LLVMValueRef
485 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
486 {
487 return LLVMBuildMul(ctx->builder,
488 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
489 LLVMConstInt(ctx->i32, 4, false), "");
490 }
491
492 static LLVMValueRef
493 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
494 {
495 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
496 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
497
498 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
499 }
500
501 static LLVMValueRef
502 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
503 {
504 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
505 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
506 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
507
508 return LLVMBuildAdd(ctx->builder, patch0_offset,
509 LLVMBuildMul(ctx->builder, patch_stride,
510 rel_patch_id, ""),
511 "");
512 }
513
514 static LLVMValueRef
515 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
516 {
517 LLVMValueRef patch0_patch_data_offset =
518 get_tcs_out_patch0_patch_data_offset(ctx);
519 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
520 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
521
522 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
523 LLVMBuildMul(ctx->builder, patch_stride,
524 rel_patch_id, ""),
525 "");
526 }
527
528 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
529 {
530 ud_info->sgpr_idx = sgpr_idx;
531 ud_info->num_sgprs = num_sgprs;
532 ud_info->indirect = false;
533 ud_info->indirect_offset = 0;
534 }
535
536 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
537 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
538 {
539 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
540 }
541
542
543 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
544 uint32_t indirect_offset)
545 {
546 ud_info->sgpr_idx = sgpr_idx;
547 ud_info->num_sgprs = num_sgprs;
548 ud_info->indirect = true;
549 ud_info->indirect_offset = indirect_offset;
550 }
551
552 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
553 {
554 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
555 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
556 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
557 "tess_lds");
558 }
559
560 struct user_sgpr_info {
561 bool need_ring_offsets;
562 uint8_t sgpr_count;
563 bool indirect_all_descriptor_sets;
564 };
565
566 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
567 struct user_sgpr_info *user_sgpr_info)
568 {
569 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
570
571 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
572 if (ctx->stage == MESA_SHADER_GEOMETRY ||
573 ctx->stage == MESA_SHADER_VERTEX ||
574 ctx->stage == MESA_SHADER_TESS_CTRL ||
575 ctx->stage == MESA_SHADER_TESS_EVAL ||
576 ctx->is_gs_copy_shader)
577 user_sgpr_info->need_ring_offsets = true;
578
579 if (ctx->stage == MESA_SHADER_FRAGMENT &&
580 ctx->shader_info->info.ps.needs_sample_positions)
581 user_sgpr_info->need_ring_offsets = true;
582
583 /* 2 user sgprs will nearly always be allocated for scratch/rings */
584 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
585 user_sgpr_info->sgpr_count += 2;
586 }
587
588 switch (ctx->stage) {
589 case MESA_SHADER_COMPUTE:
590 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
591 break;
592 case MESA_SHADER_FRAGMENT:
593 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
594 break;
595 case MESA_SHADER_VERTEX:
596 if (!ctx->is_gs_copy_shader) {
597 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
598 if (ctx->shader_info->info.vs.needs_draw_id) {
599 user_sgpr_info->sgpr_count += 3;
600 } else {
601 user_sgpr_info->sgpr_count += 2;
602 }
603 }
604 if (ctx->options->key.vs.as_ls)
605 user_sgpr_info->sgpr_count++;
606 break;
607 case MESA_SHADER_TESS_CTRL:
608 user_sgpr_info->sgpr_count += 4;
609 break;
610 case MESA_SHADER_TESS_EVAL:
611 user_sgpr_info->sgpr_count += 1;
612 break;
613 case MESA_SHADER_GEOMETRY:
614 user_sgpr_info->sgpr_count += 2;
615 break;
616 default:
617 break;
618 }
619
620 if (ctx->shader_info->info.needs_push_constants)
621 user_sgpr_info->sgpr_count += 2;
622
623 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
624 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
625 user_sgpr_info->sgpr_count += 2;
626 user_sgpr_info->indirect_all_descriptor_sets = true;
627 } else {
628 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
629 }
630 }
631
632 static void create_function(struct nir_to_llvm_context *ctx)
633 {
634 LLVMTypeRef arg_types[23];
635 unsigned arg_idx = 0;
636 unsigned array_params_mask = 0;
637 unsigned sgpr_count = 0, user_sgpr_count;
638 unsigned i;
639 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
640 unsigned user_sgpr_idx;
641 struct user_sgpr_info user_sgpr_info;
642
643 allocate_user_sgprs(ctx, &user_sgpr_info);
644 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
645 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* address of rings */
646 }
647
648 /* 1 for each descriptor set */
649 if (!user_sgpr_info.indirect_all_descriptor_sets) {
650 for (unsigned i = 0; i < num_sets; ++i) {
651 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
652 array_params_mask |= (1 << arg_idx);
653 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
654 }
655 }
656 } else {
657 array_params_mask |= (1 << arg_idx);
658 arg_types[arg_idx++] = const_array(const_array(ctx->i8, 1024 * 1024), 32);
659 }
660
661 if (ctx->shader_info->info.needs_push_constants) {
662 /* 1 for push constants and dynamic descriptors */
663 array_params_mask |= (1 << arg_idx);
664 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
665 }
666
667 switch (ctx->stage) {
668 case MESA_SHADER_COMPUTE:
669 if (ctx->shader_info->info.cs.grid_components_used)
670 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used); /* grid size */
671 user_sgpr_count = arg_idx;
672 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
673 arg_types[arg_idx++] = ctx->i32;
674 sgpr_count = arg_idx;
675
676 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
677 break;
678 case MESA_SHADER_VERTEX:
679 if (!ctx->is_gs_copy_shader) {
680 if (ctx->shader_info->info.vs.has_vertex_buffers)
681 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
682 arg_types[arg_idx++] = ctx->i32; // base vertex
683 arg_types[arg_idx++] = ctx->i32; // start instance
684 if (ctx->shader_info->info.vs.needs_draw_id)
685 arg_types[arg_idx++] = ctx->i32; // draw index
686 }
687 user_sgpr_count = arg_idx;
688 if (ctx->options->key.vs.as_es)
689 arg_types[arg_idx++] = ctx->i32; //es2gs offset
690 else if (ctx->options->key.vs.as_ls) {
691 arg_types[arg_idx++] = ctx->i32; //ls out layout
692 user_sgpr_count++;
693 }
694 sgpr_count = arg_idx;
695 arg_types[arg_idx++] = ctx->i32; // vertex id
696 if (!ctx->is_gs_copy_shader) {
697 arg_types[arg_idx++] = ctx->i32; // rel auto id
698 arg_types[arg_idx++] = ctx->i32; // vs prim id
699 arg_types[arg_idx++] = ctx->i32; // instance id
700 }
701 break;
702 case MESA_SHADER_TESS_CTRL:
703 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
704 arg_types[arg_idx++] = ctx->i32; // tcs out offsets
705 arg_types[arg_idx++] = ctx->i32; // tcs out layout
706 arg_types[arg_idx++] = ctx->i32; // tcs in layout
707 user_sgpr_count = arg_idx;
708 arg_types[arg_idx++] = ctx->i32; // param oc lds
709 arg_types[arg_idx++] = ctx->i32; // tess factor offset
710 sgpr_count = arg_idx;
711 arg_types[arg_idx++] = ctx->i32; // patch id
712 arg_types[arg_idx++] = ctx->i32; // rel ids;
713 break;
714 case MESA_SHADER_TESS_EVAL:
715 arg_types[arg_idx++] = ctx->i32; // tcs offchip layout
716 user_sgpr_count = arg_idx;
717 if (ctx->options->key.tes.as_es) {
718 arg_types[arg_idx++] = ctx->i32; // OC LDS
719 arg_types[arg_idx++] = ctx->i32; //
720 arg_types[arg_idx++] = ctx->i32; // es2gs offset
721 } else {
722 arg_types[arg_idx++] = ctx->i32; //
723 arg_types[arg_idx++] = ctx->i32; // OC LDS
724 }
725 sgpr_count = arg_idx;
726 arg_types[arg_idx++] = ctx->f32; // tes_u
727 arg_types[arg_idx++] = ctx->f32; // tes_v
728 arg_types[arg_idx++] = ctx->i32; // tes rel patch id
729 arg_types[arg_idx++] = ctx->i32; // tes patch id
730 break;
731 case MESA_SHADER_GEOMETRY:
732 arg_types[arg_idx++] = ctx->i32; // gsvs stride
733 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
734 user_sgpr_count = arg_idx;
735 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
736 arg_types[arg_idx++] = ctx->i32; // wave id
737 sgpr_count = arg_idx;
738 arg_types[arg_idx++] = ctx->i32; // vtx0
739 arg_types[arg_idx++] = ctx->i32; // vtx1
740 arg_types[arg_idx++] = ctx->i32; // prim id
741 arg_types[arg_idx++] = ctx->i32; // vtx2
742 arg_types[arg_idx++] = ctx->i32; // vtx3
743 arg_types[arg_idx++] = ctx->i32; // vtx4
744 arg_types[arg_idx++] = ctx->i32; // vtx5
745 arg_types[arg_idx++] = ctx->i32; // GS instance id
746 break;
747 case MESA_SHADER_FRAGMENT:
748 if (ctx->shader_info->info.ps.needs_sample_positions)
749 arg_types[arg_idx++] = ctx->i32; /* sample position offset */
750 user_sgpr_count = arg_idx;
751 arg_types[arg_idx++] = ctx->i32; /* prim mask */
752 sgpr_count = arg_idx;
753 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
754 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
755 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
756 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
757 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
758 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
759 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
760 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
761 arg_types[arg_idx++] = ctx->f32; /* pos x float */
762 arg_types[arg_idx++] = ctx->f32; /* pos y float */
763 arg_types[arg_idx++] = ctx->f32; /* pos z float */
764 arg_types[arg_idx++] = ctx->f32; /* pos w float */
765 arg_types[arg_idx++] = ctx->i32; /* front face */
766 arg_types[arg_idx++] = ctx->i32; /* ancillary */
767 arg_types[arg_idx++] = ctx->i32; /* sample coverage */
768 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
769 break;
770 default:
771 unreachable("Shader stage not implemented");
772 }
773
774 ctx->main_function = create_llvm_function(
775 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
776 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
777 set_llvm_calling_convention(ctx->main_function, ctx->stage);
778
779 ctx->shader_info->num_input_sgprs = 0;
780 ctx->shader_info->num_input_vgprs = 0;
781
782 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
783 for (i = 0; i < user_sgpr_count; i++)
784 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
785
786 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
787 for (; i < sgpr_count; i++)
788 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
789
790 if (ctx->stage != MESA_SHADER_FRAGMENT)
791 for (; i < arg_idx; ++i)
792 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
793
794 arg_idx = 0;
795 user_sgpr_idx = 0;
796
797 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
798 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
799 user_sgpr_idx += 2;
800 if (ctx->options->supports_spill) {
801 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
802 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
803 NULL, 0, AC_FUNC_ATTR_READNONE);
804 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
805 const_array(ctx->v16i8, 16), "");
806 } else
807 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
808 }
809
810 if (!user_sgpr_info.indirect_all_descriptor_sets) {
811 for (unsigned i = 0; i < num_sets; ++i) {
812 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
813 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
814 user_sgpr_idx += 2;
815 ctx->descriptor_sets[i] =
816 LLVMGetParam(ctx->main_function, arg_idx++);
817 } else
818 ctx->descriptor_sets[i] = NULL;
819 }
820 } else {
821 uint32_t desc_sgpr_idx = user_sgpr_idx;
822 LLVMValueRef desc_sets = LLVMGetParam(ctx->main_function, arg_idx++);
823 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, user_sgpr_idx, 2);
824 user_sgpr_idx += 2;
825
826 for (unsigned i = 0; i < num_sets; ++i) {
827 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
828 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
829 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
830
831 } else
832 ctx->descriptor_sets[i] = NULL;
833 }
834 ctx->shader_info->need_indirect_descriptor_sets = true;
835 }
836
837 if (ctx->shader_info->info.needs_push_constants) {
838 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
839 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
840 user_sgpr_idx += 2;
841 }
842
843 switch (ctx->stage) {
844 case MESA_SHADER_COMPUTE:
845 if (ctx->shader_info->info.cs.grid_components_used) {
846 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
847 user_sgpr_idx += ctx->shader_info->info.cs.grid_components_used;
848 ctx->num_work_groups =
849 LLVMGetParam(ctx->main_function, arg_idx++);
850 }
851 ctx->workgroup_ids =
852 LLVMGetParam(ctx->main_function, arg_idx++);
853 ctx->tg_size =
854 LLVMGetParam(ctx->main_function, arg_idx++);
855 ctx->local_invocation_ids =
856 LLVMGetParam(ctx->main_function, arg_idx++);
857 break;
858 case MESA_SHADER_VERTEX:
859 if (!ctx->is_gs_copy_shader) {
860 if (ctx->shader_info->info.vs.has_vertex_buffers) {
861 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
862 user_sgpr_idx += 2;
863 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
864 }
865 unsigned vs_num = 2;
866 if (ctx->shader_info->info.vs.needs_draw_id)
867 vs_num++;
868
869 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, vs_num);
870 user_sgpr_idx += vs_num;
871
872 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
873 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
874 if (ctx->shader_info->info.vs.needs_draw_id)
875 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
876 }
877 if (ctx->options->key.vs.as_es)
878 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
879 else if (ctx->options->key.vs.as_ls) {
880 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, user_sgpr_idx, 1);
881 user_sgpr_idx += 1;
882 ctx->ls_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
883 }
884 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
885 if (!ctx->is_gs_copy_shader) {
886 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
887 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
888 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
889 }
890 if (ctx->options->key.vs.as_ls)
891 declare_tess_lds(ctx);
892 break;
893 case MESA_SHADER_TESS_CTRL:
894 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, user_sgpr_idx, 4);
895 user_sgpr_idx += 4;
896 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
897 ctx->tcs_out_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
898 ctx->tcs_out_layout = LLVMGetParam(ctx->main_function, arg_idx++);
899 ctx->tcs_in_layout = LLVMGetParam(ctx->main_function, arg_idx++);
900 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
901 ctx->tess_factor_offset = LLVMGetParam(ctx->main_function, arg_idx++);
902 ctx->tcs_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
903 ctx->tcs_rel_ids = LLVMGetParam(ctx->main_function, arg_idx++);
904
905 declare_tess_lds(ctx);
906 break;
907 case MESA_SHADER_TESS_EVAL:
908 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, user_sgpr_idx, 1);
909 user_sgpr_idx += 1;
910 ctx->tcs_offchip_layout = LLVMGetParam(ctx->main_function, arg_idx++);
911 if (ctx->options->key.tes.as_es) {
912 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
913 arg_idx++;
914 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
915 } else {
916 arg_idx++;
917 ctx->oc_lds = LLVMGetParam(ctx->main_function, arg_idx++);
918 }
919 ctx->tes_u = LLVMGetParam(ctx->main_function, arg_idx++);
920 ctx->tes_v = LLVMGetParam(ctx->main_function, arg_idx++);
921 ctx->tes_rel_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
922 ctx->tes_patch_id = LLVMGetParam(ctx->main_function, arg_idx++);
923 break;
924 case MESA_SHADER_GEOMETRY:
925 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
926 user_sgpr_idx += 2;
927 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
928 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
929 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
930 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
931 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
932 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
933 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
934 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
935 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
936 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
937 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
938 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
939 break;
940 case MESA_SHADER_FRAGMENT:
941 if (ctx->shader_info->info.ps.needs_sample_positions) {
942 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, user_sgpr_idx, 1);
943 user_sgpr_idx += 1;
944 ctx->sample_pos_offset = LLVMGetParam(ctx->main_function, arg_idx++);
945 }
946 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
947 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
948 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
949 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
950 arg_idx++;
951 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
952 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
953 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
954 arg_idx++; /* line stipple */
955 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
956 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
957 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
958 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
959 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
960 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
961 ctx->sample_coverage = LLVMGetParam(ctx->main_function, arg_idx++);
962 break;
963 default:
964 unreachable("Shader stage not implemented");
965 }
966 }
967
968 static void setup_types(struct nir_to_llvm_context *ctx)
969 {
970 LLVMValueRef args[4];
971
972 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
973 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
974 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
975 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
976 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
977 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
978 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
979 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
980 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
981 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
982 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
983 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
984 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
985 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
986 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
987 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
988
989 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
990 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
991 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
992 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
993 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
994 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
995
996 args[0] = ctx->f32zero;
997 args[1] = ctx->f32zero;
998 args[2] = ctx->f32zero;
999 args[3] = ctx->f32one;
1000 ctx->v4f32empty = LLVMConstVector(args, 4);
1001
1002 ctx->uniform_md_kind =
1003 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
1004 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
1005
1006 args[0] = LLVMConstReal(ctx->f32, 2.5);
1007 }
1008
1009 static int get_llvm_num_components(LLVMValueRef value)
1010 {
1011 LLVMTypeRef type = LLVMTypeOf(value);
1012 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1013 ? LLVMGetVectorSize(type)
1014 : 1;
1015 return num_components;
1016 }
1017
1018 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
1019 LLVMValueRef value,
1020 int index)
1021 {
1022 int count = get_llvm_num_components(value);
1023
1024 assert(index < count);
1025 if (count == 1)
1026 return value;
1027
1028 return LLVMBuildExtractElement(ctx->builder, value,
1029 LLVMConstInt(ctx->i32, index, false), "");
1030 }
1031
1032 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
1033 LLVMValueRef value, unsigned count)
1034 {
1035 unsigned num_components = get_llvm_num_components(value);
1036 if (count == num_components)
1037 return value;
1038
1039 LLVMValueRef masks[] = {
1040 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1041 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1042
1043 if (count == 1)
1044 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1045 "");
1046
1047 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1048 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1049 }
1050
1051 static void
1052 build_store_values_extended(struct nir_to_llvm_context *ctx,
1053 LLVMValueRef *values,
1054 unsigned value_count,
1055 unsigned value_stride,
1056 LLVMValueRef vec)
1057 {
1058 LLVMBuilderRef builder = ctx->builder;
1059 unsigned i;
1060
1061 if (value_count == 1) {
1062 LLVMBuildStore(builder, vec, values[0]);
1063 return;
1064 }
1065
1066 for (i = 0; i < value_count; i++) {
1067 LLVMValueRef ptr = values[i * value_stride];
1068 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
1069 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1070 LLVMBuildStore(builder, value, ptr);
1071 }
1072 }
1073
1074 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
1075 nir_ssa_def *def)
1076 {
1077 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
1078 if (def->num_components > 1) {
1079 type = LLVMVectorType(type, def->num_components);
1080 }
1081 return type;
1082 }
1083
1084 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1085 {
1086 assert(src.is_ssa);
1087 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1088 return (LLVMValueRef)entry->data;
1089 }
1090
1091
1092 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1093 struct nir_block *b)
1094 {
1095 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1096 return (LLVMBasicBlockRef)entry->data;
1097 }
1098
1099 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1100 nir_alu_src src,
1101 unsigned num_components)
1102 {
1103 LLVMValueRef value = get_src(ctx, src.src);
1104 bool need_swizzle = false;
1105
1106 assert(value);
1107 LLVMTypeRef type = LLVMTypeOf(value);
1108 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1109 ? LLVMGetVectorSize(type)
1110 : 1;
1111
1112 for (unsigned i = 0; i < num_components; ++i) {
1113 assert(src.swizzle[i] < src_components);
1114 if (src.swizzle[i] != i)
1115 need_swizzle = true;
1116 }
1117
1118 if (need_swizzle || num_components != src_components) {
1119 LLVMValueRef masks[] = {
1120 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1121 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1122 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1123 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1124
1125 if (src_components > 1 && num_components == 1) {
1126 value = LLVMBuildExtractElement(ctx->builder, value,
1127 masks[0], "");
1128 } else if (src_components == 1 && num_components > 1) {
1129 LLVMValueRef values[] = {value, value, value, value};
1130 value = ac_build_gather_values(&ctx->ac, values, num_components);
1131 } else {
1132 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1133 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1134 swizzle, "");
1135 }
1136 }
1137 assert(!src.negate);
1138 assert(!src.abs);
1139 return value;
1140 }
1141
1142 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
1143 LLVMIntPredicate pred, LLVMValueRef src0,
1144 LLVMValueRef src1)
1145 {
1146 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1147 return LLVMBuildSelect(ctx->builder, result,
1148 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1149 LLVMConstInt(ctx->i32, 0, false), "");
1150 }
1151
1152 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
1153 LLVMRealPredicate pred, LLVMValueRef src0,
1154 LLVMValueRef src1)
1155 {
1156 LLVMValueRef result;
1157 src0 = to_float(ctx, src0);
1158 src1 = to_float(ctx, src1);
1159 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1160 return LLVMBuildSelect(ctx->builder, result,
1161 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1162 LLVMConstInt(ctx->i32, 0, false), "");
1163 }
1164
1165 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
1166 const char *intrin,
1167 LLVMTypeRef result_type,
1168 LLVMValueRef src0)
1169 {
1170 char name[64];
1171 LLVMValueRef params[] = {
1172 to_float(ctx, src0),
1173 };
1174
1175 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1176 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1177 }
1178
1179 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
1180 const char *intrin,
1181 LLVMTypeRef result_type,
1182 LLVMValueRef src0, LLVMValueRef src1)
1183 {
1184 char name[64];
1185 LLVMValueRef params[] = {
1186 to_float(ctx, src0),
1187 to_float(ctx, src1),
1188 };
1189
1190 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1191 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1192 }
1193
1194 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
1195 const char *intrin,
1196 LLVMTypeRef result_type,
1197 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1198 {
1199 char name[64];
1200 LLVMValueRef params[] = {
1201 to_float(ctx, src0),
1202 to_float(ctx, src1),
1203 to_float(ctx, src2),
1204 };
1205
1206 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
1207 return ac_build_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1208 }
1209
1210 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
1211 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1212 {
1213 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1214 ctx->i32zero, "");
1215 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1216 }
1217
1218 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
1219 LLVMValueRef src0)
1220 {
1221 LLVMValueRef params[2] = {
1222 src0,
1223
1224 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1225 * add special code to check for x=0. The reason is that
1226 * the LLVM behavior for x=0 is different from what we
1227 * need here.
1228 *
1229 * The hardware already implements the correct behavior.
1230 */
1231 LLVMConstInt(ctx->i32, 1, false),
1232 };
1233 return ac_build_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1234 }
1235
1236 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
1237 LLVMValueRef src0)
1238 {
1239 return ac_build_imsb(&ctx->ac, src0, ctx->i32);
1240 }
1241
1242 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
1243 LLVMValueRef src0)
1244 {
1245 return ac_build_umsb(&ctx->ac, src0, ctx->i32);
1246 }
1247
1248 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
1249 LLVMIntPredicate pred,
1250 LLVMValueRef src0, LLVMValueRef src1)
1251 {
1252 return LLVMBuildSelect(ctx->builder,
1253 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1254 src0,
1255 src1, "");
1256
1257 }
1258 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
1259 LLVMValueRef src0)
1260 {
1261 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1262 LLVMBuildNeg(ctx->builder, src0, ""));
1263 }
1264
1265 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1266 LLVMValueRef src0)
1267 {
1268 LLVMValueRef cmp, val;
1269
1270 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1271 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1272 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1273 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1274 return val;
1275 }
1276
1277 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1278 LLVMValueRef src0)
1279 {
1280 LLVMValueRef cmp, val;
1281
1282 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1283 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1284 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1285 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1286 return val;
1287 }
1288
1289 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1290 LLVMValueRef src0)
1291 {
1292 const char *intr = "llvm.floor.f32";
1293 LLVMValueRef fsrc0 = to_float(ctx, src0);
1294 LLVMValueRef params[] = {
1295 fsrc0,
1296 };
1297 LLVMValueRef floor = ac_build_intrinsic(&ctx->ac, intr,
1298 ctx->f32, params, 1,
1299 AC_FUNC_ATTR_READNONE);
1300 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1301 }
1302
1303 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1304 const char *intrin,
1305 LLVMValueRef src0, LLVMValueRef src1)
1306 {
1307 LLVMTypeRef ret_type;
1308 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1309 LLVMValueRef res;
1310 LLVMValueRef params[] = { src0, src1 };
1311 ret_type = LLVMStructTypeInContext(ctx->context, types,
1312 2, true);
1313
1314 res = ac_build_intrinsic(&ctx->ac, intrin, ret_type,
1315 params, 2, AC_FUNC_ATTR_READNONE);
1316
1317 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1318 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1319 return res;
1320 }
1321
1322 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1323 LLVMValueRef src0)
1324 {
1325 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1326 }
1327
1328 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1329 LLVMValueRef src0, LLVMValueRef src1)
1330 {
1331 LLVMValueRef dst64, result;
1332 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1333 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1334
1335 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1336 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1337 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1338 return result;
1339 }
1340
1341 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1342 LLVMValueRef src0, LLVMValueRef src1)
1343 {
1344 LLVMValueRef dst64, result;
1345 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1346 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1347
1348 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1349 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1350 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1351 return result;
1352 }
1353
1354 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1355 bool is_signed,
1356 LLVMValueRef srcs[3])
1357 {
1358 LLVMValueRef result;
1359 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1360
1361 result = ac_build_bfe(&ctx->ac, srcs[0], srcs[1], srcs[2], is_signed);
1362 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1363 return result;
1364 }
1365
1366 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1367 LLVMValueRef src0, LLVMValueRef src1,
1368 LLVMValueRef src2, LLVMValueRef src3)
1369 {
1370 LLVMValueRef bfi_args[3], result;
1371
1372 bfi_args[0] = LLVMBuildShl(ctx->builder,
1373 LLVMBuildSub(ctx->builder,
1374 LLVMBuildShl(ctx->builder,
1375 ctx->i32one,
1376 src3, ""),
1377 ctx->i32one, ""),
1378 src2, "");
1379 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1380 bfi_args[2] = src0;
1381
1382 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1383
1384 /* Calculate:
1385 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1386 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1387 */
1388 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1389 LLVMBuildAnd(ctx->builder, bfi_args[0],
1390 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1391
1392 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1393 return result;
1394 }
1395
1396 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1397 LLVMValueRef src0)
1398 {
1399 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1400 int i;
1401 LLVMValueRef comp[2];
1402
1403 src0 = to_float(ctx, src0);
1404 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1405 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1406 for (i = 0; i < 2; i++) {
1407 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1408 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1409 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1410 }
1411
1412 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1413 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1414
1415 return comp[0];
1416 }
1417
1418 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1419 LLVMValueRef src0)
1420 {
1421 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1422 LLVMValueRef temps[2], result, val;
1423 int i;
1424
1425 for (i = 0; i < 2; i++) {
1426 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1427 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1428 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1429 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1430 }
1431
1432 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1433 ctx->i32zero, "");
1434 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1435 ctx->i32one, "");
1436 return result;
1437 }
1438
1439 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1440 nir_op op,
1441 LLVMValueRef src0)
1442 {
1443 unsigned mask;
1444 int idx;
1445 LLVMValueRef result;
1446 ctx->has_ddxy = true;
1447
1448 if (!ctx->lds && !ctx->has_ds_bpermute)
1449 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1450 LLVMArrayType(ctx->i32, 64),
1451 "ddxy_lds", LOCAL_ADDR_SPACE);
1452
1453 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1454 mask = AC_TID_MASK_LEFT;
1455 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1456 mask = AC_TID_MASK_TOP;
1457 else
1458 mask = AC_TID_MASK_TOP_LEFT;
1459
1460 /* for DDX we want to next X pixel, DDY next Y pixel. */
1461 if (op == nir_op_fddx_fine ||
1462 op == nir_op_fddx_coarse ||
1463 op == nir_op_fddx)
1464 idx = 1;
1465 else
1466 idx = 2;
1467
1468 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1469 mask, idx, ctx->lds,
1470 src0);
1471 return result;
1472 }
1473
1474 /*
1475 * this takes an I,J coordinate pair,
1476 * and works out the X and Y derivatives.
1477 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1478 */
1479 static LLVMValueRef emit_ddxy_interp(
1480 struct nir_to_llvm_context *ctx,
1481 LLVMValueRef interp_ij)
1482 {
1483 LLVMValueRef result[4], a;
1484 unsigned i;
1485
1486 for (i = 0; i < 2; i++) {
1487 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1488 LLVMConstInt(ctx->i32, i, false), "");
1489 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1490 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1491 }
1492 return ac_build_gather_values(&ctx->ac, result, 4);
1493 }
1494
1495 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1496 {
1497 LLVMValueRef src[4], result = NULL;
1498 unsigned num_components = instr->dest.dest.ssa.num_components;
1499 unsigned src_components;
1500 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1501
1502 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1503 switch (instr->op) {
1504 case nir_op_vec2:
1505 case nir_op_vec3:
1506 case nir_op_vec4:
1507 src_components = 1;
1508 break;
1509 case nir_op_pack_half_2x16:
1510 src_components = 2;
1511 break;
1512 case nir_op_unpack_half_2x16:
1513 src_components = 1;
1514 break;
1515 default:
1516 src_components = num_components;
1517 break;
1518 }
1519 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1520 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1521
1522 switch (instr->op) {
1523 case nir_op_fmov:
1524 case nir_op_imov:
1525 result = src[0];
1526 break;
1527 case nir_op_fneg:
1528 src[0] = to_float(ctx, src[0]);
1529 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1530 break;
1531 case nir_op_ineg:
1532 result = LLVMBuildNeg(ctx->builder, src[0], "");
1533 break;
1534 case nir_op_inot:
1535 result = LLVMBuildNot(ctx->builder, src[0], "");
1536 break;
1537 case nir_op_iadd:
1538 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1539 break;
1540 case nir_op_fadd:
1541 src[0] = to_float(ctx, src[0]);
1542 src[1] = to_float(ctx, src[1]);
1543 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1544 break;
1545 case nir_op_fsub:
1546 src[0] = to_float(ctx, src[0]);
1547 src[1] = to_float(ctx, src[1]);
1548 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1549 break;
1550 case nir_op_isub:
1551 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1552 break;
1553 case nir_op_imul:
1554 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1555 break;
1556 case nir_op_imod:
1557 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1558 break;
1559 case nir_op_umod:
1560 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1561 break;
1562 case nir_op_fmod:
1563 src[0] = to_float(ctx, src[0]);
1564 src[1] = to_float(ctx, src[1]);
1565 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1566 result = emit_intrin_1f_param(ctx, "llvm.floor",
1567 to_float_type(ctx, def_type), result);
1568 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1569 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1570 break;
1571 case nir_op_frem:
1572 src[0] = to_float(ctx, src[0]);
1573 src[1] = to_float(ctx, src[1]);
1574 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1575 break;
1576 case nir_op_irem:
1577 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1578 break;
1579 case nir_op_idiv:
1580 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1581 break;
1582 case nir_op_udiv:
1583 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1584 break;
1585 case nir_op_fmul:
1586 src[0] = to_float(ctx, src[0]);
1587 src[1] = to_float(ctx, src[1]);
1588 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1589 break;
1590 case nir_op_fdiv:
1591 src[0] = to_float(ctx, src[0]);
1592 src[1] = to_float(ctx, src[1]);
1593 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1594 break;
1595 case nir_op_frcp:
1596 src[0] = to_float(ctx, src[0]);
1597 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1598 break;
1599 case nir_op_iand:
1600 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1601 break;
1602 case nir_op_ior:
1603 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1604 break;
1605 case nir_op_ixor:
1606 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1607 break;
1608 case nir_op_ishl:
1609 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1610 break;
1611 case nir_op_ishr:
1612 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1613 break;
1614 case nir_op_ushr:
1615 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1616 break;
1617 case nir_op_ilt:
1618 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1619 break;
1620 case nir_op_ine:
1621 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1622 break;
1623 case nir_op_ieq:
1624 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1625 break;
1626 case nir_op_ige:
1627 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1628 break;
1629 case nir_op_ult:
1630 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1631 break;
1632 case nir_op_uge:
1633 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1634 break;
1635 case nir_op_feq:
1636 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1637 break;
1638 case nir_op_fne:
1639 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1640 break;
1641 case nir_op_flt:
1642 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1643 break;
1644 case nir_op_fge:
1645 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1646 break;
1647 case nir_op_fabs:
1648 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1649 to_float_type(ctx, def_type), src[0]);
1650 break;
1651 case nir_op_iabs:
1652 result = emit_iabs(ctx, src[0]);
1653 break;
1654 case nir_op_imax:
1655 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1656 break;
1657 case nir_op_imin:
1658 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1659 break;
1660 case nir_op_umax:
1661 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1662 break;
1663 case nir_op_umin:
1664 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1665 break;
1666 case nir_op_isign:
1667 result = emit_isign(ctx, src[0]);
1668 break;
1669 case nir_op_fsign:
1670 src[0] = to_float(ctx, src[0]);
1671 result = emit_fsign(ctx, src[0]);
1672 break;
1673 case nir_op_ffloor:
1674 result = emit_intrin_1f_param(ctx, "llvm.floor",
1675 to_float_type(ctx, def_type), src[0]);
1676 break;
1677 case nir_op_ftrunc:
1678 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1679 to_float_type(ctx, def_type), src[0]);
1680 break;
1681 case nir_op_fceil:
1682 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1683 to_float_type(ctx, def_type), src[0]);
1684 break;
1685 case nir_op_fround_even:
1686 result = emit_intrin_1f_param(ctx, "llvm.rint",
1687 to_float_type(ctx, def_type),src[0]);
1688 break;
1689 case nir_op_ffract:
1690 result = emit_ffract(ctx, src[0]);
1691 break;
1692 case nir_op_fsin:
1693 result = emit_intrin_1f_param(ctx, "llvm.sin",
1694 to_float_type(ctx, def_type), src[0]);
1695 break;
1696 case nir_op_fcos:
1697 result = emit_intrin_1f_param(ctx, "llvm.cos",
1698 to_float_type(ctx, def_type), src[0]);
1699 break;
1700 case nir_op_fsqrt:
1701 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1702 to_float_type(ctx, def_type), src[0]);
1703 break;
1704 case nir_op_fexp2:
1705 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1706 to_float_type(ctx, def_type), src[0]);
1707 break;
1708 case nir_op_flog2:
1709 result = emit_intrin_1f_param(ctx, "llvm.log2",
1710 to_float_type(ctx, def_type), src[0]);
1711 break;
1712 case nir_op_frsq:
1713 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1714 to_float_type(ctx, def_type), src[0]);
1715 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1716 break;
1717 case nir_op_fpow:
1718 result = emit_intrin_2f_param(ctx, "llvm.pow",
1719 to_float_type(ctx, def_type), src[0], src[1]);
1720 break;
1721 case nir_op_fmax:
1722 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1723 to_float_type(ctx, def_type), src[0], src[1]);
1724 break;
1725 case nir_op_fmin:
1726 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1727 to_float_type(ctx, def_type), src[0], src[1]);
1728 break;
1729 case nir_op_ffma:
1730 result = emit_intrin_3f_param(ctx, "llvm.fma",
1731 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1732 break;
1733 case nir_op_ibitfield_extract:
1734 result = emit_bitfield_extract(ctx, true, src);
1735 break;
1736 case nir_op_ubitfield_extract:
1737 result = emit_bitfield_extract(ctx, false, src);
1738 break;
1739 case nir_op_bitfield_insert:
1740 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1741 break;
1742 case nir_op_bitfield_reverse:
1743 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1744 break;
1745 case nir_op_bit_count:
1746 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1747 break;
1748 case nir_op_vec2:
1749 case nir_op_vec3:
1750 case nir_op_vec4:
1751 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1752 src[i] = to_integer(ctx, src[i]);
1753 result = ac_build_gather_values(&ctx->ac, src, num_components);
1754 break;
1755 case nir_op_f2i32:
1756 case nir_op_f2i64:
1757 src[0] = to_float(ctx, src[0]);
1758 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1759 break;
1760 case nir_op_f2u32:
1761 case nir_op_f2u64:
1762 src[0] = to_float(ctx, src[0]);
1763 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1764 break;
1765 case nir_op_i2f32:
1766 case nir_op_i2f64:
1767 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1768 break;
1769 case nir_op_u2f32:
1770 case nir_op_u2f64:
1771 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1772 break;
1773 case nir_op_f2f64:
1774 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1775 break;
1776 case nir_op_f2f32:
1777 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1778 break;
1779 case nir_op_u2u32:
1780 case nir_op_u2u64:
1781 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1782 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1783 else
1784 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1785 break;
1786 case nir_op_i2i32:
1787 case nir_op_i2i64:
1788 if (get_elem_bits(ctx, LLVMTypeOf(src[0])) < get_elem_bits(ctx, def_type))
1789 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1790 else
1791 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1792 break;
1793 case nir_op_bcsel:
1794 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1795 break;
1796 case nir_op_find_lsb:
1797 result = emit_find_lsb(ctx, src[0]);
1798 break;
1799 case nir_op_ufind_msb:
1800 result = emit_ufind_msb(ctx, src[0]);
1801 break;
1802 case nir_op_ifind_msb:
1803 result = emit_ifind_msb(ctx, src[0]);
1804 break;
1805 case nir_op_uadd_carry:
1806 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1807 break;
1808 case nir_op_usub_borrow:
1809 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1810 break;
1811 case nir_op_b2f:
1812 result = emit_b2f(ctx, src[0]);
1813 break;
1814 case nir_op_fquantize2f16:
1815 src[0] = to_float(ctx, src[0]);
1816 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1817 /* need to convert back up to f32 */
1818 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1819 break;
1820 case nir_op_umul_high:
1821 result = emit_umul_high(ctx, src[0], src[1]);
1822 break;
1823 case nir_op_imul_high:
1824 result = emit_imul_high(ctx, src[0], src[1]);
1825 break;
1826 case nir_op_pack_half_2x16:
1827 result = emit_pack_half_2x16(ctx, src[0]);
1828 break;
1829 case nir_op_unpack_half_2x16:
1830 result = emit_unpack_half_2x16(ctx, src[0]);
1831 break;
1832 case nir_op_fddx:
1833 case nir_op_fddy:
1834 case nir_op_fddx_fine:
1835 case nir_op_fddy_fine:
1836 case nir_op_fddx_coarse:
1837 case nir_op_fddy_coarse:
1838 result = emit_ddxy(ctx, instr->op, src[0]);
1839 break;
1840 default:
1841 fprintf(stderr, "Unknown NIR alu instr: ");
1842 nir_print_instr(&instr->instr, stderr);
1843 fprintf(stderr, "\n");
1844 abort();
1845 }
1846
1847 if (result) {
1848 assert(instr->dest.dest.is_ssa);
1849 result = to_integer(ctx, result);
1850 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1851 result);
1852 }
1853 }
1854
1855 static void visit_load_const(struct nir_to_llvm_context *ctx,
1856 nir_load_const_instr *instr)
1857 {
1858 LLVMValueRef values[4], value = NULL;
1859 LLVMTypeRef element_type =
1860 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1861
1862 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1863 switch (instr->def.bit_size) {
1864 case 32:
1865 values[i] = LLVMConstInt(element_type,
1866 instr->value.u32[i], false);
1867 break;
1868 case 64:
1869 values[i] = LLVMConstInt(element_type,
1870 instr->value.u64[i], false);
1871 break;
1872 default:
1873 fprintf(stderr,
1874 "unsupported nir load_const bit_size: %d\n",
1875 instr->def.bit_size);
1876 abort();
1877 }
1878 }
1879 if (instr->def.num_components > 1) {
1880 value = LLVMConstVector(values, instr->def.num_components);
1881 } else
1882 value = values[0];
1883
1884 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1885 }
1886
1887 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1888 LLVMTypeRef type)
1889 {
1890 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1891 return LLVMBuildBitCast(ctx->builder, ptr,
1892 LLVMPointerType(type, addr_space), "");
1893 }
1894
1895 static LLVMValueRef
1896 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1897 {
1898 LLVMValueRef size =
1899 LLVMBuildExtractElement(ctx->builder, descriptor,
1900 LLVMConstInt(ctx->i32, 2, false), "");
1901
1902 /* VI only */
1903 if (ctx->options->chip_class >= VI && in_elements) {
1904 /* On VI, the descriptor contains the size in bytes,
1905 * but TXQ must return the size in elements.
1906 * The stride is always non-zero for resources using TXQ.
1907 */
1908 LLVMValueRef stride =
1909 LLVMBuildExtractElement(ctx->builder, descriptor,
1910 LLVMConstInt(ctx->i32, 1, false), "");
1911 stride = LLVMBuildLShr(ctx->builder, stride,
1912 LLVMConstInt(ctx->i32, 16, false), "");
1913 stride = LLVMBuildAnd(ctx->builder, stride,
1914 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1915
1916 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1917 }
1918 return size;
1919 }
1920
1921 /**
1922 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1923 * intrinsic names).
1924 */
1925 static void build_int_type_name(
1926 LLVMTypeRef type,
1927 char *buf, unsigned bufsize)
1928 {
1929 assert(bufsize >= 6);
1930
1931 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1932 snprintf(buf, bufsize, "v%ui32",
1933 LLVMGetVectorSize(type));
1934 else
1935 strcpy(buf, "i32");
1936 }
1937
1938 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1939 struct ac_image_args *args,
1940 nir_tex_instr *instr)
1941 {
1942 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1943 LLVMValueRef coord = args->addr;
1944 LLVMValueRef half_texel[2];
1945 LLVMValueRef compare_cube_wa;
1946 LLVMValueRef result;
1947 int c;
1948 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1949
1950 //TODO Rect
1951 {
1952 struct ac_image_args txq_args = { 0 };
1953
1954 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1955 txq_args.opcode = ac_image_get_resinfo;
1956 txq_args.dmask = 0xf;
1957 txq_args.addr = ctx->i32zero;
1958 txq_args.resource = args->resource;
1959 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1960
1961 for (c = 0; c < 2; c++) {
1962 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1963 LLVMConstInt(ctx->i32, c, false), "");
1964 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1965 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1966 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1967 LLVMConstReal(ctx->f32, -0.5), "");
1968 }
1969 }
1970
1971 LLVMValueRef orig_coords = args->addr;
1972
1973 for (c = 0; c < 2; c++) {
1974 LLVMValueRef tmp;
1975 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1976 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1977 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1978 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1979 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1980 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1981 }
1982
1983
1984 /*
1985 * Apparantly cube has issue with integer types that the workaround doesn't solve,
1986 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
1987 * workaround by sampling using a scaled type and converting.
1988 * This is taken from amdgpu-pro shaders.
1989 */
1990 /* NOTE this produces some ugly code compared to amdgpu-pro,
1991 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
1992 * and then reads them back. -pro generates two selects,
1993 * one s_cmp for the descriptor rewriting
1994 * one v_cmp for the coordinate and result changes.
1995 */
1996 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1997 LLVMValueRef tmp, tmp2;
1998
1999 /* workaround 8/8/8/8 uint/sint cube gather bug */
2000 /* first detect it then change to a scaled read and f2i */
2001 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
2002 tmp2 = tmp;
2003
2004 /* extract the DATA_FORMAT */
2005 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
2006 LLVMConstInt(ctx->i32, 6, false), false);
2007
2008 /* is the DATA_FORMAT == 8_8_8_8 */
2009 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2010
2011 if (stype == GLSL_TYPE_UINT)
2012 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2013 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2014 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2015 else
2016 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2017 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2018 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2019
2020 /* replace the NUM FORMAT in the descriptor */
2021 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2022 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2023
2024 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2025
2026 /* don't modify the coordinates for this case */
2027 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2028 }
2029 args->addr = coord;
2030 result = ac_build_image_opcode(&ctx->ac, args);
2031
2032 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2033 LLVMValueRef tmp, tmp2;
2034
2035 /* if the cube workaround is in place, f2i the result. */
2036 for (c = 0; c < 4; c++) {
2037 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2038 if (stype == GLSL_TYPE_UINT)
2039 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2040 else
2041 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2042 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2043 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2044 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2045 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2046 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2047 }
2048 }
2049 return result;
2050 }
2051
2052 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2053 nir_tex_instr *instr,
2054 bool lod_is_zero,
2055 struct ac_image_args *args)
2056 {
2057 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2058 return ac_build_buffer_load_format(&ctx->ac,
2059 args->resource,
2060 args->addr,
2061 LLVMConstInt(ctx->i32, 0, false),
2062 true);
2063 }
2064
2065 args->opcode = ac_image_sample;
2066 args->compare = instr->is_shadow;
2067
2068 switch (instr->op) {
2069 case nir_texop_txf:
2070 case nir_texop_txf_ms:
2071 case nir_texop_samples_identical:
2072 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2073 args->compare = false;
2074 args->offset = false;
2075 break;
2076 case nir_texop_txb:
2077 args->bias = true;
2078 break;
2079 case nir_texop_txl:
2080 if (lod_is_zero)
2081 args->level_zero = true;
2082 else
2083 args->lod = true;
2084 break;
2085 case nir_texop_txs:
2086 case nir_texop_query_levels:
2087 args->opcode = ac_image_get_resinfo;
2088 break;
2089 case nir_texop_tex:
2090 if (ctx->stage != MESA_SHADER_FRAGMENT)
2091 args->level_zero = true;
2092 break;
2093 case nir_texop_txd:
2094 args->deriv = true;
2095 break;
2096 case nir_texop_tg4:
2097 args->opcode = ac_image_gather4;
2098 args->level_zero = true;
2099 break;
2100 case nir_texop_lod:
2101 args->opcode = ac_image_get_lod;
2102 args->compare = false;
2103 args->offset = false;
2104 break;
2105 default:
2106 break;
2107 }
2108
2109 if (instr->op == nir_texop_tg4) {
2110 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2111 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2112 return radv_lower_gather4_integer(ctx, args, instr);
2113 }
2114 }
2115 return ac_build_image_opcode(&ctx->ac, args);
2116 }
2117
2118 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2119 nir_intrinsic_instr *instr)
2120 {
2121 LLVMValueRef index = get_src(ctx, instr->src[0]);
2122 unsigned desc_set = nir_intrinsic_desc_set(instr);
2123 unsigned binding = nir_intrinsic_binding(instr);
2124 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2125 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2126 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2127 unsigned base_offset = layout->binding[binding].offset;
2128 LLVMValueRef offset, stride;
2129
2130 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2131 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2132 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2133 layout->binding[binding].dynamic_offset_offset;
2134 desc_ptr = ctx->push_constants;
2135 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2136 stride = LLVMConstInt(ctx->i32, 16, false);
2137 } else
2138 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2139
2140 offset = LLVMConstInt(ctx->i32, base_offset, false);
2141 index = LLVMBuildMul(ctx->builder, index, stride, "");
2142 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2143
2144 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2145 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2146 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2147
2148 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2149 }
2150
2151 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2152 nir_intrinsic_instr *instr)
2153 {
2154 LLVMValueRef ptr, addr;
2155
2156 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2157 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2158
2159 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2160 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2161
2162 return LLVMBuildLoad(ctx->builder, ptr, "");
2163 }
2164
2165 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2166 nir_intrinsic_instr *instr)
2167 {
2168 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2169
2170 return get_buffer_size(ctx, desc, false);
2171 }
2172 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2173 nir_intrinsic_instr *instr)
2174 {
2175 const char *store_name;
2176 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2177 LLVMTypeRef data_type = ctx->f32;
2178 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
2179 int components_32bit = elem_size_mult * instr->num_components;
2180 unsigned writemask = nir_intrinsic_write_mask(instr);
2181 LLVMValueRef base_data, base_offset;
2182 LLVMValueRef params[6];
2183
2184 if (ctx->stage == MESA_SHADER_FRAGMENT)
2185 ctx->shader_info->fs.writes_memory = true;
2186
2187 params[1] = get_src(ctx, instr->src[1]);
2188 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2189 params[4] = ctx->i1false; /* glc */
2190 params[5] = ctx->i1false; /* slc */
2191
2192 if (components_32bit > 1)
2193 data_type = LLVMVectorType(ctx->f32, components_32bit);
2194
2195 base_data = to_float(ctx, src_data);
2196 base_data = trim_vector(ctx, base_data, instr->num_components);
2197 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2198 data_type, "");
2199 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2200 while (writemask) {
2201 int start, count;
2202 LLVMValueRef data;
2203 LLVMValueRef offset;
2204 LLVMValueRef tmp;
2205 u_bit_scan_consecutive_range(&writemask, &start, &count);
2206
2207 /* Due to an LLVM limitation, split 3-element writes
2208 * into a 2-element and a 1-element write. */
2209 if (count == 3) {
2210 writemask |= 1 << (start + 2);
2211 count = 2;
2212 }
2213
2214 start *= elem_size_mult;
2215 count *= elem_size_mult;
2216
2217 if (count > 4) {
2218 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2219 count = 4;
2220 }
2221
2222 if (count == 4) {
2223 store_name = "llvm.amdgcn.buffer.store.v4f32";
2224 data = base_data;
2225 } else if (count == 2) {
2226 tmp = LLVMBuildExtractElement(ctx->builder,
2227 base_data, LLVMConstInt(ctx->i32, start, false), "");
2228 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2229 ctx->i32zero, "");
2230
2231 tmp = LLVMBuildExtractElement(ctx->builder,
2232 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2233 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2234 ctx->i32one, "");
2235 store_name = "llvm.amdgcn.buffer.store.v2f32";
2236
2237 } else {
2238 assert(count == 1);
2239 if (get_llvm_num_components(base_data) > 1)
2240 data = LLVMBuildExtractElement(ctx->builder, base_data,
2241 LLVMConstInt(ctx->i32, start, false), "");
2242 else
2243 data = base_data;
2244 store_name = "llvm.amdgcn.buffer.store.f32";
2245 }
2246
2247 offset = base_offset;
2248 if (start != 0) {
2249 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2250 }
2251 params[0] = data;
2252 params[3] = offset;
2253 ac_build_intrinsic(&ctx->ac, store_name,
2254 ctx->voidt, params, 6, 0);
2255 }
2256 }
2257
2258 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2259 nir_intrinsic_instr *instr)
2260 {
2261 const char *name;
2262 LLVMValueRef params[6];
2263 int arg_count = 0;
2264 if (ctx->stage == MESA_SHADER_FRAGMENT)
2265 ctx->shader_info->fs.writes_memory = true;
2266
2267 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2268 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2269 }
2270 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2271 params[arg_count++] = get_src(ctx, instr->src[0]);
2272 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2273 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2274 params[arg_count++] = ctx->i1false; /* slc */
2275
2276 switch (instr->intrinsic) {
2277 case nir_intrinsic_ssbo_atomic_add:
2278 name = "llvm.amdgcn.buffer.atomic.add";
2279 break;
2280 case nir_intrinsic_ssbo_atomic_imin:
2281 name = "llvm.amdgcn.buffer.atomic.smin";
2282 break;
2283 case nir_intrinsic_ssbo_atomic_umin:
2284 name = "llvm.amdgcn.buffer.atomic.umin";
2285 break;
2286 case nir_intrinsic_ssbo_atomic_imax:
2287 name = "llvm.amdgcn.buffer.atomic.smax";
2288 break;
2289 case nir_intrinsic_ssbo_atomic_umax:
2290 name = "llvm.amdgcn.buffer.atomic.umax";
2291 break;
2292 case nir_intrinsic_ssbo_atomic_and:
2293 name = "llvm.amdgcn.buffer.atomic.and";
2294 break;
2295 case nir_intrinsic_ssbo_atomic_or:
2296 name = "llvm.amdgcn.buffer.atomic.or";
2297 break;
2298 case nir_intrinsic_ssbo_atomic_xor:
2299 name = "llvm.amdgcn.buffer.atomic.xor";
2300 break;
2301 case nir_intrinsic_ssbo_atomic_exchange:
2302 name = "llvm.amdgcn.buffer.atomic.swap";
2303 break;
2304 case nir_intrinsic_ssbo_atomic_comp_swap:
2305 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2306 break;
2307 default:
2308 abort();
2309 }
2310
2311 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2312 }
2313
2314 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2315 nir_intrinsic_instr *instr)
2316 {
2317 LLVMValueRef results[2];
2318 int load_components;
2319 int num_components = instr->num_components;
2320 if (instr->dest.ssa.bit_size == 64)
2321 num_components *= 2;
2322
2323 for (int i = 0; i < num_components; i += load_components) {
2324 load_components = MIN2(num_components - i, 4);
2325 const char *load_name;
2326 LLVMTypeRef data_type = ctx->f32;
2327 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2328 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2329
2330 if (load_components == 3)
2331 data_type = LLVMVectorType(ctx->f32, 4);
2332 else if (load_components > 1)
2333 data_type = LLVMVectorType(ctx->f32, load_components);
2334
2335 if (load_components >= 3)
2336 load_name = "llvm.amdgcn.buffer.load.v4f32";
2337 else if (load_components == 2)
2338 load_name = "llvm.amdgcn.buffer.load.v2f32";
2339 else if (load_components == 1)
2340 load_name = "llvm.amdgcn.buffer.load.f32";
2341 else
2342 unreachable("unhandled number of components");
2343
2344 LLVMValueRef params[] = {
2345 get_src(ctx, instr->src[0]),
2346 LLVMConstInt(ctx->i32, 0, false),
2347 offset,
2348 ctx->i1false,
2349 ctx->i1false,
2350 };
2351
2352 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2353
2354 }
2355
2356 LLVMValueRef ret = results[0];
2357 if (num_components > 4 || num_components == 3) {
2358 LLVMValueRef masks[] = {
2359 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2360 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2361 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2362 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2363 };
2364
2365 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2366 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2367 results[num_components > 4 ? 1 : 0], swizzle, "");
2368 }
2369
2370 return LLVMBuildBitCast(ctx->builder, ret,
2371 get_def_type(ctx, &instr->dest.ssa), "");
2372 }
2373
2374 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2375 nir_intrinsic_instr *instr)
2376 {
2377 LLVMValueRef results[8], ret;
2378 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2379 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2380 int num_components = instr->num_components;
2381
2382 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2383
2384 if (instr->dest.ssa.bit_size == 64)
2385 num_components *= 2;
2386
2387 for (unsigned i = 0; i < num_components; ++i) {
2388 LLVMValueRef params[] = {
2389 rsrc,
2390 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2391 offset, "")
2392 };
2393 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2394 params, 2,
2395 AC_FUNC_ATTR_READNONE |
2396 AC_FUNC_ATTR_LEGACY);
2397 }
2398
2399
2400 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2401 return LLVMBuildBitCast(ctx->builder, ret,
2402 get_def_type(ctx, &instr->dest.ssa), "");
2403 }
2404
2405 static void
2406 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2407 bool vs_in, unsigned *vertex_index_out,
2408 LLVMValueRef *vertex_index_ref,
2409 unsigned *const_out, LLVMValueRef *indir_out)
2410 {
2411 unsigned const_offset = 0;
2412 nir_deref *tail = &deref->deref;
2413 LLVMValueRef offset = NULL;
2414
2415 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2416 tail = tail->child;
2417 nir_deref_array *deref_array = nir_deref_as_array(tail);
2418 if (vertex_index_out)
2419 *vertex_index_out = deref_array->base_offset;
2420
2421 if (vertex_index_ref) {
2422 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2423 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2424 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2425 }
2426 *vertex_index_ref = vtx;
2427 }
2428 }
2429
2430 if (deref->var->data.compact) {
2431 assert(tail->child->deref_type == nir_deref_type_array);
2432 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2433 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2434 /* We always lower indirect dereferences for "compact" array vars. */
2435 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2436
2437 const_offset = deref_array->base_offset;
2438 goto out;
2439 }
2440
2441 while (tail->child != NULL) {
2442 const struct glsl_type *parent_type = tail->type;
2443 tail = tail->child;
2444
2445 if (tail->deref_type == nir_deref_type_array) {
2446 nir_deref_array *deref_array = nir_deref_as_array(tail);
2447 LLVMValueRef index, stride, local_offset;
2448 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2449
2450 const_offset += size * deref_array->base_offset;
2451 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2452 continue;
2453
2454 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2455 index = get_src(ctx, deref_array->indirect);
2456 stride = LLVMConstInt(ctx->i32, size, 0);
2457 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2458
2459 if (offset)
2460 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2461 else
2462 offset = local_offset;
2463 } else if (tail->deref_type == nir_deref_type_struct) {
2464 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2465
2466 for (unsigned i = 0; i < deref_struct->index; i++) {
2467 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2468 const_offset += glsl_count_attribute_slots(ft, vs_in);
2469 }
2470 } else
2471 unreachable("unsupported deref type");
2472
2473 }
2474 out:
2475 if (const_offset && offset)
2476 offset = LLVMBuildAdd(ctx->builder, offset,
2477 LLVMConstInt(ctx->i32, const_offset, 0),
2478 "");
2479
2480 *const_out = const_offset;
2481 *indir_out = offset;
2482 }
2483
2484 static LLVMValueRef
2485 lds_load(struct nir_to_llvm_context *ctx,
2486 LLVMValueRef dw_addr)
2487 {
2488 LLVMValueRef value;
2489 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2490 return value;
2491 }
2492
2493 static void
2494 lds_store(struct nir_to_llvm_context *ctx,
2495 LLVMValueRef dw_addr, LLVMValueRef value)
2496 {
2497 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2498 ac_build_indexed_store(&ctx->ac, ctx->lds,
2499 dw_addr, value);
2500 }
2501
2502 /* The offchip buffer layout for TCS->TES is
2503 *
2504 * - attribute 0 of patch 0 vertex 0
2505 * - attribute 0 of patch 0 vertex 1
2506 * - attribute 0 of patch 0 vertex 2
2507 * ...
2508 * - attribute 0 of patch 1 vertex 0
2509 * - attribute 0 of patch 1 vertex 1
2510 * ...
2511 * - attribute 1 of patch 0 vertex 0
2512 * - attribute 1 of patch 0 vertex 1
2513 * ...
2514 * - per patch attribute 0 of patch 0
2515 * - per patch attribute 0 of patch 1
2516 * ...
2517 *
2518 * Note that every attribute has 4 components.
2519 */
2520 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2521 LLVMValueRef vertex_index,
2522 LLVMValueRef param_index)
2523 {
2524 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2525 LLVMValueRef param_stride, constant16;
2526 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2527
2528 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2529 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2530 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2531 num_patches, "");
2532
2533 constant16 = LLVMConstInt(ctx->i32, 16, false);
2534 if (vertex_index) {
2535 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2536 vertices_per_patch, "");
2537
2538 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2539 vertex_index, "");
2540
2541 param_stride = total_vertices;
2542 } else {
2543 base_addr = rel_patch_id;
2544 param_stride = num_patches;
2545 }
2546
2547 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2548 LLVMBuildMul(ctx->builder, param_index,
2549 param_stride, ""), "");
2550
2551 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2552
2553 if (!vertex_index) {
2554 LLVMValueRef patch_data_offset =
2555 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2556
2557 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2558 patch_data_offset, "");
2559 }
2560 return base_addr;
2561 }
2562
2563 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2564 unsigned param,
2565 unsigned const_index,
2566 bool is_compact,
2567 LLVMValueRef vertex_index,
2568 LLVMValueRef indir_index)
2569 {
2570 LLVMValueRef param_index;
2571
2572 if (indir_index)
2573 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2574 indir_index, "");
2575 else {
2576 if (const_index && !is_compact)
2577 param += const_index;
2578 param_index = LLVMConstInt(ctx->i32, param, false);
2579 }
2580 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2581 }
2582
2583 static void
2584 mark_tess_output(struct nir_to_llvm_context *ctx,
2585 bool is_patch, uint32_t param)
2586
2587 {
2588 if (is_patch) {
2589 ctx->tess_patch_outputs_written |= (1ull << param);
2590 } else
2591 ctx->tess_outputs_written |= (1ull << param);
2592 }
2593
2594 static LLVMValueRef
2595 get_dw_address(struct nir_to_llvm_context *ctx,
2596 LLVMValueRef dw_addr,
2597 unsigned param,
2598 unsigned const_index,
2599 bool compact_const_index,
2600 LLVMValueRef vertex_index,
2601 LLVMValueRef stride,
2602 LLVMValueRef indir_index)
2603
2604 {
2605
2606 if (vertex_index) {
2607 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2608 LLVMBuildMul(ctx->builder,
2609 vertex_index,
2610 stride, ""), "");
2611 }
2612
2613 if (indir_index)
2614 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2615 LLVMBuildMul(ctx->builder, indir_index,
2616 LLVMConstInt(ctx->i32, 4, false), ""), "");
2617 else if (const_index && !compact_const_index)
2618 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2619 LLVMConstInt(ctx->i32, const_index, false), "");
2620
2621 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2622 LLVMConstInt(ctx->i32, param * 4, false), "");
2623
2624 if (const_index && compact_const_index)
2625 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2626 LLVMConstInt(ctx->i32, const_index, false), "");
2627 return dw_addr;
2628 }
2629
2630 static LLVMValueRef
2631 load_tcs_input(struct nir_to_llvm_context *ctx,
2632 nir_intrinsic_instr *instr)
2633 {
2634 LLVMValueRef dw_addr, stride;
2635 unsigned const_index;
2636 LLVMValueRef vertex_index;
2637 LLVMValueRef indir_index;
2638 unsigned param;
2639 LLVMValueRef value[4], result;
2640 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2641 const bool is_compact = instr->variables[0]->var->data.compact;
2642 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2643 radv_get_deref_offset(ctx, instr->variables[0],
2644 false, NULL, per_vertex ? &vertex_index : NULL,
2645 &const_index, &indir_index);
2646
2647 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2648 dw_addr = get_tcs_in_current_patch_offset(ctx);
2649 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2650 indir_index);
2651
2652 for (unsigned i = 0; i < instr->num_components; i++) {
2653 value[i] = lds_load(ctx, dw_addr);
2654 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2655 ctx->i32one, "");
2656 }
2657 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2658 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2659 return result;
2660 }
2661
2662 static LLVMValueRef
2663 load_tcs_output(struct nir_to_llvm_context *ctx,
2664 nir_intrinsic_instr *instr)
2665 {
2666 LLVMValueRef dw_addr, stride;
2667 LLVMValueRef value[4], result;
2668 LLVMValueRef vertex_index = NULL;
2669 LLVMValueRef indir_index = NULL;
2670 unsigned const_index = 0;
2671 unsigned param;
2672 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2673 const bool is_compact = instr->variables[0]->var->data.compact;
2674 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2675 radv_get_deref_offset(ctx, instr->variables[0],
2676 false, NULL, per_vertex ? &vertex_index : NULL,
2677 &const_index, &indir_index);
2678
2679 if (!instr->variables[0]->var->data.patch) {
2680 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2681 dw_addr = get_tcs_out_current_patch_offset(ctx);
2682 } else {
2683 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2684 }
2685
2686 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2687 indir_index);
2688
2689 for (unsigned i = 0; i < instr->num_components; i++) {
2690 value[i] = lds_load(ctx, dw_addr);
2691 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2692 ctx->i32one, "");
2693 }
2694 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2695 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2696 return result;
2697 }
2698
2699 static void
2700 store_tcs_output(struct nir_to_llvm_context *ctx,
2701 nir_intrinsic_instr *instr,
2702 LLVMValueRef src,
2703 unsigned writemask)
2704 {
2705 LLVMValueRef stride, dw_addr;
2706 LLVMValueRef buf_addr = NULL;
2707 LLVMValueRef vertex_index = NULL;
2708 LLVMValueRef indir_index = NULL;
2709 unsigned const_index = 0;
2710 unsigned param;
2711 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2712 const bool is_compact = instr->variables[0]->var->data.compact;
2713
2714 radv_get_deref_offset(ctx, instr->variables[0],
2715 false, NULL, per_vertex ? &vertex_index : NULL,
2716 &const_index, &indir_index);
2717
2718 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2719 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2720 is_compact && const_index > 3) {
2721 const_index -= 3;
2722 param++;
2723 }
2724
2725 if (!instr->variables[0]->var->data.patch) {
2726 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2727 dw_addr = get_tcs_out_current_patch_offset(ctx);
2728 } else {
2729 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2730 }
2731
2732 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2733
2734 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2735 indir_index);
2736 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2737 vertex_index, indir_index);
2738
2739 unsigned base = is_compact ? const_index : 0;
2740 for (unsigned chan = 0; chan < 8; chan++) {
2741 bool is_tess_factor = false;
2742 if (!(writemask & (1 << chan)))
2743 continue;
2744 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2745
2746 lds_store(ctx, dw_addr, value);
2747
2748 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2749 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2750 is_tess_factor = true;
2751
2752 if (!is_tess_factor && writemask != 0xF)
2753 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2754 buf_addr, ctx->oc_lds,
2755 4 * (base + chan), 1, 0, true, false);
2756
2757 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2758 ctx->i32one, "");
2759 }
2760
2761 if (writemask == 0xF) {
2762 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2763 buf_addr, ctx->oc_lds,
2764 (base * 4), 1, 0, true, false);
2765 }
2766 }
2767
2768 static LLVMValueRef
2769 load_tes_input(struct nir_to_llvm_context *ctx,
2770 nir_intrinsic_instr *instr)
2771 {
2772 LLVMValueRef buf_addr;
2773 LLVMValueRef result;
2774 LLVMValueRef vertex_index = NULL;
2775 LLVMValueRef indir_index = NULL;
2776 unsigned const_index = 0;
2777 unsigned param;
2778 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2779 const bool is_compact = instr->variables[0]->var->data.compact;
2780
2781 radv_get_deref_offset(ctx, instr->variables[0],
2782 false, NULL, per_vertex ? &vertex_index : NULL,
2783 &const_index, &indir_index);
2784 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2785 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2786 is_compact && const_index > 3) {
2787 const_index -= 3;
2788 param++;
2789 }
2790 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2791 is_compact, vertex_index, indir_index);
2792
2793 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2794 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true);
2795 result = trim_vector(ctx, result, instr->num_components);
2796 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2797 return result;
2798 }
2799
2800 static LLVMValueRef
2801 load_gs_input(struct nir_to_llvm_context *ctx,
2802 nir_intrinsic_instr *instr)
2803 {
2804 LLVMValueRef indir_index, vtx_offset;
2805 unsigned const_index;
2806 LLVMValueRef args[9];
2807 unsigned param, vtx_offset_param;
2808 LLVMValueRef value[4], result;
2809 unsigned vertex_index;
2810 radv_get_deref_offset(ctx, instr->variables[0],
2811 false, &vertex_index, NULL,
2812 &const_index, &indir_index);
2813 vtx_offset_param = vertex_index;
2814 assert(vtx_offset_param < 6);
2815 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2816 LLVMConstInt(ctx->i32, 4, false), "");
2817
2818 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2819 for (unsigned i = 0; i < instr->num_components; i++) {
2820
2821 args[0] = ctx->esgs_ring;
2822 args[1] = vtx_offset;
2823 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2824 args[3] = ctx->i32zero;
2825 args[4] = ctx->i32one; /* OFFEN */
2826 args[5] = ctx->i32zero; /* IDXEN */
2827 args[6] = ctx->i32one; /* GLC */
2828 args[7] = ctx->i32zero; /* SLC */
2829 args[8] = ctx->i32zero; /* TFE */
2830
2831 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2832 ctx->i32, args, 9,
2833 AC_FUNC_ATTR_READONLY |
2834 AC_FUNC_ATTR_LEGACY);
2835 }
2836 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2837
2838 return result;
2839 }
2840
2841 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2842 nir_intrinsic_instr *instr)
2843 {
2844 LLVMValueRef values[8];
2845 int idx = instr->variables[0]->var->data.driver_location;
2846 int ve = instr->dest.ssa.num_components;
2847 LLVMValueRef indir_index;
2848 LLVMValueRef ret;
2849 unsigned const_index;
2850 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2851 instr->variables[0]->var->data.mode == nir_var_shader_in;
2852 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2853 &const_index, &indir_index);
2854
2855 if (instr->dest.ssa.bit_size == 64)
2856 ve *= 2;
2857
2858 switch (instr->variables[0]->var->data.mode) {
2859 case nir_var_shader_in:
2860 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2861 return load_tcs_input(ctx, instr);
2862 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2863 return load_tes_input(ctx, instr);
2864 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2865 return load_gs_input(ctx, instr);
2866 }
2867 for (unsigned chan = 0; chan < ve; chan++) {
2868 if (indir_index) {
2869 unsigned count = glsl_count_attribute_slots(
2870 instr->variables[0]->var->type,
2871 ctx->stage == MESA_SHADER_VERTEX);
2872 count -= chan / 4;
2873 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2874 &ctx->ac, ctx->inputs + idx + chan, count,
2875 4, false);
2876
2877 values[chan] = LLVMBuildExtractElement(ctx->builder,
2878 tmp_vec,
2879 indir_index, "");
2880 } else
2881 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2882 }
2883 break;
2884 case nir_var_local:
2885 for (unsigned chan = 0; chan < ve; chan++) {
2886 if (indir_index) {
2887 unsigned count = glsl_count_attribute_slots(
2888 instr->variables[0]->var->type, false);
2889 count -= chan / 4;
2890 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2891 &ctx->ac, ctx->locals + idx + chan, count,
2892 4, true);
2893
2894 values[chan] = LLVMBuildExtractElement(ctx->builder,
2895 tmp_vec,
2896 indir_index, "");
2897 } else {
2898 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2899 }
2900 }
2901 break;
2902 case nir_var_shader_out:
2903 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2904 return load_tcs_output(ctx, instr);
2905 for (unsigned chan = 0; chan < ve; chan++) {
2906 if (indir_index) {
2907 unsigned count = glsl_count_attribute_slots(
2908 instr->variables[0]->var->type, false);
2909 count -= chan / 4;
2910 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2911 &ctx->ac, ctx->outputs + idx + chan, count,
2912 4, true);
2913
2914 values[chan] = LLVMBuildExtractElement(ctx->builder,
2915 tmp_vec,
2916 indir_index, "");
2917 } else {
2918 values[chan] = LLVMBuildLoad(ctx->builder,
2919 ctx->outputs[idx + chan + const_index * 4],
2920 "");
2921 }
2922 }
2923 break;
2924 case nir_var_shared: {
2925 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2926 LLVMValueRef derived_ptr;
2927
2928 if (indir_index)
2929 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2930
2931 for (unsigned chan = 0; chan < ve; chan++) {
2932 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2933 if (indir_index)
2934 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2935 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2936
2937 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2938 }
2939 break;
2940 }
2941 default:
2942 unreachable("unhandle variable mode");
2943 }
2944 ret = ac_build_gather_values(&ctx->ac, values, ve);
2945 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2946 }
2947
2948 static void
2949 visit_store_var(struct nir_to_llvm_context *ctx,
2950 nir_intrinsic_instr *instr)
2951 {
2952 LLVMValueRef temp_ptr, value;
2953 int idx = instr->variables[0]->var->data.driver_location;
2954 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2955 int writemask = instr->const_index[0];
2956 LLVMValueRef indir_index;
2957 unsigned const_index;
2958 radv_get_deref_offset(ctx, instr->variables[0], false,
2959 NULL, NULL, &const_index, &indir_index);
2960
2961 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2962 int old_writemask = writemask;
2963
2964 src = LLVMBuildBitCast(ctx->builder, src,
2965 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2966 "");
2967
2968 writemask = 0;
2969 for (unsigned chan = 0; chan < 4; chan++) {
2970 if (old_writemask & (1 << chan))
2971 writemask |= 3u << (2 * chan);
2972 }
2973 }
2974
2975 switch (instr->variables[0]->var->data.mode) {
2976 case nir_var_shader_out:
2977
2978 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
2979 store_tcs_output(ctx, instr, src, writemask);
2980 return;
2981 }
2982
2983 for (unsigned chan = 0; chan < 8; chan++) {
2984 int stride = 4;
2985 if (!(writemask & (1 << chan)))
2986 continue;
2987
2988 value = llvm_extract_elem(ctx, src, chan);
2989
2990 if (instr->variables[0]->var->data.compact)
2991 stride = 1;
2992 if (indir_index) {
2993 unsigned count = glsl_count_attribute_slots(
2994 instr->variables[0]->var->type, false);
2995 count -= chan / 4;
2996 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2997 &ctx->ac, ctx->outputs + idx + chan, count,
2998 stride, true);
2999
3000 if (get_llvm_num_components(tmp_vec) > 1) {
3001 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3002 value, indir_index, "");
3003 } else
3004 tmp_vec = value;
3005 build_store_values_extended(ctx, ctx->outputs + idx + chan,
3006 count, stride, tmp_vec);
3007
3008 } else {
3009 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3010
3011 LLVMBuildStore(ctx->builder, value, temp_ptr);
3012 }
3013 }
3014 break;
3015 case nir_var_local:
3016 for (unsigned chan = 0; chan < 8; chan++) {
3017 if (!(writemask & (1 << chan)))
3018 continue;
3019
3020 value = llvm_extract_elem(ctx, src, chan);
3021 if (indir_index) {
3022 unsigned count = glsl_count_attribute_slots(
3023 instr->variables[0]->var->type, false);
3024 count -= chan / 4;
3025 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3026 &ctx->ac, ctx->locals + idx + chan, count,
3027 4, true);
3028
3029 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3030 value, indir_index, "");
3031 build_store_values_extended(ctx, ctx->locals + idx + chan,
3032 count, 4, tmp_vec);
3033 } else {
3034 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3035
3036 LLVMBuildStore(ctx->builder, value, temp_ptr);
3037 }
3038 }
3039 break;
3040 case nir_var_shared: {
3041 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3042
3043 if (indir_index)
3044 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
3045
3046 for (unsigned chan = 0; chan < 8; chan++) {
3047 if (!(writemask & (1 << chan)))
3048 continue;
3049 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
3050 LLVMValueRef derived_ptr;
3051
3052 if (indir_index)
3053 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
3054
3055 value = llvm_extract_elem(ctx, src, chan);
3056 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
3057 LLVMBuildStore(ctx->builder,
3058 to_integer(ctx, value), derived_ptr);
3059 }
3060 break;
3061 }
3062 default:
3063 break;
3064 }
3065 }
3066
3067 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3068 {
3069 switch (dim) {
3070 case GLSL_SAMPLER_DIM_BUF:
3071 return 1;
3072 case GLSL_SAMPLER_DIM_1D:
3073 return array ? 2 : 1;
3074 case GLSL_SAMPLER_DIM_2D:
3075 return array ? 3 : 2;
3076 case GLSL_SAMPLER_DIM_MS:
3077 return array ? 4 : 3;
3078 case GLSL_SAMPLER_DIM_3D:
3079 case GLSL_SAMPLER_DIM_CUBE:
3080 return 3;
3081 case GLSL_SAMPLER_DIM_RECT:
3082 case GLSL_SAMPLER_DIM_SUBPASS:
3083 return 2;
3084 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3085 return 3;
3086 default:
3087 break;
3088 }
3089 return 0;
3090 }
3091
3092
3093
3094 /* Adjust the sample index according to FMASK.
3095 *
3096 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3097 * which is the identity mapping. Each nibble says which physical sample
3098 * should be fetched to get that sample.
3099 *
3100 * For example, 0x11111100 means there are only 2 samples stored and
3101 * the second sample covers 3/4 of the pixel. When reading samples 0
3102 * and 1, return physical sample 0 (determined by the first two 0s
3103 * in FMASK), otherwise return physical sample 1.
3104 *
3105 * The sample index should be adjusted as follows:
3106 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3107 */
3108 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3109 LLVMValueRef coord_x, LLVMValueRef coord_y,
3110 LLVMValueRef coord_z,
3111 LLVMValueRef sample_index,
3112 LLVMValueRef fmask_desc_ptr)
3113 {
3114 LLVMValueRef fmask_load_address[4];
3115 LLVMValueRef res;
3116
3117 fmask_load_address[0] = coord_x;
3118 fmask_load_address[1] = coord_y;
3119 if (coord_z) {
3120 fmask_load_address[2] = coord_z;
3121 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3122 }
3123
3124 struct ac_image_args args = {0};
3125
3126 args.opcode = ac_image_load;
3127 args.da = coord_z ? true : false;
3128 args.resource = fmask_desc_ptr;
3129 args.dmask = 0xf;
3130 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3131
3132 res = ac_build_image_opcode(&ctx->ac, &args);
3133
3134 res = to_integer(ctx, res);
3135 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3136 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3137
3138 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3139 res,
3140 ctx->i32zero, "");
3141
3142 LLVMValueRef sample_index4 =
3143 LLVMBuildMul(ctx->builder, sample_index, four, "");
3144 LLVMValueRef shifted_fmask =
3145 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3146 LLVMValueRef final_sample =
3147 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3148
3149 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3150 * resource descriptor is 0 (invalid),
3151 */
3152 LLVMValueRef fmask_desc =
3153 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3154 ctx->v8i32, "");
3155
3156 LLVMValueRef fmask_word1 =
3157 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3158 ctx->i32one, "");
3159
3160 LLVMValueRef word1_is_nonzero =
3161 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3162 fmask_word1, ctx->i32zero, "");
3163
3164 /* Replace the MSAA sample index. */
3165 sample_index =
3166 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3167 final_sample, sample_index, "");
3168 return sample_index;
3169 }
3170
3171 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3172 nir_intrinsic_instr *instr)
3173 {
3174 const struct glsl_type *type = instr->variables[0]->var->type;
3175 if(instr->variables[0]->deref.child)
3176 type = instr->variables[0]->deref.child->type;
3177
3178 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3179 LLVMValueRef coords[4];
3180 LLVMValueRef masks[] = {
3181 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3182 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3183 };
3184 LLVMValueRef res;
3185 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3186
3187 int count;
3188 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3189 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3190 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3191 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3192 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3193
3194 count = image_type_to_components_count(dim,
3195 glsl_sampler_type_is_array(type));
3196
3197 if (is_ms) {
3198 LLVMValueRef fmask_load_address[3];
3199 int chan;
3200
3201 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3202 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3203 if (glsl_sampler_type_is_array(type))
3204 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3205 else
3206 fmask_load_address[2] = NULL;
3207 if (add_frag_pos) {
3208 for (chan = 0; chan < 2; ++chan)
3209 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3210 }
3211 sample_index = adjust_sample_index_using_fmask(ctx,
3212 fmask_load_address[0],
3213 fmask_load_address[1],
3214 fmask_load_address[2],
3215 sample_index,
3216 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3217 }
3218 if (count == 1) {
3219 if (instr->src[0].ssa->num_components)
3220 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3221 else
3222 res = src0;
3223 } else {
3224 int chan;
3225 if (is_ms)
3226 count--;
3227 for (chan = 0; chan < count; ++chan) {
3228 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3229 }
3230
3231 if (add_frag_pos) {
3232 for (chan = 0; chan < count; ++chan)
3233 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3234 }
3235 if (is_ms) {
3236 coords[count] = sample_index;
3237 count++;
3238 }
3239
3240 if (count == 3) {
3241 coords[3] = LLVMGetUndef(ctx->i32);
3242 count = 4;
3243 }
3244 res = ac_build_gather_values(&ctx->ac, coords, count);
3245 }
3246 return res;
3247 }
3248
3249 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3250 nir_intrinsic_instr *instr)
3251 {
3252 LLVMValueRef params[7];
3253 LLVMValueRef res;
3254 char intrinsic_name[64];
3255 const nir_variable *var = instr->variables[0]->var;
3256 const struct glsl_type *type = var->type;
3257 if(instr->variables[0]->deref.child)
3258 type = instr->variables[0]->deref.child->type;
3259
3260 type = glsl_without_array(type);
3261 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3262 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3263 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3264 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3265 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3266 params[3] = ctx->i1false; /* glc */
3267 params[4] = ctx->i1false; /* slc */
3268 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3269 params, 5, 0);
3270
3271 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3272 res = to_integer(ctx, res);
3273 } else {
3274 bool is_da = glsl_sampler_type_is_array(type) ||
3275 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3276 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3277 LLVMValueRef glc = ctx->i1false;
3278 LLVMValueRef slc = ctx->i1false;
3279
3280 params[0] = get_image_coords(ctx, instr);
3281 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3282 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3283 if (HAVE_LLVM <= 0x0309) {
3284 params[3] = ctx->i1false; /* r128 */
3285 params[4] = da;
3286 params[5] = glc;
3287 params[6] = slc;
3288 } else {
3289 LLVMValueRef lwe = ctx->i1false;
3290 params[3] = glc;
3291 params[4] = slc;
3292 params[5] = lwe;
3293 params[6] = da;
3294 }
3295
3296 ac_get_image_intr_name("llvm.amdgcn.image.load",
3297 ctx->v4f32, /* vdata */
3298 LLVMTypeOf(params[0]), /* coords */
3299 LLVMTypeOf(params[1]), /* rsrc */
3300 intrinsic_name, sizeof(intrinsic_name));
3301
3302 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3303 params, 7, AC_FUNC_ATTR_READONLY);
3304 }
3305 return to_integer(ctx, res);
3306 }
3307
3308 static void visit_image_store(struct nir_to_llvm_context *ctx,
3309 nir_intrinsic_instr *instr)
3310 {
3311 LLVMValueRef params[8];
3312 char intrinsic_name[64];
3313 const nir_variable *var = instr->variables[0]->var;
3314 const struct glsl_type *type = glsl_without_array(var->type);
3315
3316 if (ctx->stage == MESA_SHADER_FRAGMENT)
3317 ctx->shader_info->fs.writes_memory = true;
3318
3319 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3320 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
3321 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3322 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3323 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3324 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3325 params[4] = ctx->i1false; /* glc */
3326 params[5] = ctx->i1false; /* slc */
3327 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3328 params, 6, 0);
3329 } else {
3330 bool is_da = glsl_sampler_type_is_array(type) ||
3331 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3332 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3333 LLVMValueRef glc = ctx->i1false;
3334 LLVMValueRef slc = ctx->i1false;
3335
3336 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
3337 params[1] = get_image_coords(ctx, instr); /* coords */
3338 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3339 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3340 if (HAVE_LLVM <= 0x0309) {
3341 params[4] = ctx->i1false; /* r128 */
3342 params[5] = da;
3343 params[6] = glc;
3344 params[7] = slc;
3345 } else {
3346 LLVMValueRef lwe = ctx->i1false;
3347 params[4] = glc;
3348 params[5] = slc;
3349 params[6] = lwe;
3350 params[7] = da;
3351 }
3352
3353 ac_get_image_intr_name("llvm.amdgcn.image.store",
3354 LLVMTypeOf(params[0]), /* vdata */
3355 LLVMTypeOf(params[1]), /* coords */
3356 LLVMTypeOf(params[2]), /* rsrc */
3357 intrinsic_name, sizeof(intrinsic_name));
3358
3359 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3360 params, 8, 0);
3361 }
3362
3363 }
3364
3365 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3366 nir_intrinsic_instr *instr)
3367 {
3368 LLVMValueRef params[6];
3369 int param_count = 0;
3370 const nir_variable *var = instr->variables[0]->var;
3371
3372 const char *base_name = "llvm.amdgcn.image.atomic";
3373 const char *atomic_name;
3374 LLVMValueRef coords;
3375 char intrinsic_name[32], coords_type[8];
3376 const struct glsl_type *type = glsl_without_array(var->type);
3377
3378 if (ctx->stage == MESA_SHADER_FRAGMENT)
3379 ctx->shader_info->fs.writes_memory = true;
3380
3381 params[param_count++] = get_src(ctx, instr->src[2]);
3382 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3383 params[param_count++] = get_src(ctx, instr->src[3]);
3384
3385 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3386 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3387 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3388 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3389 params[param_count++] = ctx->i32zero; /* voffset */
3390 params[param_count++] = ctx->i1false; /* glc */
3391 params[param_count++] = ctx->i1false; /* slc */
3392 } else {
3393 bool da = glsl_sampler_type_is_array(type) ||
3394 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3395
3396 coords = params[param_count++] = get_image_coords(ctx, instr);
3397 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3398 params[param_count++] = ctx->i1false; /* r128 */
3399 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3400 params[param_count++] = ctx->i1false; /* slc */
3401 }
3402
3403 switch (instr->intrinsic) {
3404 case nir_intrinsic_image_atomic_add:
3405 atomic_name = "add";
3406 break;
3407 case nir_intrinsic_image_atomic_min:
3408 atomic_name = "smin";
3409 break;
3410 case nir_intrinsic_image_atomic_max:
3411 atomic_name = "smax";
3412 break;
3413 case nir_intrinsic_image_atomic_and:
3414 atomic_name = "and";
3415 break;
3416 case nir_intrinsic_image_atomic_or:
3417 atomic_name = "or";
3418 break;
3419 case nir_intrinsic_image_atomic_xor:
3420 atomic_name = "xor";
3421 break;
3422 case nir_intrinsic_image_atomic_exchange:
3423 atomic_name = "swap";
3424 break;
3425 case nir_intrinsic_image_atomic_comp_swap:
3426 atomic_name = "cmpswap";
3427 break;
3428 default:
3429 abort();
3430 }
3431 build_int_type_name(LLVMTypeOf(coords),
3432 coords_type, sizeof(coords_type));
3433
3434 snprintf(intrinsic_name, sizeof(intrinsic_name),
3435 "%s.%s.%s", base_name, atomic_name, coords_type);
3436 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3437 }
3438
3439 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3440 nir_intrinsic_instr *instr)
3441 {
3442 LLVMValueRef res;
3443 const nir_variable *var = instr->variables[0]->var;
3444 const struct glsl_type *type = instr->variables[0]->var->type;
3445 bool da = glsl_sampler_type_is_array(var->type) ||
3446 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3447 if(instr->variables[0]->deref.child)
3448 type = instr->variables[0]->deref.child->type;
3449
3450 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3451 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3452
3453 struct ac_image_args args = { 0 };
3454
3455 args.da = da;
3456 args.dmask = 0xf;
3457 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3458 args.opcode = ac_image_get_resinfo;
3459 args.addr = ctx->i32zero;
3460
3461 res = ac_build_image_opcode(&ctx->ac, &args);
3462
3463 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3464 glsl_sampler_type_is_array(type)) {
3465 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3466 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3467 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3468 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3469 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3470 }
3471 return res;
3472 }
3473
3474 #define NOOP_WAITCNT 0xf7f
3475 #define LGKM_CNT 0x07f
3476 #define VM_CNT 0xf70
3477
3478 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3479 unsigned simm16)
3480 {
3481 LLVMValueRef args[1] = {
3482 LLVMConstInt(ctx->i32, simm16, false),
3483 };
3484 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3485 ctx->voidt, args, 1, 0);
3486 }
3487
3488 static void emit_barrier(struct nir_to_llvm_context *ctx)
3489 {
3490 /* SI only (thanks to a hw bug workaround):
3491 * The real barrier instruction isn’t needed, because an entire patch
3492 * always fits into a single wave.
3493 */
3494 if (ctx->options->chip_class == SI &&
3495 ctx->stage == MESA_SHADER_TESS_CTRL) {
3496 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3497 return;
3498 }
3499 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3500 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3501 }
3502
3503 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3504 nir_intrinsic_instr *instr)
3505 {
3506 LLVMValueRef cond;
3507 ctx->shader_info->fs.can_discard = true;
3508
3509 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3510 get_src(ctx, instr->src[0]),
3511 ctx->i32zero, "");
3512
3513 cond = LLVMBuildSelect(ctx->builder, cond,
3514 LLVMConstReal(ctx->f32, -1.0f),
3515 ctx->f32zero, "");
3516 ac_build_kill(&ctx->ac, cond);
3517 }
3518
3519 static LLVMValueRef
3520 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3521 {
3522 LLVMValueRef result;
3523 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3524 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3525 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3526
3527 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3528 }
3529
3530 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3531 nir_intrinsic_instr *instr)
3532 {
3533 LLVMValueRef ptr, result;
3534 int idx = instr->variables[0]->var->data.driver_location;
3535 LLVMValueRef src = get_src(ctx, instr->src[0]);
3536 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3537
3538 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3539 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3540 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3541 ptr, src, src1,
3542 LLVMAtomicOrderingSequentiallyConsistent,
3543 LLVMAtomicOrderingSequentiallyConsistent,
3544 false);
3545 } else {
3546 LLVMAtomicRMWBinOp op;
3547 switch (instr->intrinsic) {
3548 case nir_intrinsic_var_atomic_add:
3549 op = LLVMAtomicRMWBinOpAdd;
3550 break;
3551 case nir_intrinsic_var_atomic_umin:
3552 op = LLVMAtomicRMWBinOpUMin;
3553 break;
3554 case nir_intrinsic_var_atomic_umax:
3555 op = LLVMAtomicRMWBinOpUMax;
3556 break;
3557 case nir_intrinsic_var_atomic_imin:
3558 op = LLVMAtomicRMWBinOpMin;
3559 break;
3560 case nir_intrinsic_var_atomic_imax:
3561 op = LLVMAtomicRMWBinOpMax;
3562 break;
3563 case nir_intrinsic_var_atomic_and:
3564 op = LLVMAtomicRMWBinOpAnd;
3565 break;
3566 case nir_intrinsic_var_atomic_or:
3567 op = LLVMAtomicRMWBinOpOr;
3568 break;
3569 case nir_intrinsic_var_atomic_xor:
3570 op = LLVMAtomicRMWBinOpXor;
3571 break;
3572 case nir_intrinsic_var_atomic_exchange:
3573 op = LLVMAtomicRMWBinOpXchg;
3574 break;
3575 default:
3576 return NULL;
3577 }
3578
3579 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
3580 LLVMAtomicOrderingSequentiallyConsistent,
3581 false);
3582 }
3583 return result;
3584 }
3585
3586 #define INTERP_CENTER 0
3587 #define INTERP_CENTROID 1
3588 #define INTERP_SAMPLE 2
3589
3590 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3591 enum glsl_interp_mode interp, unsigned location)
3592 {
3593 switch (interp) {
3594 case INTERP_MODE_FLAT:
3595 default:
3596 return NULL;
3597 case INTERP_MODE_SMOOTH:
3598 case INTERP_MODE_NONE:
3599 if (location == INTERP_CENTER)
3600 return ctx->persp_center;
3601 else if (location == INTERP_CENTROID)
3602 return ctx->persp_centroid;
3603 else if (location == INTERP_SAMPLE)
3604 return ctx->persp_sample;
3605 break;
3606 case INTERP_MODE_NOPERSPECTIVE:
3607 if (location == INTERP_CENTER)
3608 return ctx->linear_center;
3609 else if (location == INTERP_CENTROID)
3610 return ctx->linear_centroid;
3611 else if (location == INTERP_SAMPLE)
3612 return ctx->linear_sample;
3613 break;
3614 }
3615 return NULL;
3616 }
3617
3618 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3619 LLVMValueRef sample_id)
3620 {
3621 LLVMValueRef result;
3622 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3623
3624 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3625 const_array(ctx->v2f32, 64), "");
3626
3627 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3628 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3629
3630 return result;
3631 }
3632
3633 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3634 {
3635 LLVMValueRef values[2];
3636
3637 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
3638 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
3639 return ac_build_gather_values(&ctx->ac, values, 2);
3640 }
3641
3642 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3643 nir_intrinsic_instr *instr)
3644 {
3645 LLVMValueRef result[2];
3646 LLVMValueRef interp_param, attr_number;
3647 unsigned location;
3648 unsigned chan;
3649 LLVMValueRef src_c0, src_c1;
3650 LLVMValueRef src0;
3651 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3652 switch (instr->intrinsic) {
3653 case nir_intrinsic_interp_var_at_centroid:
3654 location = INTERP_CENTROID;
3655 break;
3656 case nir_intrinsic_interp_var_at_sample:
3657 case nir_intrinsic_interp_var_at_offset:
3658 location = INTERP_CENTER;
3659 src0 = get_src(ctx, instr->src[0]);
3660 break;
3661 default:
3662 break;
3663 }
3664
3665 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3666 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3667 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3668 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3669 LLVMValueRef sample_position;
3670 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3671
3672 /* fetch sample ID */
3673 sample_position = load_sample_position(ctx, src0);
3674
3675 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3676 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3677 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3678 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3679 }
3680 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3681 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3682
3683 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3684 LLVMValueRef ij_out[2];
3685 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3686
3687 /*
3688 * take the I then J parameters, and the DDX/Y for it, and
3689 * calculate the IJ inputs for the interpolator.
3690 * temp1 = ddx * offset/sample.x + I;
3691 * interp_param.I = ddy * offset/sample.y + temp1;
3692 * temp1 = ddx * offset/sample.x + J;
3693 * interp_param.J = ddy * offset/sample.y + temp1;
3694 */
3695 for (unsigned i = 0; i < 2; i++) {
3696 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3697 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3698 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3699 ddxy_out, ix_ll, "");
3700 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3701 ddxy_out, iy_ll, "");
3702 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3703 interp_param, ix_ll, "");
3704 LLVMValueRef temp1, temp2;
3705
3706 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3707 ctx->f32, "");
3708
3709 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3710 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3711
3712 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3713 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3714
3715 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3716 temp2, ctx->i32, "");
3717 }
3718 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3719
3720 }
3721
3722 for (chan = 0; chan < 2; chan++) {
3723 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3724
3725 if (interp_param) {
3726 interp_param = LLVMBuildBitCast(ctx->builder,
3727 interp_param, LLVMVectorType(ctx->f32, 2), "");
3728 LLVMValueRef i = LLVMBuildExtractElement(
3729 ctx->builder, interp_param, ctx->i32zero, "");
3730 LLVMValueRef j = LLVMBuildExtractElement(
3731 ctx->builder, interp_param, ctx->i32one, "");
3732
3733 result[chan] = ac_build_fs_interp(&ctx->ac,
3734 llvm_chan, attr_number,
3735 ctx->prim_mask, i, j);
3736 } else {
3737 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3738 LLVMConstInt(ctx->i32, 2, false),
3739 llvm_chan, attr_number,
3740 ctx->prim_mask);
3741 }
3742 }
3743 return ac_build_gather_values(&ctx->ac, result, 2);
3744 }
3745
3746 static void
3747 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3748 nir_intrinsic_instr *instr)
3749 {
3750 LLVMValueRef gs_next_vertex;
3751 LLVMValueRef can_emit, kill;
3752 int idx;
3753
3754 assert(instr->const_index[0] == 0);
3755 /* Write vertex attribute values to GSVS ring */
3756 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3757 ctx->gs_next_vertex,
3758 "");
3759
3760 /* If this thread has already emitted the declared maximum number of
3761 * vertices, kill it: excessive vertex emissions are not supposed to
3762 * have any effect, and GS threads have no externally observable
3763 * effects other than emitting vertices.
3764 */
3765 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3766 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3767
3768 kill = LLVMBuildSelect(ctx->builder, can_emit,
3769 LLVMConstReal(ctx->f32, 1.0f),
3770 LLVMConstReal(ctx->f32, -1.0f), "");
3771 ac_build_kill(&ctx->ac, kill);
3772
3773 /* loop num outputs */
3774 idx = 0;
3775 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3776 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3777 int length = 4;
3778 int slot = idx;
3779 int slot_inc = 1;
3780
3781 if (!(ctx->output_mask & (1ull << i)))
3782 continue;
3783
3784 if (i == VARYING_SLOT_CLIP_DIST0) {
3785 /* pack clip and cull into a single set of slots */
3786 length = ctx->num_output_clips + ctx->num_output_culls;
3787 if (length > 4)
3788 slot_inc = 2;
3789 }
3790 for (unsigned j = 0; j < length; j++) {
3791 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3792 out_ptr[j], "");
3793 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3794 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3795 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3796
3797 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3798
3799 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3800 out_val, 1,
3801 voffset, ctx->gs2vs_offset, 0,
3802 1, 1, true, true);
3803 }
3804 idx += slot_inc;
3805 }
3806
3807 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3808 ctx->i32one, "");
3809 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3810
3811 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3812 }
3813
3814 static void
3815 visit_end_primitive(struct nir_to_llvm_context *ctx,
3816 nir_intrinsic_instr *instr)
3817 {
3818 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3819 }
3820
3821 static LLVMValueRef
3822 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3823 nir_intrinsic_instr *instr)
3824 {
3825 LLVMValueRef coord[4] = {
3826 ctx->tes_u,
3827 ctx->tes_v,
3828 ctx->f32zero,
3829 ctx->f32zero,
3830 };
3831
3832 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3833 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3834 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3835
3836 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3837 return LLVMBuildBitCast(ctx->builder, result,
3838 get_def_type(ctx, &instr->dest.ssa), "");
3839 }
3840
3841 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3842 nir_intrinsic_instr *instr)
3843 {
3844 LLVMValueRef result = NULL;
3845
3846 switch (instr->intrinsic) {
3847 case nir_intrinsic_load_work_group_id: {
3848 result = ctx->workgroup_ids;
3849 break;
3850 }
3851 case nir_intrinsic_load_base_vertex: {
3852 result = ctx->base_vertex;
3853 break;
3854 }
3855 case nir_intrinsic_load_vertex_id_zero_base: {
3856 result = ctx->vertex_id;
3857 break;
3858 }
3859 case nir_intrinsic_load_local_invocation_id: {
3860 result = ctx->local_invocation_ids;
3861 break;
3862 }
3863 case nir_intrinsic_load_base_instance:
3864 result = ctx->start_instance;
3865 break;
3866 case nir_intrinsic_load_draw_id:
3867 result = ctx->draw_index;
3868 break;
3869 case nir_intrinsic_load_invocation_id:
3870 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3871 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3872 else
3873 result = ctx->gs_invocation_id;
3874 break;
3875 case nir_intrinsic_load_primitive_id:
3876 if (ctx->stage == MESA_SHADER_GEOMETRY)
3877 result = ctx->gs_prim_id;
3878 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
3879 result = ctx->tcs_patch_id;
3880 else if (ctx->stage == MESA_SHADER_TESS_EVAL)
3881 result = ctx->tes_patch_id;
3882 else
3883 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3884 break;
3885 case nir_intrinsic_load_sample_id:
3886 ctx->shader_info->fs.force_persample = true;
3887 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3888 break;
3889 case nir_intrinsic_load_sample_pos:
3890 ctx->shader_info->fs.force_persample = true;
3891 result = load_sample_pos(ctx);
3892 break;
3893 case nir_intrinsic_load_sample_mask_in:
3894 result = ctx->sample_coverage;
3895 break;
3896 case nir_intrinsic_load_front_face:
3897 result = ctx->front_face;
3898 break;
3899 case nir_intrinsic_load_instance_id:
3900 result = ctx->instance_id;
3901 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3902 ctx->shader_info->vs.vgpr_comp_cnt);
3903 break;
3904 case nir_intrinsic_load_num_work_groups:
3905 result = ctx->num_work_groups;
3906 break;
3907 case nir_intrinsic_load_local_invocation_index:
3908 result = visit_load_local_invocation_index(ctx);
3909 break;
3910 case nir_intrinsic_load_push_constant:
3911 result = visit_load_push_constant(ctx, instr);
3912 break;
3913 case nir_intrinsic_vulkan_resource_index:
3914 result = visit_vulkan_resource_index(ctx, instr);
3915 break;
3916 case nir_intrinsic_store_ssbo:
3917 visit_store_ssbo(ctx, instr);
3918 break;
3919 case nir_intrinsic_load_ssbo:
3920 result = visit_load_buffer(ctx, instr);
3921 break;
3922 case nir_intrinsic_ssbo_atomic_add:
3923 case nir_intrinsic_ssbo_atomic_imin:
3924 case nir_intrinsic_ssbo_atomic_umin:
3925 case nir_intrinsic_ssbo_atomic_imax:
3926 case nir_intrinsic_ssbo_atomic_umax:
3927 case nir_intrinsic_ssbo_atomic_and:
3928 case nir_intrinsic_ssbo_atomic_or:
3929 case nir_intrinsic_ssbo_atomic_xor:
3930 case nir_intrinsic_ssbo_atomic_exchange:
3931 case nir_intrinsic_ssbo_atomic_comp_swap:
3932 result = visit_atomic_ssbo(ctx, instr);
3933 break;
3934 case nir_intrinsic_load_ubo:
3935 result = visit_load_ubo_buffer(ctx, instr);
3936 break;
3937 case nir_intrinsic_get_buffer_size:
3938 result = visit_get_buffer_size(ctx, instr);
3939 break;
3940 case nir_intrinsic_load_var:
3941 result = visit_load_var(ctx, instr);
3942 break;
3943 case nir_intrinsic_store_var:
3944 visit_store_var(ctx, instr);
3945 break;
3946 case nir_intrinsic_image_load:
3947 result = visit_image_load(ctx, instr);
3948 break;
3949 case nir_intrinsic_image_store:
3950 visit_image_store(ctx, instr);
3951 break;
3952 case nir_intrinsic_image_atomic_add:
3953 case nir_intrinsic_image_atomic_min:
3954 case nir_intrinsic_image_atomic_max:
3955 case nir_intrinsic_image_atomic_and:
3956 case nir_intrinsic_image_atomic_or:
3957 case nir_intrinsic_image_atomic_xor:
3958 case nir_intrinsic_image_atomic_exchange:
3959 case nir_intrinsic_image_atomic_comp_swap:
3960 result = visit_image_atomic(ctx, instr);
3961 break;
3962 case nir_intrinsic_image_size:
3963 result = visit_image_size(ctx, instr);
3964 break;
3965 case nir_intrinsic_discard:
3966 ctx->shader_info->fs.can_discard = true;
3967 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3968 ctx->voidt,
3969 NULL, 0, AC_FUNC_ATTR_LEGACY);
3970 break;
3971 case nir_intrinsic_discard_if:
3972 emit_discard_if(ctx, instr);
3973 break;
3974 case nir_intrinsic_memory_barrier:
3975 emit_waitcnt(ctx, VM_CNT);
3976 break;
3977 case nir_intrinsic_barrier:
3978 emit_barrier(ctx);
3979 break;
3980 case nir_intrinsic_var_atomic_add:
3981 case nir_intrinsic_var_atomic_imin:
3982 case nir_intrinsic_var_atomic_umin:
3983 case nir_intrinsic_var_atomic_imax:
3984 case nir_intrinsic_var_atomic_umax:
3985 case nir_intrinsic_var_atomic_and:
3986 case nir_intrinsic_var_atomic_or:
3987 case nir_intrinsic_var_atomic_xor:
3988 case nir_intrinsic_var_atomic_exchange:
3989 case nir_intrinsic_var_atomic_comp_swap:
3990 result = visit_var_atomic(ctx, instr);
3991 break;
3992 case nir_intrinsic_interp_var_at_centroid:
3993 case nir_intrinsic_interp_var_at_sample:
3994 case nir_intrinsic_interp_var_at_offset:
3995 result = visit_interp(ctx, instr);
3996 break;
3997 case nir_intrinsic_emit_vertex:
3998 visit_emit_vertex(ctx, instr);
3999 break;
4000 case nir_intrinsic_end_primitive:
4001 visit_end_primitive(ctx, instr);
4002 break;
4003 case nir_intrinsic_load_tess_coord:
4004 result = visit_load_tess_coord(ctx, instr);
4005 break;
4006 case nir_intrinsic_load_patch_vertices_in:
4007 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
4008 break;
4009 default:
4010 fprintf(stderr, "Unknown intrinsic: ");
4011 nir_print_instr(&instr->instr, stderr);
4012 fprintf(stderr, "\n");
4013 break;
4014 }
4015 if (result) {
4016 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4017 }
4018 }
4019
4020 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4021 nir_deref_var *deref,
4022 enum desc_type desc_type)
4023 {
4024 unsigned desc_set = deref->var->data.descriptor_set;
4025 LLVMValueRef list = ctx->descriptor_sets[desc_set];
4026 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4027 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4028 unsigned offset = binding->offset;
4029 unsigned stride = binding->size;
4030 unsigned type_size;
4031 LLVMBuilderRef builder = ctx->builder;
4032 LLVMTypeRef type;
4033 LLVMValueRef index = NULL;
4034 unsigned constant_index = 0;
4035
4036 assert(deref->var->data.binding < layout->binding_count);
4037
4038 switch (desc_type) {
4039 case DESC_IMAGE:
4040 type = ctx->v8i32;
4041 type_size = 32;
4042 break;
4043 case DESC_FMASK:
4044 type = ctx->v8i32;
4045 offset += 32;
4046 type_size = 32;
4047 break;
4048 case DESC_SAMPLER:
4049 type = ctx->v4i32;
4050 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4051 offset += 64;
4052
4053 type_size = 16;
4054 break;
4055 case DESC_BUFFER:
4056 type = ctx->v4i32;
4057 type_size = 16;
4058 break;
4059 default:
4060 unreachable("invalid desc_type\n");
4061 }
4062
4063 if (deref->deref.child) {
4064 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
4065
4066 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4067 offset += child->base_offset * stride;
4068 if (child->deref_array_type == nir_deref_array_type_indirect) {
4069 index = get_src(ctx, child->indirect);
4070 }
4071
4072 constant_index = child->base_offset;
4073 }
4074 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4075 (!index || binding->immutable_samplers_equal)) {
4076 if (binding->immutable_samplers_equal)
4077 constant_index = 0;
4078
4079 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4080
4081 LLVMValueRef constants[] = {
4082 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4083 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4084 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4085 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4086 };
4087 return ac_build_gather_values(&ctx->ac, constants, 4);
4088 }
4089
4090 assert(stride % type_size == 0);
4091
4092 if (!index)
4093 index = ctx->i32zero;
4094
4095 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4096
4097 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4098 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4099
4100 return ac_build_indexed_load_const(&ctx->ac, list, index);
4101 }
4102
4103 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4104 struct ac_image_args *args,
4105 nir_tex_instr *instr,
4106 nir_texop op,
4107 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4108 LLVMValueRef *param, unsigned count,
4109 unsigned dmask)
4110 {
4111 unsigned is_rect = 0;
4112 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4113
4114 if (op == nir_texop_lod)
4115 da = false;
4116 /* Pad to power of two vector */
4117 while (count < util_next_power_of_two(count))
4118 param[count++] = LLVMGetUndef(ctx->i32);
4119
4120 if (count > 1)
4121 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4122 else
4123 args->addr = param[0];
4124
4125 args->resource = res_ptr;
4126 args->sampler = samp_ptr;
4127
4128 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4129 args->addr = param[0];
4130 return;
4131 }
4132
4133 args->dmask = dmask;
4134 args->unorm = is_rect;
4135 args->da = da;
4136 }
4137
4138 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4139 *
4140 * SI-CI:
4141 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4142 * filtering manually. The driver sets img7 to a mask clearing
4143 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4144 * s_and_b32 samp0, samp0, img7
4145 *
4146 * VI:
4147 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4148 */
4149 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4150 LLVMValueRef res, LLVMValueRef samp)
4151 {
4152 LLVMBuilderRef builder = ctx->builder;
4153 LLVMValueRef img7, samp0;
4154
4155 if (ctx->options->chip_class >= VI)
4156 return samp;
4157
4158 img7 = LLVMBuildExtractElement(builder, res,
4159 LLVMConstInt(ctx->i32, 7, 0), "");
4160 samp0 = LLVMBuildExtractElement(builder, samp,
4161 LLVMConstInt(ctx->i32, 0, 0), "");
4162 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4163 return LLVMBuildInsertElement(builder, samp, samp0,
4164 LLVMConstInt(ctx->i32, 0, 0), "");
4165 }
4166
4167 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4168 nir_tex_instr *instr,
4169 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4170 LLVMValueRef *fmask_ptr)
4171 {
4172 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4173 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4174 else
4175 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4176 if (samp_ptr) {
4177 if (instr->sampler)
4178 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4179 else
4180 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4181 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4182 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4183 }
4184 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4185 instr->op == nir_texop_samples_identical))
4186 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4187 }
4188
4189 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4190 LLVMValueRef coord)
4191 {
4192 coord = to_float(ctx, coord);
4193 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4194 coord = to_integer(ctx, coord);
4195 return coord;
4196 }
4197
4198 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4199 {
4200 LLVMValueRef result = NULL;
4201 struct ac_image_args args = { 0 };
4202 unsigned dmask = 0xf;
4203 LLVMValueRef address[16];
4204 LLVMValueRef coords[5];
4205 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4206 LLVMValueRef bias = NULL, offsets = NULL;
4207 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4208 LLVMValueRef ddx = NULL, ddy = NULL;
4209 LLVMValueRef derivs[6];
4210 unsigned chan, count = 0;
4211 unsigned const_src = 0, num_deriv_comp = 0;
4212 bool lod_is_zero = false;
4213 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4214
4215 for (unsigned i = 0; i < instr->num_srcs; i++) {
4216 switch (instr->src[i].src_type) {
4217 case nir_tex_src_coord:
4218 coord = get_src(ctx, instr->src[i].src);
4219 break;
4220 case nir_tex_src_projector:
4221 break;
4222 case nir_tex_src_comparator:
4223 comparator = get_src(ctx, instr->src[i].src);
4224 break;
4225 case nir_tex_src_offset:
4226 offsets = get_src(ctx, instr->src[i].src);
4227 const_src = i;
4228 break;
4229 case nir_tex_src_bias:
4230 bias = get_src(ctx, instr->src[i].src);
4231 break;
4232 case nir_tex_src_lod: {
4233 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4234
4235 if (val && val->i32[0] == 0)
4236 lod_is_zero = true;
4237 lod = get_src(ctx, instr->src[i].src);
4238 break;
4239 }
4240 case nir_tex_src_ms_index:
4241 sample_index = get_src(ctx, instr->src[i].src);
4242 break;
4243 case nir_tex_src_ms_mcs:
4244 break;
4245 case nir_tex_src_ddx:
4246 ddx = get_src(ctx, instr->src[i].src);
4247 num_deriv_comp = instr->src[i].src.ssa->num_components;
4248 break;
4249 case nir_tex_src_ddy:
4250 ddy = get_src(ctx, instr->src[i].src);
4251 break;
4252 case nir_tex_src_texture_offset:
4253 case nir_tex_src_sampler_offset:
4254 case nir_tex_src_plane:
4255 default:
4256 break;
4257 }
4258 }
4259
4260 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4261 result = get_buffer_size(ctx, res_ptr, true);
4262 goto write_result;
4263 }
4264
4265 if (instr->op == nir_texop_texture_samples) {
4266 LLVMValueRef res, samples, is_msaa;
4267 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4268 samples = LLVMBuildExtractElement(ctx->builder, res,
4269 LLVMConstInt(ctx->i32, 3, false), "");
4270 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4271 LLVMConstInt(ctx->i32, 28, false), "");
4272 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4273 LLVMConstInt(ctx->i32, 0xe, false), "");
4274 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4275 LLVMConstInt(ctx->i32, 0xe, false), "");
4276
4277 samples = LLVMBuildLShr(ctx->builder, samples,
4278 LLVMConstInt(ctx->i32, 16, false), "");
4279 samples = LLVMBuildAnd(ctx->builder, samples,
4280 LLVMConstInt(ctx->i32, 0xf, false), "");
4281 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4282 samples, "");
4283 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4284 ctx->i32one, "");
4285 result = samples;
4286 goto write_result;
4287 }
4288
4289 if (coord)
4290 for (chan = 0; chan < instr->coord_components; chan++)
4291 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4292
4293 if (offsets && instr->op != nir_texop_txf) {
4294 LLVMValueRef offset[3], pack;
4295 for (chan = 0; chan < 3; ++chan)
4296 offset[chan] = ctx->i32zero;
4297
4298 args.offset = true;
4299 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4300 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4301 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4302 LLVMConstInt(ctx->i32, 0x3f, false), "");
4303 if (chan)
4304 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4305 LLVMConstInt(ctx->i32, chan * 8, false), "");
4306 }
4307 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4308 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4309 address[count++] = pack;
4310
4311 }
4312 /* pack LOD bias value */
4313 if (instr->op == nir_texop_txb && bias) {
4314 address[count++] = bias;
4315 }
4316
4317 /* Pack depth comparison value */
4318 if (instr->is_shadow && comparator) {
4319 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4320 }
4321
4322 /* pack derivatives */
4323 if (ddx || ddy) {
4324 switch (instr->sampler_dim) {
4325 case GLSL_SAMPLER_DIM_3D:
4326 case GLSL_SAMPLER_DIM_CUBE:
4327 num_deriv_comp = 3;
4328 break;
4329 case GLSL_SAMPLER_DIM_2D:
4330 default:
4331 num_deriv_comp = 2;
4332 break;
4333 case GLSL_SAMPLER_DIM_1D:
4334 num_deriv_comp = 1;
4335 break;
4336 }
4337
4338 for (unsigned i = 0; i < num_deriv_comp; i++) {
4339 derivs[i] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
4340 derivs[num_deriv_comp + i] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
4341 }
4342 }
4343
4344 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4345 if (instr->is_array && instr->op != nir_texop_lod)
4346 coords[3] = apply_round_slice(ctx, coords[3]);
4347 for (chan = 0; chan < instr->coord_components; chan++)
4348 coords[chan] = to_float(ctx, coords[chan]);
4349 if (instr->coord_components == 3)
4350 coords[3] = LLVMGetUndef(ctx->f32);
4351 ac_prepare_cube_coords(&ctx->ac,
4352 instr->op == nir_texop_txd, instr->is_array,
4353 coords, derivs);
4354 if (num_deriv_comp)
4355 num_deriv_comp--;
4356 }
4357
4358 if (ddx || ddy) {
4359 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4360 address[count++] = derivs[i];
4361 }
4362
4363 /* Pack texture coordinates */
4364 if (coord) {
4365 address[count++] = coords[0];
4366 if (instr->coord_components > 1) {
4367 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4368 coords[1] = apply_round_slice(ctx, coords[1]);
4369 }
4370 address[count++] = coords[1];
4371 }
4372 if (instr->coord_components > 2) {
4373 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4374 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4375 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4376 instr->op != nir_texop_txf) {
4377 coords[2] = apply_round_slice(ctx, coords[2]);
4378 }
4379 address[count++] = coords[2];
4380 }
4381 }
4382
4383 /* Pack LOD */
4384 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4385 instr->op == nir_texop_txf)) {
4386 address[count++] = lod;
4387 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4388 address[count++] = sample_index;
4389 } else if(instr->op == nir_texop_txs) {
4390 count = 0;
4391 if (lod)
4392 address[count++] = lod;
4393 else
4394 address[count++] = ctx->i32zero;
4395 }
4396
4397 for (chan = 0; chan < count; chan++) {
4398 address[chan] = LLVMBuildBitCast(ctx->builder,
4399 address[chan], ctx->i32, "");
4400 }
4401
4402 if (instr->op == nir_texop_samples_identical) {
4403 LLVMValueRef txf_address[4];
4404 struct ac_image_args txf_args = { 0 };
4405 unsigned txf_count = count;
4406 memcpy(txf_address, address, sizeof(txf_address));
4407
4408 if (!instr->is_array)
4409 txf_address[2] = ctx->i32zero;
4410 txf_address[3] = ctx->i32zero;
4411
4412 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4413 fmask_ptr, NULL,
4414 txf_address, txf_count, 0xf);
4415
4416 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4417
4418 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4419 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
4420 goto write_result;
4421 }
4422
4423 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4424 instr->op != nir_texop_txs) {
4425 unsigned sample_chan = instr->is_array ? 3 : 2;
4426 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4427 address[0],
4428 address[1],
4429 instr->is_array ? address[2] : NULL,
4430 address[sample_chan],
4431 fmask_ptr);
4432 }
4433
4434 if (offsets && instr->op == nir_texop_txf) {
4435 nir_const_value *const_offset =
4436 nir_src_as_const_value(instr->src[const_src].src);
4437 int num_offsets = instr->src[const_src].src.ssa->num_components;
4438 assert(const_offset);
4439 num_offsets = MIN2(num_offsets, instr->coord_components);
4440 if (num_offsets > 2)
4441 address[2] = LLVMBuildAdd(ctx->builder,
4442 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4443 if (num_offsets > 1)
4444 address[1] = LLVMBuildAdd(ctx->builder,
4445 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4446 address[0] = LLVMBuildAdd(ctx->builder,
4447 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4448
4449 }
4450
4451 /* TODO TG4 support */
4452 if (instr->op == nir_texop_tg4) {
4453 if (instr->is_shadow)
4454 dmask = 1;
4455 else
4456 dmask = 1 << instr->component;
4457 }
4458 set_tex_fetch_args(ctx, &args, instr, instr->op,
4459 res_ptr, samp_ptr, address, count, dmask);
4460
4461 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4462
4463 if (instr->op == nir_texop_query_levels)
4464 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4465 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4466 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4467 else if (instr->op == nir_texop_txs &&
4468 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4469 instr->is_array) {
4470 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4471 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4472 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4473 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4474 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4475 } else if (instr->dest.ssa.num_components != 4)
4476 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4477
4478 write_result:
4479 if (result) {
4480 assert(instr->dest.is_ssa);
4481 result = to_integer(ctx, result);
4482 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4483 }
4484 }
4485
4486
4487 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4488 {
4489 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4490 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4491
4492 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4493 _mesa_hash_table_insert(ctx->phis, instr, result);
4494 }
4495
4496 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4497 nir_phi_instr *instr,
4498 LLVMValueRef llvm_phi)
4499 {
4500 nir_foreach_phi_src(src, instr) {
4501 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4502 LLVMValueRef llvm_src = get_src(ctx, src->src);
4503
4504 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4505 }
4506 }
4507
4508 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4509 {
4510 struct hash_entry *entry;
4511 hash_table_foreach(ctx->phis, entry) {
4512 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4513 (LLVMValueRef)entry->data);
4514 }
4515 }
4516
4517
4518 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4519 nir_ssa_undef_instr *instr)
4520 {
4521 unsigned num_components = instr->def.num_components;
4522 LLVMValueRef undef;
4523
4524 if (num_components == 1)
4525 undef = LLVMGetUndef(ctx->i32);
4526 else {
4527 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4528 }
4529 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4530 }
4531
4532 static void visit_jump(struct nir_to_llvm_context *ctx,
4533 nir_jump_instr *instr)
4534 {
4535 switch (instr->type) {
4536 case nir_jump_break:
4537 LLVMBuildBr(ctx->builder, ctx->break_block);
4538 LLVMClearInsertionPosition(ctx->builder);
4539 break;
4540 case nir_jump_continue:
4541 LLVMBuildBr(ctx->builder, ctx->continue_block);
4542 LLVMClearInsertionPosition(ctx->builder);
4543 break;
4544 default:
4545 fprintf(stderr, "Unknown NIR jump instr: ");
4546 nir_print_instr(&instr->instr, stderr);
4547 fprintf(stderr, "\n");
4548 abort();
4549 }
4550 }
4551
4552 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4553 struct exec_list *list);
4554
4555 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4556 {
4557 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4558 nir_foreach_instr(instr, block)
4559 {
4560 switch (instr->type) {
4561 case nir_instr_type_alu:
4562 visit_alu(ctx, nir_instr_as_alu(instr));
4563 break;
4564 case nir_instr_type_load_const:
4565 visit_load_const(ctx, nir_instr_as_load_const(instr));
4566 break;
4567 case nir_instr_type_intrinsic:
4568 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4569 break;
4570 case nir_instr_type_tex:
4571 visit_tex(ctx, nir_instr_as_tex(instr));
4572 break;
4573 case nir_instr_type_phi:
4574 visit_phi(ctx, nir_instr_as_phi(instr));
4575 break;
4576 case nir_instr_type_ssa_undef:
4577 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4578 break;
4579 case nir_instr_type_jump:
4580 visit_jump(ctx, nir_instr_as_jump(instr));
4581 break;
4582 default:
4583 fprintf(stderr, "Unknown NIR instr type: ");
4584 nir_print_instr(instr, stderr);
4585 fprintf(stderr, "\n");
4586 abort();
4587 }
4588 }
4589
4590 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4591 }
4592
4593 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4594 {
4595 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4596
4597 LLVMBasicBlockRef merge_block =
4598 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4599 LLVMBasicBlockRef if_block =
4600 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4601 LLVMBasicBlockRef else_block = merge_block;
4602 if (!exec_list_is_empty(&if_stmt->else_list))
4603 else_block = LLVMAppendBasicBlockInContext(
4604 ctx->context, ctx->main_function, "");
4605
4606 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4607 LLVMConstInt(ctx->i32, 0, false), "");
4608 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4609
4610 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4611 visit_cf_list(ctx, &if_stmt->then_list);
4612 if (LLVMGetInsertBlock(ctx->builder))
4613 LLVMBuildBr(ctx->builder, merge_block);
4614
4615 if (!exec_list_is_empty(&if_stmt->else_list)) {
4616 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4617 visit_cf_list(ctx, &if_stmt->else_list);
4618 if (LLVMGetInsertBlock(ctx->builder))
4619 LLVMBuildBr(ctx->builder, merge_block);
4620 }
4621
4622 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4623 }
4624
4625 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4626 {
4627 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4628 LLVMBasicBlockRef break_parent = ctx->break_block;
4629
4630 ctx->continue_block =
4631 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4632 ctx->break_block =
4633 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4634
4635 LLVMBuildBr(ctx->builder, ctx->continue_block);
4636 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4637 visit_cf_list(ctx, &loop->body);
4638
4639 if (LLVMGetInsertBlock(ctx->builder))
4640 LLVMBuildBr(ctx->builder, ctx->continue_block);
4641 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4642
4643 ctx->continue_block = continue_parent;
4644 ctx->break_block = break_parent;
4645 }
4646
4647 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4648 struct exec_list *list)
4649 {
4650 foreach_list_typed(nir_cf_node, node, node, list)
4651 {
4652 switch (node->type) {
4653 case nir_cf_node_block:
4654 visit_block(ctx, nir_cf_node_as_block(node));
4655 break;
4656
4657 case nir_cf_node_if:
4658 visit_if(ctx, nir_cf_node_as_if(node));
4659 break;
4660
4661 case nir_cf_node_loop:
4662 visit_loop(ctx, nir_cf_node_as_loop(node));
4663 break;
4664
4665 default:
4666 assert(0);
4667 }
4668 }
4669 }
4670
4671 static void
4672 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4673 struct nir_variable *variable)
4674 {
4675 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4676 LLVMValueRef t_offset;
4677 LLVMValueRef t_list;
4678 LLVMValueRef input;
4679 LLVMValueRef buffer_index;
4680 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4681 int idx = variable->data.location;
4682 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4683
4684 variable->data.driver_location = idx * 4;
4685
4686 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4687 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4688 ctx->start_instance, "");
4689 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4690 ctx->shader_info->vs.vgpr_comp_cnt);
4691 } else
4692 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4693 ctx->base_vertex, "");
4694
4695 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4696 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4697
4698 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4699
4700 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4701 buffer_index,
4702 LLVMConstInt(ctx->i32, 0, false),
4703 true);
4704
4705 for (unsigned chan = 0; chan < 4; chan++) {
4706 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4707 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4708 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
4709 input, llvm_chan, ""));
4710 }
4711 }
4712 }
4713
4714 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4715 unsigned attr,
4716 LLVMValueRef interp_param,
4717 LLVMValueRef prim_mask,
4718 LLVMValueRef result[4])
4719 {
4720 LLVMValueRef attr_number;
4721 unsigned chan;
4722 LLVMValueRef i, j;
4723 bool interp = interp_param != NULL;
4724
4725 attr_number = LLVMConstInt(ctx->i32, attr, false);
4726
4727 /* fs.constant returns the param from the middle vertex, so it's not
4728 * really useful for flat shading. It's meant to be used for custom
4729 * interpolation (but the intrinsic can't fetch from the other two
4730 * vertices).
4731 *
4732 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4733 * to do the right thing. The only reason we use fs.constant is that
4734 * fs.interp cannot be used on integers, because they can be equal
4735 * to NaN.
4736 */
4737 if (interp) {
4738 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4739 LLVMVectorType(ctx->f32, 2), "");
4740
4741 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4742 ctx->i32zero, "");
4743 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4744 ctx->i32one, "");
4745 }
4746
4747 for (chan = 0; chan < 4; chan++) {
4748 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4749
4750 if (interp) {
4751 result[chan] = ac_build_fs_interp(&ctx->ac,
4752 llvm_chan,
4753 attr_number,
4754 prim_mask, i, j);
4755 } else {
4756 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4757 LLVMConstInt(ctx->i32, 2, false),
4758 llvm_chan,
4759 attr_number,
4760 prim_mask);
4761 }
4762 }
4763 }
4764
4765 static void
4766 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4767 struct nir_variable *variable)
4768 {
4769 int idx = variable->data.location;
4770 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4771 LLVMValueRef interp;
4772
4773 variable->data.driver_location = idx * 4;
4774 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4775
4776 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4777 unsigned interp_type;
4778 if (variable->data.sample) {
4779 interp_type = INTERP_SAMPLE;
4780 ctx->shader_info->fs.force_persample = true;
4781 } else if (variable->data.centroid)
4782 interp_type = INTERP_CENTROID;
4783 else
4784 interp_type = INTERP_CENTER;
4785
4786 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4787 } else
4788 interp = NULL;
4789
4790 for (unsigned i = 0; i < attrib_count; ++i)
4791 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4792
4793 }
4794
4795 static void
4796 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4797 struct nir_variable *variable)
4798 {
4799 switch (ctx->stage) {
4800 case MESA_SHADER_VERTEX:
4801 handle_vs_input_decl(ctx, variable);
4802 break;
4803 case MESA_SHADER_FRAGMENT:
4804 handle_fs_input_decl(ctx, variable);
4805 break;
4806 default:
4807 break;
4808 }
4809
4810 }
4811
4812 static void
4813 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4814 struct nir_shader *nir)
4815 {
4816 unsigned index = 0;
4817 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4818 LLVMValueRef interp_param;
4819 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4820
4821 if (!(ctx->input_mask & (1ull << i)))
4822 continue;
4823
4824 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4825 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4826 interp_param = *inputs;
4827 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4828 inputs);
4829
4830 if (!interp_param)
4831 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4832 ++index;
4833 } else if (i == VARYING_SLOT_POS) {
4834 for(int i = 0; i < 3; ++i)
4835 inputs[i] = ctx->frag_pos[i];
4836
4837 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4838 }
4839 }
4840 ctx->shader_info->fs.num_interp = index;
4841 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4842 ctx->shader_info->fs.has_pcoord = true;
4843 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4844 ctx->shader_info->fs.prim_id_input = true;
4845 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4846 ctx->shader_info->fs.layer_input = true;
4847 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4848 }
4849
4850 static LLVMValueRef
4851 ac_build_alloca(struct nir_to_llvm_context *ctx,
4852 LLVMTypeRef type,
4853 const char *name)
4854 {
4855 LLVMBuilderRef builder = ctx->builder;
4856 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4857 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4858 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4859 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4860 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4861 LLVMValueRef res;
4862
4863 if (first_instr) {
4864 LLVMPositionBuilderBefore(first_builder, first_instr);
4865 } else {
4866 LLVMPositionBuilderAtEnd(first_builder, first_block);
4867 }
4868
4869 res = LLVMBuildAlloca(first_builder, type, name);
4870 LLVMBuildStore(builder, LLVMConstNull(type), res);
4871
4872 LLVMDisposeBuilder(first_builder);
4873
4874 return res;
4875 }
4876
4877 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4878 LLVMTypeRef type,
4879 const char *name)
4880 {
4881 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4882 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4883 return ptr;
4884 }
4885
4886 static void
4887 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4888 struct nir_variable *variable)
4889 {
4890 int idx = variable->data.location + variable->data.index;
4891 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4892 uint64_t mask_attribs;
4893 variable->data.driver_location = idx * 4;
4894
4895 /* tess ctrl has it's own load/store paths for outputs */
4896 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4897 return;
4898
4899 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4900 if (ctx->stage == MESA_SHADER_VERTEX ||
4901 ctx->stage == MESA_SHADER_TESS_EVAL ||
4902 ctx->stage == MESA_SHADER_GEOMETRY) {
4903 if (idx == VARYING_SLOT_CLIP_DIST0) {
4904 int length = ctx->num_output_clips + ctx->num_output_culls;
4905 if (ctx->stage == MESA_SHADER_VERTEX) {
4906 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4907 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4908 }
4909 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4910 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4911 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4912 }
4913
4914 if (length > 4)
4915 attrib_count = 2;
4916 else
4917 attrib_count = 1;
4918 mask_attribs = 1ull << idx;
4919 }
4920 }
4921
4922 for (unsigned i = 0; i < attrib_count; ++i) {
4923 for (unsigned chan = 0; chan < 4; chan++) {
4924 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4925 si_build_alloca_undef(ctx, ctx->f32, "");
4926 }
4927 }
4928 ctx->output_mask |= mask_attribs;
4929 }
4930
4931 static void
4932 setup_locals(struct nir_to_llvm_context *ctx,
4933 struct nir_function *func)
4934 {
4935 int i, j;
4936 ctx->num_locals = 0;
4937 nir_foreach_variable(variable, &func->impl->locals) {
4938 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4939 variable->data.driver_location = ctx->num_locals * 4;
4940 ctx->num_locals += attrib_count;
4941 }
4942 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4943 if (!ctx->locals)
4944 return;
4945
4946 for (i = 0; i < ctx->num_locals; i++) {
4947 for (j = 0; j < 4; j++) {
4948 ctx->locals[i * 4 + j] =
4949 si_build_alloca_undef(ctx, ctx->f32, "temp");
4950 }
4951 }
4952 }
4953
4954 static LLVMValueRef
4955 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4956 {
4957 v = to_float(ctx, v);
4958 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4959 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4960 }
4961
4962
4963 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4964 LLVMValueRef src0, LLVMValueRef src1)
4965 {
4966 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4967 LLVMValueRef comp[2];
4968
4969 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4970 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4971 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4972 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4973 }
4974
4975 /* Initialize arguments for the shader export intrinsic */
4976 static void
4977 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4978 LLVMValueRef *values,
4979 unsigned target,
4980 struct ac_export_args *args)
4981 {
4982 /* Default is 0xf. Adjusted below depending on the format. */
4983 args->enabled_channels = 0xf;
4984
4985 /* Specify whether the EXEC mask represents the valid mask */
4986 args->valid_mask = 0;
4987
4988 /* Specify whether this is the last export */
4989 args->done = 0;
4990
4991 /* Specify the target we are exporting */
4992 args->target = target;
4993
4994 args->compr = false;
4995 args->out[0] = LLVMGetUndef(ctx->f32);
4996 args->out[1] = LLVMGetUndef(ctx->f32);
4997 args->out[2] = LLVMGetUndef(ctx->f32);
4998 args->out[3] = LLVMGetUndef(ctx->f32);
4999
5000 if (!values)
5001 return;
5002
5003 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5004 LLVMValueRef val[4];
5005 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5006 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5007 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5008
5009 switch(col_format) {
5010 case V_028714_SPI_SHADER_ZERO:
5011 args->enabled_channels = 0; /* writemask */
5012 args->target = V_008DFC_SQ_EXP_NULL;
5013 break;
5014
5015 case V_028714_SPI_SHADER_32_R:
5016 args->enabled_channels = 1;
5017 args->out[0] = values[0];
5018 break;
5019
5020 case V_028714_SPI_SHADER_32_GR:
5021 args->enabled_channels = 0x3;
5022 args->out[0] = values[0];
5023 args->out[1] = values[1];
5024 break;
5025
5026 case V_028714_SPI_SHADER_32_AR:
5027 args->enabled_channels = 0x9;
5028 args->out[0] = values[0];
5029 args->out[3] = values[3];
5030 break;
5031
5032 case V_028714_SPI_SHADER_FP16_ABGR:
5033 args->compr = 1;
5034
5035 for (unsigned chan = 0; chan < 2; chan++) {
5036 LLVMValueRef pack_args[2] = {
5037 values[2 * chan],
5038 values[2 * chan + 1]
5039 };
5040 LLVMValueRef packed;
5041
5042 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5043 args->out[chan] = packed;
5044 }
5045 break;
5046
5047 case V_028714_SPI_SHADER_UNORM16_ABGR:
5048 for (unsigned chan = 0; chan < 4; chan++) {
5049 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5050 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5051 LLVMConstReal(ctx->f32, 65535), "");
5052 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5053 LLVMConstReal(ctx->f32, 0.5), "");
5054 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5055 ctx->i32, "");
5056 }
5057
5058 args->compr = 1;
5059 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5060 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5061 break;
5062
5063 case V_028714_SPI_SHADER_SNORM16_ABGR:
5064 for (unsigned chan = 0; chan < 4; chan++) {
5065 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
5066 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5067 LLVMConstReal(ctx->f32, 32767), "");
5068
5069 /* If positive, add 0.5, else add -0.5. */
5070 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5071 LLVMBuildSelect(ctx->builder,
5072 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5073 val[chan], ctx->f32zero, ""),
5074 LLVMConstReal(ctx->f32, 0.5),
5075 LLVMConstReal(ctx->f32, -0.5), ""), "");
5076 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5077 }
5078
5079 args->compr = 1;
5080 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5081 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5082 break;
5083
5084 case V_028714_SPI_SHADER_UINT16_ABGR: {
5085 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5086
5087 for (unsigned chan = 0; chan < 4; chan++) {
5088 val[chan] = to_integer(ctx, values[chan]);
5089 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
5090 }
5091
5092 args->compr = 1;
5093 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5094 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5095 break;
5096 }
5097
5098 case V_028714_SPI_SHADER_SINT16_ABGR: {
5099 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5100 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5101
5102 /* Clamp. */
5103 for (unsigned chan = 0; chan < 4; chan++) {
5104 val[chan] = to_integer(ctx, values[chan]);
5105 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
5106 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
5107 }
5108
5109 args->compr = 1;
5110 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5111 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5112 break;
5113 }
5114
5115 default:
5116 case V_028714_SPI_SHADER_32_ABGR:
5117 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5118 break;
5119 }
5120 } else
5121 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5122
5123 for (unsigned i = 0; i < 4; ++i)
5124 args->out[i] = to_float(ctx, args->out[i]);
5125 }
5126
5127 static void
5128 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5129 struct ac_vs_output_info *outinfo)
5130 {
5131 uint32_t param_count = 0;
5132 unsigned target;
5133 unsigned pos_idx, num_pos_exports = 0;
5134 struct ac_export_args args, pos_args[4] = {};
5135 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5136 int i;
5137
5138 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5139 sizeof(outinfo->vs_output_param_offset));
5140
5141 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5142 LLVMValueRef slots[8];
5143 unsigned j;
5144
5145 if (outinfo->cull_dist_mask)
5146 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5147
5148 i = VARYING_SLOT_CLIP_DIST0;
5149 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5150 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5151 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5152
5153 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5154 slots[i] = LLVMGetUndef(ctx->f32);
5155
5156 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5157 target = V_008DFC_SQ_EXP_POS + 3;
5158 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5159 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5160 &args, sizeof(args));
5161 }
5162
5163 target = V_008DFC_SQ_EXP_POS + 2;
5164 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5165 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5166 &args, sizeof(args));
5167
5168 }
5169
5170 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5171 LLVMValueRef values[4];
5172 if (!(ctx->output_mask & (1ull << i)))
5173 continue;
5174
5175 for (unsigned j = 0; j < 4; j++)
5176 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5177 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5178
5179 if (i == VARYING_SLOT_POS) {
5180 target = V_008DFC_SQ_EXP_POS;
5181 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5182 continue;
5183 } else if (i == VARYING_SLOT_PSIZ) {
5184 outinfo->writes_pointsize = true;
5185 psize_value = values[0];
5186 continue;
5187 } else if (i == VARYING_SLOT_LAYER) {
5188 outinfo->writes_layer = true;
5189 layer_value = values[0];
5190 target = V_008DFC_SQ_EXP_PARAM + param_count;
5191 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5192 param_count++;
5193 } else if (i == VARYING_SLOT_VIEWPORT) {
5194 outinfo->writes_viewport_index = true;
5195 viewport_index_value = values[0];
5196 continue;
5197 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5198 target = V_008DFC_SQ_EXP_PARAM + param_count;
5199 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5200 param_count++;
5201 } else if (i >= VARYING_SLOT_VAR0) {
5202 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5203 target = V_008DFC_SQ_EXP_PARAM + param_count;
5204 outinfo->vs_output_param_offset[i] = param_count;
5205 param_count++;
5206 }
5207
5208 si_llvm_init_export_args(ctx, values, target, &args);
5209
5210 if (target >= V_008DFC_SQ_EXP_POS &&
5211 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5212 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5213 &args, sizeof(args));
5214 } else {
5215 ac_build_export(&ctx->ac, &args);
5216 }
5217 }
5218
5219 /* We need to add the position output manually if it's missing. */
5220 if (!pos_args[0].out[0]) {
5221 pos_args[0].enabled_channels = 0xf;
5222 pos_args[0].valid_mask = 0;
5223 pos_args[0].done = 0;
5224 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5225 pos_args[0].compr = 0;
5226 pos_args[0].out[0] = ctx->f32zero; /* X */
5227 pos_args[0].out[1] = ctx->f32zero; /* Y */
5228 pos_args[0].out[2] = ctx->f32zero; /* Z */
5229 pos_args[0].out[3] = ctx->f32one; /* W */
5230 }
5231
5232 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5233 (outinfo->writes_layer == true ? 4 : 0) |
5234 (outinfo->writes_viewport_index == true ? 8 : 0));
5235 if (mask) {
5236 pos_args[1].enabled_channels = mask;
5237 pos_args[1].valid_mask = 0;
5238 pos_args[1].done = 0;
5239 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5240 pos_args[1].compr = 0;
5241 pos_args[1].out[0] = ctx->f32zero; /* X */
5242 pos_args[1].out[1] = ctx->f32zero; /* Y */
5243 pos_args[1].out[2] = ctx->f32zero; /* Z */
5244 pos_args[1].out[3] = ctx->f32zero; /* W */
5245
5246 if (outinfo->writes_pointsize == true)
5247 pos_args[1].out[0] = psize_value;
5248 if (outinfo->writes_layer == true)
5249 pos_args[1].out[2] = layer_value;
5250 if (outinfo->writes_viewport_index == true)
5251 pos_args[1].out[3] = viewport_index_value;
5252 }
5253 for (i = 0; i < 4; i++) {
5254 if (pos_args[i].out[0])
5255 num_pos_exports++;
5256 }
5257
5258 pos_idx = 0;
5259 for (i = 0; i < 4; i++) {
5260 if (!pos_args[i].out[0])
5261 continue;
5262
5263 /* Specify the target we are exporting */
5264 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5265 if (pos_idx == num_pos_exports)
5266 pos_args[i].done = 1;
5267 ac_build_export(&ctx->ac, &pos_args[i]);
5268 }
5269
5270 outinfo->pos_exports = num_pos_exports;
5271 outinfo->param_exports = param_count;
5272 }
5273
5274 static void
5275 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5276 struct ac_es_output_info *outinfo)
5277 {
5278 int j;
5279 uint64_t max_output_written = 0;
5280 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5281 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5282 int param_index;
5283 int length = 4;
5284
5285 if (!(ctx->output_mask & (1ull << i)))
5286 continue;
5287
5288 if (i == VARYING_SLOT_CLIP_DIST0)
5289 length = ctx->num_output_clips + ctx->num_output_culls;
5290
5291 param_index = shader_io_get_unique_index(i);
5292
5293 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5294
5295 for (j = 0; j < length; j++) {
5296 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5297 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5298
5299 ac_build_buffer_store_dword(&ctx->ac,
5300 ctx->esgs_ring,
5301 out_val, 1,
5302 NULL, ctx->es2gs_offset,
5303 (4 * param_index + j) * 4,
5304 1, 1, true, true);
5305 }
5306 }
5307 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5308 }
5309
5310 static void
5311 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5312 {
5313 LLVMValueRef vertex_id = ctx->rel_auto_id;
5314 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5315 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5316 vertex_dw_stride, "");
5317
5318 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5319 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5320 int length = 4;
5321
5322 if (!(ctx->output_mask & (1ull << i)))
5323 continue;
5324
5325 if (i == VARYING_SLOT_CLIP_DIST0)
5326 length = ctx->num_output_clips + ctx->num_output_culls;
5327 int param = shader_io_get_unique_index(i);
5328 mark_tess_output(ctx, false, param);
5329 if (length > 4)
5330 mark_tess_output(ctx, false, param + 1);
5331 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5332 LLVMConstInt(ctx->i32, param * 4, false),
5333 "");
5334 for (unsigned j = 0; j < length; j++) {
5335 lds_store(ctx, dw_addr,
5336 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5337 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5338 }
5339 }
5340 }
5341
5342 struct ac_build_if_state
5343 {
5344 struct nir_to_llvm_context *ctx;
5345 LLVMValueRef condition;
5346 LLVMBasicBlockRef entry_block;
5347 LLVMBasicBlockRef true_block;
5348 LLVMBasicBlockRef false_block;
5349 LLVMBasicBlockRef merge_block;
5350 };
5351
5352 static LLVMBasicBlockRef
5353 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5354 {
5355 LLVMBasicBlockRef current_block;
5356 LLVMBasicBlockRef next_block;
5357 LLVMBasicBlockRef new_block;
5358
5359 /* get current basic block */
5360 current_block = LLVMGetInsertBlock(ctx->builder);
5361
5362 /* chqeck if there's another block after this one */
5363 next_block = LLVMGetNextBasicBlock(current_block);
5364 if (next_block) {
5365 /* insert the new block before the next block */
5366 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5367 }
5368 else {
5369 /* append new block after current block */
5370 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5371 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5372 }
5373 return new_block;
5374 }
5375
5376 static void
5377 ac_nir_build_if(struct ac_build_if_state *ifthen,
5378 struct nir_to_llvm_context *ctx,
5379 LLVMValueRef condition)
5380 {
5381 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5382
5383 memset(ifthen, 0, sizeof *ifthen);
5384 ifthen->ctx = ctx;
5385 ifthen->condition = condition;
5386 ifthen->entry_block = block;
5387
5388 /* create endif/merge basic block for the phi functions */
5389 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5390
5391 /* create/insert true_block before merge_block */
5392 ifthen->true_block =
5393 LLVMInsertBasicBlockInContext(ctx->context,
5394 ifthen->merge_block,
5395 "if-true-block");
5396
5397 /* successive code goes into the true block */
5398 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5399 }
5400
5401 /**
5402 * End a conditional.
5403 */
5404 static void
5405 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5406 {
5407 LLVMBuilderRef builder = ifthen->ctx->builder;
5408
5409 /* Insert branch to the merge block from current block */
5410 LLVMBuildBr(builder, ifthen->merge_block);
5411
5412 /*
5413 * Now patch in the various branch instructions.
5414 */
5415
5416 /* Insert the conditional branch instruction at the end of entry_block */
5417 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5418 if (ifthen->false_block) {
5419 /* we have an else clause */
5420 LLVMBuildCondBr(builder, ifthen->condition,
5421 ifthen->true_block, ifthen->false_block);
5422 }
5423 else {
5424 /* no else clause */
5425 LLVMBuildCondBr(builder, ifthen->condition,
5426 ifthen->true_block, ifthen->merge_block);
5427 }
5428
5429 /* Resume building code at end of the ifthen->merge_block */
5430 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5431 }
5432
5433 static void
5434 write_tess_factors(struct nir_to_llvm_context *ctx)
5435 {
5436 unsigned stride, outer_comps, inner_comps;
5437 struct ac_build_if_state if_ctx, inner_if_ctx;
5438 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5439 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5440 unsigned tess_inner_index, tess_outer_index;
5441 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5442 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5443 int i;
5444 emit_barrier(ctx);
5445
5446 switch (ctx->options->key.tcs.primitive_mode) {
5447 case GL_ISOLINES:
5448 stride = 2;
5449 outer_comps = 2;
5450 inner_comps = 0;
5451 break;
5452 case GL_TRIANGLES:
5453 stride = 4;
5454 outer_comps = 3;
5455 inner_comps = 1;
5456 break;
5457 case GL_QUADS:
5458 stride = 6;
5459 outer_comps = 4;
5460 inner_comps = 2;
5461 break;
5462 default:
5463 return;
5464 }
5465
5466 ac_nir_build_if(&if_ctx, ctx,
5467 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5468 invocation_id, ctx->i32zero, ""));
5469
5470 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5471 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5472
5473 mark_tess_output(ctx, true, tess_inner_index);
5474 mark_tess_output(ctx, true, tess_outer_index);
5475 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5476 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5477 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5478 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5479 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5480
5481 for (i = 0; i < 4; i++) {
5482 inner[i] = LLVMGetUndef(ctx->i32);
5483 outer[i] = LLVMGetUndef(ctx->i32);
5484 }
5485
5486 // LINES reverseal
5487 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5488 outer[0] = out[1] = lds_load(ctx, lds_outer);
5489 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5490 LLVMConstInt(ctx->i32, 1, false), "");
5491 outer[1] = out[0] = lds_load(ctx, lds_outer);
5492 } else {
5493 for (i = 0; i < outer_comps; i++) {
5494 outer[i] = out[i] =
5495 lds_load(ctx, lds_outer);
5496 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5497 LLVMConstInt(ctx->i32, 1, false), "");
5498 }
5499 for (i = 0; i < inner_comps; i++) {
5500 inner[i] = out[outer_comps+i] =
5501 lds_load(ctx, lds_inner);
5502 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5503 LLVMConstInt(ctx->i32, 1, false), "");
5504 }
5505 }
5506
5507 /* Convert the outputs to vectors for stores. */
5508 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5509 vec1 = NULL;
5510
5511 if (stride > 4)
5512 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5513
5514
5515 buffer = ctx->hs_ring_tess_factor;
5516 tf_base = ctx->tess_factor_offset;
5517 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5518 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5519
5520 ac_nir_build_if(&inner_if_ctx, ctx,
5521 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5522 rel_patch_id, ctx->i32zero, ""));
5523
5524 /* Store the dynamic HS control word. */
5525 ac_build_buffer_store_dword(&ctx->ac, buffer,
5526 LLVMConstInt(ctx->i32, 0x80000000, false),
5527 1, ctx->i32zero, tf_base,
5528 0, 1, 0, true, false);
5529 ac_nir_build_endif(&inner_if_ctx);
5530
5531 /* Store the tessellation factors. */
5532 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5533 MIN2(stride, 4), byteoffset, tf_base,
5534 4, 1, 0, true, false);
5535 if (vec1)
5536 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5537 stride - 4, byteoffset, tf_base,
5538 20, 1, 0, true, false);
5539
5540 //TODO store to offchip for TES to read - only if TES reads them
5541 if (1) {
5542 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5543 LLVMValueRef tf_inner_offset;
5544 unsigned param_outer, param_inner;
5545
5546 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5547 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5548 LLVMConstInt(ctx->i32, param_outer, 0));
5549
5550 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5551 util_next_power_of_two(outer_comps));
5552
5553 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5554 outer_comps, tf_outer_offset,
5555 ctx->oc_lds, 0, 1, 0, true, false);
5556 if (inner_comps) {
5557 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5558 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5559 LLVMConstInt(ctx->i32, param_inner, 0));
5560
5561 inner_vec = inner_comps == 1 ? inner[0] :
5562 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5563 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5564 inner_comps, tf_inner_offset,
5565 ctx->oc_lds, 0, 1, 0, true, false);
5566 }
5567 }
5568 ac_nir_build_endif(&if_ctx);
5569 }
5570
5571 static void
5572 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5573 {
5574 write_tess_factors(ctx);
5575 }
5576
5577 static bool
5578 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5579 LLVMValueRef *color, unsigned param, bool is_last,
5580 struct ac_export_args *args)
5581 {
5582 /* Export */
5583 si_llvm_init_export_args(ctx, color, param,
5584 args);
5585
5586 if (is_last) {
5587 args->valid_mask = 1; /* whether the EXEC mask is valid */
5588 args->done = 1; /* DONE bit */
5589 } else if (!args->enabled_channels)
5590 return false; /* unnecessary NULL export */
5591
5592 return true;
5593 }
5594
5595 static void
5596 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5597 LLVMValueRef depth, LLVMValueRef stencil,
5598 LLVMValueRef samplemask)
5599 {
5600 struct ac_export_args args;
5601
5602 args.enabled_channels = 0;
5603 args.valid_mask = 1;
5604 args.done = 1;
5605 args.target = V_008DFC_SQ_EXP_MRTZ;
5606 args.compr = false;
5607
5608 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5609 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5610 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5611 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5612
5613 if (depth) {
5614 args.out[0] = depth;
5615 args.enabled_channels |= 0x1;
5616 }
5617
5618 if (stencil) {
5619 args.out[1] = stencil;
5620 args.enabled_channels |= 0x2;
5621 }
5622
5623 if (samplemask) {
5624 args.out[2] = samplemask;
5625 args.enabled_channels |= 0x4;
5626 }
5627
5628 /* SI (except OLAND) has a bug that it only looks
5629 * at the X writemask component. */
5630 if (ctx->options->chip_class == SI &&
5631 ctx->options->family != CHIP_OLAND)
5632 args.enabled_channels |= 0x1;
5633
5634 ac_build_export(&ctx->ac, &args);
5635 }
5636
5637 static void
5638 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5639 {
5640 unsigned index = 0;
5641 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5642 struct ac_export_args color_args[8];
5643
5644 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5645 LLVMValueRef values[4];
5646
5647 if (!(ctx->output_mask & (1ull << i)))
5648 continue;
5649
5650 if (i == FRAG_RESULT_DEPTH) {
5651 ctx->shader_info->fs.writes_z = true;
5652 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
5653 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5654 } else if (i == FRAG_RESULT_STENCIL) {
5655 ctx->shader_info->fs.writes_stencil = true;
5656 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
5657 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5658 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5659 ctx->shader_info->fs.writes_sample_mask = true;
5660 samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
5661 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5662 } else {
5663 bool last = false;
5664 for (unsigned j = 0; j < 4; j++)
5665 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
5666 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5667
5668 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5669 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5670
5671 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5672 if (ret)
5673 index++;
5674 }
5675 }
5676
5677 for (unsigned i = 0; i < index; i++)
5678 ac_build_export(&ctx->ac, &color_args[i]);
5679 if (depth || stencil || samplemask)
5680 si_export_mrt_z(ctx, depth, stencil, samplemask);
5681 else if (!index) {
5682 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5683 ac_build_export(&ctx->ac, &color_args[0]);
5684 }
5685
5686 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5687 }
5688
5689 static void
5690 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5691 {
5692 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5693 }
5694
5695 static void
5696 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5697 {
5698 switch (ctx->stage) {
5699 case MESA_SHADER_VERTEX:
5700 if (ctx->options->key.vs.as_ls)
5701 handle_ls_outputs_post(ctx);
5702 else if (ctx->options->key.vs.as_es)
5703 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5704 else
5705 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
5706 break;
5707 case MESA_SHADER_FRAGMENT:
5708 handle_fs_outputs_post(ctx);
5709 break;
5710 case MESA_SHADER_GEOMETRY:
5711 emit_gs_epilogue(ctx);
5712 break;
5713 case MESA_SHADER_TESS_CTRL:
5714 handle_tcs_outputs_post(ctx);
5715 break;
5716 case MESA_SHADER_TESS_EVAL:
5717 if (ctx->options->key.tes.as_es)
5718 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5719 else
5720 handle_vs_outputs_post(ctx, &ctx->shader_info->tes.outinfo);
5721 break;
5722 default:
5723 break;
5724 }
5725 }
5726
5727 static void
5728 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5729 struct nir_variable *variable, uint32_t *offset, int idx)
5730 {
5731 unsigned size = glsl_count_attribute_slots(variable->type, false);
5732 variable->data.driver_location = *offset;
5733 *offset += size;
5734 }
5735
5736 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5737 {
5738 LLVMPassManagerRef passmgr;
5739 /* Create the pass manager */
5740 passmgr = LLVMCreateFunctionPassManagerForModule(
5741 ctx->module);
5742
5743 /* This pass should eliminate all the load and store instructions */
5744 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5745
5746 /* Add some optimization passes */
5747 LLVMAddScalarReplAggregatesPass(passmgr);
5748 LLVMAddLICMPass(passmgr);
5749 LLVMAddAggressiveDCEPass(passmgr);
5750 LLVMAddCFGSimplificationPass(passmgr);
5751 LLVMAddInstructionCombiningPass(passmgr);
5752
5753 /* Run the pass */
5754 LLVMInitializeFunctionPassManager(passmgr);
5755 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5756 LLVMFinalizeFunctionPassManager(passmgr);
5757
5758 LLVMDisposeBuilder(ctx->builder);
5759 LLVMDisposePassManager(passmgr);
5760 }
5761
5762 static void
5763 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
5764 {
5765 struct ac_vs_output_info *outinfo;
5766
5767 if (ctx->stage == MESA_SHADER_FRAGMENT ||
5768 ctx->stage == MESA_SHADER_COMPUTE ||
5769 ctx->stage == MESA_SHADER_TESS_CTRL ||
5770 ctx->stage == MESA_SHADER_GEOMETRY)
5771 return;
5772
5773 if (ctx->stage == MESA_SHADER_VERTEX) {
5774 if (ctx->options->key.vs.as_ls ||
5775 ctx->options->key.vs.as_es)
5776 return;
5777 outinfo = &ctx->shader_info->vs.outinfo;
5778 }
5779
5780 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5781 if (ctx->options->key.vs.as_es)
5782 return;
5783 outinfo = &ctx->shader_info->tes.outinfo;
5784 }
5785
5786 ac_eliminate_const_vs_outputs(&ctx->ac,
5787 ctx->main_function,
5788 outinfo->vs_output_param_offset,
5789 VARYING_SLOT_MAX,
5790 &outinfo->param_exports);
5791 }
5792
5793 static void
5794 ac_setup_rings(struct nir_to_llvm_context *ctx)
5795 {
5796 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5797 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5798 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5799 }
5800
5801 if (ctx->is_gs_copy_shader) {
5802 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5803 }
5804 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5805 LLVMValueRef tmp;
5806 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5807 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5808
5809 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5810
5811 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5812 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5813 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5814 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5815
5816 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
5817 }
5818
5819 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5820 ctx->stage == MESA_SHADER_TESS_EVAL) {
5821 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5822 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5823 }
5824 }
5825
5826 static
5827 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5828 struct nir_shader *nir,
5829 struct ac_shader_variant_info *shader_info,
5830 const struct ac_nir_compiler_options *options)
5831 {
5832 struct nir_to_llvm_context ctx = {0};
5833 struct nir_function *func;
5834 unsigned i;
5835 ctx.options = options;
5836 ctx.shader_info = shader_info;
5837 ctx.context = LLVMContextCreate();
5838 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5839
5840 ac_llvm_context_init(&ctx.ac, ctx.context);
5841 ctx.ac.module = ctx.module;
5842
5843 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5844
5845 memset(shader_info, 0, sizeof(*shader_info));
5846
5847 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5848
5849 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5850
5851 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5852 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5853 LLVMSetDataLayout(ctx.module, data_layout_str);
5854 LLVMDisposeTargetData(data_layout);
5855 LLVMDisposeMessage(data_layout_str);
5856
5857 setup_types(&ctx);
5858
5859 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5860 ctx.ac.builder = ctx.builder;
5861 ctx.stage = nir->stage;
5862
5863 for (i = 0; i < AC_UD_MAX_SETS; i++)
5864 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5865 for (i = 0; i < AC_UD_MAX_UD; i++)
5866 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5867
5868 create_function(&ctx);
5869
5870 if (nir->stage == MESA_SHADER_COMPUTE) {
5871 int num_shared = 0;
5872 nir_foreach_variable(variable, &nir->shared)
5873 num_shared++;
5874 if (num_shared) {
5875 int idx = 0;
5876 uint32_t shared_size = 0;
5877 LLVMValueRef var;
5878 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5879 nir_foreach_variable(variable, &nir->shared) {
5880 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5881 idx++;
5882 }
5883
5884 shared_size *= 16;
5885 var = LLVMAddGlobalInAddressSpace(ctx.module,
5886 LLVMArrayType(ctx.i8, shared_size),
5887 "compute_lds",
5888 LOCAL_ADDR_SPACE);
5889 LLVMSetAlignment(var, 4);
5890 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5891 }
5892 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5893 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5894
5895 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
5896 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5897 ctx.tes_primitive_mode = nir->info->tess.primitive_mode;
5898 }
5899
5900 ac_setup_rings(&ctx);
5901
5902 nir_foreach_variable(variable, &nir->inputs)
5903 handle_shader_input_decl(&ctx, variable);
5904
5905 if (nir->stage == MESA_SHADER_FRAGMENT)
5906 handle_fs_inputs_pre(&ctx, nir);
5907
5908 ctx.num_output_clips = nir->info->clip_distance_array_size;
5909 ctx.num_output_culls = nir->info->cull_distance_array_size;
5910
5911 nir_foreach_variable(variable, &nir->outputs)
5912 handle_shader_output_decl(&ctx, variable);
5913
5914 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5915 _mesa_key_pointer_equal);
5916 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5917 _mesa_key_pointer_equal);
5918
5919 func = (struct nir_function *)exec_list_get_head(&nir->functions);
5920
5921 setup_locals(&ctx, func);
5922
5923 visit_cf_list(&ctx, &func->impl->body);
5924 phi_post_pass(&ctx);
5925
5926 handle_shader_outputs_post(&ctx);
5927 LLVMBuildRetVoid(ctx.builder);
5928
5929 ac_llvm_finalize_module(&ctx);
5930
5931 ac_nir_eliminate_const_vs_outputs(&ctx);
5932 free(ctx.locals);
5933 ralloc_free(ctx.defs);
5934 ralloc_free(ctx.phis);
5935
5936 if (nir->stage == MESA_SHADER_GEOMETRY) {
5937 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
5938 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
5939 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
5940 nir->info->gs.vertices_out;
5941 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
5942 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
5943 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
5944 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
5945 shader_info->vs.outputs_written = ctx.tess_outputs_written;
5946 }
5947
5948 return ctx.module;
5949 }
5950
5951 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
5952 {
5953 unsigned *retval = (unsigned *)context;
5954 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
5955 char *description = LLVMGetDiagInfoDescription(di);
5956
5957 if (severity == LLVMDSError) {
5958 *retval = 1;
5959 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
5960 description);
5961 }
5962
5963 LLVMDisposeMessage(description);
5964 }
5965
5966 static unsigned ac_llvm_compile(LLVMModuleRef M,
5967 struct ac_shader_binary *binary,
5968 LLVMTargetMachineRef tm)
5969 {
5970 unsigned retval = 0;
5971 char *err;
5972 LLVMContextRef llvm_ctx;
5973 LLVMMemoryBufferRef out_buffer;
5974 unsigned buffer_size;
5975 const char *buffer_data;
5976 LLVMBool mem_err;
5977
5978 /* Setup Diagnostic Handler*/
5979 llvm_ctx = LLVMGetModuleContext(M);
5980
5981 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
5982 &retval);
5983
5984 /* Compile IR*/
5985 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
5986 &err, &out_buffer);
5987
5988 /* Process Errors/Warnings */
5989 if (mem_err) {
5990 fprintf(stderr, "%s: %s", __FUNCTION__, err);
5991 free(err);
5992 retval = 1;
5993 goto out;
5994 }
5995
5996 /* Extract Shader Code*/
5997 buffer_size = LLVMGetBufferSize(out_buffer);
5998 buffer_data = LLVMGetBufferStart(out_buffer);
5999
6000 ac_elf_read(buffer_data, buffer_size, binary);
6001
6002 /* Clean up */
6003 LLVMDisposeMemoryBuffer(out_buffer);
6004
6005 out:
6006 return retval;
6007 }
6008
6009 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6010 LLVMModuleRef llvm_module,
6011 struct ac_shader_binary *binary,
6012 struct ac_shader_config *config,
6013 struct ac_shader_variant_info *shader_info,
6014 gl_shader_stage stage,
6015 bool dump_shader, bool supports_spill)
6016 {
6017 if (dump_shader)
6018 ac_dump_module(llvm_module);
6019
6020 memset(binary, 0, sizeof(*binary));
6021 int v = ac_llvm_compile(llvm_module, binary, tm);
6022 if (v) {
6023 fprintf(stderr, "compile failed\n");
6024 }
6025
6026 if (dump_shader)
6027 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6028
6029 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6030
6031 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6032 LLVMDisposeModule(llvm_module);
6033 LLVMContextDispose(ctx);
6034
6035 if (stage == MESA_SHADER_FRAGMENT) {
6036 shader_info->num_input_vgprs = 0;
6037 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6038 shader_info->num_input_vgprs += 2;
6039 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6040 shader_info->num_input_vgprs += 2;
6041 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6042 shader_info->num_input_vgprs += 2;
6043 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6044 shader_info->num_input_vgprs += 3;
6045 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6046 shader_info->num_input_vgprs += 2;
6047 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6048 shader_info->num_input_vgprs += 2;
6049 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6050 shader_info->num_input_vgprs += 2;
6051 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6052 shader_info->num_input_vgprs += 1;
6053 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6054 shader_info->num_input_vgprs += 1;
6055 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6056 shader_info->num_input_vgprs += 1;
6057 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6058 shader_info->num_input_vgprs += 1;
6059 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6060 shader_info->num_input_vgprs += 1;
6061 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6062 shader_info->num_input_vgprs += 1;
6063 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6064 shader_info->num_input_vgprs += 1;
6065 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6066 shader_info->num_input_vgprs += 1;
6067 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6068 shader_info->num_input_vgprs += 1;
6069 }
6070 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6071
6072 /* +3 for scratch wave offset and VCC */
6073 config->num_sgprs = MAX2(config->num_sgprs,
6074 shader_info->num_input_sgprs + 3);
6075 }
6076
6077 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6078 struct ac_shader_binary *binary,
6079 struct ac_shader_config *config,
6080 struct ac_shader_variant_info *shader_info,
6081 struct nir_shader *nir,
6082 const struct ac_nir_compiler_options *options,
6083 bool dump_shader)
6084 {
6085
6086 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6087 options);
6088
6089 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6090 switch (nir->stage) {
6091 case MESA_SHADER_COMPUTE:
6092 for (int i = 0; i < 3; ++i)
6093 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
6094 break;
6095 case MESA_SHADER_FRAGMENT:
6096 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
6097 break;
6098 case MESA_SHADER_GEOMETRY:
6099 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
6100 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
6101 shader_info->gs.output_prim = nir->info->gs.output_primitive;
6102 shader_info->gs.invocations = nir->info->gs.invocations;
6103 break;
6104 case MESA_SHADER_TESS_EVAL:
6105 shader_info->tes.primitive_mode = nir->info->tess.primitive_mode;
6106 shader_info->tes.spacing = nir->info->tess.spacing;
6107 shader_info->tes.ccw = nir->info->tess.ccw;
6108 shader_info->tes.point_mode = nir->info->tess.point_mode;
6109 shader_info->tes.as_es = options->key.tes.as_es;
6110 break;
6111 case MESA_SHADER_TESS_CTRL:
6112 shader_info->tcs.tcs_vertices_out = nir->info->tess.tcs_vertices_out;
6113 break;
6114 case MESA_SHADER_VERTEX:
6115 shader_info->vs.as_es = options->key.vs.as_es;
6116 shader_info->vs.as_ls = options->key.vs.as_ls;
6117 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6118 if (options->key.vs.as_ls)
6119 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6120 break;
6121 default:
6122 break;
6123 }
6124 }
6125
6126 static void
6127 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6128 {
6129 LLVMValueRef args[9];
6130 args[0] = ctx->gsvs_ring;
6131 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6132 args[3] = ctx->i32zero;
6133 args[4] = ctx->i32one; /* OFFEN */
6134 args[5] = ctx->i32zero; /* IDXEN */
6135 args[6] = ctx->i32one; /* GLC */
6136 args[7] = ctx->i32one; /* SLC */
6137 args[8] = ctx->i32zero; /* TFE */
6138
6139 int idx = 0;
6140
6141 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6142 int length = 4;
6143 int slot = idx;
6144 int slot_inc = 1;
6145 if (!(ctx->output_mask & (1ull << i)))
6146 continue;
6147
6148 if (i == VARYING_SLOT_CLIP_DIST0) {
6149 /* unpack clip and cull from a single set of slots */
6150 length = ctx->num_output_clips + ctx->num_output_culls;
6151 if (length > 4)
6152 slot_inc = 2;
6153 }
6154
6155 for (unsigned j = 0; j < length; j++) {
6156 LLVMValueRef value;
6157 args[2] = LLVMConstInt(ctx->i32,
6158 (slot * 4 + j) *
6159 ctx->gs_max_out_vertices * 16 * 4, false);
6160
6161 value = ac_build_intrinsic(&ctx->ac,
6162 "llvm.SI.buffer.load.dword.i32.i32",
6163 ctx->i32, args, 9,
6164 AC_FUNC_ATTR_READONLY |
6165 AC_FUNC_ATTR_LEGACY);
6166
6167 LLVMBuildStore(ctx->builder,
6168 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6169 }
6170 idx += slot_inc;
6171 }
6172 handle_vs_outputs_post(ctx, &ctx->shader_info->vs.outinfo);
6173 }
6174
6175 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6176 struct nir_shader *geom_shader,
6177 struct ac_shader_binary *binary,
6178 struct ac_shader_config *config,
6179 struct ac_shader_variant_info *shader_info,
6180 const struct ac_nir_compiler_options *options,
6181 bool dump_shader)
6182 {
6183 struct nir_to_llvm_context ctx = {0};
6184 ctx.context = LLVMContextCreate();
6185 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6186 ctx.options = options;
6187 ctx.shader_info = shader_info;
6188
6189 ac_llvm_context_init(&ctx.ac, ctx.context);
6190 ctx.ac.module = ctx.module;
6191
6192 ctx.is_gs_copy_shader = true;
6193 LLVMSetTarget(ctx.module, "amdgcn--");
6194 setup_types(&ctx);
6195
6196 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6197 ctx.ac.builder = ctx.builder;
6198 ctx.stage = MESA_SHADER_VERTEX;
6199
6200 create_function(&ctx);
6201
6202 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
6203 ac_setup_rings(&ctx);
6204
6205 ctx.num_output_clips = geom_shader->info->clip_distance_array_size;
6206 ctx.num_output_culls = geom_shader->info->cull_distance_array_size;
6207
6208 nir_foreach_variable(variable, &geom_shader->outputs)
6209 handle_shader_output_decl(&ctx, variable);
6210
6211 ac_gs_copy_shader_emit(&ctx);
6212
6213 LLVMBuildRetVoid(ctx.builder);
6214
6215 ac_llvm_finalize_module(&ctx);
6216
6217 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6218 MESA_SHADER_VERTEX,
6219 dump_shader, options->supports_spill);
6220 }