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ac/nir: add image and write parameter to ac_shader_abi::load_sampler_desc
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 struct nir_to_llvm_context;
51
52 struct ac_nir_context {
53 struct ac_llvm_context ac;
54 struct ac_shader_abi *abi;
55
56 gl_shader_stage stage;
57
58 struct hash_table *defs;
59 struct hash_table *phis;
60 struct hash_table *vars;
61
62 LLVMValueRef main_function;
63 LLVMBasicBlockRef continue_block;
64 LLVMBasicBlockRef break_block;
65
66 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
67
68 int num_locals;
69 LLVMValueRef *locals;
70
71 struct nir_to_llvm_context *nctx; /* TODO get rid of this */
72 };
73
74 struct nir_to_llvm_context {
75 struct ac_llvm_context ac;
76 const struct ac_nir_compiler_options *options;
77 struct ac_shader_variant_info *shader_info;
78 struct ac_shader_abi abi;
79 struct ac_nir_context *nir;
80
81 unsigned max_workgroup_size;
82 LLVMContextRef context;
83 LLVMModuleRef module;
84 LLVMBuilderRef builder;
85 LLVMValueRef main_function;
86
87 struct hash_table *defs;
88 struct hash_table *phis;
89
90 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
91 LLVMValueRef ring_offsets;
92 LLVMValueRef push_constants;
93 LLVMValueRef num_work_groups;
94 LLVMValueRef workgroup_ids;
95 LLVMValueRef local_invocation_ids;
96 LLVMValueRef tg_size;
97
98 LLVMValueRef vertex_buffers;
99 LLVMValueRef rel_auto_id;
100 LLVMValueRef vs_prim_id;
101 LLVMValueRef ls_out_layout;
102 LLVMValueRef es2gs_offset;
103
104 LLVMValueRef tcs_offchip_layout;
105 LLVMValueRef tcs_out_offsets;
106 LLVMValueRef tcs_out_layout;
107 LLVMValueRef tcs_in_layout;
108 LLVMValueRef oc_lds;
109 LLVMValueRef tess_factor_offset;
110 LLVMValueRef tcs_patch_id;
111 LLVMValueRef tcs_rel_ids;
112 LLVMValueRef tes_rel_patch_id;
113 LLVMValueRef tes_patch_id;
114 LLVMValueRef tes_u;
115 LLVMValueRef tes_v;
116
117 LLVMValueRef gsvs_ring_stride;
118 LLVMValueRef gsvs_num_entries;
119 LLVMValueRef gs2vs_offset;
120 LLVMValueRef gs_wave_id;
121 LLVMValueRef gs_vtx_offset[6];
122 LLVMValueRef gs_prim_id, gs_invocation_id;
123
124 LLVMValueRef esgs_ring;
125 LLVMValueRef gsvs_ring;
126 LLVMValueRef hs_ring_tess_offchip;
127 LLVMValueRef hs_ring_tess_factor;
128
129 LLVMValueRef prim_mask;
130 LLVMValueRef sample_pos_offset;
131 LLVMValueRef persp_sample, persp_center, persp_centroid;
132 LLVMValueRef linear_sample, linear_center, linear_centroid;
133 LLVMValueRef front_face;
134 LLVMValueRef ancillary;
135 LLVMValueRef sample_coverage;
136 LLVMValueRef frag_pos[4];
137
138 LLVMTypeRef i1;
139 LLVMTypeRef i8;
140 LLVMTypeRef i16;
141 LLVMTypeRef i32;
142 LLVMTypeRef i64;
143 LLVMTypeRef v2i32;
144 LLVMTypeRef v3i32;
145 LLVMTypeRef v4i32;
146 LLVMTypeRef v8i32;
147 LLVMTypeRef f64;
148 LLVMTypeRef f32;
149 LLVMTypeRef f16;
150 LLVMTypeRef v2f32;
151 LLVMTypeRef v4f32;
152 LLVMTypeRef voidt;
153
154 LLVMValueRef i1true;
155 LLVMValueRef i1false;
156 LLVMValueRef i32zero;
157 LLVMValueRef i32one;
158 LLVMValueRef f32zero;
159 LLVMValueRef f32one;
160 LLVMValueRef v4f32empty;
161
162 unsigned uniform_md_kind;
163 LLVMValueRef empty_md;
164 gl_shader_stage stage;
165
166 LLVMValueRef lds;
167 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
168
169 uint64_t input_mask;
170 uint64_t output_mask;
171 uint8_t num_output_clips;
172 uint8_t num_output_culls;
173
174 bool has_ds_bpermute;
175
176 bool is_gs_copy_shader;
177 LLVMValueRef gs_next_vertex;
178 unsigned gs_max_out_vertices;
179
180 unsigned tes_primitive_mode;
181 uint64_t tess_outputs_written;
182 uint64_t tess_patch_outputs_written;
183 };
184
185 static inline struct nir_to_llvm_context *
186 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
187 {
188 struct nir_to_llvm_context *ctx = NULL;
189 return container_of(abi, ctx, abi);
190 }
191
192 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
193 const nir_deref_var *deref,
194 enum ac_descriptor_type desc_type,
195 bool image, bool write);
196
197 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
198 {
199 return (index * 4) + chan;
200 }
201
202 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
203 {
204 /* handle patch indices separate */
205 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
206 return 0;
207 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
208 return 1;
209 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
210 return 2 + (slot - VARYING_SLOT_PATCH0);
211
212 if (slot == VARYING_SLOT_POS)
213 return 0;
214 if (slot == VARYING_SLOT_PSIZ)
215 return 1;
216 if (slot == VARYING_SLOT_CLIP_DIST0)
217 return 2;
218 /* 3 is reserved for clip dist as well */
219 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
220 return 4 + (slot - VARYING_SLOT_VAR0);
221 unreachable("illegal slot in get unique index\n");
222 }
223
224 static unsigned llvm_get_type_size(LLVMTypeRef type)
225 {
226 LLVMTypeKind kind = LLVMGetTypeKind(type);
227
228 switch (kind) {
229 case LLVMIntegerTypeKind:
230 return LLVMGetIntTypeWidth(type) / 8;
231 case LLVMFloatTypeKind:
232 return 4;
233 case LLVMPointerTypeKind:
234 return 8;
235 case LLVMVectorTypeKind:
236 return LLVMGetVectorSize(type) *
237 llvm_get_type_size(LLVMGetElementType(type));
238 default:
239 assert(0);
240 return 0;
241 }
242 }
243
244 static void set_llvm_calling_convention(LLVMValueRef func,
245 gl_shader_stage stage)
246 {
247 enum radeon_llvm_calling_convention calling_conv;
248
249 switch (stage) {
250 case MESA_SHADER_VERTEX:
251 case MESA_SHADER_TESS_CTRL:
252 case MESA_SHADER_TESS_EVAL:
253 calling_conv = RADEON_LLVM_AMDGPU_VS;
254 break;
255 case MESA_SHADER_GEOMETRY:
256 calling_conv = RADEON_LLVM_AMDGPU_GS;
257 break;
258 case MESA_SHADER_FRAGMENT:
259 calling_conv = RADEON_LLVM_AMDGPU_PS;
260 break;
261 case MESA_SHADER_COMPUTE:
262 calling_conv = RADEON_LLVM_AMDGPU_CS;
263 break;
264 default:
265 unreachable("Unhandle shader type");
266 }
267
268 LLVMSetFunctionCallConv(func, calling_conv);
269 }
270
271 #define MAX_ARGS 23
272 struct arg_info {
273 LLVMTypeRef types[MAX_ARGS];
274 LLVMValueRef *assign[MAX_ARGS];
275 unsigned array_params_mask;
276 uint8_t count;
277 uint8_t user_sgpr_count;
278 uint8_t sgpr_count;
279 uint8_t num_user_sgprs_used;
280 uint8_t num_sgprs_used;
281 uint8_t num_vgprs_used;
282 };
283
284 static inline void
285 add_argument(struct arg_info *info,
286 LLVMTypeRef type, LLVMValueRef *param_ptr)
287 {
288 assert(info->count < MAX_ARGS);
289 info->assign[info->count] = param_ptr;
290 info->types[info->count] = type;
291 info->count++;
292 }
293
294 static inline void
295 add_sgpr_argument(struct arg_info *info,
296 LLVMTypeRef type, LLVMValueRef *param_ptr)
297 {
298 add_argument(info, type, param_ptr);
299 info->num_sgprs_used += llvm_get_type_size(type) / 4;
300 info->sgpr_count++;
301 }
302
303 static inline void
304 add_user_sgpr_argument(struct arg_info *info,
305 LLVMTypeRef type,
306 LLVMValueRef *param_ptr)
307 {
308 add_sgpr_argument(info, type, param_ptr);
309 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
310 info->user_sgpr_count++;
311 }
312
313 static inline void
314 add_vgpr_argument(struct arg_info *info,
315 LLVMTypeRef type,
316 LLVMValueRef *param_ptr)
317 {
318 add_argument(info, type, param_ptr);
319 info->num_vgprs_used += llvm_get_type_size(type) / 4;
320 }
321
322 static inline void
323 add_user_sgpr_array_argument(struct arg_info *info,
324 LLVMTypeRef type,
325 LLVMValueRef *param_ptr)
326 {
327 info->array_params_mask |= (1 << info->count);
328 add_user_sgpr_argument(info, type, param_ptr);
329 }
330
331 static void assign_arguments(LLVMValueRef main_function,
332 struct arg_info *info)
333 {
334 unsigned i;
335 for (i = 0; i < info->count; i++) {
336 if (info->assign[i])
337 *info->assign[i] = LLVMGetParam(main_function, i);
338 }
339 }
340
341 static LLVMValueRef
342 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
343 LLVMBuilderRef builder, LLVMTypeRef *return_types,
344 unsigned num_return_elems,
345 struct arg_info *args,
346 unsigned max_workgroup_size,
347 bool unsafe_math)
348 {
349 LLVMTypeRef main_function_type, ret_type;
350 LLVMBasicBlockRef main_function_body;
351
352 if (num_return_elems)
353 ret_type = LLVMStructTypeInContext(ctx, return_types,
354 num_return_elems, true);
355 else
356 ret_type = LLVMVoidTypeInContext(ctx);
357
358 /* Setup the function */
359 main_function_type =
360 LLVMFunctionType(ret_type, args->types, args->count, 0);
361 LLVMValueRef main_function =
362 LLVMAddFunction(module, "main", main_function_type);
363 main_function_body =
364 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
365 LLVMPositionBuilderAtEnd(builder, main_function_body);
366
367 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
368 for (unsigned i = 0; i < args->sgpr_count; ++i) {
369 if (args->array_params_mask & (1 << i)) {
370 LLVMValueRef P = LLVMGetParam(main_function, i);
371 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
372 ac_add_attr_dereferenceable(P, UINT64_MAX);
373 }
374 else {
375 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
376 }
377 }
378
379 if (max_workgroup_size) {
380 ac_llvm_add_target_dep_function_attr(main_function,
381 "amdgpu-max-work-group-size",
382 max_workgroup_size);
383 }
384 if (unsafe_math) {
385 /* These were copied from some LLVM test. */
386 LLVMAddTargetDependentFunctionAttr(main_function,
387 "less-precise-fpmad",
388 "true");
389 LLVMAddTargetDependentFunctionAttr(main_function,
390 "no-infs-fp-math",
391 "true");
392 LLVMAddTargetDependentFunctionAttr(main_function,
393 "no-nans-fp-math",
394 "true");
395 LLVMAddTargetDependentFunctionAttr(main_function,
396 "unsafe-fp-math",
397 "true");
398 }
399 return main_function;
400 }
401
402 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
403 {
404 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
405 CONST_ADDR_SPACE);
406 }
407
408 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
409 {
410 if (t == ctx->f16 || t == ctx->i16)
411 return ctx->i16;
412 else if (t == ctx->f32 || t == ctx->i32)
413 return ctx->i32;
414 else if (t == ctx->f64 || t == ctx->i64)
415 return ctx->i64;
416 else
417 unreachable("Unhandled integer size");
418 }
419
420 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
421 {
422 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
423 LLVMTypeRef elem_type = LLVMGetElementType(t);
424 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
425 LLVMGetVectorSize(t));
426 }
427 return to_integer_type_scalar(ctx, t);
428 }
429
430 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
431 {
432 LLVMTypeRef type = LLVMTypeOf(v);
433 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
434 }
435
436 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
437 {
438 if (t == ctx->i16 || t == ctx->f16)
439 return ctx->f16;
440 else if (t == ctx->i32 || t == ctx->f32)
441 return ctx->f32;
442 else if (t == ctx->i64 || t == ctx->f64)
443 return ctx->f64;
444 else
445 unreachable("Unhandled float size");
446 }
447
448 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
449 {
450 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
451 LLVMTypeRef elem_type = LLVMGetElementType(t);
452 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
453 LLVMGetVectorSize(t));
454 }
455 return to_float_type_scalar(ctx, t);
456 }
457
458 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
459 {
460 LLVMTypeRef type = LLVMTypeOf(v);
461 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
462 }
463
464 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
465 {
466 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
467 type = LLVMGetElementType(type);
468
469 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
470 return LLVMGetIntTypeWidth(type);
471
472 if (type == ctx->f16)
473 return 16;
474 if (type == ctx->f32)
475 return 32;
476 if (type == ctx->f64)
477 return 64;
478
479 unreachable("Unhandled type kind in get_elem_bits");
480 }
481
482 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
483 LLVMValueRef param, unsigned rshift,
484 unsigned bitwidth)
485 {
486 LLVMValueRef value = param;
487 if (rshift)
488 value = LLVMBuildLShr(ctx->builder, value,
489 LLVMConstInt(ctx->i32, rshift, false), "");
490
491 if (rshift + bitwidth < 32) {
492 unsigned mask = (1 << bitwidth) - 1;
493 value = LLVMBuildAnd(ctx->builder, value,
494 LLVMConstInt(ctx->i32, mask, false), "");
495 }
496 return value;
497 }
498
499 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
500 {
501 switch (ctx->stage) {
502 case MESA_SHADER_TESS_CTRL:
503 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
504 case MESA_SHADER_TESS_EVAL:
505 return ctx->tes_rel_patch_id;
506 break;
507 default:
508 unreachable("Illegal stage");
509 }
510 }
511
512 /* Tessellation shaders pass outputs to the next shader using LDS.
513 *
514 * LS outputs = TCS inputs
515 * TCS outputs = TES inputs
516 *
517 * The LDS layout is:
518 * - TCS inputs for patch 0
519 * - TCS inputs for patch 1
520 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
521 * - ...
522 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
523 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
524 * - TCS outputs for patch 1
525 * - Per-patch TCS outputs for patch 1
526 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
527 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
528 * - ...
529 *
530 * All three shaders VS(LS), TCS, TES share the same LDS space.
531 */
532 static LLVMValueRef
533 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
534 {
535 if (ctx->stage == MESA_SHADER_VERTEX)
536 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
537 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
538 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
539 else {
540 assert(0);
541 return NULL;
542 }
543 }
544
545 static LLVMValueRef
546 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
547 {
548 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
549 }
550
551 static LLVMValueRef
552 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
553 {
554 return LLVMBuildMul(ctx->builder,
555 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
556 LLVMConstInt(ctx->i32, 4, false), "");
557 }
558
559 static LLVMValueRef
560 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
561 {
562 return LLVMBuildMul(ctx->builder,
563 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
564 LLVMConstInt(ctx->i32, 4, false), "");
565 }
566
567 static LLVMValueRef
568 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
569 {
570 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
571 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
572
573 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
574 }
575
576 static LLVMValueRef
577 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
578 {
579 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
580 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
581 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
582
583 return LLVMBuildAdd(ctx->builder, patch0_offset,
584 LLVMBuildMul(ctx->builder, patch_stride,
585 rel_patch_id, ""),
586 "");
587 }
588
589 static LLVMValueRef
590 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
591 {
592 LLVMValueRef patch0_patch_data_offset =
593 get_tcs_out_patch0_patch_data_offset(ctx);
594 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
595 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
596
597 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
598 LLVMBuildMul(ctx->builder, patch_stride,
599 rel_patch_id, ""),
600 "");
601 }
602
603 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
604 {
605 ud_info->sgpr_idx = *sgpr_idx;
606 ud_info->num_sgprs = num_sgprs;
607 ud_info->indirect = false;
608 ud_info->indirect_offset = 0;
609 *sgpr_idx += num_sgprs;
610 }
611
612 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
613 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
614 {
615 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
616 }
617
618
619 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
620 uint32_t indirect_offset)
621 {
622 ud_info->sgpr_idx = sgpr_idx;
623 ud_info->num_sgprs = num_sgprs;
624 ud_info->indirect = true;
625 ud_info->indirect_offset = indirect_offset;
626 }
627
628 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
629 {
630 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
631 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
632 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
633 "tess_lds");
634 }
635
636 struct user_sgpr_info {
637 bool need_ring_offsets;
638 uint8_t sgpr_count;
639 bool indirect_all_descriptor_sets;
640 };
641
642 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
643 struct user_sgpr_info *user_sgpr_info)
644 {
645 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
646
647 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
648 if (ctx->stage == MESA_SHADER_GEOMETRY ||
649 ctx->stage == MESA_SHADER_VERTEX ||
650 ctx->stage == MESA_SHADER_TESS_CTRL ||
651 ctx->stage == MESA_SHADER_TESS_EVAL ||
652 ctx->is_gs_copy_shader)
653 user_sgpr_info->need_ring_offsets = true;
654
655 if (ctx->stage == MESA_SHADER_FRAGMENT &&
656 ctx->shader_info->info.ps.needs_sample_positions)
657 user_sgpr_info->need_ring_offsets = true;
658
659 /* 2 user sgprs will nearly always be allocated for scratch/rings */
660 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
661 user_sgpr_info->sgpr_count += 2;
662 }
663
664 switch (ctx->stage) {
665 case MESA_SHADER_COMPUTE:
666 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
667 break;
668 case MESA_SHADER_FRAGMENT:
669 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
670 break;
671 case MESA_SHADER_VERTEX:
672 if (!ctx->is_gs_copy_shader) {
673 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
674 if (ctx->shader_info->info.vs.needs_draw_id) {
675 user_sgpr_info->sgpr_count += 3;
676 } else {
677 user_sgpr_info->sgpr_count += 2;
678 }
679 }
680 if (ctx->options->key.vs.as_ls)
681 user_sgpr_info->sgpr_count++;
682 break;
683 case MESA_SHADER_TESS_CTRL:
684 user_sgpr_info->sgpr_count += 4;
685 break;
686 case MESA_SHADER_TESS_EVAL:
687 user_sgpr_info->sgpr_count += 1;
688 break;
689 case MESA_SHADER_GEOMETRY:
690 user_sgpr_info->sgpr_count += 2;
691 break;
692 default:
693 break;
694 }
695
696 if (ctx->shader_info->info.needs_push_constants)
697 user_sgpr_info->sgpr_count += 2;
698
699 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
700 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
701 user_sgpr_info->sgpr_count += 2;
702 user_sgpr_info->indirect_all_descriptor_sets = true;
703 } else {
704 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
705 }
706 }
707
708 static void create_function(struct nir_to_llvm_context *ctx)
709 {
710 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
711 uint8_t user_sgpr_idx;
712 struct user_sgpr_info user_sgpr_info;
713 struct arg_info args = {};
714 LLVMValueRef desc_sets;
715
716 allocate_user_sgprs(ctx, &user_sgpr_info);
717 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
718 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
719 }
720
721 /* 1 for each descriptor set */
722 if (!user_sgpr_info.indirect_all_descriptor_sets) {
723 for (unsigned i = 0; i < num_sets; ++i) {
724 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
725 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
726 }
727 }
728 } else
729 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
730
731 if (ctx->shader_info->info.needs_push_constants) {
732 /* 1 for push constants and dynamic descriptors */
733 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
734 }
735
736 switch (ctx->stage) {
737 case MESA_SHADER_COMPUTE:
738 if (ctx->shader_info->info.cs.grid_components_used)
739 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
740 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
741 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
742 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
743 break;
744 case MESA_SHADER_VERTEX:
745 if (!ctx->is_gs_copy_shader) {
746 if (ctx->shader_info->info.vs.has_vertex_buffers)
747 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
748 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
749 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
750 if (ctx->shader_info->info.vs.needs_draw_id)
751 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
752 }
753 if (ctx->options->key.vs.as_es)
754 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
755 else if (ctx->options->key.vs.as_ls)
756 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
757 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
758 if (!ctx->is_gs_copy_shader) {
759 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
760 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
761 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
762 }
763 break;
764 case MESA_SHADER_TESS_CTRL:
765 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
766 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
767 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
768 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
769 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
770 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
771 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
772 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
773 break;
774 case MESA_SHADER_TESS_EVAL:
775 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
776 if (ctx->options->key.tes.as_es) {
777 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
778 add_sgpr_argument(&args, ctx->i32, NULL); //
779 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
780 } else {
781 add_sgpr_argument(&args, ctx->i32, NULL); //
782 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
783 }
784 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
785 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
786 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
787 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
788 break;
789 case MESA_SHADER_GEOMETRY:
790 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
791 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
792 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
793 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
796 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
798 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
799 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
800 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
801 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
802 break;
803 case MESA_SHADER_FRAGMENT:
804 if (ctx->shader_info->info.ps.needs_sample_positions)
805 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
806 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
808 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
809 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
810 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
811 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
812 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
813 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
814 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
815 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
816 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
817 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
818 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
819 add_vgpr_argument(&args, ctx->i32, &ctx->front_face); /* front face */
820 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
821 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
822 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
823 break;
824 default:
825 unreachable("Shader stage not implemented");
826 }
827
828 ctx->main_function = create_llvm_function(
829 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
830 ctx->max_workgroup_size,
831 ctx->options->unsafe_math);
832 set_llvm_calling_convention(ctx->main_function, ctx->stage);
833
834
835 ctx->shader_info->num_input_vgprs = 0;
836 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
837 ctx->options->supports_spill ? 2 : 0;
838
839 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
840 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
841
842 if (ctx->stage != MESA_SHADER_FRAGMENT)
843 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
844
845 assign_arguments(ctx->main_function, &args);
846
847 user_sgpr_idx = 0;
848
849 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
850 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
851 if (ctx->options->supports_spill) {
852 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
853 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
854 NULL, 0, AC_FUNC_ATTR_READNONE);
855 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
856 const_array(ctx->v4i32, 16), "");
857 }
858 }
859
860 if (!user_sgpr_info.indirect_all_descriptor_sets) {
861 for (unsigned i = 0; i < num_sets; ++i) {
862 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
863 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
864 } else
865 ctx->descriptor_sets[i] = NULL;
866 }
867 } else {
868 uint32_t desc_sgpr_idx = user_sgpr_idx;
869 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
870
871 for (unsigned i = 0; i < num_sets; ++i) {
872 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
873 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
874 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
875
876 } else
877 ctx->descriptor_sets[i] = NULL;
878 }
879 ctx->shader_info->need_indirect_descriptor_sets = true;
880 }
881
882 if (ctx->shader_info->info.needs_push_constants) {
883 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
884 }
885
886 switch (ctx->stage) {
887 case MESA_SHADER_COMPUTE:
888 if (ctx->shader_info->info.cs.grid_components_used) {
889 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
890 }
891 break;
892 case MESA_SHADER_VERTEX:
893 if (!ctx->is_gs_copy_shader) {
894 if (ctx->shader_info->info.vs.has_vertex_buffers) {
895 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
896 }
897 unsigned vs_num = 2;
898 if (ctx->shader_info->info.vs.needs_draw_id)
899 vs_num++;
900
901 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
902 }
903 if (ctx->options->key.vs.as_ls) {
904 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
905 }
906 if (ctx->options->key.vs.as_ls)
907 declare_tess_lds(ctx);
908 break;
909 case MESA_SHADER_TESS_CTRL:
910 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
911 declare_tess_lds(ctx);
912 break;
913 case MESA_SHADER_TESS_EVAL:
914 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
915 break;
916 case MESA_SHADER_GEOMETRY:
917 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
918 break;
919 case MESA_SHADER_FRAGMENT:
920 if (ctx->shader_info->info.ps.needs_sample_positions) {
921 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
922 }
923 break;
924 default:
925 unreachable("Shader stage not implemented");
926 }
927 }
928
929 static void setup_types(struct nir_to_llvm_context *ctx)
930 {
931 LLVMValueRef args[4];
932
933 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
934 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
935 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
936 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
937 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
938 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
939 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
940 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
941 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
942 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
943 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
944 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
945 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
946 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
947 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
948
949 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
950 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
951 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
952 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
953 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
954 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
955
956 args[0] = ctx->f32zero;
957 args[1] = ctx->f32zero;
958 args[2] = ctx->f32zero;
959 args[3] = ctx->f32one;
960 ctx->v4f32empty = LLVMConstVector(args, 4);
961
962 ctx->uniform_md_kind =
963 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
964 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
965
966 args[0] = LLVMConstReal(ctx->f32, 2.5);
967 }
968
969 static int get_llvm_num_components(LLVMValueRef value)
970 {
971 LLVMTypeRef type = LLVMTypeOf(value);
972 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
973 ? LLVMGetVectorSize(type)
974 : 1;
975 return num_components;
976 }
977
978 static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
979 LLVMValueRef value,
980 int index)
981 {
982 int count = get_llvm_num_components(value);
983
984 assert(index < count);
985 if (count == 1)
986 return value;
987
988 return LLVMBuildExtractElement(ac->builder, value,
989 LLVMConstInt(ac->i32, index, false), "");
990 }
991
992 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
993 LLVMValueRef value, unsigned count)
994 {
995 unsigned num_components = get_llvm_num_components(value);
996 if (count == num_components)
997 return value;
998
999 LLVMValueRef masks[] = {
1000 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1001 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1002
1003 if (count == 1)
1004 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1005 "");
1006
1007 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1008 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1009 }
1010
1011 static void
1012 build_store_values_extended(struct ac_llvm_context *ac,
1013 LLVMValueRef *values,
1014 unsigned value_count,
1015 unsigned value_stride,
1016 LLVMValueRef vec)
1017 {
1018 LLVMBuilderRef builder = ac->builder;
1019 unsigned i;
1020
1021 if (value_count == 1) {
1022 LLVMBuildStore(builder, vec, values[0]);
1023 return;
1024 }
1025
1026 for (i = 0; i < value_count; i++) {
1027 LLVMValueRef ptr = values[i * value_stride];
1028 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1029 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1030 LLVMBuildStore(builder, value, ptr);
1031 }
1032 }
1033
1034 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1035 const nir_ssa_def *def)
1036 {
1037 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1038 if (def->num_components > 1) {
1039 type = LLVMVectorType(type, def->num_components);
1040 }
1041 return type;
1042 }
1043
1044 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1045 {
1046 assert(src.is_ssa);
1047 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1048 return (LLVMValueRef)entry->data;
1049 }
1050
1051
1052 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1053 const struct nir_block *b)
1054 {
1055 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1056 return (LLVMBasicBlockRef)entry->data;
1057 }
1058
1059 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1060 nir_alu_src src,
1061 unsigned num_components)
1062 {
1063 LLVMValueRef value = get_src(ctx, src.src);
1064 bool need_swizzle = false;
1065
1066 assert(value);
1067 LLVMTypeRef type = LLVMTypeOf(value);
1068 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1069 ? LLVMGetVectorSize(type)
1070 : 1;
1071
1072 for (unsigned i = 0; i < num_components; ++i) {
1073 assert(src.swizzle[i] < src_components);
1074 if (src.swizzle[i] != i)
1075 need_swizzle = true;
1076 }
1077
1078 if (need_swizzle || num_components != src_components) {
1079 LLVMValueRef masks[] = {
1080 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1081 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1082 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1083 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1084
1085 if (src_components > 1 && num_components == 1) {
1086 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1087 masks[0], "");
1088 } else if (src_components == 1 && num_components > 1) {
1089 LLVMValueRef values[] = {value, value, value, value};
1090 value = ac_build_gather_values(&ctx->ac, values, num_components);
1091 } else {
1092 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1093 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1094 swizzle, "");
1095 }
1096 }
1097 assert(!src.negate);
1098 assert(!src.abs);
1099 return value;
1100 }
1101
1102 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1103 LLVMIntPredicate pred, LLVMValueRef src0,
1104 LLVMValueRef src1)
1105 {
1106 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1107 return LLVMBuildSelect(ctx->builder, result,
1108 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1109 LLVMConstInt(ctx->i32, 0, false), "");
1110 }
1111
1112 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1113 LLVMRealPredicate pred, LLVMValueRef src0,
1114 LLVMValueRef src1)
1115 {
1116 LLVMValueRef result;
1117 src0 = to_float(ctx, src0);
1118 src1 = to_float(ctx, src1);
1119 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1120 return LLVMBuildSelect(ctx->builder, result,
1121 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1122 LLVMConstInt(ctx->i32, 0, false), "");
1123 }
1124
1125 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1126 const char *intrin,
1127 LLVMTypeRef result_type,
1128 LLVMValueRef src0)
1129 {
1130 char name[64];
1131 LLVMValueRef params[] = {
1132 to_float(ctx, src0),
1133 };
1134
1135 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1136 get_elem_bits(ctx, result_type));
1137 assert(length < sizeof(name));
1138 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1139 }
1140
1141 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1142 const char *intrin,
1143 LLVMTypeRef result_type,
1144 LLVMValueRef src0, LLVMValueRef src1)
1145 {
1146 char name[64];
1147 LLVMValueRef params[] = {
1148 to_float(ctx, src0),
1149 to_float(ctx, src1),
1150 };
1151
1152 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1153 get_elem_bits(ctx, result_type));
1154 assert(length < sizeof(name));
1155 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1156 }
1157
1158 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1159 const char *intrin,
1160 LLVMTypeRef result_type,
1161 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1162 {
1163 char name[64];
1164 LLVMValueRef params[] = {
1165 to_float(ctx, src0),
1166 to_float(ctx, src1),
1167 to_float(ctx, src2),
1168 };
1169
1170 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1171 get_elem_bits(ctx, result_type));
1172 assert(length < sizeof(name));
1173 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1174 }
1175
1176 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1177 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1178 {
1179 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1180 ctx->i32_0, "");
1181 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1182 }
1183
1184 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1185 LLVMValueRef src0)
1186 {
1187 LLVMValueRef params[2] = {
1188 src0,
1189
1190 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1191 * add special code to check for x=0. The reason is that
1192 * the LLVM behavior for x=0 is different from what we
1193 * need here.
1194 *
1195 * The hardware already implements the correct behavior.
1196 */
1197 LLVMConstInt(ctx->i1, 1, false),
1198 };
1199 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1200 }
1201
1202 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1203 LLVMValueRef src0)
1204 {
1205 return ac_build_imsb(ctx, src0, ctx->i32);
1206 }
1207
1208 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1209 LLVMValueRef src0)
1210 {
1211 return ac_build_umsb(ctx, src0, ctx->i32);
1212 }
1213
1214 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1215 LLVMIntPredicate pred,
1216 LLVMValueRef src0, LLVMValueRef src1)
1217 {
1218 return LLVMBuildSelect(ctx->builder,
1219 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1220 src0,
1221 src1, "");
1222
1223 }
1224 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1225 LLVMValueRef src0)
1226 {
1227 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1228 LLVMBuildNeg(ctx->builder, src0, ""));
1229 }
1230
1231 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1232 LLVMValueRef src0)
1233 {
1234 LLVMValueRef cmp, val;
1235
1236 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1237 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1238 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1239 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1240 return val;
1241 }
1242
1243 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1244 LLVMValueRef src0)
1245 {
1246 LLVMValueRef cmp, val;
1247
1248 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1249 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1250 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1251 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1252 return val;
1253 }
1254
1255 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1256 LLVMValueRef src0)
1257 {
1258 const char *intr = "llvm.floor.f32";
1259 LLVMValueRef fsrc0 = to_float(ctx, src0);
1260 LLVMValueRef params[] = {
1261 fsrc0,
1262 };
1263 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1264 ctx->f32, params, 1,
1265 AC_FUNC_ATTR_READNONE);
1266 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1267 }
1268
1269 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1270 const char *intrin,
1271 LLVMValueRef src0, LLVMValueRef src1)
1272 {
1273 LLVMTypeRef ret_type;
1274 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1275 LLVMValueRef res;
1276 LLVMValueRef params[] = { src0, src1 };
1277 ret_type = LLVMStructTypeInContext(ctx->context, types,
1278 2, true);
1279
1280 res = ac_build_intrinsic(ctx, intrin, ret_type,
1281 params, 2, AC_FUNC_ATTR_READNONE);
1282
1283 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1284 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1285 return res;
1286 }
1287
1288 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1289 LLVMValueRef src0)
1290 {
1291 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1292 }
1293
1294 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1295 LLVMValueRef src0)
1296 {
1297 src0 = to_float(ctx, src0);
1298 return LLVMBuildSExt(ctx->builder,
1299 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1300 ctx->i32, "");
1301 }
1302
1303 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1304 LLVMValueRef src0)
1305 {
1306 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1307 }
1308
1309 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1310 LLVMValueRef src0)
1311 {
1312 return LLVMBuildSExt(ctx->builder,
1313 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1314 ctx->i32, "");
1315 }
1316
1317 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1318 LLVMValueRef src0)
1319 {
1320 LLVMValueRef result;
1321 LLVMValueRef cond;
1322
1323 src0 = to_float(&ctx->ac, src0);
1324 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1325
1326 /* TODO SI/CIK options here */
1327 if (ctx->options->chip_class >= VI) {
1328 LLVMValueRef args[2];
1329 /* Check if the result is a denormal - and flush to 0 if so. */
1330 args[0] = result;
1331 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1332 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1333 }
1334
1335 /* need to convert back up to f32 */
1336 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1337
1338 if (ctx->options->chip_class >= VI)
1339 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1340
1341 return result;
1342 }
1343
1344 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1345 LLVMValueRef src0, LLVMValueRef src1)
1346 {
1347 LLVMValueRef dst64, result;
1348 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1349 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1350
1351 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1352 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1353 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1354 return result;
1355 }
1356
1357 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1358 LLVMValueRef src0, LLVMValueRef src1)
1359 {
1360 LLVMValueRef dst64, result;
1361 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1362 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1363
1364 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1365 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1366 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1367 return result;
1368 }
1369
1370 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1371 bool is_signed,
1372 const LLVMValueRef srcs[3])
1373 {
1374 LLVMValueRef result;
1375 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1376
1377 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1378 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1379 return result;
1380 }
1381
1382 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1383 LLVMValueRef src0, LLVMValueRef src1,
1384 LLVMValueRef src2, LLVMValueRef src3)
1385 {
1386 LLVMValueRef bfi_args[3], result;
1387
1388 bfi_args[0] = LLVMBuildShl(ctx->builder,
1389 LLVMBuildSub(ctx->builder,
1390 LLVMBuildShl(ctx->builder,
1391 ctx->i32_1,
1392 src3, ""),
1393 ctx->i32_1, ""),
1394 src2, "");
1395 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1396 bfi_args[2] = src0;
1397
1398 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1399
1400 /* Calculate:
1401 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1402 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1403 */
1404 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1405 LLVMBuildAnd(ctx->builder, bfi_args[0],
1406 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1407
1408 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1409 return result;
1410 }
1411
1412 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1413 LLVMValueRef src0)
1414 {
1415 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1416 int i;
1417 LLVMValueRef comp[2];
1418
1419 src0 = to_float(ctx, src0);
1420 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1421 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1422 for (i = 0; i < 2; i++) {
1423 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1424 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1425 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1426 }
1427
1428 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1429 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1430
1431 return comp[0];
1432 }
1433
1434 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1435 LLVMValueRef src0)
1436 {
1437 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1438 LLVMValueRef temps[2], result, val;
1439 int i;
1440
1441 for (i = 0; i < 2; i++) {
1442 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1443 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1444 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1445 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1446 }
1447
1448 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1449 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1450 ctx->i32_0, "");
1451 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1452 ctx->i32_1, "");
1453 return result;
1454 }
1455
1456 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1457 nir_op op,
1458 LLVMValueRef src0)
1459 {
1460 unsigned mask;
1461 int idx;
1462 LLVMValueRef result;
1463
1464 if (!ctx->lds && !ctx->has_ds_bpermute)
1465 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1466 LLVMArrayType(ctx->i32, 64),
1467 "ddxy_lds", LOCAL_ADDR_SPACE);
1468
1469 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1470 mask = AC_TID_MASK_LEFT;
1471 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1472 mask = AC_TID_MASK_TOP;
1473 else
1474 mask = AC_TID_MASK_TOP_LEFT;
1475
1476 /* for DDX we want to next X pixel, DDY next Y pixel. */
1477 if (op == nir_op_fddx_fine ||
1478 op == nir_op_fddx_coarse ||
1479 op == nir_op_fddx)
1480 idx = 1;
1481 else
1482 idx = 2;
1483
1484 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1485 mask, idx, ctx->lds,
1486 src0);
1487 return result;
1488 }
1489
1490 /*
1491 * this takes an I,J coordinate pair,
1492 * and works out the X and Y derivatives.
1493 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1494 */
1495 static LLVMValueRef emit_ddxy_interp(
1496 struct nir_to_llvm_context *ctx,
1497 LLVMValueRef interp_ij)
1498 {
1499 LLVMValueRef result[4], a;
1500 unsigned i;
1501
1502 for (i = 0; i < 2; i++) {
1503 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1504 LLVMConstInt(ctx->i32, i, false), "");
1505 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1506 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1507 }
1508 return ac_build_gather_values(&ctx->ac, result, 4);
1509 }
1510
1511 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1512 {
1513 LLVMValueRef src[4], result = NULL;
1514 unsigned num_components = instr->dest.dest.ssa.num_components;
1515 unsigned src_components;
1516 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1517
1518 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1519 switch (instr->op) {
1520 case nir_op_vec2:
1521 case nir_op_vec3:
1522 case nir_op_vec4:
1523 src_components = 1;
1524 break;
1525 case nir_op_pack_half_2x16:
1526 src_components = 2;
1527 break;
1528 case nir_op_unpack_half_2x16:
1529 src_components = 1;
1530 break;
1531 default:
1532 src_components = num_components;
1533 break;
1534 }
1535 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1536 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1537
1538 switch (instr->op) {
1539 case nir_op_fmov:
1540 case nir_op_imov:
1541 result = src[0];
1542 break;
1543 case nir_op_fneg:
1544 src[0] = to_float(&ctx->ac, src[0]);
1545 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1546 break;
1547 case nir_op_ineg:
1548 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1549 break;
1550 case nir_op_inot:
1551 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1552 break;
1553 case nir_op_iadd:
1554 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1555 break;
1556 case nir_op_fadd:
1557 src[0] = to_float(&ctx->ac, src[0]);
1558 src[1] = to_float(&ctx->ac, src[1]);
1559 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1560 break;
1561 case nir_op_fsub:
1562 src[0] = to_float(&ctx->ac, src[0]);
1563 src[1] = to_float(&ctx->ac, src[1]);
1564 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1565 break;
1566 case nir_op_isub:
1567 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1568 break;
1569 case nir_op_imul:
1570 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1571 break;
1572 case nir_op_imod:
1573 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1574 break;
1575 case nir_op_umod:
1576 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1577 break;
1578 case nir_op_fmod:
1579 src[0] = to_float(&ctx->ac, src[0]);
1580 src[1] = to_float(&ctx->ac, src[1]);
1581 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1582 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1583 to_float_type(&ctx->ac, def_type), result);
1584 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1585 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1586 break;
1587 case nir_op_frem:
1588 src[0] = to_float(&ctx->ac, src[0]);
1589 src[1] = to_float(&ctx->ac, src[1]);
1590 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1591 break;
1592 case nir_op_irem:
1593 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1594 break;
1595 case nir_op_idiv:
1596 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1597 break;
1598 case nir_op_udiv:
1599 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1600 break;
1601 case nir_op_fmul:
1602 src[0] = to_float(&ctx->ac, src[0]);
1603 src[1] = to_float(&ctx->ac, src[1]);
1604 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1605 break;
1606 case nir_op_fdiv:
1607 src[0] = to_float(&ctx->ac, src[0]);
1608 src[1] = to_float(&ctx->ac, src[1]);
1609 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1610 break;
1611 case nir_op_frcp:
1612 src[0] = to_float(&ctx->ac, src[0]);
1613 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, src[0]);
1614 break;
1615 case nir_op_iand:
1616 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1617 break;
1618 case nir_op_ior:
1619 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1620 break;
1621 case nir_op_ixor:
1622 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1623 break;
1624 case nir_op_ishl:
1625 result = LLVMBuildShl(ctx->ac.builder, src[0],
1626 LLVMBuildZExt(ctx->ac.builder, src[1],
1627 LLVMTypeOf(src[0]), ""),
1628 "");
1629 break;
1630 case nir_op_ishr:
1631 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1632 LLVMBuildZExt(ctx->ac.builder, src[1],
1633 LLVMTypeOf(src[0]), ""),
1634 "");
1635 break;
1636 case nir_op_ushr:
1637 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1638 LLVMBuildZExt(ctx->ac.builder, src[1],
1639 LLVMTypeOf(src[0]), ""),
1640 "");
1641 break;
1642 case nir_op_ilt:
1643 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1644 break;
1645 case nir_op_ine:
1646 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1647 break;
1648 case nir_op_ieq:
1649 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1650 break;
1651 case nir_op_ige:
1652 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1653 break;
1654 case nir_op_ult:
1655 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1656 break;
1657 case nir_op_uge:
1658 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1659 break;
1660 case nir_op_feq:
1661 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1662 break;
1663 case nir_op_fne:
1664 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1665 break;
1666 case nir_op_flt:
1667 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1668 break;
1669 case nir_op_fge:
1670 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1671 break;
1672 case nir_op_fabs:
1673 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1674 to_float_type(&ctx->ac, def_type), src[0]);
1675 break;
1676 case nir_op_iabs:
1677 result = emit_iabs(&ctx->ac, src[0]);
1678 break;
1679 case nir_op_imax:
1680 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1681 break;
1682 case nir_op_imin:
1683 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1684 break;
1685 case nir_op_umax:
1686 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1687 break;
1688 case nir_op_umin:
1689 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1690 break;
1691 case nir_op_isign:
1692 result = emit_isign(&ctx->ac, src[0]);
1693 break;
1694 case nir_op_fsign:
1695 src[0] = to_float(&ctx->ac, src[0]);
1696 result = emit_fsign(&ctx->ac, src[0]);
1697 break;
1698 case nir_op_ffloor:
1699 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1700 to_float_type(&ctx->ac, def_type), src[0]);
1701 break;
1702 case nir_op_ftrunc:
1703 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1704 to_float_type(&ctx->ac, def_type), src[0]);
1705 break;
1706 case nir_op_fceil:
1707 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1708 to_float_type(&ctx->ac, def_type), src[0]);
1709 break;
1710 case nir_op_fround_even:
1711 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1712 to_float_type(&ctx->ac, def_type),src[0]);
1713 break;
1714 case nir_op_ffract:
1715 result = emit_ffract(&ctx->ac, src[0]);
1716 break;
1717 case nir_op_fsin:
1718 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1719 to_float_type(&ctx->ac, def_type), src[0]);
1720 break;
1721 case nir_op_fcos:
1722 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1723 to_float_type(&ctx->ac, def_type), src[0]);
1724 break;
1725 case nir_op_fsqrt:
1726 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1727 to_float_type(&ctx->ac, def_type), src[0]);
1728 break;
1729 case nir_op_fexp2:
1730 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1731 to_float_type(&ctx->ac, def_type), src[0]);
1732 break;
1733 case nir_op_flog2:
1734 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1735 to_float_type(&ctx->ac, def_type), src[0]);
1736 break;
1737 case nir_op_frsq:
1738 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1739 to_float_type(&ctx->ac, def_type), src[0]);
1740 result = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, result);
1741 break;
1742 case nir_op_fpow:
1743 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1744 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1745 break;
1746 case nir_op_fmax:
1747 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1748 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1749 if (instr->dest.dest.ssa.bit_size == 32)
1750 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1751 to_float_type(&ctx->ac, def_type),
1752 result);
1753 break;
1754 case nir_op_fmin:
1755 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1756 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1757 if (instr->dest.dest.ssa.bit_size == 32)
1758 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1759 to_float_type(&ctx->ac, def_type),
1760 result);
1761 break;
1762 case nir_op_ffma:
1763 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1764 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1765 break;
1766 case nir_op_ibitfield_extract:
1767 result = emit_bitfield_extract(&ctx->ac, true, src);
1768 break;
1769 case nir_op_ubitfield_extract:
1770 result = emit_bitfield_extract(&ctx->ac, false, src);
1771 break;
1772 case nir_op_bitfield_insert:
1773 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1774 break;
1775 case nir_op_bitfield_reverse:
1776 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1777 break;
1778 case nir_op_bit_count:
1779 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1780 break;
1781 case nir_op_vec2:
1782 case nir_op_vec3:
1783 case nir_op_vec4:
1784 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1785 src[i] = to_integer(&ctx->ac, src[i]);
1786 result = ac_build_gather_values(&ctx->ac, src, num_components);
1787 break;
1788 case nir_op_f2i32:
1789 case nir_op_f2i64:
1790 src[0] = to_float(&ctx->ac, src[0]);
1791 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1792 break;
1793 case nir_op_f2u32:
1794 case nir_op_f2u64:
1795 src[0] = to_float(&ctx->ac, src[0]);
1796 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1797 break;
1798 case nir_op_i2f32:
1799 case nir_op_i2f64:
1800 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1801 break;
1802 case nir_op_u2f32:
1803 case nir_op_u2f64:
1804 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1805 break;
1806 case nir_op_f2f64:
1807 result = LLVMBuildFPExt(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1808 break;
1809 case nir_op_f2f32:
1810 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], to_float_type(&ctx->ac, def_type), "");
1811 break;
1812 case nir_op_u2u32:
1813 case nir_op_u2u64:
1814 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1815 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1816 else
1817 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1818 break;
1819 case nir_op_i2i32:
1820 case nir_op_i2i64:
1821 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1822 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1823 else
1824 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1825 break;
1826 case nir_op_bcsel:
1827 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1828 break;
1829 case nir_op_find_lsb:
1830 result = emit_find_lsb(&ctx->ac, src[0]);
1831 break;
1832 case nir_op_ufind_msb:
1833 result = emit_ufind_msb(&ctx->ac, src[0]);
1834 break;
1835 case nir_op_ifind_msb:
1836 result = emit_ifind_msb(&ctx->ac, src[0]);
1837 break;
1838 case nir_op_uadd_carry:
1839 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1840 break;
1841 case nir_op_usub_borrow:
1842 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1843 break;
1844 case nir_op_b2f:
1845 result = emit_b2f(&ctx->ac, src[0]);
1846 break;
1847 case nir_op_f2b:
1848 result = emit_f2b(&ctx->ac, src[0]);
1849 break;
1850 case nir_op_b2i:
1851 result = emit_b2i(&ctx->ac, src[0]);
1852 break;
1853 case nir_op_i2b:
1854 result = emit_i2b(&ctx->ac, src[0]);
1855 break;
1856 case nir_op_fquantize2f16:
1857 result = emit_f2f16(ctx->nctx, src[0]);
1858 break;
1859 case nir_op_umul_high:
1860 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1861 break;
1862 case nir_op_imul_high:
1863 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1864 break;
1865 case nir_op_pack_half_2x16:
1866 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1867 break;
1868 case nir_op_unpack_half_2x16:
1869 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1870 break;
1871 case nir_op_fddx:
1872 case nir_op_fddy:
1873 case nir_op_fddx_fine:
1874 case nir_op_fddy_fine:
1875 case nir_op_fddx_coarse:
1876 case nir_op_fddy_coarse:
1877 result = emit_ddxy(ctx->nctx, instr->op, src[0]);
1878 break;
1879
1880 case nir_op_unpack_64_2x32_split_x: {
1881 assert(instr->src[0].src.ssa->num_components == 1);
1882 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1883 LLVMVectorType(ctx->ac.i32, 2),
1884 "");
1885 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1886 ctx->ac.i32_0, "");
1887 break;
1888 }
1889
1890 case nir_op_unpack_64_2x32_split_y: {
1891 assert(instr->src[0].src.ssa->num_components == 1);
1892 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
1893 LLVMVectorType(ctx->ac.i32, 2),
1894 "");
1895 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
1896 ctx->ac.i32_0, "");
1897 break;
1898 }
1899
1900 case nir_op_pack_64_2x32_split: {
1901 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 2));
1902 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1903 src[0], ctx->ac.i32_0, "");
1904 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
1905 src[1], ctx->ac.i32_1, "");
1906 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
1907 break;
1908 }
1909
1910 default:
1911 fprintf(stderr, "Unknown NIR alu instr: ");
1912 nir_print_instr(&instr->instr, stderr);
1913 fprintf(stderr, "\n");
1914 abort();
1915 }
1916
1917 if (result) {
1918 assert(instr->dest.dest.is_ssa);
1919 result = to_integer(&ctx->ac, result);
1920 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1921 result);
1922 }
1923 }
1924
1925 static void visit_load_const(struct ac_nir_context *ctx,
1926 const nir_load_const_instr *instr)
1927 {
1928 LLVMValueRef values[4], value = NULL;
1929 LLVMTypeRef element_type =
1930 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
1931
1932 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1933 switch (instr->def.bit_size) {
1934 case 32:
1935 values[i] = LLVMConstInt(element_type,
1936 instr->value.u32[i], false);
1937 break;
1938 case 64:
1939 values[i] = LLVMConstInt(element_type,
1940 instr->value.u64[i], false);
1941 break;
1942 default:
1943 fprintf(stderr,
1944 "unsupported nir load_const bit_size: %d\n",
1945 instr->def.bit_size);
1946 abort();
1947 }
1948 }
1949 if (instr->def.num_components > 1) {
1950 value = LLVMConstVector(values, instr->def.num_components);
1951 } else
1952 value = values[0];
1953
1954 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1955 }
1956
1957 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1958 LLVMTypeRef type)
1959 {
1960 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1961 return LLVMBuildBitCast(ctx->builder, ptr,
1962 LLVMPointerType(type, addr_space), "");
1963 }
1964
1965 static LLVMValueRef
1966 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
1967 {
1968 LLVMValueRef size =
1969 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1970 LLVMConstInt(ctx->ac.i32, 2, false), "");
1971
1972 /* VI only */
1973 if (ctx->abi->chip_class >= VI && in_elements) {
1974 /* On VI, the descriptor contains the size in bytes,
1975 * but TXQ must return the size in elements.
1976 * The stride is always non-zero for resources using TXQ.
1977 */
1978 LLVMValueRef stride =
1979 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
1980 LLVMConstInt(ctx->ac.i32, 1, false), "");
1981 stride = LLVMBuildLShr(ctx->ac.builder, stride,
1982 LLVMConstInt(ctx->ac.i32, 16, false), "");
1983 stride = LLVMBuildAnd(ctx->ac.builder, stride,
1984 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
1985
1986 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
1987 }
1988 return size;
1989 }
1990
1991 /**
1992 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1993 * intrinsic names).
1994 */
1995 static void build_int_type_name(
1996 LLVMTypeRef type,
1997 char *buf, unsigned bufsize)
1998 {
1999 assert(bufsize >= 6);
2000
2001 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2002 snprintf(buf, bufsize, "v%ui32",
2003 LLVMGetVectorSize(type));
2004 else
2005 strcpy(buf, "i32");
2006 }
2007
2008 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2009 struct ac_image_args *args,
2010 const nir_tex_instr *instr)
2011 {
2012 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2013 LLVMValueRef coord = args->addr;
2014 LLVMValueRef half_texel[2];
2015 LLVMValueRef compare_cube_wa;
2016 LLVMValueRef result;
2017 int c;
2018 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2019
2020 //TODO Rect
2021 {
2022 struct ac_image_args txq_args = { 0 };
2023
2024 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2025 txq_args.opcode = ac_image_get_resinfo;
2026 txq_args.dmask = 0xf;
2027 txq_args.addr = ctx->i32_0;
2028 txq_args.resource = args->resource;
2029 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2030
2031 for (c = 0; c < 2; c++) {
2032 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2033 LLVMConstInt(ctx->i32, c, false), "");
2034 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2035 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2036 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2037 LLVMConstReal(ctx->f32, -0.5), "");
2038 }
2039 }
2040
2041 LLVMValueRef orig_coords = args->addr;
2042
2043 for (c = 0; c < 2; c++) {
2044 LLVMValueRef tmp;
2045 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2046 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2047 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2048 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2049 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2050 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2051 }
2052
2053
2054 /*
2055 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2056 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2057 * workaround by sampling using a scaled type and converting.
2058 * This is taken from amdgpu-pro shaders.
2059 */
2060 /* NOTE this produces some ugly code compared to amdgpu-pro,
2061 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2062 * and then reads them back. -pro generates two selects,
2063 * one s_cmp for the descriptor rewriting
2064 * one v_cmp for the coordinate and result changes.
2065 */
2066 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2067 LLVMValueRef tmp, tmp2;
2068
2069 /* workaround 8/8/8/8 uint/sint cube gather bug */
2070 /* first detect it then change to a scaled read and f2i */
2071 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2072 tmp2 = tmp;
2073
2074 /* extract the DATA_FORMAT */
2075 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2076 LLVMConstInt(ctx->i32, 6, false), false);
2077
2078 /* is the DATA_FORMAT == 8_8_8_8 */
2079 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2080
2081 if (stype == GLSL_TYPE_UINT)
2082 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2083 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2084 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2085 else
2086 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2087 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2088 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2089
2090 /* replace the NUM FORMAT in the descriptor */
2091 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2092 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2093
2094 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2095
2096 /* don't modify the coordinates for this case */
2097 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2098 }
2099 args->addr = coord;
2100 result = ac_build_image_opcode(ctx, args);
2101
2102 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2103 LLVMValueRef tmp, tmp2;
2104
2105 /* if the cube workaround is in place, f2i the result. */
2106 for (c = 0; c < 4; c++) {
2107 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2108 if (stype == GLSL_TYPE_UINT)
2109 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2110 else
2111 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2112 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2113 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2114 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2115 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2116 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2117 }
2118 }
2119 return result;
2120 }
2121
2122 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2123 const nir_tex_instr *instr,
2124 bool lod_is_zero,
2125 struct ac_image_args *args)
2126 {
2127 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2128 return ac_build_buffer_load_format(&ctx->ac,
2129 args->resource,
2130 args->addr,
2131 LLVMConstInt(ctx->ac.i32, 0, false),
2132 true);
2133 }
2134
2135 args->opcode = ac_image_sample;
2136 args->compare = instr->is_shadow;
2137
2138 switch (instr->op) {
2139 case nir_texop_txf:
2140 case nir_texop_txf_ms:
2141 case nir_texop_samples_identical:
2142 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2143 args->compare = false;
2144 args->offset = false;
2145 break;
2146 case nir_texop_txb:
2147 args->bias = true;
2148 break;
2149 case nir_texop_txl:
2150 if (lod_is_zero)
2151 args->level_zero = true;
2152 else
2153 args->lod = true;
2154 break;
2155 case nir_texop_txs:
2156 case nir_texop_query_levels:
2157 args->opcode = ac_image_get_resinfo;
2158 break;
2159 case nir_texop_tex:
2160 if (ctx->stage != MESA_SHADER_FRAGMENT)
2161 args->level_zero = true;
2162 break;
2163 case nir_texop_txd:
2164 args->deriv = true;
2165 break;
2166 case nir_texop_tg4:
2167 args->opcode = ac_image_gather4;
2168 args->level_zero = true;
2169 break;
2170 case nir_texop_lod:
2171 args->opcode = ac_image_get_lod;
2172 args->compare = false;
2173 args->offset = false;
2174 break;
2175 default:
2176 break;
2177 }
2178
2179 if (instr->op == nir_texop_tg4) {
2180 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2181 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2182 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2183 }
2184 }
2185 return ac_build_image_opcode(&ctx->ac, args);
2186 }
2187
2188 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2189 nir_intrinsic_instr *instr)
2190 {
2191 LLVMValueRef index = get_src(ctx->nir, instr->src[0]);
2192 unsigned desc_set = nir_intrinsic_desc_set(instr);
2193 unsigned binding = nir_intrinsic_binding(instr);
2194 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2195 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2196 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2197 unsigned base_offset = layout->binding[binding].offset;
2198 LLVMValueRef offset, stride;
2199
2200 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2201 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2202 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2203 layout->binding[binding].dynamic_offset_offset;
2204 desc_ptr = ctx->push_constants;
2205 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2206 stride = LLVMConstInt(ctx->i32, 16, false);
2207 } else
2208 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2209
2210 offset = LLVMConstInt(ctx->i32, base_offset, false);
2211 index = LLVMBuildMul(ctx->builder, index, stride, "");
2212 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2213
2214 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2215 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2216 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2217
2218 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2219 }
2220
2221 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2222 nir_intrinsic_instr *instr)
2223 {
2224 LLVMValueRef ptr, addr;
2225
2226 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2227 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx->nir, instr->src[0]), "");
2228
2229 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2230 ptr = cast_ptr(ctx, ptr, get_def_type(ctx->nir, &instr->dest.ssa));
2231
2232 return LLVMBuildLoad(ctx->builder, ptr, "");
2233 }
2234
2235 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2236 const nir_intrinsic_instr *instr)
2237 {
2238 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2239
2240 return get_buffer_size(ctx, desc, false);
2241 }
2242 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2243 nir_intrinsic_instr *instr)
2244 {
2245 const char *store_name;
2246 LLVMValueRef src_data = get_src(ctx->nir, instr->src[0]);
2247 LLVMTypeRef data_type = ctx->f32;
2248 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2249 int components_32bit = elem_size_mult * instr->num_components;
2250 unsigned writemask = nir_intrinsic_write_mask(instr);
2251 LLVMValueRef base_data, base_offset;
2252 LLVMValueRef params[6];
2253
2254 if (ctx->stage == MESA_SHADER_FRAGMENT)
2255 ctx->shader_info->fs.writes_memory = true;
2256
2257 params[1] = get_src(ctx->nir, instr->src[1]);
2258 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2259 params[4] = ctx->i1false; /* glc */
2260 params[5] = ctx->i1false; /* slc */
2261
2262 if (components_32bit > 1)
2263 data_type = LLVMVectorType(ctx->f32, components_32bit);
2264
2265 base_data = to_float(&ctx->ac, src_data);
2266 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2267 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2268 data_type, "");
2269 base_offset = get_src(ctx->nir, instr->src[2]); /* voffset */
2270 while (writemask) {
2271 int start, count;
2272 LLVMValueRef data;
2273 LLVMValueRef offset;
2274 LLVMValueRef tmp;
2275 u_bit_scan_consecutive_range(&writemask, &start, &count);
2276
2277 /* Due to an LLVM limitation, split 3-element writes
2278 * into a 2-element and a 1-element write. */
2279 if (count == 3) {
2280 writemask |= 1 << (start + 2);
2281 count = 2;
2282 }
2283
2284 start *= elem_size_mult;
2285 count *= elem_size_mult;
2286
2287 if (count > 4) {
2288 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2289 count = 4;
2290 }
2291
2292 if (count == 4) {
2293 store_name = "llvm.amdgcn.buffer.store.v4f32";
2294 data = base_data;
2295 } else if (count == 2) {
2296 tmp = LLVMBuildExtractElement(ctx->builder,
2297 base_data, LLVMConstInt(ctx->i32, start, false), "");
2298 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2299 ctx->i32zero, "");
2300
2301 tmp = LLVMBuildExtractElement(ctx->builder,
2302 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2303 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2304 ctx->i32one, "");
2305 store_name = "llvm.amdgcn.buffer.store.v2f32";
2306
2307 } else {
2308 assert(count == 1);
2309 if (get_llvm_num_components(base_data) > 1)
2310 data = LLVMBuildExtractElement(ctx->builder, base_data,
2311 LLVMConstInt(ctx->i32, start, false), "");
2312 else
2313 data = base_data;
2314 store_name = "llvm.amdgcn.buffer.store.f32";
2315 }
2316
2317 offset = base_offset;
2318 if (start != 0) {
2319 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2320 }
2321 params[0] = data;
2322 params[3] = offset;
2323 ac_build_intrinsic(&ctx->ac, store_name,
2324 ctx->voidt, params, 6, 0);
2325 }
2326 }
2327
2328 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2329 const nir_intrinsic_instr *instr)
2330 {
2331 const char *name;
2332 LLVMValueRef params[6];
2333 int arg_count = 0;
2334 if (ctx->stage == MESA_SHADER_FRAGMENT)
2335 ctx->shader_info->fs.writes_memory = true;
2336
2337 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2338 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx->nir, instr->src[3]), 0);
2339 }
2340 params[arg_count++] = llvm_extract_elem(&ctx->ac, get_src(ctx->nir, instr->src[2]), 0);
2341 params[arg_count++] = get_src(ctx->nir, instr->src[0]);
2342 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2343 params[arg_count++] = get_src(ctx->nir, instr->src[1]); /* voffset */
2344 params[arg_count++] = ctx->i1false; /* slc */
2345
2346 switch (instr->intrinsic) {
2347 case nir_intrinsic_ssbo_atomic_add:
2348 name = "llvm.amdgcn.buffer.atomic.add";
2349 break;
2350 case nir_intrinsic_ssbo_atomic_imin:
2351 name = "llvm.amdgcn.buffer.atomic.smin";
2352 break;
2353 case nir_intrinsic_ssbo_atomic_umin:
2354 name = "llvm.amdgcn.buffer.atomic.umin";
2355 break;
2356 case nir_intrinsic_ssbo_atomic_imax:
2357 name = "llvm.amdgcn.buffer.atomic.smax";
2358 break;
2359 case nir_intrinsic_ssbo_atomic_umax:
2360 name = "llvm.amdgcn.buffer.atomic.umax";
2361 break;
2362 case nir_intrinsic_ssbo_atomic_and:
2363 name = "llvm.amdgcn.buffer.atomic.and";
2364 break;
2365 case nir_intrinsic_ssbo_atomic_or:
2366 name = "llvm.amdgcn.buffer.atomic.or";
2367 break;
2368 case nir_intrinsic_ssbo_atomic_xor:
2369 name = "llvm.amdgcn.buffer.atomic.xor";
2370 break;
2371 case nir_intrinsic_ssbo_atomic_exchange:
2372 name = "llvm.amdgcn.buffer.atomic.swap";
2373 break;
2374 case nir_intrinsic_ssbo_atomic_comp_swap:
2375 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2376 break;
2377 default:
2378 abort();
2379 }
2380
2381 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2382 }
2383
2384 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2385 const nir_intrinsic_instr *instr)
2386 {
2387 LLVMValueRef results[2];
2388 int load_components;
2389 int num_components = instr->num_components;
2390 if (instr->dest.ssa.bit_size == 64)
2391 num_components *= 2;
2392
2393 for (int i = 0; i < num_components; i += load_components) {
2394 load_components = MIN2(num_components - i, 4);
2395 const char *load_name;
2396 LLVMTypeRef data_type = ctx->f32;
2397 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2398 offset = LLVMBuildAdd(ctx->builder, get_src(ctx->nir, instr->src[1]), offset, "");
2399
2400 if (load_components == 3)
2401 data_type = LLVMVectorType(ctx->f32, 4);
2402 else if (load_components > 1)
2403 data_type = LLVMVectorType(ctx->f32, load_components);
2404
2405 if (load_components >= 3)
2406 load_name = "llvm.amdgcn.buffer.load.v4f32";
2407 else if (load_components == 2)
2408 load_name = "llvm.amdgcn.buffer.load.v2f32";
2409 else if (load_components == 1)
2410 load_name = "llvm.amdgcn.buffer.load.f32";
2411 else
2412 unreachable("unhandled number of components");
2413
2414 LLVMValueRef params[] = {
2415 get_src(ctx->nir, instr->src[0]),
2416 LLVMConstInt(ctx->i32, 0, false),
2417 offset,
2418 ctx->i1false,
2419 ctx->i1false,
2420 };
2421
2422 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2423
2424 }
2425
2426 LLVMValueRef ret = results[0];
2427 if (num_components > 4 || num_components == 3) {
2428 LLVMValueRef masks[] = {
2429 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2430 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2431 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2432 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2433 };
2434
2435 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2436 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2437 results[num_components > 4 ? 1 : 0], swizzle, "");
2438 }
2439
2440 return LLVMBuildBitCast(ctx->builder, ret,
2441 get_def_type(ctx->nir, &instr->dest.ssa), "");
2442 }
2443
2444 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2445 const nir_intrinsic_instr *instr)
2446 {
2447 LLVMValueRef results[8], ret;
2448 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2449 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2450 int num_components = instr->num_components;
2451
2452 if (ctx->abi->load_ubo)
2453 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2454
2455 if (instr->dest.ssa.bit_size == 64)
2456 num_components *= 2;
2457
2458 for (unsigned i = 0; i < num_components; ++i) {
2459 LLVMValueRef params[] = {
2460 rsrc,
2461 LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, 4 * i, 0),
2462 offset, "")
2463 };
2464 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->ac.f32,
2465 params, 2,
2466 AC_FUNC_ATTR_READNONE |
2467 AC_FUNC_ATTR_LEGACY);
2468 }
2469
2470
2471 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2472 return LLVMBuildBitCast(ctx->ac.builder, ret,
2473 get_def_type(ctx, &instr->dest.ssa), "");
2474 }
2475
2476 static void
2477 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2478 bool vs_in, unsigned *vertex_index_out,
2479 LLVMValueRef *vertex_index_ref,
2480 unsigned *const_out, LLVMValueRef *indir_out)
2481 {
2482 unsigned const_offset = 0;
2483 nir_deref *tail = &deref->deref;
2484 LLVMValueRef offset = NULL;
2485
2486 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2487 tail = tail->child;
2488 nir_deref_array *deref_array = nir_deref_as_array(tail);
2489 if (vertex_index_out)
2490 *vertex_index_out = deref_array->base_offset;
2491
2492 if (vertex_index_ref) {
2493 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2494 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2495 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2496 }
2497 *vertex_index_ref = vtx;
2498 }
2499 }
2500
2501 if (deref->var->data.compact) {
2502 assert(tail->child->deref_type == nir_deref_type_array);
2503 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2504 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2505 /* We always lower indirect dereferences for "compact" array vars. */
2506 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2507
2508 const_offset = deref_array->base_offset;
2509 goto out;
2510 }
2511
2512 while (tail->child != NULL) {
2513 const struct glsl_type *parent_type = tail->type;
2514 tail = tail->child;
2515
2516 if (tail->deref_type == nir_deref_type_array) {
2517 nir_deref_array *deref_array = nir_deref_as_array(tail);
2518 LLVMValueRef index, stride, local_offset;
2519 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2520
2521 const_offset += size * deref_array->base_offset;
2522 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2523 continue;
2524
2525 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2526 index = get_src(ctx, deref_array->indirect);
2527 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2528 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2529
2530 if (offset)
2531 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2532 else
2533 offset = local_offset;
2534 } else if (tail->deref_type == nir_deref_type_struct) {
2535 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2536
2537 for (unsigned i = 0; i < deref_struct->index; i++) {
2538 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2539 const_offset += glsl_count_attribute_slots(ft, vs_in);
2540 }
2541 } else
2542 unreachable("unsupported deref type");
2543
2544 }
2545 out:
2546 if (const_offset && offset)
2547 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2548 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2549 "");
2550
2551 *const_out = const_offset;
2552 *indir_out = offset;
2553 }
2554
2555 static LLVMValueRef
2556 lds_load(struct nir_to_llvm_context *ctx,
2557 LLVMValueRef dw_addr)
2558 {
2559 LLVMValueRef value;
2560 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2561 return value;
2562 }
2563
2564 static void
2565 lds_store(struct nir_to_llvm_context *ctx,
2566 LLVMValueRef dw_addr, LLVMValueRef value)
2567 {
2568 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2569 ac_build_indexed_store(&ctx->ac, ctx->lds,
2570 dw_addr, value);
2571 }
2572
2573 /* The offchip buffer layout for TCS->TES is
2574 *
2575 * - attribute 0 of patch 0 vertex 0
2576 * - attribute 0 of patch 0 vertex 1
2577 * - attribute 0 of patch 0 vertex 2
2578 * ...
2579 * - attribute 0 of patch 1 vertex 0
2580 * - attribute 0 of patch 1 vertex 1
2581 * ...
2582 * - attribute 1 of patch 0 vertex 0
2583 * - attribute 1 of patch 0 vertex 1
2584 * ...
2585 * - per patch attribute 0 of patch 0
2586 * - per patch attribute 0 of patch 1
2587 * ...
2588 *
2589 * Note that every attribute has 4 components.
2590 */
2591 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2592 LLVMValueRef vertex_index,
2593 LLVMValueRef param_index)
2594 {
2595 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2596 LLVMValueRef param_stride, constant16;
2597 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2598
2599 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2600 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2601 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2602 num_patches, "");
2603
2604 constant16 = LLVMConstInt(ctx->i32, 16, false);
2605 if (vertex_index) {
2606 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2607 vertices_per_patch, "");
2608
2609 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2610 vertex_index, "");
2611
2612 param_stride = total_vertices;
2613 } else {
2614 base_addr = rel_patch_id;
2615 param_stride = num_patches;
2616 }
2617
2618 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2619 LLVMBuildMul(ctx->builder, param_index,
2620 param_stride, ""), "");
2621
2622 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2623
2624 if (!vertex_index) {
2625 LLVMValueRef patch_data_offset =
2626 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2627
2628 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2629 patch_data_offset, "");
2630 }
2631 return base_addr;
2632 }
2633
2634 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2635 unsigned param,
2636 unsigned const_index,
2637 bool is_compact,
2638 LLVMValueRef vertex_index,
2639 LLVMValueRef indir_index)
2640 {
2641 LLVMValueRef param_index;
2642
2643 if (indir_index)
2644 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2645 indir_index, "");
2646 else {
2647 if (const_index && !is_compact)
2648 param += const_index;
2649 param_index = LLVMConstInt(ctx->i32, param, false);
2650 }
2651 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2652 }
2653
2654 static void
2655 mark_tess_output(struct nir_to_llvm_context *ctx,
2656 bool is_patch, uint32_t param)
2657
2658 {
2659 if (is_patch) {
2660 ctx->tess_patch_outputs_written |= (1ull << param);
2661 } else
2662 ctx->tess_outputs_written |= (1ull << param);
2663 }
2664
2665 static LLVMValueRef
2666 get_dw_address(struct nir_to_llvm_context *ctx,
2667 LLVMValueRef dw_addr,
2668 unsigned param,
2669 unsigned const_index,
2670 bool compact_const_index,
2671 LLVMValueRef vertex_index,
2672 LLVMValueRef stride,
2673 LLVMValueRef indir_index)
2674
2675 {
2676
2677 if (vertex_index) {
2678 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2679 LLVMBuildMul(ctx->builder,
2680 vertex_index,
2681 stride, ""), "");
2682 }
2683
2684 if (indir_index)
2685 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2686 LLVMBuildMul(ctx->builder, indir_index,
2687 LLVMConstInt(ctx->i32, 4, false), ""), "");
2688 else if (const_index && !compact_const_index)
2689 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2690 LLVMConstInt(ctx->i32, const_index, false), "");
2691
2692 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2693 LLVMConstInt(ctx->i32, param * 4, false), "");
2694
2695 if (const_index && compact_const_index)
2696 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2697 LLVMConstInt(ctx->i32, const_index, false), "");
2698 return dw_addr;
2699 }
2700
2701 static LLVMValueRef
2702 load_tcs_input(struct nir_to_llvm_context *ctx,
2703 nir_intrinsic_instr *instr)
2704 {
2705 LLVMValueRef dw_addr, stride;
2706 unsigned const_index;
2707 LLVMValueRef vertex_index;
2708 LLVMValueRef indir_index;
2709 unsigned param;
2710 LLVMValueRef value[4], result;
2711 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2712 const bool is_compact = instr->variables[0]->var->data.compact;
2713 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2714 get_deref_offset(ctx->nir, instr->variables[0],
2715 false, NULL, per_vertex ? &vertex_index : NULL,
2716 &const_index, &indir_index);
2717
2718 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2719 dw_addr = get_tcs_in_current_patch_offset(ctx);
2720 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2721 indir_index);
2722
2723 for (unsigned i = 0; i < instr->num_components; i++) {
2724 value[i] = lds_load(ctx, dw_addr);
2725 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2726 ctx->i32one, "");
2727 }
2728 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2729 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2730 return result;
2731 }
2732
2733 static LLVMValueRef
2734 load_tcs_output(struct nir_to_llvm_context *ctx,
2735 nir_intrinsic_instr *instr)
2736 {
2737 LLVMValueRef dw_addr, stride;
2738 LLVMValueRef value[4], result;
2739 LLVMValueRef vertex_index = NULL;
2740 LLVMValueRef indir_index = NULL;
2741 unsigned const_index = 0;
2742 unsigned param;
2743 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2744 const bool is_compact = instr->variables[0]->var->data.compact;
2745 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2746 get_deref_offset(ctx->nir, instr->variables[0],
2747 false, NULL, per_vertex ? &vertex_index : NULL,
2748 &const_index, &indir_index);
2749
2750 if (!instr->variables[0]->var->data.patch) {
2751 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2752 dw_addr = get_tcs_out_current_patch_offset(ctx);
2753 } else {
2754 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2755 }
2756
2757 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2758 indir_index);
2759
2760 for (unsigned i = 0; i < instr->num_components; i++) {
2761 value[i] = lds_load(ctx, dw_addr);
2762 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2763 ctx->i32one, "");
2764 }
2765 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2766 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2767 return result;
2768 }
2769
2770 static void
2771 store_tcs_output(struct nir_to_llvm_context *ctx,
2772 nir_intrinsic_instr *instr,
2773 LLVMValueRef src,
2774 unsigned writemask)
2775 {
2776 LLVMValueRef stride, dw_addr;
2777 LLVMValueRef buf_addr = NULL;
2778 LLVMValueRef vertex_index = NULL;
2779 LLVMValueRef indir_index = NULL;
2780 unsigned const_index = 0;
2781 unsigned param;
2782 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2783 const bool is_compact = instr->variables[0]->var->data.compact;
2784
2785 get_deref_offset(ctx->nir, instr->variables[0],
2786 false, NULL, per_vertex ? &vertex_index : NULL,
2787 &const_index, &indir_index);
2788
2789 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2790 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2791 is_compact && const_index > 3) {
2792 const_index -= 3;
2793 param++;
2794 }
2795
2796 if (!instr->variables[0]->var->data.patch) {
2797 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2798 dw_addr = get_tcs_out_current_patch_offset(ctx);
2799 } else {
2800 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2801 }
2802
2803 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2804
2805 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2806 indir_index);
2807 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2808 vertex_index, indir_index);
2809
2810 unsigned base = is_compact ? const_index : 0;
2811 for (unsigned chan = 0; chan < 8; chan++) {
2812 bool is_tess_factor = false;
2813 if (!(writemask & (1 << chan)))
2814 continue;
2815 LLVMValueRef value = llvm_extract_elem(&ctx->ac, src, chan);
2816
2817 lds_store(ctx, dw_addr, value);
2818
2819 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2820 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2821 is_tess_factor = true;
2822
2823 if (!is_tess_factor && writemask != 0xF)
2824 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2825 buf_addr, ctx->oc_lds,
2826 4 * (base + chan), 1, 0, true, false);
2827
2828 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2829 ctx->i32one, "");
2830 }
2831
2832 if (writemask == 0xF) {
2833 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2834 buf_addr, ctx->oc_lds,
2835 (base * 4), 1, 0, true, false);
2836 }
2837 }
2838
2839 static LLVMValueRef
2840 load_tes_input(struct nir_to_llvm_context *ctx,
2841 const nir_intrinsic_instr *instr)
2842 {
2843 LLVMValueRef buf_addr;
2844 LLVMValueRef result;
2845 LLVMValueRef vertex_index = NULL;
2846 LLVMValueRef indir_index = NULL;
2847 unsigned const_index = 0;
2848 unsigned param;
2849 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2850 const bool is_compact = instr->variables[0]->var->data.compact;
2851
2852 get_deref_offset(ctx->nir, instr->variables[0],
2853 false, NULL, per_vertex ? &vertex_index : NULL,
2854 &const_index, &indir_index);
2855 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2856 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2857 is_compact && const_index > 3) {
2858 const_index -= 3;
2859 param++;
2860 }
2861 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2862 is_compact, vertex_index, indir_index);
2863
2864 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2865 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2866 result = trim_vector(&ctx->ac, result, instr->num_components);
2867 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, &instr->dest.ssa), "");
2868 return result;
2869 }
2870
2871 static LLVMValueRef
2872 load_gs_input(struct nir_to_llvm_context *ctx,
2873 nir_intrinsic_instr *instr)
2874 {
2875 LLVMValueRef indir_index, vtx_offset;
2876 unsigned const_index;
2877 LLVMValueRef args[9];
2878 unsigned param, vtx_offset_param;
2879 LLVMValueRef value[4], result;
2880 unsigned vertex_index;
2881 get_deref_offset(ctx->nir, instr->variables[0],
2882 false, &vertex_index, NULL,
2883 &const_index, &indir_index);
2884 vtx_offset_param = vertex_index;
2885 assert(vtx_offset_param < 6);
2886 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2887 LLVMConstInt(ctx->i32, 4, false), "");
2888
2889 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2890 for (unsigned i = 0; i < instr->num_components; i++) {
2891
2892 args[0] = ctx->esgs_ring;
2893 args[1] = vtx_offset;
2894 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2895 args[3] = ctx->i32zero;
2896 args[4] = ctx->i32one; /* OFFEN */
2897 args[5] = ctx->i32zero; /* IDXEN */
2898 args[6] = ctx->i32one; /* GLC */
2899 args[7] = ctx->i32zero; /* SLC */
2900 args[8] = ctx->i32zero; /* TFE */
2901
2902 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2903 ctx->i32, args, 9,
2904 AC_FUNC_ATTR_READONLY |
2905 AC_FUNC_ATTR_LEGACY);
2906 }
2907 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2908
2909 return result;
2910 }
2911
2912 static LLVMValueRef
2913 build_gep_for_deref(struct ac_nir_context *ctx,
2914 nir_deref_var *deref)
2915 {
2916 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2917 assert(entry->data);
2918 LLVMValueRef val = entry->data;
2919 nir_deref *tail = deref->deref.child;
2920 while (tail != NULL) {
2921 LLVMValueRef offset;
2922 switch (tail->deref_type) {
2923 case nir_deref_type_array: {
2924 nir_deref_array *array = nir_deref_as_array(tail);
2925 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
2926 if (array->deref_array_type ==
2927 nir_deref_array_type_indirect) {
2928 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2929 get_src(ctx,
2930 array->indirect),
2931 "");
2932 }
2933 break;
2934 }
2935 case nir_deref_type_struct: {
2936 nir_deref_struct *deref_struct =
2937 nir_deref_as_struct(tail);
2938 offset = LLVMConstInt(ctx->ac.i32,
2939 deref_struct->index, 0);
2940 break;
2941 }
2942 default:
2943 unreachable("bad deref type");
2944 }
2945 val = ac_build_gep0(&ctx->ac, val, offset);
2946 tail = tail->child;
2947 }
2948 return val;
2949 }
2950
2951 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
2952 nir_intrinsic_instr *instr)
2953 {
2954 LLVMValueRef values[8];
2955 int idx = instr->variables[0]->var->data.driver_location;
2956 int ve = instr->dest.ssa.num_components;
2957 LLVMValueRef indir_index;
2958 LLVMValueRef ret;
2959 unsigned const_index;
2960 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2961 instr->variables[0]->var->data.mode == nir_var_shader_in;
2962 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2963 &const_index, &indir_index);
2964
2965 if (instr->dest.ssa.bit_size == 64)
2966 ve *= 2;
2967
2968 switch (instr->variables[0]->var->data.mode) {
2969 case nir_var_shader_in:
2970 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2971 return load_tcs_input(ctx->nctx, instr);
2972 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2973 return load_tes_input(ctx->nctx, instr);
2974 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2975 return load_gs_input(ctx->nctx, instr);
2976 }
2977 for (unsigned chan = 0; chan < ve; chan++) {
2978 if (indir_index) {
2979 unsigned count = glsl_count_attribute_slots(
2980 instr->variables[0]->var->type,
2981 ctx->stage == MESA_SHADER_VERTEX);
2982 count -= chan / 4;
2983 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2984 &ctx->ac, ctx->abi->inputs + idx + chan, count,
2985 4, false);
2986
2987 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
2988 tmp_vec,
2989 indir_index, "");
2990 } else
2991 values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
2992 }
2993 break;
2994 case nir_var_local:
2995 for (unsigned chan = 0; chan < ve; chan++) {
2996 if (indir_index) {
2997 unsigned count = glsl_count_attribute_slots(
2998 instr->variables[0]->var->type, false);
2999 count -= chan / 4;
3000 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3001 &ctx->ac, ctx->locals + idx + chan, count,
3002 4, true);
3003
3004 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3005 tmp_vec,
3006 indir_index, "");
3007 } else {
3008 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
3009 }
3010 }
3011 break;
3012 case nir_var_shared: {
3013 LLVMValueRef address = build_gep_for_deref(ctx,
3014 instr->variables[0]);
3015 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3016 return LLVMBuildBitCast(ctx->ac.builder, val,
3017 get_def_type(ctx, &instr->dest.ssa),
3018 "");
3019 }
3020 case nir_var_shader_out:
3021 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3022 return load_tcs_output(ctx->nctx, instr);
3023 for (unsigned chan = 0; chan < ve; chan++) {
3024 if (indir_index) {
3025 unsigned count = glsl_count_attribute_slots(
3026 instr->variables[0]->var->type, false);
3027 count -= chan / 4;
3028 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3029 &ctx->ac, ctx->outputs + idx + chan, count,
3030 4, true);
3031
3032 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3033 tmp_vec,
3034 indir_index, "");
3035 } else {
3036 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3037 ctx->outputs[idx + chan + const_index * 4],
3038 "");
3039 }
3040 }
3041 break;
3042 default:
3043 unreachable("unhandle variable mode");
3044 }
3045 ret = ac_build_gather_values(&ctx->ac, values, ve);
3046 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3047 }
3048
3049 static void
3050 visit_store_var(struct ac_nir_context *ctx,
3051 nir_intrinsic_instr *instr)
3052 {
3053 LLVMValueRef temp_ptr, value;
3054 int idx = instr->variables[0]->var->data.driver_location;
3055 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3056 int writemask = instr->const_index[0];
3057 LLVMValueRef indir_index;
3058 unsigned const_index;
3059 get_deref_offset(ctx, instr->variables[0], false,
3060 NULL, NULL, &const_index, &indir_index);
3061
3062 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3063 int old_writemask = writemask;
3064
3065 src = LLVMBuildBitCast(ctx->ac.builder, src,
3066 LLVMVectorType(ctx->ac.f32, get_llvm_num_components(src) * 2),
3067 "");
3068
3069 writemask = 0;
3070 for (unsigned chan = 0; chan < 4; chan++) {
3071 if (old_writemask & (1 << chan))
3072 writemask |= 3u << (2 * chan);
3073 }
3074 }
3075
3076 switch (instr->variables[0]->var->data.mode) {
3077 case nir_var_shader_out:
3078
3079 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3080 store_tcs_output(ctx->nctx, instr, src, writemask);
3081 return;
3082 }
3083
3084 for (unsigned chan = 0; chan < 8; chan++) {
3085 int stride = 4;
3086 if (!(writemask & (1 << chan)))
3087 continue;
3088
3089 value = llvm_extract_elem(&ctx->ac, src, chan);
3090
3091 if (instr->variables[0]->var->data.compact)
3092 stride = 1;
3093 if (indir_index) {
3094 unsigned count = glsl_count_attribute_slots(
3095 instr->variables[0]->var->type, false);
3096 count -= chan / 4;
3097 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3098 &ctx->ac, ctx->outputs + idx + chan, count,
3099 stride, true);
3100
3101 if (get_llvm_num_components(tmp_vec) > 1) {
3102 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3103 value, indir_index, "");
3104 } else
3105 tmp_vec = value;
3106 build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
3107 count, stride, tmp_vec);
3108
3109 } else {
3110 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3111
3112 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3113 }
3114 }
3115 break;
3116 case nir_var_local:
3117 for (unsigned chan = 0; chan < 8; chan++) {
3118 if (!(writemask & (1 << chan)))
3119 continue;
3120
3121 value = llvm_extract_elem(&ctx->ac, src, chan);
3122 if (indir_index) {
3123 unsigned count = glsl_count_attribute_slots(
3124 instr->variables[0]->var->type, false);
3125 count -= chan / 4;
3126 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3127 &ctx->ac, ctx->locals + idx + chan, count,
3128 4, true);
3129
3130 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3131 value, indir_index, "");
3132 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3133 count, 4, tmp_vec);
3134 } else {
3135 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3136
3137 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3138 }
3139 }
3140 break;
3141 case nir_var_shared: {
3142 int writemask = instr->const_index[0];
3143 LLVMValueRef address = build_gep_for_deref(ctx,
3144 instr->variables[0]);
3145 LLVMValueRef val = get_src(ctx, instr->src[0]);
3146 unsigned components =
3147 glsl_get_vector_elements(
3148 nir_deref_tail(&instr->variables[0]->deref)->type);
3149 if (writemask == (1 << components) - 1) {
3150 val = LLVMBuildBitCast(
3151 ctx->ac.builder, val,
3152 LLVMGetElementType(LLVMTypeOf(address)), "");
3153 LLVMBuildStore(ctx->ac.builder, val, address);
3154 } else {
3155 for (unsigned chan = 0; chan < 4; chan++) {
3156 if (!(writemask & (1 << chan)))
3157 continue;
3158 LLVMValueRef ptr =
3159 LLVMBuildStructGEP(ctx->ac.builder,
3160 address, chan, "");
3161 LLVMValueRef src = llvm_extract_elem(&ctx->ac, val,
3162 chan);
3163 src = LLVMBuildBitCast(
3164 ctx->ac.builder, src,
3165 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3166 LLVMBuildStore(ctx->ac.builder, src, ptr);
3167 }
3168 }
3169 break;
3170 }
3171 default:
3172 break;
3173 }
3174 }
3175
3176 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3177 {
3178 switch (dim) {
3179 case GLSL_SAMPLER_DIM_BUF:
3180 return 1;
3181 case GLSL_SAMPLER_DIM_1D:
3182 return array ? 2 : 1;
3183 case GLSL_SAMPLER_DIM_2D:
3184 return array ? 3 : 2;
3185 case GLSL_SAMPLER_DIM_MS:
3186 return array ? 4 : 3;
3187 case GLSL_SAMPLER_DIM_3D:
3188 case GLSL_SAMPLER_DIM_CUBE:
3189 return 3;
3190 case GLSL_SAMPLER_DIM_RECT:
3191 case GLSL_SAMPLER_DIM_SUBPASS:
3192 return 2;
3193 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3194 return 3;
3195 default:
3196 break;
3197 }
3198 return 0;
3199 }
3200
3201
3202
3203 /* Adjust the sample index according to FMASK.
3204 *
3205 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3206 * which is the identity mapping. Each nibble says which physical sample
3207 * should be fetched to get that sample.
3208 *
3209 * For example, 0x11111100 means there are only 2 samples stored and
3210 * the second sample covers 3/4 of the pixel. When reading samples 0
3211 * and 1, return physical sample 0 (determined by the first two 0s
3212 * in FMASK), otherwise return physical sample 1.
3213 *
3214 * The sample index should be adjusted as follows:
3215 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3216 */
3217 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3218 LLVMValueRef coord_x, LLVMValueRef coord_y,
3219 LLVMValueRef coord_z,
3220 LLVMValueRef sample_index,
3221 LLVMValueRef fmask_desc_ptr)
3222 {
3223 LLVMValueRef fmask_load_address[4];
3224 LLVMValueRef res;
3225
3226 fmask_load_address[0] = coord_x;
3227 fmask_load_address[1] = coord_y;
3228 if (coord_z) {
3229 fmask_load_address[2] = coord_z;
3230 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3231 }
3232
3233 struct ac_image_args args = {0};
3234
3235 args.opcode = ac_image_load;
3236 args.da = coord_z ? true : false;
3237 args.resource = fmask_desc_ptr;
3238 args.dmask = 0xf;
3239 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3240
3241 res = ac_build_image_opcode(ctx, &args);
3242
3243 res = to_integer(ctx, res);
3244 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3245 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3246
3247 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3248 res,
3249 ctx->i32_0, "");
3250
3251 LLVMValueRef sample_index4 =
3252 LLVMBuildMul(ctx->builder, sample_index, four, "");
3253 LLVMValueRef shifted_fmask =
3254 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3255 LLVMValueRef final_sample =
3256 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3257
3258 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3259 * resource descriptor is 0 (invalid),
3260 */
3261 LLVMValueRef fmask_desc =
3262 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3263 ctx->v8i32, "");
3264
3265 LLVMValueRef fmask_word1 =
3266 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3267 ctx->i32_1, "");
3268
3269 LLVMValueRef word1_is_nonzero =
3270 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3271 fmask_word1, ctx->i32_0, "");
3272
3273 /* Replace the MSAA sample index. */
3274 sample_index =
3275 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3276 final_sample, sample_index, "");
3277 return sample_index;
3278 }
3279
3280 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3281 const nir_intrinsic_instr *instr)
3282 {
3283 const struct glsl_type *type = instr->variables[0]->var->type;
3284 if(instr->variables[0]->deref.child)
3285 type = instr->variables[0]->deref.child->type;
3286
3287 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3288 LLVMValueRef coords[4];
3289 LLVMValueRef masks[] = {
3290 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3291 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3292 };
3293 LLVMValueRef res;
3294 LLVMValueRef sample_index = llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3295
3296 int count;
3297 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3298 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3299 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3300 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3301 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3302
3303 count = image_type_to_components_count(dim,
3304 glsl_sampler_type_is_array(type));
3305
3306 if (is_ms) {
3307 LLVMValueRef fmask_load_address[3];
3308 int chan;
3309
3310 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3311 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3312 if (glsl_sampler_type_is_array(type))
3313 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3314 else
3315 fmask_load_address[2] = NULL;
3316 if (add_frag_pos) {
3317 for (chan = 0; chan < 2; ++chan)
3318 fmask_load_address[chan] = LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan], ctx->ac.i32, ""), "");
3319 }
3320 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3321 fmask_load_address[0],
3322 fmask_load_address[1],
3323 fmask_load_address[2],
3324 sample_index,
3325 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
3326 }
3327 if (count == 1) {
3328 if (instr->src[0].ssa->num_components)
3329 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3330 else
3331 res = src0;
3332 } else {
3333 int chan;
3334 if (is_ms)
3335 count--;
3336 for (chan = 0; chan < count; ++chan) {
3337 coords[chan] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[chan], "");
3338 }
3339
3340 if (add_frag_pos) {
3341 for (chan = 0; chan < count; ++chan)
3342 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan], ctx->ac.i32, ""), "");
3343 }
3344 if (is_ms) {
3345 coords[count] = sample_index;
3346 count++;
3347 }
3348
3349 if (count == 3) {
3350 coords[3] = LLVMGetUndef(ctx->ac.i32);
3351 count = 4;
3352 }
3353 res = ac_build_gather_values(&ctx->ac, coords, count);
3354 }
3355 return res;
3356 }
3357
3358 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3359 const nir_intrinsic_instr *instr)
3360 {
3361 LLVMValueRef params[7];
3362 LLVMValueRef res;
3363 char intrinsic_name[64];
3364 const nir_variable *var = instr->variables[0]->var;
3365 const struct glsl_type *type = var->type;
3366 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3367 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3368
3369 if(instr->variables[0]->deref.child)
3370 type = instr->variables[0]->deref.child->type;
3371
3372 type = glsl_without_array(type);
3373 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3374 params[0] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, false);
3375 params[1] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3376 ctx->ac.i32_0, ""); /* vindex */
3377 params[2] = ctx->ac.i32_0; /* voffset */
3378 params[3] = i1false; /* glc */
3379 params[4] = i1false; /* slc */
3380 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->ac.v4f32,
3381 params, 5, 0);
3382
3383 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3384 res = to_integer(&ctx->ac, res);
3385 } else {
3386 bool is_da = glsl_sampler_type_is_array(type) ||
3387 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3388 LLVMValueRef da = is_da ? i1true : i1false;
3389 LLVMValueRef glc = i1false;
3390 LLVMValueRef slc = i1false;
3391
3392 params[0] = get_image_coords(ctx, instr);
3393 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3394 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3395 if (HAVE_LLVM <= 0x0309) {
3396 params[3] = i1false; /* r128 */
3397 params[4] = da;
3398 params[5] = glc;
3399 params[6] = slc;
3400 } else {
3401 LLVMValueRef lwe = i1false;
3402 params[3] = glc;
3403 params[4] = slc;
3404 params[5] = lwe;
3405 params[6] = da;
3406 }
3407
3408 ac_get_image_intr_name("llvm.amdgcn.image.load",
3409 ctx->ac.v4f32, /* vdata */
3410 LLVMTypeOf(params[0]), /* coords */
3411 LLVMTypeOf(params[1]), /* rsrc */
3412 intrinsic_name, sizeof(intrinsic_name));
3413
3414 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3415 params, 7, AC_FUNC_ATTR_READONLY);
3416 }
3417 return to_integer(&ctx->ac, res);
3418 }
3419
3420 static void visit_image_store(struct ac_nir_context *ctx,
3421 nir_intrinsic_instr *instr)
3422 {
3423 LLVMValueRef params[8];
3424 char intrinsic_name[64];
3425 const nir_variable *var = instr->variables[0]->var;
3426 const struct glsl_type *type = glsl_without_array(var->type);
3427 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3428 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3429 LLVMValueRef glc = i1false;
3430 bool force_glc = ctx->abi->chip_class == SI;
3431 if (force_glc)
3432 glc = i1true;
3433
3434 if (ctx->stage == MESA_SHADER_FRAGMENT)
3435 ctx->nctx->shader_info->fs.writes_memory = true;
3436
3437 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3438 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3439 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
3440 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3441 ctx->ac.i32_0, ""); /* vindex */
3442 params[3] = ctx->ac.i32_0; /* voffset */
3443 params[4] = glc; /* glc */
3444 params[5] = i1false; /* slc */
3445 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3446 params, 6, 0);
3447 } else {
3448 bool is_da = glsl_sampler_type_is_array(type) ||
3449 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3450 LLVMValueRef da = is_da ? i1true : i1false;
3451 LLVMValueRef slc = i1false;
3452
3453 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3454 params[1] = get_image_coords(ctx, instr); /* coords */
3455 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, true);
3456 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3457 if (HAVE_LLVM <= 0x0309) {
3458 params[4] = i1false; /* r128 */
3459 params[5] = da;
3460 params[6] = glc;
3461 params[7] = slc;
3462 } else {
3463 LLVMValueRef lwe = i1false;
3464 params[4] = glc;
3465 params[5] = slc;
3466 params[6] = lwe;
3467 params[7] = da;
3468 }
3469
3470 ac_get_image_intr_name("llvm.amdgcn.image.store",
3471 LLVMTypeOf(params[0]), /* vdata */
3472 LLVMTypeOf(params[1]), /* coords */
3473 LLVMTypeOf(params[2]), /* rsrc */
3474 intrinsic_name, sizeof(intrinsic_name));
3475
3476 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3477 params, 8, 0);
3478 }
3479
3480 }
3481
3482 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3483 const nir_intrinsic_instr *instr)
3484 {
3485 LLVMValueRef params[6];
3486 int param_count = 0;
3487 const nir_variable *var = instr->variables[0]->var;
3488
3489 const char *atomic_name;
3490 char intrinsic_name[41];
3491 const struct glsl_type *type = glsl_without_array(var->type);
3492 LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
3493 LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
3494 MAYBE_UNUSED int length;
3495
3496 if (ctx->stage == MESA_SHADER_FRAGMENT)
3497 ctx->nctx->shader_info->fs.writes_memory = true;
3498
3499 switch (instr->intrinsic) {
3500 case nir_intrinsic_image_atomic_add:
3501 atomic_name = "add";
3502 break;
3503 case nir_intrinsic_image_atomic_min:
3504 atomic_name = "smin";
3505 break;
3506 case nir_intrinsic_image_atomic_max:
3507 atomic_name = "smax";
3508 break;
3509 case nir_intrinsic_image_atomic_and:
3510 atomic_name = "and";
3511 break;
3512 case nir_intrinsic_image_atomic_or:
3513 atomic_name = "or";
3514 break;
3515 case nir_intrinsic_image_atomic_xor:
3516 atomic_name = "xor";
3517 break;
3518 case nir_intrinsic_image_atomic_exchange:
3519 atomic_name = "swap";
3520 break;
3521 case nir_intrinsic_image_atomic_comp_swap:
3522 atomic_name = "cmpswap";
3523 break;
3524 default:
3525 abort();
3526 }
3527
3528 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3529 params[param_count++] = get_src(ctx, instr->src[3]);
3530 params[param_count++] = get_src(ctx, instr->src[2]);
3531
3532 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3533 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3534 true, true);
3535 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3536 ctx->ac.i32_0, ""); /* vindex */
3537 params[param_count++] = ctx->ac.i32_0; /* voffset */
3538 params[param_count++] = i1false; /* slc */
3539
3540 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3541 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3542 } else {
3543 char coords_type[8];
3544
3545 bool da = glsl_sampler_type_is_array(type) ||
3546 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3547
3548 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3549 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3550 true, true);
3551 params[param_count++] = i1false; /* r128 */
3552 params[param_count++] = da ? i1true : i1false; /* da */
3553 params[param_count++] = i1false; /* slc */
3554
3555 build_int_type_name(LLVMTypeOf(coords),
3556 coords_type, sizeof(coords_type));
3557
3558 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3559 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3560 }
3561
3562 assert(length < sizeof(intrinsic_name));
3563 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3564 }
3565
3566 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3567 const nir_intrinsic_instr *instr)
3568 {
3569 LLVMValueRef res;
3570 const nir_variable *var = instr->variables[0]->var;
3571 const struct glsl_type *type = instr->variables[0]->var->type;
3572 bool da = glsl_sampler_type_is_array(var->type) ||
3573 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3574 if(instr->variables[0]->deref.child)
3575 type = instr->variables[0]->deref.child->type;
3576
3577 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3578 return get_buffer_size(ctx,
3579 get_sampler_desc(ctx, instr->variables[0],
3580 AC_DESC_BUFFER, true, false), true);
3581
3582 struct ac_image_args args = { 0 };
3583
3584 args.da = da;
3585 args.dmask = 0xf;
3586 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, true, false);
3587 args.opcode = ac_image_get_resinfo;
3588 args.addr = ctx->ac.i32_0;
3589
3590 res = ac_build_image_opcode(&ctx->ac, &args);
3591
3592 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3593 glsl_sampler_type_is_array(type)) {
3594 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3595 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3596 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3597 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3598 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3599 }
3600 return res;
3601 }
3602
3603 #define NOOP_WAITCNT 0xf7f
3604 #define LGKM_CNT 0x07f
3605 #define VM_CNT 0xf70
3606
3607 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3608 unsigned simm16)
3609 {
3610 LLVMValueRef args[1] = {
3611 LLVMConstInt(ctx->i32, simm16, false),
3612 };
3613 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3614 ctx->voidt, args, 1, 0);
3615 }
3616
3617 static void emit_barrier(struct nir_to_llvm_context *ctx)
3618 {
3619 /* SI only (thanks to a hw bug workaround):
3620 * The real barrier instruction isn’t needed, because an entire patch
3621 * always fits into a single wave.
3622 */
3623 if (ctx->options->chip_class == SI &&
3624 ctx->stage == MESA_SHADER_TESS_CTRL) {
3625 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3626 return;
3627 }
3628 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3629 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3630 }
3631
3632 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3633 const nir_intrinsic_instr *instr)
3634 {
3635 LLVMValueRef cond;
3636 ctx->shader_info->fs.can_discard = true;
3637
3638 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3639 get_src(ctx->nir, instr->src[0]),
3640 ctx->i32zero, "");
3641
3642 cond = LLVMBuildSelect(ctx->builder, cond,
3643 LLVMConstReal(ctx->f32, -1.0f),
3644 ctx->f32zero, "");
3645 ac_build_kill(&ctx->ac, cond);
3646 }
3647
3648 static LLVMValueRef
3649 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3650 {
3651 LLVMValueRef result;
3652 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3653 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3654 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3655
3656 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3657 }
3658
3659 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3660 const nir_intrinsic_instr *instr)
3661 {
3662 LLVMValueRef ptr, result;
3663 LLVMValueRef src = get_src(ctx->nir, instr->src[0]);
3664 ptr = build_gep_for_deref(ctx->nir, instr->variables[0]);
3665
3666 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3667 LLVMValueRef src1 = get_src(ctx->nir, instr->src[1]);
3668 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3669 ptr, src, src1,
3670 LLVMAtomicOrderingSequentiallyConsistent,
3671 LLVMAtomicOrderingSequentiallyConsistent,
3672 false);
3673 } else {
3674 LLVMAtomicRMWBinOp op;
3675 switch (instr->intrinsic) {
3676 case nir_intrinsic_var_atomic_add:
3677 op = LLVMAtomicRMWBinOpAdd;
3678 break;
3679 case nir_intrinsic_var_atomic_umin:
3680 op = LLVMAtomicRMWBinOpUMin;
3681 break;
3682 case nir_intrinsic_var_atomic_umax:
3683 op = LLVMAtomicRMWBinOpUMax;
3684 break;
3685 case nir_intrinsic_var_atomic_imin:
3686 op = LLVMAtomicRMWBinOpMin;
3687 break;
3688 case nir_intrinsic_var_atomic_imax:
3689 op = LLVMAtomicRMWBinOpMax;
3690 break;
3691 case nir_intrinsic_var_atomic_and:
3692 op = LLVMAtomicRMWBinOpAnd;
3693 break;
3694 case nir_intrinsic_var_atomic_or:
3695 op = LLVMAtomicRMWBinOpOr;
3696 break;
3697 case nir_intrinsic_var_atomic_xor:
3698 op = LLVMAtomicRMWBinOpXor;
3699 break;
3700 case nir_intrinsic_var_atomic_exchange:
3701 op = LLVMAtomicRMWBinOpXchg;
3702 break;
3703 default:
3704 return NULL;
3705 }
3706
3707 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3708 LLVMAtomicOrderingSequentiallyConsistent,
3709 false);
3710 }
3711 return result;
3712 }
3713
3714 #define INTERP_CENTER 0
3715 #define INTERP_CENTROID 1
3716 #define INTERP_SAMPLE 2
3717
3718 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3719 enum glsl_interp_mode interp, unsigned location)
3720 {
3721 switch (interp) {
3722 case INTERP_MODE_FLAT:
3723 default:
3724 return NULL;
3725 case INTERP_MODE_SMOOTH:
3726 case INTERP_MODE_NONE:
3727 if (location == INTERP_CENTER)
3728 return ctx->persp_center;
3729 else if (location == INTERP_CENTROID)
3730 return ctx->persp_centroid;
3731 else if (location == INTERP_SAMPLE)
3732 return ctx->persp_sample;
3733 break;
3734 case INTERP_MODE_NOPERSPECTIVE:
3735 if (location == INTERP_CENTER)
3736 return ctx->linear_center;
3737 else if (location == INTERP_CENTROID)
3738 return ctx->linear_centroid;
3739 else if (location == INTERP_SAMPLE)
3740 return ctx->linear_sample;
3741 break;
3742 }
3743 return NULL;
3744 }
3745
3746 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3747 LLVMValueRef sample_id)
3748 {
3749 LLVMValueRef result;
3750 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3751
3752 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3753 const_array(ctx->v2f32, 64), "");
3754
3755 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3756 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3757
3758 return result;
3759 }
3760
3761 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3762 {
3763 LLVMValueRef values[2];
3764
3765 values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
3766 values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
3767 return ac_build_gather_values(&ctx->ac, values, 2);
3768 }
3769
3770 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3771 const nir_intrinsic_instr *instr)
3772 {
3773 LLVMValueRef result[2];
3774 LLVMValueRef interp_param, attr_number;
3775 unsigned location;
3776 unsigned chan;
3777 LLVMValueRef src_c0, src_c1;
3778 LLVMValueRef src0;
3779 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3780 switch (instr->intrinsic) {
3781 case nir_intrinsic_interp_var_at_centroid:
3782 location = INTERP_CENTROID;
3783 break;
3784 case nir_intrinsic_interp_var_at_sample:
3785 case nir_intrinsic_interp_var_at_offset:
3786 location = INTERP_CENTER;
3787 src0 = get_src(ctx->nir, instr->src[0]);
3788 break;
3789 default:
3790 break;
3791 }
3792
3793 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3794 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3795 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3796 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3797 LLVMValueRef sample_position;
3798 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3799
3800 /* fetch sample ID */
3801 sample_position = load_sample_position(ctx, src0);
3802
3803 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3804 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3805 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3806 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3807 }
3808 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3809 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3810
3811 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3812 LLVMValueRef ij_out[2];
3813 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3814
3815 /*
3816 * take the I then J parameters, and the DDX/Y for it, and
3817 * calculate the IJ inputs for the interpolator.
3818 * temp1 = ddx * offset/sample.x + I;
3819 * interp_param.I = ddy * offset/sample.y + temp1;
3820 * temp1 = ddx * offset/sample.x + J;
3821 * interp_param.J = ddy * offset/sample.y + temp1;
3822 */
3823 for (unsigned i = 0; i < 2; i++) {
3824 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3825 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3826 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3827 ddxy_out, ix_ll, "");
3828 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3829 ddxy_out, iy_ll, "");
3830 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3831 interp_param, ix_ll, "");
3832 LLVMValueRef temp1, temp2;
3833
3834 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3835 ctx->f32, "");
3836
3837 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3838 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3839
3840 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3841 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3842
3843 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3844 temp2, ctx->i32, "");
3845 }
3846 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3847
3848 }
3849
3850 for (chan = 0; chan < 2; chan++) {
3851 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3852
3853 if (interp_param) {
3854 interp_param = LLVMBuildBitCast(ctx->builder,
3855 interp_param, LLVMVectorType(ctx->f32, 2), "");
3856 LLVMValueRef i = LLVMBuildExtractElement(
3857 ctx->builder, interp_param, ctx->i32zero, "");
3858 LLVMValueRef j = LLVMBuildExtractElement(
3859 ctx->builder, interp_param, ctx->i32one, "");
3860
3861 result[chan] = ac_build_fs_interp(&ctx->ac,
3862 llvm_chan, attr_number,
3863 ctx->prim_mask, i, j);
3864 } else {
3865 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3866 LLVMConstInt(ctx->i32, 2, false),
3867 llvm_chan, attr_number,
3868 ctx->prim_mask);
3869 }
3870 }
3871 return ac_build_gather_values(&ctx->ac, result, 2);
3872 }
3873
3874 static void
3875 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3876 const nir_intrinsic_instr *instr)
3877 {
3878 LLVMValueRef gs_next_vertex;
3879 LLVMValueRef can_emit, kill;
3880 int idx;
3881
3882 assert(instr->const_index[0] == 0);
3883 /* Write vertex attribute values to GSVS ring */
3884 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3885 ctx->gs_next_vertex,
3886 "");
3887
3888 /* If this thread has already emitted the declared maximum number of
3889 * vertices, kill it: excessive vertex emissions are not supposed to
3890 * have any effect, and GS threads have no externally observable
3891 * effects other than emitting vertices.
3892 */
3893 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3894 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3895
3896 kill = LLVMBuildSelect(ctx->builder, can_emit,
3897 LLVMConstReal(ctx->f32, 1.0f),
3898 LLVMConstReal(ctx->f32, -1.0f), "");
3899 ac_build_kill(&ctx->ac, kill);
3900
3901 /* loop num outputs */
3902 idx = 0;
3903 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3904 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
3905 int length = 4;
3906 int slot = idx;
3907 int slot_inc = 1;
3908
3909 if (!(ctx->output_mask & (1ull << i)))
3910 continue;
3911
3912 if (i == VARYING_SLOT_CLIP_DIST0) {
3913 /* pack clip and cull into a single set of slots */
3914 length = ctx->num_output_clips + ctx->num_output_culls;
3915 if (length > 4)
3916 slot_inc = 2;
3917 }
3918 for (unsigned j = 0; j < length; j++) {
3919 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3920 out_ptr[j], "");
3921 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3922 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3923 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3924
3925 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3926
3927 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3928 out_val, 1,
3929 voffset, ctx->gs2vs_offset, 0,
3930 1, 1, true, true);
3931 }
3932 idx += slot_inc;
3933 }
3934
3935 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3936 ctx->i32one, "");
3937 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3938
3939 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3940 }
3941
3942 static void
3943 visit_end_primitive(struct nir_to_llvm_context *ctx,
3944 const nir_intrinsic_instr *instr)
3945 {
3946 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3947 }
3948
3949 static LLVMValueRef
3950 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3951 const nir_intrinsic_instr *instr)
3952 {
3953 LLVMValueRef coord[4] = {
3954 ctx->tes_u,
3955 ctx->tes_v,
3956 ctx->f32zero,
3957 ctx->f32zero,
3958 };
3959
3960 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3961 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3962 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3963
3964 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3965 return LLVMBuildBitCast(ctx->builder, result,
3966 get_def_type(ctx->nir, &instr->dest.ssa), "");
3967 }
3968
3969 static void visit_intrinsic(struct ac_nir_context *ctx,
3970 nir_intrinsic_instr *instr)
3971 {
3972 LLVMValueRef result = NULL;
3973
3974 switch (instr->intrinsic) {
3975 case nir_intrinsic_load_work_group_id: {
3976 result = ctx->nctx->workgroup_ids;
3977 break;
3978 }
3979 case nir_intrinsic_load_base_vertex: {
3980 result = ctx->abi->base_vertex;
3981 break;
3982 }
3983 case nir_intrinsic_load_vertex_id_zero_base: {
3984 result = ctx->abi->vertex_id;
3985 break;
3986 }
3987 case nir_intrinsic_load_local_invocation_id: {
3988 result = ctx->nctx->local_invocation_ids;
3989 break;
3990 }
3991 case nir_intrinsic_load_base_instance:
3992 result = ctx->abi->start_instance;
3993 break;
3994 case nir_intrinsic_load_draw_id:
3995 result = ctx->abi->draw_id;
3996 break;
3997 case nir_intrinsic_load_invocation_id:
3998 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3999 result = unpack_param(ctx->nctx, ctx->nctx->tcs_rel_ids, 8, 5);
4000 else
4001 result = ctx->nctx->gs_invocation_id;
4002 break;
4003 case nir_intrinsic_load_primitive_id:
4004 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4005 ctx->nctx->shader_info->gs.uses_prim_id = true;
4006 result = ctx->nctx->gs_prim_id;
4007 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4008 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4009 result = ctx->nctx->tcs_patch_id;
4010 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4011 ctx->nctx->shader_info->tcs.uses_prim_id = true;
4012 result = ctx->nctx->tes_patch_id;
4013 } else
4014 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4015 break;
4016 case nir_intrinsic_load_sample_id:
4017 ctx->nctx->shader_info->fs.force_persample = true;
4018 result = unpack_param(ctx->nctx, ctx->nctx->ancillary, 8, 4);
4019 break;
4020 case nir_intrinsic_load_sample_pos:
4021 ctx->nctx->shader_info->fs.force_persample = true;
4022 result = load_sample_pos(ctx->nctx);
4023 break;
4024 case nir_intrinsic_load_sample_mask_in:
4025 result = ctx->nctx->sample_coverage;
4026 break;
4027 case nir_intrinsic_load_front_face:
4028 result = ctx->nctx->front_face;
4029 break;
4030 case nir_intrinsic_load_instance_id:
4031 result = ctx->abi->instance_id;
4032 ctx->nctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4033 ctx->nctx->shader_info->vs.vgpr_comp_cnt);
4034 break;
4035 case nir_intrinsic_load_num_work_groups:
4036 result = ctx->nctx->num_work_groups;
4037 break;
4038 case nir_intrinsic_load_local_invocation_index:
4039 result = visit_load_local_invocation_index(ctx->nctx);
4040 break;
4041 case nir_intrinsic_load_push_constant:
4042 result = visit_load_push_constant(ctx->nctx, instr);
4043 break;
4044 case nir_intrinsic_vulkan_resource_index:
4045 result = visit_vulkan_resource_index(ctx->nctx, instr);
4046 break;
4047 case nir_intrinsic_store_ssbo:
4048 visit_store_ssbo(ctx->nctx, instr);
4049 break;
4050 case nir_intrinsic_load_ssbo:
4051 result = visit_load_buffer(ctx->nctx, instr);
4052 break;
4053 case nir_intrinsic_ssbo_atomic_add:
4054 case nir_intrinsic_ssbo_atomic_imin:
4055 case nir_intrinsic_ssbo_atomic_umin:
4056 case nir_intrinsic_ssbo_atomic_imax:
4057 case nir_intrinsic_ssbo_atomic_umax:
4058 case nir_intrinsic_ssbo_atomic_and:
4059 case nir_intrinsic_ssbo_atomic_or:
4060 case nir_intrinsic_ssbo_atomic_xor:
4061 case nir_intrinsic_ssbo_atomic_exchange:
4062 case nir_intrinsic_ssbo_atomic_comp_swap:
4063 result = visit_atomic_ssbo(ctx->nctx, instr);
4064 break;
4065 case nir_intrinsic_load_ubo:
4066 result = visit_load_ubo_buffer(ctx, instr);
4067 break;
4068 case nir_intrinsic_get_buffer_size:
4069 result = visit_get_buffer_size(ctx, instr);
4070 break;
4071 case nir_intrinsic_load_var:
4072 result = visit_load_var(ctx, instr);
4073 break;
4074 case nir_intrinsic_store_var:
4075 visit_store_var(ctx, instr);
4076 break;
4077 case nir_intrinsic_image_load:
4078 result = visit_image_load(ctx, instr);
4079 break;
4080 case nir_intrinsic_image_store:
4081 visit_image_store(ctx, instr);
4082 break;
4083 case nir_intrinsic_image_atomic_add:
4084 case nir_intrinsic_image_atomic_min:
4085 case nir_intrinsic_image_atomic_max:
4086 case nir_intrinsic_image_atomic_and:
4087 case nir_intrinsic_image_atomic_or:
4088 case nir_intrinsic_image_atomic_xor:
4089 case nir_intrinsic_image_atomic_exchange:
4090 case nir_intrinsic_image_atomic_comp_swap:
4091 result = visit_image_atomic(ctx, instr);
4092 break;
4093 case nir_intrinsic_image_size:
4094 result = visit_image_size(ctx, instr);
4095 break;
4096 case nir_intrinsic_discard:
4097 ctx->nctx->shader_info->fs.can_discard = true;
4098 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4099 LLVMVoidTypeInContext(ctx->ac.context),
4100 NULL, 0, AC_FUNC_ATTR_LEGACY);
4101 break;
4102 case nir_intrinsic_discard_if:
4103 emit_discard_if(ctx->nctx, instr);
4104 break;
4105 case nir_intrinsic_memory_barrier:
4106 emit_waitcnt(ctx->nctx, VM_CNT);
4107 break;
4108 case nir_intrinsic_barrier:
4109 emit_barrier(ctx->nctx);
4110 break;
4111 case nir_intrinsic_var_atomic_add:
4112 case nir_intrinsic_var_atomic_imin:
4113 case nir_intrinsic_var_atomic_umin:
4114 case nir_intrinsic_var_atomic_imax:
4115 case nir_intrinsic_var_atomic_umax:
4116 case nir_intrinsic_var_atomic_and:
4117 case nir_intrinsic_var_atomic_or:
4118 case nir_intrinsic_var_atomic_xor:
4119 case nir_intrinsic_var_atomic_exchange:
4120 case nir_intrinsic_var_atomic_comp_swap:
4121 result = visit_var_atomic(ctx->nctx, instr);
4122 break;
4123 case nir_intrinsic_interp_var_at_centroid:
4124 case nir_intrinsic_interp_var_at_sample:
4125 case nir_intrinsic_interp_var_at_offset:
4126 result = visit_interp(ctx->nctx, instr);
4127 break;
4128 case nir_intrinsic_emit_vertex:
4129 visit_emit_vertex(ctx->nctx, instr);
4130 break;
4131 case nir_intrinsic_end_primitive:
4132 visit_end_primitive(ctx->nctx, instr);
4133 break;
4134 case nir_intrinsic_load_tess_coord:
4135 result = visit_load_tess_coord(ctx->nctx, instr);
4136 break;
4137 case nir_intrinsic_load_patch_vertices_in:
4138 result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
4139 break;
4140 default:
4141 fprintf(stderr, "Unknown intrinsic: ");
4142 nir_print_instr(&instr->instr, stderr);
4143 fprintf(stderr, "\n");
4144 break;
4145 }
4146 if (result) {
4147 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4148 }
4149 }
4150
4151 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4152 unsigned descriptor_set,
4153 unsigned base_index,
4154 unsigned constant_index,
4155 LLVMValueRef index,
4156 enum ac_descriptor_type desc_type,
4157 bool image, bool write)
4158 {
4159 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4160 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4161 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4162 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4163 unsigned offset = binding->offset;
4164 unsigned stride = binding->size;
4165 unsigned type_size;
4166 LLVMBuilderRef builder = ctx->builder;
4167 LLVMTypeRef type;
4168
4169 assert(base_index < layout->binding_count);
4170
4171 switch (desc_type) {
4172 case AC_DESC_IMAGE:
4173 type = ctx->v8i32;
4174 type_size = 32;
4175 break;
4176 case AC_DESC_FMASK:
4177 type = ctx->v8i32;
4178 offset += 32;
4179 type_size = 32;
4180 break;
4181 case AC_DESC_SAMPLER:
4182 type = ctx->v4i32;
4183 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4184 offset += 64;
4185
4186 type_size = 16;
4187 break;
4188 case AC_DESC_BUFFER:
4189 type = ctx->v4i32;
4190 type_size = 16;
4191 break;
4192 default:
4193 unreachable("invalid desc_type\n");
4194 }
4195
4196 offset += constant_index * stride;
4197
4198 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4199 (!index || binding->immutable_samplers_equal)) {
4200 if (binding->immutable_samplers_equal)
4201 constant_index = 0;
4202
4203 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4204
4205 LLVMValueRef constants[] = {
4206 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4207 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4208 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4209 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4210 };
4211 return ac_build_gather_values(&ctx->ac, constants, 4);
4212 }
4213
4214 assert(stride % type_size == 0);
4215
4216 if (!index)
4217 index = ctx->i32zero;
4218
4219 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4220
4221 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4222 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4223
4224 return ac_build_indexed_load_const(&ctx->ac, list, index);
4225 }
4226
4227 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4228 const nir_deref_var *deref,
4229 enum ac_descriptor_type desc_type,
4230 bool image, bool write)
4231 {
4232 LLVMValueRef index = NULL;
4233 unsigned constant_index = 0;
4234 const nir_deref *tail = &deref->deref;
4235
4236 while (tail->child) {
4237 const nir_deref_array *child = nir_deref_as_array(tail->child);
4238 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4239
4240 if (!array_size)
4241 array_size = 1;
4242
4243 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4244
4245 if (child->deref_array_type == nir_deref_array_type_indirect) {
4246 LLVMValueRef indirect = get_src(ctx, child->indirect);
4247
4248 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4249 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4250
4251 if (!index)
4252 index = indirect;
4253 else
4254 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4255 }
4256
4257 constant_index += child->base_offset * array_size;
4258
4259 tail = &child->deref;
4260 }
4261
4262 return ctx->abi->load_sampler_desc(ctx->abi,
4263 deref->var->data.descriptor_set,
4264 deref->var->data.binding,
4265 constant_index, index,
4266 desc_type, image, write);
4267 }
4268
4269 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4270 struct ac_image_args *args,
4271 const nir_tex_instr *instr,
4272 nir_texop op,
4273 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4274 LLVMValueRef *param, unsigned count,
4275 unsigned dmask)
4276 {
4277 unsigned is_rect = 0;
4278 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4279
4280 if (op == nir_texop_lod)
4281 da = false;
4282 /* Pad to power of two vector */
4283 while (count < util_next_power_of_two(count))
4284 param[count++] = LLVMGetUndef(ctx->i32);
4285
4286 if (count > 1)
4287 args->addr = ac_build_gather_values(ctx, param, count);
4288 else
4289 args->addr = param[0];
4290
4291 args->resource = res_ptr;
4292 args->sampler = samp_ptr;
4293
4294 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4295 args->addr = param[0];
4296 return;
4297 }
4298
4299 args->dmask = dmask;
4300 args->unorm = is_rect;
4301 args->da = da;
4302 }
4303
4304 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4305 *
4306 * SI-CI:
4307 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4308 * filtering manually. The driver sets img7 to a mask clearing
4309 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4310 * s_and_b32 samp0, samp0, img7
4311 *
4312 * VI:
4313 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4314 */
4315 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4316 LLVMValueRef res, LLVMValueRef samp)
4317 {
4318 LLVMBuilderRef builder = ctx->ac.builder;
4319 LLVMValueRef img7, samp0;
4320
4321 if (ctx->abi->chip_class >= VI)
4322 return samp;
4323
4324 img7 = LLVMBuildExtractElement(builder, res,
4325 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4326 samp0 = LLVMBuildExtractElement(builder, samp,
4327 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4328 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4329 return LLVMBuildInsertElement(builder, samp, samp0,
4330 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4331 }
4332
4333 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4334 nir_tex_instr *instr,
4335 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4336 LLVMValueRef *fmask_ptr)
4337 {
4338 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4339 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, false, false);
4340 else
4341 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, false, false);
4342 if (samp_ptr) {
4343 if (instr->sampler)
4344 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, false, false);
4345 else
4346 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, false, false);
4347 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4348 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4349 }
4350 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4351 instr->op == nir_texop_samples_identical))
4352 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, false, false);
4353 }
4354
4355 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4356 LLVMValueRef coord)
4357 {
4358 coord = to_float(ctx, coord);
4359 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4360 coord = to_integer(ctx, coord);
4361 return coord;
4362 }
4363
4364 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4365 {
4366 LLVMValueRef result = NULL;
4367 struct ac_image_args args = { 0 };
4368 unsigned dmask = 0xf;
4369 LLVMValueRef address[16];
4370 LLVMValueRef coords[5];
4371 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4372 LLVMValueRef bias = NULL, offsets = NULL;
4373 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4374 LLVMValueRef ddx = NULL, ddy = NULL;
4375 LLVMValueRef derivs[6];
4376 unsigned chan, count = 0;
4377 unsigned const_src = 0, num_deriv_comp = 0;
4378 bool lod_is_zero = false;
4379
4380 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4381
4382 for (unsigned i = 0; i < instr->num_srcs; i++) {
4383 switch (instr->src[i].src_type) {
4384 case nir_tex_src_coord:
4385 coord = get_src(ctx, instr->src[i].src);
4386 break;
4387 case nir_tex_src_projector:
4388 break;
4389 case nir_tex_src_comparator:
4390 comparator = get_src(ctx, instr->src[i].src);
4391 break;
4392 case nir_tex_src_offset:
4393 offsets = get_src(ctx, instr->src[i].src);
4394 const_src = i;
4395 break;
4396 case nir_tex_src_bias:
4397 bias = get_src(ctx, instr->src[i].src);
4398 break;
4399 case nir_tex_src_lod: {
4400 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4401
4402 if (val && val->i32[0] == 0)
4403 lod_is_zero = true;
4404 lod = get_src(ctx, instr->src[i].src);
4405 break;
4406 }
4407 case nir_tex_src_ms_index:
4408 sample_index = get_src(ctx, instr->src[i].src);
4409 break;
4410 case nir_tex_src_ms_mcs:
4411 break;
4412 case nir_tex_src_ddx:
4413 ddx = get_src(ctx, instr->src[i].src);
4414 num_deriv_comp = instr->src[i].src.ssa->num_components;
4415 break;
4416 case nir_tex_src_ddy:
4417 ddy = get_src(ctx, instr->src[i].src);
4418 break;
4419 case nir_tex_src_texture_offset:
4420 case nir_tex_src_sampler_offset:
4421 case nir_tex_src_plane:
4422 default:
4423 break;
4424 }
4425 }
4426
4427 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4428 result = get_buffer_size(ctx, res_ptr, true);
4429 goto write_result;
4430 }
4431
4432 if (instr->op == nir_texop_texture_samples) {
4433 LLVMValueRef res, samples, is_msaa;
4434 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4435 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4436 LLVMConstInt(ctx->ac.i32, 3, false), "");
4437 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4438 LLVMConstInt(ctx->ac.i32, 28, false), "");
4439 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4440 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4441 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4442 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4443
4444 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4445 LLVMConstInt(ctx->ac.i32, 16, false), "");
4446 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4447 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4448 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4449 samples, "");
4450 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4451 ctx->ac.i32_1, "");
4452 result = samples;
4453 goto write_result;
4454 }
4455
4456 if (coord)
4457 for (chan = 0; chan < instr->coord_components; chan++)
4458 coords[chan] = llvm_extract_elem(&ctx->ac, coord, chan);
4459
4460 if (offsets && instr->op != nir_texop_txf) {
4461 LLVMValueRef offset[3], pack;
4462 for (chan = 0; chan < 3; ++chan)
4463 offset[chan] = ctx->ac.i32_0;
4464
4465 args.offset = true;
4466 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4467 offset[chan] = llvm_extract_elem(&ctx->ac, offsets, chan);
4468 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4469 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4470 if (chan)
4471 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4472 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4473 }
4474 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4475 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4476 address[count++] = pack;
4477
4478 }
4479 /* pack LOD bias value */
4480 if (instr->op == nir_texop_txb && bias) {
4481 address[count++] = bias;
4482 }
4483
4484 /* Pack depth comparison value */
4485 if (instr->is_shadow && comparator) {
4486 address[count++] = llvm_extract_elem(&ctx->ac, comparator, 0);
4487 }
4488
4489 /* pack derivatives */
4490 if (ddx || ddy) {
4491 switch (instr->sampler_dim) {
4492 case GLSL_SAMPLER_DIM_3D:
4493 case GLSL_SAMPLER_DIM_CUBE:
4494 num_deriv_comp = 3;
4495 break;
4496 case GLSL_SAMPLER_DIM_2D:
4497 default:
4498 num_deriv_comp = 2;
4499 break;
4500 case GLSL_SAMPLER_DIM_1D:
4501 num_deriv_comp = 1;
4502 break;
4503 }
4504
4505 for (unsigned i = 0; i < num_deriv_comp; i++) {
4506 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddx, i));
4507 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(&ctx->ac, ddy, i));
4508 }
4509 }
4510
4511 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4512 if (instr->is_array && instr->op != nir_texop_lod)
4513 coords[3] = apply_round_slice(&ctx->ac, coords[3]);
4514 for (chan = 0; chan < instr->coord_components; chan++)
4515 coords[chan] = to_float(&ctx->ac, coords[chan]);
4516 if (instr->coord_components == 3)
4517 coords[3] = LLVMGetUndef(ctx->ac.f32);
4518 ac_prepare_cube_coords(&ctx->ac,
4519 instr->op == nir_texop_txd, instr->is_array,
4520 coords, derivs);
4521 if (num_deriv_comp)
4522 num_deriv_comp--;
4523 }
4524
4525 if (ddx || ddy) {
4526 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4527 address[count++] = derivs[i];
4528 }
4529
4530 /* Pack texture coordinates */
4531 if (coord) {
4532 address[count++] = coords[0];
4533 if (instr->coord_components > 1) {
4534 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4535 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
4536 }
4537 address[count++] = coords[1];
4538 }
4539 if (instr->coord_components > 2) {
4540 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4541 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4542 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4543 instr->op != nir_texop_txf) {
4544 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
4545 }
4546 address[count++] = coords[2];
4547 }
4548 }
4549
4550 /* Pack LOD */
4551 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4552 instr->op == nir_texop_txf)) {
4553 address[count++] = lod;
4554 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4555 address[count++] = sample_index;
4556 } else if(instr->op == nir_texop_txs) {
4557 count = 0;
4558 if (lod)
4559 address[count++] = lod;
4560 else
4561 address[count++] = ctx->ac.i32_0;
4562 }
4563
4564 for (chan = 0; chan < count; chan++) {
4565 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
4566 address[chan], ctx->ac.i32, "");
4567 }
4568
4569 if (instr->op == nir_texop_samples_identical) {
4570 LLVMValueRef txf_address[4];
4571 struct ac_image_args txf_args = { 0 };
4572 unsigned txf_count = count;
4573 memcpy(txf_address, address, sizeof(txf_address));
4574
4575 if (!instr->is_array)
4576 txf_address[2] = ctx->ac.i32_0;
4577 txf_address[3] = ctx->ac.i32_0;
4578
4579 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
4580 fmask_ptr, NULL,
4581 txf_address, txf_count, 0xf);
4582
4583 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4584
4585 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4586 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
4587 goto write_result;
4588 }
4589
4590 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4591 instr->op != nir_texop_txs) {
4592 unsigned sample_chan = instr->is_array ? 3 : 2;
4593 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
4594 address[0],
4595 address[1],
4596 instr->is_array ? address[2] : NULL,
4597 address[sample_chan],
4598 fmask_ptr);
4599 }
4600
4601 if (offsets && instr->op == nir_texop_txf) {
4602 nir_const_value *const_offset =
4603 nir_src_as_const_value(instr->src[const_src].src);
4604 int num_offsets = instr->src[const_src].src.ssa->num_components;
4605 assert(const_offset);
4606 num_offsets = MIN2(num_offsets, instr->coord_components);
4607 if (num_offsets > 2)
4608 address[2] = LLVMBuildAdd(ctx->ac.builder,
4609 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
4610 if (num_offsets > 1)
4611 address[1] = LLVMBuildAdd(ctx->ac.builder,
4612 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
4613 address[0] = LLVMBuildAdd(ctx->ac.builder,
4614 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
4615
4616 }
4617
4618 /* TODO TG4 support */
4619 if (instr->op == nir_texop_tg4) {
4620 if (instr->is_shadow)
4621 dmask = 1;
4622 else
4623 dmask = 1 << instr->component;
4624 }
4625 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
4626 res_ptr, samp_ptr, address, count, dmask);
4627
4628 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4629
4630 if (instr->op == nir_texop_query_levels)
4631 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
4632 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4633 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
4634 else if (instr->op == nir_texop_txs &&
4635 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4636 instr->is_array) {
4637 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
4638 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
4639 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
4640 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
4641 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
4642 } else if (instr->dest.ssa.num_components != 4)
4643 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
4644
4645 write_result:
4646 if (result) {
4647 assert(instr->dest.is_ssa);
4648 result = to_integer(&ctx->ac, result);
4649 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4650 }
4651 }
4652
4653
4654 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
4655 {
4656 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4657 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
4658
4659 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4660 _mesa_hash_table_insert(ctx->phis, instr, result);
4661 }
4662
4663 static void visit_post_phi(struct ac_nir_context *ctx,
4664 nir_phi_instr *instr,
4665 LLVMValueRef llvm_phi)
4666 {
4667 nir_foreach_phi_src(src, instr) {
4668 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4669 LLVMValueRef llvm_src = get_src(ctx, src->src);
4670
4671 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4672 }
4673 }
4674
4675 static void phi_post_pass(struct ac_nir_context *ctx)
4676 {
4677 struct hash_entry *entry;
4678 hash_table_foreach(ctx->phis, entry) {
4679 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4680 (LLVMValueRef)entry->data);
4681 }
4682 }
4683
4684
4685 static void visit_ssa_undef(struct ac_nir_context *ctx,
4686 const nir_ssa_undef_instr *instr)
4687 {
4688 unsigned num_components = instr->def.num_components;
4689 LLVMValueRef undef;
4690
4691 if (num_components == 1)
4692 undef = LLVMGetUndef(ctx->ac.i32);
4693 else {
4694 undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, num_components));
4695 }
4696 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4697 }
4698
4699 static void visit_jump(struct ac_nir_context *ctx,
4700 const nir_jump_instr *instr)
4701 {
4702 switch (instr->type) {
4703 case nir_jump_break:
4704 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
4705 LLVMClearInsertionPosition(ctx->ac.builder);
4706 break;
4707 case nir_jump_continue:
4708 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4709 LLVMClearInsertionPosition(ctx->ac.builder);
4710 break;
4711 default:
4712 fprintf(stderr, "Unknown NIR jump instr: ");
4713 nir_print_instr(&instr->instr, stderr);
4714 fprintf(stderr, "\n");
4715 abort();
4716 }
4717 }
4718
4719 static void visit_cf_list(struct ac_nir_context *ctx,
4720 struct exec_list *list);
4721
4722 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
4723 {
4724 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
4725 nir_foreach_instr(instr, block)
4726 {
4727 switch (instr->type) {
4728 case nir_instr_type_alu:
4729 visit_alu(ctx, nir_instr_as_alu(instr));
4730 break;
4731 case nir_instr_type_load_const:
4732 visit_load_const(ctx, nir_instr_as_load_const(instr));
4733 break;
4734 case nir_instr_type_intrinsic:
4735 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4736 break;
4737 case nir_instr_type_tex:
4738 visit_tex(ctx, nir_instr_as_tex(instr));
4739 break;
4740 case nir_instr_type_phi:
4741 visit_phi(ctx, nir_instr_as_phi(instr));
4742 break;
4743 case nir_instr_type_ssa_undef:
4744 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4745 break;
4746 case nir_instr_type_jump:
4747 visit_jump(ctx, nir_instr_as_jump(instr));
4748 break;
4749 default:
4750 fprintf(stderr, "Unknown NIR instr type: ");
4751 nir_print_instr(instr, stderr);
4752 fprintf(stderr, "\n");
4753 abort();
4754 }
4755 }
4756
4757 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4758 }
4759
4760 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
4761 {
4762 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4763
4764 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4765 LLVMBasicBlockRef merge_block =
4766 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4767 LLVMBasicBlockRef if_block =
4768 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4769 LLVMBasicBlockRef else_block = merge_block;
4770 if (!exec_list_is_empty(&if_stmt->else_list))
4771 else_block = LLVMAppendBasicBlockInContext(
4772 ctx->ac.context, fn, "");
4773
4774 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
4775 LLVMConstInt(ctx->ac.i32, 0, false), "");
4776 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
4777
4778 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
4779 visit_cf_list(ctx, &if_stmt->then_list);
4780 if (LLVMGetInsertBlock(ctx->ac.builder))
4781 LLVMBuildBr(ctx->ac.builder, merge_block);
4782
4783 if (!exec_list_is_empty(&if_stmt->else_list)) {
4784 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
4785 visit_cf_list(ctx, &if_stmt->else_list);
4786 if (LLVMGetInsertBlock(ctx->ac.builder))
4787 LLVMBuildBr(ctx->ac.builder, merge_block);
4788 }
4789
4790 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
4791 }
4792
4793 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
4794 {
4795 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
4796 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4797 LLVMBasicBlockRef break_parent = ctx->break_block;
4798
4799 ctx->continue_block =
4800 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4801 ctx->break_block =
4802 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
4803
4804 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4805 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
4806 visit_cf_list(ctx, &loop->body);
4807
4808 if (LLVMGetInsertBlock(ctx->ac.builder))
4809 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
4810 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
4811
4812 ctx->continue_block = continue_parent;
4813 ctx->break_block = break_parent;
4814 }
4815
4816 static void visit_cf_list(struct ac_nir_context *ctx,
4817 struct exec_list *list)
4818 {
4819 foreach_list_typed(nir_cf_node, node, node, list)
4820 {
4821 switch (node->type) {
4822 case nir_cf_node_block:
4823 visit_block(ctx, nir_cf_node_as_block(node));
4824 break;
4825
4826 case nir_cf_node_if:
4827 visit_if(ctx, nir_cf_node_as_if(node));
4828 break;
4829
4830 case nir_cf_node_loop:
4831 visit_loop(ctx, nir_cf_node_as_loop(node));
4832 break;
4833
4834 default:
4835 assert(0);
4836 }
4837 }
4838 }
4839
4840 static void
4841 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4842 struct nir_variable *variable)
4843 {
4844 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4845 LLVMValueRef t_offset;
4846 LLVMValueRef t_list;
4847 LLVMValueRef input;
4848 LLVMValueRef buffer_index;
4849 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4850 int idx = variable->data.location;
4851 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4852
4853 variable->data.driver_location = idx * 4;
4854
4855 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4856 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4857 ctx->abi.start_instance, "");
4858 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4859 ctx->shader_info->vs.vgpr_comp_cnt);
4860 } else
4861 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4862 ctx->abi.base_vertex, "");
4863
4864 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4865 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4866
4867 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4868
4869 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4870 buffer_index,
4871 LLVMConstInt(ctx->i32, 0, false),
4872 true);
4873
4874 for (unsigned chan = 0; chan < 4; chan++) {
4875 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4876 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4877 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4878 input, llvm_chan, ""));
4879 }
4880 }
4881 }
4882
4883 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4884 unsigned attr,
4885 LLVMValueRef interp_param,
4886 LLVMValueRef prim_mask,
4887 LLVMValueRef result[4])
4888 {
4889 LLVMValueRef attr_number;
4890 unsigned chan;
4891 LLVMValueRef i, j;
4892 bool interp = interp_param != NULL;
4893
4894 attr_number = LLVMConstInt(ctx->i32, attr, false);
4895
4896 /* fs.constant returns the param from the middle vertex, so it's not
4897 * really useful for flat shading. It's meant to be used for custom
4898 * interpolation (but the intrinsic can't fetch from the other two
4899 * vertices).
4900 *
4901 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4902 * to do the right thing. The only reason we use fs.constant is that
4903 * fs.interp cannot be used on integers, because they can be equal
4904 * to NaN.
4905 */
4906 if (interp) {
4907 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4908 LLVMVectorType(ctx->f32, 2), "");
4909
4910 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4911 ctx->i32zero, "");
4912 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4913 ctx->i32one, "");
4914 }
4915
4916 for (chan = 0; chan < 4; chan++) {
4917 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4918
4919 if (interp) {
4920 result[chan] = ac_build_fs_interp(&ctx->ac,
4921 llvm_chan,
4922 attr_number,
4923 prim_mask, i, j);
4924 } else {
4925 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4926 LLVMConstInt(ctx->i32, 2, false),
4927 llvm_chan,
4928 attr_number,
4929 prim_mask);
4930 }
4931 }
4932 }
4933
4934 static void
4935 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4936 struct nir_variable *variable)
4937 {
4938 int idx = variable->data.location;
4939 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4940 LLVMValueRef interp;
4941
4942 variable->data.driver_location = idx * 4;
4943 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4944
4945 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4946 unsigned interp_type;
4947 if (variable->data.sample) {
4948 interp_type = INTERP_SAMPLE;
4949 ctx->shader_info->fs.force_persample = true;
4950 } else if (variable->data.centroid)
4951 interp_type = INTERP_CENTROID;
4952 else
4953 interp_type = INTERP_CENTER;
4954
4955 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4956 } else
4957 interp = NULL;
4958
4959 for (unsigned i = 0; i < attrib_count; ++i)
4960 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4961
4962 }
4963
4964 static void
4965 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4966 struct nir_variable *variable)
4967 {
4968 switch (ctx->stage) {
4969 case MESA_SHADER_VERTEX:
4970 handle_vs_input_decl(ctx, variable);
4971 break;
4972 case MESA_SHADER_FRAGMENT:
4973 handle_fs_input_decl(ctx, variable);
4974 break;
4975 default:
4976 break;
4977 }
4978
4979 }
4980
4981 static void
4982 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4983 struct nir_shader *nir)
4984 {
4985 unsigned index = 0;
4986 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4987 LLVMValueRef interp_param;
4988 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4989
4990 if (!(ctx->input_mask & (1ull << i)))
4991 continue;
4992
4993 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4994 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4995 interp_param = *inputs;
4996 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4997 inputs);
4998
4999 if (!interp_param)
5000 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5001 ++index;
5002 } else if (i == VARYING_SLOT_POS) {
5003 for(int i = 0; i < 3; ++i)
5004 inputs[i] = ctx->frag_pos[i];
5005
5006 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
5007 }
5008 }
5009 ctx->shader_info->fs.num_interp = index;
5010 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5011 ctx->shader_info->fs.has_pcoord = true;
5012 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5013 ctx->shader_info->fs.prim_id_input = true;
5014 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5015 ctx->shader_info->fs.layer_input = true;
5016 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5017 }
5018
5019 static LLVMValueRef
5020 ac_build_alloca(struct ac_llvm_context *ac,
5021 LLVMTypeRef type,
5022 const char *name)
5023 {
5024 LLVMBuilderRef builder = ac->builder;
5025 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5026 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5027 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5028 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5029 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5030 LLVMValueRef res;
5031
5032 if (first_instr) {
5033 LLVMPositionBuilderBefore(first_builder, first_instr);
5034 } else {
5035 LLVMPositionBuilderAtEnd(first_builder, first_block);
5036 }
5037
5038 res = LLVMBuildAlloca(first_builder, type, name);
5039 LLVMBuildStore(builder, LLVMConstNull(type), res);
5040
5041 LLVMDisposeBuilder(first_builder);
5042
5043 return res;
5044 }
5045
5046 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5047 LLVMTypeRef type,
5048 const char *name)
5049 {
5050 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5051 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5052 return ptr;
5053 }
5054
5055 static void
5056 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5057 struct nir_variable *variable)
5058 {
5059 int idx = variable->data.location + variable->data.index;
5060 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5061 uint64_t mask_attribs;
5062
5063 variable->data.driver_location = idx * 4;
5064
5065 /* tess ctrl has it's own load/store paths for outputs */
5066 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5067 return;
5068
5069 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5070 if (ctx->stage == MESA_SHADER_VERTEX ||
5071 ctx->stage == MESA_SHADER_TESS_EVAL ||
5072 ctx->stage == MESA_SHADER_GEOMETRY) {
5073 if (idx == VARYING_SLOT_CLIP_DIST0) {
5074 int length = ctx->num_output_clips + ctx->num_output_culls;
5075 if (ctx->stage == MESA_SHADER_VERTEX) {
5076 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5077 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5078 }
5079 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5080 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5081 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5082 }
5083
5084 if (length > 4)
5085 attrib_count = 2;
5086 else
5087 attrib_count = 1;
5088 mask_attribs = 1ull << idx;
5089 }
5090 }
5091
5092 ctx->output_mask |= mask_attribs;
5093 }
5094
5095 static void
5096 handle_shader_output_decl(struct ac_nir_context *ctx,
5097 struct nir_shader *nir,
5098 struct nir_variable *variable)
5099 {
5100 unsigned output_loc = variable->data.driver_location / 4;
5101 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5102
5103 /* tess ctrl has it's own load/store paths for outputs */
5104 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5105 return;
5106
5107 if (ctx->stage == MESA_SHADER_VERTEX ||
5108 ctx->stage == MESA_SHADER_TESS_EVAL ||
5109 ctx->stage == MESA_SHADER_GEOMETRY) {
5110 int idx = variable->data.location + variable->data.index;
5111 if (idx == VARYING_SLOT_CLIP_DIST0) {
5112 int length = nir->info.clip_distance_array_size +
5113 nir->info.cull_distance_array_size;
5114
5115 if (length > 4)
5116 attrib_count = 2;
5117 else
5118 attrib_count = 1;
5119 }
5120 }
5121
5122 for (unsigned i = 0; i < attrib_count; ++i) {
5123 for (unsigned chan = 0; chan < 4; chan++) {
5124 ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5125 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5126 }
5127 }
5128 }
5129
5130 static LLVMTypeRef
5131 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5132 enum glsl_base_type type)
5133 {
5134 switch (type) {
5135 case GLSL_TYPE_INT:
5136 case GLSL_TYPE_UINT:
5137 case GLSL_TYPE_BOOL:
5138 case GLSL_TYPE_SUBROUTINE:
5139 return ctx->i32;
5140 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5141 return ctx->f32;
5142 case GLSL_TYPE_INT64:
5143 case GLSL_TYPE_UINT64:
5144 return ctx->i64;
5145 case GLSL_TYPE_DOUBLE:
5146 return ctx->f64;
5147 default:
5148 unreachable("unknown GLSL type");
5149 }
5150 }
5151
5152 static LLVMTypeRef
5153 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5154 const struct glsl_type *type)
5155 {
5156 if (glsl_type_is_scalar(type)) {
5157 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5158 }
5159
5160 if (glsl_type_is_vector(type)) {
5161 return LLVMVectorType(
5162 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5163 glsl_get_vector_elements(type));
5164 }
5165
5166 if (glsl_type_is_matrix(type)) {
5167 return LLVMArrayType(
5168 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5169 glsl_get_matrix_columns(type));
5170 }
5171
5172 if (glsl_type_is_array(type)) {
5173 return LLVMArrayType(
5174 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5175 glsl_get_length(type));
5176 }
5177
5178 assert(glsl_type_is_struct(type));
5179
5180 LLVMTypeRef member_types[glsl_get_length(type)];
5181
5182 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5183 member_types[i] =
5184 glsl_to_llvm_type(ctx,
5185 glsl_get_struct_field(type, i));
5186 }
5187
5188 return LLVMStructTypeInContext(ctx->context, member_types,
5189 glsl_get_length(type), false);
5190 }
5191
5192 static void
5193 setup_locals(struct ac_nir_context *ctx,
5194 struct nir_function *func)
5195 {
5196 int i, j;
5197 ctx->num_locals = 0;
5198 nir_foreach_variable(variable, &func->impl->locals) {
5199 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5200 variable->data.driver_location = ctx->num_locals * 4;
5201 ctx->num_locals += attrib_count;
5202 }
5203 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5204 if (!ctx->locals)
5205 return;
5206
5207 for (i = 0; i < ctx->num_locals; i++) {
5208 for (j = 0; j < 4; j++) {
5209 ctx->locals[i * 4 + j] =
5210 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5211 }
5212 }
5213 }
5214
5215 static void
5216 setup_shared(struct ac_nir_context *ctx,
5217 struct nir_shader *nir)
5218 {
5219 nir_foreach_variable(variable, &nir->shared) {
5220 LLVMValueRef shared =
5221 LLVMAddGlobalInAddressSpace(
5222 ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
5223 variable->name ? variable->name : "",
5224 LOCAL_ADDR_SPACE);
5225 _mesa_hash_table_insert(ctx->vars, variable, shared);
5226 }
5227 }
5228
5229 static LLVMValueRef
5230 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5231 {
5232 v = to_float(ctx, v);
5233 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5234 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5235 }
5236
5237
5238 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5239 LLVMValueRef src0, LLVMValueRef src1)
5240 {
5241 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5242 LLVMValueRef comp[2];
5243
5244 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5245 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5246 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5247 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5248 }
5249
5250 /* Initialize arguments for the shader export intrinsic */
5251 static void
5252 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5253 LLVMValueRef *values,
5254 unsigned target,
5255 struct ac_export_args *args)
5256 {
5257 /* Default is 0xf. Adjusted below depending on the format. */
5258 args->enabled_channels = 0xf;
5259
5260 /* Specify whether the EXEC mask represents the valid mask */
5261 args->valid_mask = 0;
5262
5263 /* Specify whether this is the last export */
5264 args->done = 0;
5265
5266 /* Specify the target we are exporting */
5267 args->target = target;
5268
5269 args->compr = false;
5270 args->out[0] = LLVMGetUndef(ctx->f32);
5271 args->out[1] = LLVMGetUndef(ctx->f32);
5272 args->out[2] = LLVMGetUndef(ctx->f32);
5273 args->out[3] = LLVMGetUndef(ctx->f32);
5274
5275 if (!values)
5276 return;
5277
5278 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5279 LLVMValueRef val[4];
5280 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5281 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5282 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5283
5284 switch(col_format) {
5285 case V_028714_SPI_SHADER_ZERO:
5286 args->enabled_channels = 0; /* writemask */
5287 args->target = V_008DFC_SQ_EXP_NULL;
5288 break;
5289
5290 case V_028714_SPI_SHADER_32_R:
5291 args->enabled_channels = 1;
5292 args->out[0] = values[0];
5293 break;
5294
5295 case V_028714_SPI_SHADER_32_GR:
5296 args->enabled_channels = 0x3;
5297 args->out[0] = values[0];
5298 args->out[1] = values[1];
5299 break;
5300
5301 case V_028714_SPI_SHADER_32_AR:
5302 args->enabled_channels = 0x9;
5303 args->out[0] = values[0];
5304 args->out[3] = values[3];
5305 break;
5306
5307 case V_028714_SPI_SHADER_FP16_ABGR:
5308 args->compr = 1;
5309
5310 for (unsigned chan = 0; chan < 2; chan++) {
5311 LLVMValueRef pack_args[2] = {
5312 values[2 * chan],
5313 values[2 * chan + 1]
5314 };
5315 LLVMValueRef packed;
5316
5317 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5318 args->out[chan] = packed;
5319 }
5320 break;
5321
5322 case V_028714_SPI_SHADER_UNORM16_ABGR:
5323 for (unsigned chan = 0; chan < 4; chan++) {
5324 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5325 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5326 LLVMConstReal(ctx->f32, 65535), "");
5327 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5328 LLVMConstReal(ctx->f32, 0.5), "");
5329 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5330 ctx->i32, "");
5331 }
5332
5333 args->compr = 1;
5334 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5335 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5336 break;
5337
5338 case V_028714_SPI_SHADER_SNORM16_ABGR:
5339 for (unsigned chan = 0; chan < 4; chan++) {
5340 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5341 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5342 LLVMConstReal(ctx->f32, 32767), "");
5343
5344 /* If positive, add 0.5, else add -0.5. */
5345 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5346 LLVMBuildSelect(ctx->builder,
5347 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5348 val[chan], ctx->f32zero, ""),
5349 LLVMConstReal(ctx->f32, 0.5),
5350 LLVMConstReal(ctx->f32, -0.5), ""), "");
5351 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5352 }
5353
5354 args->compr = 1;
5355 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5356 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5357 break;
5358
5359 case V_028714_SPI_SHADER_UINT16_ABGR: {
5360 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5361
5362 for (unsigned chan = 0; chan < 4; chan++) {
5363 val[chan] = to_integer(&ctx->ac, values[chan]);
5364 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
5365 }
5366
5367 args->compr = 1;
5368 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5369 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5370 break;
5371 }
5372
5373 case V_028714_SPI_SHADER_SINT16_ABGR: {
5374 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5375 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5376
5377 /* Clamp. */
5378 for (unsigned chan = 0; chan < 4; chan++) {
5379 val[chan] = to_integer(&ctx->ac, values[chan]);
5380 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
5381 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
5382 }
5383
5384 args->compr = 1;
5385 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5386 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5387 break;
5388 }
5389
5390 default:
5391 case V_028714_SPI_SHADER_32_ABGR:
5392 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5393 break;
5394 }
5395 } else
5396 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5397
5398 for (unsigned i = 0; i < 4; ++i)
5399 args->out[i] = to_float(&ctx->ac, args->out[i]);
5400 }
5401
5402 static void
5403 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5404 bool export_prim_id,
5405 struct ac_vs_output_info *outinfo)
5406 {
5407 uint32_t param_count = 0;
5408 unsigned target;
5409 unsigned pos_idx, num_pos_exports = 0;
5410 struct ac_export_args args, pos_args[4] = {};
5411 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5412 int i;
5413
5414 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5415 sizeof(outinfo->vs_output_param_offset));
5416
5417 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5418 LLVMValueRef slots[8];
5419 unsigned j;
5420
5421 if (outinfo->cull_dist_mask)
5422 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5423
5424 i = VARYING_SLOT_CLIP_DIST0;
5425 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5426 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5427 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5428
5429 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5430 slots[i] = LLVMGetUndef(ctx->f32);
5431
5432 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5433 target = V_008DFC_SQ_EXP_POS + 3;
5434 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5435 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5436 &args, sizeof(args));
5437 }
5438
5439 target = V_008DFC_SQ_EXP_POS + 2;
5440 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5441 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5442 &args, sizeof(args));
5443
5444 }
5445
5446 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5447 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5448 for (unsigned j = 0; j < 4; j++)
5449 pos_values[j] = LLVMBuildLoad(ctx->builder,
5450 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5451 }
5452 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5453
5454 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5455 outinfo->writes_pointsize = true;
5456 psize_value = LLVMBuildLoad(ctx->builder,
5457 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5458 }
5459
5460 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5461 outinfo->writes_layer = true;
5462 layer_value = LLVMBuildLoad(ctx->builder,
5463 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5464 }
5465
5466 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5467 outinfo->writes_viewport_index = true;
5468 viewport_index_value = LLVMBuildLoad(ctx->builder,
5469 ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5470 }
5471
5472 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5473 (outinfo->writes_layer == true ? 4 : 0) |
5474 (outinfo->writes_viewport_index == true ? 8 : 0));
5475 if (mask) {
5476 pos_args[1].enabled_channels = mask;
5477 pos_args[1].valid_mask = 0;
5478 pos_args[1].done = 0;
5479 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5480 pos_args[1].compr = 0;
5481 pos_args[1].out[0] = ctx->f32zero; /* X */
5482 pos_args[1].out[1] = ctx->f32zero; /* Y */
5483 pos_args[1].out[2] = ctx->f32zero; /* Z */
5484 pos_args[1].out[3] = ctx->f32zero; /* W */
5485
5486 if (outinfo->writes_pointsize == true)
5487 pos_args[1].out[0] = psize_value;
5488 if (outinfo->writes_layer == true)
5489 pos_args[1].out[2] = layer_value;
5490 if (outinfo->writes_viewport_index == true)
5491 pos_args[1].out[3] = viewport_index_value;
5492 }
5493 for (i = 0; i < 4; i++) {
5494 if (pos_args[i].out[0])
5495 num_pos_exports++;
5496 }
5497
5498 pos_idx = 0;
5499 for (i = 0; i < 4; i++) {
5500 if (!pos_args[i].out[0])
5501 continue;
5502
5503 /* Specify the target we are exporting */
5504 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5505 if (pos_idx == num_pos_exports)
5506 pos_args[i].done = 1;
5507 ac_build_export(&ctx->ac, &pos_args[i]);
5508 }
5509
5510 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5511 LLVMValueRef values[4];
5512 if (!(ctx->output_mask & (1ull << i)))
5513 continue;
5514
5515 for (unsigned j = 0; j < 4; j++)
5516 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5517 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5518
5519 if (i == VARYING_SLOT_LAYER) {
5520 target = V_008DFC_SQ_EXP_PARAM + param_count;
5521 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5522 param_count++;
5523 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5524 target = V_008DFC_SQ_EXP_PARAM + param_count;
5525 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5526 param_count++;
5527 } else if (i >= VARYING_SLOT_VAR0) {
5528 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5529 target = V_008DFC_SQ_EXP_PARAM + param_count;
5530 outinfo->vs_output_param_offset[i] = param_count;
5531 param_count++;
5532 } else
5533 continue;
5534
5535 si_llvm_init_export_args(ctx, values, target, &args);
5536
5537 if (target >= V_008DFC_SQ_EXP_POS &&
5538 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5539 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5540 &args, sizeof(args));
5541 } else {
5542 ac_build_export(&ctx->ac, &args);
5543 }
5544 }
5545
5546 if (export_prim_id) {
5547 LLVMValueRef values[4];
5548 target = V_008DFC_SQ_EXP_PARAM + param_count;
5549 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5550 param_count++;
5551
5552 values[0] = ctx->vs_prim_id;
5553 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5554 ctx->shader_info->vs.vgpr_comp_cnt);
5555 for (unsigned j = 1; j < 4; j++)
5556 values[j] = ctx->f32zero;
5557 si_llvm_init_export_args(ctx, values, target, &args);
5558 ac_build_export(&ctx->ac, &args);
5559 outinfo->export_prim_id = true;
5560 }
5561
5562 outinfo->pos_exports = num_pos_exports;
5563 outinfo->param_exports = param_count;
5564 }
5565
5566 static void
5567 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5568 struct ac_es_output_info *outinfo)
5569 {
5570 int j;
5571 uint64_t max_output_written = 0;
5572 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5573 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5574 int param_index;
5575 int length = 4;
5576
5577 if (!(ctx->output_mask & (1ull << i)))
5578 continue;
5579
5580 if (i == VARYING_SLOT_CLIP_DIST0)
5581 length = ctx->num_output_clips + ctx->num_output_culls;
5582
5583 param_index = shader_io_get_unique_index(i);
5584
5585 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5586
5587 for (j = 0; j < length; j++) {
5588 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5589 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5590
5591 ac_build_buffer_store_dword(&ctx->ac,
5592 ctx->esgs_ring,
5593 out_val, 1,
5594 NULL, ctx->es2gs_offset,
5595 (4 * param_index + j) * 4,
5596 1, 1, true, true);
5597 }
5598 }
5599 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5600 }
5601
5602 static void
5603 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5604 {
5605 LLVMValueRef vertex_id = ctx->rel_auto_id;
5606 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5607 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5608 vertex_dw_stride, "");
5609
5610 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5611 LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
5612 int length = 4;
5613
5614 if (!(ctx->output_mask & (1ull << i)))
5615 continue;
5616
5617 if (i == VARYING_SLOT_CLIP_DIST0)
5618 length = ctx->num_output_clips + ctx->num_output_culls;
5619 int param = shader_io_get_unique_index(i);
5620 mark_tess_output(ctx, false, param);
5621 if (length > 4)
5622 mark_tess_output(ctx, false, param + 1);
5623 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5624 LLVMConstInt(ctx->i32, param * 4, false),
5625 "");
5626 for (unsigned j = 0; j < length; j++) {
5627 lds_store(ctx, dw_addr,
5628 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5629 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5630 }
5631 }
5632 }
5633
5634 struct ac_build_if_state
5635 {
5636 struct nir_to_llvm_context *ctx;
5637 LLVMValueRef condition;
5638 LLVMBasicBlockRef entry_block;
5639 LLVMBasicBlockRef true_block;
5640 LLVMBasicBlockRef false_block;
5641 LLVMBasicBlockRef merge_block;
5642 };
5643
5644 static LLVMBasicBlockRef
5645 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5646 {
5647 LLVMBasicBlockRef current_block;
5648 LLVMBasicBlockRef next_block;
5649 LLVMBasicBlockRef new_block;
5650
5651 /* get current basic block */
5652 current_block = LLVMGetInsertBlock(ctx->builder);
5653
5654 /* chqeck if there's another block after this one */
5655 next_block = LLVMGetNextBasicBlock(current_block);
5656 if (next_block) {
5657 /* insert the new block before the next block */
5658 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5659 }
5660 else {
5661 /* append new block after current block */
5662 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5663 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5664 }
5665 return new_block;
5666 }
5667
5668 static void
5669 ac_nir_build_if(struct ac_build_if_state *ifthen,
5670 struct nir_to_llvm_context *ctx,
5671 LLVMValueRef condition)
5672 {
5673 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5674
5675 memset(ifthen, 0, sizeof *ifthen);
5676 ifthen->ctx = ctx;
5677 ifthen->condition = condition;
5678 ifthen->entry_block = block;
5679
5680 /* create endif/merge basic block for the phi functions */
5681 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5682
5683 /* create/insert true_block before merge_block */
5684 ifthen->true_block =
5685 LLVMInsertBasicBlockInContext(ctx->context,
5686 ifthen->merge_block,
5687 "if-true-block");
5688
5689 /* successive code goes into the true block */
5690 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5691 }
5692
5693 /**
5694 * End a conditional.
5695 */
5696 static void
5697 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5698 {
5699 LLVMBuilderRef builder = ifthen->ctx->builder;
5700
5701 /* Insert branch to the merge block from current block */
5702 LLVMBuildBr(builder, ifthen->merge_block);
5703
5704 /*
5705 * Now patch in the various branch instructions.
5706 */
5707
5708 /* Insert the conditional branch instruction at the end of entry_block */
5709 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5710 if (ifthen->false_block) {
5711 /* we have an else clause */
5712 LLVMBuildCondBr(builder, ifthen->condition,
5713 ifthen->true_block, ifthen->false_block);
5714 }
5715 else {
5716 /* no else clause */
5717 LLVMBuildCondBr(builder, ifthen->condition,
5718 ifthen->true_block, ifthen->merge_block);
5719 }
5720
5721 /* Resume building code at end of the ifthen->merge_block */
5722 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5723 }
5724
5725 static void
5726 write_tess_factors(struct nir_to_llvm_context *ctx)
5727 {
5728 unsigned stride, outer_comps, inner_comps;
5729 struct ac_build_if_state if_ctx, inner_if_ctx;
5730 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5731 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5732 unsigned tess_inner_index, tess_outer_index;
5733 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5734 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5735 int i;
5736 emit_barrier(ctx);
5737
5738 switch (ctx->options->key.tcs.primitive_mode) {
5739 case GL_ISOLINES:
5740 stride = 2;
5741 outer_comps = 2;
5742 inner_comps = 0;
5743 break;
5744 case GL_TRIANGLES:
5745 stride = 4;
5746 outer_comps = 3;
5747 inner_comps = 1;
5748 break;
5749 case GL_QUADS:
5750 stride = 6;
5751 outer_comps = 4;
5752 inner_comps = 2;
5753 break;
5754 default:
5755 return;
5756 }
5757
5758 ac_nir_build_if(&if_ctx, ctx,
5759 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5760 invocation_id, ctx->i32zero, ""));
5761
5762 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5763 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5764
5765 mark_tess_output(ctx, true, tess_inner_index);
5766 mark_tess_output(ctx, true, tess_outer_index);
5767 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5768 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5769 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5770 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5771 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5772
5773 for (i = 0; i < 4; i++) {
5774 inner[i] = LLVMGetUndef(ctx->i32);
5775 outer[i] = LLVMGetUndef(ctx->i32);
5776 }
5777
5778 // LINES reverseal
5779 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5780 outer[0] = out[1] = lds_load(ctx, lds_outer);
5781 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5782 LLVMConstInt(ctx->i32, 1, false), "");
5783 outer[1] = out[0] = lds_load(ctx, lds_outer);
5784 } else {
5785 for (i = 0; i < outer_comps; i++) {
5786 outer[i] = out[i] =
5787 lds_load(ctx, lds_outer);
5788 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5789 LLVMConstInt(ctx->i32, 1, false), "");
5790 }
5791 for (i = 0; i < inner_comps; i++) {
5792 inner[i] = out[outer_comps+i] =
5793 lds_load(ctx, lds_inner);
5794 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5795 LLVMConstInt(ctx->i32, 1, false), "");
5796 }
5797 }
5798
5799 /* Convert the outputs to vectors for stores. */
5800 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5801 vec1 = NULL;
5802
5803 if (stride > 4)
5804 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5805
5806
5807 buffer = ctx->hs_ring_tess_factor;
5808 tf_base = ctx->tess_factor_offset;
5809 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5810 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5811
5812 ac_nir_build_if(&inner_if_ctx, ctx,
5813 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5814 rel_patch_id, ctx->i32zero, ""));
5815
5816 /* Store the dynamic HS control word. */
5817 ac_build_buffer_store_dword(&ctx->ac, buffer,
5818 LLVMConstInt(ctx->i32, 0x80000000, false),
5819 1, ctx->i32zero, tf_base,
5820 0, 1, 0, true, false);
5821 ac_nir_build_endif(&inner_if_ctx);
5822
5823 /* Store the tessellation factors. */
5824 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5825 MIN2(stride, 4), byteoffset, tf_base,
5826 4, 1, 0, true, false);
5827 if (vec1)
5828 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5829 stride - 4, byteoffset, tf_base,
5830 20, 1, 0, true, false);
5831
5832 //TODO store to offchip for TES to read - only if TES reads them
5833 if (1) {
5834 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5835 LLVMValueRef tf_inner_offset;
5836 unsigned param_outer, param_inner;
5837
5838 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5839 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5840 LLVMConstInt(ctx->i32, param_outer, 0));
5841
5842 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5843 util_next_power_of_two(outer_comps));
5844
5845 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5846 outer_comps, tf_outer_offset,
5847 ctx->oc_lds, 0, 1, 0, true, false);
5848 if (inner_comps) {
5849 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5850 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5851 LLVMConstInt(ctx->i32, param_inner, 0));
5852
5853 inner_vec = inner_comps == 1 ? inner[0] :
5854 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5855 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5856 inner_comps, tf_inner_offset,
5857 ctx->oc_lds, 0, 1, 0, true, false);
5858 }
5859 }
5860 ac_nir_build_endif(&if_ctx);
5861 }
5862
5863 static void
5864 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5865 {
5866 write_tess_factors(ctx);
5867 }
5868
5869 static bool
5870 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5871 LLVMValueRef *color, unsigned param, bool is_last,
5872 struct ac_export_args *args)
5873 {
5874 /* Export */
5875 si_llvm_init_export_args(ctx, color, param,
5876 args);
5877
5878 if (is_last) {
5879 args->valid_mask = 1; /* whether the EXEC mask is valid */
5880 args->done = 1; /* DONE bit */
5881 } else if (!args->enabled_channels)
5882 return false; /* unnecessary NULL export */
5883
5884 return true;
5885 }
5886
5887 static void
5888 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5889 LLVMValueRef depth, LLVMValueRef stencil,
5890 LLVMValueRef samplemask)
5891 {
5892 struct ac_export_args args;
5893
5894 args.enabled_channels = 0;
5895 args.valid_mask = 1;
5896 args.done = 1;
5897 args.target = V_008DFC_SQ_EXP_MRTZ;
5898 args.compr = false;
5899
5900 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5901 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5902 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5903 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5904
5905 if (depth) {
5906 args.out[0] = depth;
5907 args.enabled_channels |= 0x1;
5908 }
5909
5910 if (stencil) {
5911 args.out[1] = stencil;
5912 args.enabled_channels |= 0x2;
5913 }
5914
5915 if (samplemask) {
5916 args.out[2] = samplemask;
5917 args.enabled_channels |= 0x4;
5918 }
5919
5920 /* SI (except OLAND and HAINAN) has a bug that it only looks
5921 * at the X writemask component. */
5922 if (ctx->options->chip_class == SI &&
5923 ctx->options->family != CHIP_OLAND &&
5924 ctx->options->family != CHIP_HAINAN)
5925 args.enabled_channels |= 0x1;
5926
5927 ac_build_export(&ctx->ac, &args);
5928 }
5929
5930 static void
5931 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5932 {
5933 unsigned index = 0;
5934 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5935 struct ac_export_args color_args[8];
5936
5937 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5938 LLVMValueRef values[4];
5939
5940 if (!(ctx->output_mask & (1ull << i)))
5941 continue;
5942
5943 if (i == FRAG_RESULT_DEPTH) {
5944 ctx->shader_info->fs.writes_z = true;
5945 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5946 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5947 } else if (i == FRAG_RESULT_STENCIL) {
5948 ctx->shader_info->fs.writes_stencil = true;
5949 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5950 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5951 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5952 ctx->shader_info->fs.writes_sample_mask = true;
5953 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5954 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5955 } else {
5956 bool last = false;
5957 for (unsigned j = 0; j < 4; j++)
5958 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5959 ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5960
5961 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5962 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5963
5964 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5965 if (ret)
5966 index++;
5967 }
5968 }
5969
5970 for (unsigned i = 0; i < index; i++)
5971 ac_build_export(&ctx->ac, &color_args[i]);
5972 if (depth || stencil || samplemask)
5973 si_export_mrt_z(ctx, depth, stencil, samplemask);
5974 else if (!index) {
5975 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5976 ac_build_export(&ctx->ac, &color_args[0]);
5977 }
5978
5979 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5980 }
5981
5982 static void
5983 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5984 {
5985 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5986 }
5987
5988 static void
5989 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
5990 LLVMValueRef *addrs)
5991 {
5992 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
5993
5994 switch (ctx->stage) {
5995 case MESA_SHADER_VERTEX:
5996 if (ctx->options->key.vs.as_ls)
5997 handle_ls_outputs_post(ctx);
5998 else if (ctx->options->key.vs.as_es)
5999 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6000 else
6001 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6002 &ctx->shader_info->vs.outinfo);
6003 break;
6004 case MESA_SHADER_FRAGMENT:
6005 handle_fs_outputs_post(ctx);
6006 break;
6007 case MESA_SHADER_GEOMETRY:
6008 emit_gs_epilogue(ctx);
6009 break;
6010 case MESA_SHADER_TESS_CTRL:
6011 handle_tcs_outputs_post(ctx);
6012 break;
6013 case MESA_SHADER_TESS_EVAL:
6014 if (ctx->options->key.tes.as_es)
6015 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6016 else
6017 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6018 &ctx->shader_info->tes.outinfo);
6019 break;
6020 default:
6021 break;
6022 }
6023 }
6024
6025 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6026 {
6027 LLVMPassManagerRef passmgr;
6028 /* Create the pass manager */
6029 passmgr = LLVMCreateFunctionPassManagerForModule(
6030 ctx->module);
6031
6032 /* This pass should eliminate all the load and store instructions */
6033 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6034
6035 /* Add some optimization passes */
6036 LLVMAddScalarReplAggregatesPass(passmgr);
6037 LLVMAddLICMPass(passmgr);
6038 LLVMAddAggressiveDCEPass(passmgr);
6039 LLVMAddCFGSimplificationPass(passmgr);
6040 LLVMAddInstructionCombiningPass(passmgr);
6041
6042 /* Run the pass */
6043 LLVMInitializeFunctionPassManager(passmgr);
6044 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6045 LLVMFinalizeFunctionPassManager(passmgr);
6046
6047 LLVMDisposeBuilder(ctx->builder);
6048 LLVMDisposePassManager(passmgr);
6049 }
6050
6051 static void
6052 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6053 {
6054 struct ac_vs_output_info *outinfo;
6055
6056 switch (ctx->stage) {
6057 case MESA_SHADER_FRAGMENT:
6058 case MESA_SHADER_COMPUTE:
6059 case MESA_SHADER_TESS_CTRL:
6060 case MESA_SHADER_GEOMETRY:
6061 return;
6062 case MESA_SHADER_VERTEX:
6063 if (ctx->options->key.vs.as_ls ||
6064 ctx->options->key.vs.as_es)
6065 return;
6066 outinfo = &ctx->shader_info->vs.outinfo;
6067 break;
6068 case MESA_SHADER_TESS_EVAL:
6069 if (ctx->options->key.vs.as_es)
6070 return;
6071 outinfo = &ctx->shader_info->tes.outinfo;
6072 break;
6073 default:
6074 unreachable("Unhandled shader type");
6075 }
6076
6077 ac_optimize_vs_outputs(&ctx->ac,
6078 ctx->main_function,
6079 outinfo->vs_output_param_offset,
6080 VARYING_SLOT_MAX,
6081 &outinfo->param_exports);
6082 }
6083
6084 static void
6085 ac_setup_rings(struct nir_to_llvm_context *ctx)
6086 {
6087 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6088 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6089 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
6090 }
6091
6092 if (ctx->is_gs_copy_shader) {
6093 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
6094 }
6095 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6096 LLVMValueRef tmp;
6097 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
6098 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
6099
6100 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
6101
6102 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
6103 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
6104 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6105 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6106 }
6107
6108 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6109 ctx->stage == MESA_SHADER_TESS_EVAL) {
6110 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6111 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6112 }
6113 }
6114
6115 static unsigned
6116 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6117 const struct nir_shader *nir)
6118 {
6119 switch (nir->stage) {
6120 case MESA_SHADER_TESS_CTRL:
6121 return chip_class >= CIK ? 128 : 64;
6122 case MESA_SHADER_GEOMETRY:
6123 return 64;
6124 case MESA_SHADER_COMPUTE:
6125 break;
6126 default:
6127 return 0;
6128 }
6129
6130 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6131 nir->info.cs.local_size[1] *
6132 nir->info.cs.local_size[2];
6133 return max_workgroup_size;
6134 }
6135
6136 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6137 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6138 {
6139 struct ac_nir_context ctx = {};
6140 struct nir_function *func;
6141
6142 ctx.ac = *ac;
6143 ctx.abi = abi;
6144
6145 ctx.nctx = nctx;
6146 if (nctx)
6147 nctx->nir = &ctx;
6148
6149 ctx.stage = nir->stage;
6150
6151 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6152
6153 nir_foreach_variable(variable, &nir->outputs)
6154 handle_shader_output_decl(&ctx, nir, variable);
6155
6156 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6157 _mesa_key_pointer_equal);
6158 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6159 _mesa_key_pointer_equal);
6160 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6161 _mesa_key_pointer_equal);
6162
6163 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6164
6165 setup_locals(&ctx, func);
6166
6167 if (nir->stage == MESA_SHADER_COMPUTE)
6168 setup_shared(&ctx, nir);
6169
6170 visit_cf_list(&ctx, &func->impl->body);
6171 phi_post_pass(&ctx);
6172
6173 ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
6174 ctx.outputs);
6175
6176 free(ctx.locals);
6177 ralloc_free(ctx.defs);
6178 ralloc_free(ctx.phis);
6179 ralloc_free(ctx.vars);
6180
6181 if (nctx)
6182 nctx->nir = NULL;
6183 }
6184
6185 static
6186 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6187 struct nir_shader *nir,
6188 struct ac_shader_variant_info *shader_info,
6189 const struct ac_nir_compiler_options *options)
6190 {
6191 struct nir_to_llvm_context ctx = {0};
6192 unsigned i;
6193 ctx.options = options;
6194 ctx.shader_info = shader_info;
6195 ctx.context = LLVMContextCreate();
6196 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6197
6198 ac_llvm_context_init(&ctx.ac, ctx.context);
6199 ctx.ac.module = ctx.module;
6200
6201 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
6202
6203 memset(shader_info, 0, sizeof(*shader_info));
6204
6205 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6206
6207 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6208
6209 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6210 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6211 LLVMSetDataLayout(ctx.module, data_layout_str);
6212 LLVMDisposeTargetData(data_layout);
6213 LLVMDisposeMessage(data_layout_str);
6214
6215 setup_types(&ctx);
6216
6217 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6218 ctx.ac.builder = ctx.builder;
6219 ctx.stage = nir->stage;
6220 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6221
6222 for (i = 0; i < AC_UD_MAX_SETS; i++)
6223 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6224 for (i = 0; i < AC_UD_MAX_UD; i++)
6225 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6226
6227 create_function(&ctx);
6228
6229 if (nir->stage == MESA_SHADER_GEOMETRY) {
6230 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
6231
6232 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6233 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6234 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6235 }
6236
6237 ac_setup_rings(&ctx);
6238
6239 ctx.num_output_clips = nir->info.clip_distance_array_size;
6240 ctx.num_output_culls = nir->info.cull_distance_array_size;
6241
6242 nir_foreach_variable(variable, &nir->inputs)
6243 handle_shader_input_decl(&ctx, variable);
6244
6245 if (nir->stage == MESA_SHADER_FRAGMENT)
6246 handle_fs_inputs_pre(&ctx, nir);
6247
6248 ctx.abi.chip_class = options->chip_class;
6249 ctx.abi.inputs = &ctx.inputs[0];
6250 ctx.abi.emit_outputs = handle_shader_outputs_post;
6251 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6252
6253 nir_foreach_variable(variable, &nir->outputs)
6254 scan_shader_output_decl(&ctx, variable);
6255
6256 ac_nir_translate(&ctx.ac, &ctx.abi, nir, &ctx);
6257
6258 LLVMBuildRetVoid(ctx.builder);
6259
6260 ac_llvm_finalize_module(&ctx);
6261
6262 ac_nir_eliminate_const_vs_outputs(&ctx);
6263
6264 if (nir->stage == MESA_SHADER_GEOMETRY) {
6265 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6266 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6267 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6268 nir->info.gs.vertices_out;
6269 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6270 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6271 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6272 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6273 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6274 }
6275
6276 return ctx.module;
6277 }
6278
6279 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6280 {
6281 unsigned *retval = (unsigned *)context;
6282 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6283 char *description = LLVMGetDiagInfoDescription(di);
6284
6285 if (severity == LLVMDSError) {
6286 *retval = 1;
6287 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6288 description);
6289 }
6290
6291 LLVMDisposeMessage(description);
6292 }
6293
6294 static unsigned ac_llvm_compile(LLVMModuleRef M,
6295 struct ac_shader_binary *binary,
6296 LLVMTargetMachineRef tm)
6297 {
6298 unsigned retval = 0;
6299 char *err;
6300 LLVMContextRef llvm_ctx;
6301 LLVMMemoryBufferRef out_buffer;
6302 unsigned buffer_size;
6303 const char *buffer_data;
6304 LLVMBool mem_err;
6305
6306 /* Setup Diagnostic Handler*/
6307 llvm_ctx = LLVMGetModuleContext(M);
6308
6309 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6310 &retval);
6311
6312 /* Compile IR*/
6313 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6314 &err, &out_buffer);
6315
6316 /* Process Errors/Warnings */
6317 if (mem_err) {
6318 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6319 free(err);
6320 retval = 1;
6321 goto out;
6322 }
6323
6324 /* Extract Shader Code*/
6325 buffer_size = LLVMGetBufferSize(out_buffer);
6326 buffer_data = LLVMGetBufferStart(out_buffer);
6327
6328 ac_elf_read(buffer_data, buffer_size, binary);
6329
6330 /* Clean up */
6331 LLVMDisposeMemoryBuffer(out_buffer);
6332
6333 out:
6334 return retval;
6335 }
6336
6337 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6338 LLVMModuleRef llvm_module,
6339 struct ac_shader_binary *binary,
6340 struct ac_shader_config *config,
6341 struct ac_shader_variant_info *shader_info,
6342 gl_shader_stage stage,
6343 bool dump_shader, bool supports_spill)
6344 {
6345 if (dump_shader)
6346 ac_dump_module(llvm_module);
6347
6348 memset(binary, 0, sizeof(*binary));
6349 int v = ac_llvm_compile(llvm_module, binary, tm);
6350 if (v) {
6351 fprintf(stderr, "compile failed\n");
6352 }
6353
6354 if (dump_shader)
6355 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6356
6357 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6358
6359 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6360 LLVMDisposeModule(llvm_module);
6361 LLVMContextDispose(ctx);
6362
6363 if (stage == MESA_SHADER_FRAGMENT) {
6364 shader_info->num_input_vgprs = 0;
6365 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6366 shader_info->num_input_vgprs += 2;
6367 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6368 shader_info->num_input_vgprs += 2;
6369 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6370 shader_info->num_input_vgprs += 2;
6371 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6372 shader_info->num_input_vgprs += 3;
6373 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6374 shader_info->num_input_vgprs += 2;
6375 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6376 shader_info->num_input_vgprs += 2;
6377 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6378 shader_info->num_input_vgprs += 2;
6379 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6380 shader_info->num_input_vgprs += 1;
6381 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6382 shader_info->num_input_vgprs += 1;
6383 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6384 shader_info->num_input_vgprs += 1;
6385 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6386 shader_info->num_input_vgprs += 1;
6387 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6388 shader_info->num_input_vgprs += 1;
6389 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6390 shader_info->num_input_vgprs += 1;
6391 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6392 shader_info->num_input_vgprs += 1;
6393 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6394 shader_info->num_input_vgprs += 1;
6395 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6396 shader_info->num_input_vgprs += 1;
6397 }
6398 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6399
6400 /* +3 for scratch wave offset and VCC */
6401 config->num_sgprs = MAX2(config->num_sgprs,
6402 shader_info->num_input_sgprs + 3);
6403 }
6404
6405 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6406 struct ac_shader_binary *binary,
6407 struct ac_shader_config *config,
6408 struct ac_shader_variant_info *shader_info,
6409 struct nir_shader *nir,
6410 const struct ac_nir_compiler_options *options,
6411 bool dump_shader)
6412 {
6413
6414 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6415 options);
6416
6417 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6418 switch (nir->stage) {
6419 case MESA_SHADER_COMPUTE:
6420 for (int i = 0; i < 3; ++i)
6421 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6422 break;
6423 case MESA_SHADER_FRAGMENT:
6424 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6425 break;
6426 case MESA_SHADER_GEOMETRY:
6427 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6428 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6429 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6430 shader_info->gs.invocations = nir->info.gs.invocations;
6431 break;
6432 case MESA_SHADER_TESS_EVAL:
6433 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6434 shader_info->tes.spacing = nir->info.tess.spacing;
6435 shader_info->tes.ccw = nir->info.tess.ccw;
6436 shader_info->tes.point_mode = nir->info.tess.point_mode;
6437 shader_info->tes.as_es = options->key.tes.as_es;
6438 break;
6439 case MESA_SHADER_TESS_CTRL:
6440 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6441 break;
6442 case MESA_SHADER_VERTEX:
6443 shader_info->vs.as_es = options->key.vs.as_es;
6444 shader_info->vs.as_ls = options->key.vs.as_ls;
6445 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6446 if (options->key.vs.as_ls)
6447 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6448 break;
6449 default:
6450 break;
6451 }
6452 }
6453
6454 static void
6455 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6456 {
6457 LLVMValueRef args[9];
6458 args[0] = ctx->gsvs_ring;
6459 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6460 args[3] = ctx->i32zero;
6461 args[4] = ctx->i32one; /* OFFEN */
6462 args[5] = ctx->i32zero; /* IDXEN */
6463 args[6] = ctx->i32one; /* GLC */
6464 args[7] = ctx->i32one; /* SLC */
6465 args[8] = ctx->i32zero; /* TFE */
6466
6467 int idx = 0;
6468
6469 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6470 int length = 4;
6471 int slot = idx;
6472 int slot_inc = 1;
6473 if (!(ctx->output_mask & (1ull << i)))
6474 continue;
6475
6476 if (i == VARYING_SLOT_CLIP_DIST0) {
6477 /* unpack clip and cull from a single set of slots */
6478 length = ctx->num_output_clips + ctx->num_output_culls;
6479 if (length > 4)
6480 slot_inc = 2;
6481 }
6482
6483 for (unsigned j = 0; j < length; j++) {
6484 LLVMValueRef value;
6485 args[2] = LLVMConstInt(ctx->i32,
6486 (slot * 4 + j) *
6487 ctx->gs_max_out_vertices * 16 * 4, false);
6488
6489 value = ac_build_intrinsic(&ctx->ac,
6490 "llvm.SI.buffer.load.dword.i32.i32",
6491 ctx->i32, args, 9,
6492 AC_FUNC_ATTR_READONLY |
6493 AC_FUNC_ATTR_LEGACY);
6494
6495 LLVMBuildStore(ctx->builder,
6496 to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
6497 }
6498 idx += slot_inc;
6499 }
6500 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6501 }
6502
6503 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6504 struct nir_shader *geom_shader,
6505 struct ac_shader_binary *binary,
6506 struct ac_shader_config *config,
6507 struct ac_shader_variant_info *shader_info,
6508 const struct ac_nir_compiler_options *options,
6509 bool dump_shader)
6510 {
6511 struct nir_to_llvm_context ctx = {0};
6512 ctx.context = LLVMContextCreate();
6513 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6514 ctx.options = options;
6515 ctx.shader_info = shader_info;
6516
6517 ac_llvm_context_init(&ctx.ac, ctx.context);
6518 ctx.ac.module = ctx.module;
6519
6520 ctx.is_gs_copy_shader = true;
6521 LLVMSetTarget(ctx.module, "amdgcn--");
6522 setup_types(&ctx);
6523
6524 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6525 ctx.ac.builder = ctx.builder;
6526 ctx.stage = MESA_SHADER_VERTEX;
6527
6528 create_function(&ctx);
6529
6530 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6531 ac_setup_rings(&ctx);
6532
6533 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6534 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6535
6536 struct ac_nir_context nir_ctx = {};
6537 nir_ctx.ac = ctx.ac;
6538 nir_ctx.abi = &ctx.abi;
6539
6540 nir_ctx.nctx = &ctx;
6541 ctx.nir = &nir_ctx;
6542
6543 nir_foreach_variable(variable, &geom_shader->outputs) {
6544 scan_shader_output_decl(&ctx, variable);
6545 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
6546 }
6547
6548 ac_gs_copy_shader_emit(&ctx);
6549
6550 ctx.nir = NULL;
6551
6552 LLVMBuildRetVoid(ctx.builder);
6553
6554 ac_llvm_finalize_module(&ctx);
6555
6556 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6557 MESA_SHADER_VERTEX,
6558 dump_shader, options->supports_spill);
6559 }