projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ac/nir: start using ac_shader_abi
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_exp_param.h"
36
37 enum radeon_llvm_calling_convention {
38 RADEON_LLVM_AMDGPU_VS = 87,
39 RADEON_LLVM_AMDGPU_GS = 88,
40 RADEON_LLVM_AMDGPU_PS = 89,
41 RADEON_LLVM_AMDGPU_CS = 90,
42 };
43
44 #define CONST_ADDR_SPACE 2
45 #define LOCAL_ADDR_SPACE 3
46
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
49
50 enum desc_type {
51 DESC_IMAGE,
52 DESC_FMASK,
53 DESC_SAMPLER,
54 DESC_BUFFER,
55 };
56
57 struct nir_to_llvm_context {
58 struct ac_llvm_context ac;
59 const struct ac_nir_compiler_options *options;
60 struct ac_shader_variant_info *shader_info;
61 struct ac_shader_abi abi;
62
63 unsigned max_workgroup_size;
64 LLVMContextRef context;
65 LLVMModuleRef module;
66 LLVMBuilderRef builder;
67 LLVMValueRef main_function;
68
69 struct hash_table *defs;
70 struct hash_table *phis;
71 struct hash_table *vars;
72
73 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
74 LLVMValueRef ring_offsets;
75 LLVMValueRef push_constants;
76 LLVMValueRef num_work_groups;
77 LLVMValueRef workgroup_ids;
78 LLVMValueRef local_invocation_ids;
79 LLVMValueRef tg_size;
80
81 LLVMValueRef vertex_buffers;
82 LLVMValueRef rel_auto_id;
83 LLVMValueRef vs_prim_id;
84 LLVMValueRef ls_out_layout;
85 LLVMValueRef es2gs_offset;
86
87 LLVMValueRef tcs_offchip_layout;
88 LLVMValueRef tcs_out_offsets;
89 LLVMValueRef tcs_out_layout;
90 LLVMValueRef tcs_in_layout;
91 LLVMValueRef oc_lds;
92 LLVMValueRef tess_factor_offset;
93 LLVMValueRef tcs_patch_id;
94 LLVMValueRef tcs_rel_ids;
95 LLVMValueRef tes_rel_patch_id;
96 LLVMValueRef tes_patch_id;
97 LLVMValueRef tes_u;
98 LLVMValueRef tes_v;
99
100 LLVMValueRef gsvs_ring_stride;
101 LLVMValueRef gsvs_num_entries;
102 LLVMValueRef gs2vs_offset;
103 LLVMValueRef gs_wave_id;
104 LLVMValueRef gs_vtx_offset[6];
105 LLVMValueRef gs_prim_id, gs_invocation_id;
106
107 LLVMValueRef esgs_ring;
108 LLVMValueRef gsvs_ring;
109 LLVMValueRef hs_ring_tess_offchip;
110 LLVMValueRef hs_ring_tess_factor;
111
112 LLVMValueRef prim_mask;
113 LLVMValueRef sample_pos_offset;
114 LLVMValueRef persp_sample, persp_center, persp_centroid;
115 LLVMValueRef linear_sample, linear_center, linear_centroid;
116 LLVMValueRef front_face;
117 LLVMValueRef ancillary;
118 LLVMValueRef sample_coverage;
119 LLVMValueRef frag_pos[4];
120
121 LLVMBasicBlockRef continue_block;
122 LLVMBasicBlockRef break_block;
123
124 LLVMTypeRef i1;
125 LLVMTypeRef i8;
126 LLVMTypeRef i16;
127 LLVMTypeRef i32;
128 LLVMTypeRef i64;
129 LLVMTypeRef v2i32;
130 LLVMTypeRef v3i32;
131 LLVMTypeRef v4i32;
132 LLVMTypeRef v8i32;
133 LLVMTypeRef f64;
134 LLVMTypeRef f32;
135 LLVMTypeRef f16;
136 LLVMTypeRef v2f32;
137 LLVMTypeRef v4f32;
138 LLVMTypeRef voidt;
139
140 LLVMValueRef i1true;
141 LLVMValueRef i1false;
142 LLVMValueRef i32zero;
143 LLVMValueRef i32one;
144 LLVMValueRef f32zero;
145 LLVMValueRef f32one;
146 LLVMValueRef v4f32empty;
147
148 unsigned uniform_md_kind;
149 LLVMValueRef empty_md;
150 gl_shader_stage stage;
151
152 LLVMValueRef lds;
153 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
154 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
155
156 uint64_t input_mask;
157 uint64_t output_mask;
158 int num_locals;
159 LLVMValueRef *locals;
160 uint8_t num_output_clips;
161 uint8_t num_output_culls;
162
163 bool has_ds_bpermute;
164
165 bool is_gs_copy_shader;
166 LLVMValueRef gs_next_vertex;
167 unsigned gs_max_out_vertices;
168
169 unsigned tes_primitive_mode;
170 uint64_t tess_outputs_written;
171 uint64_t tess_patch_outputs_written;
172 };
173
174 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
175 const nir_deref_var *deref,
176 enum desc_type desc_type);
177 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
178 {
179 return (index * 4) + chan;
180 }
181
182 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
183 {
184 /* handle patch indices separate */
185 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
186 return 0;
187 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
188 return 1;
189 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
190 return 2 + (slot - VARYING_SLOT_PATCH0);
191
192 if (slot == VARYING_SLOT_POS)
193 return 0;
194 if (slot == VARYING_SLOT_PSIZ)
195 return 1;
196 if (slot == VARYING_SLOT_CLIP_DIST0)
197 return 2;
198 /* 3 is reserved for clip dist as well */
199 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
200 return 4 + (slot - VARYING_SLOT_VAR0);
201 unreachable("illegal slot in get unique index\n");
202 }
203
204 static unsigned llvm_get_type_size(LLVMTypeRef type)
205 {
206 LLVMTypeKind kind = LLVMGetTypeKind(type);
207
208 switch (kind) {
209 case LLVMIntegerTypeKind:
210 return LLVMGetIntTypeWidth(type) / 8;
211 case LLVMFloatTypeKind:
212 return 4;
213 case LLVMPointerTypeKind:
214 return 8;
215 case LLVMVectorTypeKind:
216 return LLVMGetVectorSize(type) *
217 llvm_get_type_size(LLVMGetElementType(type));
218 default:
219 assert(0);
220 return 0;
221 }
222 }
223
224 static void set_llvm_calling_convention(LLVMValueRef func,
225 gl_shader_stage stage)
226 {
227 enum radeon_llvm_calling_convention calling_conv;
228
229 switch (stage) {
230 case MESA_SHADER_VERTEX:
231 case MESA_SHADER_TESS_CTRL:
232 case MESA_SHADER_TESS_EVAL:
233 calling_conv = RADEON_LLVM_AMDGPU_VS;
234 break;
235 case MESA_SHADER_GEOMETRY:
236 calling_conv = RADEON_LLVM_AMDGPU_GS;
237 break;
238 case MESA_SHADER_FRAGMENT:
239 calling_conv = RADEON_LLVM_AMDGPU_PS;
240 break;
241 case MESA_SHADER_COMPUTE:
242 calling_conv = RADEON_LLVM_AMDGPU_CS;
243 break;
244 default:
245 unreachable("Unhandle shader type");
246 }
247
248 LLVMSetFunctionCallConv(func, calling_conv);
249 }
250
251 #define MAX_ARGS 23
252 struct arg_info {
253 LLVMTypeRef types[MAX_ARGS];
254 LLVMValueRef *assign[MAX_ARGS];
255 unsigned array_params_mask;
256 uint8_t count;
257 uint8_t user_sgpr_count;
258 uint8_t sgpr_count;
259 uint8_t num_user_sgprs_used;
260 uint8_t num_sgprs_used;
261 uint8_t num_vgprs_used;
262 };
263
264 static inline void
265 add_argument(struct arg_info *info,
266 LLVMTypeRef type, LLVMValueRef *param_ptr)
267 {
268 assert(info->count < MAX_ARGS);
269 info->assign[info->count] = param_ptr;
270 info->types[info->count] = type;
271 info->count++;
272 }
273
274 static inline void
275 add_sgpr_argument(struct arg_info *info,
276 LLVMTypeRef type, LLVMValueRef *param_ptr)
277 {
278 add_argument(info, type, param_ptr);
279 info->num_sgprs_used += llvm_get_type_size(type) / 4;
280 info->sgpr_count++;
281 }
282
283 static inline void
284 add_user_sgpr_argument(struct arg_info *info,
285 LLVMTypeRef type,
286 LLVMValueRef *param_ptr)
287 {
288 add_sgpr_argument(info, type, param_ptr);
289 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
290 info->user_sgpr_count++;
291 }
292
293 static inline void
294 add_vgpr_argument(struct arg_info *info,
295 LLVMTypeRef type,
296 LLVMValueRef *param_ptr)
297 {
298 add_argument(info, type, param_ptr);
299 info->num_vgprs_used += llvm_get_type_size(type) / 4;
300 }
301
302 static inline void
303 add_user_sgpr_array_argument(struct arg_info *info,
304 LLVMTypeRef type,
305 LLVMValueRef *param_ptr)
306 {
307 info->array_params_mask |= (1 << info->count);
308 add_user_sgpr_argument(info, type, param_ptr);
309 }
310
311 static void assign_arguments(LLVMValueRef main_function,
312 struct arg_info *info)
313 {
314 unsigned i;
315 for (i = 0; i < info->count; i++) {
316 if (info->assign[i])
317 *info->assign[i] = LLVMGetParam(main_function, i);
318 }
319 }
320
321 static LLVMValueRef
322 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
323 LLVMBuilderRef builder, LLVMTypeRef *return_types,
324 unsigned num_return_elems,
325 struct arg_info *args,
326 unsigned max_workgroup_size,
327 bool unsafe_math)
328 {
329 LLVMTypeRef main_function_type, ret_type;
330 LLVMBasicBlockRef main_function_body;
331
332 if (num_return_elems)
333 ret_type = LLVMStructTypeInContext(ctx, return_types,
334 num_return_elems, true);
335 else
336 ret_type = LLVMVoidTypeInContext(ctx);
337
338 /* Setup the function */
339 main_function_type =
340 LLVMFunctionType(ret_type, args->types, args->count, 0);
341 LLVMValueRef main_function =
342 LLVMAddFunction(module, "main", main_function_type);
343 main_function_body =
344 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
345 LLVMPositionBuilderAtEnd(builder, main_function_body);
346
347 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
348 for (unsigned i = 0; i < args->sgpr_count; ++i) {
349 if (args->array_params_mask & (1 << i)) {
350 LLVMValueRef P = LLVMGetParam(main_function, i);
351 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
352 ac_add_attr_dereferenceable(P, UINT64_MAX);
353 }
354 else {
355 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
356 }
357 }
358
359 if (max_workgroup_size) {
360 ac_llvm_add_target_dep_function_attr(main_function,
361 "amdgpu-max-work-group-size",
362 max_workgroup_size);
363 }
364 if (unsafe_math) {
365 /* These were copied from some LLVM test. */
366 LLVMAddTargetDependentFunctionAttr(main_function,
367 "less-precise-fpmad",
368 "true");
369 LLVMAddTargetDependentFunctionAttr(main_function,
370 "no-infs-fp-math",
371 "true");
372 LLVMAddTargetDependentFunctionAttr(main_function,
373 "no-nans-fp-math",
374 "true");
375 LLVMAddTargetDependentFunctionAttr(main_function,
376 "unsafe-fp-math",
377 "true");
378 }
379 return main_function;
380 }
381
382 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
383 {
384 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
385 CONST_ADDR_SPACE);
386 }
387
388 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
389 {
390 if (t == ctx->f16 || t == ctx->i16)
391 return ctx->i16;
392 else if (t == ctx->f32 || t == ctx->i32)
393 return ctx->i32;
394 else if (t == ctx->f64 || t == ctx->i64)
395 return ctx->i64;
396 else
397 unreachable("Unhandled integer size");
398 }
399
400 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
401 {
402 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
403 LLVMTypeRef elem_type = LLVMGetElementType(t);
404 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
405 LLVMGetVectorSize(t));
406 }
407 return to_integer_type_scalar(ctx, t);
408 }
409
410 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
411 {
412 LLVMTypeRef type = LLVMTypeOf(v);
413 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
414 }
415
416 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
417 {
418 if (t == ctx->i16 || t == ctx->f16)
419 return ctx->f16;
420 else if (t == ctx->i32 || t == ctx->f32)
421 return ctx->f32;
422 else if (t == ctx->i64 || t == ctx->f64)
423 return ctx->f64;
424 else
425 unreachable("Unhandled float size");
426 }
427
428 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
429 {
430 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
431 LLVMTypeRef elem_type = LLVMGetElementType(t);
432 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
433 LLVMGetVectorSize(t));
434 }
435 return to_float_type_scalar(ctx, t);
436 }
437
438 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
439 {
440 LLVMTypeRef type = LLVMTypeOf(v);
441 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
442 }
443
444 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
445 {
446 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
447 type = LLVMGetElementType(type);
448
449 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
450 return LLVMGetIntTypeWidth(type);
451
452 if (type == ctx->f16)
453 return 16;
454 if (type == ctx->f32)
455 return 32;
456 if (type == ctx->f64)
457 return 64;
458
459 unreachable("Unhandled type kind in get_elem_bits");
460 }
461
462 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
463 LLVMValueRef param, unsigned rshift,
464 unsigned bitwidth)
465 {
466 LLVMValueRef value = param;
467 if (rshift)
468 value = LLVMBuildLShr(ctx->builder, value,
469 LLVMConstInt(ctx->i32, rshift, false), "");
470
471 if (rshift + bitwidth < 32) {
472 unsigned mask = (1 << bitwidth) - 1;
473 value = LLVMBuildAnd(ctx->builder, value,
474 LLVMConstInt(ctx->i32, mask, false), "");
475 }
476 return value;
477 }
478
479 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
480 {
481 switch (ctx->stage) {
482 case MESA_SHADER_TESS_CTRL:
483 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
484 case MESA_SHADER_TESS_EVAL:
485 return ctx->tes_rel_patch_id;
486 break;
487 default:
488 unreachable("Illegal stage");
489 }
490 }
491
492 /* Tessellation shaders pass outputs to the next shader using LDS.
493 *
494 * LS outputs = TCS inputs
495 * TCS outputs = TES inputs
496 *
497 * The LDS layout is:
498 * - TCS inputs for patch 0
499 * - TCS inputs for patch 1
500 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
501 * - ...
502 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
503 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
504 * - TCS outputs for patch 1
505 * - Per-patch TCS outputs for patch 1
506 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
507 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
508 * - ...
509 *
510 * All three shaders VS(LS), TCS, TES share the same LDS space.
511 */
512 static LLVMValueRef
513 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
514 {
515 if (ctx->stage == MESA_SHADER_VERTEX)
516 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
517 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
518 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
519 else {
520 assert(0);
521 return NULL;
522 }
523 }
524
525 static LLVMValueRef
526 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
527 {
528 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
529 }
530
531 static LLVMValueRef
532 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
533 {
534 return LLVMBuildMul(ctx->builder,
535 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
536 LLVMConstInt(ctx->i32, 4, false), "");
537 }
538
539 static LLVMValueRef
540 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
541 {
542 return LLVMBuildMul(ctx->builder,
543 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
544 LLVMConstInt(ctx->i32, 4, false), "");
545 }
546
547 static LLVMValueRef
548 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
549 {
550 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
551 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
552
553 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
554 }
555
556 static LLVMValueRef
557 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
558 {
559 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
560 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
561 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
562
563 return LLVMBuildAdd(ctx->builder, patch0_offset,
564 LLVMBuildMul(ctx->builder, patch_stride,
565 rel_patch_id, ""),
566 "");
567 }
568
569 static LLVMValueRef
570 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
571 {
572 LLVMValueRef patch0_patch_data_offset =
573 get_tcs_out_patch0_patch_data_offset(ctx);
574 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
575 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
576
577 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
578 LLVMBuildMul(ctx->builder, patch_stride,
579 rel_patch_id, ""),
580 "");
581 }
582
583 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
584 {
585 ud_info->sgpr_idx = *sgpr_idx;
586 ud_info->num_sgprs = num_sgprs;
587 ud_info->indirect = false;
588 ud_info->indirect_offset = 0;
589 *sgpr_idx += num_sgprs;
590 }
591
592 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
593 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
594 {
595 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
596 }
597
598
599 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
600 uint32_t indirect_offset)
601 {
602 ud_info->sgpr_idx = sgpr_idx;
603 ud_info->num_sgprs = num_sgprs;
604 ud_info->indirect = true;
605 ud_info->indirect_offset = indirect_offset;
606 }
607
608 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
609 {
610 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
611 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
612 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
613 "tess_lds");
614 }
615
616 struct user_sgpr_info {
617 bool need_ring_offsets;
618 uint8_t sgpr_count;
619 bool indirect_all_descriptor_sets;
620 };
621
622 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
623 struct user_sgpr_info *user_sgpr_info)
624 {
625 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
626
627 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
628 if (ctx->stage == MESA_SHADER_GEOMETRY ||
629 ctx->stage == MESA_SHADER_VERTEX ||
630 ctx->stage == MESA_SHADER_TESS_CTRL ||
631 ctx->stage == MESA_SHADER_TESS_EVAL ||
632 ctx->is_gs_copy_shader)
633 user_sgpr_info->need_ring_offsets = true;
634
635 if (ctx->stage == MESA_SHADER_FRAGMENT &&
636 ctx->shader_info->info.ps.needs_sample_positions)
637 user_sgpr_info->need_ring_offsets = true;
638
639 /* 2 user sgprs will nearly always be allocated for scratch/rings */
640 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
641 user_sgpr_info->sgpr_count += 2;
642 }
643
644 switch (ctx->stage) {
645 case MESA_SHADER_COMPUTE:
646 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
647 break;
648 case MESA_SHADER_FRAGMENT:
649 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
650 break;
651 case MESA_SHADER_VERTEX:
652 if (!ctx->is_gs_copy_shader) {
653 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
654 if (ctx->shader_info->info.vs.needs_draw_id) {
655 user_sgpr_info->sgpr_count += 3;
656 } else {
657 user_sgpr_info->sgpr_count += 2;
658 }
659 }
660 if (ctx->options->key.vs.as_ls)
661 user_sgpr_info->sgpr_count++;
662 break;
663 case MESA_SHADER_TESS_CTRL:
664 user_sgpr_info->sgpr_count += 4;
665 break;
666 case MESA_SHADER_TESS_EVAL:
667 user_sgpr_info->sgpr_count += 1;
668 break;
669 case MESA_SHADER_GEOMETRY:
670 user_sgpr_info->sgpr_count += 2;
671 break;
672 default:
673 break;
674 }
675
676 if (ctx->shader_info->info.needs_push_constants)
677 user_sgpr_info->sgpr_count += 2;
678
679 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
680 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
681 user_sgpr_info->sgpr_count += 2;
682 user_sgpr_info->indirect_all_descriptor_sets = true;
683 } else {
684 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
685 }
686 }
687
688 static void create_function(struct nir_to_llvm_context *ctx)
689 {
690 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
691 uint8_t user_sgpr_idx;
692 struct user_sgpr_info user_sgpr_info;
693 struct arg_info args = {};
694 LLVMValueRef desc_sets;
695
696 allocate_user_sgprs(ctx, &user_sgpr_info);
697 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
698 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
699 }
700
701 /* 1 for each descriptor set */
702 if (!user_sgpr_info.indirect_all_descriptor_sets) {
703 for (unsigned i = 0; i < num_sets; ++i) {
704 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
705 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
706 }
707 }
708 } else
709 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
710
711 if (ctx->shader_info->info.needs_push_constants) {
712 /* 1 for push constants and dynamic descriptors */
713 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
714 }
715
716 switch (ctx->stage) {
717 case MESA_SHADER_COMPUTE:
718 if (ctx->shader_info->info.cs.grid_components_used)
719 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
720 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
721 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
722 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
723 break;
724 case MESA_SHADER_VERTEX:
725 if (!ctx->is_gs_copy_shader) {
726 if (ctx->shader_info->info.vs.has_vertex_buffers)
727 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
728 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.base_vertex); // base vertex
729 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.start_instance);// start instance
730 if (ctx->shader_info->info.vs.needs_draw_id)
731 add_user_sgpr_argument(&args, ctx->i32, &ctx->abi.draw_id); // draw id
732 }
733 if (ctx->options->key.vs.as_es)
734 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
735 else if (ctx->options->key.vs.as_ls)
736 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
737 add_vgpr_argument(&args, ctx->i32, &ctx->abi.vertex_id); // vertex id
738 if (!ctx->is_gs_copy_shader) {
739 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
740 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
741 add_vgpr_argument(&args, ctx->i32, &ctx->abi.instance_id); // instance id
742 }
743 break;
744 case MESA_SHADER_TESS_CTRL:
745 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
746 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
747 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
748 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
749 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
750 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
751 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
752 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
753 break;
754 case MESA_SHADER_TESS_EVAL:
755 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
756 if (ctx->options->key.tes.as_es) {
757 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
758 add_sgpr_argument(&args, ctx->i32, NULL); //
759 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
760 } else {
761 add_sgpr_argument(&args, ctx->i32, NULL); //
762 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
763 }
764 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
765 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
766 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
767 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
768 break;
769 case MESA_SHADER_GEOMETRY:
770 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
771 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
772 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
773 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
774 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
775 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
776 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
777 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
778 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
779 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
780 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
781 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
782 break;
783 case MESA_SHADER_FRAGMENT:
784 if (ctx->shader_info->info.ps.needs_sample_positions)
785 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
786 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
787 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
788 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
789 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
790 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
791 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
792 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
793 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
794 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
795 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
796 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
797 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
798 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
799 add_vgpr_argument(&args, ctx->i32, &ctx->front_face); /* front face */
800 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
801 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
802 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
803 break;
804 default:
805 unreachable("Shader stage not implemented");
806 }
807
808 ctx->main_function = create_llvm_function(
809 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
810 ctx->max_workgroup_size,
811 ctx->options->unsafe_math);
812 set_llvm_calling_convention(ctx->main_function, ctx->stage);
813
814
815 ctx->shader_info->num_input_vgprs = 0;
816 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
817 ctx->options->supports_spill ? 2 : 0;
818
819 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
820 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
821
822 if (ctx->stage != MESA_SHADER_FRAGMENT)
823 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
824
825 assign_arguments(ctx->main_function, &args);
826
827 user_sgpr_idx = 0;
828
829 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
830 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
831 if (ctx->options->supports_spill) {
832 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
833 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
834 NULL, 0, AC_FUNC_ATTR_READNONE);
835 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
836 const_array(ctx->v4i32, 16), "");
837 }
838 }
839
840 if (!user_sgpr_info.indirect_all_descriptor_sets) {
841 for (unsigned i = 0; i < num_sets; ++i) {
842 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
843 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
844 } else
845 ctx->descriptor_sets[i] = NULL;
846 }
847 } else {
848 uint32_t desc_sgpr_idx = user_sgpr_idx;
849 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
850
851 for (unsigned i = 0; i < num_sets; ++i) {
852 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
853 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
854 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
855
856 } else
857 ctx->descriptor_sets[i] = NULL;
858 }
859 ctx->shader_info->need_indirect_descriptor_sets = true;
860 }
861
862 if (ctx->shader_info->info.needs_push_constants) {
863 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
864 }
865
866 switch (ctx->stage) {
867 case MESA_SHADER_COMPUTE:
868 if (ctx->shader_info->info.cs.grid_components_used) {
869 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
870 }
871 break;
872 case MESA_SHADER_VERTEX:
873 if (!ctx->is_gs_copy_shader) {
874 if (ctx->shader_info->info.vs.has_vertex_buffers) {
875 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
876 }
877 unsigned vs_num = 2;
878 if (ctx->shader_info->info.vs.needs_draw_id)
879 vs_num++;
880
881 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
882 }
883 if (ctx->options->key.vs.as_ls) {
884 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
885 }
886 if (ctx->options->key.vs.as_ls)
887 declare_tess_lds(ctx);
888 break;
889 case MESA_SHADER_TESS_CTRL:
890 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
891 declare_tess_lds(ctx);
892 break;
893 case MESA_SHADER_TESS_EVAL:
894 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
895 break;
896 case MESA_SHADER_GEOMETRY:
897 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
898 break;
899 case MESA_SHADER_FRAGMENT:
900 if (ctx->shader_info->info.ps.needs_sample_positions) {
901 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
902 }
903 break;
904 default:
905 unreachable("Shader stage not implemented");
906 }
907 }
908
909 static void setup_types(struct nir_to_llvm_context *ctx)
910 {
911 LLVMValueRef args[4];
912
913 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
914 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
915 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
916 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
917 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
918 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
919 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
920 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
921 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
922 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
923 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
924 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
925 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
926 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
927 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
928
929 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
930 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
931 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
932 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
933 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
934 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
935
936 args[0] = ctx->f32zero;
937 args[1] = ctx->f32zero;
938 args[2] = ctx->f32zero;
939 args[3] = ctx->f32one;
940 ctx->v4f32empty = LLVMConstVector(args, 4);
941
942 ctx->uniform_md_kind =
943 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
944 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
945
946 args[0] = LLVMConstReal(ctx->f32, 2.5);
947 }
948
949 static int get_llvm_num_components(LLVMValueRef value)
950 {
951 LLVMTypeRef type = LLVMTypeOf(value);
952 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
953 ? LLVMGetVectorSize(type)
954 : 1;
955 return num_components;
956 }
957
958 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
959 LLVMValueRef value,
960 int index)
961 {
962 int count = get_llvm_num_components(value);
963
964 assert(index < count);
965 if (count == 1)
966 return value;
967
968 return LLVMBuildExtractElement(ctx->builder, value,
969 LLVMConstInt(ctx->i32, index, false), "");
970 }
971
972 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
973 LLVMValueRef value, unsigned count)
974 {
975 unsigned num_components = get_llvm_num_components(value);
976 if (count == num_components)
977 return value;
978
979 LLVMValueRef masks[] = {
980 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
981 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
982
983 if (count == 1)
984 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
985 "");
986
987 LLVMValueRef swizzle = LLVMConstVector(masks, count);
988 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
989 }
990
991 static void
992 build_store_values_extended(struct nir_to_llvm_context *ctx,
993 LLVMValueRef *values,
994 unsigned value_count,
995 unsigned value_stride,
996 LLVMValueRef vec)
997 {
998 LLVMBuilderRef builder = ctx->builder;
999 unsigned i;
1000
1001 if (value_count == 1) {
1002 LLVMBuildStore(builder, vec, values[0]);
1003 return;
1004 }
1005
1006 for (i = 0; i < value_count; i++) {
1007 LLVMValueRef ptr = values[i * value_stride];
1008 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
1009 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1010 LLVMBuildStore(builder, value, ptr);
1011 }
1012 }
1013
1014 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
1015 const nir_ssa_def *def)
1016 {
1017 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
1018 if (def->num_components > 1) {
1019 type = LLVMVectorType(type, def->num_components);
1020 }
1021 return type;
1022 }
1023
1024 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1025 {
1026 assert(src.is_ssa);
1027 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1028 return (LLVMValueRef)entry->data;
1029 }
1030
1031
1032 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1033 const struct nir_block *b)
1034 {
1035 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1036 return (LLVMBasicBlockRef)entry->data;
1037 }
1038
1039 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1040 nir_alu_src src,
1041 unsigned num_components)
1042 {
1043 LLVMValueRef value = get_src(ctx, src.src);
1044 bool need_swizzle = false;
1045
1046 assert(value);
1047 LLVMTypeRef type = LLVMTypeOf(value);
1048 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1049 ? LLVMGetVectorSize(type)
1050 : 1;
1051
1052 for (unsigned i = 0; i < num_components; ++i) {
1053 assert(src.swizzle[i] < src_components);
1054 if (src.swizzle[i] != i)
1055 need_swizzle = true;
1056 }
1057
1058 if (need_swizzle || num_components != src_components) {
1059 LLVMValueRef masks[] = {
1060 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1061 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1062 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1063 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1064
1065 if (src_components > 1 && num_components == 1) {
1066 value = LLVMBuildExtractElement(ctx->builder, value,
1067 masks[0], "");
1068 } else if (src_components == 1 && num_components > 1) {
1069 LLVMValueRef values[] = {value, value, value, value};
1070 value = ac_build_gather_values(&ctx->ac, values, num_components);
1071 } else {
1072 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1073 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1074 swizzle, "");
1075 }
1076 }
1077 assert(!src.negate);
1078 assert(!src.abs);
1079 return value;
1080 }
1081
1082 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1083 LLVMIntPredicate pred, LLVMValueRef src0,
1084 LLVMValueRef src1)
1085 {
1086 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1087 return LLVMBuildSelect(ctx->builder, result,
1088 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1089 LLVMConstInt(ctx->i32, 0, false), "");
1090 }
1091
1092 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1093 LLVMRealPredicate pred, LLVMValueRef src0,
1094 LLVMValueRef src1)
1095 {
1096 LLVMValueRef result;
1097 src0 = to_float(ctx, src0);
1098 src1 = to_float(ctx, src1);
1099 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1100 return LLVMBuildSelect(ctx->builder, result,
1101 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1102 LLVMConstInt(ctx->i32, 0, false), "");
1103 }
1104
1105 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1106 const char *intrin,
1107 LLVMTypeRef result_type,
1108 LLVMValueRef src0)
1109 {
1110 char name[64];
1111 LLVMValueRef params[] = {
1112 to_float(ctx, src0),
1113 };
1114
1115 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1116 get_elem_bits(ctx, result_type));
1117 assert(length < sizeof(name));
1118 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1119 }
1120
1121 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1122 const char *intrin,
1123 LLVMTypeRef result_type,
1124 LLVMValueRef src0, LLVMValueRef src1)
1125 {
1126 char name[64];
1127 LLVMValueRef params[] = {
1128 to_float(ctx, src0),
1129 to_float(ctx, src1),
1130 };
1131
1132 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1133 get_elem_bits(ctx, result_type));
1134 assert(length < sizeof(name));
1135 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1136 }
1137
1138 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1139 const char *intrin,
1140 LLVMTypeRef result_type,
1141 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1142 {
1143 char name[64];
1144 LLVMValueRef params[] = {
1145 to_float(ctx, src0),
1146 to_float(ctx, src1),
1147 to_float(ctx, src2),
1148 };
1149
1150 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1151 get_elem_bits(ctx, result_type));
1152 assert(length < sizeof(name));
1153 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1154 }
1155
1156 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1157 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1158 {
1159 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1160 ctx->i32_0, "");
1161 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1162 }
1163
1164 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1165 LLVMValueRef src0)
1166 {
1167 LLVMValueRef params[2] = {
1168 src0,
1169
1170 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1171 * add special code to check for x=0. The reason is that
1172 * the LLVM behavior for x=0 is different from what we
1173 * need here.
1174 *
1175 * The hardware already implements the correct behavior.
1176 */
1177 LLVMConstInt(ctx->i1, 1, false),
1178 };
1179 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1180 }
1181
1182 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1183 LLVMValueRef src0)
1184 {
1185 return ac_build_imsb(ctx, src0, ctx->i32);
1186 }
1187
1188 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1189 LLVMValueRef src0)
1190 {
1191 return ac_build_umsb(ctx, src0, ctx->i32);
1192 }
1193
1194 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1195 LLVMIntPredicate pred,
1196 LLVMValueRef src0, LLVMValueRef src1)
1197 {
1198 return LLVMBuildSelect(ctx->builder,
1199 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1200 src0,
1201 src1, "");
1202
1203 }
1204 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1205 LLVMValueRef src0)
1206 {
1207 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1208 LLVMBuildNeg(ctx->builder, src0, ""));
1209 }
1210
1211 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1212 LLVMValueRef src0)
1213 {
1214 LLVMValueRef cmp, val;
1215
1216 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1217 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1218 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1219 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1220 return val;
1221 }
1222
1223 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1224 LLVMValueRef src0)
1225 {
1226 LLVMValueRef cmp, val;
1227
1228 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1229 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1230 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1231 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1232 return val;
1233 }
1234
1235 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1236 LLVMValueRef src0)
1237 {
1238 const char *intr = "llvm.floor.f32";
1239 LLVMValueRef fsrc0 = to_float(ctx, src0);
1240 LLVMValueRef params[] = {
1241 fsrc0,
1242 };
1243 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1244 ctx->f32, params, 1,
1245 AC_FUNC_ATTR_READNONE);
1246 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1247 }
1248
1249 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1250 const char *intrin,
1251 LLVMValueRef src0, LLVMValueRef src1)
1252 {
1253 LLVMTypeRef ret_type;
1254 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1255 LLVMValueRef res;
1256 LLVMValueRef params[] = { src0, src1 };
1257 ret_type = LLVMStructTypeInContext(ctx->context, types,
1258 2, true);
1259
1260 res = ac_build_intrinsic(ctx, intrin, ret_type,
1261 params, 2, AC_FUNC_ATTR_READNONE);
1262
1263 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1264 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1265 return res;
1266 }
1267
1268 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1269 LLVMValueRef src0)
1270 {
1271 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1272 }
1273
1274 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1275 LLVMValueRef src0)
1276 {
1277 src0 = to_float(ctx, src0);
1278 return LLVMBuildSExt(ctx->builder,
1279 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1280 ctx->i32, "");
1281 }
1282
1283 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1284 LLVMValueRef src0)
1285 {
1286 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1287 }
1288
1289 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1290 LLVMValueRef src0)
1291 {
1292 return LLVMBuildSExt(ctx->builder,
1293 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1294 ctx->i32, "");
1295 }
1296
1297 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1298 LLVMValueRef src0)
1299 {
1300 LLVMValueRef result;
1301 LLVMValueRef cond;
1302
1303 src0 = to_float(&ctx->ac, src0);
1304 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1305
1306 /* TODO SI/CIK options here */
1307 if (ctx->options->chip_class >= VI) {
1308 LLVMValueRef args[2];
1309 /* Check if the result is a denormal - and flush to 0 if so. */
1310 args[0] = result;
1311 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1312 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1313 }
1314
1315 /* need to convert back up to f32 */
1316 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1317
1318 if (ctx->options->chip_class >= VI)
1319 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1320
1321 return result;
1322 }
1323
1324 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1325 LLVMValueRef src0, LLVMValueRef src1)
1326 {
1327 LLVMValueRef dst64, result;
1328 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1329 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1330
1331 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1332 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1333 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1334 return result;
1335 }
1336
1337 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1338 LLVMValueRef src0, LLVMValueRef src1)
1339 {
1340 LLVMValueRef dst64, result;
1341 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1342 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1343
1344 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1345 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1346 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1347 return result;
1348 }
1349
1350 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1351 bool is_signed,
1352 const LLVMValueRef srcs[3])
1353 {
1354 LLVMValueRef result;
1355 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1356
1357 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1358 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1359 return result;
1360 }
1361
1362 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1363 LLVMValueRef src0, LLVMValueRef src1,
1364 LLVMValueRef src2, LLVMValueRef src3)
1365 {
1366 LLVMValueRef bfi_args[3], result;
1367
1368 bfi_args[0] = LLVMBuildShl(ctx->builder,
1369 LLVMBuildSub(ctx->builder,
1370 LLVMBuildShl(ctx->builder,
1371 ctx->i32_1,
1372 src3, ""),
1373 ctx->i32_1, ""),
1374 src2, "");
1375 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1376 bfi_args[2] = src0;
1377
1378 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1379
1380 /* Calculate:
1381 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1382 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1383 */
1384 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1385 LLVMBuildAnd(ctx->builder, bfi_args[0],
1386 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1387
1388 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1389 return result;
1390 }
1391
1392 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1393 LLVMValueRef src0)
1394 {
1395 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1396 int i;
1397 LLVMValueRef comp[2];
1398
1399 src0 = to_float(ctx, src0);
1400 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1401 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1402 for (i = 0; i < 2; i++) {
1403 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1404 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1405 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1406 }
1407
1408 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1409 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1410
1411 return comp[0];
1412 }
1413
1414 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1415 LLVMValueRef src0)
1416 {
1417 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1418 LLVMValueRef temps[2], result, val;
1419 int i;
1420
1421 for (i = 0; i < 2; i++) {
1422 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1423 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1424 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1425 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1426 }
1427
1428 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1429 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1430 ctx->i32_0, "");
1431 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1432 ctx->i32_1, "");
1433 return result;
1434 }
1435
1436 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1437 nir_op op,
1438 LLVMValueRef src0)
1439 {
1440 unsigned mask;
1441 int idx;
1442 LLVMValueRef result;
1443
1444 if (!ctx->lds && !ctx->has_ds_bpermute)
1445 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1446 LLVMArrayType(ctx->i32, 64),
1447 "ddxy_lds", LOCAL_ADDR_SPACE);
1448
1449 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1450 mask = AC_TID_MASK_LEFT;
1451 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1452 mask = AC_TID_MASK_TOP;
1453 else
1454 mask = AC_TID_MASK_TOP_LEFT;
1455
1456 /* for DDX we want to next X pixel, DDY next Y pixel. */
1457 if (op == nir_op_fddx_fine ||
1458 op == nir_op_fddx_coarse ||
1459 op == nir_op_fddx)
1460 idx = 1;
1461 else
1462 idx = 2;
1463
1464 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1465 mask, idx, ctx->lds,
1466 src0);
1467 return result;
1468 }
1469
1470 /*
1471 * this takes an I,J coordinate pair,
1472 * and works out the X and Y derivatives.
1473 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1474 */
1475 static LLVMValueRef emit_ddxy_interp(
1476 struct nir_to_llvm_context *ctx,
1477 LLVMValueRef interp_ij)
1478 {
1479 LLVMValueRef result[4], a;
1480 unsigned i;
1481
1482 for (i = 0; i < 2; i++) {
1483 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1484 LLVMConstInt(ctx->i32, i, false), "");
1485 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1486 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1487 }
1488 return ac_build_gather_values(&ctx->ac, result, 4);
1489 }
1490
1491 static void visit_alu(struct nir_to_llvm_context *ctx, const nir_alu_instr *instr)
1492 {
1493 LLVMValueRef src[4], result = NULL;
1494 unsigned num_components = instr->dest.dest.ssa.num_components;
1495 unsigned src_components;
1496 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1497
1498 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1499 switch (instr->op) {
1500 case nir_op_vec2:
1501 case nir_op_vec3:
1502 case nir_op_vec4:
1503 src_components = 1;
1504 break;
1505 case nir_op_pack_half_2x16:
1506 src_components = 2;
1507 break;
1508 case nir_op_unpack_half_2x16:
1509 src_components = 1;
1510 break;
1511 default:
1512 src_components = num_components;
1513 break;
1514 }
1515 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1516 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1517
1518 switch (instr->op) {
1519 case nir_op_fmov:
1520 case nir_op_imov:
1521 result = src[0];
1522 break;
1523 case nir_op_fneg:
1524 src[0] = to_float(&ctx->ac, src[0]);
1525 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1526 break;
1527 case nir_op_ineg:
1528 result = LLVMBuildNeg(ctx->builder, src[0], "");
1529 break;
1530 case nir_op_inot:
1531 result = LLVMBuildNot(ctx->builder, src[0], "");
1532 break;
1533 case nir_op_iadd:
1534 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1535 break;
1536 case nir_op_fadd:
1537 src[0] = to_float(&ctx->ac, src[0]);
1538 src[1] = to_float(&ctx->ac, src[1]);
1539 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1540 break;
1541 case nir_op_fsub:
1542 src[0] = to_float(&ctx->ac, src[0]);
1543 src[1] = to_float(&ctx->ac, src[1]);
1544 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1545 break;
1546 case nir_op_isub:
1547 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1548 break;
1549 case nir_op_imul:
1550 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1551 break;
1552 case nir_op_imod:
1553 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1554 break;
1555 case nir_op_umod:
1556 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1557 break;
1558 case nir_op_fmod:
1559 src[0] = to_float(&ctx->ac, src[0]);
1560 src[1] = to_float(&ctx->ac, src[1]);
1561 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1562 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1563 to_float_type(&ctx->ac, def_type), result);
1564 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1565 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1566 break;
1567 case nir_op_frem:
1568 src[0] = to_float(&ctx->ac, src[0]);
1569 src[1] = to_float(&ctx->ac, src[1]);
1570 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1571 break;
1572 case nir_op_irem:
1573 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1574 break;
1575 case nir_op_idiv:
1576 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1577 break;
1578 case nir_op_udiv:
1579 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1580 break;
1581 case nir_op_fmul:
1582 src[0] = to_float(&ctx->ac, src[0]);
1583 src[1] = to_float(&ctx->ac, src[1]);
1584 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1585 break;
1586 case nir_op_fdiv:
1587 src[0] = to_float(&ctx->ac, src[0]);
1588 src[1] = to_float(&ctx->ac, src[1]);
1589 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1590 break;
1591 case nir_op_frcp:
1592 src[0] = to_float(&ctx->ac, src[0]);
1593 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1594 break;
1595 case nir_op_iand:
1596 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1597 break;
1598 case nir_op_ior:
1599 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1600 break;
1601 case nir_op_ixor:
1602 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1603 break;
1604 case nir_op_ishl:
1605 result = LLVMBuildShl(ctx->builder, src[0],
1606 LLVMBuildZExt(ctx->builder, src[1],
1607 LLVMTypeOf(src[0]), ""),
1608 "");
1609 break;
1610 case nir_op_ishr:
1611 result = LLVMBuildAShr(ctx->builder, src[0],
1612 LLVMBuildZExt(ctx->builder, src[1],
1613 LLVMTypeOf(src[0]), ""),
1614 "");
1615 break;
1616 case nir_op_ushr:
1617 result = LLVMBuildLShr(ctx->builder, src[0],
1618 LLVMBuildZExt(ctx->builder, src[1],
1619 LLVMTypeOf(src[0]), ""),
1620 "");
1621 break;
1622 case nir_op_ilt:
1623 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1624 break;
1625 case nir_op_ine:
1626 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1627 break;
1628 case nir_op_ieq:
1629 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1630 break;
1631 case nir_op_ige:
1632 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1633 break;
1634 case nir_op_ult:
1635 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1636 break;
1637 case nir_op_uge:
1638 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1639 break;
1640 case nir_op_feq:
1641 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1642 break;
1643 case nir_op_fne:
1644 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1645 break;
1646 case nir_op_flt:
1647 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1648 break;
1649 case nir_op_fge:
1650 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1651 break;
1652 case nir_op_fabs:
1653 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1654 to_float_type(&ctx->ac, def_type), src[0]);
1655 break;
1656 case nir_op_iabs:
1657 result = emit_iabs(&ctx->ac, src[0]);
1658 break;
1659 case nir_op_imax:
1660 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1661 break;
1662 case nir_op_imin:
1663 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1664 break;
1665 case nir_op_umax:
1666 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1667 break;
1668 case nir_op_umin:
1669 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1670 break;
1671 case nir_op_isign:
1672 result = emit_isign(&ctx->ac, src[0]);
1673 break;
1674 case nir_op_fsign:
1675 src[0] = to_float(&ctx->ac, src[0]);
1676 result = emit_fsign(&ctx->ac, src[0]);
1677 break;
1678 case nir_op_ffloor:
1679 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1680 to_float_type(&ctx->ac, def_type), src[0]);
1681 break;
1682 case nir_op_ftrunc:
1683 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1684 to_float_type(&ctx->ac, def_type), src[0]);
1685 break;
1686 case nir_op_fceil:
1687 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1688 to_float_type(&ctx->ac, def_type), src[0]);
1689 break;
1690 case nir_op_fround_even:
1691 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1692 to_float_type(&ctx->ac, def_type),src[0]);
1693 break;
1694 case nir_op_ffract:
1695 result = emit_ffract(&ctx->ac, src[0]);
1696 break;
1697 case nir_op_fsin:
1698 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1699 to_float_type(&ctx->ac, def_type), src[0]);
1700 break;
1701 case nir_op_fcos:
1702 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1703 to_float_type(&ctx->ac, def_type), src[0]);
1704 break;
1705 case nir_op_fsqrt:
1706 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1707 to_float_type(&ctx->ac, def_type), src[0]);
1708 break;
1709 case nir_op_fexp2:
1710 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1711 to_float_type(&ctx->ac, def_type), src[0]);
1712 break;
1713 case nir_op_flog2:
1714 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1715 to_float_type(&ctx->ac, def_type), src[0]);
1716 break;
1717 case nir_op_frsq:
1718 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1719 to_float_type(&ctx->ac, def_type), src[0]);
1720 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1721 break;
1722 case nir_op_fpow:
1723 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1724 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1725 break;
1726 case nir_op_fmax:
1727 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1728 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1729 if (instr->dest.dest.ssa.bit_size == 32)
1730 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1731 to_float_type(&ctx->ac, def_type),
1732 result);
1733 break;
1734 case nir_op_fmin:
1735 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1736 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1737 if (instr->dest.dest.ssa.bit_size == 32)
1738 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1739 to_float_type(&ctx->ac, def_type),
1740 result);
1741 break;
1742 case nir_op_ffma:
1743 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1744 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1745 break;
1746 case nir_op_ibitfield_extract:
1747 result = emit_bitfield_extract(&ctx->ac, true, src);
1748 break;
1749 case nir_op_ubitfield_extract:
1750 result = emit_bitfield_extract(&ctx->ac, false, src);
1751 break;
1752 case nir_op_bitfield_insert:
1753 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1754 break;
1755 case nir_op_bitfield_reverse:
1756 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1757 break;
1758 case nir_op_bit_count:
1759 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1760 break;
1761 case nir_op_vec2:
1762 case nir_op_vec3:
1763 case nir_op_vec4:
1764 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1765 src[i] = to_integer(&ctx->ac, src[i]);
1766 result = ac_build_gather_values(&ctx->ac, src, num_components);
1767 break;
1768 case nir_op_f2i32:
1769 case nir_op_f2i64:
1770 src[0] = to_float(&ctx->ac, src[0]);
1771 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1772 break;
1773 case nir_op_f2u32:
1774 case nir_op_f2u64:
1775 src[0] = to_float(&ctx->ac, src[0]);
1776 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1777 break;
1778 case nir_op_i2f32:
1779 case nir_op_i2f64:
1780 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1781 break;
1782 case nir_op_u2f32:
1783 case nir_op_u2f64:
1784 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1785 break;
1786 case nir_op_f2f64:
1787 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1788 break;
1789 case nir_op_f2f32:
1790 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1791 break;
1792 case nir_op_u2u32:
1793 case nir_op_u2u64:
1794 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1795 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1796 else
1797 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1798 break;
1799 case nir_op_i2i32:
1800 case nir_op_i2i64:
1801 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1802 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1803 else
1804 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1805 break;
1806 case nir_op_bcsel:
1807 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1808 break;
1809 case nir_op_find_lsb:
1810 result = emit_find_lsb(&ctx->ac, src[0]);
1811 break;
1812 case nir_op_ufind_msb:
1813 result = emit_ufind_msb(&ctx->ac, src[0]);
1814 break;
1815 case nir_op_ifind_msb:
1816 result = emit_ifind_msb(&ctx->ac, src[0]);
1817 break;
1818 case nir_op_uadd_carry:
1819 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1820 break;
1821 case nir_op_usub_borrow:
1822 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1823 break;
1824 case nir_op_b2f:
1825 result = emit_b2f(&ctx->ac, src[0]);
1826 break;
1827 case nir_op_f2b:
1828 result = emit_f2b(&ctx->ac, src[0]);
1829 break;
1830 case nir_op_b2i:
1831 result = emit_b2i(&ctx->ac, src[0]);
1832 break;
1833 case nir_op_i2b:
1834 result = emit_i2b(&ctx->ac, src[0]);
1835 break;
1836 case nir_op_fquantize2f16:
1837 result = emit_f2f16(ctx, src[0]);
1838 break;
1839 case nir_op_umul_high:
1840 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1841 break;
1842 case nir_op_imul_high:
1843 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1844 break;
1845 case nir_op_pack_half_2x16:
1846 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1847 break;
1848 case nir_op_unpack_half_2x16:
1849 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1850 break;
1851 case nir_op_fddx:
1852 case nir_op_fddy:
1853 case nir_op_fddx_fine:
1854 case nir_op_fddy_fine:
1855 case nir_op_fddx_coarse:
1856 case nir_op_fddy_coarse:
1857 result = emit_ddxy(ctx, instr->op, src[0]);
1858 break;
1859
1860 case nir_op_unpack_64_2x32_split_x: {
1861 assert(instr->src[0].src.ssa->num_components == 1);
1862 LLVMValueRef tmp = LLVMBuildBitCast(ctx->builder, src[0],
1863 LLVMVectorType(ctx->i32, 2),
1864 "");
1865 result = LLVMBuildExtractElement(ctx->builder, tmp,
1866 ctx->i32zero, "");
1867 break;
1868 }
1869
1870 case nir_op_unpack_64_2x32_split_y: {
1871 assert(instr->src[0].src.ssa->num_components == 1);
1872 LLVMValueRef tmp = LLVMBuildBitCast(ctx->builder, src[0],
1873 LLVMVectorType(ctx->i32, 2),
1874 "");
1875 result = LLVMBuildExtractElement(ctx->builder, tmp,
1876 ctx->i32one, "");
1877 break;
1878 }
1879
1880 case nir_op_pack_64_2x32_split: {
1881 LLVMValueRef tmp = LLVMGetUndef(LLVMVectorType(ctx->i32, 2));
1882 tmp = LLVMBuildInsertElement(ctx->builder, tmp,
1883 src[0], ctx->i32zero, "");
1884 tmp = LLVMBuildInsertElement(ctx->builder, tmp,
1885 src[1], ctx->i32one, "");
1886 result = LLVMBuildBitCast(ctx->builder, tmp, ctx->i64, "");
1887 break;
1888 }
1889
1890 default:
1891 fprintf(stderr, "Unknown NIR alu instr: ");
1892 nir_print_instr(&instr->instr, stderr);
1893 fprintf(stderr, "\n");
1894 abort();
1895 }
1896
1897 if (result) {
1898 assert(instr->dest.dest.is_ssa);
1899 result = to_integer(&ctx->ac, result);
1900 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1901 result);
1902 }
1903 }
1904
1905 static void visit_load_const(struct nir_to_llvm_context *ctx,
1906 const nir_load_const_instr *instr)
1907 {
1908 LLVMValueRef values[4], value = NULL;
1909 LLVMTypeRef element_type =
1910 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1911
1912 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1913 switch (instr->def.bit_size) {
1914 case 32:
1915 values[i] = LLVMConstInt(element_type,
1916 instr->value.u32[i], false);
1917 break;
1918 case 64:
1919 values[i] = LLVMConstInt(element_type,
1920 instr->value.u64[i], false);
1921 break;
1922 default:
1923 fprintf(stderr,
1924 "unsupported nir load_const bit_size: %d\n",
1925 instr->def.bit_size);
1926 abort();
1927 }
1928 }
1929 if (instr->def.num_components > 1) {
1930 value = LLVMConstVector(values, instr->def.num_components);
1931 } else
1932 value = values[0];
1933
1934 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1935 }
1936
1937 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1938 LLVMTypeRef type)
1939 {
1940 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1941 return LLVMBuildBitCast(ctx->builder, ptr,
1942 LLVMPointerType(type, addr_space), "");
1943 }
1944
1945 static LLVMValueRef
1946 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1947 {
1948 LLVMValueRef size =
1949 LLVMBuildExtractElement(ctx->builder, descriptor,
1950 LLVMConstInt(ctx->i32, 2, false), "");
1951
1952 /* VI only */
1953 if (ctx->options->chip_class >= VI && in_elements) {
1954 /* On VI, the descriptor contains the size in bytes,
1955 * but TXQ must return the size in elements.
1956 * The stride is always non-zero for resources using TXQ.
1957 */
1958 LLVMValueRef stride =
1959 LLVMBuildExtractElement(ctx->builder, descriptor,
1960 LLVMConstInt(ctx->i32, 1, false), "");
1961 stride = LLVMBuildLShr(ctx->builder, stride,
1962 LLVMConstInt(ctx->i32, 16, false), "");
1963 stride = LLVMBuildAnd(ctx->builder, stride,
1964 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1965
1966 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1967 }
1968 return size;
1969 }
1970
1971 /**
1972 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1973 * intrinsic names).
1974 */
1975 static void build_int_type_name(
1976 LLVMTypeRef type,
1977 char *buf, unsigned bufsize)
1978 {
1979 assert(bufsize >= 6);
1980
1981 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1982 snprintf(buf, bufsize, "v%ui32",
1983 LLVMGetVectorSize(type));
1984 else
1985 strcpy(buf, "i32");
1986 }
1987
1988 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1989 struct ac_image_args *args,
1990 const nir_tex_instr *instr)
1991 {
1992 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1993 LLVMValueRef coord = args->addr;
1994 LLVMValueRef half_texel[2];
1995 LLVMValueRef compare_cube_wa;
1996 LLVMValueRef result;
1997 int c;
1998 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1999
2000 //TODO Rect
2001 {
2002 struct ac_image_args txq_args = { 0 };
2003
2004 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2005 txq_args.opcode = ac_image_get_resinfo;
2006 txq_args.dmask = 0xf;
2007 txq_args.addr = ctx->i32zero;
2008 txq_args.resource = args->resource;
2009 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
2010
2011 for (c = 0; c < 2; c++) {
2012 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2013 LLVMConstInt(ctx->i32, c, false), "");
2014 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2015 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
2016 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2017 LLVMConstReal(ctx->f32, -0.5), "");
2018 }
2019 }
2020
2021 LLVMValueRef orig_coords = args->addr;
2022
2023 for (c = 0; c < 2; c++) {
2024 LLVMValueRef tmp;
2025 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2026 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2027 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2028 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2029 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2030 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2031 }
2032
2033
2034 /*
2035 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2036 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2037 * workaround by sampling using a scaled type and converting.
2038 * This is taken from amdgpu-pro shaders.
2039 */
2040 /* NOTE this produces some ugly code compared to amdgpu-pro,
2041 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2042 * and then reads them back. -pro generates two selects,
2043 * one s_cmp for the descriptor rewriting
2044 * one v_cmp for the coordinate and result changes.
2045 */
2046 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2047 LLVMValueRef tmp, tmp2;
2048
2049 /* workaround 8/8/8/8 uint/sint cube gather bug */
2050 /* first detect it then change to a scaled read and f2i */
2051 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
2052 tmp2 = tmp;
2053
2054 /* extract the DATA_FORMAT */
2055 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
2056 LLVMConstInt(ctx->i32, 6, false), false);
2057
2058 /* is the DATA_FORMAT == 8_8_8_8 */
2059 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2060
2061 if (stype == GLSL_TYPE_UINT)
2062 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2063 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2064 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2065 else
2066 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2067 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2068 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2069
2070 /* replace the NUM FORMAT in the descriptor */
2071 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2072 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2073
2074 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2075
2076 /* don't modify the coordinates for this case */
2077 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2078 }
2079 args->addr = coord;
2080 result = ac_build_image_opcode(&ctx->ac, args);
2081
2082 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2083 LLVMValueRef tmp, tmp2;
2084
2085 /* if the cube workaround is in place, f2i the result. */
2086 for (c = 0; c < 4; c++) {
2087 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2088 if (stype == GLSL_TYPE_UINT)
2089 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2090 else
2091 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2092 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2093 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2094 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2095 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2096 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2097 }
2098 }
2099 return result;
2100 }
2101
2102 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2103 const nir_tex_instr *instr,
2104 bool lod_is_zero,
2105 struct ac_image_args *args)
2106 {
2107 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2108 return ac_build_buffer_load_format(&ctx->ac,
2109 args->resource,
2110 args->addr,
2111 LLVMConstInt(ctx->i32, 0, false),
2112 true);
2113 }
2114
2115 args->opcode = ac_image_sample;
2116 args->compare = instr->is_shadow;
2117
2118 switch (instr->op) {
2119 case nir_texop_txf:
2120 case nir_texop_txf_ms:
2121 case nir_texop_samples_identical:
2122 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2123 args->compare = false;
2124 args->offset = false;
2125 break;
2126 case nir_texop_txb:
2127 args->bias = true;
2128 break;
2129 case nir_texop_txl:
2130 if (lod_is_zero)
2131 args->level_zero = true;
2132 else
2133 args->lod = true;
2134 break;
2135 case nir_texop_txs:
2136 case nir_texop_query_levels:
2137 args->opcode = ac_image_get_resinfo;
2138 break;
2139 case nir_texop_tex:
2140 if (ctx->stage != MESA_SHADER_FRAGMENT)
2141 args->level_zero = true;
2142 break;
2143 case nir_texop_txd:
2144 args->deriv = true;
2145 break;
2146 case nir_texop_tg4:
2147 args->opcode = ac_image_gather4;
2148 args->level_zero = true;
2149 break;
2150 case nir_texop_lod:
2151 args->opcode = ac_image_get_lod;
2152 args->compare = false;
2153 args->offset = false;
2154 break;
2155 default:
2156 break;
2157 }
2158
2159 if (instr->op == nir_texop_tg4) {
2160 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2161 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2162 return radv_lower_gather4_integer(ctx, args, instr);
2163 }
2164 }
2165 return ac_build_image_opcode(&ctx->ac, args);
2166 }
2167
2168 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2169 nir_intrinsic_instr *instr)
2170 {
2171 LLVMValueRef index = get_src(ctx, instr->src[0]);
2172 unsigned desc_set = nir_intrinsic_desc_set(instr);
2173 unsigned binding = nir_intrinsic_binding(instr);
2174 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2175 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2176 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2177 unsigned base_offset = layout->binding[binding].offset;
2178 LLVMValueRef offset, stride;
2179
2180 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2181 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2182 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2183 layout->binding[binding].dynamic_offset_offset;
2184 desc_ptr = ctx->push_constants;
2185 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2186 stride = LLVMConstInt(ctx->i32, 16, false);
2187 } else
2188 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2189
2190 offset = LLVMConstInt(ctx->i32, base_offset, false);
2191 index = LLVMBuildMul(ctx->builder, index, stride, "");
2192 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2193
2194 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2195 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2196 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2197
2198 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2199 }
2200
2201 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2202 nir_intrinsic_instr *instr)
2203 {
2204 LLVMValueRef ptr, addr;
2205
2206 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2207 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2208
2209 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2210 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2211
2212 return LLVMBuildLoad(ctx->builder, ptr, "");
2213 }
2214
2215 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2216 const nir_intrinsic_instr *instr)
2217 {
2218 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2219
2220 return get_buffer_size(ctx, desc, false);
2221 }
2222 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2223 nir_intrinsic_instr *instr)
2224 {
2225 const char *store_name;
2226 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2227 LLVMTypeRef data_type = ctx->f32;
2228 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2229 int components_32bit = elem_size_mult * instr->num_components;
2230 unsigned writemask = nir_intrinsic_write_mask(instr);
2231 LLVMValueRef base_data, base_offset;
2232 LLVMValueRef params[6];
2233
2234 if (ctx->stage == MESA_SHADER_FRAGMENT)
2235 ctx->shader_info->fs.writes_memory = true;
2236
2237 params[1] = get_src(ctx, instr->src[1]);
2238 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2239 params[4] = ctx->i1false; /* glc */
2240 params[5] = ctx->i1false; /* slc */
2241
2242 if (components_32bit > 1)
2243 data_type = LLVMVectorType(ctx->f32, components_32bit);
2244
2245 base_data = to_float(&ctx->ac, src_data);
2246 base_data = trim_vector(ctx, base_data, instr->num_components);
2247 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2248 data_type, "");
2249 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2250 while (writemask) {
2251 int start, count;
2252 LLVMValueRef data;
2253 LLVMValueRef offset;
2254 LLVMValueRef tmp;
2255 u_bit_scan_consecutive_range(&writemask, &start, &count);
2256
2257 /* Due to an LLVM limitation, split 3-element writes
2258 * into a 2-element and a 1-element write. */
2259 if (count == 3) {
2260 writemask |= 1 << (start + 2);
2261 count = 2;
2262 }
2263
2264 start *= elem_size_mult;
2265 count *= elem_size_mult;
2266
2267 if (count > 4) {
2268 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2269 count = 4;
2270 }
2271
2272 if (count == 4) {
2273 store_name = "llvm.amdgcn.buffer.store.v4f32";
2274 data = base_data;
2275 } else if (count == 2) {
2276 tmp = LLVMBuildExtractElement(ctx->builder,
2277 base_data, LLVMConstInt(ctx->i32, start, false), "");
2278 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2279 ctx->i32zero, "");
2280
2281 tmp = LLVMBuildExtractElement(ctx->builder,
2282 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2283 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2284 ctx->i32one, "");
2285 store_name = "llvm.amdgcn.buffer.store.v2f32";
2286
2287 } else {
2288 assert(count == 1);
2289 if (get_llvm_num_components(base_data) > 1)
2290 data = LLVMBuildExtractElement(ctx->builder, base_data,
2291 LLVMConstInt(ctx->i32, start, false), "");
2292 else
2293 data = base_data;
2294 store_name = "llvm.amdgcn.buffer.store.f32";
2295 }
2296
2297 offset = base_offset;
2298 if (start != 0) {
2299 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2300 }
2301 params[0] = data;
2302 params[3] = offset;
2303 ac_build_intrinsic(&ctx->ac, store_name,
2304 ctx->voidt, params, 6, 0);
2305 }
2306 }
2307
2308 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2309 const nir_intrinsic_instr *instr)
2310 {
2311 const char *name;
2312 LLVMValueRef params[6];
2313 int arg_count = 0;
2314 if (ctx->stage == MESA_SHADER_FRAGMENT)
2315 ctx->shader_info->fs.writes_memory = true;
2316
2317 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2318 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2319 }
2320 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2321 params[arg_count++] = get_src(ctx, instr->src[0]);
2322 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2323 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2324 params[arg_count++] = ctx->i1false; /* slc */
2325
2326 switch (instr->intrinsic) {
2327 case nir_intrinsic_ssbo_atomic_add:
2328 name = "llvm.amdgcn.buffer.atomic.add";
2329 break;
2330 case nir_intrinsic_ssbo_atomic_imin:
2331 name = "llvm.amdgcn.buffer.atomic.smin";
2332 break;
2333 case nir_intrinsic_ssbo_atomic_umin:
2334 name = "llvm.amdgcn.buffer.atomic.umin";
2335 break;
2336 case nir_intrinsic_ssbo_atomic_imax:
2337 name = "llvm.amdgcn.buffer.atomic.smax";
2338 break;
2339 case nir_intrinsic_ssbo_atomic_umax:
2340 name = "llvm.amdgcn.buffer.atomic.umax";
2341 break;
2342 case nir_intrinsic_ssbo_atomic_and:
2343 name = "llvm.amdgcn.buffer.atomic.and";
2344 break;
2345 case nir_intrinsic_ssbo_atomic_or:
2346 name = "llvm.amdgcn.buffer.atomic.or";
2347 break;
2348 case nir_intrinsic_ssbo_atomic_xor:
2349 name = "llvm.amdgcn.buffer.atomic.xor";
2350 break;
2351 case nir_intrinsic_ssbo_atomic_exchange:
2352 name = "llvm.amdgcn.buffer.atomic.swap";
2353 break;
2354 case nir_intrinsic_ssbo_atomic_comp_swap:
2355 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2356 break;
2357 default:
2358 abort();
2359 }
2360
2361 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2362 }
2363
2364 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2365 const nir_intrinsic_instr *instr)
2366 {
2367 LLVMValueRef results[2];
2368 int load_components;
2369 int num_components = instr->num_components;
2370 if (instr->dest.ssa.bit_size == 64)
2371 num_components *= 2;
2372
2373 for (int i = 0; i < num_components; i += load_components) {
2374 load_components = MIN2(num_components - i, 4);
2375 const char *load_name;
2376 LLVMTypeRef data_type = ctx->f32;
2377 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2378 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2379
2380 if (load_components == 3)
2381 data_type = LLVMVectorType(ctx->f32, 4);
2382 else if (load_components > 1)
2383 data_type = LLVMVectorType(ctx->f32, load_components);
2384
2385 if (load_components >= 3)
2386 load_name = "llvm.amdgcn.buffer.load.v4f32";
2387 else if (load_components == 2)
2388 load_name = "llvm.amdgcn.buffer.load.v2f32";
2389 else if (load_components == 1)
2390 load_name = "llvm.amdgcn.buffer.load.f32";
2391 else
2392 unreachable("unhandled number of components");
2393
2394 LLVMValueRef params[] = {
2395 get_src(ctx, instr->src[0]),
2396 LLVMConstInt(ctx->i32, 0, false),
2397 offset,
2398 ctx->i1false,
2399 ctx->i1false,
2400 };
2401
2402 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2403
2404 }
2405
2406 LLVMValueRef ret = results[0];
2407 if (num_components > 4 || num_components == 3) {
2408 LLVMValueRef masks[] = {
2409 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2410 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2411 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2412 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2413 };
2414
2415 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2416 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2417 results[num_components > 4 ? 1 : 0], swizzle, "");
2418 }
2419
2420 return LLVMBuildBitCast(ctx->builder, ret,
2421 get_def_type(ctx, &instr->dest.ssa), "");
2422 }
2423
2424 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2425 const nir_intrinsic_instr *instr)
2426 {
2427 LLVMValueRef results[8], ret;
2428 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2429 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2430 int num_components = instr->num_components;
2431
2432 if (instr->dest.ssa.bit_size == 64)
2433 num_components *= 2;
2434
2435 for (unsigned i = 0; i < num_components; ++i) {
2436 LLVMValueRef params[] = {
2437 rsrc,
2438 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2439 offset, "")
2440 };
2441 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const.v4i32", ctx->f32,
2442 params, 2,
2443 AC_FUNC_ATTR_READNONE |
2444 AC_FUNC_ATTR_LEGACY);
2445 }
2446
2447
2448 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2449 return LLVMBuildBitCast(ctx->builder, ret,
2450 get_def_type(ctx, &instr->dest.ssa), "");
2451 }
2452
2453 static void
2454 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2455 bool vs_in, unsigned *vertex_index_out,
2456 LLVMValueRef *vertex_index_ref,
2457 unsigned *const_out, LLVMValueRef *indir_out)
2458 {
2459 unsigned const_offset = 0;
2460 nir_deref *tail = &deref->deref;
2461 LLVMValueRef offset = NULL;
2462
2463 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2464 tail = tail->child;
2465 nir_deref_array *deref_array = nir_deref_as_array(tail);
2466 if (vertex_index_out)
2467 *vertex_index_out = deref_array->base_offset;
2468
2469 if (vertex_index_ref) {
2470 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2471 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2472 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2473 }
2474 *vertex_index_ref = vtx;
2475 }
2476 }
2477
2478 if (deref->var->data.compact) {
2479 assert(tail->child->deref_type == nir_deref_type_array);
2480 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2481 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2482 /* We always lower indirect dereferences for "compact" array vars. */
2483 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2484
2485 const_offset = deref_array->base_offset;
2486 goto out;
2487 }
2488
2489 while (tail->child != NULL) {
2490 const struct glsl_type *parent_type = tail->type;
2491 tail = tail->child;
2492
2493 if (tail->deref_type == nir_deref_type_array) {
2494 nir_deref_array *deref_array = nir_deref_as_array(tail);
2495 LLVMValueRef index, stride, local_offset;
2496 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2497
2498 const_offset += size * deref_array->base_offset;
2499 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2500 continue;
2501
2502 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2503 index = get_src(ctx, deref_array->indirect);
2504 stride = LLVMConstInt(ctx->i32, size, 0);
2505 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2506
2507 if (offset)
2508 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2509 else
2510 offset = local_offset;
2511 } else if (tail->deref_type == nir_deref_type_struct) {
2512 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2513
2514 for (unsigned i = 0; i < deref_struct->index; i++) {
2515 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2516 const_offset += glsl_count_attribute_slots(ft, vs_in);
2517 }
2518 } else
2519 unreachable("unsupported deref type");
2520
2521 }
2522 out:
2523 if (const_offset && offset)
2524 offset = LLVMBuildAdd(ctx->builder, offset,
2525 LLVMConstInt(ctx->i32, const_offset, 0),
2526 "");
2527
2528 *const_out = const_offset;
2529 *indir_out = offset;
2530 }
2531
2532 static LLVMValueRef
2533 lds_load(struct nir_to_llvm_context *ctx,
2534 LLVMValueRef dw_addr)
2535 {
2536 LLVMValueRef value;
2537 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2538 return value;
2539 }
2540
2541 static void
2542 lds_store(struct nir_to_llvm_context *ctx,
2543 LLVMValueRef dw_addr, LLVMValueRef value)
2544 {
2545 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2546 ac_build_indexed_store(&ctx->ac, ctx->lds,
2547 dw_addr, value);
2548 }
2549
2550 /* The offchip buffer layout for TCS->TES is
2551 *
2552 * - attribute 0 of patch 0 vertex 0
2553 * - attribute 0 of patch 0 vertex 1
2554 * - attribute 0 of patch 0 vertex 2
2555 * ...
2556 * - attribute 0 of patch 1 vertex 0
2557 * - attribute 0 of patch 1 vertex 1
2558 * ...
2559 * - attribute 1 of patch 0 vertex 0
2560 * - attribute 1 of patch 0 vertex 1
2561 * ...
2562 * - per patch attribute 0 of patch 0
2563 * - per patch attribute 0 of patch 1
2564 * ...
2565 *
2566 * Note that every attribute has 4 components.
2567 */
2568 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2569 LLVMValueRef vertex_index,
2570 LLVMValueRef param_index)
2571 {
2572 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2573 LLVMValueRef param_stride, constant16;
2574 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2575
2576 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2577 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2578 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2579 num_patches, "");
2580
2581 constant16 = LLVMConstInt(ctx->i32, 16, false);
2582 if (vertex_index) {
2583 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2584 vertices_per_patch, "");
2585
2586 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2587 vertex_index, "");
2588
2589 param_stride = total_vertices;
2590 } else {
2591 base_addr = rel_patch_id;
2592 param_stride = num_patches;
2593 }
2594
2595 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2596 LLVMBuildMul(ctx->builder, param_index,
2597 param_stride, ""), "");
2598
2599 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2600
2601 if (!vertex_index) {
2602 LLVMValueRef patch_data_offset =
2603 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2604
2605 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2606 patch_data_offset, "");
2607 }
2608 return base_addr;
2609 }
2610
2611 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2612 unsigned param,
2613 unsigned const_index,
2614 bool is_compact,
2615 LLVMValueRef vertex_index,
2616 LLVMValueRef indir_index)
2617 {
2618 LLVMValueRef param_index;
2619
2620 if (indir_index)
2621 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2622 indir_index, "");
2623 else {
2624 if (const_index && !is_compact)
2625 param += const_index;
2626 param_index = LLVMConstInt(ctx->i32, param, false);
2627 }
2628 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2629 }
2630
2631 static void
2632 mark_tess_output(struct nir_to_llvm_context *ctx,
2633 bool is_patch, uint32_t param)
2634
2635 {
2636 if (is_patch) {
2637 ctx->tess_patch_outputs_written |= (1ull << param);
2638 } else
2639 ctx->tess_outputs_written |= (1ull << param);
2640 }
2641
2642 static LLVMValueRef
2643 get_dw_address(struct nir_to_llvm_context *ctx,
2644 LLVMValueRef dw_addr,
2645 unsigned param,
2646 unsigned const_index,
2647 bool compact_const_index,
2648 LLVMValueRef vertex_index,
2649 LLVMValueRef stride,
2650 LLVMValueRef indir_index)
2651
2652 {
2653
2654 if (vertex_index) {
2655 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2656 LLVMBuildMul(ctx->builder,
2657 vertex_index,
2658 stride, ""), "");
2659 }
2660
2661 if (indir_index)
2662 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2663 LLVMBuildMul(ctx->builder, indir_index,
2664 LLVMConstInt(ctx->i32, 4, false), ""), "");
2665 else if (const_index && !compact_const_index)
2666 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2667 LLVMConstInt(ctx->i32, const_index, false), "");
2668
2669 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2670 LLVMConstInt(ctx->i32, param * 4, false), "");
2671
2672 if (const_index && compact_const_index)
2673 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2674 LLVMConstInt(ctx->i32, const_index, false), "");
2675 return dw_addr;
2676 }
2677
2678 static LLVMValueRef
2679 load_tcs_input(struct nir_to_llvm_context *ctx,
2680 nir_intrinsic_instr *instr)
2681 {
2682 LLVMValueRef dw_addr, stride;
2683 unsigned const_index;
2684 LLVMValueRef vertex_index;
2685 LLVMValueRef indir_index;
2686 unsigned param;
2687 LLVMValueRef value[4], result;
2688 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2689 const bool is_compact = instr->variables[0]->var->data.compact;
2690 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2691 radv_get_deref_offset(ctx, instr->variables[0],
2692 false, NULL, per_vertex ? &vertex_index : NULL,
2693 &const_index, &indir_index);
2694
2695 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2696 dw_addr = get_tcs_in_current_patch_offset(ctx);
2697 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2698 indir_index);
2699
2700 for (unsigned i = 0; i < instr->num_components; i++) {
2701 value[i] = lds_load(ctx, dw_addr);
2702 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2703 ctx->i32one, "");
2704 }
2705 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2706 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2707 return result;
2708 }
2709
2710 static LLVMValueRef
2711 load_tcs_output(struct nir_to_llvm_context *ctx,
2712 nir_intrinsic_instr *instr)
2713 {
2714 LLVMValueRef dw_addr, stride;
2715 LLVMValueRef value[4], result;
2716 LLVMValueRef vertex_index = NULL;
2717 LLVMValueRef indir_index = NULL;
2718 unsigned const_index = 0;
2719 unsigned param;
2720 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2721 const bool is_compact = instr->variables[0]->var->data.compact;
2722 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2723 radv_get_deref_offset(ctx, instr->variables[0],
2724 false, NULL, per_vertex ? &vertex_index : NULL,
2725 &const_index, &indir_index);
2726
2727 if (!instr->variables[0]->var->data.patch) {
2728 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2729 dw_addr = get_tcs_out_current_patch_offset(ctx);
2730 } else {
2731 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2732 }
2733
2734 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2735 indir_index);
2736
2737 for (unsigned i = 0; i < instr->num_components; i++) {
2738 value[i] = lds_load(ctx, dw_addr);
2739 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2740 ctx->i32one, "");
2741 }
2742 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2743 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2744 return result;
2745 }
2746
2747 static void
2748 store_tcs_output(struct nir_to_llvm_context *ctx,
2749 nir_intrinsic_instr *instr,
2750 LLVMValueRef src,
2751 unsigned writemask)
2752 {
2753 LLVMValueRef stride, dw_addr;
2754 LLVMValueRef buf_addr = NULL;
2755 LLVMValueRef vertex_index = NULL;
2756 LLVMValueRef indir_index = NULL;
2757 unsigned const_index = 0;
2758 unsigned param;
2759 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2760 const bool is_compact = instr->variables[0]->var->data.compact;
2761
2762 radv_get_deref_offset(ctx, instr->variables[0],
2763 false, NULL, per_vertex ? &vertex_index : NULL,
2764 &const_index, &indir_index);
2765
2766 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2767 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2768 is_compact && const_index > 3) {
2769 const_index -= 3;
2770 param++;
2771 }
2772
2773 if (!instr->variables[0]->var->data.patch) {
2774 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2775 dw_addr = get_tcs_out_current_patch_offset(ctx);
2776 } else {
2777 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2778 }
2779
2780 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2781
2782 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2783 indir_index);
2784 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2785 vertex_index, indir_index);
2786
2787 unsigned base = is_compact ? const_index : 0;
2788 for (unsigned chan = 0; chan < 8; chan++) {
2789 bool is_tess_factor = false;
2790 if (!(writemask & (1 << chan)))
2791 continue;
2792 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2793
2794 lds_store(ctx, dw_addr, value);
2795
2796 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2797 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2798 is_tess_factor = true;
2799
2800 if (!is_tess_factor && writemask != 0xF)
2801 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2802 buf_addr, ctx->oc_lds,
2803 4 * (base + chan), 1, 0, true, false);
2804
2805 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2806 ctx->i32one, "");
2807 }
2808
2809 if (writemask == 0xF) {
2810 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2811 buf_addr, ctx->oc_lds,
2812 (base * 4), 1, 0, true, false);
2813 }
2814 }
2815
2816 static LLVMValueRef
2817 load_tes_input(struct nir_to_llvm_context *ctx,
2818 const nir_intrinsic_instr *instr)
2819 {
2820 LLVMValueRef buf_addr;
2821 LLVMValueRef result;
2822 LLVMValueRef vertex_index = NULL;
2823 LLVMValueRef indir_index = NULL;
2824 unsigned const_index = 0;
2825 unsigned param;
2826 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2827 const bool is_compact = instr->variables[0]->var->data.compact;
2828
2829 radv_get_deref_offset(ctx, instr->variables[0],
2830 false, NULL, per_vertex ? &vertex_index : NULL,
2831 &const_index, &indir_index);
2832 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2833 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2834 is_compact && const_index > 3) {
2835 const_index -= 3;
2836 param++;
2837 }
2838 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2839 is_compact, vertex_index, indir_index);
2840
2841 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2842 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2843 result = trim_vector(ctx, result, instr->num_components);
2844 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2845 return result;
2846 }
2847
2848 static LLVMValueRef
2849 load_gs_input(struct nir_to_llvm_context *ctx,
2850 nir_intrinsic_instr *instr)
2851 {
2852 LLVMValueRef indir_index, vtx_offset;
2853 unsigned const_index;
2854 LLVMValueRef args[9];
2855 unsigned param, vtx_offset_param;
2856 LLVMValueRef value[4], result;
2857 unsigned vertex_index;
2858 radv_get_deref_offset(ctx, instr->variables[0],
2859 false, &vertex_index, NULL,
2860 &const_index, &indir_index);
2861 vtx_offset_param = vertex_index;
2862 assert(vtx_offset_param < 6);
2863 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2864 LLVMConstInt(ctx->i32, 4, false), "");
2865
2866 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2867 for (unsigned i = 0; i < instr->num_components; i++) {
2868
2869 args[0] = ctx->esgs_ring;
2870 args[1] = vtx_offset;
2871 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2872 args[3] = ctx->i32zero;
2873 args[4] = ctx->i32one; /* OFFEN */
2874 args[5] = ctx->i32zero; /* IDXEN */
2875 args[6] = ctx->i32one; /* GLC */
2876 args[7] = ctx->i32zero; /* SLC */
2877 args[8] = ctx->i32zero; /* TFE */
2878
2879 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2880 ctx->i32, args, 9,
2881 AC_FUNC_ATTR_READONLY |
2882 AC_FUNC_ATTR_LEGACY);
2883 }
2884 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2885
2886 return result;
2887 }
2888
2889 static LLVMValueRef
2890 build_gep_for_deref(struct nir_to_llvm_context *ctx,
2891 nir_deref_var *deref)
2892 {
2893 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
2894 assert(entry->data);
2895 LLVMValueRef val = entry->data;
2896 nir_deref *tail = deref->deref.child;
2897 while (tail != NULL) {
2898 LLVMValueRef offset;
2899 switch (tail->deref_type) {
2900 case nir_deref_type_array: {
2901 nir_deref_array *array = nir_deref_as_array(tail);
2902 offset = LLVMConstInt(ctx->i32, array->base_offset, 0);
2903 if (array->deref_array_type ==
2904 nir_deref_array_type_indirect) {
2905 offset = LLVMBuildAdd(ctx->builder, offset,
2906 get_src(ctx,
2907 array->indirect),
2908 "");
2909 }
2910 break;
2911 }
2912 case nir_deref_type_struct: {
2913 nir_deref_struct *deref_struct =
2914 nir_deref_as_struct(tail);
2915 offset = LLVMConstInt(ctx->i32,
2916 deref_struct->index, 0);
2917 break;
2918 }
2919 default:
2920 unreachable("bad deref type");
2921 }
2922 val = ac_build_gep0(&ctx->ac, val, offset);
2923 tail = tail->child;
2924 }
2925 return val;
2926 }
2927
2928 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2929 nir_intrinsic_instr *instr)
2930 {
2931 LLVMValueRef values[8];
2932 int idx = instr->variables[0]->var->data.driver_location;
2933 int ve = instr->dest.ssa.num_components;
2934 LLVMValueRef indir_index;
2935 LLVMValueRef ret;
2936 unsigned const_index;
2937 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2938 instr->variables[0]->var->data.mode == nir_var_shader_in;
2939 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2940 &const_index, &indir_index);
2941
2942 if (instr->dest.ssa.bit_size == 64)
2943 ve *= 2;
2944
2945 switch (instr->variables[0]->var->data.mode) {
2946 case nir_var_shader_in:
2947 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2948 return load_tcs_input(ctx, instr);
2949 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2950 return load_tes_input(ctx, instr);
2951 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2952 return load_gs_input(ctx, instr);
2953 }
2954 for (unsigned chan = 0; chan < ve; chan++) {
2955 if (indir_index) {
2956 unsigned count = glsl_count_attribute_slots(
2957 instr->variables[0]->var->type,
2958 ctx->stage == MESA_SHADER_VERTEX);
2959 count -= chan / 4;
2960 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2961 &ctx->ac, ctx->inputs + idx + chan, count,
2962 4, false);
2963
2964 values[chan] = LLVMBuildExtractElement(ctx->builder,
2965 tmp_vec,
2966 indir_index, "");
2967 } else
2968 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2969 }
2970 break;
2971 case nir_var_local:
2972 for (unsigned chan = 0; chan < ve; chan++) {
2973 if (indir_index) {
2974 unsigned count = glsl_count_attribute_slots(
2975 instr->variables[0]->var->type, false);
2976 count -= chan / 4;
2977 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2978 &ctx->ac, ctx->locals + idx + chan, count,
2979 4, true);
2980
2981 values[chan] = LLVMBuildExtractElement(ctx->builder,
2982 tmp_vec,
2983 indir_index, "");
2984 } else {
2985 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2986 }
2987 }
2988 break;
2989 case nir_var_shared: {
2990 LLVMValueRef address = build_gep_for_deref(ctx,
2991 instr->variables[0]);
2992 LLVMValueRef val = LLVMBuildLoad(ctx->builder, address, "");
2993 return LLVMBuildBitCast(ctx->builder, val,
2994 get_def_type(ctx, &instr->dest.ssa),
2995 "");
2996 }
2997 case nir_var_shader_out:
2998 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2999 return load_tcs_output(ctx, instr);
3000 for (unsigned chan = 0; chan < ve; chan++) {
3001 if (indir_index) {
3002 unsigned count = glsl_count_attribute_slots(
3003 instr->variables[0]->var->type, false);
3004 count -= chan / 4;
3005 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3006 &ctx->ac, ctx->outputs + idx + chan, count,
3007 4, true);
3008
3009 values[chan] = LLVMBuildExtractElement(ctx->builder,
3010 tmp_vec,
3011 indir_index, "");
3012 } else {
3013 values[chan] = LLVMBuildLoad(ctx->builder,
3014 ctx->outputs[idx + chan + const_index * 4],
3015 "");
3016 }
3017 }
3018 break;
3019 default:
3020 unreachable("unhandle variable mode");
3021 }
3022 ret = ac_build_gather_values(&ctx->ac, values, ve);
3023 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3024 }
3025
3026 static void
3027 visit_store_var(struct nir_to_llvm_context *ctx,
3028 nir_intrinsic_instr *instr)
3029 {
3030 LLVMValueRef temp_ptr, value;
3031 int idx = instr->variables[0]->var->data.driver_location;
3032 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3033 int writemask = instr->const_index[0];
3034 LLVMValueRef indir_index;
3035 unsigned const_index;
3036 radv_get_deref_offset(ctx, instr->variables[0], false,
3037 NULL, NULL, &const_index, &indir_index);
3038
3039 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3040 int old_writemask = writemask;
3041
3042 src = LLVMBuildBitCast(ctx->builder, src,
3043 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
3044 "");
3045
3046 writemask = 0;
3047 for (unsigned chan = 0; chan < 4; chan++) {
3048 if (old_writemask & (1 << chan))
3049 writemask |= 3u << (2 * chan);
3050 }
3051 }
3052
3053 switch (instr->variables[0]->var->data.mode) {
3054 case nir_var_shader_out:
3055
3056 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3057 store_tcs_output(ctx, instr, src, writemask);
3058 return;
3059 }
3060
3061 for (unsigned chan = 0; chan < 8; chan++) {
3062 int stride = 4;
3063 if (!(writemask & (1 << chan)))
3064 continue;
3065
3066 value = llvm_extract_elem(ctx, src, chan);
3067
3068 if (instr->variables[0]->var->data.compact)
3069 stride = 1;
3070 if (indir_index) {
3071 unsigned count = glsl_count_attribute_slots(
3072 instr->variables[0]->var->type, false);
3073 count -= chan / 4;
3074 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3075 &ctx->ac, ctx->outputs + idx + chan, count,
3076 stride, true);
3077
3078 if (get_llvm_num_components(tmp_vec) > 1) {
3079 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3080 value, indir_index, "");
3081 } else
3082 tmp_vec = value;
3083 build_store_values_extended(ctx, ctx->outputs + idx + chan,
3084 count, stride, tmp_vec);
3085
3086 } else {
3087 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3088
3089 LLVMBuildStore(ctx->builder, value, temp_ptr);
3090 }
3091 }
3092 break;
3093 case nir_var_local:
3094 for (unsigned chan = 0; chan < 8; chan++) {
3095 if (!(writemask & (1 << chan)))
3096 continue;
3097
3098 value = llvm_extract_elem(ctx, src, chan);
3099 if (indir_index) {
3100 unsigned count = glsl_count_attribute_slots(
3101 instr->variables[0]->var->type, false);
3102 count -= chan / 4;
3103 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3104 &ctx->ac, ctx->locals + idx + chan, count,
3105 4, true);
3106
3107 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3108 value, indir_index, "");
3109 build_store_values_extended(ctx, ctx->locals + idx + chan,
3110 count, 4, tmp_vec);
3111 } else {
3112 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3113
3114 LLVMBuildStore(ctx->builder, value, temp_ptr);
3115 }
3116 }
3117 break;
3118 case nir_var_shared: {
3119 int writemask = instr->const_index[0];
3120 LLVMValueRef address = build_gep_for_deref(ctx,
3121 instr->variables[0]);
3122 LLVMValueRef val = get_src(ctx, instr->src[0]);
3123 unsigned components =
3124 glsl_get_vector_elements(
3125 nir_deref_tail(&instr->variables[0]->deref)->type);
3126 if (writemask == (1 << components) - 1) {
3127 val = LLVMBuildBitCast(
3128 ctx->builder, val,
3129 LLVMGetElementType(LLVMTypeOf(address)), "");
3130 LLVMBuildStore(ctx->builder, val, address);
3131 } else {
3132 for (unsigned chan = 0; chan < 4; chan++) {
3133 if (!(writemask & (1 << chan)))
3134 continue;
3135 LLVMValueRef ptr =
3136 LLVMBuildStructGEP(ctx->builder,
3137 address, chan, "");
3138 LLVMValueRef src = llvm_extract_elem(ctx, val,
3139 chan);
3140 src = LLVMBuildBitCast(
3141 ctx->builder, src,
3142 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3143 LLVMBuildStore(ctx->builder, src, ptr);
3144 }
3145 }
3146 break;
3147 }
3148 default:
3149 break;
3150 }
3151 }
3152
3153 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3154 {
3155 switch (dim) {
3156 case GLSL_SAMPLER_DIM_BUF:
3157 return 1;
3158 case GLSL_SAMPLER_DIM_1D:
3159 return array ? 2 : 1;
3160 case GLSL_SAMPLER_DIM_2D:
3161 return array ? 3 : 2;
3162 case GLSL_SAMPLER_DIM_MS:
3163 return array ? 4 : 3;
3164 case GLSL_SAMPLER_DIM_3D:
3165 case GLSL_SAMPLER_DIM_CUBE:
3166 return 3;
3167 case GLSL_SAMPLER_DIM_RECT:
3168 case GLSL_SAMPLER_DIM_SUBPASS:
3169 return 2;
3170 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3171 return 3;
3172 default:
3173 break;
3174 }
3175 return 0;
3176 }
3177
3178
3179
3180 /* Adjust the sample index according to FMASK.
3181 *
3182 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3183 * which is the identity mapping. Each nibble says which physical sample
3184 * should be fetched to get that sample.
3185 *
3186 * For example, 0x11111100 means there are only 2 samples stored and
3187 * the second sample covers 3/4 of the pixel. When reading samples 0
3188 * and 1, return physical sample 0 (determined by the first two 0s
3189 * in FMASK), otherwise return physical sample 1.
3190 *
3191 * The sample index should be adjusted as follows:
3192 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3193 */
3194 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3195 LLVMValueRef coord_x, LLVMValueRef coord_y,
3196 LLVMValueRef coord_z,
3197 LLVMValueRef sample_index,
3198 LLVMValueRef fmask_desc_ptr)
3199 {
3200 LLVMValueRef fmask_load_address[4];
3201 LLVMValueRef res;
3202
3203 fmask_load_address[0] = coord_x;
3204 fmask_load_address[1] = coord_y;
3205 if (coord_z) {
3206 fmask_load_address[2] = coord_z;
3207 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3208 }
3209
3210 struct ac_image_args args = {0};
3211
3212 args.opcode = ac_image_load;
3213 args.da = coord_z ? true : false;
3214 args.resource = fmask_desc_ptr;
3215 args.dmask = 0xf;
3216 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3217
3218 res = ac_build_image_opcode(&ctx->ac, &args);
3219
3220 res = to_integer(&ctx->ac, res);
3221 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3222 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3223
3224 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3225 res,
3226 ctx->i32zero, "");
3227
3228 LLVMValueRef sample_index4 =
3229 LLVMBuildMul(ctx->builder, sample_index, four, "");
3230 LLVMValueRef shifted_fmask =
3231 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3232 LLVMValueRef final_sample =
3233 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3234
3235 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3236 * resource descriptor is 0 (invalid),
3237 */
3238 LLVMValueRef fmask_desc =
3239 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3240 ctx->v8i32, "");
3241
3242 LLVMValueRef fmask_word1 =
3243 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3244 ctx->i32one, "");
3245
3246 LLVMValueRef word1_is_nonzero =
3247 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3248 fmask_word1, ctx->i32zero, "");
3249
3250 /* Replace the MSAA sample index. */
3251 sample_index =
3252 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3253 final_sample, sample_index, "");
3254 return sample_index;
3255 }
3256
3257 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3258 const nir_intrinsic_instr *instr)
3259 {
3260 const struct glsl_type *type = instr->variables[0]->var->type;
3261 if(instr->variables[0]->deref.child)
3262 type = instr->variables[0]->deref.child->type;
3263
3264 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3265 LLVMValueRef coords[4];
3266 LLVMValueRef masks[] = {
3267 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3268 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3269 };
3270 LLVMValueRef res;
3271 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3272
3273 int count;
3274 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3275 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3276 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3277 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3278 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3279
3280 count = image_type_to_components_count(dim,
3281 glsl_sampler_type_is_array(type));
3282
3283 if (is_ms) {
3284 LLVMValueRef fmask_load_address[3];
3285 int chan;
3286
3287 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3288 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3289 if (glsl_sampler_type_is_array(type))
3290 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3291 else
3292 fmask_load_address[2] = NULL;
3293 if (add_frag_pos) {
3294 for (chan = 0; chan < 2; ++chan)
3295 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3296 }
3297 sample_index = adjust_sample_index_using_fmask(ctx,
3298 fmask_load_address[0],
3299 fmask_load_address[1],
3300 fmask_load_address[2],
3301 sample_index,
3302 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3303 }
3304 if (count == 1) {
3305 if (instr->src[0].ssa->num_components)
3306 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3307 else
3308 res = src0;
3309 } else {
3310 int chan;
3311 if (is_ms)
3312 count--;
3313 for (chan = 0; chan < count; ++chan) {
3314 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3315 }
3316
3317 if (add_frag_pos) {
3318 for (chan = 0; chan < count; ++chan)
3319 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3320 }
3321 if (is_ms) {
3322 coords[count] = sample_index;
3323 count++;
3324 }
3325
3326 if (count == 3) {
3327 coords[3] = LLVMGetUndef(ctx->i32);
3328 count = 4;
3329 }
3330 res = ac_build_gather_values(&ctx->ac, coords, count);
3331 }
3332 return res;
3333 }
3334
3335 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3336 const nir_intrinsic_instr *instr)
3337 {
3338 LLVMValueRef params[7];
3339 LLVMValueRef res;
3340 char intrinsic_name[64];
3341 const nir_variable *var = instr->variables[0]->var;
3342 const struct glsl_type *type = var->type;
3343 if(instr->variables[0]->deref.child)
3344 type = instr->variables[0]->deref.child->type;
3345
3346 type = glsl_without_array(type);
3347 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3348 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3349 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3350 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3351 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3352 params[3] = ctx->i1false; /* glc */
3353 params[4] = ctx->i1false; /* slc */
3354 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3355 params, 5, 0);
3356
3357 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3358 res = to_integer(&ctx->ac, res);
3359 } else {
3360 bool is_da = glsl_sampler_type_is_array(type) ||
3361 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3362 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3363 LLVMValueRef glc = ctx->i1false;
3364 LLVMValueRef slc = ctx->i1false;
3365
3366 params[0] = get_image_coords(ctx, instr);
3367 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3368 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3369 if (HAVE_LLVM <= 0x0309) {
3370 params[3] = ctx->i1false; /* r128 */
3371 params[4] = da;
3372 params[5] = glc;
3373 params[6] = slc;
3374 } else {
3375 LLVMValueRef lwe = ctx->i1false;
3376 params[3] = glc;
3377 params[4] = slc;
3378 params[5] = lwe;
3379 params[6] = da;
3380 }
3381
3382 ac_get_image_intr_name("llvm.amdgcn.image.load",
3383 ctx->v4f32, /* vdata */
3384 LLVMTypeOf(params[0]), /* coords */
3385 LLVMTypeOf(params[1]), /* rsrc */
3386 intrinsic_name, sizeof(intrinsic_name));
3387
3388 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3389 params, 7, AC_FUNC_ATTR_READONLY);
3390 }
3391 return to_integer(&ctx->ac, res);
3392 }
3393
3394 static void visit_image_store(struct nir_to_llvm_context *ctx,
3395 nir_intrinsic_instr *instr)
3396 {
3397 LLVMValueRef params[8];
3398 char intrinsic_name[64];
3399 const nir_variable *var = instr->variables[0]->var;
3400 const struct glsl_type *type = glsl_without_array(var->type);
3401 LLVMValueRef glc = ctx->i1false;
3402 bool force_glc = ctx->options->chip_class == SI;
3403 if (force_glc)
3404 glc = ctx->i1true;
3405 if (ctx->stage == MESA_SHADER_FRAGMENT)
3406 ctx->shader_info->fs.writes_memory = true;
3407
3408 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3409 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3410 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3411 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3412 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3413 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3414 params[4] = glc; /* glc */
3415 params[5] = ctx->i1false; /* slc */
3416 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3417 params, 6, 0);
3418 } else {
3419 bool is_da = glsl_sampler_type_is_array(type) ||
3420 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3421 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3422 LLVMValueRef slc = ctx->i1false;
3423
3424 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3425 params[1] = get_image_coords(ctx, instr); /* coords */
3426 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3427 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3428 if (HAVE_LLVM <= 0x0309) {
3429 params[4] = ctx->i1false; /* r128 */
3430 params[5] = da;
3431 params[6] = glc;
3432 params[7] = slc;
3433 } else {
3434 LLVMValueRef lwe = ctx->i1false;
3435 params[4] = glc;
3436 params[5] = slc;
3437 params[6] = lwe;
3438 params[7] = da;
3439 }
3440
3441 ac_get_image_intr_name("llvm.amdgcn.image.store",
3442 LLVMTypeOf(params[0]), /* vdata */
3443 LLVMTypeOf(params[1]), /* coords */
3444 LLVMTypeOf(params[2]), /* rsrc */
3445 intrinsic_name, sizeof(intrinsic_name));
3446
3447 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3448 params, 8, 0);
3449 }
3450
3451 }
3452
3453 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3454 const nir_intrinsic_instr *instr)
3455 {
3456 LLVMValueRef params[6];
3457 int param_count = 0;
3458 const nir_variable *var = instr->variables[0]->var;
3459
3460 const char *atomic_name;
3461 char intrinsic_name[41];
3462 const struct glsl_type *type = glsl_without_array(var->type);
3463 MAYBE_UNUSED int length;
3464
3465 if (ctx->stage == MESA_SHADER_FRAGMENT)
3466 ctx->shader_info->fs.writes_memory = true;
3467
3468 switch (instr->intrinsic) {
3469 case nir_intrinsic_image_atomic_add:
3470 atomic_name = "add";
3471 break;
3472 case nir_intrinsic_image_atomic_min:
3473 atomic_name = "smin";
3474 break;
3475 case nir_intrinsic_image_atomic_max:
3476 atomic_name = "smax";
3477 break;
3478 case nir_intrinsic_image_atomic_and:
3479 atomic_name = "and";
3480 break;
3481 case nir_intrinsic_image_atomic_or:
3482 atomic_name = "or";
3483 break;
3484 case nir_intrinsic_image_atomic_xor:
3485 atomic_name = "xor";
3486 break;
3487 case nir_intrinsic_image_atomic_exchange:
3488 atomic_name = "swap";
3489 break;
3490 case nir_intrinsic_image_atomic_comp_swap:
3491 atomic_name = "cmpswap";
3492 break;
3493 default:
3494 abort();
3495 }
3496
3497 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3498 params[param_count++] = get_src(ctx, instr->src[3]);
3499 params[param_count++] = get_src(ctx, instr->src[2]);
3500
3501 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3502 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3503 params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3504 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3505 params[param_count++] = ctx->i32zero; /* voffset */
3506 params[param_count++] = ctx->i1false; /* slc */
3507
3508 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3509 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3510 } else {
3511 char coords_type[8];
3512
3513 bool da = glsl_sampler_type_is_array(type) ||
3514 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3515
3516 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3517 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3518 params[param_count++] = ctx->i1false; /* r128 */
3519 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3520 params[param_count++] = ctx->i1false; /* slc */
3521
3522 build_int_type_name(LLVMTypeOf(coords),
3523 coords_type, sizeof(coords_type));
3524
3525 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3526 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3527 }
3528
3529 assert(length < sizeof(intrinsic_name));
3530 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3531 }
3532
3533 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3534 const nir_intrinsic_instr *instr)
3535 {
3536 LLVMValueRef res;
3537 const nir_variable *var = instr->variables[0]->var;
3538 const struct glsl_type *type = instr->variables[0]->var->type;
3539 bool da = glsl_sampler_type_is_array(var->type) ||
3540 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3541 if(instr->variables[0]->deref.child)
3542 type = instr->variables[0]->deref.child->type;
3543
3544 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3545 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3546
3547 struct ac_image_args args = { 0 };
3548
3549 args.da = da;
3550 args.dmask = 0xf;
3551 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3552 args.opcode = ac_image_get_resinfo;
3553 args.addr = ctx->i32zero;
3554
3555 res = ac_build_image_opcode(&ctx->ac, &args);
3556
3557 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3558 glsl_sampler_type_is_array(type)) {
3559 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3560 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3561 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3562 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3563 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3564 }
3565 return res;
3566 }
3567
3568 #define NOOP_WAITCNT 0xf7f
3569 #define LGKM_CNT 0x07f
3570 #define VM_CNT 0xf70
3571
3572 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3573 unsigned simm16)
3574 {
3575 LLVMValueRef args[1] = {
3576 LLVMConstInt(ctx->i32, simm16, false),
3577 };
3578 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3579 ctx->voidt, args, 1, 0);
3580 }
3581
3582 static void emit_barrier(struct nir_to_llvm_context *ctx)
3583 {
3584 /* SI only (thanks to a hw bug workaround):
3585 * The real barrier instruction isn’t needed, because an entire patch
3586 * always fits into a single wave.
3587 */
3588 if (ctx->options->chip_class == SI &&
3589 ctx->stage == MESA_SHADER_TESS_CTRL) {
3590 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3591 return;
3592 }
3593 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3594 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3595 }
3596
3597 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3598 const nir_intrinsic_instr *instr)
3599 {
3600 LLVMValueRef cond;
3601 ctx->shader_info->fs.can_discard = true;
3602
3603 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3604 get_src(ctx, instr->src[0]),
3605 ctx->i32zero, "");
3606
3607 cond = LLVMBuildSelect(ctx->builder, cond,
3608 LLVMConstReal(ctx->f32, -1.0f),
3609 ctx->f32zero, "");
3610 ac_build_kill(&ctx->ac, cond);
3611 }
3612
3613 static LLVMValueRef
3614 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3615 {
3616 LLVMValueRef result;
3617 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3618 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3619 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3620
3621 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3622 }
3623
3624 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3625 const nir_intrinsic_instr *instr)
3626 {
3627 LLVMValueRef ptr, result;
3628 LLVMValueRef src = get_src(ctx, instr->src[0]);
3629 ptr = build_gep_for_deref(ctx, instr->variables[0]);
3630
3631 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3632 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3633 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3634 ptr, src, src1,
3635 LLVMAtomicOrderingSequentiallyConsistent,
3636 LLVMAtomicOrderingSequentiallyConsistent,
3637 false);
3638 } else {
3639 LLVMAtomicRMWBinOp op;
3640 switch (instr->intrinsic) {
3641 case nir_intrinsic_var_atomic_add:
3642 op = LLVMAtomicRMWBinOpAdd;
3643 break;
3644 case nir_intrinsic_var_atomic_umin:
3645 op = LLVMAtomicRMWBinOpUMin;
3646 break;
3647 case nir_intrinsic_var_atomic_umax:
3648 op = LLVMAtomicRMWBinOpUMax;
3649 break;
3650 case nir_intrinsic_var_atomic_imin:
3651 op = LLVMAtomicRMWBinOpMin;
3652 break;
3653 case nir_intrinsic_var_atomic_imax:
3654 op = LLVMAtomicRMWBinOpMax;
3655 break;
3656 case nir_intrinsic_var_atomic_and:
3657 op = LLVMAtomicRMWBinOpAnd;
3658 break;
3659 case nir_intrinsic_var_atomic_or:
3660 op = LLVMAtomicRMWBinOpOr;
3661 break;
3662 case nir_intrinsic_var_atomic_xor:
3663 op = LLVMAtomicRMWBinOpXor;
3664 break;
3665 case nir_intrinsic_var_atomic_exchange:
3666 op = LLVMAtomicRMWBinOpXchg;
3667 break;
3668 default:
3669 return NULL;
3670 }
3671
3672 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3673 LLVMAtomicOrderingSequentiallyConsistent,
3674 false);
3675 }
3676 return result;
3677 }
3678
3679 #define INTERP_CENTER 0
3680 #define INTERP_CENTROID 1
3681 #define INTERP_SAMPLE 2
3682
3683 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3684 enum glsl_interp_mode interp, unsigned location)
3685 {
3686 switch (interp) {
3687 case INTERP_MODE_FLAT:
3688 default:
3689 return NULL;
3690 case INTERP_MODE_SMOOTH:
3691 case INTERP_MODE_NONE:
3692 if (location == INTERP_CENTER)
3693 return ctx->persp_center;
3694 else if (location == INTERP_CENTROID)
3695 return ctx->persp_centroid;
3696 else if (location == INTERP_SAMPLE)
3697 return ctx->persp_sample;
3698 break;
3699 case INTERP_MODE_NOPERSPECTIVE:
3700 if (location == INTERP_CENTER)
3701 return ctx->linear_center;
3702 else if (location == INTERP_CENTROID)
3703 return ctx->linear_centroid;
3704 else if (location == INTERP_SAMPLE)
3705 return ctx->linear_sample;
3706 break;
3707 }
3708 return NULL;
3709 }
3710
3711 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3712 LLVMValueRef sample_id)
3713 {
3714 LLVMValueRef result;
3715 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3716
3717 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3718 const_array(ctx->v2f32, 64), "");
3719
3720 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3721 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3722
3723 return result;
3724 }
3725
3726 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3727 {
3728 LLVMValueRef values[2];
3729
3730 values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
3731 values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
3732 return ac_build_gather_values(&ctx->ac, values, 2);
3733 }
3734
3735 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3736 const nir_intrinsic_instr *instr)
3737 {
3738 LLVMValueRef result[2];
3739 LLVMValueRef interp_param, attr_number;
3740 unsigned location;
3741 unsigned chan;
3742 LLVMValueRef src_c0, src_c1;
3743 LLVMValueRef src0;
3744 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3745 switch (instr->intrinsic) {
3746 case nir_intrinsic_interp_var_at_centroid:
3747 location = INTERP_CENTROID;
3748 break;
3749 case nir_intrinsic_interp_var_at_sample:
3750 case nir_intrinsic_interp_var_at_offset:
3751 location = INTERP_CENTER;
3752 src0 = get_src(ctx, instr->src[0]);
3753 break;
3754 default:
3755 break;
3756 }
3757
3758 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3759 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3760 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3761 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3762 LLVMValueRef sample_position;
3763 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3764
3765 /* fetch sample ID */
3766 sample_position = load_sample_position(ctx, src0);
3767
3768 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3769 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3770 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3771 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3772 }
3773 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3774 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3775
3776 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3777 LLVMValueRef ij_out[2];
3778 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3779
3780 /*
3781 * take the I then J parameters, and the DDX/Y for it, and
3782 * calculate the IJ inputs for the interpolator.
3783 * temp1 = ddx * offset/sample.x + I;
3784 * interp_param.I = ddy * offset/sample.y + temp1;
3785 * temp1 = ddx * offset/sample.x + J;
3786 * interp_param.J = ddy * offset/sample.y + temp1;
3787 */
3788 for (unsigned i = 0; i < 2; i++) {
3789 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3790 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3791 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3792 ddxy_out, ix_ll, "");
3793 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3794 ddxy_out, iy_ll, "");
3795 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3796 interp_param, ix_ll, "");
3797 LLVMValueRef temp1, temp2;
3798
3799 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3800 ctx->f32, "");
3801
3802 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3803 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3804
3805 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3806 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3807
3808 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3809 temp2, ctx->i32, "");
3810 }
3811 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3812
3813 }
3814
3815 for (chan = 0; chan < 2; chan++) {
3816 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3817
3818 if (interp_param) {
3819 interp_param = LLVMBuildBitCast(ctx->builder,
3820 interp_param, LLVMVectorType(ctx->f32, 2), "");
3821 LLVMValueRef i = LLVMBuildExtractElement(
3822 ctx->builder, interp_param, ctx->i32zero, "");
3823 LLVMValueRef j = LLVMBuildExtractElement(
3824 ctx->builder, interp_param, ctx->i32one, "");
3825
3826 result[chan] = ac_build_fs_interp(&ctx->ac,
3827 llvm_chan, attr_number,
3828 ctx->prim_mask, i, j);
3829 } else {
3830 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3831 LLVMConstInt(ctx->i32, 2, false),
3832 llvm_chan, attr_number,
3833 ctx->prim_mask);
3834 }
3835 }
3836 return ac_build_gather_values(&ctx->ac, result, 2);
3837 }
3838
3839 static void
3840 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3841 const nir_intrinsic_instr *instr)
3842 {
3843 LLVMValueRef gs_next_vertex;
3844 LLVMValueRef can_emit, kill;
3845 int idx;
3846
3847 assert(instr->const_index[0] == 0);
3848 /* Write vertex attribute values to GSVS ring */
3849 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3850 ctx->gs_next_vertex,
3851 "");
3852
3853 /* If this thread has already emitted the declared maximum number of
3854 * vertices, kill it: excessive vertex emissions are not supposed to
3855 * have any effect, and GS threads have no externally observable
3856 * effects other than emitting vertices.
3857 */
3858 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3859 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3860
3861 kill = LLVMBuildSelect(ctx->builder, can_emit,
3862 LLVMConstReal(ctx->f32, 1.0f),
3863 LLVMConstReal(ctx->f32, -1.0f), "");
3864 ac_build_kill(&ctx->ac, kill);
3865
3866 /* loop num outputs */
3867 idx = 0;
3868 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3869 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3870 int length = 4;
3871 int slot = idx;
3872 int slot_inc = 1;
3873
3874 if (!(ctx->output_mask & (1ull << i)))
3875 continue;
3876
3877 if (i == VARYING_SLOT_CLIP_DIST0) {
3878 /* pack clip and cull into a single set of slots */
3879 length = ctx->num_output_clips + ctx->num_output_culls;
3880 if (length > 4)
3881 slot_inc = 2;
3882 }
3883 for (unsigned j = 0; j < length; j++) {
3884 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3885 out_ptr[j], "");
3886 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3887 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3888 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3889
3890 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3891
3892 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3893 out_val, 1,
3894 voffset, ctx->gs2vs_offset, 0,
3895 1, 1, true, true);
3896 }
3897 idx += slot_inc;
3898 }
3899
3900 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3901 ctx->i32one, "");
3902 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3903
3904 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3905 }
3906
3907 static void
3908 visit_end_primitive(struct nir_to_llvm_context *ctx,
3909 const nir_intrinsic_instr *instr)
3910 {
3911 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3912 }
3913
3914 static LLVMValueRef
3915 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3916 const nir_intrinsic_instr *instr)
3917 {
3918 LLVMValueRef coord[4] = {
3919 ctx->tes_u,
3920 ctx->tes_v,
3921 ctx->f32zero,
3922 ctx->f32zero,
3923 };
3924
3925 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3926 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3927 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3928
3929 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3930 return LLVMBuildBitCast(ctx->builder, result,
3931 get_def_type(ctx, &instr->dest.ssa), "");
3932 }
3933
3934 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3935 nir_intrinsic_instr *instr)
3936 {
3937 LLVMValueRef result = NULL;
3938
3939 switch (instr->intrinsic) {
3940 case nir_intrinsic_load_work_group_id: {
3941 result = ctx->workgroup_ids;
3942 break;
3943 }
3944 case nir_intrinsic_load_base_vertex: {
3945 result = ctx->abi.base_vertex;
3946 break;
3947 }
3948 case nir_intrinsic_load_vertex_id_zero_base: {
3949 result = ctx->abi.vertex_id;
3950 break;
3951 }
3952 case nir_intrinsic_load_local_invocation_id: {
3953 result = ctx->local_invocation_ids;
3954 break;
3955 }
3956 case nir_intrinsic_load_base_instance:
3957 result = ctx->abi.start_instance;
3958 break;
3959 case nir_intrinsic_load_draw_id:
3960 result = ctx->abi.draw_id;
3961 break;
3962 case nir_intrinsic_load_invocation_id:
3963 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3964 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3965 else
3966 result = ctx->gs_invocation_id;
3967 break;
3968 case nir_intrinsic_load_primitive_id:
3969 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3970 ctx->shader_info->gs.uses_prim_id = true;
3971 result = ctx->gs_prim_id;
3972 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3973 ctx->shader_info->tcs.uses_prim_id = true;
3974 result = ctx->tcs_patch_id;
3975 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
3976 ctx->shader_info->tcs.uses_prim_id = true;
3977 result = ctx->tes_patch_id;
3978 } else
3979 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3980 break;
3981 case nir_intrinsic_load_sample_id:
3982 ctx->shader_info->fs.force_persample = true;
3983 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3984 break;
3985 case nir_intrinsic_load_sample_pos:
3986 ctx->shader_info->fs.force_persample = true;
3987 result = load_sample_pos(ctx);
3988 break;
3989 case nir_intrinsic_load_sample_mask_in:
3990 result = ctx->sample_coverage;
3991 break;
3992 case nir_intrinsic_load_front_face:
3993 result = ctx->front_face;
3994 break;
3995 case nir_intrinsic_load_instance_id:
3996 result = ctx->abi.instance_id;
3997 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3998 ctx->shader_info->vs.vgpr_comp_cnt);
3999 break;
4000 case nir_intrinsic_load_num_work_groups:
4001 result = ctx->num_work_groups;
4002 break;
4003 case nir_intrinsic_load_local_invocation_index:
4004 result = visit_load_local_invocation_index(ctx);
4005 break;
4006 case nir_intrinsic_load_push_constant:
4007 result = visit_load_push_constant(ctx, instr);
4008 break;
4009 case nir_intrinsic_vulkan_resource_index:
4010 result = visit_vulkan_resource_index(ctx, instr);
4011 break;
4012 case nir_intrinsic_store_ssbo:
4013 visit_store_ssbo(ctx, instr);
4014 break;
4015 case nir_intrinsic_load_ssbo:
4016 result = visit_load_buffer(ctx, instr);
4017 break;
4018 case nir_intrinsic_ssbo_atomic_add:
4019 case nir_intrinsic_ssbo_atomic_imin:
4020 case nir_intrinsic_ssbo_atomic_umin:
4021 case nir_intrinsic_ssbo_atomic_imax:
4022 case nir_intrinsic_ssbo_atomic_umax:
4023 case nir_intrinsic_ssbo_atomic_and:
4024 case nir_intrinsic_ssbo_atomic_or:
4025 case nir_intrinsic_ssbo_atomic_xor:
4026 case nir_intrinsic_ssbo_atomic_exchange:
4027 case nir_intrinsic_ssbo_atomic_comp_swap:
4028 result = visit_atomic_ssbo(ctx, instr);
4029 break;
4030 case nir_intrinsic_load_ubo:
4031 result = visit_load_ubo_buffer(ctx, instr);
4032 break;
4033 case nir_intrinsic_get_buffer_size:
4034 result = visit_get_buffer_size(ctx, instr);
4035 break;
4036 case nir_intrinsic_load_var:
4037 result = visit_load_var(ctx, instr);
4038 break;
4039 case nir_intrinsic_store_var:
4040 visit_store_var(ctx, instr);
4041 break;
4042 case nir_intrinsic_image_load:
4043 result = visit_image_load(ctx, instr);
4044 break;
4045 case nir_intrinsic_image_store:
4046 visit_image_store(ctx, instr);
4047 break;
4048 case nir_intrinsic_image_atomic_add:
4049 case nir_intrinsic_image_atomic_min:
4050 case nir_intrinsic_image_atomic_max:
4051 case nir_intrinsic_image_atomic_and:
4052 case nir_intrinsic_image_atomic_or:
4053 case nir_intrinsic_image_atomic_xor:
4054 case nir_intrinsic_image_atomic_exchange:
4055 case nir_intrinsic_image_atomic_comp_swap:
4056 result = visit_image_atomic(ctx, instr);
4057 break;
4058 case nir_intrinsic_image_size:
4059 result = visit_image_size(ctx, instr);
4060 break;
4061 case nir_intrinsic_discard:
4062 ctx->shader_info->fs.can_discard = true;
4063 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4064 ctx->voidt,
4065 NULL, 0, AC_FUNC_ATTR_LEGACY);
4066 break;
4067 case nir_intrinsic_discard_if:
4068 emit_discard_if(ctx, instr);
4069 break;
4070 case nir_intrinsic_memory_barrier:
4071 emit_waitcnt(ctx, VM_CNT);
4072 break;
4073 case nir_intrinsic_barrier:
4074 emit_barrier(ctx);
4075 break;
4076 case nir_intrinsic_var_atomic_add:
4077 case nir_intrinsic_var_atomic_imin:
4078 case nir_intrinsic_var_atomic_umin:
4079 case nir_intrinsic_var_atomic_imax:
4080 case nir_intrinsic_var_atomic_umax:
4081 case nir_intrinsic_var_atomic_and:
4082 case nir_intrinsic_var_atomic_or:
4083 case nir_intrinsic_var_atomic_xor:
4084 case nir_intrinsic_var_atomic_exchange:
4085 case nir_intrinsic_var_atomic_comp_swap:
4086 result = visit_var_atomic(ctx, instr);
4087 break;
4088 case nir_intrinsic_interp_var_at_centroid:
4089 case nir_intrinsic_interp_var_at_sample:
4090 case nir_intrinsic_interp_var_at_offset:
4091 result = visit_interp(ctx, instr);
4092 break;
4093 case nir_intrinsic_emit_vertex:
4094 visit_emit_vertex(ctx, instr);
4095 break;
4096 case nir_intrinsic_end_primitive:
4097 visit_end_primitive(ctx, instr);
4098 break;
4099 case nir_intrinsic_load_tess_coord:
4100 result = visit_load_tess_coord(ctx, instr);
4101 break;
4102 case nir_intrinsic_load_patch_vertices_in:
4103 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
4104 break;
4105 default:
4106 fprintf(stderr, "Unknown intrinsic: ");
4107 nir_print_instr(&instr->instr, stderr);
4108 fprintf(stderr, "\n");
4109 break;
4110 }
4111 if (result) {
4112 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4113 }
4114 }
4115
4116 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4117 const nir_deref_var *deref,
4118 enum desc_type desc_type)
4119 {
4120 unsigned desc_set = deref->var->data.descriptor_set;
4121 LLVMValueRef list = ctx->descriptor_sets[desc_set];
4122 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4123 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4124 unsigned offset = binding->offset;
4125 unsigned stride = binding->size;
4126 unsigned type_size;
4127 LLVMBuilderRef builder = ctx->builder;
4128 LLVMTypeRef type;
4129 LLVMValueRef index = NULL;
4130 unsigned constant_index = 0;
4131
4132 assert(deref->var->data.binding < layout->binding_count);
4133
4134 switch (desc_type) {
4135 case DESC_IMAGE:
4136 type = ctx->v8i32;
4137 type_size = 32;
4138 break;
4139 case DESC_FMASK:
4140 type = ctx->v8i32;
4141 offset += 32;
4142 type_size = 32;
4143 break;
4144 case DESC_SAMPLER:
4145 type = ctx->v4i32;
4146 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4147 offset += 64;
4148
4149 type_size = 16;
4150 break;
4151 case DESC_BUFFER:
4152 type = ctx->v4i32;
4153 type_size = 16;
4154 break;
4155 default:
4156 unreachable("invalid desc_type\n");
4157 }
4158
4159 if (deref->deref.child) {
4160 const nir_deref_array *child =
4161 (const nir_deref_array *)deref->deref.child;
4162
4163 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4164 offset += child->base_offset * stride;
4165 if (child->deref_array_type == nir_deref_array_type_indirect) {
4166 index = get_src(ctx, child->indirect);
4167 }
4168
4169 constant_index = child->base_offset;
4170 }
4171 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4172 (!index || binding->immutable_samplers_equal)) {
4173 if (binding->immutable_samplers_equal)
4174 constant_index = 0;
4175
4176 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4177
4178 LLVMValueRef constants[] = {
4179 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4180 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4181 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4182 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4183 };
4184 return ac_build_gather_values(&ctx->ac, constants, 4);
4185 }
4186
4187 assert(stride % type_size == 0);
4188
4189 if (!index)
4190 index = ctx->i32zero;
4191
4192 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4193
4194 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4195 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4196
4197 return ac_build_indexed_load_const(&ctx->ac, list, index);
4198 }
4199
4200 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4201 struct ac_image_args *args,
4202 const nir_tex_instr *instr,
4203 nir_texop op,
4204 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4205 LLVMValueRef *param, unsigned count,
4206 unsigned dmask)
4207 {
4208 unsigned is_rect = 0;
4209 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4210
4211 if (op == nir_texop_lod)
4212 da = false;
4213 /* Pad to power of two vector */
4214 while (count < util_next_power_of_two(count))
4215 param[count++] = LLVMGetUndef(ctx->i32);
4216
4217 if (count > 1)
4218 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4219 else
4220 args->addr = param[0];
4221
4222 args->resource = res_ptr;
4223 args->sampler = samp_ptr;
4224
4225 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4226 args->addr = param[0];
4227 return;
4228 }
4229
4230 args->dmask = dmask;
4231 args->unorm = is_rect;
4232 args->da = da;
4233 }
4234
4235 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4236 *
4237 * SI-CI:
4238 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4239 * filtering manually. The driver sets img7 to a mask clearing
4240 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4241 * s_and_b32 samp0, samp0, img7
4242 *
4243 * VI:
4244 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4245 */
4246 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4247 LLVMValueRef res, LLVMValueRef samp)
4248 {
4249 LLVMBuilderRef builder = ctx->builder;
4250 LLVMValueRef img7, samp0;
4251
4252 if (ctx->options->chip_class >= VI)
4253 return samp;
4254
4255 img7 = LLVMBuildExtractElement(builder, res,
4256 LLVMConstInt(ctx->i32, 7, 0), "");
4257 samp0 = LLVMBuildExtractElement(builder, samp,
4258 LLVMConstInt(ctx->i32, 0, 0), "");
4259 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4260 return LLVMBuildInsertElement(builder, samp, samp0,
4261 LLVMConstInt(ctx->i32, 0, 0), "");
4262 }
4263
4264 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4265 nir_tex_instr *instr,
4266 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4267 LLVMValueRef *fmask_ptr)
4268 {
4269 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4270 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4271 else
4272 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4273 if (samp_ptr) {
4274 if (instr->sampler)
4275 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4276 else
4277 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4278 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4279 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4280 }
4281 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4282 instr->op == nir_texop_samples_identical))
4283 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4284 }
4285
4286 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4287 LLVMValueRef coord)
4288 {
4289 coord = to_float(&ctx->ac, coord);
4290 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4291 coord = to_integer(&ctx->ac, coord);
4292 return coord;
4293 }
4294
4295 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4296 {
4297 LLVMValueRef result = NULL;
4298 struct ac_image_args args = { 0 };
4299 unsigned dmask = 0xf;
4300 LLVMValueRef address[16];
4301 LLVMValueRef coords[5];
4302 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4303 LLVMValueRef bias = NULL, offsets = NULL;
4304 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4305 LLVMValueRef ddx = NULL, ddy = NULL;
4306 LLVMValueRef derivs[6];
4307 unsigned chan, count = 0;
4308 unsigned const_src = 0, num_deriv_comp = 0;
4309 bool lod_is_zero = false;
4310 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4311
4312 for (unsigned i = 0; i < instr->num_srcs; i++) {
4313 switch (instr->src[i].src_type) {
4314 case nir_tex_src_coord:
4315 coord = get_src(ctx, instr->src[i].src);
4316 break;
4317 case nir_tex_src_projector:
4318 break;
4319 case nir_tex_src_comparator:
4320 comparator = get_src(ctx, instr->src[i].src);
4321 break;
4322 case nir_tex_src_offset:
4323 offsets = get_src(ctx, instr->src[i].src);
4324 const_src = i;
4325 break;
4326 case nir_tex_src_bias:
4327 bias = get_src(ctx, instr->src[i].src);
4328 break;
4329 case nir_tex_src_lod: {
4330 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4331
4332 if (val && val->i32[0] == 0)
4333 lod_is_zero = true;
4334 lod = get_src(ctx, instr->src[i].src);
4335 break;
4336 }
4337 case nir_tex_src_ms_index:
4338 sample_index = get_src(ctx, instr->src[i].src);
4339 break;
4340 case nir_tex_src_ms_mcs:
4341 break;
4342 case nir_tex_src_ddx:
4343 ddx = get_src(ctx, instr->src[i].src);
4344 num_deriv_comp = instr->src[i].src.ssa->num_components;
4345 break;
4346 case nir_tex_src_ddy:
4347 ddy = get_src(ctx, instr->src[i].src);
4348 break;
4349 case nir_tex_src_texture_offset:
4350 case nir_tex_src_sampler_offset:
4351 case nir_tex_src_plane:
4352 default:
4353 break;
4354 }
4355 }
4356
4357 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4358 result = get_buffer_size(ctx, res_ptr, true);
4359 goto write_result;
4360 }
4361
4362 if (instr->op == nir_texop_texture_samples) {
4363 LLVMValueRef res, samples, is_msaa;
4364 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4365 samples = LLVMBuildExtractElement(ctx->builder, res,
4366 LLVMConstInt(ctx->i32, 3, false), "");
4367 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4368 LLVMConstInt(ctx->i32, 28, false), "");
4369 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4370 LLVMConstInt(ctx->i32, 0xe, false), "");
4371 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4372 LLVMConstInt(ctx->i32, 0xe, false), "");
4373
4374 samples = LLVMBuildLShr(ctx->builder, samples,
4375 LLVMConstInt(ctx->i32, 16, false), "");
4376 samples = LLVMBuildAnd(ctx->builder, samples,
4377 LLVMConstInt(ctx->i32, 0xf, false), "");
4378 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4379 samples, "");
4380 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4381 ctx->i32one, "");
4382 result = samples;
4383 goto write_result;
4384 }
4385
4386 if (coord)
4387 for (chan = 0; chan < instr->coord_components; chan++)
4388 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4389
4390 if (offsets && instr->op != nir_texop_txf) {
4391 LLVMValueRef offset[3], pack;
4392 for (chan = 0; chan < 3; ++chan)
4393 offset[chan] = ctx->i32zero;
4394
4395 args.offset = true;
4396 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4397 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4398 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4399 LLVMConstInt(ctx->i32, 0x3f, false), "");
4400 if (chan)
4401 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4402 LLVMConstInt(ctx->i32, chan * 8, false), "");
4403 }
4404 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4405 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4406 address[count++] = pack;
4407
4408 }
4409 /* pack LOD bias value */
4410 if (instr->op == nir_texop_txb && bias) {
4411 address[count++] = bias;
4412 }
4413
4414 /* Pack depth comparison value */
4415 if (instr->is_shadow && comparator) {
4416 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4417 }
4418
4419 /* pack derivatives */
4420 if (ddx || ddy) {
4421 switch (instr->sampler_dim) {
4422 case GLSL_SAMPLER_DIM_3D:
4423 case GLSL_SAMPLER_DIM_CUBE:
4424 num_deriv_comp = 3;
4425 break;
4426 case GLSL_SAMPLER_DIM_2D:
4427 default:
4428 num_deriv_comp = 2;
4429 break;
4430 case GLSL_SAMPLER_DIM_1D:
4431 num_deriv_comp = 1;
4432 break;
4433 }
4434
4435 for (unsigned i = 0; i < num_deriv_comp; i++) {
4436 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(ctx, ddx, i));
4437 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(ctx, ddy, i));
4438 }
4439 }
4440
4441 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4442 if (instr->is_array && instr->op != nir_texop_lod)
4443 coords[3] = apply_round_slice(ctx, coords[3]);
4444 for (chan = 0; chan < instr->coord_components; chan++)
4445 coords[chan] = to_float(&ctx->ac, coords[chan]);
4446 if (instr->coord_components == 3)
4447 coords[3] = LLVMGetUndef(ctx->f32);
4448 ac_prepare_cube_coords(&ctx->ac,
4449 instr->op == nir_texop_txd, instr->is_array,
4450 coords, derivs);
4451 if (num_deriv_comp)
4452 num_deriv_comp--;
4453 }
4454
4455 if (ddx || ddy) {
4456 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4457 address[count++] = derivs[i];
4458 }
4459
4460 /* Pack texture coordinates */
4461 if (coord) {
4462 address[count++] = coords[0];
4463 if (instr->coord_components > 1) {
4464 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4465 coords[1] = apply_round_slice(ctx, coords[1]);
4466 }
4467 address[count++] = coords[1];
4468 }
4469 if (instr->coord_components > 2) {
4470 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4471 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4472 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4473 instr->op != nir_texop_txf) {
4474 coords[2] = apply_round_slice(ctx, coords[2]);
4475 }
4476 address[count++] = coords[2];
4477 }
4478 }
4479
4480 /* Pack LOD */
4481 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4482 instr->op == nir_texop_txf)) {
4483 address[count++] = lod;
4484 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4485 address[count++] = sample_index;
4486 } else if(instr->op == nir_texop_txs) {
4487 count = 0;
4488 if (lod)
4489 address[count++] = lod;
4490 else
4491 address[count++] = ctx->i32zero;
4492 }
4493
4494 for (chan = 0; chan < count; chan++) {
4495 address[chan] = LLVMBuildBitCast(ctx->builder,
4496 address[chan], ctx->i32, "");
4497 }
4498
4499 if (instr->op == nir_texop_samples_identical) {
4500 LLVMValueRef txf_address[4];
4501 struct ac_image_args txf_args = { 0 };
4502 unsigned txf_count = count;
4503 memcpy(txf_address, address, sizeof(txf_address));
4504
4505 if (!instr->is_array)
4506 txf_address[2] = ctx->i32zero;
4507 txf_address[3] = ctx->i32zero;
4508
4509 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4510 fmask_ptr, NULL,
4511 txf_address, txf_count, 0xf);
4512
4513 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4514
4515 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4516 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->i32zero);
4517 goto write_result;
4518 }
4519
4520 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4521 instr->op != nir_texop_txs) {
4522 unsigned sample_chan = instr->is_array ? 3 : 2;
4523 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4524 address[0],
4525 address[1],
4526 instr->is_array ? address[2] : NULL,
4527 address[sample_chan],
4528 fmask_ptr);
4529 }
4530
4531 if (offsets && instr->op == nir_texop_txf) {
4532 nir_const_value *const_offset =
4533 nir_src_as_const_value(instr->src[const_src].src);
4534 int num_offsets = instr->src[const_src].src.ssa->num_components;
4535 assert(const_offset);
4536 num_offsets = MIN2(num_offsets, instr->coord_components);
4537 if (num_offsets > 2)
4538 address[2] = LLVMBuildAdd(ctx->builder,
4539 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4540 if (num_offsets > 1)
4541 address[1] = LLVMBuildAdd(ctx->builder,
4542 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4543 address[0] = LLVMBuildAdd(ctx->builder,
4544 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4545
4546 }
4547
4548 /* TODO TG4 support */
4549 if (instr->op == nir_texop_tg4) {
4550 if (instr->is_shadow)
4551 dmask = 1;
4552 else
4553 dmask = 1 << instr->component;
4554 }
4555 set_tex_fetch_args(ctx, &args, instr, instr->op,
4556 res_ptr, samp_ptr, address, count, dmask);
4557
4558 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4559
4560 if (instr->op == nir_texop_query_levels)
4561 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4562 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4563 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4564 else if (instr->op == nir_texop_txs &&
4565 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4566 instr->is_array) {
4567 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4568 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4569 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4570 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4571 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4572 } else if (instr->dest.ssa.num_components != 4)
4573 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4574
4575 write_result:
4576 if (result) {
4577 assert(instr->dest.is_ssa);
4578 result = to_integer(&ctx->ac, result);
4579 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4580 }
4581 }
4582
4583
4584 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4585 {
4586 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4587 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4588
4589 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4590 _mesa_hash_table_insert(ctx->phis, instr, result);
4591 }
4592
4593 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4594 nir_phi_instr *instr,
4595 LLVMValueRef llvm_phi)
4596 {
4597 nir_foreach_phi_src(src, instr) {
4598 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4599 LLVMValueRef llvm_src = get_src(ctx, src->src);
4600
4601 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4602 }
4603 }
4604
4605 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4606 {
4607 struct hash_entry *entry;
4608 hash_table_foreach(ctx->phis, entry) {
4609 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4610 (LLVMValueRef)entry->data);
4611 }
4612 }
4613
4614
4615 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4616 const nir_ssa_undef_instr *instr)
4617 {
4618 unsigned num_components = instr->def.num_components;
4619 LLVMValueRef undef;
4620
4621 if (num_components == 1)
4622 undef = LLVMGetUndef(ctx->i32);
4623 else {
4624 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4625 }
4626 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4627 }
4628
4629 static void visit_jump(struct nir_to_llvm_context *ctx,
4630 const nir_jump_instr *instr)
4631 {
4632 switch (instr->type) {
4633 case nir_jump_break:
4634 LLVMBuildBr(ctx->builder, ctx->break_block);
4635 LLVMClearInsertionPosition(ctx->builder);
4636 break;
4637 case nir_jump_continue:
4638 LLVMBuildBr(ctx->builder, ctx->continue_block);
4639 LLVMClearInsertionPosition(ctx->builder);
4640 break;
4641 default:
4642 fprintf(stderr, "Unknown NIR jump instr: ");
4643 nir_print_instr(&instr->instr, stderr);
4644 fprintf(stderr, "\n");
4645 abort();
4646 }
4647 }
4648
4649 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4650 struct exec_list *list);
4651
4652 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4653 {
4654 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4655 nir_foreach_instr(instr, block)
4656 {
4657 switch (instr->type) {
4658 case nir_instr_type_alu:
4659 visit_alu(ctx, nir_instr_as_alu(instr));
4660 break;
4661 case nir_instr_type_load_const:
4662 visit_load_const(ctx, nir_instr_as_load_const(instr));
4663 break;
4664 case nir_instr_type_intrinsic:
4665 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4666 break;
4667 case nir_instr_type_tex:
4668 visit_tex(ctx, nir_instr_as_tex(instr));
4669 break;
4670 case nir_instr_type_phi:
4671 visit_phi(ctx, nir_instr_as_phi(instr));
4672 break;
4673 case nir_instr_type_ssa_undef:
4674 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4675 break;
4676 case nir_instr_type_jump:
4677 visit_jump(ctx, nir_instr_as_jump(instr));
4678 break;
4679 default:
4680 fprintf(stderr, "Unknown NIR instr type: ");
4681 nir_print_instr(instr, stderr);
4682 fprintf(stderr, "\n");
4683 abort();
4684 }
4685 }
4686
4687 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4688 }
4689
4690 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4691 {
4692 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4693
4694 LLVMBasicBlockRef merge_block =
4695 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4696 LLVMBasicBlockRef if_block =
4697 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4698 LLVMBasicBlockRef else_block = merge_block;
4699 if (!exec_list_is_empty(&if_stmt->else_list))
4700 else_block = LLVMAppendBasicBlockInContext(
4701 ctx->context, ctx->main_function, "");
4702
4703 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4704 LLVMConstInt(ctx->i32, 0, false), "");
4705 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4706
4707 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4708 visit_cf_list(ctx, &if_stmt->then_list);
4709 if (LLVMGetInsertBlock(ctx->builder))
4710 LLVMBuildBr(ctx->builder, merge_block);
4711
4712 if (!exec_list_is_empty(&if_stmt->else_list)) {
4713 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4714 visit_cf_list(ctx, &if_stmt->else_list);
4715 if (LLVMGetInsertBlock(ctx->builder))
4716 LLVMBuildBr(ctx->builder, merge_block);
4717 }
4718
4719 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4720 }
4721
4722 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4723 {
4724 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4725 LLVMBasicBlockRef break_parent = ctx->break_block;
4726
4727 ctx->continue_block =
4728 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4729 ctx->break_block =
4730 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4731
4732 LLVMBuildBr(ctx->builder, ctx->continue_block);
4733 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4734 visit_cf_list(ctx, &loop->body);
4735
4736 if (LLVMGetInsertBlock(ctx->builder))
4737 LLVMBuildBr(ctx->builder, ctx->continue_block);
4738 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4739
4740 ctx->continue_block = continue_parent;
4741 ctx->break_block = break_parent;
4742 }
4743
4744 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4745 struct exec_list *list)
4746 {
4747 foreach_list_typed(nir_cf_node, node, node, list)
4748 {
4749 switch (node->type) {
4750 case nir_cf_node_block:
4751 visit_block(ctx, nir_cf_node_as_block(node));
4752 break;
4753
4754 case nir_cf_node_if:
4755 visit_if(ctx, nir_cf_node_as_if(node));
4756 break;
4757
4758 case nir_cf_node_loop:
4759 visit_loop(ctx, nir_cf_node_as_loop(node));
4760 break;
4761
4762 default:
4763 assert(0);
4764 }
4765 }
4766 }
4767
4768 static void
4769 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4770 struct nir_variable *variable)
4771 {
4772 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4773 LLVMValueRef t_offset;
4774 LLVMValueRef t_list;
4775 LLVMValueRef input;
4776 LLVMValueRef buffer_index;
4777 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4778 int idx = variable->data.location;
4779 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4780
4781 variable->data.driver_location = idx * 4;
4782
4783 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4784 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.instance_id,
4785 ctx->abi.start_instance, "");
4786 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4787 ctx->shader_info->vs.vgpr_comp_cnt);
4788 } else
4789 buffer_index = LLVMBuildAdd(ctx->builder, ctx->abi.vertex_id,
4790 ctx->abi.base_vertex, "");
4791
4792 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4793 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4794
4795 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4796
4797 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4798 buffer_index,
4799 LLVMConstInt(ctx->i32, 0, false),
4800 true);
4801
4802 for (unsigned chan = 0; chan < 4; chan++) {
4803 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4804 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4805 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4806 input, llvm_chan, ""));
4807 }
4808 }
4809 }
4810
4811 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4812 unsigned attr,
4813 LLVMValueRef interp_param,
4814 LLVMValueRef prim_mask,
4815 LLVMValueRef result[4])
4816 {
4817 LLVMValueRef attr_number;
4818 unsigned chan;
4819 LLVMValueRef i, j;
4820 bool interp = interp_param != NULL;
4821
4822 attr_number = LLVMConstInt(ctx->i32, attr, false);
4823
4824 /* fs.constant returns the param from the middle vertex, so it's not
4825 * really useful for flat shading. It's meant to be used for custom
4826 * interpolation (but the intrinsic can't fetch from the other two
4827 * vertices).
4828 *
4829 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4830 * to do the right thing. The only reason we use fs.constant is that
4831 * fs.interp cannot be used on integers, because they can be equal
4832 * to NaN.
4833 */
4834 if (interp) {
4835 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4836 LLVMVectorType(ctx->f32, 2), "");
4837
4838 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4839 ctx->i32zero, "");
4840 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4841 ctx->i32one, "");
4842 }
4843
4844 for (chan = 0; chan < 4; chan++) {
4845 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4846
4847 if (interp) {
4848 result[chan] = ac_build_fs_interp(&ctx->ac,
4849 llvm_chan,
4850 attr_number,
4851 prim_mask, i, j);
4852 } else {
4853 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4854 LLVMConstInt(ctx->i32, 2, false),
4855 llvm_chan,
4856 attr_number,
4857 prim_mask);
4858 }
4859 }
4860 }
4861
4862 static void
4863 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4864 struct nir_variable *variable)
4865 {
4866 int idx = variable->data.location;
4867 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4868 LLVMValueRef interp;
4869
4870 variable->data.driver_location = idx * 4;
4871 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4872
4873 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4874 unsigned interp_type;
4875 if (variable->data.sample) {
4876 interp_type = INTERP_SAMPLE;
4877 ctx->shader_info->fs.force_persample = true;
4878 } else if (variable->data.centroid)
4879 interp_type = INTERP_CENTROID;
4880 else
4881 interp_type = INTERP_CENTER;
4882
4883 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4884 } else
4885 interp = NULL;
4886
4887 for (unsigned i = 0; i < attrib_count; ++i)
4888 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4889
4890 }
4891
4892 static void
4893 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4894 struct nir_variable *variable)
4895 {
4896 switch (ctx->stage) {
4897 case MESA_SHADER_VERTEX:
4898 handle_vs_input_decl(ctx, variable);
4899 break;
4900 case MESA_SHADER_FRAGMENT:
4901 handle_fs_input_decl(ctx, variable);
4902 break;
4903 default:
4904 break;
4905 }
4906
4907 }
4908
4909 static void
4910 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4911 struct nir_shader *nir)
4912 {
4913 unsigned index = 0;
4914 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4915 LLVMValueRef interp_param;
4916 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4917
4918 if (!(ctx->input_mask & (1ull << i)))
4919 continue;
4920
4921 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4922 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4923 interp_param = *inputs;
4924 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4925 inputs);
4926
4927 if (!interp_param)
4928 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4929 ++index;
4930 } else if (i == VARYING_SLOT_POS) {
4931 for(int i = 0; i < 3; ++i)
4932 inputs[i] = ctx->frag_pos[i];
4933
4934 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4935 }
4936 }
4937 ctx->shader_info->fs.num_interp = index;
4938 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4939 ctx->shader_info->fs.has_pcoord = true;
4940 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4941 ctx->shader_info->fs.prim_id_input = true;
4942 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4943 ctx->shader_info->fs.layer_input = true;
4944 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4945 }
4946
4947 static LLVMValueRef
4948 ac_build_alloca(struct nir_to_llvm_context *ctx,
4949 LLVMTypeRef type,
4950 const char *name)
4951 {
4952 LLVMBuilderRef builder = ctx->builder;
4953 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4954 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4955 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4956 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4957 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4958 LLVMValueRef res;
4959
4960 if (first_instr) {
4961 LLVMPositionBuilderBefore(first_builder, first_instr);
4962 } else {
4963 LLVMPositionBuilderAtEnd(first_builder, first_block);
4964 }
4965
4966 res = LLVMBuildAlloca(first_builder, type, name);
4967 LLVMBuildStore(builder, LLVMConstNull(type), res);
4968
4969 LLVMDisposeBuilder(first_builder);
4970
4971 return res;
4972 }
4973
4974 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4975 LLVMTypeRef type,
4976 const char *name)
4977 {
4978 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4979 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4980 return ptr;
4981 }
4982
4983 static void
4984 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4985 struct nir_variable *variable)
4986 {
4987 int idx = variable->data.location + variable->data.index;
4988 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4989 uint64_t mask_attribs;
4990 variable->data.driver_location = idx * 4;
4991
4992 /* tess ctrl has it's own load/store paths for outputs */
4993 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4994 return;
4995
4996 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4997 if (ctx->stage == MESA_SHADER_VERTEX ||
4998 ctx->stage == MESA_SHADER_TESS_EVAL ||
4999 ctx->stage == MESA_SHADER_GEOMETRY) {
5000 if (idx == VARYING_SLOT_CLIP_DIST0) {
5001 int length = ctx->num_output_clips + ctx->num_output_culls;
5002 if (ctx->stage == MESA_SHADER_VERTEX) {
5003 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5004 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5005 }
5006 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
5007 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
5008 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
5009 }
5010
5011 if (length > 4)
5012 attrib_count = 2;
5013 else
5014 attrib_count = 1;
5015 mask_attribs = 1ull << idx;
5016 }
5017 }
5018
5019 for (unsigned i = 0; i < attrib_count; ++i) {
5020 for (unsigned chan = 0; chan < 4; chan++) {
5021 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
5022 si_build_alloca_undef(ctx, ctx->f32, "");
5023 }
5024 }
5025 ctx->output_mask |= mask_attribs;
5026 }
5027
5028 static LLVMTypeRef
5029 glsl_base_to_llvm_type(struct nir_to_llvm_context *ctx,
5030 enum glsl_base_type type)
5031 {
5032 switch (type) {
5033 case GLSL_TYPE_INT:
5034 case GLSL_TYPE_UINT:
5035 case GLSL_TYPE_BOOL:
5036 case GLSL_TYPE_SUBROUTINE:
5037 return ctx->i32;
5038 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5039 return ctx->f32;
5040 case GLSL_TYPE_INT64:
5041 case GLSL_TYPE_UINT64:
5042 return ctx->i64;
5043 case GLSL_TYPE_DOUBLE:
5044 return ctx->f64;
5045 default:
5046 unreachable("unknown GLSL type");
5047 }
5048 }
5049
5050 static LLVMTypeRef
5051 glsl_to_llvm_type(struct nir_to_llvm_context *ctx,
5052 const struct glsl_type *type)
5053 {
5054 if (glsl_type_is_scalar(type)) {
5055 return glsl_base_to_llvm_type(ctx, glsl_get_base_type(type));
5056 }
5057
5058 if (glsl_type_is_vector(type)) {
5059 return LLVMVectorType(
5060 glsl_base_to_llvm_type(ctx, glsl_get_base_type(type)),
5061 glsl_get_vector_elements(type));
5062 }
5063
5064 if (glsl_type_is_matrix(type)) {
5065 return LLVMArrayType(
5066 glsl_to_llvm_type(ctx, glsl_get_column_type(type)),
5067 glsl_get_matrix_columns(type));
5068 }
5069
5070 if (glsl_type_is_array(type)) {
5071 return LLVMArrayType(
5072 glsl_to_llvm_type(ctx, glsl_get_array_element(type)),
5073 glsl_get_length(type));
5074 }
5075
5076 assert(glsl_type_is_struct(type));
5077
5078 LLVMTypeRef member_types[glsl_get_length(type)];
5079
5080 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5081 member_types[i] =
5082 glsl_to_llvm_type(ctx,
5083 glsl_get_struct_field(type, i));
5084 }
5085
5086 return LLVMStructTypeInContext(ctx->context, member_types,
5087 glsl_get_length(type), false);
5088 }
5089
5090 static void
5091 setup_locals(struct nir_to_llvm_context *ctx,
5092 struct nir_function *func)
5093 {
5094 int i, j;
5095 ctx->num_locals = 0;
5096 nir_foreach_variable(variable, &func->impl->locals) {
5097 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5098 variable->data.driver_location = ctx->num_locals * 4;
5099 ctx->num_locals += attrib_count;
5100 }
5101 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5102 if (!ctx->locals)
5103 return;
5104
5105 for (i = 0; i < ctx->num_locals; i++) {
5106 for (j = 0; j < 4; j++) {
5107 ctx->locals[i * 4 + j] =
5108 si_build_alloca_undef(ctx, ctx->f32, "temp");
5109 }
5110 }
5111 }
5112
5113 static void
5114 setup_shared(struct nir_to_llvm_context *ctx,
5115 struct nir_shader *nir)
5116 {
5117 nir_foreach_variable(variable, &nir->shared) {
5118 LLVMValueRef shared =
5119 LLVMAddGlobalInAddressSpace(
5120 ctx->module, glsl_to_llvm_type(ctx, variable->type),
5121 variable->name ? variable->name : "",
5122 LOCAL_ADDR_SPACE);
5123 _mesa_hash_table_insert(ctx->vars, variable, shared);
5124 }
5125 }
5126
5127 static LLVMValueRef
5128 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
5129 {
5130 v = to_float(ctx, v);
5131 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
5132 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
5133 }
5134
5135
5136 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5137 LLVMValueRef src0, LLVMValueRef src1)
5138 {
5139 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5140 LLVMValueRef comp[2];
5141
5142 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5143 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5144 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5145 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5146 }
5147
5148 /* Initialize arguments for the shader export intrinsic */
5149 static void
5150 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5151 LLVMValueRef *values,
5152 unsigned target,
5153 struct ac_export_args *args)
5154 {
5155 /* Default is 0xf. Adjusted below depending on the format. */
5156 args->enabled_channels = 0xf;
5157
5158 /* Specify whether the EXEC mask represents the valid mask */
5159 args->valid_mask = 0;
5160
5161 /* Specify whether this is the last export */
5162 args->done = 0;
5163
5164 /* Specify the target we are exporting */
5165 args->target = target;
5166
5167 args->compr = false;
5168 args->out[0] = LLVMGetUndef(ctx->f32);
5169 args->out[1] = LLVMGetUndef(ctx->f32);
5170 args->out[2] = LLVMGetUndef(ctx->f32);
5171 args->out[3] = LLVMGetUndef(ctx->f32);
5172
5173 if (!values)
5174 return;
5175
5176 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5177 LLVMValueRef val[4];
5178 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5179 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5180 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5181
5182 switch(col_format) {
5183 case V_028714_SPI_SHADER_ZERO:
5184 args->enabled_channels = 0; /* writemask */
5185 args->target = V_008DFC_SQ_EXP_NULL;
5186 break;
5187
5188 case V_028714_SPI_SHADER_32_R:
5189 args->enabled_channels = 1;
5190 args->out[0] = values[0];
5191 break;
5192
5193 case V_028714_SPI_SHADER_32_GR:
5194 args->enabled_channels = 0x3;
5195 args->out[0] = values[0];
5196 args->out[1] = values[1];
5197 break;
5198
5199 case V_028714_SPI_SHADER_32_AR:
5200 args->enabled_channels = 0x9;
5201 args->out[0] = values[0];
5202 args->out[3] = values[3];
5203 break;
5204
5205 case V_028714_SPI_SHADER_FP16_ABGR:
5206 args->compr = 1;
5207
5208 for (unsigned chan = 0; chan < 2; chan++) {
5209 LLVMValueRef pack_args[2] = {
5210 values[2 * chan],
5211 values[2 * chan + 1]
5212 };
5213 LLVMValueRef packed;
5214
5215 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5216 args->out[chan] = packed;
5217 }
5218 break;
5219
5220 case V_028714_SPI_SHADER_UNORM16_ABGR:
5221 for (unsigned chan = 0; chan < 4; chan++) {
5222 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5223 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5224 LLVMConstReal(ctx->f32, 65535), "");
5225 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5226 LLVMConstReal(ctx->f32, 0.5), "");
5227 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5228 ctx->i32, "");
5229 }
5230
5231 args->compr = 1;
5232 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5233 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5234 break;
5235
5236 case V_028714_SPI_SHADER_SNORM16_ABGR:
5237 for (unsigned chan = 0; chan < 4; chan++) {
5238 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5239 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5240 LLVMConstReal(ctx->f32, 32767), "");
5241
5242 /* If positive, add 0.5, else add -0.5. */
5243 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5244 LLVMBuildSelect(ctx->builder,
5245 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5246 val[chan], ctx->f32zero, ""),
5247 LLVMConstReal(ctx->f32, 0.5),
5248 LLVMConstReal(ctx->f32, -0.5), ""), "");
5249 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5250 }
5251
5252 args->compr = 1;
5253 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5254 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5255 break;
5256
5257 case V_028714_SPI_SHADER_UINT16_ABGR: {
5258 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5259
5260 for (unsigned chan = 0; chan < 4; chan++) {
5261 val[chan] = to_integer(&ctx->ac, values[chan]);
5262 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
5263 }
5264
5265 args->compr = 1;
5266 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5267 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5268 break;
5269 }
5270
5271 case V_028714_SPI_SHADER_SINT16_ABGR: {
5272 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5273 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5274
5275 /* Clamp. */
5276 for (unsigned chan = 0; chan < 4; chan++) {
5277 val[chan] = to_integer(&ctx->ac, values[chan]);
5278 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
5279 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
5280 }
5281
5282 args->compr = 1;
5283 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5284 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5285 break;
5286 }
5287
5288 default:
5289 case V_028714_SPI_SHADER_32_ABGR:
5290 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5291 break;
5292 }
5293 } else
5294 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5295
5296 for (unsigned i = 0; i < 4; ++i)
5297 args->out[i] = to_float(&ctx->ac, args->out[i]);
5298 }
5299
5300 static void
5301 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5302 bool export_prim_id,
5303 struct ac_vs_output_info *outinfo)
5304 {
5305 uint32_t param_count = 0;
5306 unsigned target;
5307 unsigned pos_idx, num_pos_exports = 0;
5308 struct ac_export_args args, pos_args[4] = {};
5309 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5310 int i;
5311
5312 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5313 sizeof(outinfo->vs_output_param_offset));
5314
5315 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5316 LLVMValueRef slots[8];
5317 unsigned j;
5318
5319 if (outinfo->cull_dist_mask)
5320 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5321
5322 i = VARYING_SLOT_CLIP_DIST0;
5323 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5324 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5325 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5326
5327 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5328 slots[i] = LLVMGetUndef(ctx->f32);
5329
5330 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5331 target = V_008DFC_SQ_EXP_POS + 3;
5332 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5333 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5334 &args, sizeof(args));
5335 }
5336
5337 target = V_008DFC_SQ_EXP_POS + 2;
5338 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5339 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5340 &args, sizeof(args));
5341
5342 }
5343
5344 LLVMValueRef pos_values[4] = {ctx->f32zero, ctx->f32zero, ctx->f32zero, ctx->f32one};
5345 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
5346 for (unsigned j = 0; j < 4; j++)
5347 pos_values[j] = LLVMBuildLoad(ctx->builder,
5348 ctx->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_POS, j)], "");
5349 }
5350 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
5351
5352 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
5353 outinfo->writes_pointsize = true;
5354 psize_value = LLVMBuildLoad(ctx->builder,
5355 ctx->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_PSIZ, 0)], "");
5356 }
5357
5358 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
5359 outinfo->writes_layer = true;
5360 layer_value = LLVMBuildLoad(ctx->builder,
5361 ctx->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)], "");
5362 }
5363
5364 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
5365 outinfo->writes_viewport_index = true;
5366 viewport_index_value = LLVMBuildLoad(ctx->builder,
5367 ctx->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_VIEWPORT, 0)], "");
5368 }
5369
5370 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5371 (outinfo->writes_layer == true ? 4 : 0) |
5372 (outinfo->writes_viewport_index == true ? 8 : 0));
5373 if (mask) {
5374 pos_args[1].enabled_channels = mask;
5375 pos_args[1].valid_mask = 0;
5376 pos_args[1].done = 0;
5377 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5378 pos_args[1].compr = 0;
5379 pos_args[1].out[0] = ctx->f32zero; /* X */
5380 pos_args[1].out[1] = ctx->f32zero; /* Y */
5381 pos_args[1].out[2] = ctx->f32zero; /* Z */
5382 pos_args[1].out[3] = ctx->f32zero; /* W */
5383
5384 if (outinfo->writes_pointsize == true)
5385 pos_args[1].out[0] = psize_value;
5386 if (outinfo->writes_layer == true)
5387 pos_args[1].out[2] = layer_value;
5388 if (outinfo->writes_viewport_index == true)
5389 pos_args[1].out[3] = viewport_index_value;
5390 }
5391 for (i = 0; i < 4; i++) {
5392 if (pos_args[i].out[0])
5393 num_pos_exports++;
5394 }
5395
5396 pos_idx = 0;
5397 for (i = 0; i < 4; i++) {
5398 if (!pos_args[i].out[0])
5399 continue;
5400
5401 /* Specify the target we are exporting */
5402 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5403 if (pos_idx == num_pos_exports)
5404 pos_args[i].done = 1;
5405 ac_build_export(&ctx->ac, &pos_args[i]);
5406 }
5407
5408 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5409 LLVMValueRef values[4];
5410 if (!(ctx->output_mask & (1ull << i)))
5411 continue;
5412
5413 for (unsigned j = 0; j < 4; j++)
5414 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5415 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5416
5417 if (i == VARYING_SLOT_LAYER) {
5418 target = V_008DFC_SQ_EXP_PARAM + param_count;
5419 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5420 param_count++;
5421 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5422 target = V_008DFC_SQ_EXP_PARAM + param_count;
5423 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5424 param_count++;
5425 } else if (i >= VARYING_SLOT_VAR0) {
5426 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5427 target = V_008DFC_SQ_EXP_PARAM + param_count;
5428 outinfo->vs_output_param_offset[i] = param_count;
5429 param_count++;
5430 } else
5431 continue;
5432
5433 si_llvm_init_export_args(ctx, values, target, &args);
5434
5435 if (target >= V_008DFC_SQ_EXP_POS &&
5436 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5437 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5438 &args, sizeof(args));
5439 } else {
5440 ac_build_export(&ctx->ac, &args);
5441 }
5442 }
5443
5444 if (export_prim_id) {
5445 LLVMValueRef values[4];
5446 target = V_008DFC_SQ_EXP_PARAM + param_count;
5447 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5448 param_count++;
5449
5450 values[0] = ctx->vs_prim_id;
5451 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5452 ctx->shader_info->vs.vgpr_comp_cnt);
5453 for (unsigned j = 1; j < 4; j++)
5454 values[j] = ctx->f32zero;
5455 si_llvm_init_export_args(ctx, values, target, &args);
5456 ac_build_export(&ctx->ac, &args);
5457 outinfo->export_prim_id = true;
5458 }
5459
5460 outinfo->pos_exports = num_pos_exports;
5461 outinfo->param_exports = param_count;
5462 }
5463
5464 static void
5465 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5466 struct ac_es_output_info *outinfo)
5467 {
5468 int j;
5469 uint64_t max_output_written = 0;
5470 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5471 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5472 int param_index;
5473 int length = 4;
5474
5475 if (!(ctx->output_mask & (1ull << i)))
5476 continue;
5477
5478 if (i == VARYING_SLOT_CLIP_DIST0)
5479 length = ctx->num_output_clips + ctx->num_output_culls;
5480
5481 param_index = shader_io_get_unique_index(i);
5482
5483 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5484
5485 for (j = 0; j < length; j++) {
5486 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5487 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5488
5489 ac_build_buffer_store_dword(&ctx->ac,
5490 ctx->esgs_ring,
5491 out_val, 1,
5492 NULL, ctx->es2gs_offset,
5493 (4 * param_index + j) * 4,
5494 1, 1, true, true);
5495 }
5496 }
5497 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5498 }
5499
5500 static void
5501 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5502 {
5503 LLVMValueRef vertex_id = ctx->rel_auto_id;
5504 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5505 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5506 vertex_dw_stride, "");
5507
5508 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5509 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5510 int length = 4;
5511
5512 if (!(ctx->output_mask & (1ull << i)))
5513 continue;
5514
5515 if (i == VARYING_SLOT_CLIP_DIST0)
5516 length = ctx->num_output_clips + ctx->num_output_culls;
5517 int param = shader_io_get_unique_index(i);
5518 mark_tess_output(ctx, false, param);
5519 if (length > 4)
5520 mark_tess_output(ctx, false, param + 1);
5521 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5522 LLVMConstInt(ctx->i32, param * 4, false),
5523 "");
5524 for (unsigned j = 0; j < length; j++) {
5525 lds_store(ctx, dw_addr,
5526 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5527 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5528 }
5529 }
5530 }
5531
5532 struct ac_build_if_state
5533 {
5534 struct nir_to_llvm_context *ctx;
5535 LLVMValueRef condition;
5536 LLVMBasicBlockRef entry_block;
5537 LLVMBasicBlockRef true_block;
5538 LLVMBasicBlockRef false_block;
5539 LLVMBasicBlockRef merge_block;
5540 };
5541
5542 static LLVMBasicBlockRef
5543 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5544 {
5545 LLVMBasicBlockRef current_block;
5546 LLVMBasicBlockRef next_block;
5547 LLVMBasicBlockRef new_block;
5548
5549 /* get current basic block */
5550 current_block = LLVMGetInsertBlock(ctx->builder);
5551
5552 /* chqeck if there's another block after this one */
5553 next_block = LLVMGetNextBasicBlock(current_block);
5554 if (next_block) {
5555 /* insert the new block before the next block */
5556 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5557 }
5558 else {
5559 /* append new block after current block */
5560 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5561 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5562 }
5563 return new_block;
5564 }
5565
5566 static void
5567 ac_nir_build_if(struct ac_build_if_state *ifthen,
5568 struct nir_to_llvm_context *ctx,
5569 LLVMValueRef condition)
5570 {
5571 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5572
5573 memset(ifthen, 0, sizeof *ifthen);
5574 ifthen->ctx = ctx;
5575 ifthen->condition = condition;
5576 ifthen->entry_block = block;
5577
5578 /* create endif/merge basic block for the phi functions */
5579 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5580
5581 /* create/insert true_block before merge_block */
5582 ifthen->true_block =
5583 LLVMInsertBasicBlockInContext(ctx->context,
5584 ifthen->merge_block,
5585 "if-true-block");
5586
5587 /* successive code goes into the true block */
5588 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5589 }
5590
5591 /**
5592 * End a conditional.
5593 */
5594 static void
5595 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5596 {
5597 LLVMBuilderRef builder = ifthen->ctx->builder;
5598
5599 /* Insert branch to the merge block from current block */
5600 LLVMBuildBr(builder, ifthen->merge_block);
5601
5602 /*
5603 * Now patch in the various branch instructions.
5604 */
5605
5606 /* Insert the conditional branch instruction at the end of entry_block */
5607 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5608 if (ifthen->false_block) {
5609 /* we have an else clause */
5610 LLVMBuildCondBr(builder, ifthen->condition,
5611 ifthen->true_block, ifthen->false_block);
5612 }
5613 else {
5614 /* no else clause */
5615 LLVMBuildCondBr(builder, ifthen->condition,
5616 ifthen->true_block, ifthen->merge_block);
5617 }
5618
5619 /* Resume building code at end of the ifthen->merge_block */
5620 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5621 }
5622
5623 static void
5624 write_tess_factors(struct nir_to_llvm_context *ctx)
5625 {
5626 unsigned stride, outer_comps, inner_comps;
5627 struct ac_build_if_state if_ctx, inner_if_ctx;
5628 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5629 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5630 unsigned tess_inner_index, tess_outer_index;
5631 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5632 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5633 int i;
5634 emit_barrier(ctx);
5635
5636 switch (ctx->options->key.tcs.primitive_mode) {
5637 case GL_ISOLINES:
5638 stride = 2;
5639 outer_comps = 2;
5640 inner_comps = 0;
5641 break;
5642 case GL_TRIANGLES:
5643 stride = 4;
5644 outer_comps = 3;
5645 inner_comps = 1;
5646 break;
5647 case GL_QUADS:
5648 stride = 6;
5649 outer_comps = 4;
5650 inner_comps = 2;
5651 break;
5652 default:
5653 return;
5654 }
5655
5656 ac_nir_build_if(&if_ctx, ctx,
5657 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5658 invocation_id, ctx->i32zero, ""));
5659
5660 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5661 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5662
5663 mark_tess_output(ctx, true, tess_inner_index);
5664 mark_tess_output(ctx, true, tess_outer_index);
5665 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5666 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5667 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5668 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5669 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5670
5671 for (i = 0; i < 4; i++) {
5672 inner[i] = LLVMGetUndef(ctx->i32);
5673 outer[i] = LLVMGetUndef(ctx->i32);
5674 }
5675
5676 // LINES reverseal
5677 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5678 outer[0] = out[1] = lds_load(ctx, lds_outer);
5679 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5680 LLVMConstInt(ctx->i32, 1, false), "");
5681 outer[1] = out[0] = lds_load(ctx, lds_outer);
5682 } else {
5683 for (i = 0; i < outer_comps; i++) {
5684 outer[i] = out[i] =
5685 lds_load(ctx, lds_outer);
5686 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5687 LLVMConstInt(ctx->i32, 1, false), "");
5688 }
5689 for (i = 0; i < inner_comps; i++) {
5690 inner[i] = out[outer_comps+i] =
5691 lds_load(ctx, lds_inner);
5692 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5693 LLVMConstInt(ctx->i32, 1, false), "");
5694 }
5695 }
5696
5697 /* Convert the outputs to vectors for stores. */
5698 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5699 vec1 = NULL;
5700
5701 if (stride > 4)
5702 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5703
5704
5705 buffer = ctx->hs_ring_tess_factor;
5706 tf_base = ctx->tess_factor_offset;
5707 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5708 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5709
5710 ac_nir_build_if(&inner_if_ctx, ctx,
5711 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5712 rel_patch_id, ctx->i32zero, ""));
5713
5714 /* Store the dynamic HS control word. */
5715 ac_build_buffer_store_dword(&ctx->ac, buffer,
5716 LLVMConstInt(ctx->i32, 0x80000000, false),
5717 1, ctx->i32zero, tf_base,
5718 0, 1, 0, true, false);
5719 ac_nir_build_endif(&inner_if_ctx);
5720
5721 /* Store the tessellation factors. */
5722 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5723 MIN2(stride, 4), byteoffset, tf_base,
5724 4, 1, 0, true, false);
5725 if (vec1)
5726 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5727 stride - 4, byteoffset, tf_base,
5728 20, 1, 0, true, false);
5729
5730 //TODO store to offchip for TES to read - only if TES reads them
5731 if (1) {
5732 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5733 LLVMValueRef tf_inner_offset;
5734 unsigned param_outer, param_inner;
5735
5736 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5737 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5738 LLVMConstInt(ctx->i32, param_outer, 0));
5739
5740 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5741 util_next_power_of_two(outer_comps));
5742
5743 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5744 outer_comps, tf_outer_offset,
5745 ctx->oc_lds, 0, 1, 0, true, false);
5746 if (inner_comps) {
5747 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5748 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5749 LLVMConstInt(ctx->i32, param_inner, 0));
5750
5751 inner_vec = inner_comps == 1 ? inner[0] :
5752 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5753 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5754 inner_comps, tf_inner_offset,
5755 ctx->oc_lds, 0, 1, 0, true, false);
5756 }
5757 }
5758 ac_nir_build_endif(&if_ctx);
5759 }
5760
5761 static void
5762 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5763 {
5764 write_tess_factors(ctx);
5765 }
5766
5767 static bool
5768 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5769 LLVMValueRef *color, unsigned param, bool is_last,
5770 struct ac_export_args *args)
5771 {
5772 /* Export */
5773 si_llvm_init_export_args(ctx, color, param,
5774 args);
5775
5776 if (is_last) {
5777 args->valid_mask = 1; /* whether the EXEC mask is valid */
5778 args->done = 1; /* DONE bit */
5779 } else if (!args->enabled_channels)
5780 return false; /* unnecessary NULL export */
5781
5782 return true;
5783 }
5784
5785 static void
5786 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5787 LLVMValueRef depth, LLVMValueRef stencil,
5788 LLVMValueRef samplemask)
5789 {
5790 struct ac_export_args args;
5791
5792 args.enabled_channels = 0;
5793 args.valid_mask = 1;
5794 args.done = 1;
5795 args.target = V_008DFC_SQ_EXP_MRTZ;
5796 args.compr = false;
5797
5798 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5799 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5800 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5801 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5802
5803 if (depth) {
5804 args.out[0] = depth;
5805 args.enabled_channels |= 0x1;
5806 }
5807
5808 if (stencil) {
5809 args.out[1] = stencil;
5810 args.enabled_channels |= 0x2;
5811 }
5812
5813 if (samplemask) {
5814 args.out[2] = samplemask;
5815 args.enabled_channels |= 0x4;
5816 }
5817
5818 /* SI (except OLAND and HAINAN) has a bug that it only looks
5819 * at the X writemask component. */
5820 if (ctx->options->chip_class == SI &&
5821 ctx->options->family != CHIP_OLAND &&
5822 ctx->options->family != CHIP_HAINAN)
5823 args.enabled_channels |= 0x1;
5824
5825 ac_build_export(&ctx->ac, &args);
5826 }
5827
5828 static void
5829 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5830 {
5831 unsigned index = 0;
5832 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5833 struct ac_export_args color_args[8];
5834
5835 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5836 LLVMValueRef values[4];
5837
5838 if (!(ctx->output_mask & (1ull << i)))
5839 continue;
5840
5841 if (i == FRAG_RESULT_DEPTH) {
5842 ctx->shader_info->fs.writes_z = true;
5843 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5844 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5845 } else if (i == FRAG_RESULT_STENCIL) {
5846 ctx->shader_info->fs.writes_stencil = true;
5847 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5848 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5849 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5850 ctx->shader_info->fs.writes_sample_mask = true;
5851 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5852 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5853 } else {
5854 bool last = false;
5855 for (unsigned j = 0; j < 4; j++)
5856 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5857 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5858
5859 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5860 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5861
5862 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5863 if (ret)
5864 index++;
5865 }
5866 }
5867
5868 for (unsigned i = 0; i < index; i++)
5869 ac_build_export(&ctx->ac, &color_args[i]);
5870 if (depth || stencil || samplemask)
5871 si_export_mrt_z(ctx, depth, stencil, samplemask);
5872 else if (!index) {
5873 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5874 ac_build_export(&ctx->ac, &color_args[0]);
5875 }
5876
5877 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5878 }
5879
5880 static void
5881 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5882 {
5883 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5884 }
5885
5886 static void
5887 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5888 {
5889 switch (ctx->stage) {
5890 case MESA_SHADER_VERTEX:
5891 if (ctx->options->key.vs.as_ls)
5892 handle_ls_outputs_post(ctx);
5893 else if (ctx->options->key.vs.as_es)
5894 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5895 else
5896 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
5897 &ctx->shader_info->vs.outinfo);
5898 break;
5899 case MESA_SHADER_FRAGMENT:
5900 handle_fs_outputs_post(ctx);
5901 break;
5902 case MESA_SHADER_GEOMETRY:
5903 emit_gs_epilogue(ctx);
5904 break;
5905 case MESA_SHADER_TESS_CTRL:
5906 handle_tcs_outputs_post(ctx);
5907 break;
5908 case MESA_SHADER_TESS_EVAL:
5909 if (ctx->options->key.tes.as_es)
5910 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5911 else
5912 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
5913 &ctx->shader_info->tes.outinfo);
5914 break;
5915 default:
5916 break;
5917 }
5918 }
5919
5920 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5921 {
5922 LLVMPassManagerRef passmgr;
5923 /* Create the pass manager */
5924 passmgr = LLVMCreateFunctionPassManagerForModule(
5925 ctx->module);
5926
5927 /* This pass should eliminate all the load and store instructions */
5928 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5929
5930 /* Add some optimization passes */
5931 LLVMAddScalarReplAggregatesPass(passmgr);
5932 LLVMAddLICMPass(passmgr);
5933 LLVMAddAggressiveDCEPass(passmgr);
5934 LLVMAddCFGSimplificationPass(passmgr);
5935 LLVMAddInstructionCombiningPass(passmgr);
5936
5937 /* Run the pass */
5938 LLVMInitializeFunctionPassManager(passmgr);
5939 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5940 LLVMFinalizeFunctionPassManager(passmgr);
5941
5942 LLVMDisposeBuilder(ctx->builder);
5943 LLVMDisposePassManager(passmgr);
5944 }
5945
5946 static void
5947 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
5948 {
5949 struct ac_vs_output_info *outinfo;
5950
5951 switch (ctx->stage) {
5952 case MESA_SHADER_FRAGMENT:
5953 case MESA_SHADER_COMPUTE:
5954 case MESA_SHADER_TESS_CTRL:
5955 case MESA_SHADER_GEOMETRY:
5956 return;
5957 case MESA_SHADER_VERTEX:
5958 if (ctx->options->key.vs.as_ls ||
5959 ctx->options->key.vs.as_es)
5960 return;
5961 outinfo = &ctx->shader_info->vs.outinfo;
5962 break;
5963 case MESA_SHADER_TESS_EVAL:
5964 if (ctx->options->key.vs.as_es)
5965 return;
5966 outinfo = &ctx->shader_info->tes.outinfo;
5967 break;
5968 default:
5969 unreachable("Unhandled shader type");
5970 }
5971
5972 ac_optimize_vs_outputs(&ctx->ac,
5973 ctx->main_function,
5974 outinfo->vs_output_param_offset,
5975 VARYING_SLOT_MAX,
5976 &outinfo->param_exports);
5977 }
5978
5979 static void
5980 ac_setup_rings(struct nir_to_llvm_context *ctx)
5981 {
5982 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5983 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5984 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5985 }
5986
5987 if (ctx->is_gs_copy_shader) {
5988 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5989 }
5990 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5991 LLVMValueRef tmp;
5992 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5993 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5994
5995 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5996
5997 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5998 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5999 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
6000 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
6001 }
6002
6003 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6004 ctx->stage == MESA_SHADER_TESS_EVAL) {
6005 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
6006 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
6007 }
6008 }
6009
6010 static unsigned
6011 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6012 const struct nir_shader *nir)
6013 {
6014 switch (nir->stage) {
6015 case MESA_SHADER_TESS_CTRL:
6016 return chip_class >= CIK ? 128 : 64;
6017 case MESA_SHADER_GEOMETRY:
6018 return 64;
6019 case MESA_SHADER_COMPUTE:
6020 break;
6021 default:
6022 return 0;
6023 }
6024
6025 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6026 nir->info.cs.local_size[1] *
6027 nir->info.cs.local_size[2];
6028 return max_workgroup_size;
6029 }
6030
6031 static
6032 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6033 struct nir_shader *nir,
6034 struct ac_shader_variant_info *shader_info,
6035 const struct ac_nir_compiler_options *options)
6036 {
6037 struct nir_to_llvm_context ctx = {0};
6038 struct nir_function *func;
6039 unsigned i;
6040 ctx.options = options;
6041 ctx.shader_info = shader_info;
6042 ctx.context = LLVMContextCreate();
6043 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6044
6045 ac_llvm_context_init(&ctx.ac, ctx.context);
6046 ctx.ac.module = ctx.module;
6047
6048 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
6049
6050 memset(shader_info, 0, sizeof(*shader_info));
6051
6052 ac_nir_shader_info_pass(nir, options, &shader_info->info);
6053
6054 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6055
6056 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6057 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6058 LLVMSetDataLayout(ctx.module, data_layout_str);
6059 LLVMDisposeTargetData(data_layout);
6060 LLVMDisposeMessage(data_layout_str);
6061
6062 setup_types(&ctx);
6063
6064 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6065 ctx.ac.builder = ctx.builder;
6066 ctx.stage = nir->stage;
6067 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
6068
6069 for (i = 0; i < AC_UD_MAX_SETS; i++)
6070 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6071 for (i = 0; i < AC_UD_MAX_UD; i++)
6072 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6073
6074 create_function(&ctx);
6075
6076 if (nir->stage == MESA_SHADER_GEOMETRY) {
6077 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
6078
6079 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
6080 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
6081 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
6082 }
6083
6084 ac_setup_rings(&ctx);
6085
6086 nir_foreach_variable(variable, &nir->inputs)
6087 handle_shader_input_decl(&ctx, variable);
6088
6089 if (nir->stage == MESA_SHADER_FRAGMENT)
6090 handle_fs_inputs_pre(&ctx, nir);
6091
6092 ctx.num_output_clips = nir->info.clip_distance_array_size;
6093 ctx.num_output_culls = nir->info.cull_distance_array_size;
6094
6095 nir_foreach_variable(variable, &nir->outputs)
6096 handle_shader_output_decl(&ctx, variable);
6097
6098 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6099 _mesa_key_pointer_equal);
6100 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6101 _mesa_key_pointer_equal);
6102 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6103 _mesa_key_pointer_equal);
6104
6105 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6106
6107 setup_locals(&ctx, func);
6108
6109 if (nir->stage == MESA_SHADER_COMPUTE)
6110 setup_shared(&ctx, nir);
6111
6112 visit_cf_list(&ctx, &func->impl->body);
6113 phi_post_pass(&ctx);
6114
6115 handle_shader_outputs_post(&ctx);
6116 LLVMBuildRetVoid(ctx.builder);
6117
6118 ac_llvm_finalize_module(&ctx);
6119
6120 ac_nir_eliminate_const_vs_outputs(&ctx);
6121 free(ctx.locals);
6122 ralloc_free(ctx.defs);
6123 ralloc_free(ctx.phis);
6124 ralloc_free(ctx.vars);
6125
6126 if (nir->stage == MESA_SHADER_GEOMETRY) {
6127 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6128 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6129 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6130 nir->info.gs.vertices_out;
6131 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6132 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6133 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6134 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6135 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6136 }
6137
6138 return ctx.module;
6139 }
6140
6141 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6142 {
6143 unsigned *retval = (unsigned *)context;
6144 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6145 char *description = LLVMGetDiagInfoDescription(di);
6146
6147 if (severity == LLVMDSError) {
6148 *retval = 1;
6149 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6150 description);
6151 }
6152
6153 LLVMDisposeMessage(description);
6154 }
6155
6156 static unsigned ac_llvm_compile(LLVMModuleRef M,
6157 struct ac_shader_binary *binary,
6158 LLVMTargetMachineRef tm)
6159 {
6160 unsigned retval = 0;
6161 char *err;
6162 LLVMContextRef llvm_ctx;
6163 LLVMMemoryBufferRef out_buffer;
6164 unsigned buffer_size;
6165 const char *buffer_data;
6166 LLVMBool mem_err;
6167
6168 /* Setup Diagnostic Handler*/
6169 llvm_ctx = LLVMGetModuleContext(M);
6170
6171 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6172 &retval);
6173
6174 /* Compile IR*/
6175 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6176 &err, &out_buffer);
6177
6178 /* Process Errors/Warnings */
6179 if (mem_err) {
6180 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6181 free(err);
6182 retval = 1;
6183 goto out;
6184 }
6185
6186 /* Extract Shader Code*/
6187 buffer_size = LLVMGetBufferSize(out_buffer);
6188 buffer_data = LLVMGetBufferStart(out_buffer);
6189
6190 ac_elf_read(buffer_data, buffer_size, binary);
6191
6192 /* Clean up */
6193 LLVMDisposeMemoryBuffer(out_buffer);
6194
6195 out:
6196 return retval;
6197 }
6198
6199 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6200 LLVMModuleRef llvm_module,
6201 struct ac_shader_binary *binary,
6202 struct ac_shader_config *config,
6203 struct ac_shader_variant_info *shader_info,
6204 gl_shader_stage stage,
6205 bool dump_shader, bool supports_spill)
6206 {
6207 if (dump_shader)
6208 ac_dump_module(llvm_module);
6209
6210 memset(binary, 0, sizeof(*binary));
6211 int v = ac_llvm_compile(llvm_module, binary, tm);
6212 if (v) {
6213 fprintf(stderr, "compile failed\n");
6214 }
6215
6216 if (dump_shader)
6217 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6218
6219 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6220
6221 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6222 LLVMDisposeModule(llvm_module);
6223 LLVMContextDispose(ctx);
6224
6225 if (stage == MESA_SHADER_FRAGMENT) {
6226 shader_info->num_input_vgprs = 0;
6227 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6228 shader_info->num_input_vgprs += 2;
6229 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6230 shader_info->num_input_vgprs += 2;
6231 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6232 shader_info->num_input_vgprs += 2;
6233 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6234 shader_info->num_input_vgprs += 3;
6235 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6236 shader_info->num_input_vgprs += 2;
6237 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6238 shader_info->num_input_vgprs += 2;
6239 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6240 shader_info->num_input_vgprs += 2;
6241 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6242 shader_info->num_input_vgprs += 1;
6243 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6244 shader_info->num_input_vgprs += 1;
6245 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6246 shader_info->num_input_vgprs += 1;
6247 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6248 shader_info->num_input_vgprs += 1;
6249 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6250 shader_info->num_input_vgprs += 1;
6251 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6252 shader_info->num_input_vgprs += 1;
6253 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6254 shader_info->num_input_vgprs += 1;
6255 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6256 shader_info->num_input_vgprs += 1;
6257 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6258 shader_info->num_input_vgprs += 1;
6259 }
6260 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6261
6262 /* +3 for scratch wave offset and VCC */
6263 config->num_sgprs = MAX2(config->num_sgprs,
6264 shader_info->num_input_sgprs + 3);
6265 }
6266
6267 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6268 struct ac_shader_binary *binary,
6269 struct ac_shader_config *config,
6270 struct ac_shader_variant_info *shader_info,
6271 struct nir_shader *nir,
6272 const struct ac_nir_compiler_options *options,
6273 bool dump_shader)
6274 {
6275
6276 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6277 options);
6278
6279 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6280 switch (nir->stage) {
6281 case MESA_SHADER_COMPUTE:
6282 for (int i = 0; i < 3; ++i)
6283 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6284 break;
6285 case MESA_SHADER_FRAGMENT:
6286 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6287 break;
6288 case MESA_SHADER_GEOMETRY:
6289 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6290 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6291 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6292 shader_info->gs.invocations = nir->info.gs.invocations;
6293 break;
6294 case MESA_SHADER_TESS_EVAL:
6295 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6296 shader_info->tes.spacing = nir->info.tess.spacing;
6297 shader_info->tes.ccw = nir->info.tess.ccw;
6298 shader_info->tes.point_mode = nir->info.tess.point_mode;
6299 shader_info->tes.as_es = options->key.tes.as_es;
6300 break;
6301 case MESA_SHADER_TESS_CTRL:
6302 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6303 break;
6304 case MESA_SHADER_VERTEX:
6305 shader_info->vs.as_es = options->key.vs.as_es;
6306 shader_info->vs.as_ls = options->key.vs.as_ls;
6307 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6308 if (options->key.vs.as_ls)
6309 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6310 break;
6311 default:
6312 break;
6313 }
6314 }
6315
6316 static void
6317 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6318 {
6319 LLVMValueRef args[9];
6320 args[0] = ctx->gsvs_ring;
6321 args[1] = LLVMBuildMul(ctx->builder, ctx->abi.vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6322 args[3] = ctx->i32zero;
6323 args[4] = ctx->i32one; /* OFFEN */
6324 args[5] = ctx->i32zero; /* IDXEN */
6325 args[6] = ctx->i32one; /* GLC */
6326 args[7] = ctx->i32one; /* SLC */
6327 args[8] = ctx->i32zero; /* TFE */
6328
6329 int idx = 0;
6330
6331 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6332 int length = 4;
6333 int slot = idx;
6334 int slot_inc = 1;
6335 if (!(ctx->output_mask & (1ull << i)))
6336 continue;
6337
6338 if (i == VARYING_SLOT_CLIP_DIST0) {
6339 /* unpack clip and cull from a single set of slots */
6340 length = ctx->num_output_clips + ctx->num_output_culls;
6341 if (length > 4)
6342 slot_inc = 2;
6343 }
6344
6345 for (unsigned j = 0; j < length; j++) {
6346 LLVMValueRef value;
6347 args[2] = LLVMConstInt(ctx->i32,
6348 (slot * 4 + j) *
6349 ctx->gs_max_out_vertices * 16 * 4, false);
6350
6351 value = ac_build_intrinsic(&ctx->ac,
6352 "llvm.SI.buffer.load.dword.i32.i32",
6353 ctx->i32, args, 9,
6354 AC_FUNC_ATTR_READONLY |
6355 AC_FUNC_ATTR_LEGACY);
6356
6357 LLVMBuildStore(ctx->builder,
6358 to_float(&ctx->ac, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6359 }
6360 idx += slot_inc;
6361 }
6362 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6363 }
6364
6365 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6366 struct nir_shader *geom_shader,
6367 struct ac_shader_binary *binary,
6368 struct ac_shader_config *config,
6369 struct ac_shader_variant_info *shader_info,
6370 const struct ac_nir_compiler_options *options,
6371 bool dump_shader)
6372 {
6373 struct nir_to_llvm_context ctx = {0};
6374 ctx.context = LLVMContextCreate();
6375 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6376 ctx.options = options;
6377 ctx.shader_info = shader_info;
6378
6379 ac_llvm_context_init(&ctx.ac, ctx.context);
6380 ctx.ac.module = ctx.module;
6381
6382 ctx.is_gs_copy_shader = true;
6383 LLVMSetTarget(ctx.module, "amdgcn--");
6384 setup_types(&ctx);
6385
6386 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6387 ctx.ac.builder = ctx.builder;
6388 ctx.stage = MESA_SHADER_VERTEX;
6389
6390 create_function(&ctx);
6391
6392 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6393 ac_setup_rings(&ctx);
6394
6395 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6396 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6397
6398 nir_foreach_variable(variable, &geom_shader->outputs)
6399 handle_shader_output_decl(&ctx, variable);
6400
6401 ac_gs_copy_shader_emit(&ctx);
6402
6403 LLVMBuildRetVoid(ctx.builder);
6404
6405 ac_llvm_finalize_module(&ctx);
6406
6407 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6408 MESA_SHADER_VERTEX,
6409 dump_shader, options->supports_spill);
6410 }