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radv/ac: use shader imsb emission code.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33
34 enum radeon_llvm_calling_convention {
35 RADEON_LLVM_AMDGPU_VS = 87,
36 RADEON_LLVM_AMDGPU_GS = 88,
37 RADEON_LLVM_AMDGPU_PS = 89,
38 RADEON_LLVM_AMDGPU_CS = 90,
39 };
40
41 #define CONST_ADDR_SPACE 2
42 #define LOCAL_ADDR_SPACE 3
43
44 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
46
47 enum desc_type {
48 DESC_IMAGE,
49 DESC_FMASK,
50 DESC_SAMPLER,
51 DESC_BUFFER,
52 };
53
54 struct nir_to_llvm_context {
55 struct ac_llvm_context ac;
56 const struct ac_nir_compiler_options *options;
57 struct ac_shader_variant_info *shader_info;
58
59 LLVMContextRef context;
60 LLVMModuleRef module;
61 LLVMBuilderRef builder;
62 LLVMValueRef main_function;
63
64 struct hash_table *defs;
65 struct hash_table *phis;
66
67 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
68 LLVMValueRef ring_offsets;
69 LLVMValueRef push_constants;
70 LLVMValueRef num_work_groups;
71 LLVMValueRef workgroup_ids;
72 LLVMValueRef local_invocation_ids;
73 LLVMValueRef tg_size;
74
75 LLVMValueRef vertex_buffers;
76 LLVMValueRef base_vertex;
77 LLVMValueRef start_instance;
78 LLVMValueRef draw_index;
79 LLVMValueRef vertex_id;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef instance_id;
83
84 LLVMValueRef es2gs_offset;
85
86 LLVMValueRef gsvs_ring_stride;
87 LLVMValueRef gsvs_num_entries;
88 LLVMValueRef gs2vs_offset;
89 LLVMValueRef gs_wave_id;
90 LLVMValueRef gs_vtx_offset[6];
91 LLVMValueRef gs_prim_id, gs_invocation_id;
92
93 LLVMValueRef esgs_ring;
94 LLVMValueRef gsvs_ring;
95
96 LLVMValueRef prim_mask;
97 LLVMValueRef sample_positions;
98 LLVMValueRef persp_sample, persp_center, persp_centroid;
99 LLVMValueRef linear_sample, linear_center, linear_centroid;
100 LLVMValueRef front_face;
101 LLVMValueRef ancillary;
102 LLVMValueRef frag_pos[4];
103
104 LLVMBasicBlockRef continue_block;
105 LLVMBasicBlockRef break_block;
106
107 LLVMTypeRef i1;
108 LLVMTypeRef i8;
109 LLVMTypeRef i16;
110 LLVMTypeRef i32;
111 LLVMTypeRef i64;
112 LLVMTypeRef v2i32;
113 LLVMTypeRef v3i32;
114 LLVMTypeRef v4i32;
115 LLVMTypeRef v8i32;
116 LLVMTypeRef f64;
117 LLVMTypeRef f32;
118 LLVMTypeRef f16;
119 LLVMTypeRef v2f32;
120 LLVMTypeRef v4f32;
121 LLVMTypeRef v16i8;
122 LLVMTypeRef voidt;
123
124 LLVMValueRef i32zero;
125 LLVMValueRef i32one;
126 LLVMValueRef f32zero;
127 LLVMValueRef f32one;
128 LLVMValueRef v4f32empty;
129
130 unsigned uniform_md_kind;
131 LLVMValueRef empty_md;
132 gl_shader_stage stage;
133
134 LLVMValueRef lds;
135 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
136 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
137
138 LLVMValueRef shared_memory;
139 uint64_t input_mask;
140 uint64_t output_mask;
141 int num_locals;
142 LLVMValueRef *locals;
143 bool has_ddxy;
144 unsigned num_clips;
145 unsigned num_culls;
146
147 bool has_ds_bpermute;
148
149 bool is_gs_copy_shader;
150 LLVMValueRef gs_next_vertex;
151 unsigned gs_max_out_vertices;
152 };
153
154 struct ac_tex_info {
155 LLVMValueRef args[12];
156 int arg_count;
157 LLVMTypeRef dst_type;
158 bool has_offset;
159 };
160
161 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
162 nir_deref_var *deref,
163 enum desc_type desc_type);
164 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
165 {
166 return (index * 4) + chan;
167 }
168
169 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
170 {
171 if (slot == VARYING_SLOT_POS)
172 return 0;
173 if (slot == VARYING_SLOT_PSIZ)
174 return 1;
175 if (slot == VARYING_SLOT_CLIP_DIST0)
176 return 2;
177 if (slot == VARYING_SLOT_CLIP_DIST1)
178 return 3;
179 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
180 return 4 + (slot - VARYING_SLOT_VAR0);
181 unreachable("illegal slot in get unique index\n");
182 }
183
184 static unsigned llvm_get_type_size(LLVMTypeRef type)
185 {
186 LLVMTypeKind kind = LLVMGetTypeKind(type);
187
188 switch (kind) {
189 case LLVMIntegerTypeKind:
190 return LLVMGetIntTypeWidth(type) / 8;
191 case LLVMFloatTypeKind:
192 return 4;
193 case LLVMPointerTypeKind:
194 return 8;
195 case LLVMVectorTypeKind:
196 return LLVMGetVectorSize(type) *
197 llvm_get_type_size(LLVMGetElementType(type));
198 default:
199 assert(0);
200 return 0;
201 }
202 }
203
204 static void set_llvm_calling_convention(LLVMValueRef func,
205 gl_shader_stage stage)
206 {
207 enum radeon_llvm_calling_convention calling_conv;
208
209 switch (stage) {
210 case MESA_SHADER_VERTEX:
211 case MESA_SHADER_TESS_CTRL:
212 case MESA_SHADER_TESS_EVAL:
213 calling_conv = RADEON_LLVM_AMDGPU_VS;
214 break;
215 case MESA_SHADER_GEOMETRY:
216 calling_conv = RADEON_LLVM_AMDGPU_GS;
217 break;
218 case MESA_SHADER_FRAGMENT:
219 calling_conv = RADEON_LLVM_AMDGPU_PS;
220 break;
221 case MESA_SHADER_COMPUTE:
222 calling_conv = RADEON_LLVM_AMDGPU_CS;
223 break;
224 default:
225 unreachable("Unhandle shader type");
226 }
227
228 LLVMSetFunctionCallConv(func, calling_conv);
229 }
230
231 static LLVMValueRef
232 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
233 LLVMBuilderRef builder, LLVMTypeRef *return_types,
234 unsigned num_return_elems, LLVMTypeRef *param_types,
235 unsigned param_count, unsigned array_params_mask,
236 unsigned sgpr_params, bool unsafe_math)
237 {
238 LLVMTypeRef main_function_type, ret_type;
239 LLVMBasicBlockRef main_function_body;
240
241 if (num_return_elems)
242 ret_type = LLVMStructTypeInContext(ctx, return_types,
243 num_return_elems, true);
244 else
245 ret_type = LLVMVoidTypeInContext(ctx);
246
247 /* Setup the function */
248 main_function_type =
249 LLVMFunctionType(ret_type, param_types, param_count, 0);
250 LLVMValueRef main_function =
251 LLVMAddFunction(module, "main", main_function_type);
252 main_function_body =
253 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
254 LLVMPositionBuilderAtEnd(builder, main_function_body);
255
256 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
257 for (unsigned i = 0; i < sgpr_params; ++i) {
258 if (array_params_mask & (1 << i)) {
259 LLVMValueRef P = LLVMGetParam(main_function, i);
260 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
261 ac_add_attr_dereferenceable(P, UINT64_MAX);
262 }
263 else {
264 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
265 }
266 }
267
268 if (unsafe_math) {
269 /* These were copied from some LLVM test. */
270 LLVMAddTargetDependentFunctionAttr(main_function,
271 "less-precise-fpmad",
272 "true");
273 LLVMAddTargetDependentFunctionAttr(main_function,
274 "no-infs-fp-math",
275 "true");
276 LLVMAddTargetDependentFunctionAttr(main_function,
277 "no-nans-fp-math",
278 "true");
279 LLVMAddTargetDependentFunctionAttr(main_function,
280 "unsafe-fp-math",
281 "true");
282 }
283 return main_function;
284 }
285
286 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
287 {
288 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
289 CONST_ADDR_SPACE);
290 }
291
292 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
293 int idx,
294 LLVMTypeRef type)
295 {
296 LLVMValueRef offset;
297 LLVMValueRef ptr;
298 int addr_space;
299
300 offset = LLVMConstInt(ctx->i32, idx, false);
301
302 ptr = ctx->shared_memory;
303 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
304 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
305 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
306 return ptr;
307 }
308
309 static LLVMTypeRef to_integer_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
310 {
311 if (t == ctx->f16 || t == ctx->i16)
312 return ctx->i16;
313 else if (t == ctx->f32 || t == ctx->i32)
314 return ctx->i32;
315 else if (t == ctx->f64 || t == ctx->i64)
316 return ctx->i64;
317 else
318 unreachable("Unhandled integer size");
319 }
320
321 static LLVMTypeRef to_integer_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
322 {
323 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
324 LLVMTypeRef elem_type = LLVMGetElementType(t);
325 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
326 LLVMGetVectorSize(t));
327 }
328 return to_integer_type_scalar(ctx, t);
329 }
330
331 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
332 {
333 LLVMTypeRef type = LLVMTypeOf(v);
334 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
335 }
336
337 static LLVMTypeRef to_float_type_scalar(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
338 {
339 if (t == ctx->i16 || t == ctx->f16)
340 return ctx->f16;
341 else if (t == ctx->i32 || t == ctx->f32)
342 return ctx->f32;
343 else if (t == ctx->i64 || t == ctx->f64)
344 return ctx->f64;
345 else
346 unreachable("Unhandled float size");
347 }
348
349 static LLVMTypeRef to_float_type(struct nir_to_llvm_context *ctx, LLVMTypeRef t)
350 {
351 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
352 LLVMTypeRef elem_type = LLVMGetElementType(t);
353 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
354 LLVMGetVectorSize(t));
355 }
356 return to_float_type_scalar(ctx, t);
357 }
358
359 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
360 {
361 LLVMTypeRef type = LLVMTypeOf(v);
362 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
363 }
364
365 static int get_elem_bits(struct nir_to_llvm_context *ctx, LLVMTypeRef type)
366 {
367 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
368 type = LLVMGetElementType(type);
369
370 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
371 return LLVMGetIntTypeWidth(type);
372
373 if (type == ctx->f16)
374 return 16;
375 if (type == ctx->f32)
376 return 32;
377 if (type == ctx->f64)
378 return 64;
379
380 unreachable("Unhandled type kind in get_elem_bits");
381 }
382
383 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
384 LLVMValueRef param, unsigned rshift,
385 unsigned bitwidth)
386 {
387 LLVMValueRef value = param;
388 if (rshift)
389 value = LLVMBuildLShr(ctx->builder, value,
390 LLVMConstInt(ctx->i32, rshift, false), "");
391
392 if (rshift + bitwidth < 32) {
393 unsigned mask = (1 << bitwidth) - 1;
394 value = LLVMBuildAnd(ctx->builder, value,
395 LLVMConstInt(ctx->i32, mask, false), "");
396 }
397 return value;
398 }
399
400 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
401 {
402 ud_info->sgpr_idx = sgpr_idx;
403 ud_info->num_sgprs = num_sgprs;
404 ud_info->indirect = false;
405 ud_info->indirect_offset = 0;
406 }
407
408 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
409 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
410 {
411 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
412 }
413
414 #if 0
415 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
416 uint32_t indirect_offset)
417 {
418 ud_info->sgpr_idx = sgpr_idx;
419 ud_info->num_sgprs = num_sgprs;
420 ud_info->indirect = true;
421 ud_info->indirect_offset = indirect_offset;
422 }
423 #endif
424
425 static void create_function(struct nir_to_llvm_context *ctx)
426 {
427 LLVMTypeRef arg_types[23];
428 unsigned arg_idx = 0;
429 unsigned array_params_mask = 0;
430 unsigned sgpr_count = 0, user_sgpr_count;
431 unsigned i;
432 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
433 unsigned user_sgpr_idx;
434 bool need_push_constants;
435 bool need_ring_offsets = false;
436
437 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
438 if (ctx->stage == MESA_SHADER_GEOMETRY ||
439 ctx->stage == MESA_SHADER_VERTEX ||
440 ctx->is_gs_copy_shader)
441 need_ring_offsets = true;
442
443 need_push_constants = true;
444 if (!ctx->options->layout)
445 need_push_constants = false;
446 else if (!ctx->options->layout->push_constant_size &&
447 !ctx->options->layout->dynamic_offset_count)
448 need_push_constants = false;
449
450 if (need_ring_offsets && !ctx->options->supports_spill) {
451 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
452 }
453
454 /* 1 for each descriptor set */
455 for (unsigned i = 0; i < num_sets; ++i) {
456 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
457 array_params_mask |= (1 << arg_idx);
458 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
459 }
460 }
461
462 if (need_push_constants) {
463 /* 1 for push constants and dynamic descriptors */
464 array_params_mask |= (1 << arg_idx);
465 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
466 }
467
468 switch (ctx->stage) {
469 case MESA_SHADER_COMPUTE:
470 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
471 user_sgpr_count = arg_idx;
472 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
473 arg_types[arg_idx++] = ctx->i32;
474 sgpr_count = arg_idx;
475
476 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
477 break;
478 case MESA_SHADER_VERTEX:
479 if (!ctx->is_gs_copy_shader) {
480 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
481 arg_types[arg_idx++] = ctx->i32; // base vertex
482 arg_types[arg_idx++] = ctx->i32; // start instance
483 arg_types[arg_idx++] = ctx->i32; // draw index
484 }
485 user_sgpr_count = arg_idx;
486 if (ctx->options->key.vs.as_es)
487 arg_types[arg_idx++] = ctx->i32; //es2gs offset
488 sgpr_count = arg_idx;
489 arg_types[arg_idx++] = ctx->i32; // vertex id
490 if (!ctx->is_gs_copy_shader) {
491 arg_types[arg_idx++] = ctx->i32; // rel auto id
492 arg_types[arg_idx++] = ctx->i32; // vs prim id
493 arg_types[arg_idx++] = ctx->i32; // instance id
494 }
495 break;
496 case MESA_SHADER_GEOMETRY:
497 arg_types[arg_idx++] = ctx->i32; // gsvs stride
498 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
499 user_sgpr_count = arg_idx;
500 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
501 arg_types[arg_idx++] = ctx->i32; // wave id
502 sgpr_count = arg_idx;
503 arg_types[arg_idx++] = ctx->i32; // vtx0
504 arg_types[arg_idx++] = ctx->i32; // vtx1
505 arg_types[arg_idx++] = ctx->i32; // prim id
506 arg_types[arg_idx++] = ctx->i32; // vtx2
507 arg_types[arg_idx++] = ctx->i32; // vtx3
508 arg_types[arg_idx++] = ctx->i32; // vtx4
509 arg_types[arg_idx++] = ctx->i32; // vtx5
510 arg_types[arg_idx++] = ctx->i32; // GS instance id
511 break;
512 case MESA_SHADER_FRAGMENT:
513 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
514 user_sgpr_count = arg_idx;
515 arg_types[arg_idx++] = ctx->i32; /* prim mask */
516 sgpr_count = arg_idx;
517 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
518 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
519 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
520 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
521 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
522 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
523 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
524 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
525 arg_types[arg_idx++] = ctx->f32; /* pos x float */
526 arg_types[arg_idx++] = ctx->f32; /* pos y float */
527 arg_types[arg_idx++] = ctx->f32; /* pos z float */
528 arg_types[arg_idx++] = ctx->f32; /* pos w float */
529 arg_types[arg_idx++] = ctx->i32; /* front face */
530 arg_types[arg_idx++] = ctx->i32; /* ancillary */
531 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
532 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
533 break;
534 default:
535 unreachable("Shader stage not implemented");
536 }
537
538 ctx->main_function = create_llvm_function(
539 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
540 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
541 set_llvm_calling_convention(ctx->main_function, ctx->stage);
542
543 ctx->shader_info->num_input_sgprs = 0;
544 ctx->shader_info->num_input_vgprs = 0;
545
546 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
547 for (i = 0; i < user_sgpr_count; i++)
548 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
549
550 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
551 for (; i < sgpr_count; i++)
552 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
553
554 if (ctx->stage != MESA_SHADER_FRAGMENT)
555 for (; i < arg_idx; ++i)
556 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
557
558 arg_idx = 0;
559 user_sgpr_idx = 0;
560
561 if (ctx->options->supports_spill || need_ring_offsets) {
562 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
563 user_sgpr_idx += 2;
564 if (ctx->options->supports_spill) {
565 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
566 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
567 NULL, 0, AC_FUNC_ATTR_READNONE);
568 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
569 const_array(ctx->v16i8, 8), "");
570 } else
571 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
572 }
573
574 for (unsigned i = 0; i < num_sets; ++i) {
575 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
576 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
577 user_sgpr_idx += 2;
578 ctx->descriptor_sets[i] =
579 LLVMGetParam(ctx->main_function, arg_idx++);
580 } else
581 ctx->descriptor_sets[i] = NULL;
582 }
583
584 if (need_push_constants) {
585 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
586 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
587 user_sgpr_idx += 2;
588 }
589
590 switch (ctx->stage) {
591 case MESA_SHADER_COMPUTE:
592 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
593 user_sgpr_idx += 3;
594 ctx->num_work_groups =
595 LLVMGetParam(ctx->main_function, arg_idx++);
596 ctx->workgroup_ids =
597 LLVMGetParam(ctx->main_function, arg_idx++);
598 ctx->tg_size =
599 LLVMGetParam(ctx->main_function, arg_idx++);
600 ctx->local_invocation_ids =
601 LLVMGetParam(ctx->main_function, arg_idx++);
602 break;
603 case MESA_SHADER_VERTEX:
604 if (!ctx->is_gs_copy_shader) {
605 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
606 user_sgpr_idx += 2;
607 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
608 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 3);
609 user_sgpr_idx += 3;
610 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
611 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
612 ctx->draw_index = LLVMGetParam(ctx->main_function, arg_idx++);
613 }
614 if (ctx->options->key.vs.as_es)
615 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
616 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
617 if (!ctx->is_gs_copy_shader) {
618 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
619 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
620 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
621 }
622 break;
623 case MESA_SHADER_GEOMETRY:
624 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
625 user_sgpr_idx += 2;
626 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
627 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
628 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
629 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
630 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
631 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
632 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
633 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
635 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
636 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 break;
639 case MESA_SHADER_FRAGMENT:
640 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
641 user_sgpr_idx += 2;
642 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
643 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
644 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
645 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
646 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
647 arg_idx++;
648 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
651 arg_idx++; /* line stipple */
652 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
655 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
656 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
657 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
658 break;
659 default:
660 unreachable("Shader stage not implemented");
661 }
662 }
663
664 static void setup_types(struct nir_to_llvm_context *ctx)
665 {
666 LLVMValueRef args[4];
667
668 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
669 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
670 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
671 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
672 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
673 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
674 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
675 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
676 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
677 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
678 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
679 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
680 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
681 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
682 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
683 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
684
685 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
686 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
687 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
688 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
689
690 args[0] = ctx->f32zero;
691 args[1] = ctx->f32zero;
692 args[2] = ctx->f32zero;
693 args[3] = ctx->f32one;
694 ctx->v4f32empty = LLVMConstVector(args, 4);
695
696 ctx->uniform_md_kind =
697 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
698 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
699
700 args[0] = LLVMConstReal(ctx->f32, 2.5);
701 }
702
703 static int get_llvm_num_components(LLVMValueRef value)
704 {
705 LLVMTypeRef type = LLVMTypeOf(value);
706 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
707 ? LLVMGetVectorSize(type)
708 : 1;
709 return num_components;
710 }
711
712 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
713 LLVMValueRef value,
714 int index)
715 {
716 int count = get_llvm_num_components(value);
717
718 assert(index < count);
719 if (count == 1)
720 return value;
721
722 return LLVMBuildExtractElement(ctx->builder, value,
723 LLVMConstInt(ctx->i32, index, false), "");
724 }
725
726 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
727 LLVMValueRef value, unsigned count)
728 {
729 unsigned num_components = get_llvm_num_components(value);
730 if (count == num_components)
731 return value;
732
733 LLVMValueRef masks[] = {
734 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
735 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
736
737 if (count == 1)
738 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
739 "");
740
741 LLVMValueRef swizzle = LLVMConstVector(masks, count);
742 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
743 }
744
745 static void
746 build_store_values_extended(struct nir_to_llvm_context *ctx,
747 LLVMValueRef *values,
748 unsigned value_count,
749 unsigned value_stride,
750 LLVMValueRef vec)
751 {
752 LLVMBuilderRef builder = ctx->builder;
753 unsigned i;
754
755 if (value_count == 1) {
756 LLVMBuildStore(builder, vec, values[0]);
757 return;
758 }
759
760 for (i = 0; i < value_count; i++) {
761 LLVMValueRef ptr = values[i * value_stride];
762 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
763 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
764 LLVMBuildStore(builder, value, ptr);
765 }
766 }
767
768 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
769 nir_ssa_def *def)
770 {
771 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
772 if (def->num_components > 1) {
773 type = LLVMVectorType(type, def->num_components);
774 }
775 return type;
776 }
777
778 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
779 {
780 assert(src.is_ssa);
781 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
782 return (LLVMValueRef)entry->data;
783 }
784
785
786 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
787 struct nir_block *b)
788 {
789 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
790 return (LLVMBasicBlockRef)entry->data;
791 }
792
793 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
794 nir_alu_src src,
795 unsigned num_components)
796 {
797 LLVMValueRef value = get_src(ctx, src.src);
798 bool need_swizzle = false;
799
800 assert(value);
801 LLVMTypeRef type = LLVMTypeOf(value);
802 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
803 ? LLVMGetVectorSize(type)
804 : 1;
805
806 for (unsigned i = 0; i < num_components; ++i) {
807 assert(src.swizzle[i] < src_components);
808 if (src.swizzle[i] != i)
809 need_swizzle = true;
810 }
811
812 if (need_swizzle || num_components != src_components) {
813 LLVMValueRef masks[] = {
814 LLVMConstInt(ctx->i32, src.swizzle[0], false),
815 LLVMConstInt(ctx->i32, src.swizzle[1], false),
816 LLVMConstInt(ctx->i32, src.swizzle[2], false),
817 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
818
819 if (src_components > 1 && num_components == 1) {
820 value = LLVMBuildExtractElement(ctx->builder, value,
821 masks[0], "");
822 } else if (src_components == 1 && num_components > 1) {
823 LLVMValueRef values[] = {value, value, value, value};
824 value = ac_build_gather_values(&ctx->ac, values, num_components);
825 } else {
826 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
827 value = LLVMBuildShuffleVector(ctx->builder, value, value,
828 swizzle, "");
829 }
830 }
831 assert(!src.negate);
832 assert(!src.abs);
833 return value;
834 }
835
836 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
837 LLVMIntPredicate pred, LLVMValueRef src0,
838 LLVMValueRef src1)
839 {
840 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
841 return LLVMBuildSelect(ctx->builder, result,
842 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
843 LLVMConstInt(ctx->i32, 0, false), "");
844 }
845
846 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
847 LLVMRealPredicate pred, LLVMValueRef src0,
848 LLVMValueRef src1)
849 {
850 LLVMValueRef result;
851 src0 = to_float(ctx, src0);
852 src1 = to_float(ctx, src1);
853 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
854 return LLVMBuildSelect(ctx->builder, result,
855 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
856 LLVMConstInt(ctx->i32, 0, false), "");
857 }
858
859 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
860 const char *intrin,
861 LLVMTypeRef result_type,
862 LLVMValueRef src0)
863 {
864 char name[64];
865 LLVMValueRef params[] = {
866 to_float(ctx, src0),
867 };
868
869 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
870 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
871 }
872
873 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
874 const char *intrin,
875 LLVMTypeRef result_type,
876 LLVMValueRef src0, LLVMValueRef src1)
877 {
878 char name[64];
879 LLVMValueRef params[] = {
880 to_float(ctx, src0),
881 to_float(ctx, src1),
882 };
883
884 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
885 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
886 }
887
888 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
889 const char *intrin,
890 LLVMTypeRef result_type,
891 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
892 {
893 char name[64];
894 LLVMValueRef params[] = {
895 to_float(ctx, src0),
896 to_float(ctx, src1),
897 to_float(ctx, src2),
898 };
899
900 sprintf(name, "%s.f%d", intrin, get_elem_bits(ctx, result_type));
901 return ac_emit_llvm_intrinsic(&ctx->ac, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
902 }
903
904 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
905 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
906 {
907 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
908 ctx->i32zero, "");
909 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
910 }
911
912 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
913 LLVMValueRef src0)
914 {
915 LLVMValueRef params[2] = {
916 src0,
917
918 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
919 * add special code to check for x=0. The reason is that
920 * the LLVM behavior for x=0 is different from what we
921 * need here.
922 *
923 * The hardware already implements the correct behavior.
924 */
925 LLVMConstInt(ctx->i32, 1, false),
926 };
927 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
928 }
929
930 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
931 LLVMValueRef src0)
932 {
933 return ac_emit_imsb(&ctx->ac, src0, ctx->i32);
934 }
935
936 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
937 LLVMValueRef src0)
938 {
939 LLVMValueRef args[2] = {
940 src0,
941 ctx->i32one,
942 };
943 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
944 ctx->i32, args, ARRAY_SIZE(args),
945 AC_FUNC_ATTR_READNONE);
946
947 /* The HW returns the last bit index from MSB, but NIR wants
948 * the index from LSB. Invert it by doing "31 - msb". */
949 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
950 msb, "");
951
952 return LLVMBuildSelect(ctx->builder,
953 LLVMBuildICmp(ctx->builder, LLVMIntEQ, src0,
954 ctx->i32zero, ""),
955 LLVMConstInt(ctx->i32, -1, true), msb, "");
956 }
957
958 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
959 LLVMIntPredicate pred,
960 LLVMValueRef src0, LLVMValueRef src1)
961 {
962 return LLVMBuildSelect(ctx->builder,
963 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
964 src0,
965 src1, "");
966
967 }
968 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
969 LLVMValueRef src0)
970 {
971 return emit_minmax_int(ctx, LLVMIntSGT, src0,
972 LLVMBuildNeg(ctx->builder, src0, ""));
973 }
974
975 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
976 LLVMValueRef src0)
977 {
978 LLVMValueRef cmp, val;
979
980 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
981 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
982 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
983 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
984 return val;
985 }
986
987 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
988 LLVMValueRef src0)
989 {
990 LLVMValueRef cmp, val;
991
992 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
993 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
994 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
995 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
996 return val;
997 }
998
999 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1000 LLVMValueRef src0)
1001 {
1002 const char *intr = "llvm.floor.f32";
1003 LLVMValueRef fsrc0 = to_float(ctx, src0);
1004 LLVMValueRef params[] = {
1005 fsrc0,
1006 };
1007 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
1008 ctx->f32, params, 1,
1009 AC_FUNC_ATTR_READNONE);
1010 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1011 }
1012
1013 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1014 const char *intrin,
1015 LLVMValueRef src0, LLVMValueRef src1)
1016 {
1017 LLVMTypeRef ret_type;
1018 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1019 LLVMValueRef res;
1020 LLVMValueRef params[] = { src0, src1 };
1021 ret_type = LLVMStructTypeInContext(ctx->context, types,
1022 2, true);
1023
1024 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1025 params, 2, AC_FUNC_ATTR_READNONE);
1026
1027 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1028 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1029 return res;
1030 }
1031
1032 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1033 LLVMValueRef src0)
1034 {
1035 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1036 }
1037
1038 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1039 LLVMValueRef src0, LLVMValueRef src1)
1040 {
1041 LLVMValueRef dst64, result;
1042 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1043 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1044
1045 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1046 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1047 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1048 return result;
1049 }
1050
1051 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1052 LLVMValueRef src0, LLVMValueRef src1)
1053 {
1054 LLVMValueRef dst64, result;
1055 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1056 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1057
1058 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1059 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1060 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1061 return result;
1062 }
1063
1064 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1065 const char *intrin,
1066 LLVMValueRef srcs[3])
1067 {
1068 LLVMValueRef result;
1069 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1070 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1071
1072 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1073 return result;
1074 }
1075
1076 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1077 LLVMValueRef src0, LLVMValueRef src1,
1078 LLVMValueRef src2, LLVMValueRef src3)
1079 {
1080 LLVMValueRef bfi_args[3], result;
1081
1082 bfi_args[0] = LLVMBuildShl(ctx->builder,
1083 LLVMBuildSub(ctx->builder,
1084 LLVMBuildShl(ctx->builder,
1085 ctx->i32one,
1086 src3, ""),
1087 ctx->i32one, ""),
1088 src2, "");
1089 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1090 bfi_args[2] = src0;
1091
1092 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1093
1094 /* Calculate:
1095 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1096 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1097 */
1098 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1099 LLVMBuildAnd(ctx->builder, bfi_args[0],
1100 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1101
1102 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1103 return result;
1104 }
1105
1106 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1107 LLVMValueRef src0)
1108 {
1109 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1110 int i;
1111 LLVMValueRef comp[2];
1112
1113 src0 = to_float(ctx, src0);
1114 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1115 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1116 for (i = 0; i < 2; i++) {
1117 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1118 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1119 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1120 }
1121
1122 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1123 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1124
1125 return comp[0];
1126 }
1127
1128 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1129 LLVMValueRef src0)
1130 {
1131 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1132 LLVMValueRef temps[2], result, val;
1133 int i;
1134
1135 for (i = 0; i < 2; i++) {
1136 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1137 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1138 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1139 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1140 }
1141
1142 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1143 ctx->i32zero, "");
1144 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1145 ctx->i32one, "");
1146 return result;
1147 }
1148
1149 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1150 nir_op op,
1151 LLVMValueRef src0)
1152 {
1153 unsigned mask;
1154 int idx;
1155 LLVMValueRef result;
1156 ctx->has_ddxy = true;
1157
1158 if (!ctx->lds && !ctx->has_ds_bpermute)
1159 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1160 LLVMArrayType(ctx->i32, 64),
1161 "ddxy_lds", LOCAL_ADDR_SPACE);
1162
1163 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1164 mask = AC_TID_MASK_LEFT;
1165 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1166 mask = AC_TID_MASK_TOP;
1167 else
1168 mask = AC_TID_MASK_TOP_LEFT;
1169
1170 /* for DDX we want to next X pixel, DDY next Y pixel. */
1171 if (op == nir_op_fddx_fine ||
1172 op == nir_op_fddx_coarse ||
1173 op == nir_op_fddx)
1174 idx = 1;
1175 else
1176 idx = 2;
1177
1178 result = ac_emit_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1179 mask, idx, ctx->lds,
1180 src0);
1181 return result;
1182 }
1183
1184 /*
1185 * this takes an I,J coordinate pair,
1186 * and works out the X and Y derivatives.
1187 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1188 */
1189 static LLVMValueRef emit_ddxy_interp(
1190 struct nir_to_llvm_context *ctx,
1191 LLVMValueRef interp_ij)
1192 {
1193 LLVMValueRef result[4], a;
1194 unsigned i;
1195
1196 for (i = 0; i < 2; i++) {
1197 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1198 LLVMConstInt(ctx->i32, i, false), "");
1199 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1200 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1201 }
1202 return ac_build_gather_values(&ctx->ac, result, 4);
1203 }
1204
1205 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1206 {
1207 LLVMValueRef src[4], result = NULL;
1208 unsigned num_components = instr->dest.dest.ssa.num_components;
1209 unsigned src_components;
1210 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1211
1212 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1213 switch (instr->op) {
1214 case nir_op_vec2:
1215 case nir_op_vec3:
1216 case nir_op_vec4:
1217 src_components = 1;
1218 break;
1219 case nir_op_pack_half_2x16:
1220 src_components = 2;
1221 break;
1222 case nir_op_unpack_half_2x16:
1223 src_components = 1;
1224 break;
1225 default:
1226 src_components = num_components;
1227 break;
1228 }
1229 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1230 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1231
1232 switch (instr->op) {
1233 case nir_op_fmov:
1234 case nir_op_imov:
1235 result = src[0];
1236 break;
1237 case nir_op_fneg:
1238 src[0] = to_float(ctx, src[0]);
1239 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1240 break;
1241 case nir_op_ineg:
1242 result = LLVMBuildNeg(ctx->builder, src[0], "");
1243 break;
1244 case nir_op_inot:
1245 result = LLVMBuildNot(ctx->builder, src[0], "");
1246 break;
1247 case nir_op_iadd:
1248 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1249 break;
1250 case nir_op_fadd:
1251 src[0] = to_float(ctx, src[0]);
1252 src[1] = to_float(ctx, src[1]);
1253 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1254 break;
1255 case nir_op_fsub:
1256 src[0] = to_float(ctx, src[0]);
1257 src[1] = to_float(ctx, src[1]);
1258 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1259 break;
1260 case nir_op_isub:
1261 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1262 break;
1263 case nir_op_imul:
1264 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1265 break;
1266 case nir_op_imod:
1267 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1268 break;
1269 case nir_op_umod:
1270 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1271 break;
1272 case nir_op_fmod:
1273 src[0] = to_float(ctx, src[0]);
1274 src[1] = to_float(ctx, src[1]);
1275 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1276 result = emit_intrin_1f_param(ctx, "llvm.floor",
1277 to_float_type(ctx, def_type), result);
1278 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1279 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1280 break;
1281 case nir_op_frem:
1282 src[0] = to_float(ctx, src[0]);
1283 src[1] = to_float(ctx, src[1]);
1284 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1285 break;
1286 case nir_op_irem:
1287 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1288 break;
1289 case nir_op_idiv:
1290 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1291 break;
1292 case nir_op_udiv:
1293 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1294 break;
1295 case nir_op_fmul:
1296 src[0] = to_float(ctx, src[0]);
1297 src[1] = to_float(ctx, src[1]);
1298 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1299 break;
1300 case nir_op_fdiv:
1301 src[0] = to_float(ctx, src[0]);
1302 src[1] = to_float(ctx, src[1]);
1303 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1304 break;
1305 case nir_op_frcp:
1306 src[0] = to_float(ctx, src[0]);
1307 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1308 break;
1309 case nir_op_iand:
1310 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1311 break;
1312 case nir_op_ior:
1313 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1314 break;
1315 case nir_op_ixor:
1316 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1317 break;
1318 case nir_op_ishl:
1319 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1320 break;
1321 case nir_op_ishr:
1322 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1323 break;
1324 case nir_op_ushr:
1325 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1326 break;
1327 case nir_op_ilt:
1328 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1329 break;
1330 case nir_op_ine:
1331 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1332 break;
1333 case nir_op_ieq:
1334 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1335 break;
1336 case nir_op_ige:
1337 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1338 break;
1339 case nir_op_ult:
1340 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1341 break;
1342 case nir_op_uge:
1343 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1344 break;
1345 case nir_op_feq:
1346 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1347 break;
1348 case nir_op_fne:
1349 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1350 break;
1351 case nir_op_flt:
1352 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1353 break;
1354 case nir_op_fge:
1355 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1356 break;
1357 case nir_op_fabs:
1358 result = emit_intrin_1f_param(ctx, "llvm.fabs",
1359 to_float_type(ctx, def_type), src[0]);
1360 break;
1361 case nir_op_iabs:
1362 result = emit_iabs(ctx, src[0]);
1363 break;
1364 case nir_op_imax:
1365 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1366 break;
1367 case nir_op_imin:
1368 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1369 break;
1370 case nir_op_umax:
1371 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1372 break;
1373 case nir_op_umin:
1374 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1375 break;
1376 case nir_op_isign:
1377 result = emit_isign(ctx, src[0]);
1378 break;
1379 case nir_op_fsign:
1380 src[0] = to_float(ctx, src[0]);
1381 result = emit_fsign(ctx, src[0]);
1382 break;
1383 case nir_op_ffloor:
1384 result = emit_intrin_1f_param(ctx, "llvm.floor",
1385 to_float_type(ctx, def_type), src[0]);
1386 break;
1387 case nir_op_ftrunc:
1388 result = emit_intrin_1f_param(ctx, "llvm.trunc",
1389 to_float_type(ctx, def_type), src[0]);
1390 break;
1391 case nir_op_fceil:
1392 result = emit_intrin_1f_param(ctx, "llvm.ceil",
1393 to_float_type(ctx, def_type), src[0]);
1394 break;
1395 case nir_op_fround_even:
1396 result = emit_intrin_1f_param(ctx, "llvm.rint",
1397 to_float_type(ctx, def_type),src[0]);
1398 break;
1399 case nir_op_ffract:
1400 result = emit_ffract(ctx, src[0]);
1401 break;
1402 case nir_op_fsin:
1403 result = emit_intrin_1f_param(ctx, "llvm.sin",
1404 to_float_type(ctx, def_type), src[0]);
1405 break;
1406 case nir_op_fcos:
1407 result = emit_intrin_1f_param(ctx, "llvm.cos",
1408 to_float_type(ctx, def_type), src[0]);
1409 break;
1410 case nir_op_fsqrt:
1411 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1412 to_float_type(ctx, def_type), src[0]);
1413 break;
1414 case nir_op_fexp2:
1415 result = emit_intrin_1f_param(ctx, "llvm.exp2",
1416 to_float_type(ctx, def_type), src[0]);
1417 break;
1418 case nir_op_flog2:
1419 result = emit_intrin_1f_param(ctx, "llvm.log2",
1420 to_float_type(ctx, def_type), src[0]);
1421 break;
1422 case nir_op_frsq:
1423 result = emit_intrin_1f_param(ctx, "llvm.sqrt",
1424 to_float_type(ctx, def_type), src[0]);
1425 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1426 break;
1427 case nir_op_fpow:
1428 result = emit_intrin_2f_param(ctx, "llvm.pow",
1429 to_float_type(ctx, def_type), src[0], src[1]);
1430 break;
1431 case nir_op_fmax:
1432 result = emit_intrin_2f_param(ctx, "llvm.maxnum",
1433 to_float_type(ctx, def_type), src[0], src[1]);
1434 break;
1435 case nir_op_fmin:
1436 result = emit_intrin_2f_param(ctx, "llvm.minnum",
1437 to_float_type(ctx, def_type), src[0], src[1]);
1438 break;
1439 case nir_op_ffma:
1440 result = emit_intrin_3f_param(ctx, "llvm.fma",
1441 to_float_type(ctx, def_type), src[0], src[1], src[2]);
1442 break;
1443 case nir_op_ibitfield_extract:
1444 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1445 break;
1446 case nir_op_ubitfield_extract:
1447 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1448 break;
1449 case nir_op_bitfield_insert:
1450 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1451 break;
1452 case nir_op_bitfield_reverse:
1453 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1454 break;
1455 case nir_op_bit_count:
1456 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1457 break;
1458 case nir_op_vec2:
1459 case nir_op_vec3:
1460 case nir_op_vec4:
1461 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1462 src[i] = to_integer(ctx, src[i]);
1463 result = ac_build_gather_values(&ctx->ac, src, num_components);
1464 break;
1465 case nir_op_d2i:
1466 case nir_op_f2i:
1467 src[0] = to_float(ctx, src[0]);
1468 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1469 break;
1470 case nir_op_d2u:
1471 case nir_op_f2u:
1472 src[0] = to_float(ctx, src[0]);
1473 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1474 break;
1475 case nir_op_i2d:
1476 case nir_op_i2f:
1477 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1478 break;
1479 case nir_op_u2d:
1480 case nir_op_u2f:
1481 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1482 break;
1483 case nir_op_f2d:
1484 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1485 break;
1486 case nir_op_d2f:
1487 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(ctx, def_type), "");
1488 break;
1489 case nir_op_bcsel:
1490 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1491 break;
1492 case nir_op_find_lsb:
1493 result = emit_find_lsb(ctx, src[0]);
1494 break;
1495 case nir_op_ufind_msb:
1496 result = emit_ufind_msb(ctx, src[0]);
1497 break;
1498 case nir_op_ifind_msb:
1499 result = emit_ifind_msb(ctx, src[0]);
1500 break;
1501 case nir_op_uadd_carry:
1502 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1503 break;
1504 case nir_op_usub_borrow:
1505 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1506 break;
1507 case nir_op_b2f:
1508 result = emit_b2f(ctx, src[0]);
1509 break;
1510 case nir_op_fquantize2f16:
1511 src[0] = to_float(ctx, src[0]);
1512 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1513 /* need to convert back up to f32 */
1514 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1515 break;
1516 case nir_op_umul_high:
1517 result = emit_umul_high(ctx, src[0], src[1]);
1518 break;
1519 case nir_op_imul_high:
1520 result = emit_imul_high(ctx, src[0], src[1]);
1521 break;
1522 case nir_op_pack_half_2x16:
1523 result = emit_pack_half_2x16(ctx, src[0]);
1524 break;
1525 case nir_op_unpack_half_2x16:
1526 result = emit_unpack_half_2x16(ctx, src[0]);
1527 break;
1528 case nir_op_fddx:
1529 case nir_op_fddy:
1530 case nir_op_fddx_fine:
1531 case nir_op_fddy_fine:
1532 case nir_op_fddx_coarse:
1533 case nir_op_fddy_coarse:
1534 result = emit_ddxy(ctx, instr->op, src[0]);
1535 break;
1536 default:
1537 fprintf(stderr, "Unknown NIR alu instr: ");
1538 nir_print_instr(&instr->instr, stderr);
1539 fprintf(stderr, "\n");
1540 abort();
1541 }
1542
1543 if (result) {
1544 assert(instr->dest.dest.is_ssa);
1545 result = to_integer(ctx, result);
1546 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1547 result);
1548 }
1549 }
1550
1551 static void visit_load_const(struct nir_to_llvm_context *ctx,
1552 nir_load_const_instr *instr)
1553 {
1554 LLVMValueRef values[4], value = NULL;
1555 LLVMTypeRef element_type =
1556 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1557
1558 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1559 switch (instr->def.bit_size) {
1560 case 32:
1561 values[i] = LLVMConstInt(element_type,
1562 instr->value.u32[i], false);
1563 break;
1564 case 64:
1565 values[i] = LLVMConstInt(element_type,
1566 instr->value.u64[i], false);
1567 break;
1568 default:
1569 fprintf(stderr,
1570 "unsupported nir load_const bit_size: %d\n",
1571 instr->def.bit_size);
1572 abort();
1573 }
1574 }
1575 if (instr->def.num_components > 1) {
1576 value = LLVMConstVector(values, instr->def.num_components);
1577 } else
1578 value = values[0];
1579
1580 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1581 }
1582
1583 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1584 LLVMTypeRef type)
1585 {
1586 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1587 return LLVMBuildBitCast(ctx->builder, ptr,
1588 LLVMPointerType(type, addr_space), "");
1589 }
1590
1591 static LLVMValueRef
1592 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1593 {
1594 LLVMValueRef size =
1595 LLVMBuildExtractElement(ctx->builder, descriptor,
1596 LLVMConstInt(ctx->i32, 2, false), "");
1597
1598 /* VI only */
1599 if (ctx->options->chip_class >= VI && in_elements) {
1600 /* On VI, the descriptor contains the size in bytes,
1601 * but TXQ must return the size in elements.
1602 * The stride is always non-zero for resources using TXQ.
1603 */
1604 LLVMValueRef stride =
1605 LLVMBuildExtractElement(ctx->builder, descriptor,
1606 LLVMConstInt(ctx->i32, 1, false), "");
1607 stride = LLVMBuildLShr(ctx->builder, stride,
1608 LLVMConstInt(ctx->i32, 16, false), "");
1609 stride = LLVMBuildAnd(ctx->builder, stride,
1610 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1611
1612 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1613 }
1614 return size;
1615 }
1616
1617 /**
1618 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1619 * intrinsic names).
1620 */
1621 static void build_int_type_name(
1622 LLVMTypeRef type,
1623 char *buf, unsigned bufsize)
1624 {
1625 assert(bufsize >= 6);
1626
1627 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1628 snprintf(buf, bufsize, "v%ui32",
1629 LLVMGetVectorSize(type));
1630 else
1631 strcpy(buf, "i32");
1632 }
1633
1634 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1635 struct ac_tex_info *tinfo,
1636 nir_tex_instr *instr,
1637 const char *intr_name,
1638 unsigned coord_vgpr_index)
1639 {
1640 LLVMValueRef coord = tinfo->args[0];
1641 LLVMValueRef half_texel[2];
1642 int c;
1643
1644 //TODO Rect
1645 {
1646 LLVMValueRef txq_args[10];
1647 int txq_arg_count = 0;
1648 LLVMValueRef size;
1649 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1650 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1651 txq_args[txq_arg_count++] = tinfo->args[1];
1652 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1653 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1654 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1655 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1656 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1657 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1658 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1659 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1660 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1661 txq_args, txq_arg_count,
1662 AC_FUNC_ATTR_READNONE);
1663
1664 for (c = 0; c < 2; c++) {
1665 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1666 LLVMConstInt(ctx->i32, c, false), "");
1667 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1668 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1669 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1670 LLVMConstReal(ctx->f32, -0.5), "");
1671 }
1672 }
1673
1674 for (c = 0; c < 2; c++) {
1675 LLVMValueRef tmp;
1676 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1677 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1678 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1679 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1680 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1681 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1682 }
1683
1684 tinfo->args[0] = coord;
1685 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1686 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1687
1688 }
1689
1690 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1691 nir_tex_instr *instr,
1692 struct ac_tex_info *tinfo)
1693 {
1694 const char *name = "llvm.SI.image.sample";
1695 const char *infix = "";
1696 char intr_name[127];
1697 char type[64];
1698 bool is_shadow = instr->is_shadow;
1699 bool has_offset = tinfo->has_offset;
1700 switch (instr->op) {
1701 case nir_texop_txf:
1702 case nir_texop_txf_ms:
1703 case nir_texop_samples_identical:
1704 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1705 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1706 "llvm.SI.image.load.mip";
1707 is_shadow = false;
1708 has_offset = false;
1709 break;
1710 case nir_texop_txb:
1711 infix = ".b";
1712 break;
1713 case nir_texop_txl:
1714 infix = ".l";
1715 break;
1716 case nir_texop_txs:
1717 name = "llvm.SI.getresinfo";
1718 break;
1719 case nir_texop_query_levels:
1720 name = "llvm.SI.getresinfo";
1721 break;
1722 case nir_texop_tex:
1723 if (ctx->stage != MESA_SHADER_FRAGMENT)
1724 infix = ".lz";
1725 break;
1726 case nir_texop_txd:
1727 infix = ".d";
1728 break;
1729 case nir_texop_tg4:
1730 name = "llvm.SI.gather4";
1731 infix = ".lz";
1732 break;
1733 case nir_texop_lod:
1734 name = "llvm.SI.getlod";
1735 is_shadow = false;
1736 has_offset = false;
1737 break;
1738 default:
1739 break;
1740 }
1741
1742 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1743 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1744 has_offset ? ".o" : "", type);
1745
1746 if (instr->op == nir_texop_tg4) {
1747 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1748 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1749 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1750 (int)has_offset + (int)is_shadow);
1751 }
1752 }
1753 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1754 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1755
1756 }
1757
1758 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1759 nir_intrinsic_instr *instr)
1760 {
1761 LLVMValueRef index = get_src(ctx, instr->src[0]);
1762 unsigned desc_set = nir_intrinsic_desc_set(instr);
1763 unsigned binding = nir_intrinsic_binding(instr);
1764 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1765 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1766 unsigned base_offset = layout->binding[binding].offset;
1767 LLVMValueRef offset, stride;
1768
1769 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1770 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1771 desc_ptr = ctx->push_constants;
1772 base_offset = ctx->options->layout->push_constant_size;
1773 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1774 stride = LLVMConstInt(ctx->i32, 16, false);
1775 } else
1776 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1777
1778 offset = LLVMConstInt(ctx->i32, base_offset, false);
1779 index = LLVMBuildMul(ctx->builder, index, stride, "");
1780 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1781
1782 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
1783 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1784 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1785
1786 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1787 }
1788
1789 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1790 nir_intrinsic_instr *instr)
1791 {
1792 LLVMValueRef ptr, addr;
1793
1794 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1795 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1796
1797 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
1798 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1799
1800 return LLVMBuildLoad(ctx->builder, ptr, "");
1801 }
1802
1803 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1804 nir_intrinsic_instr *instr)
1805 {
1806 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1807
1808 return get_buffer_size(ctx, desc, false);
1809 }
1810 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1811 nir_intrinsic_instr *instr)
1812 {
1813 const char *store_name;
1814 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
1815 LLVMTypeRef data_type = ctx->f32;
1816 int elem_size_mult = get_elem_bits(ctx, LLVMTypeOf(src_data)) / 32;
1817 int components_32bit = elem_size_mult * instr->num_components;
1818 unsigned writemask = nir_intrinsic_write_mask(instr);
1819 LLVMValueRef base_data, base_offset;
1820 LLVMValueRef params[6];
1821
1822 if (ctx->stage == MESA_SHADER_FRAGMENT)
1823 ctx->shader_info->fs.writes_memory = true;
1824
1825 params[1] = get_src(ctx, instr->src[1]);
1826 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1827 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1828 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1829
1830 if (components_32bit > 1)
1831 data_type = LLVMVectorType(ctx->f32, components_32bit);
1832
1833 base_data = to_float(ctx, src_data);
1834 base_data = trim_vector(ctx, base_data, instr->num_components);
1835 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1836 data_type, "");
1837 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1838 while (writemask) {
1839 int start, count;
1840 LLVMValueRef data;
1841 LLVMValueRef offset;
1842 LLVMValueRef tmp;
1843 u_bit_scan_consecutive_range(&writemask, &start, &count);
1844
1845 /* Due to an LLVM limitation, split 3-element writes
1846 * into a 2-element and a 1-element write. */
1847 if (count == 3) {
1848 writemask |= 1 << (start + 2);
1849 count = 2;
1850 }
1851
1852 start *= elem_size_mult;
1853 count *= elem_size_mult;
1854
1855 if (count > 4) {
1856 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
1857 count = 4;
1858 }
1859
1860 if (count == 4) {
1861 store_name = "llvm.amdgcn.buffer.store.v4f32";
1862 data = base_data;
1863 } else if (count == 2) {
1864 tmp = LLVMBuildExtractElement(ctx->builder,
1865 base_data, LLVMConstInt(ctx->i32, start, false), "");
1866 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1867 ctx->i32zero, "");
1868
1869 tmp = LLVMBuildExtractElement(ctx->builder,
1870 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1871 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1872 ctx->i32one, "");
1873 store_name = "llvm.amdgcn.buffer.store.v2f32";
1874
1875 } else {
1876 assert(count == 1);
1877 if (get_llvm_num_components(base_data) > 1)
1878 data = LLVMBuildExtractElement(ctx->builder, base_data,
1879 LLVMConstInt(ctx->i32, start, false), "");
1880 else
1881 data = base_data;
1882 store_name = "llvm.amdgcn.buffer.store.f32";
1883 }
1884
1885 offset = base_offset;
1886 if (start != 0) {
1887 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1888 }
1889 params[0] = data;
1890 params[3] = offset;
1891 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1892 ctx->voidt, params, 6, 0);
1893 }
1894 }
1895
1896 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1897 nir_intrinsic_instr *instr)
1898 {
1899 const char *name;
1900 LLVMValueRef params[6];
1901 int arg_count = 0;
1902 if (ctx->stage == MESA_SHADER_FRAGMENT)
1903 ctx->shader_info->fs.writes_memory = true;
1904
1905 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1906 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1907 }
1908 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1909 params[arg_count++] = get_src(ctx, instr->src[0]);
1910 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1911 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1912 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1913
1914 switch (instr->intrinsic) {
1915 case nir_intrinsic_ssbo_atomic_add:
1916 name = "llvm.amdgcn.buffer.atomic.add";
1917 break;
1918 case nir_intrinsic_ssbo_atomic_imin:
1919 name = "llvm.amdgcn.buffer.atomic.smin";
1920 break;
1921 case nir_intrinsic_ssbo_atomic_umin:
1922 name = "llvm.amdgcn.buffer.atomic.umin";
1923 break;
1924 case nir_intrinsic_ssbo_atomic_imax:
1925 name = "llvm.amdgcn.buffer.atomic.smax";
1926 break;
1927 case nir_intrinsic_ssbo_atomic_umax:
1928 name = "llvm.amdgcn.buffer.atomic.umax";
1929 break;
1930 case nir_intrinsic_ssbo_atomic_and:
1931 name = "llvm.amdgcn.buffer.atomic.and";
1932 break;
1933 case nir_intrinsic_ssbo_atomic_or:
1934 name = "llvm.amdgcn.buffer.atomic.or";
1935 break;
1936 case nir_intrinsic_ssbo_atomic_xor:
1937 name = "llvm.amdgcn.buffer.atomic.xor";
1938 break;
1939 case nir_intrinsic_ssbo_atomic_exchange:
1940 name = "llvm.amdgcn.buffer.atomic.swap";
1941 break;
1942 case nir_intrinsic_ssbo_atomic_comp_swap:
1943 name = "llvm.amdgcn.buffer.atomic.cmpswap";
1944 break;
1945 default:
1946 abort();
1947 }
1948
1949 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
1950 }
1951
1952 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
1953 nir_intrinsic_instr *instr)
1954 {
1955 LLVMValueRef results[2];
1956 int load_components;
1957 int num_components = instr->num_components;
1958 if (instr->dest.ssa.bit_size == 64)
1959 num_components *= 2;
1960
1961 for (int i = 0; i < num_components; i += load_components) {
1962 load_components = MIN2(num_components - i, 4);
1963 const char *load_name;
1964 LLVMTypeRef data_type = ctx->f32;
1965 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
1966 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
1967
1968 if (load_components == 3)
1969 data_type = LLVMVectorType(ctx->f32, 4);
1970 else if (load_components > 1)
1971 data_type = LLVMVectorType(ctx->f32, load_components);
1972
1973 if (load_components >= 3)
1974 load_name = "llvm.amdgcn.buffer.load.v4f32";
1975 else if (load_components == 2)
1976 load_name = "llvm.amdgcn.buffer.load.v2f32";
1977 else if (load_components == 1)
1978 load_name = "llvm.amdgcn.buffer.load.f32";
1979 else
1980 unreachable("unhandled number of components");
1981
1982 LLVMValueRef params[] = {
1983 get_src(ctx, instr->src[0]),
1984 LLVMConstInt(ctx->i32, 0, false),
1985 offset,
1986 LLVMConstInt(ctx->i1, 0, false),
1987 LLVMConstInt(ctx->i1, 0, false),
1988 };
1989
1990 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
1991
1992 }
1993
1994 LLVMValueRef ret = results[0];
1995 if (num_components > 4 || num_components == 3) {
1996 LLVMValueRef masks[] = {
1997 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1998 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
1999 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2000 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2001 };
2002
2003 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2004 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2005 results[num_components > 4 ? 1 : 0], swizzle, "");
2006 }
2007
2008 return LLVMBuildBitCast(ctx->builder, ret,
2009 get_def_type(ctx, &instr->dest.ssa), "");
2010 }
2011
2012 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2013 nir_intrinsic_instr *instr)
2014 {
2015 LLVMValueRef results[8], ret;
2016 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2017 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2018 int num_components = instr->num_components;
2019
2020 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2021
2022 if (instr->dest.ssa.bit_size == 64)
2023 num_components *= 2;
2024
2025 for (unsigned i = 0; i < num_components; ++i) {
2026 LLVMValueRef params[] = {
2027 rsrc,
2028 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2029 offset, "")
2030 };
2031 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2032 params, 2, AC_FUNC_ATTR_READNONE);
2033 }
2034
2035
2036 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2037 return LLVMBuildBitCast(ctx->builder, ret,
2038 get_def_type(ctx, &instr->dest.ssa), "");
2039 }
2040
2041 static void
2042 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2043 bool vs_in, unsigned *vertex_index_out,
2044 unsigned *const_out, LLVMValueRef *indir_out)
2045 {
2046 unsigned const_offset = 0;
2047 LLVMValueRef offset = NULL;
2048
2049 if (vertex_index_out != NULL) {
2050 tail = tail->child;
2051 nir_deref_array *deref_array = nir_deref_as_array(tail);
2052 *vertex_index_out = deref_array->base_offset;
2053 }
2054
2055 while (tail->child != NULL) {
2056 const struct glsl_type *parent_type = tail->type;
2057 tail = tail->child;
2058
2059 if (tail->deref_type == nir_deref_type_array) {
2060 nir_deref_array *deref_array = nir_deref_as_array(tail);
2061 LLVMValueRef index, stride, local_offset;
2062 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2063
2064 const_offset += size * deref_array->base_offset;
2065 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2066 continue;
2067
2068 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2069 index = get_src(ctx, deref_array->indirect);
2070 stride = LLVMConstInt(ctx->i32, size, 0);
2071 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2072
2073 if (offset)
2074 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2075 else
2076 offset = local_offset;
2077 } else if (tail->deref_type == nir_deref_type_struct) {
2078 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2079
2080 for (unsigned i = 0; i < deref_struct->index; i++) {
2081 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2082 const_offset += glsl_count_attribute_slots(ft, vs_in);
2083 }
2084 } else
2085 unreachable("unsupported deref type");
2086
2087 }
2088
2089 if (const_offset && offset)
2090 offset = LLVMBuildAdd(ctx->builder, offset,
2091 LLVMConstInt(ctx->i32, const_offset, 0),
2092 "");
2093
2094 *const_out = const_offset;
2095 *indir_out = offset;
2096 }
2097
2098 static LLVMValueRef
2099 load_gs_input(struct nir_to_llvm_context *ctx,
2100 nir_intrinsic_instr *instr)
2101 {
2102 LLVMValueRef indir_index, vtx_offset;
2103 unsigned const_index;
2104 LLVMValueRef args[9];
2105 unsigned param, vtx_offset_param;
2106 LLVMValueRef value[4], result;
2107 unsigned vertex_index;
2108 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2109 false, &vertex_index,
2110 &const_index, &indir_index);
2111 vtx_offset_param = vertex_index;
2112 assert(vtx_offset_param < 6);
2113 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2114 LLVMConstInt(ctx->i32, 4, false), "");
2115
2116 for (unsigned i = 0; i < instr->num_components; i++) {
2117 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2118 args[0] = ctx->esgs_ring;
2119 args[1] = vtx_offset;
2120 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2121 args[3] = ctx->i32zero;
2122 args[4] = ctx->i32one; /* OFFEN */
2123 args[5] = ctx->i32zero; /* IDXEN */
2124 args[6] = ctx->i32one; /* GLC */
2125 args[7] = ctx->i32zero; /* SLC */
2126 args[8] = ctx->i32zero; /* TFE */
2127
2128 value[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2129 ctx->i32, args, 9, AC_FUNC_ATTR_READONLY);
2130 }
2131 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2132
2133 return result;
2134 }
2135
2136 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2137 nir_intrinsic_instr *instr)
2138 {
2139 LLVMValueRef values[8];
2140 int idx = instr->variables[0]->var->data.driver_location;
2141 int ve = instr->dest.ssa.num_components;
2142 LLVMValueRef indir_index;
2143 LLVMValueRef ret;
2144 unsigned const_index;
2145 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2146 instr->variables[0]->var->data.mode == nir_var_shader_in;
2147 radv_get_deref_offset(ctx, &instr->variables[0]->deref, vs_in, NULL,
2148 &const_index, &indir_index);
2149
2150 if (instr->dest.ssa.bit_size == 64)
2151 ve *= 2;
2152
2153 switch (instr->variables[0]->var->data.mode) {
2154 case nir_var_shader_in:
2155 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2156 return load_gs_input(ctx, instr);
2157 }
2158 for (unsigned chan = 0; chan < ve; chan++) {
2159 if (indir_index) {
2160 unsigned count = glsl_count_attribute_slots(
2161 instr->variables[0]->var->type,
2162 ctx->stage == MESA_SHADER_VERTEX);
2163 count -= chan / 4;
2164 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2165 &ctx->ac, ctx->inputs + idx + chan, count,
2166 4, false);
2167
2168 values[chan] = LLVMBuildExtractElement(ctx->builder,
2169 tmp_vec,
2170 indir_index, "");
2171 } else
2172 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2173 }
2174 break;
2175 case nir_var_local:
2176 for (unsigned chan = 0; chan < ve; chan++) {
2177 if (indir_index) {
2178 unsigned count = glsl_count_attribute_slots(
2179 instr->variables[0]->var->type, false);
2180 count -= chan / 4;
2181 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2182 &ctx->ac, ctx->locals + idx + chan, count,
2183 4, true);
2184
2185 values[chan] = LLVMBuildExtractElement(ctx->builder,
2186 tmp_vec,
2187 indir_index, "");
2188 } else {
2189 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2190 }
2191 }
2192 break;
2193 case nir_var_shader_out:
2194 for (unsigned chan = 0; chan < ve; chan++) {
2195 if (indir_index) {
2196 unsigned count = glsl_count_attribute_slots(
2197 instr->variables[0]->var->type, false);
2198 count -= chan / 4;
2199 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2200 &ctx->ac, ctx->outputs + idx + chan, count,
2201 4, true);
2202
2203 values[chan] = LLVMBuildExtractElement(ctx->builder,
2204 tmp_vec,
2205 indir_index, "");
2206 } else {
2207 values[chan] = LLVMBuildLoad(ctx->builder,
2208 ctx->outputs[idx + chan + const_index * 4],
2209 "");
2210 }
2211 }
2212 break;
2213 case nir_var_shared: {
2214 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2215 LLVMValueRef derived_ptr;
2216
2217 if (indir_index)
2218 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2219
2220 for (unsigned chan = 0; chan < ve; chan++) {
2221 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2222 if (indir_index)
2223 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2224 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2225
2226 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2227 }
2228 break;
2229 }
2230 default:
2231 unreachable("unhandle variable mode");
2232 }
2233 ret = ac_build_gather_values(&ctx->ac, values, ve);
2234 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2235 }
2236
2237 static void
2238 visit_store_var(struct nir_to_llvm_context *ctx,
2239 nir_intrinsic_instr *instr)
2240 {
2241 LLVMValueRef temp_ptr, value;
2242 int idx = instr->variables[0]->var->data.driver_location;
2243 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2244 int writemask = instr->const_index[0];
2245 LLVMValueRef indir_index;
2246 unsigned const_index;
2247 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2248 NULL, &const_index, &indir_index);
2249
2250 if (get_elem_bits(ctx, LLVMTypeOf(src)) == 64) {
2251 int old_writemask = writemask;
2252
2253 src = LLVMBuildBitCast(ctx->builder, src,
2254 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2255 "");
2256
2257 writemask = 0;
2258 for (unsigned chan = 0; chan < 4; chan++) {
2259 if (old_writemask & (1 << chan))
2260 writemask |= 3u << (2 * chan);
2261 }
2262 }
2263
2264 switch (instr->variables[0]->var->data.mode) {
2265 case nir_var_shader_out:
2266 for (unsigned chan = 0; chan < 8; chan++) {
2267 int stride = 4;
2268 if (!(writemask & (1 << chan)))
2269 continue;
2270
2271 value = llvm_extract_elem(ctx, src, chan);
2272
2273 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2274 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2275 stride = 1;
2276 if (indir_index) {
2277 unsigned count = glsl_count_attribute_slots(
2278 instr->variables[0]->var->type, false);
2279 count -= chan / 4;
2280 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2281 &ctx->ac, ctx->outputs + idx + chan, count,
2282 stride, true);
2283
2284 if (get_llvm_num_components(tmp_vec) > 1) {
2285 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2286 value, indir_index, "");
2287 } else
2288 tmp_vec = value;
2289 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2290 count, stride, tmp_vec);
2291
2292 } else {
2293 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2294
2295 LLVMBuildStore(ctx->builder, value, temp_ptr);
2296 }
2297 }
2298 break;
2299 case nir_var_local:
2300 for (unsigned chan = 0; chan < 8; chan++) {
2301 if (!(writemask & (1 << chan)))
2302 continue;
2303
2304 value = llvm_extract_elem(ctx, src, chan);
2305 if (indir_index) {
2306 unsigned count = glsl_count_attribute_slots(
2307 instr->variables[0]->var->type, false);
2308 count -= chan / 4;
2309 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2310 &ctx->ac, ctx->locals + idx + chan, count,
2311 4, true);
2312
2313 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2314 value, indir_index, "");
2315 build_store_values_extended(ctx, ctx->locals + idx + chan,
2316 count, 4, tmp_vec);
2317 } else {
2318 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2319
2320 LLVMBuildStore(ctx->builder, value, temp_ptr);
2321 }
2322 }
2323 break;
2324 case nir_var_shared: {
2325 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2326
2327 if (indir_index)
2328 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2329
2330 for (unsigned chan = 0; chan < 8; chan++) {
2331 if (!(writemask & (1 << chan)))
2332 continue;
2333 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2334 LLVMValueRef derived_ptr;
2335
2336 if (indir_index)
2337 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2338
2339 value = llvm_extract_elem(ctx, src, chan);
2340 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2341 LLVMBuildStore(ctx->builder,
2342 to_integer(ctx, value), derived_ptr);
2343 }
2344 break;
2345 }
2346 default:
2347 break;
2348 }
2349 }
2350
2351 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2352 {
2353 switch (dim) {
2354 case GLSL_SAMPLER_DIM_BUF:
2355 return 1;
2356 case GLSL_SAMPLER_DIM_1D:
2357 return array ? 2 : 1;
2358 case GLSL_SAMPLER_DIM_2D:
2359 return array ? 3 : 2;
2360 case GLSL_SAMPLER_DIM_MS:
2361 return array ? 4 : 3;
2362 case GLSL_SAMPLER_DIM_3D:
2363 case GLSL_SAMPLER_DIM_CUBE:
2364 return 3;
2365 case GLSL_SAMPLER_DIM_RECT:
2366 case GLSL_SAMPLER_DIM_SUBPASS:
2367 return 2;
2368 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2369 return 3;
2370 default:
2371 break;
2372 }
2373 return 0;
2374 }
2375
2376 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2377 nir_intrinsic_instr *instr)
2378 {
2379 const struct glsl_type *type = instr->variables[0]->var->type;
2380 if(instr->variables[0]->deref.child)
2381 type = instr->variables[0]->deref.child->type;
2382
2383 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2384 LLVMValueRef coords[4];
2385 LLVMValueRef masks[] = {
2386 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2387 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2388 };
2389 LLVMValueRef res;
2390 int count;
2391 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2392 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2393 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2394 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2395 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2396
2397 count = image_type_to_components_count(dim,
2398 glsl_sampler_type_is_array(type));
2399
2400 if (count == 1) {
2401 if (instr->src[0].ssa->num_components)
2402 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2403 else
2404 res = src0;
2405 } else {
2406 int chan;
2407 if (is_ms)
2408 count--;
2409 for (chan = 0; chan < count; ++chan) {
2410 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2411 }
2412
2413 if (add_frag_pos) {
2414 for (chan = 0; chan < count; ++chan)
2415 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2416 }
2417 if (is_ms) {
2418 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2419 count++;
2420 }
2421
2422 if (count == 3) {
2423 coords[3] = LLVMGetUndef(ctx->i32);
2424 count = 4;
2425 }
2426 res = ac_build_gather_values(&ctx->ac, coords, count);
2427 }
2428 return res;
2429 }
2430
2431 static void build_type_name_for_intr(
2432 LLVMTypeRef type,
2433 char *buf, unsigned bufsize)
2434 {
2435 LLVMTypeRef elem_type = type;
2436
2437 assert(bufsize >= 8);
2438
2439 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2440 int ret = snprintf(buf, bufsize, "v%u",
2441 LLVMGetVectorSize(type));
2442 if (ret < 0) {
2443 char *type_name = LLVMPrintTypeToString(type);
2444 fprintf(stderr, "Error building type name for: %s\n",
2445 type_name);
2446 return;
2447 }
2448 elem_type = LLVMGetElementType(type);
2449 buf += ret;
2450 bufsize -= ret;
2451 }
2452 switch (LLVMGetTypeKind(elem_type)) {
2453 default: break;
2454 case LLVMIntegerTypeKind:
2455 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2456 break;
2457 case LLVMFloatTypeKind:
2458 snprintf(buf, bufsize, "f32");
2459 break;
2460 case LLVMDoubleTypeKind:
2461 snprintf(buf, bufsize, "f64");
2462 break;
2463 }
2464 }
2465
2466 static void get_image_intr_name(const char *base_name,
2467 LLVMTypeRef data_type,
2468 LLVMTypeRef coords_type,
2469 LLVMTypeRef rsrc_type,
2470 char *out_name, unsigned out_len)
2471 {
2472 char coords_type_name[8];
2473
2474 build_type_name_for_intr(coords_type, coords_type_name,
2475 sizeof(coords_type_name));
2476
2477 if (HAVE_LLVM <= 0x0309) {
2478 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2479 } else {
2480 char data_type_name[8];
2481 char rsrc_type_name[8];
2482
2483 build_type_name_for_intr(data_type, data_type_name,
2484 sizeof(data_type_name));
2485 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2486 sizeof(rsrc_type_name));
2487 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2488 data_type_name, coords_type_name, rsrc_type_name);
2489 }
2490 }
2491
2492 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2493 nir_intrinsic_instr *instr)
2494 {
2495 LLVMValueRef params[7];
2496 LLVMValueRef res;
2497 char intrinsic_name[64];
2498 const nir_variable *var = instr->variables[0]->var;
2499 const struct glsl_type *type = var->type;
2500 if(instr->variables[0]->deref.child)
2501 type = instr->variables[0]->deref.child->type;
2502
2503 type = glsl_without_array(type);
2504 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2505 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2506 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2507 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2508 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2509 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2510 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2511 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2512 params, 5, 0);
2513
2514 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2515 res = to_integer(ctx, res);
2516 } else {
2517 bool is_da = glsl_sampler_type_is_array(type) ||
2518 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2519 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2520 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2521 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2522
2523 params[0] = get_image_coords(ctx, instr);
2524 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2525 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2526 if (HAVE_LLVM <= 0x0309) {
2527 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2528 params[4] = da;
2529 params[5] = glc;
2530 params[6] = slc;
2531 } else {
2532 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2533 params[3] = glc;
2534 params[4] = slc;
2535 params[5] = lwe;
2536 params[6] = da;
2537 }
2538
2539 get_image_intr_name("llvm.amdgcn.image.load",
2540 ctx->v4f32, /* vdata */
2541 LLVMTypeOf(params[0]), /* coords */
2542 LLVMTypeOf(params[1]), /* rsrc */
2543 intrinsic_name, sizeof(intrinsic_name));
2544
2545 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2546 params, 7, AC_FUNC_ATTR_READONLY);
2547 }
2548 return to_integer(ctx, res);
2549 }
2550
2551 static void visit_image_store(struct nir_to_llvm_context *ctx,
2552 nir_intrinsic_instr *instr)
2553 {
2554 LLVMValueRef params[8];
2555 char intrinsic_name[64];
2556 const nir_variable *var = instr->variables[0]->var;
2557 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2558 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2559 const struct glsl_type *type = glsl_without_array(var->type);
2560
2561 if (ctx->stage == MESA_SHADER_FRAGMENT)
2562 ctx->shader_info->fs.writes_memory = true;
2563
2564 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2565 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2566 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2567 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2568 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2569 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2570 params[4] = i1false; /* glc */
2571 params[5] = i1false; /* slc */
2572 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2573 params, 6, 0);
2574 } else {
2575 bool is_da = glsl_sampler_type_is_array(type) ||
2576 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2577 LLVMValueRef da = is_da ? i1true : i1false;
2578 LLVMValueRef glc = i1false;
2579 LLVMValueRef slc = i1false;
2580
2581 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2582 params[1] = get_image_coords(ctx, instr); /* coords */
2583 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2584 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2585 if (HAVE_LLVM <= 0x0309) {
2586 params[4] = i1false; /* r128 */
2587 params[5] = da;
2588 params[6] = glc;
2589 params[7] = slc;
2590 } else {
2591 LLVMValueRef lwe = i1false;
2592 params[4] = glc;
2593 params[5] = slc;
2594 params[6] = lwe;
2595 params[7] = da;
2596 }
2597
2598 get_image_intr_name("llvm.amdgcn.image.store",
2599 LLVMTypeOf(params[0]), /* vdata */
2600 LLVMTypeOf(params[1]), /* coords */
2601 LLVMTypeOf(params[2]), /* rsrc */
2602 intrinsic_name, sizeof(intrinsic_name));
2603
2604 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2605 params, 8, 0);
2606 }
2607
2608 }
2609
2610 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2611 nir_intrinsic_instr *instr)
2612 {
2613 LLVMValueRef params[6];
2614 int param_count = 0;
2615 const nir_variable *var = instr->variables[0]->var;
2616 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2617 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2618 const char *base_name = "llvm.amdgcn.image.atomic";
2619 const char *atomic_name;
2620 LLVMValueRef coords;
2621 char intrinsic_name[32], coords_type[8];
2622 const struct glsl_type *type = glsl_without_array(var->type);
2623
2624 if (ctx->stage == MESA_SHADER_FRAGMENT)
2625 ctx->shader_info->fs.writes_memory = true;
2626
2627 params[param_count++] = get_src(ctx, instr->src[2]);
2628 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2629 params[param_count++] = get_src(ctx, instr->src[3]);
2630
2631 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2632 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2633 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2634 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2635 params[param_count++] = ctx->i32zero; /* voffset */
2636 params[param_count++] = i1false; /* glc */
2637 params[param_count++] = i1false; /* slc */
2638 } else {
2639 bool da = glsl_sampler_type_is_array(type) ||
2640 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2641
2642 coords = params[param_count++] = get_image_coords(ctx, instr);
2643 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2644 params[param_count++] = i1false; /* r128 */
2645 params[param_count++] = da ? i1true : i1false; /* da */
2646 params[param_count++] = i1false; /* slc */
2647 }
2648
2649 switch (instr->intrinsic) {
2650 case nir_intrinsic_image_atomic_add:
2651 atomic_name = "add";
2652 break;
2653 case nir_intrinsic_image_atomic_min:
2654 atomic_name = "smin";
2655 break;
2656 case nir_intrinsic_image_atomic_max:
2657 atomic_name = "smax";
2658 break;
2659 case nir_intrinsic_image_atomic_and:
2660 atomic_name = "and";
2661 break;
2662 case nir_intrinsic_image_atomic_or:
2663 atomic_name = "or";
2664 break;
2665 case nir_intrinsic_image_atomic_xor:
2666 atomic_name = "xor";
2667 break;
2668 case nir_intrinsic_image_atomic_exchange:
2669 atomic_name = "swap";
2670 break;
2671 case nir_intrinsic_image_atomic_comp_swap:
2672 atomic_name = "cmpswap";
2673 break;
2674 default:
2675 abort();
2676 }
2677 build_int_type_name(LLVMTypeOf(coords),
2678 coords_type, sizeof(coords_type));
2679
2680 snprintf(intrinsic_name, sizeof(intrinsic_name),
2681 "%s.%s.%s", base_name, atomic_name, coords_type);
2682 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2683 }
2684
2685 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2686 nir_intrinsic_instr *instr)
2687 {
2688 LLVMValueRef res;
2689 LLVMValueRef params[10];
2690 const nir_variable *var = instr->variables[0]->var;
2691 const struct glsl_type *type = instr->variables[0]->var->type;
2692 bool da = glsl_sampler_type_is_array(var->type) ||
2693 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2694 if(instr->variables[0]->deref.child)
2695 type = instr->variables[0]->deref.child->type;
2696
2697 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2698 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2699 params[0] = ctx->i32zero;
2700 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2701 params[2] = LLVMConstInt(ctx->i32, 15, false);
2702 params[3] = ctx->i32zero;
2703 params[4] = ctx->i32zero;
2704 params[5] = da ? ctx->i32one : ctx->i32zero;
2705 params[6] = ctx->i32zero;
2706 params[7] = ctx->i32zero;
2707 params[8] = ctx->i32zero;
2708 params[9] = ctx->i32zero;
2709
2710 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2711 params, 10, AC_FUNC_ATTR_READNONE);
2712
2713 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2714 glsl_sampler_type_is_array(type)) {
2715 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2716 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2717 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2718 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2719 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2720 }
2721 return res;
2722 }
2723
2724 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2725 {
2726 LLVMValueRef args[1] = {
2727 LLVMConstInt(ctx->i32, 0xf70, false),
2728 };
2729 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2730 ctx->voidt, args, 1, 0);
2731 }
2732
2733 static void emit_barrier(struct nir_to_llvm_context *ctx)
2734 {
2735 // TODO tess
2736 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2737 ctx->voidt, NULL, 0, 0);
2738 }
2739
2740 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2741 nir_intrinsic_instr *instr)
2742 {
2743 LLVMValueRef cond;
2744 ctx->shader_info->fs.can_discard = true;
2745
2746 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2747 get_src(ctx, instr->src[0]),
2748 ctx->i32zero, "");
2749
2750 cond = LLVMBuildSelect(ctx->builder, cond,
2751 LLVMConstReal(ctx->f32, -1.0f),
2752 ctx->f32zero, "");
2753 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2754 ctx->voidt,
2755 &cond, 1, 0);
2756 }
2757
2758 static LLVMValueRef
2759 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2760 {
2761 LLVMValueRef result;
2762 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
2763 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2764 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2765
2766 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2767 }
2768
2769 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2770 nir_intrinsic_instr *instr)
2771 {
2772 LLVMValueRef ptr, result;
2773 int idx = instr->variables[0]->var->data.driver_location;
2774 LLVMValueRef src = get_src(ctx, instr->src[0]);
2775 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2776
2777 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2778 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2779 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2780 ptr, src, src1,
2781 LLVMAtomicOrderingSequentiallyConsistent,
2782 LLVMAtomicOrderingSequentiallyConsistent,
2783 false);
2784 } else {
2785 LLVMAtomicRMWBinOp op;
2786 switch (instr->intrinsic) {
2787 case nir_intrinsic_var_atomic_add:
2788 op = LLVMAtomicRMWBinOpAdd;
2789 break;
2790 case nir_intrinsic_var_atomic_umin:
2791 op = LLVMAtomicRMWBinOpUMin;
2792 break;
2793 case nir_intrinsic_var_atomic_umax:
2794 op = LLVMAtomicRMWBinOpUMax;
2795 break;
2796 case nir_intrinsic_var_atomic_imin:
2797 op = LLVMAtomicRMWBinOpMin;
2798 break;
2799 case nir_intrinsic_var_atomic_imax:
2800 op = LLVMAtomicRMWBinOpMax;
2801 break;
2802 case nir_intrinsic_var_atomic_and:
2803 op = LLVMAtomicRMWBinOpAnd;
2804 break;
2805 case nir_intrinsic_var_atomic_or:
2806 op = LLVMAtomicRMWBinOpOr;
2807 break;
2808 case nir_intrinsic_var_atomic_xor:
2809 op = LLVMAtomicRMWBinOpXor;
2810 break;
2811 case nir_intrinsic_var_atomic_exchange:
2812 op = LLVMAtomicRMWBinOpXchg;
2813 break;
2814 default:
2815 return NULL;
2816 }
2817
2818 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2819 LLVMAtomicOrderingSequentiallyConsistent,
2820 false);
2821 }
2822 return result;
2823 }
2824
2825 #define INTERP_CENTER 0
2826 #define INTERP_CENTROID 1
2827 #define INTERP_SAMPLE 2
2828
2829 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2830 enum glsl_interp_mode interp, unsigned location)
2831 {
2832 switch (interp) {
2833 case INTERP_MODE_FLAT:
2834 default:
2835 return NULL;
2836 case INTERP_MODE_SMOOTH:
2837 case INTERP_MODE_NONE:
2838 if (location == INTERP_CENTER)
2839 return ctx->persp_center;
2840 else if (location == INTERP_CENTROID)
2841 return ctx->persp_centroid;
2842 else if (location == INTERP_SAMPLE)
2843 return ctx->persp_sample;
2844 break;
2845 case INTERP_MODE_NOPERSPECTIVE:
2846 if (location == INTERP_CENTER)
2847 return ctx->linear_center;
2848 else if (location == INTERP_CENTROID)
2849 return ctx->linear_centroid;
2850 else if (location == INTERP_SAMPLE)
2851 return ctx->linear_sample;
2852 break;
2853 }
2854 return NULL;
2855 }
2856
2857 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2858 LLVMValueRef sample_id)
2859 {
2860 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2861 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2862 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2863 LLVMValueRef result[2];
2864
2865 result[0] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset0);
2866 result[1] = ac_build_indexed_load_const(&ctx->ac, ctx->sample_positions, offset1);
2867
2868 return ac_build_gather_values(&ctx->ac, result, 2);
2869 }
2870
2871 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2872 {
2873 LLVMValueRef values[2];
2874
2875 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2876 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2877 return ac_build_gather_values(&ctx->ac, values, 2);
2878 }
2879
2880 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2881 nir_intrinsic_instr *instr)
2882 {
2883 LLVMValueRef result[2];
2884 LLVMValueRef interp_param, attr_number;
2885 unsigned location;
2886 unsigned chan;
2887 LLVMValueRef src_c0, src_c1;
2888 LLVMValueRef src0;
2889 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2890 switch (instr->intrinsic) {
2891 case nir_intrinsic_interp_var_at_centroid:
2892 location = INTERP_CENTROID;
2893 break;
2894 case nir_intrinsic_interp_var_at_sample:
2895 case nir_intrinsic_interp_var_at_offset:
2896 location = INTERP_SAMPLE;
2897 src0 = get_src(ctx, instr->src[0]);
2898 break;
2899 default:
2900 break;
2901 }
2902
2903 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2904 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2905 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2906 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2907 LLVMValueRef sample_position;
2908 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2909
2910 /* fetch sample ID */
2911 sample_position = load_sample_position(ctx, src0);
2912
2913 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2914 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2915 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2916 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2917 }
2918 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2919 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2920
2921 if (location == INTERP_SAMPLE) {
2922 LLVMValueRef ij_out[2];
2923 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2924
2925 /*
2926 * take the I then J parameters, and the DDX/Y for it, and
2927 * calculate the IJ inputs for the interpolator.
2928 * temp1 = ddx * offset/sample.x + I;
2929 * interp_param.I = ddy * offset/sample.y + temp1;
2930 * temp1 = ddx * offset/sample.x + J;
2931 * interp_param.J = ddy * offset/sample.y + temp1;
2932 */
2933 for (unsigned i = 0; i < 2; i++) {
2934 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2935 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2936 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2937 ddxy_out, ix_ll, "");
2938 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2939 ddxy_out, iy_ll, "");
2940 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2941 interp_param, ix_ll, "");
2942 LLVMValueRef temp1, temp2;
2943
2944 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2945 ctx->f32, "");
2946
2947 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2948 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2949
2950 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2951 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2952
2953 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2954 temp2, ctx->i32, "");
2955 }
2956 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2957
2958 }
2959
2960 for (chan = 0; chan < 2; chan++) {
2961 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2962
2963 if (interp_param) {
2964 interp_param = LLVMBuildBitCast(ctx->builder,
2965 interp_param, LLVMVectorType(ctx->f32, 2), "");
2966 LLVMValueRef i = LLVMBuildExtractElement(
2967 ctx->builder, interp_param, ctx->i32zero, "");
2968 LLVMValueRef j = LLVMBuildExtractElement(
2969 ctx->builder, interp_param, ctx->i32one, "");
2970
2971 result[chan] = ac_build_fs_interp(&ctx->ac,
2972 llvm_chan, attr_number,
2973 ctx->prim_mask, i, j);
2974 } else {
2975 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
2976 LLVMConstInt(ctx->i32, 2, false),
2977 llvm_chan, attr_number,
2978 ctx->prim_mask);
2979 }
2980 }
2981 return ac_build_gather_values(&ctx->ac, result, 2);
2982 }
2983
2984 static void
2985 visit_emit_vertex(struct nir_to_llvm_context *ctx,
2986 nir_intrinsic_instr *instr)
2987 {
2988 LLVMValueRef gs_next_vertex;
2989 LLVMValueRef can_emit, kill;
2990 int idx;
2991
2992 assert(instr->const_index[0] == 0);
2993 /* Write vertex attribute values to GSVS ring */
2994 gs_next_vertex = LLVMBuildLoad(ctx->builder,
2995 ctx->gs_next_vertex,
2996 "");
2997
2998 /* If this thread has already emitted the declared maximum number of
2999 * vertices, kill it: excessive vertex emissions are not supposed to
3000 * have any effect, and GS threads have no externally observable
3001 * effects other than emitting vertices.
3002 */
3003 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3004 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3005
3006 kill = LLVMBuildSelect(ctx->builder, can_emit,
3007 LLVMConstReal(ctx->f32, 1.0f),
3008 LLVMConstReal(ctx->f32, -1.0f), "");
3009 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3010 ctx->voidt, &kill, 1, 0);
3011
3012 /* loop num outputs */
3013 idx = 0;
3014 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3015 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3016 if (!(ctx->output_mask & (1ull << i)))
3017 continue;
3018
3019 for (unsigned j = 0; j < 4; j++) {
3020 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3021 out_ptr[j], "");
3022 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (idx * 4 + j) * ctx->gs_max_out_vertices, false);
3023 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3024 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3025
3026 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3027
3028 ac_build_tbuffer_store(&ctx->ac, ctx->gsvs_ring,
3029 out_val, 1,
3030 voffset, ctx->gs2vs_offset, 0,
3031 V_008F0C_BUF_DATA_FORMAT_32,
3032 V_008F0C_BUF_NUM_FORMAT_UINT,
3033 1, 0, 1, 1, 0);
3034 }
3035 idx++;
3036 }
3037
3038 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3039 ctx->i32one, "");
3040 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3041
3042 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3043 }
3044
3045 static void
3046 visit_end_primitive(struct nir_to_llvm_context *ctx,
3047 nir_intrinsic_instr *instr)
3048 {
3049 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3050 }
3051
3052 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3053 nir_intrinsic_instr *instr)
3054 {
3055 LLVMValueRef result = NULL;
3056
3057 switch (instr->intrinsic) {
3058 case nir_intrinsic_load_work_group_id: {
3059 result = ctx->workgroup_ids;
3060 break;
3061 }
3062 case nir_intrinsic_load_base_vertex: {
3063 result = ctx->base_vertex;
3064 break;
3065 }
3066 case nir_intrinsic_load_vertex_id_zero_base: {
3067 result = ctx->vertex_id;
3068 break;
3069 }
3070 case nir_intrinsic_load_local_invocation_id: {
3071 result = ctx->local_invocation_ids;
3072 break;
3073 }
3074 case nir_intrinsic_load_base_instance:
3075 result = ctx->start_instance;
3076 break;
3077 case nir_intrinsic_load_draw_id:
3078 result = ctx->draw_index;
3079 break;
3080 case nir_intrinsic_load_invocation_id:
3081 result = ctx->gs_invocation_id;
3082 break;
3083 case nir_intrinsic_load_primitive_id:
3084 if (ctx->stage == MESA_SHADER_GEOMETRY)
3085 result = ctx->gs_prim_id;
3086 else
3087 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3088 break;
3089 case nir_intrinsic_load_sample_id:
3090 ctx->shader_info->fs.force_persample = true;
3091 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3092 break;
3093 case nir_intrinsic_load_sample_pos:
3094 ctx->shader_info->fs.force_persample = true;
3095 result = load_sample_pos(ctx);
3096 break;
3097 case nir_intrinsic_load_front_face:
3098 result = ctx->front_face;
3099 break;
3100 case nir_intrinsic_load_instance_id:
3101 result = ctx->instance_id;
3102 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3103 ctx->shader_info->vs.vgpr_comp_cnt);
3104 break;
3105 case nir_intrinsic_load_num_work_groups:
3106 result = ctx->num_work_groups;
3107 break;
3108 case nir_intrinsic_load_local_invocation_index:
3109 result = visit_load_local_invocation_index(ctx);
3110 break;
3111 case nir_intrinsic_load_push_constant:
3112 result = visit_load_push_constant(ctx, instr);
3113 break;
3114 case nir_intrinsic_vulkan_resource_index:
3115 result = visit_vulkan_resource_index(ctx, instr);
3116 break;
3117 case nir_intrinsic_store_ssbo:
3118 visit_store_ssbo(ctx, instr);
3119 break;
3120 case nir_intrinsic_load_ssbo:
3121 result = visit_load_buffer(ctx, instr);
3122 break;
3123 case nir_intrinsic_ssbo_atomic_add:
3124 case nir_intrinsic_ssbo_atomic_imin:
3125 case nir_intrinsic_ssbo_atomic_umin:
3126 case nir_intrinsic_ssbo_atomic_imax:
3127 case nir_intrinsic_ssbo_atomic_umax:
3128 case nir_intrinsic_ssbo_atomic_and:
3129 case nir_intrinsic_ssbo_atomic_or:
3130 case nir_intrinsic_ssbo_atomic_xor:
3131 case nir_intrinsic_ssbo_atomic_exchange:
3132 case nir_intrinsic_ssbo_atomic_comp_swap:
3133 result = visit_atomic_ssbo(ctx, instr);
3134 break;
3135 case nir_intrinsic_load_ubo:
3136 result = visit_load_ubo_buffer(ctx, instr);
3137 break;
3138 case nir_intrinsic_get_buffer_size:
3139 result = visit_get_buffer_size(ctx, instr);
3140 break;
3141 case nir_intrinsic_load_var:
3142 result = visit_load_var(ctx, instr);
3143 break;
3144 case nir_intrinsic_store_var:
3145 visit_store_var(ctx, instr);
3146 break;
3147 case nir_intrinsic_image_load:
3148 result = visit_image_load(ctx, instr);
3149 break;
3150 case nir_intrinsic_image_store:
3151 visit_image_store(ctx, instr);
3152 break;
3153 case nir_intrinsic_image_atomic_add:
3154 case nir_intrinsic_image_atomic_min:
3155 case nir_intrinsic_image_atomic_max:
3156 case nir_intrinsic_image_atomic_and:
3157 case nir_intrinsic_image_atomic_or:
3158 case nir_intrinsic_image_atomic_xor:
3159 case nir_intrinsic_image_atomic_exchange:
3160 case nir_intrinsic_image_atomic_comp_swap:
3161 result = visit_image_atomic(ctx, instr);
3162 break;
3163 case nir_intrinsic_image_size:
3164 result = visit_image_size(ctx, instr);
3165 break;
3166 case nir_intrinsic_discard:
3167 ctx->shader_info->fs.can_discard = true;
3168 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3169 ctx->voidt,
3170 NULL, 0, 0);
3171 break;
3172 case nir_intrinsic_discard_if:
3173 emit_discard_if(ctx, instr);
3174 break;
3175 case nir_intrinsic_memory_barrier:
3176 emit_waitcnt(ctx);
3177 break;
3178 case nir_intrinsic_barrier:
3179 emit_barrier(ctx);
3180 break;
3181 case nir_intrinsic_var_atomic_add:
3182 case nir_intrinsic_var_atomic_imin:
3183 case nir_intrinsic_var_atomic_umin:
3184 case nir_intrinsic_var_atomic_imax:
3185 case nir_intrinsic_var_atomic_umax:
3186 case nir_intrinsic_var_atomic_and:
3187 case nir_intrinsic_var_atomic_or:
3188 case nir_intrinsic_var_atomic_xor:
3189 case nir_intrinsic_var_atomic_exchange:
3190 case nir_intrinsic_var_atomic_comp_swap:
3191 result = visit_var_atomic(ctx, instr);
3192 break;
3193 case nir_intrinsic_interp_var_at_centroid:
3194 case nir_intrinsic_interp_var_at_sample:
3195 case nir_intrinsic_interp_var_at_offset:
3196 result = visit_interp(ctx, instr);
3197 break;
3198 case nir_intrinsic_emit_vertex:
3199 visit_emit_vertex(ctx, instr);
3200 break;
3201 case nir_intrinsic_end_primitive:
3202 visit_end_primitive(ctx, instr);
3203 break;
3204 default:
3205 fprintf(stderr, "Unknown intrinsic: ");
3206 nir_print_instr(&instr->instr, stderr);
3207 fprintf(stderr, "\n");
3208 break;
3209 }
3210 if (result) {
3211 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3212 }
3213 }
3214
3215 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3216 nir_deref_var *deref,
3217 enum desc_type desc_type)
3218 {
3219 unsigned desc_set = deref->var->data.descriptor_set;
3220 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3221 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3222 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3223 unsigned offset = binding->offset;
3224 unsigned stride = binding->size;
3225 unsigned type_size;
3226 LLVMBuilderRef builder = ctx->builder;
3227 LLVMTypeRef type;
3228 LLVMValueRef index = NULL;
3229
3230 assert(deref->var->data.binding < layout->binding_count);
3231
3232 switch (desc_type) {
3233 case DESC_IMAGE:
3234 type = ctx->v8i32;
3235 type_size = 32;
3236 break;
3237 case DESC_FMASK:
3238 type = ctx->v8i32;
3239 offset += 32;
3240 type_size = 32;
3241 break;
3242 case DESC_SAMPLER:
3243 type = ctx->v4i32;
3244 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3245 offset += 64;
3246
3247 type_size = 16;
3248 break;
3249 case DESC_BUFFER:
3250 type = ctx->v4i32;
3251 type_size = 16;
3252 break;
3253 default:
3254 unreachable("invalid desc_type\n");
3255 }
3256
3257 if (deref->deref.child) {
3258 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3259
3260 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3261 offset += child->base_offset * stride;
3262 if (child->deref_array_type == nir_deref_array_type_indirect) {
3263 index = get_src(ctx, child->indirect);
3264 }
3265 }
3266
3267 assert(stride % type_size == 0);
3268
3269 if (!index)
3270 index = ctx->i32zero;
3271
3272 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3273
3274 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
3275 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3276
3277 return ac_build_indexed_load_const(&ctx->ac, list, index);
3278 }
3279
3280 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3281 struct ac_tex_info *tinfo,
3282 nir_tex_instr *instr,
3283 nir_texop op,
3284 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3285 LLVMValueRef *param, unsigned count,
3286 unsigned dmask)
3287 {
3288 int num_args;
3289 unsigned is_rect = 0;
3290 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3291
3292 if (op == nir_texop_lod)
3293 da = false;
3294 /* Pad to power of two vector */
3295 while (count < util_next_power_of_two(count))
3296 param[count++] = LLVMGetUndef(ctx->i32);
3297
3298 if (count > 1)
3299 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3300 else
3301 tinfo->args[0] = param[0];
3302
3303 tinfo->args[1] = res_ptr;
3304 num_args = 2;
3305
3306 if (op == nir_texop_txf ||
3307 op == nir_texop_txf_ms ||
3308 op == nir_texop_query_levels ||
3309 op == nir_texop_texture_samples ||
3310 op == nir_texop_txs)
3311 tinfo->dst_type = ctx->v4i32;
3312 else {
3313 tinfo->dst_type = ctx->v4f32;
3314 tinfo->args[num_args++] = samp_ptr;
3315 }
3316
3317 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3318 tinfo->args[0] = res_ptr;
3319 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3320 tinfo->args[2] = param[0];
3321 tinfo->arg_count = 3;
3322 return;
3323 }
3324
3325 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3326 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3327 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3328 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3329 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3330 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3331 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3332 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3333
3334 tinfo->arg_count = num_args;
3335 }
3336
3337 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3338 *
3339 * SI-CI:
3340 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3341 * filtering manually. The driver sets img7 to a mask clearing
3342 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3343 * s_and_b32 samp0, samp0, img7
3344 *
3345 * VI:
3346 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3347 */
3348 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3349 LLVMValueRef res, LLVMValueRef samp)
3350 {
3351 LLVMBuilderRef builder = ctx->builder;
3352 LLVMValueRef img7, samp0;
3353
3354 if (ctx->options->chip_class >= VI)
3355 return samp;
3356
3357 img7 = LLVMBuildExtractElement(builder, res,
3358 LLVMConstInt(ctx->i32, 7, 0), "");
3359 samp0 = LLVMBuildExtractElement(builder, samp,
3360 LLVMConstInt(ctx->i32, 0, 0), "");
3361 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3362 return LLVMBuildInsertElement(builder, samp, samp0,
3363 LLVMConstInt(ctx->i32, 0, 0), "");
3364 }
3365
3366 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3367 nir_tex_instr *instr,
3368 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3369 LLVMValueRef *fmask_ptr)
3370 {
3371 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3372 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3373 else
3374 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3375 if (samp_ptr) {
3376 if (instr->sampler)
3377 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3378 else
3379 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3380 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3381 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3382 }
3383 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3384 instr->op == nir_texop_samples_identical))
3385 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3386 }
3387
3388 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
3389 LLVMValueRef coord)
3390 {
3391 coord = to_float(ctx, coord);
3392 coord = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
3393 coord = to_integer(ctx, coord);
3394 return coord;
3395 }
3396
3397 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3398 {
3399 LLVMValueRef result = NULL;
3400 struct ac_tex_info tinfo = { 0 };
3401 unsigned dmask = 0xf;
3402 LLVMValueRef address[16];
3403 LLVMValueRef coords[5];
3404 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3405 LLVMValueRef bias = NULL, offsets = NULL;
3406 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3407 LLVMValueRef ddx = NULL, ddy = NULL;
3408 LLVMValueRef derivs[6];
3409 unsigned chan, count = 0;
3410 unsigned const_src = 0, num_deriv_comp = 0;
3411
3412 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3413
3414 for (unsigned i = 0; i < instr->num_srcs; i++) {
3415 switch (instr->src[i].src_type) {
3416 case nir_tex_src_coord:
3417 coord = get_src(ctx, instr->src[i].src);
3418 break;
3419 case nir_tex_src_projector:
3420 break;
3421 case nir_tex_src_comparator:
3422 comparator = get_src(ctx, instr->src[i].src);
3423 break;
3424 case nir_tex_src_offset:
3425 offsets = get_src(ctx, instr->src[i].src);
3426 const_src = i;
3427 break;
3428 case nir_tex_src_bias:
3429 bias = get_src(ctx, instr->src[i].src);
3430 break;
3431 case nir_tex_src_lod:
3432 lod = get_src(ctx, instr->src[i].src);
3433 break;
3434 case nir_tex_src_ms_index:
3435 sample_index = get_src(ctx, instr->src[i].src);
3436 break;
3437 case nir_tex_src_ms_mcs:
3438 break;
3439 case nir_tex_src_ddx:
3440 ddx = get_src(ctx, instr->src[i].src);
3441 num_deriv_comp = instr->src[i].src.ssa->num_components;
3442 break;
3443 case nir_tex_src_ddy:
3444 ddy = get_src(ctx, instr->src[i].src);
3445 break;
3446 case nir_tex_src_texture_offset:
3447 case nir_tex_src_sampler_offset:
3448 case nir_tex_src_plane:
3449 default:
3450 break;
3451 }
3452 }
3453
3454 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3455 result = get_buffer_size(ctx, res_ptr, false);
3456 goto write_result;
3457 }
3458
3459 if (instr->op == nir_texop_texture_samples) {
3460 LLVMValueRef res, samples, is_msaa;
3461 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3462 samples = LLVMBuildExtractElement(ctx->builder, res,
3463 LLVMConstInt(ctx->i32, 3, false), "");
3464 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3465 LLVMConstInt(ctx->i32, 28, false), "");
3466 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3467 LLVMConstInt(ctx->i32, 0xe, false), "");
3468 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3469 LLVMConstInt(ctx->i32, 0xe, false), "");
3470
3471 samples = LLVMBuildLShr(ctx->builder, samples,
3472 LLVMConstInt(ctx->i32, 16, false), "");
3473 samples = LLVMBuildAnd(ctx->builder, samples,
3474 LLVMConstInt(ctx->i32, 0xf, false), "");
3475 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3476 samples, "");
3477 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3478 ctx->i32one, "");
3479 result = samples;
3480 goto write_result;
3481 }
3482
3483 if (coord)
3484 for (chan = 0; chan < instr->coord_components; chan++)
3485 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3486
3487 if (offsets && instr->op != nir_texop_txf) {
3488 LLVMValueRef offset[3], pack;
3489 for (chan = 0; chan < 3; ++chan)
3490 offset[chan] = ctx->i32zero;
3491
3492 tinfo.has_offset = true;
3493 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3494 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3495 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3496 LLVMConstInt(ctx->i32, 0x3f, false), "");
3497 if (chan)
3498 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3499 LLVMConstInt(ctx->i32, chan * 8, false), "");
3500 }
3501 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3502 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3503 address[count++] = pack;
3504
3505 }
3506 /* pack LOD bias value */
3507 if (instr->op == nir_texop_txb && bias) {
3508 address[count++] = bias;
3509 }
3510
3511 /* Pack depth comparison value */
3512 if (instr->is_shadow && comparator) {
3513 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3514 }
3515
3516 /* pack derivatives */
3517 if (ddx || ddy) {
3518 switch (instr->sampler_dim) {
3519 case GLSL_SAMPLER_DIM_3D:
3520 case GLSL_SAMPLER_DIM_CUBE:
3521 num_deriv_comp = 3;
3522 break;
3523 case GLSL_SAMPLER_DIM_2D:
3524 default:
3525 num_deriv_comp = 2;
3526 break;
3527 case GLSL_SAMPLER_DIM_1D:
3528 num_deriv_comp = 1;
3529 break;
3530 }
3531
3532 for (unsigned i = 0; i < num_deriv_comp; i++) {
3533 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3534 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3535 }
3536 }
3537
3538 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3539 for (chan = 0; chan < instr->coord_components; chan++)
3540 coords[chan] = to_float(ctx, coords[chan]);
3541 if (instr->coord_components == 3)
3542 coords[3] = LLVMGetUndef(ctx->f32);
3543 ac_prepare_cube_coords(&ctx->ac,
3544 instr->op == nir_texop_txd, instr->is_array,
3545 coords, derivs);
3546 if (num_deriv_comp)
3547 num_deriv_comp--;
3548 }
3549
3550 if (ddx || ddy) {
3551 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3552 address[count++] = derivs[i];
3553 }
3554
3555 /* Pack texture coordinates */
3556 if (coord) {
3557 address[count++] = coords[0];
3558 if (instr->coord_components > 1) {
3559 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
3560 coords[1] = apply_round_slice(ctx, coords[1]);
3561 }
3562 address[count++] = coords[1];
3563 }
3564 if (instr->coord_components > 2) {
3565 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3566 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3567 coords[2] = apply_round_slice(ctx, coords[2]);
3568 }
3569 address[count++] = coords[2];
3570 }
3571 }
3572
3573 /* Pack LOD */
3574 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3575 address[count++] = lod;
3576 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3577 address[count++] = sample_index;
3578 } else if(instr->op == nir_texop_txs) {
3579 count = 0;
3580 if (lod)
3581 address[count++] = lod;
3582 else
3583 address[count++] = ctx->i32zero;
3584 }
3585
3586 for (chan = 0; chan < count; chan++) {
3587 address[chan] = LLVMBuildBitCast(ctx->builder,
3588 address[chan], ctx->i32, "");
3589 }
3590
3591 if (instr->op == nir_texop_samples_identical) {
3592 LLVMValueRef txf_address[4];
3593 struct ac_tex_info txf_info = { 0 };
3594 unsigned txf_count = count;
3595 memcpy(txf_address, address, sizeof(txf_address));
3596
3597 if (!instr->is_array)
3598 txf_address[2] = ctx->i32zero;
3599 txf_address[3] = ctx->i32zero;
3600
3601 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3602 fmask_ptr, NULL,
3603 txf_address, txf_count, 0xf);
3604
3605 result = build_tex_intrinsic(ctx, instr, &txf_info);
3606
3607 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3608 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3609 goto write_result;
3610 }
3611
3612 /* Adjust the sample index according to FMASK.
3613 *
3614 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3615 * which is the identity mapping. Each nibble says which physical sample
3616 * should be fetched to get that sample.
3617 *
3618 * For example, 0x11111100 means there are only 2 samples stored and
3619 * the second sample covers 3/4 of the pixel. When reading samples 0
3620 * and 1, return physical sample 0 (determined by the first two 0s
3621 * in FMASK), otherwise return physical sample 1.
3622 *
3623 * The sample index should be adjusted as follows:
3624 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3625 */
3626 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
3627 instr->op != nir_texop_txs) {
3628 LLVMValueRef txf_address[4];
3629 struct ac_tex_info txf_info = { 0 };
3630 unsigned txf_count = count;
3631 memcpy(txf_address, address, sizeof(txf_address));
3632
3633 if (!instr->is_array)
3634 txf_address[2] = ctx->i32zero;
3635 txf_address[3] = ctx->i32zero;
3636
3637 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3638 fmask_ptr, NULL,
3639 txf_address, txf_count, 0xf);
3640
3641 result = build_tex_intrinsic(ctx, instr, &txf_info);
3642 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3643 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3644
3645 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3646 result,
3647 ctx->i32zero, "");
3648
3649 unsigned sample_chan = instr->is_array ? 3 : 2;
3650
3651 LLVMValueRef sample_index4 =
3652 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3653 LLVMValueRef shifted_fmask =
3654 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3655 LLVMValueRef final_sample =
3656 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3657
3658 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3659 * resource descriptor is 0 (invalid),
3660 */
3661 LLVMValueRef fmask_desc =
3662 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3663 ctx->v8i32, "");
3664
3665 LLVMValueRef fmask_word1 =
3666 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3667 ctx->i32one, "");
3668
3669 LLVMValueRef word1_is_nonzero =
3670 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3671 fmask_word1, ctx->i32zero, "");
3672
3673 /* Replace the MSAA sample index. */
3674 address[sample_chan] =
3675 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3676 final_sample, address[sample_chan], "");
3677 }
3678
3679 if (offsets && instr->op == nir_texop_txf) {
3680 nir_const_value *const_offset =
3681 nir_src_as_const_value(instr->src[const_src].src);
3682 int num_offsets = instr->src[const_src].src.ssa->num_components;
3683 assert(const_offset);
3684 num_offsets = MIN2(num_offsets, instr->coord_components);
3685 if (num_offsets > 2)
3686 address[2] = LLVMBuildAdd(ctx->builder,
3687 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3688 if (num_offsets > 1)
3689 address[1] = LLVMBuildAdd(ctx->builder,
3690 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3691 address[0] = LLVMBuildAdd(ctx->builder,
3692 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3693
3694 }
3695
3696 /* TODO TG4 support */
3697 if (instr->op == nir_texop_tg4) {
3698 if (instr->is_shadow)
3699 dmask = 1;
3700 else
3701 dmask = 1 << instr->component;
3702 }
3703 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3704 res_ptr, samp_ptr, address, count, dmask);
3705
3706 result = build_tex_intrinsic(ctx, instr, &tinfo);
3707
3708 if (instr->op == nir_texop_query_levels)
3709 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3710 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3711 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3712 else if (instr->op == nir_texop_txs &&
3713 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3714 instr->is_array) {
3715 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3716 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3717 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3718 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3719 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3720 } else if (instr->dest.ssa.num_components != 4)
3721 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3722
3723 write_result:
3724 if (result) {
3725 assert(instr->dest.is_ssa);
3726 result = to_integer(ctx, result);
3727 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3728 }
3729 }
3730
3731
3732 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3733 {
3734 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3735 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3736
3737 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3738 _mesa_hash_table_insert(ctx->phis, instr, result);
3739 }
3740
3741 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3742 nir_phi_instr *instr,
3743 LLVMValueRef llvm_phi)
3744 {
3745 nir_foreach_phi_src(src, instr) {
3746 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3747 LLVMValueRef llvm_src = get_src(ctx, src->src);
3748
3749 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3750 }
3751 }
3752
3753 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3754 {
3755 struct hash_entry *entry;
3756 hash_table_foreach(ctx->phis, entry) {
3757 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3758 (LLVMValueRef)entry->data);
3759 }
3760 }
3761
3762
3763 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3764 nir_ssa_undef_instr *instr)
3765 {
3766 unsigned num_components = instr->def.num_components;
3767 LLVMValueRef undef;
3768
3769 if (num_components == 1)
3770 undef = LLVMGetUndef(ctx->i32);
3771 else {
3772 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3773 }
3774 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3775 }
3776
3777 static void visit_jump(struct nir_to_llvm_context *ctx,
3778 nir_jump_instr *instr)
3779 {
3780 switch (instr->type) {
3781 case nir_jump_break:
3782 LLVMBuildBr(ctx->builder, ctx->break_block);
3783 LLVMClearInsertionPosition(ctx->builder);
3784 break;
3785 case nir_jump_continue:
3786 LLVMBuildBr(ctx->builder, ctx->continue_block);
3787 LLVMClearInsertionPosition(ctx->builder);
3788 break;
3789 default:
3790 fprintf(stderr, "Unknown NIR jump instr: ");
3791 nir_print_instr(&instr->instr, stderr);
3792 fprintf(stderr, "\n");
3793 abort();
3794 }
3795 }
3796
3797 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3798 struct exec_list *list);
3799
3800 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3801 {
3802 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3803 nir_foreach_instr(instr, block)
3804 {
3805 switch (instr->type) {
3806 case nir_instr_type_alu:
3807 visit_alu(ctx, nir_instr_as_alu(instr));
3808 break;
3809 case nir_instr_type_load_const:
3810 visit_load_const(ctx, nir_instr_as_load_const(instr));
3811 break;
3812 case nir_instr_type_intrinsic:
3813 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3814 break;
3815 case nir_instr_type_tex:
3816 visit_tex(ctx, nir_instr_as_tex(instr));
3817 break;
3818 case nir_instr_type_phi:
3819 visit_phi(ctx, nir_instr_as_phi(instr));
3820 break;
3821 case nir_instr_type_ssa_undef:
3822 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3823 break;
3824 case nir_instr_type_jump:
3825 visit_jump(ctx, nir_instr_as_jump(instr));
3826 break;
3827 default:
3828 fprintf(stderr, "Unknown NIR instr type: ");
3829 nir_print_instr(instr, stderr);
3830 fprintf(stderr, "\n");
3831 abort();
3832 }
3833 }
3834
3835 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3836 }
3837
3838 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3839 {
3840 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3841
3842 LLVMBasicBlockRef merge_block =
3843 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3844 LLVMBasicBlockRef if_block =
3845 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3846 LLVMBasicBlockRef else_block = merge_block;
3847 if (!exec_list_is_empty(&if_stmt->else_list))
3848 else_block = LLVMAppendBasicBlockInContext(
3849 ctx->context, ctx->main_function, "");
3850
3851 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3852 LLVMConstInt(ctx->i32, 0, false), "");
3853 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3854
3855 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3856 visit_cf_list(ctx, &if_stmt->then_list);
3857 if (LLVMGetInsertBlock(ctx->builder))
3858 LLVMBuildBr(ctx->builder, merge_block);
3859
3860 if (!exec_list_is_empty(&if_stmt->else_list)) {
3861 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3862 visit_cf_list(ctx, &if_stmt->else_list);
3863 if (LLVMGetInsertBlock(ctx->builder))
3864 LLVMBuildBr(ctx->builder, merge_block);
3865 }
3866
3867 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3868 }
3869
3870 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3871 {
3872 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3873 LLVMBasicBlockRef break_parent = ctx->break_block;
3874
3875 ctx->continue_block =
3876 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3877 ctx->break_block =
3878 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3879
3880 LLVMBuildBr(ctx->builder, ctx->continue_block);
3881 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3882 visit_cf_list(ctx, &loop->body);
3883
3884 if (LLVMGetInsertBlock(ctx->builder))
3885 LLVMBuildBr(ctx->builder, ctx->continue_block);
3886 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3887
3888 ctx->continue_block = continue_parent;
3889 ctx->break_block = break_parent;
3890 }
3891
3892 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3893 struct exec_list *list)
3894 {
3895 foreach_list_typed(nir_cf_node, node, node, list)
3896 {
3897 switch (node->type) {
3898 case nir_cf_node_block:
3899 visit_block(ctx, nir_cf_node_as_block(node));
3900 break;
3901
3902 case nir_cf_node_if:
3903 visit_if(ctx, nir_cf_node_as_if(node));
3904 break;
3905
3906 case nir_cf_node_loop:
3907 visit_loop(ctx, nir_cf_node_as_loop(node));
3908 break;
3909
3910 default:
3911 assert(0);
3912 }
3913 }
3914 }
3915
3916 static void
3917 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3918 struct nir_variable *variable)
3919 {
3920 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3921 LLVMValueRef t_offset;
3922 LLVMValueRef t_list;
3923 LLVMValueRef args[3];
3924 LLVMValueRef input;
3925 LLVMValueRef buffer_index;
3926 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3927 int idx = variable->data.location;
3928 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3929
3930 variable->data.driver_location = idx * 4;
3931
3932 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3933 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3934 ctx->start_instance, "");
3935 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3936 ctx->shader_info->vs.vgpr_comp_cnt);
3937 } else
3938 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3939 ctx->base_vertex, "");
3940
3941 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3942 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3943
3944 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
3945 args[0] = t_list;
3946 args[1] = LLVMConstInt(ctx->i32, 0, false);
3947 args[2] = buffer_index;
3948 input = ac_emit_llvm_intrinsic(&ctx->ac,
3949 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3950 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3951
3952 for (unsigned chan = 0; chan < 4; chan++) {
3953 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3954 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3955 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3956 input, llvm_chan, ""));
3957 }
3958 }
3959 }
3960
3961
3962 static void interp_fs_input(struct nir_to_llvm_context *ctx,
3963 unsigned attr,
3964 LLVMValueRef interp_param,
3965 LLVMValueRef prim_mask,
3966 LLVMValueRef result[4])
3967 {
3968 LLVMValueRef attr_number;
3969 unsigned chan;
3970 LLVMValueRef i, j;
3971 bool interp = interp_param != NULL;
3972
3973 attr_number = LLVMConstInt(ctx->i32, attr, false);
3974
3975 /* fs.constant returns the param from the middle vertex, so it's not
3976 * really useful for flat shading. It's meant to be used for custom
3977 * interpolation (but the intrinsic can't fetch from the other two
3978 * vertices).
3979 *
3980 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
3981 * to do the right thing. The only reason we use fs.constant is that
3982 * fs.interp cannot be used on integers, because they can be equal
3983 * to NaN.
3984 */
3985 if (interp) {
3986 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
3987 LLVMVectorType(ctx->f32, 2), "");
3988
3989 i = LLVMBuildExtractElement(ctx->builder, interp_param,
3990 ctx->i32zero, "");
3991 j = LLVMBuildExtractElement(ctx->builder, interp_param,
3992 ctx->i32one, "");
3993 }
3994
3995 for (chan = 0; chan < 4; chan++) {
3996 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3997
3998 if (interp) {
3999 result[chan] = ac_build_fs_interp(&ctx->ac,
4000 llvm_chan,
4001 attr_number,
4002 prim_mask, i, j);
4003 } else {
4004 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4005 LLVMConstInt(ctx->i32, 2, false),
4006 llvm_chan,
4007 attr_number,
4008 prim_mask);
4009 }
4010 }
4011 }
4012
4013 static void
4014 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4015 struct nir_variable *variable)
4016 {
4017 int idx = variable->data.location;
4018 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4019 LLVMValueRef interp;
4020
4021 variable->data.driver_location = idx * 4;
4022 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4023
4024 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4025 unsigned interp_type;
4026 if (variable->data.sample) {
4027 interp_type = INTERP_SAMPLE;
4028 ctx->shader_info->fs.force_persample = true;
4029 } else if (variable->data.centroid)
4030 interp_type = INTERP_CENTROID;
4031 else
4032 interp_type = INTERP_CENTER;
4033
4034 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4035 } else
4036 interp = NULL;
4037
4038 for (unsigned i = 0; i < attrib_count; ++i)
4039 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4040
4041 }
4042
4043 static void
4044 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4045 struct nir_variable *variable)
4046 {
4047 switch (ctx->stage) {
4048 case MESA_SHADER_VERTEX:
4049 handle_vs_input_decl(ctx, variable);
4050 break;
4051 case MESA_SHADER_FRAGMENT:
4052 handle_fs_input_decl(ctx, variable);
4053 break;
4054 default:
4055 break;
4056 }
4057
4058 }
4059
4060 static void
4061 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4062 struct nir_shader *nir)
4063 {
4064 unsigned index = 0;
4065 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4066 LLVMValueRef interp_param;
4067 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4068
4069 if (!(ctx->input_mask & (1ull << i)))
4070 continue;
4071
4072 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4073 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4074 interp_param = *inputs;
4075 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4076 inputs);
4077
4078 if (!interp_param)
4079 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4080 ++index;
4081 } else if (i == VARYING_SLOT_POS) {
4082 for(int i = 0; i < 3; ++i)
4083 inputs[i] = ctx->frag_pos[i];
4084
4085 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4086 }
4087 }
4088 ctx->shader_info->fs.num_interp = index;
4089 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4090 ctx->shader_info->fs.has_pcoord = true;
4091 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4092 ctx->shader_info->fs.prim_id_input = true;
4093 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4094 ctx->shader_info->fs.layer_input = true;
4095 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4096 }
4097
4098 static LLVMValueRef
4099 ac_build_alloca(struct nir_to_llvm_context *ctx,
4100 LLVMTypeRef type,
4101 const char *name)
4102 {
4103 LLVMBuilderRef builder = ctx->builder;
4104 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4105 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4106 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4107 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4108 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4109 LLVMValueRef res;
4110
4111 if (first_instr) {
4112 LLVMPositionBuilderBefore(first_builder, first_instr);
4113 } else {
4114 LLVMPositionBuilderAtEnd(first_builder, first_block);
4115 }
4116
4117 res = LLVMBuildAlloca(first_builder, type, name);
4118 LLVMBuildStore(builder, LLVMConstNull(type), res);
4119
4120 LLVMDisposeBuilder(first_builder);
4121
4122 return res;
4123 }
4124
4125 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4126 LLVMTypeRef type,
4127 const char *name)
4128 {
4129 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4130 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4131 return ptr;
4132 }
4133
4134 static void
4135 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4136 struct nir_variable *variable)
4137 {
4138 int idx = variable->data.location + variable->data.index;
4139 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4140
4141 variable->data.driver_location = idx * 4;
4142
4143 if (ctx->stage == MESA_SHADER_VERTEX ||
4144 ctx->stage == MESA_SHADER_GEOMETRY) {
4145 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4146 idx == VARYING_SLOT_CULL_DIST0) {
4147 int length = glsl_get_length(variable->type);
4148 if (ctx->stage == MESA_SHADER_VERTEX) {
4149 if (idx == VARYING_SLOT_CLIP_DIST0) {
4150 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4151 ctx->num_clips = length;
4152 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4153 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4154 ctx->num_culls = length;
4155 }
4156 }
4157 if (length > 4)
4158 attrib_count = 2;
4159 else
4160 attrib_count = 1;
4161 }
4162 }
4163
4164 for (unsigned i = 0; i < attrib_count; ++i) {
4165 for (unsigned chan = 0; chan < 4; chan++) {
4166 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4167 si_build_alloca_undef(ctx, ctx->f32, "");
4168 }
4169 }
4170 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4171 }
4172
4173 static void
4174 setup_locals(struct nir_to_llvm_context *ctx,
4175 struct nir_function *func)
4176 {
4177 int i, j;
4178 ctx->num_locals = 0;
4179 nir_foreach_variable(variable, &func->impl->locals) {
4180 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4181 variable->data.driver_location = ctx->num_locals * 4;
4182 ctx->num_locals += attrib_count;
4183 }
4184 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4185 if (!ctx->locals)
4186 return;
4187
4188 for (i = 0; i < ctx->num_locals; i++) {
4189 for (j = 0; j < 4; j++) {
4190 ctx->locals[i * 4 + j] =
4191 si_build_alloca_undef(ctx, ctx->f32, "temp");
4192 }
4193 }
4194 }
4195
4196 static LLVMValueRef
4197 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4198 {
4199 v = to_float(ctx, v);
4200 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4201 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4202 }
4203
4204
4205 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4206 LLVMValueRef src0, LLVMValueRef src1)
4207 {
4208 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4209 LLVMValueRef comp[2];
4210
4211 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4212 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4213 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4214 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4215 }
4216
4217 /* Initialize arguments for the shader export intrinsic */
4218 static void
4219 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4220 LLVMValueRef *values,
4221 unsigned target,
4222 LLVMValueRef *args)
4223 {
4224 /* Default is 0xf. Adjusted below depending on the format. */
4225 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4226 /* Specify whether the EXEC mask represents the valid mask */
4227 args[1] = LLVMConstInt(ctx->i32, 0, false);
4228
4229 /* Specify whether this is the last export */
4230 args[2] = LLVMConstInt(ctx->i32, 0, false);
4231 /* Specify the target we are exporting */
4232 args[3] = LLVMConstInt(ctx->i32, target, false);
4233
4234 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4235 args[5] = LLVMGetUndef(ctx->f32);
4236 args[6] = LLVMGetUndef(ctx->f32);
4237 args[7] = LLVMGetUndef(ctx->f32);
4238 args[8] = LLVMGetUndef(ctx->f32);
4239
4240 if (!values)
4241 return;
4242
4243 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4244 LLVMValueRef val[4];
4245 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4246 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4247 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4248
4249 switch(col_format) {
4250 case V_028714_SPI_SHADER_ZERO:
4251 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4252 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4253 break;
4254
4255 case V_028714_SPI_SHADER_32_R:
4256 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4257 args[5] = values[0];
4258 break;
4259
4260 case V_028714_SPI_SHADER_32_GR:
4261 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4262 args[5] = values[0];
4263 args[6] = values[1];
4264 break;
4265
4266 case V_028714_SPI_SHADER_32_AR:
4267 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4268 args[5] = values[0];
4269 args[8] = values[3];
4270 break;
4271
4272 case V_028714_SPI_SHADER_FP16_ABGR:
4273 args[4] = ctx->i32one;
4274
4275 for (unsigned chan = 0; chan < 2; chan++) {
4276 LLVMValueRef pack_args[2] = {
4277 values[2 * chan],
4278 values[2 * chan + 1]
4279 };
4280 LLVMValueRef packed;
4281
4282 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4283 ctx->i32, pack_args, 2,
4284 AC_FUNC_ATTR_READNONE);
4285 args[chan + 5] = packed;
4286 }
4287 break;
4288
4289 case V_028714_SPI_SHADER_UNORM16_ABGR:
4290 for (unsigned chan = 0; chan < 4; chan++) {
4291 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4292 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4293 LLVMConstReal(ctx->f32, 65535), "");
4294 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4295 LLVMConstReal(ctx->f32, 0.5), "");
4296 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4297 ctx->i32, "");
4298 }
4299
4300 args[4] = ctx->i32one;
4301 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4302 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4303 break;
4304
4305 case V_028714_SPI_SHADER_SNORM16_ABGR:
4306 for (unsigned chan = 0; chan < 4; chan++) {
4307 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4308 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4309 LLVMConstReal(ctx->f32, 32767), "");
4310
4311 /* If positive, add 0.5, else add -0.5. */
4312 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4313 LLVMBuildSelect(ctx->builder,
4314 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4315 val[chan], ctx->f32zero, ""),
4316 LLVMConstReal(ctx->f32, 0.5),
4317 LLVMConstReal(ctx->f32, -0.5), ""), "");
4318 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4319 }
4320
4321 args[4] = ctx->i32one;
4322 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4323 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4324 break;
4325
4326 case V_028714_SPI_SHADER_UINT16_ABGR: {
4327 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4328
4329 for (unsigned chan = 0; chan < 4; chan++) {
4330 val[chan] = to_integer(ctx, values[chan]);
4331 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4332 }
4333
4334 args[4] = ctx->i32one;
4335 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4336 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4337 break;
4338 }
4339
4340 case V_028714_SPI_SHADER_SINT16_ABGR: {
4341 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4342 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4343
4344 /* Clamp. */
4345 for (unsigned chan = 0; chan < 4; chan++) {
4346 val[chan] = to_integer(ctx, values[chan]);
4347 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4348 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4349 }
4350
4351 args[4] = ctx->i32one;
4352 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4353 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4354 break;
4355 }
4356
4357 default:
4358 case V_028714_SPI_SHADER_32_ABGR:
4359 memcpy(&args[5], values, sizeof(values[0]) * 4);
4360 break;
4361 }
4362 } else
4363 memcpy(&args[5], values, sizeof(values[0]) * 4);
4364
4365 for (unsigned i = 5; i < 9; ++i)
4366 args[i] = to_float(ctx, args[i]);
4367 }
4368
4369 static void
4370 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4371 {
4372 uint32_t param_count = 0;
4373 unsigned target;
4374 unsigned pos_idx, num_pos_exports = 0;
4375 LLVMValueRef args[9];
4376 LLVMValueRef pos_args[4][9] = { { 0 } };
4377 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4378 int i;
4379 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4380 (1ull << VARYING_SLOT_CLIP_DIST1) |
4381 (1ull << VARYING_SLOT_CULL_DIST0) |
4382 (1ull << VARYING_SLOT_CULL_DIST1));
4383
4384 ctx->shader_info->vs.prim_id_output = 0xffffffff;
4385 ctx->shader_info->vs.layer_output = 0xffffffff;
4386 if (clip_mask) {
4387 LLVMValueRef slots[8];
4388 unsigned j;
4389
4390 if (ctx->shader_info->vs.cull_dist_mask)
4391 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
4392
4393 i = VARYING_SLOT_CLIP_DIST0;
4394 for (j = 0; j < ctx->num_clips; j++)
4395 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4396 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4397 i = VARYING_SLOT_CULL_DIST0;
4398 for (j = 0; j < ctx->num_culls; j++)
4399 slots[ctx->num_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4400 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4401
4402 for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
4403 slots[i] = LLVMGetUndef(ctx->f32);
4404
4405 if (ctx->num_clips + ctx->num_culls > 4) {
4406 target = V_008DFC_SQ_EXP_POS + 3;
4407 si_llvm_init_export_args(ctx, &slots[4], target, args);
4408 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4409 args, sizeof(args));
4410 }
4411
4412 target = V_008DFC_SQ_EXP_POS + 2;
4413 si_llvm_init_export_args(ctx, &slots[0], target, args);
4414 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4415 args, sizeof(args));
4416
4417 }
4418
4419 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4420 LLVMValueRef values[4];
4421 if (!(ctx->output_mask & (1ull << i)))
4422 continue;
4423
4424 for (unsigned j = 0; j < 4; j++)
4425 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4426 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4427
4428 if (i == VARYING_SLOT_POS) {
4429 target = V_008DFC_SQ_EXP_POS;
4430 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4431 i == VARYING_SLOT_CLIP_DIST1 ||
4432 i == VARYING_SLOT_CULL_DIST0 ||
4433 i == VARYING_SLOT_CULL_DIST1) {
4434 continue;
4435 } else if (i == VARYING_SLOT_PSIZ) {
4436 ctx->shader_info->vs.writes_pointsize = true;
4437 psize_value = values[0];
4438 continue;
4439 } else if (i == VARYING_SLOT_LAYER) {
4440 ctx->shader_info->vs.writes_layer = true;
4441 layer_value = values[0];
4442 ctx->shader_info->vs.layer_output = param_count;
4443 target = V_008DFC_SQ_EXP_PARAM + param_count;
4444 param_count++;
4445 } else if (i == VARYING_SLOT_VIEWPORT) {
4446 ctx->shader_info->vs.writes_viewport_index = true;
4447 viewport_index_value = values[0];
4448 continue;
4449 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
4450 ctx->shader_info->vs.prim_id_output = param_count;
4451 target = V_008DFC_SQ_EXP_PARAM + param_count;
4452 param_count++;
4453 } else if (i >= VARYING_SLOT_VAR0) {
4454 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4455 target = V_008DFC_SQ_EXP_PARAM + param_count;
4456 param_count++;
4457 }
4458
4459 si_llvm_init_export_args(ctx, values, target, args);
4460
4461 if (target >= V_008DFC_SQ_EXP_POS &&
4462 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4463 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4464 args, sizeof(args));
4465 } else {
4466 ac_emit_llvm_intrinsic(&ctx->ac,
4467 "llvm.SI.export",
4468 ctx->voidt,
4469 args, 9, 0);
4470 }
4471 }
4472
4473 /* We need to add the position output manually if it's missing. */
4474 if (!pos_args[0][0]) {
4475 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4476 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4477 pos_args[0][2] = ctx->i32zero; /* last export? */
4478 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4479 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4480 pos_args[0][5] = ctx->f32zero; /* X */
4481 pos_args[0][6] = ctx->f32zero; /* Y */
4482 pos_args[0][7] = ctx->f32zero; /* Z */
4483 pos_args[0][8] = ctx->f32one; /* W */
4484 }
4485
4486 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4487 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4488 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4489 if (mask) {
4490 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4491 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4492 pos_args[1][2] = ctx->i32zero; /* last export? */
4493 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4494 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4495 pos_args[1][5] = ctx->f32zero; /* X */
4496 pos_args[1][6] = ctx->f32zero; /* Y */
4497 pos_args[1][7] = ctx->f32zero; /* Z */
4498 pos_args[1][8] = ctx->f32zero; /* W */
4499
4500 if (ctx->shader_info->vs.writes_pointsize == true)
4501 pos_args[1][5] = psize_value;
4502 if (ctx->shader_info->vs.writes_layer == true)
4503 pos_args[1][7] = layer_value;
4504 if (ctx->shader_info->vs.writes_viewport_index == true)
4505 pos_args[1][8] = viewport_index_value;
4506 }
4507 for (i = 0; i < 4; i++) {
4508 if (pos_args[i][0])
4509 num_pos_exports++;
4510 }
4511
4512 pos_idx = 0;
4513 for (i = 0; i < 4; i++) {
4514 if (!pos_args[i][0])
4515 continue;
4516
4517 /* Specify the target we are exporting */
4518 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4519 if (pos_idx == num_pos_exports)
4520 pos_args[i][2] = ctx->i32one;
4521 ac_emit_llvm_intrinsic(&ctx->ac,
4522 "llvm.SI.export",
4523 ctx->voidt,
4524 pos_args[i], 9, 0);
4525 }
4526
4527 ctx->shader_info->vs.pos_exports = num_pos_exports;
4528 ctx->shader_info->vs.param_exports = param_count;
4529 }
4530
4531 static void
4532 handle_es_outputs_post(struct nir_to_llvm_context *ctx)
4533 {
4534 int j;
4535 uint64_t max_output_written = 0;
4536 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4537 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
4538 int param_index;
4539 if (!(ctx->output_mask & (1ull << i)))
4540 continue;
4541
4542 param_index = shader_io_get_unique_index(i);
4543
4544 if (param_index > max_output_written)
4545 max_output_written = param_index;
4546
4547 for (j = 0; j < 4; j++) {
4548 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
4549 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
4550
4551 ac_build_tbuffer_store(&ctx->ac,
4552 ctx->esgs_ring,
4553 out_val, 1,
4554 LLVMGetUndef(ctx->i32), ctx->es2gs_offset,
4555 (4 * param_index + j) * 4,
4556 V_008F0C_BUF_DATA_FORMAT_32,
4557 V_008F0C_BUF_NUM_FORMAT_UINT,
4558 0, 0, 1, 1, 0);
4559 }
4560 }
4561 ctx->shader_info->vs.esgs_itemsize = (max_output_written + 1) * 16;
4562 }
4563
4564 static void
4565 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4566 LLVMValueRef *color, unsigned param, bool is_last)
4567 {
4568 LLVMValueRef args[9];
4569 /* Export */
4570 si_llvm_init_export_args(ctx, color, param,
4571 args);
4572
4573 if (is_last) {
4574 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4575 args[2] = ctx->i32one; /* DONE bit */
4576 } else if (args[0] == ctx->i32zero)
4577 return; /* unnecessary NULL export */
4578
4579 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4580 ctx->voidt, args, 9, 0);
4581 }
4582
4583 static void
4584 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4585 LLVMValueRef depth, LLVMValueRef stencil,
4586 LLVMValueRef samplemask)
4587 {
4588 LLVMValueRef args[9];
4589 unsigned mask = 0;
4590 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4591 args[2] = ctx->i32one; /* DONE bit */
4592 /* Specify the target we are exporting */
4593 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4594
4595 args[4] = ctx->i32zero; /* COMP flag */
4596 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4597 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4598 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4599 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4600
4601 if (depth) {
4602 args[5] = depth;
4603 mask |= 0x1;
4604 }
4605
4606 if (stencil) {
4607 args[6] = stencil;
4608 mask |= 0x2;
4609 }
4610
4611 if (samplemask) {
4612 args[7] = samplemask;
4613 mask |= 0x04;
4614 }
4615
4616 /* SI (except OLAND) has a bug that it only looks
4617 * at the X writemask component. */
4618 if (ctx->options->chip_class == SI &&
4619 ctx->options->family != CHIP_OLAND)
4620 mask |= 0x01;
4621
4622 args[0] = LLVMConstInt(ctx->i32, mask, false);
4623 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4624 ctx->voidt, args, 9, 0);
4625 }
4626
4627 static void
4628 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4629 {
4630 unsigned index = 0;
4631 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4632
4633 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4634 LLVMValueRef values[4];
4635
4636 if (!(ctx->output_mask & (1ull << i)))
4637 continue;
4638
4639 if (i == FRAG_RESULT_DEPTH) {
4640 ctx->shader_info->fs.writes_z = true;
4641 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4642 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4643 } else if (i == FRAG_RESULT_STENCIL) {
4644 ctx->shader_info->fs.writes_stencil = true;
4645 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4646 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4647 } else {
4648 bool last = false;
4649 for (unsigned j = 0; j < 4; j++)
4650 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4651 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4652
4653 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4654 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4655
4656 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4657 index++;
4658 }
4659 }
4660
4661 if (depth || stencil)
4662 si_export_mrt_z(ctx, depth, stencil, samplemask);
4663 else if (!index)
4664 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4665
4666 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4667 }
4668
4669 static void
4670 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4671 {
4672 ac_emit_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4673 }
4674
4675 static void
4676 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4677 {
4678 switch (ctx->stage) {
4679 case MESA_SHADER_VERTEX:
4680 if (ctx->options->key.vs.as_es)
4681 handle_es_outputs_post(ctx);
4682 else
4683 handle_vs_outputs_post(ctx);
4684 break;
4685 case MESA_SHADER_FRAGMENT:
4686 handle_fs_outputs_post(ctx);
4687 break;
4688 case MESA_SHADER_GEOMETRY:
4689 emit_gs_epilogue(ctx);
4690 break;
4691 default:
4692 break;
4693 }
4694 }
4695
4696 static void
4697 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4698 struct nir_variable *variable, uint32_t *offset, int idx)
4699 {
4700 unsigned size = glsl_count_attribute_slots(variable->type, false);
4701 variable->data.driver_location = *offset;
4702 *offset += size;
4703 }
4704
4705 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4706 {
4707 LLVMPassManagerRef passmgr;
4708 /* Create the pass manager */
4709 passmgr = LLVMCreateFunctionPassManagerForModule(
4710 ctx->module);
4711
4712 /* This pass should eliminate all the load and store instructions */
4713 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4714
4715 /* Add some optimization passes */
4716 LLVMAddScalarReplAggregatesPass(passmgr);
4717 LLVMAddLICMPass(passmgr);
4718 LLVMAddAggressiveDCEPass(passmgr);
4719 LLVMAddCFGSimplificationPass(passmgr);
4720 LLVMAddInstructionCombiningPass(passmgr);
4721
4722 /* Run the pass */
4723 LLVMInitializeFunctionPassManager(passmgr);
4724 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4725 LLVMFinalizeFunctionPassManager(passmgr);
4726
4727 LLVMDisposeBuilder(ctx->builder);
4728 LLVMDisposePassManager(passmgr);
4729 }
4730
4731 static void
4732 ac_setup_rings(struct nir_to_llvm_context *ctx)
4733 {
4734 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4735 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, ctx->i32one);
4736 }
4737
4738 if (ctx->is_gs_copy_shader) {
4739 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4740 }
4741 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4742 LLVMValueRef tmp;
4743 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4744 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4745
4746 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4747
4748 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4749 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4750 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4751 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4752
4753 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4754 }
4755 }
4756
4757 static
4758 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4759 struct nir_shader *nir,
4760 struct ac_shader_variant_info *shader_info,
4761 const struct ac_nir_compiler_options *options)
4762 {
4763 struct nir_to_llvm_context ctx = {0};
4764 struct nir_function *func;
4765 unsigned i;
4766 ctx.options = options;
4767 ctx.shader_info = shader_info;
4768 ctx.context = LLVMContextCreate();
4769 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4770
4771 ac_llvm_context_init(&ctx.ac, ctx.context);
4772 ctx.ac.module = ctx.module;
4773
4774 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4775
4776 memset(shader_info, 0, sizeof(*shader_info));
4777
4778 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4779 setup_types(&ctx);
4780
4781 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4782 ctx.ac.builder = ctx.builder;
4783 ctx.stage = nir->stage;
4784
4785 for (i = 0; i < AC_UD_MAX_SETS; i++)
4786 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4787 for (i = 0; i < AC_UD_MAX_UD; i++)
4788 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4789
4790 create_function(&ctx);
4791
4792 if (nir->stage == MESA_SHADER_COMPUTE) {
4793 int num_shared = 0;
4794 nir_foreach_variable(variable, &nir->shared)
4795 num_shared++;
4796 if (num_shared) {
4797 int idx = 0;
4798 uint32_t shared_size = 0;
4799 LLVMValueRef var;
4800 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4801 nir_foreach_variable(variable, &nir->shared) {
4802 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4803 idx++;
4804 }
4805
4806 shared_size *= 16;
4807 var = LLVMAddGlobalInAddressSpace(ctx.module,
4808 LLVMArrayType(ctx.i8, shared_size),
4809 "compute_lds",
4810 LOCAL_ADDR_SPACE);
4811 LLVMSetAlignment(var, 4);
4812 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4813 }
4814 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4815 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4816
4817 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4818 }
4819
4820 ac_setup_rings(&ctx);
4821
4822 nir_foreach_variable(variable, &nir->inputs)
4823 handle_shader_input_decl(&ctx, variable);
4824
4825 if (nir->stage == MESA_SHADER_FRAGMENT)
4826 handle_fs_inputs_pre(&ctx, nir);
4827
4828 nir_foreach_variable(variable, &nir->outputs)
4829 handle_shader_output_decl(&ctx, variable);
4830
4831 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4832 _mesa_key_pointer_equal);
4833 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4834 _mesa_key_pointer_equal);
4835
4836 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4837
4838 setup_locals(&ctx, func);
4839
4840 visit_cf_list(&ctx, &func->impl->body);
4841 phi_post_pass(&ctx);
4842
4843 handle_shader_outputs_post(&ctx);
4844 LLVMBuildRetVoid(ctx.builder);
4845
4846 ac_llvm_finalize_module(&ctx);
4847 free(ctx.locals);
4848 ralloc_free(ctx.defs);
4849 ralloc_free(ctx.phis);
4850
4851 if (nir->stage == MESA_SHADER_GEOMETRY) {
4852 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4853 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4854 nir->info->gs.vertices_out;
4855 }
4856 return ctx.module;
4857 }
4858
4859 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4860 {
4861 unsigned *retval = (unsigned *)context;
4862 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4863 char *description = LLVMGetDiagInfoDescription(di);
4864
4865 if (severity == LLVMDSError) {
4866 *retval = 1;
4867 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4868 description);
4869 }
4870
4871 LLVMDisposeMessage(description);
4872 }
4873
4874 static unsigned ac_llvm_compile(LLVMModuleRef M,
4875 struct ac_shader_binary *binary,
4876 LLVMTargetMachineRef tm)
4877 {
4878 unsigned retval = 0;
4879 char *err;
4880 LLVMContextRef llvm_ctx;
4881 LLVMMemoryBufferRef out_buffer;
4882 unsigned buffer_size;
4883 const char *buffer_data;
4884 LLVMBool mem_err;
4885
4886 /* Setup Diagnostic Handler*/
4887 llvm_ctx = LLVMGetModuleContext(M);
4888
4889 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4890 &retval);
4891
4892 /* Compile IR*/
4893 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4894 &err, &out_buffer);
4895
4896 /* Process Errors/Warnings */
4897 if (mem_err) {
4898 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4899 free(err);
4900 retval = 1;
4901 goto out;
4902 }
4903
4904 /* Extract Shader Code*/
4905 buffer_size = LLVMGetBufferSize(out_buffer);
4906 buffer_data = LLVMGetBufferStart(out_buffer);
4907
4908 ac_elf_read(buffer_data, buffer_size, binary);
4909
4910 /* Clean up */
4911 LLVMDisposeMemoryBuffer(out_buffer);
4912
4913 out:
4914 return retval;
4915 }
4916
4917 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4918 LLVMModuleRef llvm_module,
4919 struct ac_shader_binary *binary,
4920 struct ac_shader_config *config,
4921 struct ac_shader_variant_info *shader_info,
4922 gl_shader_stage stage,
4923 bool dump_shader, bool supports_spill)
4924 {
4925 if (dump_shader)
4926 ac_dump_module(llvm_module);
4927
4928 memset(binary, 0, sizeof(*binary));
4929 int v = ac_llvm_compile(llvm_module, binary, tm);
4930 if (v) {
4931 fprintf(stderr, "compile failed\n");
4932 }
4933
4934 if (dump_shader)
4935 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4936
4937 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4938
4939 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4940 LLVMDisposeModule(llvm_module);
4941 LLVMContextDispose(ctx);
4942
4943 if (stage == MESA_SHADER_FRAGMENT) {
4944 shader_info->num_input_vgprs = 0;
4945 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4946 shader_info->num_input_vgprs += 2;
4947 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4948 shader_info->num_input_vgprs += 2;
4949 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4950 shader_info->num_input_vgprs += 2;
4951 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4952 shader_info->num_input_vgprs += 3;
4953 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4954 shader_info->num_input_vgprs += 2;
4955 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4956 shader_info->num_input_vgprs += 2;
4957 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4958 shader_info->num_input_vgprs += 2;
4959 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4960 shader_info->num_input_vgprs += 1;
4961 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
4962 shader_info->num_input_vgprs += 1;
4963 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
4964 shader_info->num_input_vgprs += 1;
4965 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
4966 shader_info->num_input_vgprs += 1;
4967 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
4968 shader_info->num_input_vgprs += 1;
4969 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
4970 shader_info->num_input_vgprs += 1;
4971 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
4972 shader_info->num_input_vgprs += 1;
4973 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
4974 shader_info->num_input_vgprs += 1;
4975 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
4976 shader_info->num_input_vgprs += 1;
4977 }
4978 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
4979
4980 /* +3 for scratch wave offset and VCC */
4981 config->num_sgprs = MAX2(config->num_sgprs,
4982 shader_info->num_input_sgprs + 3);
4983 }
4984
4985 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
4986 struct ac_shader_binary *binary,
4987 struct ac_shader_config *config,
4988 struct ac_shader_variant_info *shader_info,
4989 struct nir_shader *nir,
4990 const struct ac_nir_compiler_options *options,
4991 bool dump_shader)
4992 {
4993
4994 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
4995 options);
4996
4997 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
4998 switch (nir->stage) {
4999 case MESA_SHADER_COMPUTE:
5000 for (int i = 0; i < 3; ++i)
5001 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
5002 break;
5003 case MESA_SHADER_FRAGMENT:
5004 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
5005 break;
5006 case MESA_SHADER_GEOMETRY:
5007 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
5008 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
5009 shader_info->gs.output_prim = nir->info->gs.output_primitive;
5010 shader_info->gs.invocations = nir->info->gs.invocations;
5011 break;
5012 case MESA_SHADER_VERTEX:
5013 shader_info->vs.as_es = options->key.vs.as_es;
5014 break;
5015 default:
5016 break;
5017 }
5018 }
5019
5020 static void
5021 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
5022 {
5023 LLVMValueRef args[9];
5024 args[0] = ctx->gsvs_ring;
5025 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
5026 args[3] = ctx->i32zero;
5027 args[4] = ctx->i32one; /* OFFEN */
5028 args[5] = ctx->i32zero; /* IDXEN */
5029 args[6] = ctx->i32one; /* GLC */
5030 args[7] = ctx->i32one; /* SLC */
5031 args[8] = ctx->i32zero; /* TFE */
5032
5033 int idx = 0;
5034 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5035 if (!(ctx->output_mask & (1ull << i)))
5036 continue;
5037
5038 for (unsigned j = 0; j < 4; j++) {
5039 LLVMValueRef value;
5040 args[2] = LLVMConstInt(ctx->i32,
5041 (idx * 4 + j) *
5042 ctx->gs_max_out_vertices * 16 * 4, false);
5043
5044 value = ac_emit_llvm_intrinsic(&ctx->ac,
5045 "llvm.SI.buffer.load.dword.i32.i32",
5046 ctx->i32, args, 9,
5047 AC_FUNC_ATTR_READONLY);
5048
5049 LLVMBuildStore(ctx->builder,
5050 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
5051 }
5052 idx++;
5053 }
5054 handle_vs_outputs_post(ctx);
5055 }
5056
5057 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5058 struct nir_shader *geom_shader,
5059 struct ac_shader_binary *binary,
5060 struct ac_shader_config *config,
5061 struct ac_shader_variant_info *shader_info,
5062 const struct ac_nir_compiler_options *options,
5063 bool dump_shader)
5064 {
5065 struct nir_to_llvm_context ctx = {0};
5066 ctx.context = LLVMContextCreate();
5067 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5068 ctx.options = options;
5069 ctx.shader_info = shader_info;
5070
5071 ac_llvm_context_init(&ctx.ac, ctx.context);
5072 ctx.ac.module = ctx.module;
5073
5074 ctx.is_gs_copy_shader = true;
5075 LLVMSetTarget(ctx.module, "amdgcn--");
5076 setup_types(&ctx);
5077
5078 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5079 ctx.ac.builder = ctx.builder;
5080 ctx.stage = MESA_SHADER_VERTEX;
5081
5082 create_function(&ctx);
5083
5084 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5085 ac_setup_rings(&ctx);
5086
5087 nir_foreach_variable(variable, &geom_shader->outputs)
5088 handle_shader_output_decl(&ctx, variable);
5089
5090 ac_gs_copy_shader_emit(&ctx);
5091
5092 LLVMBuildRetVoid(ctx.builder);
5093
5094 ac_llvm_finalize_module(&ctx);
5095
5096 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5097 MESA_SHADER_VERTEX,
5098 dump_shader, options->supports_spill);
5099 }