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ac/nir: remove last remnants of v16i8
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_info.h"
34 #include "ac_exp_param.h"
35
36 enum radeon_llvm_calling_convention {
37 RADEON_LLVM_AMDGPU_VS = 87,
38 RADEON_LLVM_AMDGPU_GS = 88,
39 RADEON_LLVM_AMDGPU_PS = 89,
40 RADEON_LLVM_AMDGPU_CS = 90,
41 };
42
43 #define CONST_ADDR_SPACE 2
44 #define LOCAL_ADDR_SPACE 3
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
48
49 enum desc_type {
50 DESC_IMAGE,
51 DESC_FMASK,
52 DESC_SAMPLER,
53 DESC_BUFFER,
54 };
55
56 struct nir_to_llvm_context {
57 struct ac_llvm_context ac;
58 const struct ac_nir_compiler_options *options;
59 struct ac_shader_variant_info *shader_info;
60 unsigned max_workgroup_size;
61 LLVMContextRef context;
62 LLVMModuleRef module;
63 LLVMBuilderRef builder;
64 LLVMValueRef main_function;
65
66 struct hash_table *defs;
67 struct hash_table *phis;
68
69 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
70 LLVMValueRef ring_offsets;
71 LLVMValueRef push_constants;
72 LLVMValueRef num_work_groups;
73 LLVMValueRef workgroup_ids;
74 LLVMValueRef local_invocation_ids;
75 LLVMValueRef tg_size;
76
77 LLVMValueRef vertex_buffers;
78 LLVMValueRef base_vertex;
79 LLVMValueRef start_instance;
80 LLVMValueRef draw_index;
81 LLVMValueRef vertex_id;
82 LLVMValueRef rel_auto_id;
83 LLVMValueRef vs_prim_id;
84 LLVMValueRef instance_id;
85 LLVMValueRef ls_out_layout;
86 LLVMValueRef es2gs_offset;
87
88 LLVMValueRef tcs_offchip_layout;
89 LLVMValueRef tcs_out_offsets;
90 LLVMValueRef tcs_out_layout;
91 LLVMValueRef tcs_in_layout;
92 LLVMValueRef oc_lds;
93 LLVMValueRef tess_factor_offset;
94 LLVMValueRef tcs_patch_id;
95 LLVMValueRef tcs_rel_ids;
96 LLVMValueRef tes_rel_patch_id;
97 LLVMValueRef tes_patch_id;
98 LLVMValueRef tes_u;
99 LLVMValueRef tes_v;
100
101 LLVMValueRef gsvs_ring_stride;
102 LLVMValueRef gsvs_num_entries;
103 LLVMValueRef gs2vs_offset;
104 LLVMValueRef gs_wave_id;
105 LLVMValueRef gs_vtx_offset[6];
106 LLVMValueRef gs_prim_id, gs_invocation_id;
107
108 LLVMValueRef esgs_ring;
109 LLVMValueRef gsvs_ring;
110 LLVMValueRef hs_ring_tess_offchip;
111 LLVMValueRef hs_ring_tess_factor;
112
113 LLVMValueRef prim_mask;
114 LLVMValueRef sample_pos_offset;
115 LLVMValueRef persp_sample, persp_center, persp_centroid;
116 LLVMValueRef linear_sample, linear_center, linear_centroid;
117 LLVMValueRef front_face;
118 LLVMValueRef ancillary;
119 LLVMValueRef sample_coverage;
120 LLVMValueRef frag_pos[4];
121
122 LLVMBasicBlockRef continue_block;
123 LLVMBasicBlockRef break_block;
124
125 LLVMTypeRef i1;
126 LLVMTypeRef i8;
127 LLVMTypeRef i16;
128 LLVMTypeRef i32;
129 LLVMTypeRef i64;
130 LLVMTypeRef v2i32;
131 LLVMTypeRef v3i32;
132 LLVMTypeRef v4i32;
133 LLVMTypeRef v8i32;
134 LLVMTypeRef f64;
135 LLVMTypeRef f32;
136 LLVMTypeRef f16;
137 LLVMTypeRef v2f32;
138 LLVMTypeRef v4f32;
139 LLVMTypeRef voidt;
140
141 LLVMValueRef i1true;
142 LLVMValueRef i1false;
143 LLVMValueRef i32zero;
144 LLVMValueRef i32one;
145 LLVMValueRef f32zero;
146 LLVMValueRef f32one;
147 LLVMValueRef v4f32empty;
148
149 unsigned uniform_md_kind;
150 LLVMValueRef empty_md;
151 gl_shader_stage stage;
152
153 LLVMValueRef lds;
154 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
155 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
156
157 LLVMValueRef shared_memory;
158 uint64_t input_mask;
159 uint64_t output_mask;
160 int num_locals;
161 LLVMValueRef *locals;
162 uint8_t num_output_clips;
163 uint8_t num_output_culls;
164
165 bool has_ds_bpermute;
166
167 bool is_gs_copy_shader;
168 LLVMValueRef gs_next_vertex;
169 unsigned gs_max_out_vertices;
170
171 unsigned tes_primitive_mode;
172 uint64_t tess_outputs_written;
173 uint64_t tess_patch_outputs_written;
174 };
175
176 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
177 const nir_deref_var *deref,
178 enum desc_type desc_type);
179 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
180 {
181 return (index * 4) + chan;
182 }
183
184 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
185 {
186 /* handle patch indices separate */
187 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
188 return 0;
189 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
190 return 1;
191 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
192 return 2 + (slot - VARYING_SLOT_PATCH0);
193
194 if (slot == VARYING_SLOT_POS)
195 return 0;
196 if (slot == VARYING_SLOT_PSIZ)
197 return 1;
198 if (slot == VARYING_SLOT_CLIP_DIST0)
199 return 2;
200 /* 3 is reserved for clip dist as well */
201 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
202 return 4 + (slot - VARYING_SLOT_VAR0);
203 unreachable("illegal slot in get unique index\n");
204 }
205
206 static unsigned llvm_get_type_size(LLVMTypeRef type)
207 {
208 LLVMTypeKind kind = LLVMGetTypeKind(type);
209
210 switch (kind) {
211 case LLVMIntegerTypeKind:
212 return LLVMGetIntTypeWidth(type) / 8;
213 case LLVMFloatTypeKind:
214 return 4;
215 case LLVMPointerTypeKind:
216 return 8;
217 case LLVMVectorTypeKind:
218 return LLVMGetVectorSize(type) *
219 llvm_get_type_size(LLVMGetElementType(type));
220 default:
221 assert(0);
222 return 0;
223 }
224 }
225
226 static void set_llvm_calling_convention(LLVMValueRef func,
227 gl_shader_stage stage)
228 {
229 enum radeon_llvm_calling_convention calling_conv;
230
231 switch (stage) {
232 case MESA_SHADER_VERTEX:
233 case MESA_SHADER_TESS_CTRL:
234 case MESA_SHADER_TESS_EVAL:
235 calling_conv = RADEON_LLVM_AMDGPU_VS;
236 break;
237 case MESA_SHADER_GEOMETRY:
238 calling_conv = RADEON_LLVM_AMDGPU_GS;
239 break;
240 case MESA_SHADER_FRAGMENT:
241 calling_conv = RADEON_LLVM_AMDGPU_PS;
242 break;
243 case MESA_SHADER_COMPUTE:
244 calling_conv = RADEON_LLVM_AMDGPU_CS;
245 break;
246 default:
247 unreachable("Unhandle shader type");
248 }
249
250 LLVMSetFunctionCallConv(func, calling_conv);
251 }
252
253 #define MAX_ARGS 23
254 struct arg_info {
255 LLVMTypeRef types[MAX_ARGS];
256 LLVMValueRef *assign[MAX_ARGS];
257 unsigned array_params_mask;
258 uint8_t count;
259 uint8_t user_sgpr_count;
260 uint8_t sgpr_count;
261 uint8_t num_user_sgprs_used;
262 uint8_t num_sgprs_used;
263 uint8_t num_vgprs_used;
264 };
265
266 static inline void
267 add_argument(struct arg_info *info,
268 LLVMTypeRef type, LLVMValueRef *param_ptr)
269 {
270 assert(info->count < MAX_ARGS);
271 info->assign[info->count] = param_ptr;
272 info->types[info->count] = type;
273 info->count++;
274 }
275
276 static inline void
277 add_sgpr_argument(struct arg_info *info,
278 LLVMTypeRef type, LLVMValueRef *param_ptr)
279 {
280 add_argument(info, type, param_ptr);
281 info->num_sgprs_used += llvm_get_type_size(type) / 4;
282 info->sgpr_count++;
283 }
284
285 static inline void
286 add_user_sgpr_argument(struct arg_info *info,
287 LLVMTypeRef type,
288 LLVMValueRef *param_ptr)
289 {
290 add_sgpr_argument(info, type, param_ptr);
291 info->num_user_sgprs_used += llvm_get_type_size(type) / 4;
292 info->user_sgpr_count++;
293 }
294
295 static inline void
296 add_vgpr_argument(struct arg_info *info,
297 LLVMTypeRef type,
298 LLVMValueRef *param_ptr)
299 {
300 add_argument(info, type, param_ptr);
301 info->num_vgprs_used += llvm_get_type_size(type) / 4;
302 }
303
304 static inline void
305 add_user_sgpr_array_argument(struct arg_info *info,
306 LLVMTypeRef type,
307 LLVMValueRef *param_ptr)
308 {
309 info->array_params_mask |= (1 << info->count);
310 add_user_sgpr_argument(info, type, param_ptr);
311 }
312
313 static void assign_arguments(LLVMValueRef main_function,
314 struct arg_info *info)
315 {
316 unsigned i;
317 for (i = 0; i < info->count; i++) {
318 if (info->assign[i])
319 *info->assign[i] = LLVMGetParam(main_function, i);
320 }
321 }
322
323 static LLVMValueRef
324 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
325 LLVMBuilderRef builder, LLVMTypeRef *return_types,
326 unsigned num_return_elems,
327 struct arg_info *args,
328 unsigned max_workgroup_size,
329 bool unsafe_math)
330 {
331 LLVMTypeRef main_function_type, ret_type;
332 LLVMBasicBlockRef main_function_body;
333
334 if (num_return_elems)
335 ret_type = LLVMStructTypeInContext(ctx, return_types,
336 num_return_elems, true);
337 else
338 ret_type = LLVMVoidTypeInContext(ctx);
339
340 /* Setup the function */
341 main_function_type =
342 LLVMFunctionType(ret_type, args->types, args->count, 0);
343 LLVMValueRef main_function =
344 LLVMAddFunction(module, "main", main_function_type);
345 main_function_body =
346 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
347 LLVMPositionBuilderAtEnd(builder, main_function_body);
348
349 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
350 for (unsigned i = 0; i < args->sgpr_count; ++i) {
351 if (args->array_params_mask & (1 << i)) {
352 LLVMValueRef P = LLVMGetParam(main_function, i);
353 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_BYVAL);
354 ac_add_attr_dereferenceable(P, UINT64_MAX);
355 }
356 else {
357 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
358 }
359 }
360
361 if (max_workgroup_size) {
362 ac_llvm_add_target_dep_function_attr(main_function,
363 "amdgpu-max-work-group-size",
364 max_workgroup_size);
365 }
366 if (unsafe_math) {
367 /* These were copied from some LLVM test. */
368 LLVMAddTargetDependentFunctionAttr(main_function,
369 "less-precise-fpmad",
370 "true");
371 LLVMAddTargetDependentFunctionAttr(main_function,
372 "no-infs-fp-math",
373 "true");
374 LLVMAddTargetDependentFunctionAttr(main_function,
375 "no-nans-fp-math",
376 "true");
377 LLVMAddTargetDependentFunctionAttr(main_function,
378 "unsafe-fp-math",
379 "true");
380 }
381 return main_function;
382 }
383
384 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
385 {
386 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
387 CONST_ADDR_SPACE);
388 }
389
390 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
391 int idx,
392 LLVMTypeRef type)
393 {
394 LLVMValueRef offset;
395 LLVMValueRef ptr;
396 int addr_space;
397
398 offset = LLVMConstInt(ctx->i32, idx * 16, false);
399
400 ptr = ctx->shared_memory;
401 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
402 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
403 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
404 return ptr;
405 }
406
407 static LLVMTypeRef to_integer_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
408 {
409 if (t == ctx->f16 || t == ctx->i16)
410 return ctx->i16;
411 else if (t == ctx->f32 || t == ctx->i32)
412 return ctx->i32;
413 else if (t == ctx->f64 || t == ctx->i64)
414 return ctx->i64;
415 else
416 unreachable("Unhandled integer size");
417 }
418
419 static LLVMTypeRef to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
420 {
421 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
422 LLVMTypeRef elem_type = LLVMGetElementType(t);
423 return LLVMVectorType(to_integer_type_scalar(ctx, elem_type),
424 LLVMGetVectorSize(t));
425 }
426 return to_integer_type_scalar(ctx, t);
427 }
428
429 static LLVMValueRef to_integer(struct ac_llvm_context *ctx, LLVMValueRef v)
430 {
431 LLVMTypeRef type = LLVMTypeOf(v);
432 return LLVMBuildBitCast(ctx->builder, v, to_integer_type(ctx, type), "");
433 }
434
435 static LLVMTypeRef to_float_type_scalar(struct ac_llvm_context *ctx, LLVMTypeRef t)
436 {
437 if (t == ctx->i16 || t == ctx->f16)
438 return ctx->f16;
439 else if (t == ctx->i32 || t == ctx->f32)
440 return ctx->f32;
441 else if (t == ctx->i64 || t == ctx->f64)
442 return ctx->f64;
443 else
444 unreachable("Unhandled float size");
445 }
446
447 static LLVMTypeRef to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t)
448 {
449 if (LLVMGetTypeKind(t) == LLVMVectorTypeKind) {
450 LLVMTypeRef elem_type = LLVMGetElementType(t);
451 return LLVMVectorType(to_float_type_scalar(ctx, elem_type),
452 LLVMGetVectorSize(t));
453 }
454 return to_float_type_scalar(ctx, t);
455 }
456
457 static LLVMValueRef to_float(struct ac_llvm_context *ctx, LLVMValueRef v)
458 {
459 LLVMTypeRef type = LLVMTypeOf(v);
460 return LLVMBuildBitCast(ctx->builder, v, to_float_type(ctx, type), "");
461 }
462
463 static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
464 {
465 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
466 type = LLVMGetElementType(type);
467
468 if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
469 return LLVMGetIntTypeWidth(type);
470
471 if (type == ctx->f16)
472 return 16;
473 if (type == ctx->f32)
474 return 32;
475 if (type == ctx->f64)
476 return 64;
477
478 unreachable("Unhandled type kind in get_elem_bits");
479 }
480
481 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
482 LLVMValueRef param, unsigned rshift,
483 unsigned bitwidth)
484 {
485 LLVMValueRef value = param;
486 if (rshift)
487 value = LLVMBuildLShr(ctx->builder, value,
488 LLVMConstInt(ctx->i32, rshift, false), "");
489
490 if (rshift + bitwidth < 32) {
491 unsigned mask = (1 << bitwidth) - 1;
492 value = LLVMBuildAnd(ctx->builder, value,
493 LLVMConstInt(ctx->i32, mask, false), "");
494 }
495 return value;
496 }
497
498 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
499 {
500 switch (ctx->stage) {
501 case MESA_SHADER_TESS_CTRL:
502 return unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
503 case MESA_SHADER_TESS_EVAL:
504 return ctx->tes_rel_patch_id;
505 break;
506 default:
507 unreachable("Illegal stage");
508 }
509 }
510
511 /* Tessellation shaders pass outputs to the next shader using LDS.
512 *
513 * LS outputs = TCS inputs
514 * TCS outputs = TES inputs
515 *
516 * The LDS layout is:
517 * - TCS inputs for patch 0
518 * - TCS inputs for patch 1
519 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
520 * - ...
521 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
522 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
523 * - TCS outputs for patch 1
524 * - Per-patch TCS outputs for patch 1
525 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
526 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
527 * - ...
528 *
529 * All three shaders VS(LS), TCS, TES share the same LDS space.
530 */
531 static LLVMValueRef
532 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
533 {
534 if (ctx->stage == MESA_SHADER_VERTEX)
535 return unpack_param(ctx, ctx->ls_out_layout, 0, 13);
536 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
537 return unpack_param(ctx, ctx->tcs_in_layout, 0, 13);
538 else {
539 assert(0);
540 return NULL;
541 }
542 }
543
544 static LLVMValueRef
545 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
546 {
547 return unpack_param(ctx, ctx->tcs_out_layout, 0, 13);
548 }
549
550 static LLVMValueRef
551 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
552 {
553 return LLVMBuildMul(ctx->builder,
554 unpack_param(ctx, ctx->tcs_out_offsets, 0, 16),
555 LLVMConstInt(ctx->i32, 4, false), "");
556 }
557
558 static LLVMValueRef
559 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
560 {
561 return LLVMBuildMul(ctx->builder,
562 unpack_param(ctx, ctx->tcs_out_offsets, 16, 16),
563 LLVMConstInt(ctx->i32, 4, false), "");
564 }
565
566 static LLVMValueRef
567 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
568 {
569 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
570 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
571
572 return LLVMBuildMul(ctx->builder, patch_stride, rel_patch_id, "");
573 }
574
575 static LLVMValueRef
576 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
577 {
578 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
579 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
580 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
581
582 return LLVMBuildAdd(ctx->builder, patch0_offset,
583 LLVMBuildMul(ctx->builder, patch_stride,
584 rel_patch_id, ""),
585 "");
586 }
587
588 static LLVMValueRef
589 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
590 {
591 LLVMValueRef patch0_patch_data_offset =
592 get_tcs_out_patch0_patch_data_offset(ctx);
593 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
594 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
595
596 return LLVMBuildAdd(ctx->builder, patch0_patch_data_offset,
597 LLVMBuildMul(ctx->builder, patch_stride,
598 rel_patch_id, ""),
599 "");
600 }
601
602 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs)
603 {
604 ud_info->sgpr_idx = *sgpr_idx;
605 ud_info->num_sgprs = num_sgprs;
606 ud_info->indirect = false;
607 ud_info->indirect_offset = 0;
608 *sgpr_idx += num_sgprs;
609 }
610
611 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
612 int idx, uint8_t *sgpr_idx, uint8_t num_sgprs)
613 {
614 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
615 }
616
617
618 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
619 uint32_t indirect_offset)
620 {
621 ud_info->sgpr_idx = sgpr_idx;
622 ud_info->num_sgprs = num_sgprs;
623 ud_info->indirect = true;
624 ud_info->indirect_offset = indirect_offset;
625 }
626
627 static void declare_tess_lds(struct nir_to_llvm_context *ctx)
628 {
629 unsigned lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
630 ctx->lds = LLVMBuildIntToPtr(ctx->builder, ctx->i32zero,
631 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
632 "tess_lds");
633 }
634
635 struct user_sgpr_info {
636 bool need_ring_offsets;
637 uint8_t sgpr_count;
638 bool indirect_all_descriptor_sets;
639 };
640
641 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
642 struct user_sgpr_info *user_sgpr_info)
643 {
644 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
645
646 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
647 if (ctx->stage == MESA_SHADER_GEOMETRY ||
648 ctx->stage == MESA_SHADER_VERTEX ||
649 ctx->stage == MESA_SHADER_TESS_CTRL ||
650 ctx->stage == MESA_SHADER_TESS_EVAL ||
651 ctx->is_gs_copy_shader)
652 user_sgpr_info->need_ring_offsets = true;
653
654 if (ctx->stage == MESA_SHADER_FRAGMENT &&
655 ctx->shader_info->info.ps.needs_sample_positions)
656 user_sgpr_info->need_ring_offsets = true;
657
658 /* 2 user sgprs will nearly always be allocated for scratch/rings */
659 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
660 user_sgpr_info->sgpr_count += 2;
661 }
662
663 switch (ctx->stage) {
664 case MESA_SHADER_COMPUTE:
665 user_sgpr_info->sgpr_count += ctx->shader_info->info.cs.grid_components_used;
666 break;
667 case MESA_SHADER_FRAGMENT:
668 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
669 break;
670 case MESA_SHADER_VERTEX:
671 if (!ctx->is_gs_copy_shader) {
672 user_sgpr_info->sgpr_count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
673 if (ctx->shader_info->info.vs.needs_draw_id) {
674 user_sgpr_info->sgpr_count += 3;
675 } else {
676 user_sgpr_info->sgpr_count += 2;
677 }
678 }
679 if (ctx->options->key.vs.as_ls)
680 user_sgpr_info->sgpr_count++;
681 break;
682 case MESA_SHADER_TESS_CTRL:
683 user_sgpr_info->sgpr_count += 4;
684 break;
685 case MESA_SHADER_TESS_EVAL:
686 user_sgpr_info->sgpr_count += 1;
687 break;
688 case MESA_SHADER_GEOMETRY:
689 user_sgpr_info->sgpr_count += 2;
690 break;
691 default:
692 break;
693 }
694
695 if (ctx->shader_info->info.needs_push_constants)
696 user_sgpr_info->sgpr_count += 2;
697
698 uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
699 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
700 user_sgpr_info->sgpr_count += 2;
701 user_sgpr_info->indirect_all_descriptor_sets = true;
702 } else {
703 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
704 }
705 }
706
707 static void create_function(struct nir_to_llvm_context *ctx)
708 {
709 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
710 uint8_t user_sgpr_idx;
711 struct user_sgpr_info user_sgpr_info;
712 struct arg_info args = {};
713 LLVMValueRef desc_sets;
714
715 allocate_user_sgprs(ctx, &user_sgpr_info);
716 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
717 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */
718 }
719
720 /* 1 for each descriptor set */
721 if (!user_sgpr_info.indirect_all_descriptor_sets) {
722 for (unsigned i = 0; i < num_sets; ++i) {
723 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
724 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->descriptor_sets[i]);
725 }
726 }
727 } else
728 add_user_sgpr_array_argument(&args, const_array(const_array(ctx->i8, 1024 * 1024), 32), &desc_sets);
729
730 if (ctx->shader_info->info.needs_push_constants) {
731 /* 1 for push constants and dynamic descriptors */
732 add_user_sgpr_array_argument(&args, const_array(ctx->i8, 1024 * 1024), &ctx->push_constants);
733 }
734
735 switch (ctx->stage) {
736 case MESA_SHADER_COMPUTE:
737 if (ctx->shader_info->info.cs.grid_components_used)
738 add_user_sgpr_argument(&args, LLVMVectorType(ctx->i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
739 add_sgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->workgroup_ids);
740 add_sgpr_argument(&args, ctx->i32, &ctx->tg_size);
741 add_vgpr_argument(&args, LLVMVectorType(ctx->i32, 3), &ctx->local_invocation_ids);
742 break;
743 case MESA_SHADER_VERTEX:
744 if (!ctx->is_gs_copy_shader) {
745 if (ctx->shader_info->info.vs.has_vertex_buffers)
746 add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->vertex_buffers); /* vertex buffers */
747 add_user_sgpr_argument(&args, ctx->i32, &ctx->base_vertex); // base vertex
748 add_user_sgpr_argument(&args, ctx->i32, &ctx->start_instance);// start instance
749 if (ctx->shader_info->info.vs.needs_draw_id)
750 add_user_sgpr_argument(&args, ctx->i32, &ctx->draw_index); // draw id
751 }
752 if (ctx->options->key.vs.as_es)
753 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
754 else if (ctx->options->key.vs.as_ls)
755 add_user_sgpr_argument(&args, ctx->i32, &ctx->ls_out_layout); // ls out layout
756 add_vgpr_argument(&args, ctx->i32, &ctx->vertex_id); // vertex id
757 if (!ctx->is_gs_copy_shader) {
758 add_vgpr_argument(&args, ctx->i32, &ctx->rel_auto_id); // rel auto id
759 add_vgpr_argument(&args, ctx->i32, &ctx->vs_prim_id); // vs prim id
760 add_vgpr_argument(&args, ctx->i32, &ctx->instance_id); // instance id
761 }
762 break;
763 case MESA_SHADER_TESS_CTRL:
764 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
765 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_offsets); // tcs out offsets
766 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_out_layout); // tcs out layout
767 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_in_layout); // tcs in layout
768 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // param oc lds
769 add_sgpr_argument(&args, ctx->i32, &ctx->tess_factor_offset); // tess factor offset
770 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_patch_id); // patch id
771 add_vgpr_argument(&args, ctx->i32, &ctx->tcs_rel_ids); // rel ids;
772 break;
773 case MESA_SHADER_TESS_EVAL:
774 add_user_sgpr_argument(&args, ctx->i32, &ctx->tcs_offchip_layout); // tcs offchip layout
775 if (ctx->options->key.tes.as_es) {
776 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
777 add_sgpr_argument(&args, ctx->i32, NULL); //
778 add_sgpr_argument(&args, ctx->i32, &ctx->es2gs_offset); // es2gs offset
779 } else {
780 add_sgpr_argument(&args, ctx->i32, NULL); //
781 add_sgpr_argument(&args, ctx->i32, &ctx->oc_lds); // OC LDS
782 }
783 add_vgpr_argument(&args, ctx->f32, &ctx->tes_u); // tes_u
784 add_vgpr_argument(&args, ctx->f32, &ctx->tes_v); // tes_v
785 add_vgpr_argument(&args, ctx->i32, &ctx->tes_rel_patch_id); // tes rel patch id
786 add_vgpr_argument(&args, ctx->i32, &ctx->tes_patch_id); // tes patch id
787 break;
788 case MESA_SHADER_GEOMETRY:
789 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_ring_stride); // gsvs stride
790 add_user_sgpr_argument(&args, ctx->i32, &ctx->gsvs_num_entries); // gsvs num entires
791 add_sgpr_argument(&args, ctx->i32, &ctx->gs2vs_offset); // gs2vs offset
792 add_sgpr_argument(&args, ctx->i32, &ctx->gs_wave_id); // wave id
793 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[0]); // vtx0
794 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[1]); // vtx1
795 add_vgpr_argument(&args, ctx->i32, &ctx->gs_prim_id); // prim id
796 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[2]);
797 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[3]);
798 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[4]);
799 add_vgpr_argument(&args, ctx->i32, &ctx->gs_vtx_offset[5]);
800 add_vgpr_argument(&args, ctx->i32, &ctx->gs_invocation_id);
801 break;
802 case MESA_SHADER_FRAGMENT:
803 if (ctx->shader_info->info.ps.needs_sample_positions)
804 add_user_sgpr_argument(&args, ctx->i32, &ctx->sample_pos_offset); /* sample position offset */
805 add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim mask */
806 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /* persp sample */
807 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /* persp center */
808 add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /* persp centroid */
809 add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */
810 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /* linear sample */
811 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /* linear center */
812 add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /* linear centroid */
813 add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */
814 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos x float */
815 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos y float */
816 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos z float */
817 add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos w float */
818 add_vgpr_argument(&args, ctx->i32, &ctx->front_face); /* front face */
819 add_vgpr_argument(&args, ctx->i32, &ctx->ancillary); /* ancillary */
820 add_vgpr_argument(&args, ctx->i32, &ctx->sample_coverage); /* sample coverage */
821 add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
822 break;
823 default:
824 unreachable("Shader stage not implemented");
825 }
826
827 ctx->main_function = create_llvm_function(
828 ctx->context, ctx->module, ctx->builder, NULL, 0, &args,
829 ctx->max_workgroup_size,
830 ctx->options->unsafe_math);
831 set_llvm_calling_convention(ctx->main_function, ctx->stage);
832
833
834 ctx->shader_info->num_input_vgprs = 0;
835 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs =
836 ctx->options->supports_spill ? 2 : 0;
837
838 ctx->shader_info->num_user_sgprs += args.num_user_sgprs_used;
839 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
840
841 if (ctx->stage != MESA_SHADER_FRAGMENT)
842 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
843
844 assign_arguments(ctx->main_function, &args);
845
846 user_sgpr_idx = 0;
847
848 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
849 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, &user_sgpr_idx, 2);
850 if (ctx->options->supports_spill) {
851 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
852 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
853 NULL, 0, AC_FUNC_ATTR_READNONE);
854 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
855 const_array(ctx->v4i32, 16), "");
856 }
857 }
858
859 if (!user_sgpr_info.indirect_all_descriptor_sets) {
860 for (unsigned i = 0; i < num_sets; ++i) {
861 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
862 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], &user_sgpr_idx, 2);
863 } else
864 ctx->descriptor_sets[i] = NULL;
865 }
866 } else {
867 uint32_t desc_sgpr_idx = user_sgpr_idx;
868 set_userdata_location_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS, &user_sgpr_idx, 2);
869
870 for (unsigned i = 0; i < num_sets; ++i) {
871 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
872 set_userdata_location_indirect(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], desc_sgpr_idx, 2, i * 8);
873 ctx->descriptor_sets[i] = ac_build_indexed_load_const(&ctx->ac, desc_sets, LLVMConstInt(ctx->i32, i, false));
874
875 } else
876 ctx->descriptor_sets[i] = NULL;
877 }
878 ctx->shader_info->need_indirect_descriptor_sets = true;
879 }
880
881 if (ctx->shader_info->info.needs_push_constants) {
882 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, &user_sgpr_idx, 2);
883 }
884
885 switch (ctx->stage) {
886 case MESA_SHADER_COMPUTE:
887 if (ctx->shader_info->info.cs.grid_components_used) {
888 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
889 }
890 break;
891 case MESA_SHADER_VERTEX:
892 if (!ctx->is_gs_copy_shader) {
893 if (ctx->shader_info->info.vs.has_vertex_buffers) {
894 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, &user_sgpr_idx, 2);
895 }
896 unsigned vs_num = 2;
897 if (ctx->shader_info->info.vs.needs_draw_id)
898 vs_num++;
899
900 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, &user_sgpr_idx, vs_num);
901 }
902 if (ctx->options->key.vs.as_ls) {
903 set_userdata_location_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT, &user_sgpr_idx, 1);
904 }
905 if (ctx->options->key.vs.as_ls)
906 declare_tess_lds(ctx);
907 break;
908 case MESA_SHADER_TESS_CTRL:
909 set_userdata_location_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
910 declare_tess_lds(ctx);
911 break;
912 case MESA_SHADER_TESS_EVAL:
913 set_userdata_location_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
914 break;
915 case MESA_SHADER_GEOMETRY:
916 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, &user_sgpr_idx, 2);
917 break;
918 case MESA_SHADER_FRAGMENT:
919 if (ctx->shader_info->info.ps.needs_sample_positions) {
920 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET, &user_sgpr_idx, 1);
921 }
922 break;
923 default:
924 unreachable("Shader stage not implemented");
925 }
926 }
927
928 static void setup_types(struct nir_to_llvm_context *ctx)
929 {
930 LLVMValueRef args[4];
931
932 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
933 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
934 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
935 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
936 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
937 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
938 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
939 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
940 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
941 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
942 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
943 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
944 ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
945 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
946 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
947
948 ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
949 ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
950 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
951 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
952 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
953 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
954
955 args[0] = ctx->f32zero;
956 args[1] = ctx->f32zero;
957 args[2] = ctx->f32zero;
958 args[3] = ctx->f32one;
959 ctx->v4f32empty = LLVMConstVector(args, 4);
960
961 ctx->uniform_md_kind =
962 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
963 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
964
965 args[0] = LLVMConstReal(ctx->f32, 2.5);
966 }
967
968 static int get_llvm_num_components(LLVMValueRef value)
969 {
970 LLVMTypeRef type = LLVMTypeOf(value);
971 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
972 ? LLVMGetVectorSize(type)
973 : 1;
974 return num_components;
975 }
976
977 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
978 LLVMValueRef value,
979 int index)
980 {
981 int count = get_llvm_num_components(value);
982
983 assert(index < count);
984 if (count == 1)
985 return value;
986
987 return LLVMBuildExtractElement(ctx->builder, value,
988 LLVMConstInt(ctx->i32, index, false), "");
989 }
990
991 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
992 LLVMValueRef value, unsigned count)
993 {
994 unsigned num_components = get_llvm_num_components(value);
995 if (count == num_components)
996 return value;
997
998 LLVMValueRef masks[] = {
999 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1000 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1001
1002 if (count == 1)
1003 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1004 "");
1005
1006 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1007 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1008 }
1009
1010 static void
1011 build_store_values_extended(struct nir_to_llvm_context *ctx,
1012 LLVMValueRef *values,
1013 unsigned value_count,
1014 unsigned value_stride,
1015 LLVMValueRef vec)
1016 {
1017 LLVMBuilderRef builder = ctx->builder;
1018 unsigned i;
1019
1020 if (value_count == 1) {
1021 LLVMBuildStore(builder, vec, values[0]);
1022 return;
1023 }
1024
1025 for (i = 0; i < value_count; i++) {
1026 LLVMValueRef ptr = values[i * value_stride];
1027 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
1028 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1029 LLVMBuildStore(builder, value, ptr);
1030 }
1031 }
1032
1033 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
1034 const nir_ssa_def *def)
1035 {
1036 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
1037 if (def->num_components > 1) {
1038 type = LLVMVectorType(type, def->num_components);
1039 }
1040 return type;
1041 }
1042
1043 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
1044 {
1045 assert(src.is_ssa);
1046 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
1047 return (LLVMValueRef)entry->data;
1048 }
1049
1050
1051 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
1052 const struct nir_block *b)
1053 {
1054 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
1055 return (LLVMBasicBlockRef)entry->data;
1056 }
1057
1058 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
1059 nir_alu_src src,
1060 unsigned num_components)
1061 {
1062 LLVMValueRef value = get_src(ctx, src.src);
1063 bool need_swizzle = false;
1064
1065 assert(value);
1066 LLVMTypeRef type = LLVMTypeOf(value);
1067 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1068 ? LLVMGetVectorSize(type)
1069 : 1;
1070
1071 for (unsigned i = 0; i < num_components; ++i) {
1072 assert(src.swizzle[i] < src_components);
1073 if (src.swizzle[i] != i)
1074 need_swizzle = true;
1075 }
1076
1077 if (need_swizzle || num_components != src_components) {
1078 LLVMValueRef masks[] = {
1079 LLVMConstInt(ctx->i32, src.swizzle[0], false),
1080 LLVMConstInt(ctx->i32, src.swizzle[1], false),
1081 LLVMConstInt(ctx->i32, src.swizzle[2], false),
1082 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
1083
1084 if (src_components > 1 && num_components == 1) {
1085 value = LLVMBuildExtractElement(ctx->builder, value,
1086 masks[0], "");
1087 } else if (src_components == 1 && num_components > 1) {
1088 LLVMValueRef values[] = {value, value, value, value};
1089 value = ac_build_gather_values(&ctx->ac, values, num_components);
1090 } else {
1091 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1092 value = LLVMBuildShuffleVector(ctx->builder, value, value,
1093 swizzle, "");
1094 }
1095 }
1096 assert(!src.negate);
1097 assert(!src.abs);
1098 return value;
1099 }
1100
1101 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1102 LLVMIntPredicate pred, LLVMValueRef src0,
1103 LLVMValueRef src1)
1104 {
1105 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1106 return LLVMBuildSelect(ctx->builder, result,
1107 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1108 LLVMConstInt(ctx->i32, 0, false), "");
1109 }
1110
1111 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1112 LLVMRealPredicate pred, LLVMValueRef src0,
1113 LLVMValueRef src1)
1114 {
1115 LLVMValueRef result;
1116 src0 = to_float(ctx, src0);
1117 src1 = to_float(ctx, src1);
1118 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1119 return LLVMBuildSelect(ctx->builder, result,
1120 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1121 LLVMConstInt(ctx->i32, 0, false), "");
1122 }
1123
1124 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1125 const char *intrin,
1126 LLVMTypeRef result_type,
1127 LLVMValueRef src0)
1128 {
1129 char name[64];
1130 LLVMValueRef params[] = {
1131 to_float(ctx, src0),
1132 };
1133
1134 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1135 get_elem_bits(ctx, result_type));
1136 assert(length < sizeof(name));
1137 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1138 }
1139
1140 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1141 const char *intrin,
1142 LLVMTypeRef result_type,
1143 LLVMValueRef src0, LLVMValueRef src1)
1144 {
1145 char name[64];
1146 LLVMValueRef params[] = {
1147 to_float(ctx, src0),
1148 to_float(ctx, src1),
1149 };
1150
1151 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1152 get_elem_bits(ctx, result_type));
1153 assert(length < sizeof(name));
1154 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1155 }
1156
1157 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1158 const char *intrin,
1159 LLVMTypeRef result_type,
1160 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1161 {
1162 char name[64];
1163 LLVMValueRef params[] = {
1164 to_float(ctx, src0),
1165 to_float(ctx, src1),
1166 to_float(ctx, src2),
1167 };
1168
1169 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1170 get_elem_bits(ctx, result_type));
1171 assert(length < sizeof(name));
1172 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1173 }
1174
1175 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1176 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1177 {
1178 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1179 ctx->i32_0, "");
1180 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1181 }
1182
1183 static LLVMValueRef emit_find_lsb(struct ac_llvm_context *ctx,
1184 LLVMValueRef src0)
1185 {
1186 LLVMValueRef params[2] = {
1187 src0,
1188
1189 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
1190 * add special code to check for x=0. The reason is that
1191 * the LLVM behavior for x=0 is different from what we
1192 * need here.
1193 *
1194 * The hardware already implements the correct behavior.
1195 */
1196 LLVMConstInt(ctx->i1, 1, false),
1197 };
1198 return ac_build_intrinsic(ctx, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
1199 }
1200
1201 static LLVMValueRef emit_ifind_msb(struct ac_llvm_context *ctx,
1202 LLVMValueRef src0)
1203 {
1204 return ac_build_imsb(ctx, src0, ctx->i32);
1205 }
1206
1207 static LLVMValueRef emit_ufind_msb(struct ac_llvm_context *ctx,
1208 LLVMValueRef src0)
1209 {
1210 return ac_build_umsb(ctx, src0, ctx->i32);
1211 }
1212
1213 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1214 LLVMIntPredicate pred,
1215 LLVMValueRef src0, LLVMValueRef src1)
1216 {
1217 return LLVMBuildSelect(ctx->builder,
1218 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1219 src0,
1220 src1, "");
1221
1222 }
1223 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1224 LLVMValueRef src0)
1225 {
1226 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1227 LLVMBuildNeg(ctx->builder, src0, ""));
1228 }
1229
1230 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1231 LLVMValueRef src0)
1232 {
1233 LLVMValueRef cmp, val;
1234
1235 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
1236 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
1237 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
1238 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1239 return val;
1240 }
1241
1242 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1243 LLVMValueRef src0)
1244 {
1245 LLVMValueRef cmp, val;
1246
1247 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
1248 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
1249 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
1250 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1251 return val;
1252 }
1253
1254 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1255 LLVMValueRef src0)
1256 {
1257 const char *intr = "llvm.floor.f32";
1258 LLVMValueRef fsrc0 = to_float(ctx, src0);
1259 LLVMValueRef params[] = {
1260 fsrc0,
1261 };
1262 LLVMValueRef floor = ac_build_intrinsic(ctx, intr,
1263 ctx->f32, params, 1,
1264 AC_FUNC_ATTR_READNONE);
1265 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1266 }
1267
1268 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1269 const char *intrin,
1270 LLVMValueRef src0, LLVMValueRef src1)
1271 {
1272 LLVMTypeRef ret_type;
1273 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1274 LLVMValueRef res;
1275 LLVMValueRef params[] = { src0, src1 };
1276 ret_type = LLVMStructTypeInContext(ctx->context, types,
1277 2, true);
1278
1279 res = ac_build_intrinsic(ctx, intrin, ret_type,
1280 params, 2, AC_FUNC_ATTR_READNONE);
1281
1282 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1283 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1284 return res;
1285 }
1286
1287 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1288 LLVMValueRef src0)
1289 {
1290 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1291 }
1292
1293 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1294 LLVMValueRef src0)
1295 {
1296 src0 = to_float(ctx, src0);
1297 return LLVMBuildSExt(ctx->builder,
1298 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1299 ctx->i32, "");
1300 }
1301
1302 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1303 LLVMValueRef src0)
1304 {
1305 return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1306 }
1307
1308 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1309 LLVMValueRef src0)
1310 {
1311 return LLVMBuildSExt(ctx->builder,
1312 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1313 ctx->i32, "");
1314 }
1315
1316 static LLVMValueRef emit_f2f16(struct nir_to_llvm_context *ctx,
1317 LLVMValueRef src0)
1318 {
1319 LLVMValueRef result;
1320 LLVMValueRef cond;
1321
1322 src0 = to_float(&ctx->ac, src0);
1323 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1324
1325 /* TODO SI/CIK options here */
1326 if (ctx->options->chip_class >= VI) {
1327 LLVMValueRef args[2];
1328 /* Check if the result is a denormal - and flush to 0 if so. */
1329 args[0] = result;
1330 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1331 cond = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1332 }
1333
1334 /* need to convert back up to f32 */
1335 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1336
1337 if (ctx->options->chip_class >= VI)
1338 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32zero, result, "");
1339
1340 return result;
1341 }
1342
1343 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1344 LLVMValueRef src0, LLVMValueRef src1)
1345 {
1346 LLVMValueRef dst64, result;
1347 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1348 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1349
1350 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1351 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1352 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1353 return result;
1354 }
1355
1356 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0, LLVMValueRef src1)
1358 {
1359 LLVMValueRef dst64, result;
1360 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1361 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1362
1363 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1364 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1365 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1366 return result;
1367 }
1368
1369 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1370 bool is_signed,
1371 const LLVMValueRef srcs[3])
1372 {
1373 LLVMValueRef result;
1374 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1375
1376 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1377 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1378 return result;
1379 }
1380
1381 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1382 LLVMValueRef src0, LLVMValueRef src1,
1383 LLVMValueRef src2, LLVMValueRef src3)
1384 {
1385 LLVMValueRef bfi_args[3], result;
1386
1387 bfi_args[0] = LLVMBuildShl(ctx->builder,
1388 LLVMBuildSub(ctx->builder,
1389 LLVMBuildShl(ctx->builder,
1390 ctx->i32_1,
1391 src3, ""),
1392 ctx->i32_1, ""),
1393 src2, "");
1394 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1395 bfi_args[2] = src0;
1396
1397 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1398
1399 /* Calculate:
1400 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1401 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1402 */
1403 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1404 LLVMBuildAnd(ctx->builder, bfi_args[0],
1405 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1406
1407 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1408 return result;
1409 }
1410
1411 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1412 LLVMValueRef src0)
1413 {
1414 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1415 int i;
1416 LLVMValueRef comp[2];
1417
1418 src0 = to_float(ctx, src0);
1419 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1420 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1421 for (i = 0; i < 2; i++) {
1422 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1423 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1424 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1425 }
1426
1427 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1428 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1429
1430 return comp[0];
1431 }
1432
1433 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1434 LLVMValueRef src0)
1435 {
1436 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1437 LLVMValueRef temps[2], result, val;
1438 int i;
1439
1440 for (i = 0; i < 2; i++) {
1441 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1442 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1443 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1444 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1445 }
1446
1447 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
1448 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(v2f32), temps[0],
1449 ctx->i32_0, "");
1450 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1451 ctx->i32_1, "");
1452 return result;
1453 }
1454
1455 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1456 nir_op op,
1457 LLVMValueRef src0)
1458 {
1459 unsigned mask;
1460 int idx;
1461 LLVMValueRef result;
1462
1463 if (!ctx->lds && !ctx->has_ds_bpermute)
1464 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1465 LLVMArrayType(ctx->i32, 64),
1466 "ddxy_lds", LOCAL_ADDR_SPACE);
1467
1468 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1469 mask = AC_TID_MASK_LEFT;
1470 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1471 mask = AC_TID_MASK_TOP;
1472 else
1473 mask = AC_TID_MASK_TOP_LEFT;
1474
1475 /* for DDX we want to next X pixel, DDY next Y pixel. */
1476 if (op == nir_op_fddx_fine ||
1477 op == nir_op_fddx_coarse ||
1478 op == nir_op_fddx)
1479 idx = 1;
1480 else
1481 idx = 2;
1482
1483 result = ac_build_ddxy(&ctx->ac, ctx->has_ds_bpermute,
1484 mask, idx, ctx->lds,
1485 src0);
1486 return result;
1487 }
1488
1489 /*
1490 * this takes an I,J coordinate pair,
1491 * and works out the X and Y derivatives.
1492 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1493 */
1494 static LLVMValueRef emit_ddxy_interp(
1495 struct nir_to_llvm_context *ctx,
1496 LLVMValueRef interp_ij)
1497 {
1498 LLVMValueRef result[4], a;
1499 unsigned i;
1500
1501 for (i = 0; i < 2; i++) {
1502 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1503 LLVMConstInt(ctx->i32, i, false), "");
1504 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1505 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1506 }
1507 return ac_build_gather_values(&ctx->ac, result, 4);
1508 }
1509
1510 static void visit_alu(struct nir_to_llvm_context *ctx, const nir_alu_instr *instr)
1511 {
1512 LLVMValueRef src[4], result = NULL;
1513 unsigned num_components = instr->dest.dest.ssa.num_components;
1514 unsigned src_components;
1515 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1516
1517 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1518 switch (instr->op) {
1519 case nir_op_vec2:
1520 case nir_op_vec3:
1521 case nir_op_vec4:
1522 src_components = 1;
1523 break;
1524 case nir_op_pack_half_2x16:
1525 src_components = 2;
1526 break;
1527 case nir_op_unpack_half_2x16:
1528 src_components = 1;
1529 break;
1530 default:
1531 src_components = num_components;
1532 break;
1533 }
1534 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1535 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1536
1537 switch (instr->op) {
1538 case nir_op_fmov:
1539 case nir_op_imov:
1540 result = src[0];
1541 break;
1542 case nir_op_fneg:
1543 src[0] = to_float(&ctx->ac, src[0]);
1544 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1545 break;
1546 case nir_op_ineg:
1547 result = LLVMBuildNeg(ctx->builder, src[0], "");
1548 break;
1549 case nir_op_inot:
1550 result = LLVMBuildNot(ctx->builder, src[0], "");
1551 break;
1552 case nir_op_iadd:
1553 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1554 break;
1555 case nir_op_fadd:
1556 src[0] = to_float(&ctx->ac, src[0]);
1557 src[1] = to_float(&ctx->ac, src[1]);
1558 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1559 break;
1560 case nir_op_fsub:
1561 src[0] = to_float(&ctx->ac, src[0]);
1562 src[1] = to_float(&ctx->ac, src[1]);
1563 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1564 break;
1565 case nir_op_isub:
1566 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1567 break;
1568 case nir_op_imul:
1569 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1570 break;
1571 case nir_op_imod:
1572 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1573 break;
1574 case nir_op_umod:
1575 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1576 break;
1577 case nir_op_fmod:
1578 src[0] = to_float(&ctx->ac, src[0]);
1579 src[1] = to_float(&ctx->ac, src[1]);
1580 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1581 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1582 to_float_type(&ctx->ac, def_type), result);
1583 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1584 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1585 break;
1586 case nir_op_frem:
1587 src[0] = to_float(&ctx->ac, src[0]);
1588 src[1] = to_float(&ctx->ac, src[1]);
1589 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1590 break;
1591 case nir_op_irem:
1592 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1593 break;
1594 case nir_op_idiv:
1595 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1596 break;
1597 case nir_op_udiv:
1598 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1599 break;
1600 case nir_op_fmul:
1601 src[0] = to_float(&ctx->ac, src[0]);
1602 src[1] = to_float(&ctx->ac, src[1]);
1603 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1604 break;
1605 case nir_op_fdiv:
1606 src[0] = to_float(&ctx->ac, src[0]);
1607 src[1] = to_float(&ctx->ac, src[1]);
1608 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1609 break;
1610 case nir_op_frcp:
1611 src[0] = to_float(&ctx->ac, src[0]);
1612 result = ac_build_fdiv(&ctx->ac, ctx->f32one, src[0]);
1613 break;
1614 case nir_op_iand:
1615 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1616 break;
1617 case nir_op_ior:
1618 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1619 break;
1620 case nir_op_ixor:
1621 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1622 break;
1623 case nir_op_ishl:
1624 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1625 break;
1626 case nir_op_ishr:
1627 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1628 break;
1629 case nir_op_ushr:
1630 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1631 break;
1632 case nir_op_ilt:
1633 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1634 break;
1635 case nir_op_ine:
1636 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1637 break;
1638 case nir_op_ieq:
1639 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1640 break;
1641 case nir_op_ige:
1642 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1643 break;
1644 case nir_op_ult:
1645 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1646 break;
1647 case nir_op_uge:
1648 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1649 break;
1650 case nir_op_feq:
1651 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1652 break;
1653 case nir_op_fne:
1654 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1655 break;
1656 case nir_op_flt:
1657 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1658 break;
1659 case nir_op_fge:
1660 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1661 break;
1662 case nir_op_fabs:
1663 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1664 to_float_type(&ctx->ac, def_type), src[0]);
1665 break;
1666 case nir_op_iabs:
1667 result = emit_iabs(&ctx->ac, src[0]);
1668 break;
1669 case nir_op_imax:
1670 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1671 break;
1672 case nir_op_imin:
1673 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1674 break;
1675 case nir_op_umax:
1676 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1677 break;
1678 case nir_op_umin:
1679 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1680 break;
1681 case nir_op_isign:
1682 result = emit_isign(&ctx->ac, src[0]);
1683 break;
1684 case nir_op_fsign:
1685 src[0] = to_float(&ctx->ac, src[0]);
1686 result = emit_fsign(&ctx->ac, src[0]);
1687 break;
1688 case nir_op_ffloor:
1689 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1690 to_float_type(&ctx->ac, def_type), src[0]);
1691 break;
1692 case nir_op_ftrunc:
1693 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1694 to_float_type(&ctx->ac, def_type), src[0]);
1695 break;
1696 case nir_op_fceil:
1697 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1698 to_float_type(&ctx->ac, def_type), src[0]);
1699 break;
1700 case nir_op_fround_even:
1701 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1702 to_float_type(&ctx->ac, def_type),src[0]);
1703 break;
1704 case nir_op_ffract:
1705 result = emit_ffract(&ctx->ac, src[0]);
1706 break;
1707 case nir_op_fsin:
1708 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1709 to_float_type(&ctx->ac, def_type), src[0]);
1710 break;
1711 case nir_op_fcos:
1712 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1713 to_float_type(&ctx->ac, def_type), src[0]);
1714 break;
1715 case nir_op_fsqrt:
1716 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1717 to_float_type(&ctx->ac, def_type), src[0]);
1718 break;
1719 case nir_op_fexp2:
1720 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1721 to_float_type(&ctx->ac, def_type), src[0]);
1722 break;
1723 case nir_op_flog2:
1724 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1725 to_float_type(&ctx->ac, def_type), src[0]);
1726 break;
1727 case nir_op_frsq:
1728 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1729 to_float_type(&ctx->ac, def_type), src[0]);
1730 result = ac_build_fdiv(&ctx->ac, ctx->f32one, result);
1731 break;
1732 case nir_op_fpow:
1733 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1734 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1735 break;
1736 case nir_op_fmax:
1737 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1738 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1739 if (instr->dest.dest.ssa.bit_size == 32)
1740 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1741 to_float_type(&ctx->ac, def_type),
1742 result);
1743 break;
1744 case nir_op_fmin:
1745 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1746 to_float_type(&ctx->ac, def_type), src[0], src[1]);
1747 if (instr->dest.dest.ssa.bit_size == 32)
1748 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1749 to_float_type(&ctx->ac, def_type),
1750 result);
1751 break;
1752 case nir_op_ffma:
1753 result = emit_intrin_3f_param(&ctx->ac, "llvm.fma",
1754 to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1755 break;
1756 case nir_op_ibitfield_extract:
1757 result = emit_bitfield_extract(&ctx->ac, true, src);
1758 break;
1759 case nir_op_ubitfield_extract:
1760 result = emit_bitfield_extract(&ctx->ac, false, src);
1761 break;
1762 case nir_op_bitfield_insert:
1763 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1764 break;
1765 case nir_op_bitfield_reverse:
1766 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1767 break;
1768 case nir_op_bit_count:
1769 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1770 break;
1771 case nir_op_vec2:
1772 case nir_op_vec3:
1773 case nir_op_vec4:
1774 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1775 src[i] = to_integer(&ctx->ac, src[i]);
1776 result = ac_build_gather_values(&ctx->ac, src, num_components);
1777 break;
1778 case nir_op_f2i32:
1779 case nir_op_f2i64:
1780 src[0] = to_float(&ctx->ac, src[0]);
1781 result = LLVMBuildFPToSI(ctx->builder, src[0], def_type, "");
1782 break;
1783 case nir_op_f2u32:
1784 case nir_op_f2u64:
1785 src[0] = to_float(&ctx->ac, src[0]);
1786 result = LLVMBuildFPToUI(ctx->builder, src[0], def_type, "");
1787 break;
1788 case nir_op_i2f32:
1789 case nir_op_i2f64:
1790 result = LLVMBuildSIToFP(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1791 break;
1792 case nir_op_u2f32:
1793 case nir_op_u2f64:
1794 result = LLVMBuildUIToFP(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1795 break;
1796 case nir_op_f2f64:
1797 result = LLVMBuildFPExt(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1798 break;
1799 case nir_op_f2f32:
1800 result = LLVMBuildFPTrunc(ctx->builder, src[0], to_float_type(&ctx->ac, def_type), "");
1801 break;
1802 case nir_op_u2u32:
1803 case nir_op_u2u64:
1804 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1805 result = LLVMBuildZExt(ctx->builder, src[0], def_type, "");
1806 else
1807 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1808 break;
1809 case nir_op_i2i32:
1810 case nir_op_i2i64:
1811 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < get_elem_bits(&ctx->ac, def_type))
1812 result = LLVMBuildSExt(ctx->builder, src[0], def_type, "");
1813 else
1814 result = LLVMBuildTrunc(ctx->builder, src[0], def_type, "");
1815 break;
1816 case nir_op_bcsel:
1817 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1818 break;
1819 case nir_op_find_lsb:
1820 result = emit_find_lsb(&ctx->ac, src[0]);
1821 break;
1822 case nir_op_ufind_msb:
1823 result = emit_ufind_msb(&ctx->ac, src[0]);
1824 break;
1825 case nir_op_ifind_msb:
1826 result = emit_ifind_msb(&ctx->ac, src[0]);
1827 break;
1828 case nir_op_uadd_carry:
1829 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1830 break;
1831 case nir_op_usub_borrow:
1832 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1833 break;
1834 case nir_op_b2f:
1835 result = emit_b2f(&ctx->ac, src[0]);
1836 break;
1837 case nir_op_f2b:
1838 result = emit_f2b(&ctx->ac, src[0]);
1839 break;
1840 case nir_op_b2i:
1841 result = emit_b2i(&ctx->ac, src[0]);
1842 break;
1843 case nir_op_i2b:
1844 result = emit_i2b(&ctx->ac, src[0]);
1845 break;
1846 case nir_op_fquantize2f16:
1847 result = emit_f2f16(ctx, src[0]);
1848 break;
1849 case nir_op_umul_high:
1850 result = emit_umul_high(&ctx->ac, src[0], src[1]);
1851 break;
1852 case nir_op_imul_high:
1853 result = emit_imul_high(&ctx->ac, src[0], src[1]);
1854 break;
1855 case nir_op_pack_half_2x16:
1856 result = emit_pack_half_2x16(&ctx->ac, src[0]);
1857 break;
1858 case nir_op_unpack_half_2x16:
1859 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
1860 break;
1861 case nir_op_fddx:
1862 case nir_op_fddy:
1863 case nir_op_fddx_fine:
1864 case nir_op_fddy_fine:
1865 case nir_op_fddx_coarse:
1866 case nir_op_fddy_coarse:
1867 result = emit_ddxy(ctx, instr->op, src[0]);
1868 break;
1869 default:
1870 fprintf(stderr, "Unknown NIR alu instr: ");
1871 nir_print_instr(&instr->instr, stderr);
1872 fprintf(stderr, "\n");
1873 abort();
1874 }
1875
1876 if (result) {
1877 assert(instr->dest.dest.is_ssa);
1878 result = to_integer(&ctx->ac, result);
1879 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1880 result);
1881 }
1882 }
1883
1884 static void visit_load_const(struct nir_to_llvm_context *ctx,
1885 const nir_load_const_instr *instr)
1886 {
1887 LLVMValueRef values[4], value = NULL;
1888 LLVMTypeRef element_type =
1889 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1890
1891 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1892 switch (instr->def.bit_size) {
1893 case 32:
1894 values[i] = LLVMConstInt(element_type,
1895 instr->value.u32[i], false);
1896 break;
1897 case 64:
1898 values[i] = LLVMConstInt(element_type,
1899 instr->value.u64[i], false);
1900 break;
1901 default:
1902 fprintf(stderr,
1903 "unsupported nir load_const bit_size: %d\n",
1904 instr->def.bit_size);
1905 abort();
1906 }
1907 }
1908 if (instr->def.num_components > 1) {
1909 value = LLVMConstVector(values, instr->def.num_components);
1910 } else
1911 value = values[0];
1912
1913 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1914 }
1915
1916 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1917 LLVMTypeRef type)
1918 {
1919 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1920 return LLVMBuildBitCast(ctx->builder, ptr,
1921 LLVMPointerType(type, addr_space), "");
1922 }
1923
1924 static LLVMValueRef
1925 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1926 {
1927 LLVMValueRef size =
1928 LLVMBuildExtractElement(ctx->builder, descriptor,
1929 LLVMConstInt(ctx->i32, 2, false), "");
1930
1931 /* VI only */
1932 if (ctx->options->chip_class >= VI && in_elements) {
1933 /* On VI, the descriptor contains the size in bytes,
1934 * but TXQ must return the size in elements.
1935 * The stride is always non-zero for resources using TXQ.
1936 */
1937 LLVMValueRef stride =
1938 LLVMBuildExtractElement(ctx->builder, descriptor,
1939 LLVMConstInt(ctx->i32, 1, false), "");
1940 stride = LLVMBuildLShr(ctx->builder, stride,
1941 LLVMConstInt(ctx->i32, 16, false), "");
1942 stride = LLVMBuildAnd(ctx->builder, stride,
1943 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1944
1945 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1946 }
1947 return size;
1948 }
1949
1950 /**
1951 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1952 * intrinsic names).
1953 */
1954 static void build_int_type_name(
1955 LLVMTypeRef type,
1956 char *buf, unsigned bufsize)
1957 {
1958 assert(bufsize >= 6);
1959
1960 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1961 snprintf(buf, bufsize, "v%ui32",
1962 LLVMGetVectorSize(type));
1963 else
1964 strcpy(buf, "i32");
1965 }
1966
1967 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1968 struct ac_image_args *args,
1969 const nir_tex_instr *instr)
1970 {
1971 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1972 LLVMValueRef coord = args->addr;
1973 LLVMValueRef half_texel[2];
1974 LLVMValueRef compare_cube_wa;
1975 LLVMValueRef result;
1976 int c;
1977 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
1978
1979 //TODO Rect
1980 {
1981 struct ac_image_args txq_args = { 0 };
1982
1983 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1984 txq_args.opcode = ac_image_get_resinfo;
1985 txq_args.dmask = 0xf;
1986 txq_args.addr = ctx->i32zero;
1987 txq_args.resource = args->resource;
1988 LLVMValueRef size = ac_build_image_opcode(&ctx->ac, &txq_args);
1989
1990 for (c = 0; c < 2; c++) {
1991 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1992 LLVMConstInt(ctx->i32, c, false), "");
1993 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1994 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1995 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1996 LLVMConstReal(ctx->f32, -0.5), "");
1997 }
1998 }
1999
2000 LLVMValueRef orig_coords = args->addr;
2001
2002 for (c = 0; c < 2; c++) {
2003 LLVMValueRef tmp;
2004 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2005 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2006 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2007 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2008 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2009 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2010 }
2011
2012
2013 /*
2014 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2015 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2016 * workaround by sampling using a scaled type and converting.
2017 * This is taken from amdgpu-pro shaders.
2018 */
2019 /* NOTE this produces some ugly code compared to amdgpu-pro,
2020 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2021 * and then reads them back. -pro generates two selects,
2022 * one s_cmp for the descriptor rewriting
2023 * one v_cmp for the coordinate and result changes.
2024 */
2025 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2026 LLVMValueRef tmp, tmp2;
2027
2028 /* workaround 8/8/8/8 uint/sint cube gather bug */
2029 /* first detect it then change to a scaled read and f2i */
2030 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32one, "");
2031 tmp2 = tmp;
2032
2033 /* extract the DATA_FORMAT */
2034 tmp = ac_build_bfe(&ctx->ac, tmp, LLVMConstInt(ctx->i32, 20, false),
2035 LLVMConstInt(ctx->i32, 6, false), false);
2036
2037 /* is the DATA_FORMAT == 8_8_8_8 */
2038 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2039
2040 if (stype == GLSL_TYPE_UINT)
2041 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2042 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2043 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2044 else
2045 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2046 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2047 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2048
2049 /* replace the NUM FORMAT in the descriptor */
2050 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2051 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2052
2053 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32one, "");
2054
2055 /* don't modify the coordinates for this case */
2056 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2057 }
2058 args->addr = coord;
2059 result = ac_build_image_opcode(&ctx->ac, args);
2060
2061 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2062 LLVMValueRef tmp, tmp2;
2063
2064 /* if the cube workaround is in place, f2i the result. */
2065 for (c = 0; c < 4; c++) {
2066 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2067 if (stype == GLSL_TYPE_UINT)
2068 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2069 else
2070 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2071 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2072 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2073 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2074 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2075 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2076 }
2077 }
2078 return result;
2079 }
2080
2081 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
2082 const nir_tex_instr *instr,
2083 bool lod_is_zero,
2084 struct ac_image_args *args)
2085 {
2086 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2087 return ac_build_buffer_load_format(&ctx->ac,
2088 args->resource,
2089 args->addr,
2090 LLVMConstInt(ctx->i32, 0, false),
2091 true);
2092 }
2093
2094 args->opcode = ac_image_sample;
2095 args->compare = instr->is_shadow;
2096
2097 switch (instr->op) {
2098 case nir_texop_txf:
2099 case nir_texop_txf_ms:
2100 case nir_texop_samples_identical:
2101 args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip;
2102 args->compare = false;
2103 args->offset = false;
2104 break;
2105 case nir_texop_txb:
2106 args->bias = true;
2107 break;
2108 case nir_texop_txl:
2109 if (lod_is_zero)
2110 args->level_zero = true;
2111 else
2112 args->lod = true;
2113 break;
2114 case nir_texop_txs:
2115 case nir_texop_query_levels:
2116 args->opcode = ac_image_get_resinfo;
2117 break;
2118 case nir_texop_tex:
2119 if (ctx->stage != MESA_SHADER_FRAGMENT)
2120 args->level_zero = true;
2121 break;
2122 case nir_texop_txd:
2123 args->deriv = true;
2124 break;
2125 case nir_texop_tg4:
2126 args->opcode = ac_image_gather4;
2127 args->level_zero = true;
2128 break;
2129 case nir_texop_lod:
2130 args->opcode = ac_image_get_lod;
2131 args->compare = false;
2132 args->offset = false;
2133 break;
2134 default:
2135 break;
2136 }
2137
2138 if (instr->op == nir_texop_tg4) {
2139 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2140 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2141 return radv_lower_gather4_integer(ctx, args, instr);
2142 }
2143 }
2144 return ac_build_image_opcode(&ctx->ac, args);
2145 }
2146
2147 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
2148 nir_intrinsic_instr *instr)
2149 {
2150 LLVMValueRef index = get_src(ctx, instr->src[0]);
2151 unsigned desc_set = nir_intrinsic_desc_set(instr);
2152 unsigned binding = nir_intrinsic_binding(instr);
2153 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2154 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2155 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2156 unsigned base_offset = layout->binding[binding].offset;
2157 LLVMValueRef offset, stride;
2158
2159 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2160 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2161 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2162 layout->binding[binding].dynamic_offset_offset;
2163 desc_ptr = ctx->push_constants;
2164 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2165 stride = LLVMConstInt(ctx->i32, 16, false);
2166 } else
2167 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
2168
2169 offset = LLVMConstInt(ctx->i32, base_offset, false);
2170 index = LLVMBuildMul(ctx->builder, index, stride, "");
2171 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
2172
2173 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2174 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
2175 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
2176
2177 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
2178 }
2179
2180 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
2181 nir_intrinsic_instr *instr)
2182 {
2183 LLVMValueRef ptr, addr;
2184
2185 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
2186 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
2187
2188 ptr = ac_build_gep0(&ctx->ac, ctx->push_constants, addr);
2189 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
2190
2191 return LLVMBuildLoad(ctx->builder, ptr, "");
2192 }
2193
2194 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
2195 const nir_intrinsic_instr *instr)
2196 {
2197 LLVMValueRef desc = get_src(ctx, instr->src[0]);
2198
2199 return get_buffer_size(ctx, desc, false);
2200 }
2201 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
2202 nir_intrinsic_instr *instr)
2203 {
2204 const char *store_name;
2205 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2206 LLVMTypeRef data_type = ctx->f32;
2207 int elem_size_mult = get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2208 int components_32bit = elem_size_mult * instr->num_components;
2209 unsigned writemask = nir_intrinsic_write_mask(instr);
2210 LLVMValueRef base_data, base_offset;
2211 LLVMValueRef params[6];
2212
2213 if (ctx->stage == MESA_SHADER_FRAGMENT)
2214 ctx->shader_info->fs.writes_memory = true;
2215
2216 params[1] = get_src(ctx, instr->src[1]);
2217 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2218 params[4] = ctx->i1false; /* glc */
2219 params[5] = ctx->i1false; /* slc */
2220
2221 if (components_32bit > 1)
2222 data_type = LLVMVectorType(ctx->f32, components_32bit);
2223
2224 base_data = to_float(&ctx->ac, src_data);
2225 base_data = trim_vector(ctx, base_data, instr->num_components);
2226 base_data = LLVMBuildBitCast(ctx->builder, base_data,
2227 data_type, "");
2228 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2229 while (writemask) {
2230 int start, count;
2231 LLVMValueRef data;
2232 LLVMValueRef offset;
2233 LLVMValueRef tmp;
2234 u_bit_scan_consecutive_range(&writemask, &start, &count);
2235
2236 /* Due to an LLVM limitation, split 3-element writes
2237 * into a 2-element and a 1-element write. */
2238 if (count == 3) {
2239 writemask |= 1 << (start + 2);
2240 count = 2;
2241 }
2242
2243 start *= elem_size_mult;
2244 count *= elem_size_mult;
2245
2246 if (count > 4) {
2247 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2248 count = 4;
2249 }
2250
2251 if (count == 4) {
2252 store_name = "llvm.amdgcn.buffer.store.v4f32";
2253 data = base_data;
2254 } else if (count == 2) {
2255 tmp = LLVMBuildExtractElement(ctx->builder,
2256 base_data, LLVMConstInt(ctx->i32, start, false), "");
2257 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
2258 ctx->i32zero, "");
2259
2260 tmp = LLVMBuildExtractElement(ctx->builder,
2261 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
2262 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
2263 ctx->i32one, "");
2264 store_name = "llvm.amdgcn.buffer.store.v2f32";
2265
2266 } else {
2267 assert(count == 1);
2268 if (get_llvm_num_components(base_data) > 1)
2269 data = LLVMBuildExtractElement(ctx->builder, base_data,
2270 LLVMConstInt(ctx->i32, start, false), "");
2271 else
2272 data = base_data;
2273 store_name = "llvm.amdgcn.buffer.store.f32";
2274 }
2275
2276 offset = base_offset;
2277 if (start != 0) {
2278 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
2279 }
2280 params[0] = data;
2281 params[3] = offset;
2282 ac_build_intrinsic(&ctx->ac, store_name,
2283 ctx->voidt, params, 6, 0);
2284 }
2285 }
2286
2287 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
2288 const nir_intrinsic_instr *instr)
2289 {
2290 const char *name;
2291 LLVMValueRef params[6];
2292 int arg_count = 0;
2293 if (ctx->stage == MESA_SHADER_FRAGMENT)
2294 ctx->shader_info->fs.writes_memory = true;
2295
2296 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2297 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
2298 }
2299 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
2300 params[arg_count++] = get_src(ctx, instr->src[0]);
2301 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
2302 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2303 params[arg_count++] = ctx->i1false; /* slc */
2304
2305 switch (instr->intrinsic) {
2306 case nir_intrinsic_ssbo_atomic_add:
2307 name = "llvm.amdgcn.buffer.atomic.add";
2308 break;
2309 case nir_intrinsic_ssbo_atomic_imin:
2310 name = "llvm.amdgcn.buffer.atomic.smin";
2311 break;
2312 case nir_intrinsic_ssbo_atomic_umin:
2313 name = "llvm.amdgcn.buffer.atomic.umin";
2314 break;
2315 case nir_intrinsic_ssbo_atomic_imax:
2316 name = "llvm.amdgcn.buffer.atomic.smax";
2317 break;
2318 case nir_intrinsic_ssbo_atomic_umax:
2319 name = "llvm.amdgcn.buffer.atomic.umax";
2320 break;
2321 case nir_intrinsic_ssbo_atomic_and:
2322 name = "llvm.amdgcn.buffer.atomic.and";
2323 break;
2324 case nir_intrinsic_ssbo_atomic_or:
2325 name = "llvm.amdgcn.buffer.atomic.or";
2326 break;
2327 case nir_intrinsic_ssbo_atomic_xor:
2328 name = "llvm.amdgcn.buffer.atomic.xor";
2329 break;
2330 case nir_intrinsic_ssbo_atomic_exchange:
2331 name = "llvm.amdgcn.buffer.atomic.swap";
2332 break;
2333 case nir_intrinsic_ssbo_atomic_comp_swap:
2334 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2335 break;
2336 default:
2337 abort();
2338 }
2339
2340 return ac_build_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2341 }
2342
2343 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2344 const nir_intrinsic_instr *instr)
2345 {
2346 LLVMValueRef results[2];
2347 int load_components;
2348 int num_components = instr->num_components;
2349 if (instr->dest.ssa.bit_size == 64)
2350 num_components *= 2;
2351
2352 for (int i = 0; i < num_components; i += load_components) {
2353 load_components = MIN2(num_components - i, 4);
2354 const char *load_name;
2355 LLVMTypeRef data_type = ctx->f32;
2356 LLVMValueRef offset = LLVMConstInt(ctx->i32, i * 4, false);
2357 offset = LLVMBuildAdd(ctx->builder, get_src(ctx, instr->src[1]), offset, "");
2358
2359 if (load_components == 3)
2360 data_type = LLVMVectorType(ctx->f32, 4);
2361 else if (load_components > 1)
2362 data_type = LLVMVectorType(ctx->f32, load_components);
2363
2364 if (load_components >= 3)
2365 load_name = "llvm.amdgcn.buffer.load.v4f32";
2366 else if (load_components == 2)
2367 load_name = "llvm.amdgcn.buffer.load.v2f32";
2368 else if (load_components == 1)
2369 load_name = "llvm.amdgcn.buffer.load.f32";
2370 else
2371 unreachable("unhandled number of components");
2372
2373 LLVMValueRef params[] = {
2374 get_src(ctx, instr->src[0]),
2375 LLVMConstInt(ctx->i32, 0, false),
2376 offset,
2377 ctx->i1false,
2378 ctx->i1false,
2379 };
2380
2381 results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2382
2383 }
2384
2385 LLVMValueRef ret = results[0];
2386 if (num_components > 4 || num_components == 3) {
2387 LLVMValueRef masks[] = {
2388 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2389 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2390 LLVMConstInt(ctx->i32, 4, false), LLVMConstInt(ctx->i32, 5, false),
2391 LLVMConstInt(ctx->i32, 6, false), LLVMConstInt(ctx->i32, 7, false)
2392 };
2393
2394 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2395 ret = LLVMBuildShuffleVector(ctx->builder, results[0],
2396 results[num_components > 4 ? 1 : 0], swizzle, "");
2397 }
2398
2399 return LLVMBuildBitCast(ctx->builder, ret,
2400 get_def_type(ctx, &instr->dest.ssa), "");
2401 }
2402
2403 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2404 const nir_intrinsic_instr *instr)
2405 {
2406 LLVMValueRef results[8], ret;
2407 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2408 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2409 int num_components = instr->num_components;
2410
2411 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2412
2413 if (instr->dest.ssa.bit_size == 64)
2414 num_components *= 2;
2415
2416 for (unsigned i = 0; i < num_components; ++i) {
2417 LLVMValueRef params[] = {
2418 rsrc,
2419 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2420 offset, "")
2421 };
2422 results[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2423 params, 2,
2424 AC_FUNC_ATTR_READNONE |
2425 AC_FUNC_ATTR_LEGACY);
2426 }
2427
2428
2429 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2430 return LLVMBuildBitCast(ctx->builder, ret,
2431 get_def_type(ctx, &instr->dest.ssa), "");
2432 }
2433
2434 static void
2435 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref_var *deref,
2436 bool vs_in, unsigned *vertex_index_out,
2437 LLVMValueRef *vertex_index_ref,
2438 unsigned *const_out, LLVMValueRef *indir_out)
2439 {
2440 unsigned const_offset = 0;
2441 nir_deref *tail = &deref->deref;
2442 LLVMValueRef offset = NULL;
2443
2444 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2445 tail = tail->child;
2446 nir_deref_array *deref_array = nir_deref_as_array(tail);
2447 if (vertex_index_out)
2448 *vertex_index_out = deref_array->base_offset;
2449
2450 if (vertex_index_ref) {
2451 LLVMValueRef vtx = LLVMConstInt(ctx->i32, deref_array->base_offset, false);
2452 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2453 vtx = LLVMBuildAdd(ctx->builder, vtx, get_src(ctx, deref_array->indirect), "");
2454 }
2455 *vertex_index_ref = vtx;
2456 }
2457 }
2458
2459 if (deref->var->data.compact) {
2460 assert(tail->child->deref_type == nir_deref_type_array);
2461 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2462 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2463 /* We always lower indirect dereferences for "compact" array vars. */
2464 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2465
2466 const_offset = deref_array->base_offset;
2467 goto out;
2468 }
2469
2470 while (tail->child != NULL) {
2471 const struct glsl_type *parent_type = tail->type;
2472 tail = tail->child;
2473
2474 if (tail->deref_type == nir_deref_type_array) {
2475 nir_deref_array *deref_array = nir_deref_as_array(tail);
2476 LLVMValueRef index, stride, local_offset;
2477 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2478
2479 const_offset += size * deref_array->base_offset;
2480 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2481 continue;
2482
2483 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2484 index = get_src(ctx, deref_array->indirect);
2485 stride = LLVMConstInt(ctx->i32, size, 0);
2486 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2487
2488 if (offset)
2489 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2490 else
2491 offset = local_offset;
2492 } else if (tail->deref_type == nir_deref_type_struct) {
2493 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2494
2495 for (unsigned i = 0; i < deref_struct->index; i++) {
2496 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2497 const_offset += glsl_count_attribute_slots(ft, vs_in);
2498 }
2499 } else
2500 unreachable("unsupported deref type");
2501
2502 }
2503 out:
2504 if (const_offset && offset)
2505 offset = LLVMBuildAdd(ctx->builder, offset,
2506 LLVMConstInt(ctx->i32, const_offset, 0),
2507 "");
2508
2509 *const_out = const_offset;
2510 *indir_out = offset;
2511 }
2512
2513 static LLVMValueRef
2514 lds_load(struct nir_to_llvm_context *ctx,
2515 LLVMValueRef dw_addr)
2516 {
2517 LLVMValueRef value;
2518 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
2519 return value;
2520 }
2521
2522 static void
2523 lds_store(struct nir_to_llvm_context *ctx,
2524 LLVMValueRef dw_addr, LLVMValueRef value)
2525 {
2526 value = LLVMBuildBitCast(ctx->builder, value, ctx->i32, "");
2527 ac_build_indexed_store(&ctx->ac, ctx->lds,
2528 dw_addr, value);
2529 }
2530
2531 /* The offchip buffer layout for TCS->TES is
2532 *
2533 * - attribute 0 of patch 0 vertex 0
2534 * - attribute 0 of patch 0 vertex 1
2535 * - attribute 0 of patch 0 vertex 2
2536 * ...
2537 * - attribute 0 of patch 1 vertex 0
2538 * - attribute 0 of patch 1 vertex 1
2539 * ...
2540 * - attribute 1 of patch 0 vertex 0
2541 * - attribute 1 of patch 0 vertex 1
2542 * ...
2543 * - per patch attribute 0 of patch 0
2544 * - per patch attribute 0 of patch 1
2545 * ...
2546 *
2547 * Note that every attribute has 4 components.
2548 */
2549 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2550 LLVMValueRef vertex_index,
2551 LLVMValueRef param_index)
2552 {
2553 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2554 LLVMValueRef param_stride, constant16;
2555 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2556
2557 vertices_per_patch = unpack_param(ctx, ctx->tcs_offchip_layout, 9, 6);
2558 num_patches = unpack_param(ctx, ctx->tcs_offchip_layout, 0, 9);
2559 total_vertices = LLVMBuildMul(ctx->builder, vertices_per_patch,
2560 num_patches, "");
2561
2562 constant16 = LLVMConstInt(ctx->i32, 16, false);
2563 if (vertex_index) {
2564 base_addr = LLVMBuildMul(ctx->builder, rel_patch_id,
2565 vertices_per_patch, "");
2566
2567 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2568 vertex_index, "");
2569
2570 param_stride = total_vertices;
2571 } else {
2572 base_addr = rel_patch_id;
2573 param_stride = num_patches;
2574 }
2575
2576 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2577 LLVMBuildMul(ctx->builder, param_index,
2578 param_stride, ""), "");
2579
2580 base_addr = LLVMBuildMul(ctx->builder, base_addr, constant16, "");
2581
2582 if (!vertex_index) {
2583 LLVMValueRef patch_data_offset =
2584 unpack_param(ctx, ctx->tcs_offchip_layout, 16, 16);
2585
2586 base_addr = LLVMBuildAdd(ctx->builder, base_addr,
2587 patch_data_offset, "");
2588 }
2589 return base_addr;
2590 }
2591
2592 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2593 unsigned param,
2594 unsigned const_index,
2595 bool is_compact,
2596 LLVMValueRef vertex_index,
2597 LLVMValueRef indir_index)
2598 {
2599 LLVMValueRef param_index;
2600
2601 if (indir_index)
2602 param_index = LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, param, false),
2603 indir_index, "");
2604 else {
2605 if (const_index && !is_compact)
2606 param += const_index;
2607 param_index = LLVMConstInt(ctx->i32, param, false);
2608 }
2609 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2610 }
2611
2612 static void
2613 mark_tess_output(struct nir_to_llvm_context *ctx,
2614 bool is_patch, uint32_t param)
2615
2616 {
2617 if (is_patch) {
2618 ctx->tess_patch_outputs_written |= (1ull << param);
2619 } else
2620 ctx->tess_outputs_written |= (1ull << param);
2621 }
2622
2623 static LLVMValueRef
2624 get_dw_address(struct nir_to_llvm_context *ctx,
2625 LLVMValueRef dw_addr,
2626 unsigned param,
2627 unsigned const_index,
2628 bool compact_const_index,
2629 LLVMValueRef vertex_index,
2630 LLVMValueRef stride,
2631 LLVMValueRef indir_index)
2632
2633 {
2634
2635 if (vertex_index) {
2636 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2637 LLVMBuildMul(ctx->builder,
2638 vertex_index,
2639 stride, ""), "");
2640 }
2641
2642 if (indir_index)
2643 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2644 LLVMBuildMul(ctx->builder, indir_index,
2645 LLVMConstInt(ctx->i32, 4, false), ""), "");
2646 else if (const_index && !compact_const_index)
2647 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2648 LLVMConstInt(ctx->i32, const_index, false), "");
2649
2650 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2651 LLVMConstInt(ctx->i32, param * 4, false), "");
2652
2653 if (const_index && compact_const_index)
2654 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2655 LLVMConstInt(ctx->i32, const_index, false), "");
2656 return dw_addr;
2657 }
2658
2659 static LLVMValueRef
2660 load_tcs_input(struct nir_to_llvm_context *ctx,
2661 nir_intrinsic_instr *instr)
2662 {
2663 LLVMValueRef dw_addr, stride;
2664 unsigned const_index;
2665 LLVMValueRef vertex_index;
2666 LLVMValueRef indir_index;
2667 unsigned param;
2668 LLVMValueRef value[4], result;
2669 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2670 const bool is_compact = instr->variables[0]->var->data.compact;
2671 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2672 radv_get_deref_offset(ctx, instr->variables[0],
2673 false, NULL, per_vertex ? &vertex_index : NULL,
2674 &const_index, &indir_index);
2675
2676 stride = unpack_param(ctx, ctx->tcs_in_layout, 13, 8);
2677 dw_addr = get_tcs_in_current_patch_offset(ctx);
2678 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2679 indir_index);
2680
2681 for (unsigned i = 0; i < instr->num_components; i++) {
2682 value[i] = lds_load(ctx, dw_addr);
2683 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2684 ctx->i32one, "");
2685 }
2686 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2687 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2688 return result;
2689 }
2690
2691 static LLVMValueRef
2692 load_tcs_output(struct nir_to_llvm_context *ctx,
2693 nir_intrinsic_instr *instr)
2694 {
2695 LLVMValueRef dw_addr, stride;
2696 LLVMValueRef value[4], result;
2697 LLVMValueRef vertex_index = NULL;
2698 LLVMValueRef indir_index = NULL;
2699 unsigned const_index = 0;
2700 unsigned param;
2701 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2702 const bool is_compact = instr->variables[0]->var->data.compact;
2703 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2704 radv_get_deref_offset(ctx, instr->variables[0],
2705 false, NULL, per_vertex ? &vertex_index : NULL,
2706 &const_index, &indir_index);
2707
2708 if (!instr->variables[0]->var->data.patch) {
2709 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2710 dw_addr = get_tcs_out_current_patch_offset(ctx);
2711 } else {
2712 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2713 }
2714
2715 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2716 indir_index);
2717
2718 for (unsigned i = 0; i < instr->num_components; i++) {
2719 value[i] = lds_load(ctx, dw_addr);
2720 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2721 ctx->i32one, "");
2722 }
2723 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2724 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2725 return result;
2726 }
2727
2728 static void
2729 store_tcs_output(struct nir_to_llvm_context *ctx,
2730 nir_intrinsic_instr *instr,
2731 LLVMValueRef src,
2732 unsigned writemask)
2733 {
2734 LLVMValueRef stride, dw_addr;
2735 LLVMValueRef buf_addr = NULL;
2736 LLVMValueRef vertex_index = NULL;
2737 LLVMValueRef indir_index = NULL;
2738 unsigned const_index = 0;
2739 unsigned param;
2740 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2741 const bool is_compact = instr->variables[0]->var->data.compact;
2742
2743 radv_get_deref_offset(ctx, instr->variables[0],
2744 false, NULL, per_vertex ? &vertex_index : NULL,
2745 &const_index, &indir_index);
2746
2747 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2748 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2749 is_compact && const_index > 3) {
2750 const_index -= 3;
2751 param++;
2752 }
2753
2754 if (!instr->variables[0]->var->data.patch) {
2755 stride = unpack_param(ctx, ctx->tcs_out_layout, 13, 8);
2756 dw_addr = get_tcs_out_current_patch_offset(ctx);
2757 } else {
2758 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2759 }
2760
2761 mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
2762
2763 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2764 indir_index);
2765 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2766 vertex_index, indir_index);
2767
2768 unsigned base = is_compact ? const_index : 0;
2769 for (unsigned chan = 0; chan < 8; chan++) {
2770 bool is_tess_factor = false;
2771 if (!(writemask & (1 << chan)))
2772 continue;
2773 LLVMValueRef value = llvm_extract_elem(ctx, src, chan);
2774
2775 lds_store(ctx, dw_addr, value);
2776
2777 if (instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
2778 instr->variables[0]->var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
2779 is_tess_factor = true;
2780
2781 if (!is_tess_factor && writemask != 0xF)
2782 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2783 buf_addr, ctx->oc_lds,
2784 4 * (base + chan), 1, 0, true, false);
2785
2786 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
2787 ctx->i32one, "");
2788 }
2789
2790 if (writemask == 0xF) {
2791 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2792 buf_addr, ctx->oc_lds,
2793 (base * 4), 1, 0, true, false);
2794 }
2795 }
2796
2797 static LLVMValueRef
2798 load_tes_input(struct nir_to_llvm_context *ctx,
2799 const nir_intrinsic_instr *instr)
2800 {
2801 LLVMValueRef buf_addr;
2802 LLVMValueRef result;
2803 LLVMValueRef vertex_index = NULL;
2804 LLVMValueRef indir_index = NULL;
2805 unsigned const_index = 0;
2806 unsigned param;
2807 const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, ctx->stage);
2808 const bool is_compact = instr->variables[0]->var->data.compact;
2809
2810 radv_get_deref_offset(ctx, instr->variables[0],
2811 false, NULL, per_vertex ? &vertex_index : NULL,
2812 &const_index, &indir_index);
2813 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2814 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 &&
2815 is_compact && const_index > 3) {
2816 const_index -= 3;
2817 param++;
2818 }
2819 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
2820 is_compact, vertex_index, indir_index);
2821
2822 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, instr->num_components, NULL,
2823 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
2824 result = trim_vector(ctx, result, instr->num_components);
2825 result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx, &instr->dest.ssa), "");
2826 return result;
2827 }
2828
2829 static LLVMValueRef
2830 load_gs_input(struct nir_to_llvm_context *ctx,
2831 nir_intrinsic_instr *instr)
2832 {
2833 LLVMValueRef indir_index, vtx_offset;
2834 unsigned const_index;
2835 LLVMValueRef args[9];
2836 unsigned param, vtx_offset_param;
2837 LLVMValueRef value[4], result;
2838 unsigned vertex_index;
2839 radv_get_deref_offset(ctx, instr->variables[0],
2840 false, &vertex_index, NULL,
2841 &const_index, &indir_index);
2842 vtx_offset_param = vertex_index;
2843 assert(vtx_offset_param < 6);
2844 vtx_offset = LLVMBuildMul(ctx->builder, ctx->gs_vtx_offset[vtx_offset_param],
2845 LLVMConstInt(ctx->i32, 4, false), "");
2846
2847 param = shader_io_get_unique_index(instr->variables[0]->var->data.location);
2848 for (unsigned i = 0; i < instr->num_components; i++) {
2849
2850 args[0] = ctx->esgs_ring;
2851 args[1] = vtx_offset;
2852 args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) * 256, false);
2853 args[3] = ctx->i32zero;
2854 args[4] = ctx->i32one; /* OFFEN */
2855 args[5] = ctx->i32zero; /* IDXEN */
2856 args[6] = ctx->i32one; /* GLC */
2857 args[7] = ctx->i32zero; /* SLC */
2858 args[8] = ctx->i32zero; /* TFE */
2859
2860 value[i] = ac_build_intrinsic(&ctx->ac, "llvm.SI.buffer.load.dword.i32.i32",
2861 ctx->i32, args, 9,
2862 AC_FUNC_ATTR_READONLY |
2863 AC_FUNC_ATTR_LEGACY);
2864 }
2865 result = ac_build_gather_values(&ctx->ac, value, instr->num_components);
2866
2867 return result;
2868 }
2869
2870 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2871 nir_intrinsic_instr *instr)
2872 {
2873 LLVMValueRef values[8];
2874 int idx = instr->variables[0]->var->data.driver_location;
2875 int ve = instr->dest.ssa.num_components;
2876 LLVMValueRef indir_index;
2877 LLVMValueRef ret;
2878 unsigned const_index;
2879 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
2880 instr->variables[0]->var->data.mode == nir_var_shader_in;
2881 radv_get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
2882 &const_index, &indir_index);
2883
2884 if (instr->dest.ssa.bit_size == 64)
2885 ve *= 2;
2886
2887 switch (instr->variables[0]->var->data.mode) {
2888 case nir_var_shader_in:
2889 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2890 return load_tcs_input(ctx, instr);
2891 if (ctx->stage == MESA_SHADER_TESS_EVAL)
2892 return load_tes_input(ctx, instr);
2893 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2894 return load_gs_input(ctx, instr);
2895 }
2896 for (unsigned chan = 0; chan < ve; chan++) {
2897 if (indir_index) {
2898 unsigned count = glsl_count_attribute_slots(
2899 instr->variables[0]->var->type,
2900 ctx->stage == MESA_SHADER_VERTEX);
2901 count -= chan / 4;
2902 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2903 &ctx->ac, ctx->inputs + idx + chan, count,
2904 4, false);
2905
2906 values[chan] = LLVMBuildExtractElement(ctx->builder,
2907 tmp_vec,
2908 indir_index, "");
2909 } else
2910 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2911 }
2912 break;
2913 case nir_var_local:
2914 for (unsigned chan = 0; chan < ve; chan++) {
2915 if (indir_index) {
2916 unsigned count = glsl_count_attribute_slots(
2917 instr->variables[0]->var->type, false);
2918 count -= chan / 4;
2919 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2920 &ctx->ac, ctx->locals + idx + chan, count,
2921 4, true);
2922
2923 values[chan] = LLVMBuildExtractElement(ctx->builder,
2924 tmp_vec,
2925 indir_index, "");
2926 } else {
2927 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2928 }
2929 }
2930 break;
2931 case nir_var_shader_out:
2932 if (ctx->stage == MESA_SHADER_TESS_CTRL)
2933 return load_tcs_output(ctx, instr);
2934 for (unsigned chan = 0; chan < ve; chan++) {
2935 if (indir_index) {
2936 unsigned count = glsl_count_attribute_slots(
2937 instr->variables[0]->var->type, false);
2938 count -= chan / 4;
2939 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2940 &ctx->ac, ctx->outputs + idx + chan, count,
2941 4, true);
2942
2943 values[chan] = LLVMBuildExtractElement(ctx->builder,
2944 tmp_vec,
2945 indir_index, "");
2946 } else {
2947 values[chan] = LLVMBuildLoad(ctx->builder,
2948 ctx->outputs[idx + chan + const_index * 4],
2949 "");
2950 }
2951 }
2952 break;
2953 case nir_var_shared: {
2954 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2955 LLVMValueRef derived_ptr;
2956
2957 if (indir_index)
2958 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
2959
2960 for (unsigned chan = 0; chan < ve; chan++) {
2961 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2962 if (indir_index)
2963 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2964 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2965
2966 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2967 }
2968 break;
2969 }
2970 default:
2971 unreachable("unhandle variable mode");
2972 }
2973 ret = ac_build_gather_values(&ctx->ac, values, ve);
2974 return LLVMBuildBitCast(ctx->builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
2975 }
2976
2977 static void
2978 visit_store_var(struct nir_to_llvm_context *ctx,
2979 nir_intrinsic_instr *instr)
2980 {
2981 LLVMValueRef temp_ptr, value;
2982 int idx = instr->variables[0]->var->data.driver_location;
2983 LLVMValueRef src = to_float(&ctx->ac, get_src(ctx, instr->src[0]));
2984 int writemask = instr->const_index[0];
2985 LLVMValueRef indir_index;
2986 unsigned const_index;
2987 radv_get_deref_offset(ctx, instr->variables[0], false,
2988 NULL, NULL, &const_index, &indir_index);
2989
2990 if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
2991 int old_writemask = writemask;
2992
2993 src = LLVMBuildBitCast(ctx->builder, src,
2994 LLVMVectorType(ctx->f32, get_llvm_num_components(src) * 2),
2995 "");
2996
2997 writemask = 0;
2998 for (unsigned chan = 0; chan < 4; chan++) {
2999 if (old_writemask & (1 << chan))
3000 writemask |= 3u << (2 * chan);
3001 }
3002 }
3003
3004 switch (instr->variables[0]->var->data.mode) {
3005 case nir_var_shader_out:
3006
3007 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3008 store_tcs_output(ctx, instr, src, writemask);
3009 return;
3010 }
3011
3012 for (unsigned chan = 0; chan < 8; chan++) {
3013 int stride = 4;
3014 if (!(writemask & (1 << chan)))
3015 continue;
3016
3017 value = llvm_extract_elem(ctx, src, chan);
3018
3019 if (instr->variables[0]->var->data.compact)
3020 stride = 1;
3021 if (indir_index) {
3022 unsigned count = glsl_count_attribute_slots(
3023 instr->variables[0]->var->type, false);
3024 count -= chan / 4;
3025 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3026 &ctx->ac, ctx->outputs + idx + chan, count,
3027 stride, true);
3028
3029 if (get_llvm_num_components(tmp_vec) > 1) {
3030 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3031 value, indir_index, "");
3032 } else
3033 tmp_vec = value;
3034 build_store_values_extended(ctx, ctx->outputs + idx + chan,
3035 count, stride, tmp_vec);
3036
3037 } else {
3038 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
3039
3040 LLVMBuildStore(ctx->builder, value, temp_ptr);
3041 }
3042 }
3043 break;
3044 case nir_var_local:
3045 for (unsigned chan = 0; chan < 8; chan++) {
3046 if (!(writemask & (1 << chan)))
3047 continue;
3048
3049 value = llvm_extract_elem(ctx, src, chan);
3050 if (indir_index) {
3051 unsigned count = glsl_count_attribute_slots(
3052 instr->variables[0]->var->type, false);
3053 count -= chan / 4;
3054 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3055 &ctx->ac, ctx->locals + idx + chan, count,
3056 4, true);
3057
3058 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
3059 value, indir_index, "");
3060 build_store_values_extended(ctx, ctx->locals + idx + chan,
3061 count, 4, tmp_vec);
3062 } else {
3063 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3064
3065 LLVMBuildStore(ctx->builder, value, temp_ptr);
3066 }
3067 }
3068 break;
3069 case nir_var_shared: {
3070 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3071
3072 if (indir_index)
3073 indir_index = LLVMBuildMul(ctx->builder, indir_index, LLVMConstInt(ctx->i32, 4, false), "");
3074
3075 for (unsigned chan = 0; chan < 8; chan++) {
3076 if (!(writemask & (1 << chan)))
3077 continue;
3078 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
3079 LLVMValueRef derived_ptr;
3080
3081 if (indir_index)
3082 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
3083
3084 value = llvm_extract_elem(ctx, src, chan);
3085 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
3086 LLVMBuildStore(ctx->builder,
3087 to_integer(&ctx->ac, value), derived_ptr);
3088 }
3089 break;
3090 }
3091 default:
3092 break;
3093 }
3094 }
3095
3096 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3097 {
3098 switch (dim) {
3099 case GLSL_SAMPLER_DIM_BUF:
3100 return 1;
3101 case GLSL_SAMPLER_DIM_1D:
3102 return array ? 2 : 1;
3103 case GLSL_SAMPLER_DIM_2D:
3104 return array ? 3 : 2;
3105 case GLSL_SAMPLER_DIM_MS:
3106 return array ? 4 : 3;
3107 case GLSL_SAMPLER_DIM_3D:
3108 case GLSL_SAMPLER_DIM_CUBE:
3109 return 3;
3110 case GLSL_SAMPLER_DIM_RECT:
3111 case GLSL_SAMPLER_DIM_SUBPASS:
3112 return 2;
3113 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3114 return 3;
3115 default:
3116 break;
3117 }
3118 return 0;
3119 }
3120
3121
3122
3123 /* Adjust the sample index according to FMASK.
3124 *
3125 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3126 * which is the identity mapping. Each nibble says which physical sample
3127 * should be fetched to get that sample.
3128 *
3129 * For example, 0x11111100 means there are only 2 samples stored and
3130 * the second sample covers 3/4 of the pixel. When reading samples 0
3131 * and 1, return physical sample 0 (determined by the first two 0s
3132 * in FMASK), otherwise return physical sample 1.
3133 *
3134 * The sample index should be adjusted as follows:
3135 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3136 */
3137 static LLVMValueRef adjust_sample_index_using_fmask(struct nir_to_llvm_context *ctx,
3138 LLVMValueRef coord_x, LLVMValueRef coord_y,
3139 LLVMValueRef coord_z,
3140 LLVMValueRef sample_index,
3141 LLVMValueRef fmask_desc_ptr)
3142 {
3143 LLVMValueRef fmask_load_address[4];
3144 LLVMValueRef res;
3145
3146 fmask_load_address[0] = coord_x;
3147 fmask_load_address[1] = coord_y;
3148 if (coord_z) {
3149 fmask_load_address[2] = coord_z;
3150 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3151 }
3152
3153 struct ac_image_args args = {0};
3154
3155 args.opcode = ac_image_load;
3156 args.da = coord_z ? true : false;
3157 args.resource = fmask_desc_ptr;
3158 args.dmask = 0xf;
3159 args.addr = ac_build_gather_values(&ctx->ac, fmask_load_address, coord_z ? 4 : 2);
3160
3161 res = ac_build_image_opcode(&ctx->ac, &args);
3162
3163 res = to_integer(&ctx->ac, res);
3164 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3165 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3166
3167 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3168 res,
3169 ctx->i32zero, "");
3170
3171 LLVMValueRef sample_index4 =
3172 LLVMBuildMul(ctx->builder, sample_index, four, "");
3173 LLVMValueRef shifted_fmask =
3174 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3175 LLVMValueRef final_sample =
3176 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3177
3178 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3179 * resource descriptor is 0 (invalid),
3180 */
3181 LLVMValueRef fmask_desc =
3182 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3183 ctx->v8i32, "");
3184
3185 LLVMValueRef fmask_word1 =
3186 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3187 ctx->i32one, "");
3188
3189 LLVMValueRef word1_is_nonzero =
3190 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3191 fmask_word1, ctx->i32zero, "");
3192
3193 /* Replace the MSAA sample index. */
3194 sample_index =
3195 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3196 final_sample, sample_index, "");
3197 return sample_index;
3198 }
3199
3200 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
3201 const nir_intrinsic_instr *instr)
3202 {
3203 const struct glsl_type *type = instr->variables[0]->var->type;
3204 if(instr->variables[0]->deref.child)
3205 type = instr->variables[0]->deref.child->type;
3206
3207 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3208 LLVMValueRef coords[4];
3209 LLVMValueRef masks[] = {
3210 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
3211 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
3212 };
3213 LLVMValueRef res;
3214 LLVMValueRef sample_index = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
3215
3216 int count;
3217 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3218 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3219 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3220 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3221 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3222
3223 count = image_type_to_components_count(dim,
3224 glsl_sampler_type_is_array(type));
3225
3226 if (is_ms) {
3227 LLVMValueRef fmask_load_address[3];
3228 int chan;
3229
3230 fmask_load_address[0] = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3231 fmask_load_address[1] = LLVMBuildExtractElement(ctx->builder, src0, masks[1], "");
3232 if (glsl_sampler_type_is_array(type))
3233 fmask_load_address[2] = LLVMBuildExtractElement(ctx->builder, src0, masks[2], "");
3234 else
3235 fmask_load_address[2] = NULL;
3236 if (add_frag_pos) {
3237 for (chan = 0; chan < 2; ++chan)
3238 fmask_load_address[chan] = LLVMBuildAdd(ctx->builder, fmask_load_address[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3239 }
3240 sample_index = adjust_sample_index_using_fmask(ctx,
3241 fmask_load_address[0],
3242 fmask_load_address[1],
3243 fmask_load_address[2],
3244 sample_index,
3245 get_sampler_desc(ctx, instr->variables[0], DESC_FMASK));
3246 }
3247 if (count == 1) {
3248 if (instr->src[0].ssa->num_components)
3249 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
3250 else
3251 res = src0;
3252 } else {
3253 int chan;
3254 if (is_ms)
3255 count--;
3256 for (chan = 0; chan < count; ++chan) {
3257 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
3258 }
3259
3260 if (add_frag_pos) {
3261 for (chan = 0; chan < count; ++chan)
3262 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
3263 }
3264 if (is_ms) {
3265 coords[count] = sample_index;
3266 count++;
3267 }
3268
3269 if (count == 3) {
3270 coords[3] = LLVMGetUndef(ctx->i32);
3271 count = 4;
3272 }
3273 res = ac_build_gather_values(&ctx->ac, coords, count);
3274 }
3275 return res;
3276 }
3277
3278 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
3279 const nir_intrinsic_instr *instr)
3280 {
3281 LLVMValueRef params[7];
3282 LLVMValueRef res;
3283 char intrinsic_name[64];
3284 const nir_variable *var = instr->variables[0]->var;
3285 const struct glsl_type *type = var->type;
3286 if(instr->variables[0]->deref.child)
3287 type = instr->variables[0]->deref.child->type;
3288
3289 type = glsl_without_array(type);
3290 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3291 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3292 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3293 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3294 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3295 params[3] = ctx->i1false; /* glc */
3296 params[4] = ctx->i1false; /* slc */
3297 res = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
3298 params, 5, 0);
3299
3300 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
3301 res = to_integer(&ctx->ac, res);
3302 } else {
3303 bool is_da = glsl_sampler_type_is_array(type) ||
3304 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3305 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3306 LLVMValueRef glc = ctx->i1false;
3307 LLVMValueRef slc = ctx->i1false;
3308
3309 params[0] = get_image_coords(ctx, instr);
3310 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3311 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3312 if (HAVE_LLVM <= 0x0309) {
3313 params[3] = ctx->i1false; /* r128 */
3314 params[4] = da;
3315 params[5] = glc;
3316 params[6] = slc;
3317 } else {
3318 LLVMValueRef lwe = ctx->i1false;
3319 params[3] = glc;
3320 params[4] = slc;
3321 params[5] = lwe;
3322 params[6] = da;
3323 }
3324
3325 ac_get_image_intr_name("llvm.amdgcn.image.load",
3326 ctx->v4f32, /* vdata */
3327 LLVMTypeOf(params[0]), /* coords */
3328 LLVMTypeOf(params[1]), /* rsrc */
3329 intrinsic_name, sizeof(intrinsic_name));
3330
3331 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
3332 params, 7, AC_FUNC_ATTR_READONLY);
3333 }
3334 return to_integer(&ctx->ac, res);
3335 }
3336
3337 static void visit_image_store(struct nir_to_llvm_context *ctx,
3338 nir_intrinsic_instr *instr)
3339 {
3340 LLVMValueRef params[8];
3341 char intrinsic_name[64];
3342 const nir_variable *var = instr->variables[0]->var;
3343 const struct glsl_type *type = glsl_without_array(var->type);
3344
3345 if (ctx->stage == MESA_SHADER_FRAGMENT)
3346 ctx->shader_info->fs.writes_memory = true;
3347
3348 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3349 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3350 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3351 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3352 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3353 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
3354 params[4] = ctx->i1false; /* glc */
3355 params[5] = ctx->i1false; /* slc */
3356 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
3357 params, 6, 0);
3358 } else {
3359 bool is_da = glsl_sampler_type_is_array(type) ||
3360 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3361 LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
3362 LLVMValueRef glc = ctx->i1false;
3363 LLVMValueRef slc = ctx->i1false;
3364
3365 params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3366 params[1] = get_image_coords(ctx, instr); /* coords */
3367 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3368 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
3369 if (HAVE_LLVM <= 0x0309) {
3370 params[4] = ctx->i1false; /* r128 */
3371 params[5] = da;
3372 params[6] = glc;
3373 params[7] = slc;
3374 } else {
3375 LLVMValueRef lwe = ctx->i1false;
3376 params[4] = glc;
3377 params[5] = slc;
3378 params[6] = lwe;
3379 params[7] = da;
3380 }
3381
3382 ac_get_image_intr_name("llvm.amdgcn.image.store",
3383 LLVMTypeOf(params[0]), /* vdata */
3384 LLVMTypeOf(params[1]), /* coords */
3385 LLVMTypeOf(params[2]), /* rsrc */
3386 intrinsic_name, sizeof(intrinsic_name));
3387
3388 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
3389 params, 8, 0);
3390 }
3391
3392 }
3393
3394 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
3395 const nir_intrinsic_instr *instr)
3396 {
3397 LLVMValueRef params[6];
3398 int param_count = 0;
3399 const nir_variable *var = instr->variables[0]->var;
3400
3401 const char *atomic_name;
3402 char intrinsic_name[41];
3403 const struct glsl_type *type = glsl_without_array(var->type);
3404 MAYBE_UNUSED int length;
3405
3406 if (ctx->stage == MESA_SHADER_FRAGMENT)
3407 ctx->shader_info->fs.writes_memory = true;
3408
3409 switch (instr->intrinsic) {
3410 case nir_intrinsic_image_atomic_add:
3411 atomic_name = "add";
3412 break;
3413 case nir_intrinsic_image_atomic_min:
3414 atomic_name = "smin";
3415 break;
3416 case nir_intrinsic_image_atomic_max:
3417 atomic_name = "smax";
3418 break;
3419 case nir_intrinsic_image_atomic_and:
3420 atomic_name = "and";
3421 break;
3422 case nir_intrinsic_image_atomic_or:
3423 atomic_name = "or";
3424 break;
3425 case nir_intrinsic_image_atomic_xor:
3426 atomic_name = "xor";
3427 break;
3428 case nir_intrinsic_image_atomic_exchange:
3429 atomic_name = "swap";
3430 break;
3431 case nir_intrinsic_image_atomic_comp_swap:
3432 atomic_name = "cmpswap";
3433 break;
3434 default:
3435 abort();
3436 }
3437
3438 params[param_count++] = get_src(ctx, instr->src[2]);
3439 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3440 params[param_count++] = get_src(ctx, instr->src[3]);
3441
3442 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3443 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
3444 params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
3445 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
3446 params[param_count++] = ctx->i32zero; /* voffset */
3447 params[param_count++] = ctx->i1false; /* slc */
3448
3449 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3450 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3451 } else {
3452 char coords_type[8];
3453
3454 bool da = glsl_sampler_type_is_array(type) ||
3455 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3456
3457 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3458 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3459 params[param_count++] = ctx->i1false; /* r128 */
3460 params[param_count++] = da ? ctx->i1true : ctx->i1false; /* da */
3461 params[param_count++] = ctx->i1false; /* slc */
3462
3463 build_int_type_name(LLVMTypeOf(coords),
3464 coords_type, sizeof(coords_type));
3465
3466 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3467 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3468 }
3469
3470 assert(length < sizeof(intrinsic_name));
3471 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
3472 }
3473
3474 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
3475 const nir_intrinsic_instr *instr)
3476 {
3477 LLVMValueRef res;
3478 const nir_variable *var = instr->variables[0]->var;
3479 const struct glsl_type *type = instr->variables[0]->var->type;
3480 bool da = glsl_sampler_type_is_array(var->type) ||
3481 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
3482 if(instr->variables[0]->deref.child)
3483 type = instr->variables[0]->deref.child->type;
3484
3485 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3486 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
3487
3488 struct ac_image_args args = { 0 };
3489
3490 args.da = da;
3491 args.dmask = 0xf;
3492 args.resource = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
3493 args.opcode = ac_image_get_resinfo;
3494 args.addr = ctx->i32zero;
3495
3496 res = ac_build_image_opcode(&ctx->ac, &args);
3497
3498 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3499 glsl_sampler_type_is_array(type)) {
3500 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3501 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3502 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
3503 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3504 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
3505 }
3506 return res;
3507 }
3508
3509 #define NOOP_WAITCNT 0xf7f
3510 #define LGKM_CNT 0x07f
3511 #define VM_CNT 0xf70
3512
3513 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
3514 unsigned simm16)
3515 {
3516 LLVMValueRef args[1] = {
3517 LLVMConstInt(ctx->i32, simm16, false),
3518 };
3519 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
3520 ctx->voidt, args, 1, 0);
3521 }
3522
3523 static void emit_barrier(struct nir_to_llvm_context *ctx)
3524 {
3525 /* SI only (thanks to a hw bug workaround):
3526 * The real barrier instruction isn’t needed, because an entire patch
3527 * always fits into a single wave.
3528 */
3529 if (ctx->options->chip_class == SI &&
3530 ctx->stage == MESA_SHADER_TESS_CTRL) {
3531 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
3532 return;
3533 }
3534 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
3535 ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3536 }
3537
3538 static void emit_discard_if(struct nir_to_llvm_context *ctx,
3539 const nir_intrinsic_instr *instr)
3540 {
3541 LLVMValueRef cond;
3542 ctx->shader_info->fs.can_discard = true;
3543
3544 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
3545 get_src(ctx, instr->src[0]),
3546 ctx->i32zero, "");
3547
3548 cond = LLVMBuildSelect(ctx->builder, cond,
3549 LLVMConstReal(ctx->f32, -1.0f),
3550 ctx->f32zero, "");
3551 ac_build_kill(&ctx->ac, cond);
3552 }
3553
3554 static LLVMValueRef
3555 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
3556 {
3557 LLVMValueRef result;
3558 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3559 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
3560 LLVMConstInt(ctx->i32, 0xfc0, false), "");
3561
3562 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
3563 }
3564
3565 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
3566 const nir_intrinsic_instr *instr)
3567 {
3568 LLVMValueRef ptr, result;
3569 int idx = instr->variables[0]->var->data.driver_location;
3570 LLVMValueRef src = get_src(ctx, instr->src[0]);
3571 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
3572
3573 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
3574 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3575 result = LLVMBuildAtomicCmpXchg(ctx->builder,
3576 ptr, src, src1,
3577 LLVMAtomicOrderingSequentiallyConsistent,
3578 LLVMAtomicOrderingSequentiallyConsistent,
3579 false);
3580 } else {
3581 LLVMAtomicRMWBinOp op;
3582 switch (instr->intrinsic) {
3583 case nir_intrinsic_var_atomic_add:
3584 op = LLVMAtomicRMWBinOpAdd;
3585 break;
3586 case nir_intrinsic_var_atomic_umin:
3587 op = LLVMAtomicRMWBinOpUMin;
3588 break;
3589 case nir_intrinsic_var_atomic_umax:
3590 op = LLVMAtomicRMWBinOpUMax;
3591 break;
3592 case nir_intrinsic_var_atomic_imin:
3593 op = LLVMAtomicRMWBinOpMin;
3594 break;
3595 case nir_intrinsic_var_atomic_imax:
3596 op = LLVMAtomicRMWBinOpMax;
3597 break;
3598 case nir_intrinsic_var_atomic_and:
3599 op = LLVMAtomicRMWBinOpAnd;
3600 break;
3601 case nir_intrinsic_var_atomic_or:
3602 op = LLVMAtomicRMWBinOpOr;
3603 break;
3604 case nir_intrinsic_var_atomic_xor:
3605 op = LLVMAtomicRMWBinOpXor;
3606 break;
3607 case nir_intrinsic_var_atomic_exchange:
3608 op = LLVMAtomicRMWBinOpXchg;
3609 break;
3610 default:
3611 return NULL;
3612 }
3613
3614 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(&ctx->ac, src),
3615 LLVMAtomicOrderingSequentiallyConsistent,
3616 false);
3617 }
3618 return result;
3619 }
3620
3621 #define INTERP_CENTER 0
3622 #define INTERP_CENTROID 1
3623 #define INTERP_SAMPLE 2
3624
3625 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
3626 enum glsl_interp_mode interp, unsigned location)
3627 {
3628 switch (interp) {
3629 case INTERP_MODE_FLAT:
3630 default:
3631 return NULL;
3632 case INTERP_MODE_SMOOTH:
3633 case INTERP_MODE_NONE:
3634 if (location == INTERP_CENTER)
3635 return ctx->persp_center;
3636 else if (location == INTERP_CENTROID)
3637 return ctx->persp_centroid;
3638 else if (location == INTERP_SAMPLE)
3639 return ctx->persp_sample;
3640 break;
3641 case INTERP_MODE_NOPERSPECTIVE:
3642 if (location == INTERP_CENTER)
3643 return ctx->linear_center;
3644 else if (location == INTERP_CENTROID)
3645 return ctx->linear_centroid;
3646 else if (location == INTERP_SAMPLE)
3647 return ctx->linear_sample;
3648 break;
3649 }
3650 return NULL;
3651 }
3652
3653 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
3654 LLVMValueRef sample_id)
3655 {
3656 LLVMValueRef result;
3657 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_PS_SAMPLE_POSITIONS, false));
3658
3659 ptr = LLVMBuildBitCast(ctx->builder, ptr,
3660 const_array(ctx->v2f32, 64), "");
3661
3662 sample_id = LLVMBuildAdd(ctx->builder, sample_id, ctx->sample_pos_offset, "");
3663 result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
3664
3665 return result;
3666 }
3667
3668 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
3669 {
3670 LLVMValueRef values[2];
3671
3672 values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
3673 values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
3674 return ac_build_gather_values(&ctx->ac, values, 2);
3675 }
3676
3677 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
3678 const nir_intrinsic_instr *instr)
3679 {
3680 LLVMValueRef result[2];
3681 LLVMValueRef interp_param, attr_number;
3682 unsigned location;
3683 unsigned chan;
3684 LLVMValueRef src_c0, src_c1;
3685 LLVMValueRef src0;
3686 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
3687 switch (instr->intrinsic) {
3688 case nir_intrinsic_interp_var_at_centroid:
3689 location = INTERP_CENTROID;
3690 break;
3691 case nir_intrinsic_interp_var_at_sample:
3692 case nir_intrinsic_interp_var_at_offset:
3693 location = INTERP_CENTER;
3694 src0 = get_src(ctx, instr->src[0]);
3695 break;
3696 default:
3697 break;
3698 }
3699
3700 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
3701 src_c0 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
3702 src_c1 = to_float(&ctx->ac, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
3703 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
3704 LLVMValueRef sample_position;
3705 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3706
3707 /* fetch sample ID */
3708 sample_position = load_sample_position(ctx, src0);
3709
3710 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
3711 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
3712 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
3713 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
3714 }
3715 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
3716 attr_number = LLVMConstInt(ctx->i32, input_index, false);
3717
3718 if (location == INTERP_SAMPLE || location == INTERP_CENTER) {
3719 LLVMValueRef ij_out[2];
3720 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
3721
3722 /*
3723 * take the I then J parameters, and the DDX/Y for it, and
3724 * calculate the IJ inputs for the interpolator.
3725 * temp1 = ddx * offset/sample.x + I;
3726 * interp_param.I = ddy * offset/sample.y + temp1;
3727 * temp1 = ddx * offset/sample.x + J;
3728 * interp_param.J = ddy * offset/sample.y + temp1;
3729 */
3730 for (unsigned i = 0; i < 2; i++) {
3731 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
3732 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
3733 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
3734 ddxy_out, ix_ll, "");
3735 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
3736 ddxy_out, iy_ll, "");
3737 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
3738 interp_param, ix_ll, "");
3739 LLVMValueRef temp1, temp2;
3740
3741 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
3742 ctx->f32, "");
3743
3744 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
3745 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
3746
3747 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
3748 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
3749
3750 ij_out[i] = LLVMBuildBitCast(ctx->builder,
3751 temp2, ctx->i32, "");
3752 }
3753 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
3754
3755 }
3756
3757 for (chan = 0; chan < 2; chan++) {
3758 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3759
3760 if (interp_param) {
3761 interp_param = LLVMBuildBitCast(ctx->builder,
3762 interp_param, LLVMVectorType(ctx->f32, 2), "");
3763 LLVMValueRef i = LLVMBuildExtractElement(
3764 ctx->builder, interp_param, ctx->i32zero, "");
3765 LLVMValueRef j = LLVMBuildExtractElement(
3766 ctx->builder, interp_param, ctx->i32one, "");
3767
3768 result[chan] = ac_build_fs_interp(&ctx->ac,
3769 llvm_chan, attr_number,
3770 ctx->prim_mask, i, j);
3771 } else {
3772 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
3773 LLVMConstInt(ctx->i32, 2, false),
3774 llvm_chan, attr_number,
3775 ctx->prim_mask);
3776 }
3777 }
3778 return ac_build_gather_values(&ctx->ac, result, 2);
3779 }
3780
3781 static void
3782 visit_emit_vertex(struct nir_to_llvm_context *ctx,
3783 const nir_intrinsic_instr *instr)
3784 {
3785 LLVMValueRef gs_next_vertex;
3786 LLVMValueRef can_emit, kill;
3787 int idx;
3788
3789 assert(instr->const_index[0] == 0);
3790 /* Write vertex attribute values to GSVS ring */
3791 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3792 ctx->gs_next_vertex,
3793 "");
3794
3795 /* If this thread has already emitted the declared maximum number of
3796 * vertices, kill it: excessive vertex emissions are not supposed to
3797 * have any effect, and GS threads have no externally observable
3798 * effects other than emitting vertices.
3799 */
3800 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3801 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3802
3803 kill = LLVMBuildSelect(ctx->builder, can_emit,
3804 LLVMConstReal(ctx->f32, 1.0f),
3805 LLVMConstReal(ctx->f32, -1.0f), "");
3806 ac_build_kill(&ctx->ac, kill);
3807
3808 /* loop num outputs */
3809 idx = 0;
3810 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3811 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3812 int length = 4;
3813 int slot = idx;
3814 int slot_inc = 1;
3815
3816 if (!(ctx->output_mask & (1ull << i)))
3817 continue;
3818
3819 if (i == VARYING_SLOT_CLIP_DIST0) {
3820 /* pack clip and cull into a single set of slots */
3821 length = ctx->num_output_clips + ctx->num_output_culls;
3822 if (length > 4)
3823 slot_inc = 2;
3824 }
3825 for (unsigned j = 0; j < length; j++) {
3826 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3827 out_ptr[j], "");
3828 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
3829 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3830 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3831
3832 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3833
3834 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
3835 out_val, 1,
3836 voffset, ctx->gs2vs_offset, 0,
3837 1, 1, true, true);
3838 }
3839 idx += slot_inc;
3840 }
3841
3842 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3843 ctx->i32one, "");
3844 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3845
3846 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3847 }
3848
3849 static void
3850 visit_end_primitive(struct nir_to_llvm_context *ctx,
3851 const nir_intrinsic_instr *instr)
3852 {
3853 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
3854 }
3855
3856 static LLVMValueRef
3857 visit_load_tess_coord(struct nir_to_llvm_context *ctx,
3858 const nir_intrinsic_instr *instr)
3859 {
3860 LLVMValueRef coord[4] = {
3861 ctx->tes_u,
3862 ctx->tes_v,
3863 ctx->f32zero,
3864 ctx->f32zero,
3865 };
3866
3867 if (ctx->tes_primitive_mode == GL_TRIANGLES)
3868 coord[2] = LLVMBuildFSub(ctx->builder, ctx->f32one,
3869 LLVMBuildFAdd(ctx->builder, coord[0], coord[1], ""), "");
3870
3871 LLVMValueRef result = ac_build_gather_values(&ctx->ac, coord, instr->num_components);
3872 return LLVMBuildBitCast(ctx->builder, result,
3873 get_def_type(ctx, &instr->dest.ssa), "");
3874 }
3875
3876 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3877 nir_intrinsic_instr *instr)
3878 {
3879 LLVMValueRef result = NULL;
3880
3881 switch (instr->intrinsic) {
3882 case nir_intrinsic_load_work_group_id: {
3883 result = ctx->workgroup_ids;
3884 break;
3885 }
3886 case nir_intrinsic_load_base_vertex: {
3887 result = ctx->base_vertex;
3888 break;
3889 }
3890 case nir_intrinsic_load_vertex_id_zero_base: {
3891 result = ctx->vertex_id;
3892 break;
3893 }
3894 case nir_intrinsic_load_local_invocation_id: {
3895 result = ctx->local_invocation_ids;
3896 break;
3897 }
3898 case nir_intrinsic_load_base_instance:
3899 result = ctx->start_instance;
3900 break;
3901 case nir_intrinsic_load_draw_id:
3902 result = ctx->draw_index;
3903 break;
3904 case nir_intrinsic_load_invocation_id:
3905 if (ctx->stage == MESA_SHADER_TESS_CTRL)
3906 result = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
3907 else
3908 result = ctx->gs_invocation_id;
3909 break;
3910 case nir_intrinsic_load_primitive_id:
3911 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3912 ctx->shader_info->gs.uses_prim_id = true;
3913 result = ctx->gs_prim_id;
3914 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3915 ctx->shader_info->tcs.uses_prim_id = true;
3916 result = ctx->tcs_patch_id;
3917 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
3918 ctx->shader_info->tcs.uses_prim_id = true;
3919 result = ctx->tes_patch_id;
3920 } else
3921 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3922 break;
3923 case nir_intrinsic_load_sample_id:
3924 ctx->shader_info->fs.force_persample = true;
3925 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3926 break;
3927 case nir_intrinsic_load_sample_pos:
3928 ctx->shader_info->fs.force_persample = true;
3929 result = load_sample_pos(ctx);
3930 break;
3931 case nir_intrinsic_load_sample_mask_in:
3932 result = ctx->sample_coverage;
3933 break;
3934 case nir_intrinsic_load_front_face:
3935 result = ctx->front_face;
3936 break;
3937 case nir_intrinsic_load_instance_id:
3938 result = ctx->instance_id;
3939 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3940 ctx->shader_info->vs.vgpr_comp_cnt);
3941 break;
3942 case nir_intrinsic_load_num_work_groups:
3943 result = ctx->num_work_groups;
3944 break;
3945 case nir_intrinsic_load_local_invocation_index:
3946 result = visit_load_local_invocation_index(ctx);
3947 break;
3948 case nir_intrinsic_load_push_constant:
3949 result = visit_load_push_constant(ctx, instr);
3950 break;
3951 case nir_intrinsic_vulkan_resource_index:
3952 result = visit_vulkan_resource_index(ctx, instr);
3953 break;
3954 case nir_intrinsic_store_ssbo:
3955 visit_store_ssbo(ctx, instr);
3956 break;
3957 case nir_intrinsic_load_ssbo:
3958 result = visit_load_buffer(ctx, instr);
3959 break;
3960 case nir_intrinsic_ssbo_atomic_add:
3961 case nir_intrinsic_ssbo_atomic_imin:
3962 case nir_intrinsic_ssbo_atomic_umin:
3963 case nir_intrinsic_ssbo_atomic_imax:
3964 case nir_intrinsic_ssbo_atomic_umax:
3965 case nir_intrinsic_ssbo_atomic_and:
3966 case nir_intrinsic_ssbo_atomic_or:
3967 case nir_intrinsic_ssbo_atomic_xor:
3968 case nir_intrinsic_ssbo_atomic_exchange:
3969 case nir_intrinsic_ssbo_atomic_comp_swap:
3970 result = visit_atomic_ssbo(ctx, instr);
3971 break;
3972 case nir_intrinsic_load_ubo:
3973 result = visit_load_ubo_buffer(ctx, instr);
3974 break;
3975 case nir_intrinsic_get_buffer_size:
3976 result = visit_get_buffer_size(ctx, instr);
3977 break;
3978 case nir_intrinsic_load_var:
3979 result = visit_load_var(ctx, instr);
3980 break;
3981 case nir_intrinsic_store_var:
3982 visit_store_var(ctx, instr);
3983 break;
3984 case nir_intrinsic_image_load:
3985 result = visit_image_load(ctx, instr);
3986 break;
3987 case nir_intrinsic_image_store:
3988 visit_image_store(ctx, instr);
3989 break;
3990 case nir_intrinsic_image_atomic_add:
3991 case nir_intrinsic_image_atomic_min:
3992 case nir_intrinsic_image_atomic_max:
3993 case nir_intrinsic_image_atomic_and:
3994 case nir_intrinsic_image_atomic_or:
3995 case nir_intrinsic_image_atomic_xor:
3996 case nir_intrinsic_image_atomic_exchange:
3997 case nir_intrinsic_image_atomic_comp_swap:
3998 result = visit_image_atomic(ctx, instr);
3999 break;
4000 case nir_intrinsic_image_size:
4001 result = visit_image_size(ctx, instr);
4002 break;
4003 case nir_intrinsic_discard:
4004 ctx->shader_info->fs.can_discard = true;
4005 ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
4006 ctx->voidt,
4007 NULL, 0, AC_FUNC_ATTR_LEGACY);
4008 break;
4009 case nir_intrinsic_discard_if:
4010 emit_discard_if(ctx, instr);
4011 break;
4012 case nir_intrinsic_memory_barrier:
4013 emit_waitcnt(ctx, VM_CNT);
4014 break;
4015 case nir_intrinsic_barrier:
4016 emit_barrier(ctx);
4017 break;
4018 case nir_intrinsic_var_atomic_add:
4019 case nir_intrinsic_var_atomic_imin:
4020 case nir_intrinsic_var_atomic_umin:
4021 case nir_intrinsic_var_atomic_imax:
4022 case nir_intrinsic_var_atomic_umax:
4023 case nir_intrinsic_var_atomic_and:
4024 case nir_intrinsic_var_atomic_or:
4025 case nir_intrinsic_var_atomic_xor:
4026 case nir_intrinsic_var_atomic_exchange:
4027 case nir_intrinsic_var_atomic_comp_swap:
4028 result = visit_var_atomic(ctx, instr);
4029 break;
4030 case nir_intrinsic_interp_var_at_centroid:
4031 case nir_intrinsic_interp_var_at_sample:
4032 case nir_intrinsic_interp_var_at_offset:
4033 result = visit_interp(ctx, instr);
4034 break;
4035 case nir_intrinsic_emit_vertex:
4036 visit_emit_vertex(ctx, instr);
4037 break;
4038 case nir_intrinsic_end_primitive:
4039 visit_end_primitive(ctx, instr);
4040 break;
4041 case nir_intrinsic_load_tess_coord:
4042 result = visit_load_tess_coord(ctx, instr);
4043 break;
4044 case nir_intrinsic_load_patch_vertices_in:
4045 result = LLVMConstInt(ctx->i32, ctx->options->key.tcs.input_vertices, false);
4046 break;
4047 default:
4048 fprintf(stderr, "Unknown intrinsic: ");
4049 nir_print_instr(&instr->instr, stderr);
4050 fprintf(stderr, "\n");
4051 break;
4052 }
4053 if (result) {
4054 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4055 }
4056 }
4057
4058 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
4059 const nir_deref_var *deref,
4060 enum desc_type desc_type)
4061 {
4062 unsigned desc_set = deref->var->data.descriptor_set;
4063 LLVMValueRef list = ctx->descriptor_sets[desc_set];
4064 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4065 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
4066 unsigned offset = binding->offset;
4067 unsigned stride = binding->size;
4068 unsigned type_size;
4069 LLVMBuilderRef builder = ctx->builder;
4070 LLVMTypeRef type;
4071 LLVMValueRef index = NULL;
4072 unsigned constant_index = 0;
4073
4074 assert(deref->var->data.binding < layout->binding_count);
4075
4076 switch (desc_type) {
4077 case DESC_IMAGE:
4078 type = ctx->v8i32;
4079 type_size = 32;
4080 break;
4081 case DESC_FMASK:
4082 type = ctx->v8i32;
4083 offset += 32;
4084 type_size = 32;
4085 break;
4086 case DESC_SAMPLER:
4087 type = ctx->v4i32;
4088 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4089 offset += 64;
4090
4091 type_size = 16;
4092 break;
4093 case DESC_BUFFER:
4094 type = ctx->v4i32;
4095 type_size = 16;
4096 break;
4097 default:
4098 unreachable("invalid desc_type\n");
4099 }
4100
4101 if (deref->deref.child) {
4102 const nir_deref_array *child =
4103 (const nir_deref_array *)deref->deref.child;
4104
4105 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4106 offset += child->base_offset * stride;
4107 if (child->deref_array_type == nir_deref_array_type_indirect) {
4108 index = get_src(ctx, child->indirect);
4109 }
4110
4111 constant_index = child->base_offset;
4112 }
4113 if (desc_type == DESC_SAMPLER && binding->immutable_samplers_offset &&
4114 (!index || binding->immutable_samplers_equal)) {
4115 if (binding->immutable_samplers_equal)
4116 constant_index = 0;
4117
4118 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4119
4120 LLVMValueRef constants[] = {
4121 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 0], 0),
4122 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 1], 0),
4123 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 2], 0),
4124 LLVMConstInt(ctx->i32, samplers[constant_index * 4 + 3], 0),
4125 };
4126 return ac_build_gather_values(&ctx->ac, constants, 4);
4127 }
4128
4129 assert(stride % type_size == 0);
4130
4131 if (!index)
4132 index = ctx->i32zero;
4133
4134 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
4135
4136 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->i32, offset, 0));
4137 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
4138
4139 return ac_build_indexed_load_const(&ctx->ac, list, index);
4140 }
4141
4142 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
4143 struct ac_image_args *args,
4144 const nir_tex_instr *instr,
4145 nir_texop op,
4146 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4147 LLVMValueRef *param, unsigned count,
4148 unsigned dmask)
4149 {
4150 unsigned is_rect = 0;
4151 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4152
4153 if (op == nir_texop_lod)
4154 da = false;
4155 /* Pad to power of two vector */
4156 while (count < util_next_power_of_two(count))
4157 param[count++] = LLVMGetUndef(ctx->i32);
4158
4159 if (count > 1)
4160 args->addr = ac_build_gather_values(&ctx->ac, param, count);
4161 else
4162 args->addr = param[0];
4163
4164 args->resource = res_ptr;
4165 args->sampler = samp_ptr;
4166
4167 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4168 args->addr = param[0];
4169 return;
4170 }
4171
4172 args->dmask = dmask;
4173 args->unorm = is_rect;
4174 args->da = da;
4175 }
4176
4177 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4178 *
4179 * SI-CI:
4180 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4181 * filtering manually. The driver sets img7 to a mask clearing
4182 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4183 * s_and_b32 samp0, samp0, img7
4184 *
4185 * VI:
4186 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4187 */
4188 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
4189 LLVMValueRef res, LLVMValueRef samp)
4190 {
4191 LLVMBuilderRef builder = ctx->builder;
4192 LLVMValueRef img7, samp0;
4193
4194 if (ctx->options->chip_class >= VI)
4195 return samp;
4196
4197 img7 = LLVMBuildExtractElement(builder, res,
4198 LLVMConstInt(ctx->i32, 7, 0), "");
4199 samp0 = LLVMBuildExtractElement(builder, samp,
4200 LLVMConstInt(ctx->i32, 0, 0), "");
4201 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4202 return LLVMBuildInsertElement(builder, samp, samp0,
4203 LLVMConstInt(ctx->i32, 0, 0), "");
4204 }
4205
4206 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
4207 nir_tex_instr *instr,
4208 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4209 LLVMValueRef *fmask_ptr)
4210 {
4211 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4212 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
4213 else
4214 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
4215 if (samp_ptr) {
4216 if (instr->sampler)
4217 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
4218 else
4219 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
4220 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4221 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4222 }
4223 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4224 instr->op == nir_texop_samples_identical))
4225 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
4226 }
4227
4228 static LLVMValueRef apply_round_slice(struct nir_to_llvm_context *ctx,
4229 LLVMValueRef coord)
4230 {
4231 coord = to_float(&ctx->ac, coord);
4232 coord = ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4233 coord = to_integer(&ctx->ac, coord);
4234 return coord;
4235 }
4236
4237 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
4238 {
4239 LLVMValueRef result = NULL;
4240 struct ac_image_args args = { 0 };
4241 unsigned dmask = 0xf;
4242 LLVMValueRef address[16];
4243 LLVMValueRef coords[5];
4244 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4245 LLVMValueRef bias = NULL, offsets = NULL;
4246 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4247 LLVMValueRef ddx = NULL, ddy = NULL;
4248 LLVMValueRef derivs[6];
4249 unsigned chan, count = 0;
4250 unsigned const_src = 0, num_deriv_comp = 0;
4251 bool lod_is_zero = false;
4252 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4253
4254 for (unsigned i = 0; i < instr->num_srcs; i++) {
4255 switch (instr->src[i].src_type) {
4256 case nir_tex_src_coord:
4257 coord = get_src(ctx, instr->src[i].src);
4258 break;
4259 case nir_tex_src_projector:
4260 break;
4261 case nir_tex_src_comparator:
4262 comparator = get_src(ctx, instr->src[i].src);
4263 break;
4264 case nir_tex_src_offset:
4265 offsets = get_src(ctx, instr->src[i].src);
4266 const_src = i;
4267 break;
4268 case nir_tex_src_bias:
4269 bias = get_src(ctx, instr->src[i].src);
4270 break;
4271 case nir_tex_src_lod: {
4272 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4273
4274 if (val && val->i32[0] == 0)
4275 lod_is_zero = true;
4276 lod = get_src(ctx, instr->src[i].src);
4277 break;
4278 }
4279 case nir_tex_src_ms_index:
4280 sample_index = get_src(ctx, instr->src[i].src);
4281 break;
4282 case nir_tex_src_ms_mcs:
4283 break;
4284 case nir_tex_src_ddx:
4285 ddx = get_src(ctx, instr->src[i].src);
4286 num_deriv_comp = instr->src[i].src.ssa->num_components;
4287 break;
4288 case nir_tex_src_ddy:
4289 ddy = get_src(ctx, instr->src[i].src);
4290 break;
4291 case nir_tex_src_texture_offset:
4292 case nir_tex_src_sampler_offset:
4293 case nir_tex_src_plane:
4294 default:
4295 break;
4296 }
4297 }
4298
4299 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4300 result = get_buffer_size(ctx, res_ptr, true);
4301 goto write_result;
4302 }
4303
4304 if (instr->op == nir_texop_texture_samples) {
4305 LLVMValueRef res, samples, is_msaa;
4306 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
4307 samples = LLVMBuildExtractElement(ctx->builder, res,
4308 LLVMConstInt(ctx->i32, 3, false), "");
4309 is_msaa = LLVMBuildLShr(ctx->builder, samples,
4310 LLVMConstInt(ctx->i32, 28, false), "");
4311 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
4312 LLVMConstInt(ctx->i32, 0xe, false), "");
4313 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
4314 LLVMConstInt(ctx->i32, 0xe, false), "");
4315
4316 samples = LLVMBuildLShr(ctx->builder, samples,
4317 LLVMConstInt(ctx->i32, 16, false), "");
4318 samples = LLVMBuildAnd(ctx->builder, samples,
4319 LLVMConstInt(ctx->i32, 0xf, false), "");
4320 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
4321 samples, "");
4322 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
4323 ctx->i32one, "");
4324 result = samples;
4325 goto write_result;
4326 }
4327
4328 if (coord)
4329 for (chan = 0; chan < instr->coord_components; chan++)
4330 coords[chan] = llvm_extract_elem(ctx, coord, chan);
4331
4332 if (offsets && instr->op != nir_texop_txf) {
4333 LLVMValueRef offset[3], pack;
4334 for (chan = 0; chan < 3; ++chan)
4335 offset[chan] = ctx->i32zero;
4336
4337 args.offset = true;
4338 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
4339 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
4340 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
4341 LLVMConstInt(ctx->i32, 0x3f, false), "");
4342 if (chan)
4343 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
4344 LLVMConstInt(ctx->i32, chan * 8, false), "");
4345 }
4346 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
4347 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
4348 address[count++] = pack;
4349
4350 }
4351 /* pack LOD bias value */
4352 if (instr->op == nir_texop_txb && bias) {
4353 address[count++] = bias;
4354 }
4355
4356 /* Pack depth comparison value */
4357 if (instr->is_shadow && comparator) {
4358 address[count++] = llvm_extract_elem(ctx, comparator, 0);
4359 }
4360
4361 /* pack derivatives */
4362 if (ddx || ddy) {
4363 switch (instr->sampler_dim) {
4364 case GLSL_SAMPLER_DIM_3D:
4365 case GLSL_SAMPLER_DIM_CUBE:
4366 num_deriv_comp = 3;
4367 break;
4368 case GLSL_SAMPLER_DIM_2D:
4369 default:
4370 num_deriv_comp = 2;
4371 break;
4372 case GLSL_SAMPLER_DIM_1D:
4373 num_deriv_comp = 1;
4374 break;
4375 }
4376
4377 for (unsigned i = 0; i < num_deriv_comp; i++) {
4378 derivs[i] = to_float(&ctx->ac, llvm_extract_elem(ctx, ddx, i));
4379 derivs[num_deriv_comp + i] = to_float(&ctx->ac, llvm_extract_elem(ctx, ddy, i));
4380 }
4381 }
4382
4383 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
4384 if (instr->is_array && instr->op != nir_texop_lod)
4385 coords[3] = apply_round_slice(ctx, coords[3]);
4386 for (chan = 0; chan < instr->coord_components; chan++)
4387 coords[chan] = to_float(&ctx->ac, coords[chan]);
4388 if (instr->coord_components == 3)
4389 coords[3] = LLVMGetUndef(ctx->f32);
4390 ac_prepare_cube_coords(&ctx->ac,
4391 instr->op == nir_texop_txd, instr->is_array,
4392 coords, derivs);
4393 if (num_deriv_comp)
4394 num_deriv_comp--;
4395 }
4396
4397 if (ddx || ddy) {
4398 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
4399 address[count++] = derivs[i];
4400 }
4401
4402 /* Pack texture coordinates */
4403 if (coord) {
4404 address[count++] = coords[0];
4405 if (instr->coord_components > 1) {
4406 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
4407 coords[1] = apply_round_slice(ctx, coords[1]);
4408 }
4409 address[count++] = coords[1];
4410 }
4411 if (instr->coord_components > 2) {
4412 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
4413 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
4414 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
4415 instr->op != nir_texop_txf) {
4416 coords[2] = apply_round_slice(ctx, coords[2]);
4417 }
4418 address[count++] = coords[2];
4419 }
4420 }
4421
4422 /* Pack LOD */
4423 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
4424 instr->op == nir_texop_txf)) {
4425 address[count++] = lod;
4426 } else if (instr->op == nir_texop_txf_ms && sample_index) {
4427 address[count++] = sample_index;
4428 } else if(instr->op == nir_texop_txs) {
4429 count = 0;
4430 if (lod)
4431 address[count++] = lod;
4432 else
4433 address[count++] = ctx->i32zero;
4434 }
4435
4436 for (chan = 0; chan < count; chan++) {
4437 address[chan] = LLVMBuildBitCast(ctx->builder,
4438 address[chan], ctx->i32, "");
4439 }
4440
4441 if (instr->op == nir_texop_samples_identical) {
4442 LLVMValueRef txf_address[4];
4443 struct ac_image_args txf_args = { 0 };
4444 unsigned txf_count = count;
4445 memcpy(txf_address, address, sizeof(txf_address));
4446
4447 if (!instr->is_array)
4448 txf_address[2] = ctx->i32zero;
4449 txf_address[3] = ctx->i32zero;
4450
4451 set_tex_fetch_args(ctx, &txf_args, instr, nir_texop_txf,
4452 fmask_ptr, NULL,
4453 txf_address, txf_count, 0xf);
4454
4455 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
4456
4457 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4458 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->i32zero);
4459 goto write_result;
4460 }
4461
4462 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
4463 instr->op != nir_texop_txs) {
4464 unsigned sample_chan = instr->is_array ? 3 : 2;
4465 address[sample_chan] = adjust_sample_index_using_fmask(ctx,
4466 address[0],
4467 address[1],
4468 instr->is_array ? address[2] : NULL,
4469 address[sample_chan],
4470 fmask_ptr);
4471 }
4472
4473 if (offsets && instr->op == nir_texop_txf) {
4474 nir_const_value *const_offset =
4475 nir_src_as_const_value(instr->src[const_src].src);
4476 int num_offsets = instr->src[const_src].src.ssa->num_components;
4477 assert(const_offset);
4478 num_offsets = MIN2(num_offsets, instr->coord_components);
4479 if (num_offsets > 2)
4480 address[2] = LLVMBuildAdd(ctx->builder,
4481 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
4482 if (num_offsets > 1)
4483 address[1] = LLVMBuildAdd(ctx->builder,
4484 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
4485 address[0] = LLVMBuildAdd(ctx->builder,
4486 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
4487
4488 }
4489
4490 /* TODO TG4 support */
4491 if (instr->op == nir_texop_tg4) {
4492 if (instr->is_shadow)
4493 dmask = 1;
4494 else
4495 dmask = 1 << instr->component;
4496 }
4497 set_tex_fetch_args(ctx, &args, instr, instr->op,
4498 res_ptr, samp_ptr, address, count, dmask);
4499
4500 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
4501
4502 if (instr->op == nir_texop_query_levels)
4503 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
4504 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
4505 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
4506 else if (instr->op == nir_texop_txs &&
4507 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
4508 instr->is_array) {
4509 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
4510 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
4511 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
4512 z = LLVMBuildSDiv(ctx->builder, z, six, "");
4513 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
4514 } else if (instr->dest.ssa.num_components != 4)
4515 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
4516
4517 write_result:
4518 if (result) {
4519 assert(instr->dest.is_ssa);
4520 result = to_integer(&ctx->ac, result);
4521 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4522 }
4523 }
4524
4525
4526 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
4527 {
4528 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
4529 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
4530
4531 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4532 _mesa_hash_table_insert(ctx->phis, instr, result);
4533 }
4534
4535 static void visit_post_phi(struct nir_to_llvm_context *ctx,
4536 nir_phi_instr *instr,
4537 LLVMValueRef llvm_phi)
4538 {
4539 nir_foreach_phi_src(src, instr) {
4540 LLVMBasicBlockRef block = get_block(ctx, src->pred);
4541 LLVMValueRef llvm_src = get_src(ctx, src->src);
4542
4543 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
4544 }
4545 }
4546
4547 static void phi_post_pass(struct nir_to_llvm_context *ctx)
4548 {
4549 struct hash_entry *entry;
4550 hash_table_foreach(ctx->phis, entry) {
4551 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
4552 (LLVMValueRef)entry->data);
4553 }
4554 }
4555
4556
4557 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
4558 const nir_ssa_undef_instr *instr)
4559 {
4560 unsigned num_components = instr->def.num_components;
4561 LLVMValueRef undef;
4562
4563 if (num_components == 1)
4564 undef = LLVMGetUndef(ctx->i32);
4565 else {
4566 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
4567 }
4568 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
4569 }
4570
4571 static void visit_jump(struct nir_to_llvm_context *ctx,
4572 const nir_jump_instr *instr)
4573 {
4574 switch (instr->type) {
4575 case nir_jump_break:
4576 LLVMBuildBr(ctx->builder, ctx->break_block);
4577 LLVMClearInsertionPosition(ctx->builder);
4578 break;
4579 case nir_jump_continue:
4580 LLVMBuildBr(ctx->builder, ctx->continue_block);
4581 LLVMClearInsertionPosition(ctx->builder);
4582 break;
4583 default:
4584 fprintf(stderr, "Unknown NIR jump instr: ");
4585 nir_print_instr(&instr->instr, stderr);
4586 fprintf(stderr, "\n");
4587 abort();
4588 }
4589 }
4590
4591 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4592 struct exec_list *list);
4593
4594 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
4595 {
4596 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
4597 nir_foreach_instr(instr, block)
4598 {
4599 switch (instr->type) {
4600 case nir_instr_type_alu:
4601 visit_alu(ctx, nir_instr_as_alu(instr));
4602 break;
4603 case nir_instr_type_load_const:
4604 visit_load_const(ctx, nir_instr_as_load_const(instr));
4605 break;
4606 case nir_instr_type_intrinsic:
4607 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
4608 break;
4609 case nir_instr_type_tex:
4610 visit_tex(ctx, nir_instr_as_tex(instr));
4611 break;
4612 case nir_instr_type_phi:
4613 visit_phi(ctx, nir_instr_as_phi(instr));
4614 break;
4615 case nir_instr_type_ssa_undef:
4616 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
4617 break;
4618 case nir_instr_type_jump:
4619 visit_jump(ctx, nir_instr_as_jump(instr));
4620 break;
4621 default:
4622 fprintf(stderr, "Unknown NIR instr type: ");
4623 nir_print_instr(instr, stderr);
4624 fprintf(stderr, "\n");
4625 abort();
4626 }
4627 }
4628
4629 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
4630 }
4631
4632 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
4633 {
4634 LLVMValueRef value = get_src(ctx, if_stmt->condition);
4635
4636 LLVMBasicBlockRef merge_block =
4637 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4638 LLVMBasicBlockRef if_block =
4639 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4640 LLVMBasicBlockRef else_block = merge_block;
4641 if (!exec_list_is_empty(&if_stmt->else_list))
4642 else_block = LLVMAppendBasicBlockInContext(
4643 ctx->context, ctx->main_function, "");
4644
4645 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
4646 LLVMConstInt(ctx->i32, 0, false), "");
4647 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
4648
4649 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
4650 visit_cf_list(ctx, &if_stmt->then_list);
4651 if (LLVMGetInsertBlock(ctx->builder))
4652 LLVMBuildBr(ctx->builder, merge_block);
4653
4654 if (!exec_list_is_empty(&if_stmt->else_list)) {
4655 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
4656 visit_cf_list(ctx, &if_stmt->else_list);
4657 if (LLVMGetInsertBlock(ctx->builder))
4658 LLVMBuildBr(ctx->builder, merge_block);
4659 }
4660
4661 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
4662 }
4663
4664 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
4665 {
4666 LLVMBasicBlockRef continue_parent = ctx->continue_block;
4667 LLVMBasicBlockRef break_parent = ctx->break_block;
4668
4669 ctx->continue_block =
4670 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4671 ctx->break_block =
4672 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
4673
4674 LLVMBuildBr(ctx->builder, ctx->continue_block);
4675 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
4676 visit_cf_list(ctx, &loop->body);
4677
4678 if (LLVMGetInsertBlock(ctx->builder))
4679 LLVMBuildBr(ctx->builder, ctx->continue_block);
4680 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
4681
4682 ctx->continue_block = continue_parent;
4683 ctx->break_block = break_parent;
4684 }
4685
4686 static void visit_cf_list(struct nir_to_llvm_context *ctx,
4687 struct exec_list *list)
4688 {
4689 foreach_list_typed(nir_cf_node, node, node, list)
4690 {
4691 switch (node->type) {
4692 case nir_cf_node_block:
4693 visit_block(ctx, nir_cf_node_as_block(node));
4694 break;
4695
4696 case nir_cf_node_if:
4697 visit_if(ctx, nir_cf_node_as_if(node));
4698 break;
4699
4700 case nir_cf_node_loop:
4701 visit_loop(ctx, nir_cf_node_as_loop(node));
4702 break;
4703
4704 default:
4705 assert(0);
4706 }
4707 }
4708 }
4709
4710 static void
4711 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
4712 struct nir_variable *variable)
4713 {
4714 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
4715 LLVMValueRef t_offset;
4716 LLVMValueRef t_list;
4717 LLVMValueRef input;
4718 LLVMValueRef buffer_index;
4719 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
4720 int idx = variable->data.location;
4721 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
4722
4723 variable->data.driver_location = idx * 4;
4724
4725 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
4726 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
4727 ctx->start_instance, "");
4728 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
4729 ctx->shader_info->vs.vgpr_comp_cnt);
4730 } else
4731 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
4732 ctx->base_vertex, "");
4733
4734 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
4735 t_offset = LLVMConstInt(ctx->i32, index + i, false);
4736
4737 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
4738
4739 input = ac_build_buffer_load_format(&ctx->ac, t_list,
4740 buffer_index,
4741 LLVMConstInt(ctx->i32, 0, false),
4742 true);
4743
4744 for (unsigned chan = 0; chan < 4; chan++) {
4745 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4746 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
4747 to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->builder,
4748 input, llvm_chan, ""));
4749 }
4750 }
4751 }
4752
4753 static void interp_fs_input(struct nir_to_llvm_context *ctx,
4754 unsigned attr,
4755 LLVMValueRef interp_param,
4756 LLVMValueRef prim_mask,
4757 LLVMValueRef result[4])
4758 {
4759 LLVMValueRef attr_number;
4760 unsigned chan;
4761 LLVMValueRef i, j;
4762 bool interp = interp_param != NULL;
4763
4764 attr_number = LLVMConstInt(ctx->i32, attr, false);
4765
4766 /* fs.constant returns the param from the middle vertex, so it's not
4767 * really useful for flat shading. It's meant to be used for custom
4768 * interpolation (but the intrinsic can't fetch from the other two
4769 * vertices).
4770 *
4771 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
4772 * to do the right thing. The only reason we use fs.constant is that
4773 * fs.interp cannot be used on integers, because they can be equal
4774 * to NaN.
4775 */
4776 if (interp) {
4777 interp_param = LLVMBuildBitCast(ctx->builder, interp_param,
4778 LLVMVectorType(ctx->f32, 2), "");
4779
4780 i = LLVMBuildExtractElement(ctx->builder, interp_param,
4781 ctx->i32zero, "");
4782 j = LLVMBuildExtractElement(ctx->builder, interp_param,
4783 ctx->i32one, "");
4784 }
4785
4786 for (chan = 0; chan < 4; chan++) {
4787 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
4788
4789 if (interp) {
4790 result[chan] = ac_build_fs_interp(&ctx->ac,
4791 llvm_chan,
4792 attr_number,
4793 prim_mask, i, j);
4794 } else {
4795 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4796 LLVMConstInt(ctx->i32, 2, false),
4797 llvm_chan,
4798 attr_number,
4799 prim_mask);
4800 }
4801 }
4802 }
4803
4804 static void
4805 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4806 struct nir_variable *variable)
4807 {
4808 int idx = variable->data.location;
4809 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4810 LLVMValueRef interp;
4811
4812 variable->data.driver_location = idx * 4;
4813 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4814
4815 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4816 unsigned interp_type;
4817 if (variable->data.sample) {
4818 interp_type = INTERP_SAMPLE;
4819 ctx->shader_info->fs.force_persample = true;
4820 } else if (variable->data.centroid)
4821 interp_type = INTERP_CENTROID;
4822 else
4823 interp_type = INTERP_CENTER;
4824
4825 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4826 } else
4827 interp = NULL;
4828
4829 for (unsigned i = 0; i < attrib_count; ++i)
4830 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4831
4832 }
4833
4834 static void
4835 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4836 struct nir_variable *variable)
4837 {
4838 switch (ctx->stage) {
4839 case MESA_SHADER_VERTEX:
4840 handle_vs_input_decl(ctx, variable);
4841 break;
4842 case MESA_SHADER_FRAGMENT:
4843 handle_fs_input_decl(ctx, variable);
4844 break;
4845 default:
4846 break;
4847 }
4848
4849 }
4850
4851 static void
4852 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4853 struct nir_shader *nir)
4854 {
4855 unsigned index = 0;
4856 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4857 LLVMValueRef interp_param;
4858 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4859
4860 if (!(ctx->input_mask & (1ull << i)))
4861 continue;
4862
4863 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
4864 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
4865 interp_param = *inputs;
4866 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4867 inputs);
4868
4869 if (!interp_param)
4870 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4871 ++index;
4872 } else if (i == VARYING_SLOT_POS) {
4873 for(int i = 0; i < 3; ++i)
4874 inputs[i] = ctx->frag_pos[i];
4875
4876 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4877 }
4878 }
4879 ctx->shader_info->fs.num_interp = index;
4880 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4881 ctx->shader_info->fs.has_pcoord = true;
4882 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
4883 ctx->shader_info->fs.prim_id_input = true;
4884 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
4885 ctx->shader_info->fs.layer_input = true;
4886 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4887 }
4888
4889 static LLVMValueRef
4890 ac_build_alloca(struct nir_to_llvm_context *ctx,
4891 LLVMTypeRef type,
4892 const char *name)
4893 {
4894 LLVMBuilderRef builder = ctx->builder;
4895 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4896 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4897 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4898 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4899 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4900 LLVMValueRef res;
4901
4902 if (first_instr) {
4903 LLVMPositionBuilderBefore(first_builder, first_instr);
4904 } else {
4905 LLVMPositionBuilderAtEnd(first_builder, first_block);
4906 }
4907
4908 res = LLVMBuildAlloca(first_builder, type, name);
4909 LLVMBuildStore(builder, LLVMConstNull(type), res);
4910
4911 LLVMDisposeBuilder(first_builder);
4912
4913 return res;
4914 }
4915
4916 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4917 LLVMTypeRef type,
4918 const char *name)
4919 {
4920 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4921 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4922 return ptr;
4923 }
4924
4925 static void
4926 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4927 struct nir_variable *variable)
4928 {
4929 int idx = variable->data.location + variable->data.index;
4930 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4931 uint64_t mask_attribs;
4932 variable->data.driver_location = idx * 4;
4933
4934 /* tess ctrl has it's own load/store paths for outputs */
4935 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4936 return;
4937
4938 mask_attribs = ((1ull << attrib_count) - 1) << idx;
4939 if (ctx->stage == MESA_SHADER_VERTEX ||
4940 ctx->stage == MESA_SHADER_TESS_EVAL ||
4941 ctx->stage == MESA_SHADER_GEOMETRY) {
4942 if (idx == VARYING_SLOT_CLIP_DIST0) {
4943 int length = ctx->num_output_clips + ctx->num_output_culls;
4944 if (ctx->stage == MESA_SHADER_VERTEX) {
4945 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4946 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4947 }
4948 if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4949 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << ctx->num_output_clips) - 1;
4950 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << ctx->num_output_culls) - 1;
4951 }
4952
4953 if (length > 4)
4954 attrib_count = 2;
4955 else
4956 attrib_count = 1;
4957 mask_attribs = 1ull << idx;
4958 }
4959 }
4960
4961 for (unsigned i = 0; i < attrib_count; ++i) {
4962 for (unsigned chan = 0; chan < 4; chan++) {
4963 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4964 si_build_alloca_undef(ctx, ctx->f32, "");
4965 }
4966 }
4967 ctx->output_mask |= mask_attribs;
4968 }
4969
4970 static void
4971 setup_locals(struct nir_to_llvm_context *ctx,
4972 struct nir_function *func)
4973 {
4974 int i, j;
4975 ctx->num_locals = 0;
4976 nir_foreach_variable(variable, &func->impl->locals) {
4977 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4978 variable->data.driver_location = ctx->num_locals * 4;
4979 ctx->num_locals += attrib_count;
4980 }
4981 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4982 if (!ctx->locals)
4983 return;
4984
4985 for (i = 0; i < ctx->num_locals; i++) {
4986 for (j = 0; j < 4; j++) {
4987 ctx->locals[i * 4 + j] =
4988 si_build_alloca_undef(ctx, ctx->f32, "temp");
4989 }
4990 }
4991 }
4992
4993 static LLVMValueRef
4994 emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4995 {
4996 v = to_float(ctx, v);
4997 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, lo));
4998 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", ctx->f32, v, LLVMConstReal(ctx->f32, hi));
4999 }
5000
5001
5002 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
5003 LLVMValueRef src0, LLVMValueRef src1)
5004 {
5005 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
5006 LLVMValueRef comp[2];
5007
5008 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
5009 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
5010 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
5011 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
5012 }
5013
5014 /* Initialize arguments for the shader export intrinsic */
5015 static void
5016 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5017 LLVMValueRef *values,
5018 unsigned target,
5019 struct ac_export_args *args)
5020 {
5021 /* Default is 0xf. Adjusted below depending on the format. */
5022 args->enabled_channels = 0xf;
5023
5024 /* Specify whether the EXEC mask represents the valid mask */
5025 args->valid_mask = 0;
5026
5027 /* Specify whether this is the last export */
5028 args->done = 0;
5029
5030 /* Specify the target we are exporting */
5031 args->target = target;
5032
5033 args->compr = false;
5034 args->out[0] = LLVMGetUndef(ctx->f32);
5035 args->out[1] = LLVMGetUndef(ctx->f32);
5036 args->out[2] = LLVMGetUndef(ctx->f32);
5037 args->out[3] = LLVMGetUndef(ctx->f32);
5038
5039 if (!values)
5040 return;
5041
5042 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5043 LLVMValueRef val[4];
5044 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5045 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5046 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5047
5048 switch(col_format) {
5049 case V_028714_SPI_SHADER_ZERO:
5050 args->enabled_channels = 0; /* writemask */
5051 args->target = V_008DFC_SQ_EXP_NULL;
5052 break;
5053
5054 case V_028714_SPI_SHADER_32_R:
5055 args->enabled_channels = 1;
5056 args->out[0] = values[0];
5057 break;
5058
5059 case V_028714_SPI_SHADER_32_GR:
5060 args->enabled_channels = 0x3;
5061 args->out[0] = values[0];
5062 args->out[1] = values[1];
5063 break;
5064
5065 case V_028714_SPI_SHADER_32_AR:
5066 args->enabled_channels = 0x9;
5067 args->out[0] = values[0];
5068 args->out[3] = values[3];
5069 break;
5070
5071 case V_028714_SPI_SHADER_FP16_ABGR:
5072 args->compr = 1;
5073
5074 for (unsigned chan = 0; chan < 2; chan++) {
5075 LLVMValueRef pack_args[2] = {
5076 values[2 * chan],
5077 values[2 * chan + 1]
5078 };
5079 LLVMValueRef packed;
5080
5081 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
5082 args->out[chan] = packed;
5083 }
5084 break;
5085
5086 case V_028714_SPI_SHADER_UNORM16_ABGR:
5087 for (unsigned chan = 0; chan < 4; chan++) {
5088 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
5089 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5090 LLVMConstReal(ctx->f32, 65535), "");
5091 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5092 LLVMConstReal(ctx->f32, 0.5), "");
5093 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
5094 ctx->i32, "");
5095 }
5096
5097 args->compr = 1;
5098 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5099 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5100 break;
5101
5102 case V_028714_SPI_SHADER_SNORM16_ABGR:
5103 for (unsigned chan = 0; chan < 4; chan++) {
5104 val[chan] = emit_float_saturate(&ctx->ac, values[chan], -1, 1);
5105 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
5106 LLVMConstReal(ctx->f32, 32767), "");
5107
5108 /* If positive, add 0.5, else add -0.5. */
5109 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
5110 LLVMBuildSelect(ctx->builder,
5111 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
5112 val[chan], ctx->f32zero, ""),
5113 LLVMConstReal(ctx->f32, 0.5),
5114 LLVMConstReal(ctx->f32, -0.5), ""), "");
5115 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
5116 }
5117
5118 args->compr = 1;
5119 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5120 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5121 break;
5122
5123 case V_028714_SPI_SHADER_UINT16_ABGR: {
5124 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
5125
5126 for (unsigned chan = 0; chan < 4; chan++) {
5127 val[chan] = to_integer(&ctx->ac, values[chan]);
5128 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntULT, val[chan], max);
5129 }
5130
5131 args->compr = 1;
5132 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5133 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5134 break;
5135 }
5136
5137 case V_028714_SPI_SHADER_SINT16_ABGR: {
5138 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
5139 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
5140
5141 /* Clamp. */
5142 for (unsigned chan = 0; chan < 4; chan++) {
5143 val[chan] = to_integer(&ctx->ac, values[chan]);
5144 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSLT, val[chan], max);
5145 val[chan] = emit_minmax_int(&ctx->ac, LLVMIntSGT, val[chan], min);
5146 }
5147
5148 args->compr = 1;
5149 args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
5150 args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
5151 break;
5152 }
5153
5154 default:
5155 case V_028714_SPI_SHADER_32_ABGR:
5156 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5157 break;
5158 }
5159 } else
5160 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5161
5162 for (unsigned i = 0; i < 4; ++i)
5163 args->out[i] = to_float(&ctx->ac, args->out[i]);
5164 }
5165
5166 static void
5167 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5168 bool export_prim_id,
5169 struct ac_vs_output_info *outinfo)
5170 {
5171 uint32_t param_count = 0;
5172 unsigned target;
5173 unsigned pos_idx, num_pos_exports = 0;
5174 struct ac_export_args args, pos_args[4] = {};
5175 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5176 int i;
5177
5178 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5179 sizeof(outinfo->vs_output_param_offset));
5180
5181 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5182 LLVMValueRef slots[8];
5183 unsigned j;
5184
5185 if (outinfo->cull_dist_mask)
5186 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5187
5188 i = VARYING_SLOT_CLIP_DIST0;
5189 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5190 slots[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5191 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5192
5193 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5194 slots[i] = LLVMGetUndef(ctx->f32);
5195
5196 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
5197 target = V_008DFC_SQ_EXP_POS + 3;
5198 si_llvm_init_export_args(ctx, &slots[4], target, &args);
5199 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5200 &args, sizeof(args));
5201 }
5202
5203 target = V_008DFC_SQ_EXP_POS + 2;
5204 si_llvm_init_export_args(ctx, &slots[0], target, &args);
5205 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5206 &args, sizeof(args));
5207
5208 }
5209
5210 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5211 LLVMValueRef values[4];
5212 if (!(ctx->output_mask & (1ull << i)))
5213 continue;
5214
5215 for (unsigned j = 0; j < 4; j++)
5216 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5217 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5218
5219 if (i == VARYING_SLOT_POS) {
5220 target = V_008DFC_SQ_EXP_POS;
5221 } else if (i == VARYING_SLOT_CLIP_DIST0) {
5222 continue;
5223 } else if (i == VARYING_SLOT_PSIZ) {
5224 outinfo->writes_pointsize = true;
5225 psize_value = values[0];
5226 continue;
5227 } else if (i == VARYING_SLOT_LAYER) {
5228 outinfo->writes_layer = true;
5229 layer_value = values[0];
5230 target = V_008DFC_SQ_EXP_PARAM + param_count;
5231 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = param_count;
5232 param_count++;
5233 } else if (i == VARYING_SLOT_VIEWPORT) {
5234 outinfo->writes_viewport_index = true;
5235 viewport_index_value = values[0];
5236 continue;
5237 } else if (i == VARYING_SLOT_PRIMITIVE_ID) {
5238 target = V_008DFC_SQ_EXP_PARAM + param_count;
5239 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5240 param_count++;
5241 } else if (i >= VARYING_SLOT_VAR0) {
5242 outinfo->export_mask |= 1u << (i - VARYING_SLOT_VAR0);
5243 target = V_008DFC_SQ_EXP_PARAM + param_count;
5244 outinfo->vs_output_param_offset[i] = param_count;
5245 param_count++;
5246 }
5247
5248 si_llvm_init_export_args(ctx, values, target, &args);
5249
5250 if (target >= V_008DFC_SQ_EXP_POS &&
5251 target <= (V_008DFC_SQ_EXP_POS + 3)) {
5252 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
5253 &args, sizeof(args));
5254 } else {
5255 ac_build_export(&ctx->ac, &args);
5256 }
5257 }
5258
5259 /* We need to add the position output manually if it's missing. */
5260 if (!pos_args[0].out[0]) {
5261 pos_args[0].enabled_channels = 0xf;
5262 pos_args[0].valid_mask = 0;
5263 pos_args[0].done = 0;
5264 pos_args[0].target = V_008DFC_SQ_EXP_POS;
5265 pos_args[0].compr = 0;
5266 pos_args[0].out[0] = ctx->f32zero; /* X */
5267 pos_args[0].out[1] = ctx->f32zero; /* Y */
5268 pos_args[0].out[2] = ctx->f32zero; /* Z */
5269 pos_args[0].out[3] = ctx->f32one; /* W */
5270 }
5271
5272 uint32_t mask = ((outinfo->writes_pointsize == true ? 1 : 0) |
5273 (outinfo->writes_layer == true ? 4 : 0) |
5274 (outinfo->writes_viewport_index == true ? 8 : 0));
5275 if (mask) {
5276 pos_args[1].enabled_channels = mask;
5277 pos_args[1].valid_mask = 0;
5278 pos_args[1].done = 0;
5279 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
5280 pos_args[1].compr = 0;
5281 pos_args[1].out[0] = ctx->f32zero; /* X */
5282 pos_args[1].out[1] = ctx->f32zero; /* Y */
5283 pos_args[1].out[2] = ctx->f32zero; /* Z */
5284 pos_args[1].out[3] = ctx->f32zero; /* W */
5285
5286 if (outinfo->writes_pointsize == true)
5287 pos_args[1].out[0] = psize_value;
5288 if (outinfo->writes_layer == true)
5289 pos_args[1].out[2] = layer_value;
5290 if (outinfo->writes_viewport_index == true)
5291 pos_args[1].out[3] = viewport_index_value;
5292 }
5293 for (i = 0; i < 4; i++) {
5294 if (pos_args[i].out[0])
5295 num_pos_exports++;
5296 }
5297
5298 pos_idx = 0;
5299 for (i = 0; i < 4; i++) {
5300 if (!pos_args[i].out[0])
5301 continue;
5302
5303 /* Specify the target we are exporting */
5304 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
5305 if (pos_idx == num_pos_exports)
5306 pos_args[i].done = 1;
5307 ac_build_export(&ctx->ac, &pos_args[i]);
5308 }
5309
5310
5311 if (export_prim_id) {
5312 LLVMValueRef values[4];
5313 target = V_008DFC_SQ_EXP_PARAM + param_count;
5314 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count;
5315 param_count++;
5316
5317 values[0] = ctx->vs_prim_id;
5318 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
5319 ctx->shader_info->vs.vgpr_comp_cnt);
5320 for (unsigned j = 1; j < 4; j++)
5321 values[j] = ctx->f32zero;
5322 si_llvm_init_export_args(ctx, values, target, &args);
5323 ac_build_export(&ctx->ac, &args);
5324 outinfo->export_prim_id = true;
5325 }
5326
5327 outinfo->pos_exports = num_pos_exports;
5328 outinfo->param_exports = param_count;
5329 }
5330
5331 static void
5332 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
5333 struct ac_es_output_info *outinfo)
5334 {
5335 int j;
5336 uint64_t max_output_written = 0;
5337 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5338 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5339 int param_index;
5340 int length = 4;
5341
5342 if (!(ctx->output_mask & (1ull << i)))
5343 continue;
5344
5345 if (i == VARYING_SLOT_CLIP_DIST0)
5346 length = ctx->num_output_clips + ctx->num_output_culls;
5347
5348 param_index = shader_io_get_unique_index(i);
5349
5350 max_output_written = MAX2(param_index + (length > 4), max_output_written);
5351
5352 for (j = 0; j < length; j++) {
5353 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder, out_ptr[j], "");
5354 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
5355
5356 ac_build_buffer_store_dword(&ctx->ac,
5357 ctx->esgs_ring,
5358 out_val, 1,
5359 NULL, ctx->es2gs_offset,
5360 (4 * param_index + j) * 4,
5361 1, 1, true, true);
5362 }
5363 }
5364 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
5365 }
5366
5367 static void
5368 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
5369 {
5370 LLVMValueRef vertex_id = ctx->rel_auto_id;
5371 LLVMValueRef vertex_dw_stride = unpack_param(ctx, ctx->ls_out_layout, 13, 8);
5372 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->builder, vertex_id,
5373 vertex_dw_stride, "");
5374
5375 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5376 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
5377 int length = 4;
5378
5379 if (!(ctx->output_mask & (1ull << i)))
5380 continue;
5381
5382 if (i == VARYING_SLOT_CLIP_DIST0)
5383 length = ctx->num_output_clips + ctx->num_output_culls;
5384 int param = shader_io_get_unique_index(i);
5385 mark_tess_output(ctx, false, param);
5386 if (length > 4)
5387 mark_tess_output(ctx, false, param + 1);
5388 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->builder, base_dw_addr,
5389 LLVMConstInt(ctx->i32, param * 4, false),
5390 "");
5391 for (unsigned j = 0; j < length; j++) {
5392 lds_store(ctx, dw_addr,
5393 LLVMBuildLoad(ctx->builder, out_ptr[j], ""));
5394 dw_addr = LLVMBuildAdd(ctx->builder, dw_addr, ctx->i32one, "");
5395 }
5396 }
5397 }
5398
5399 struct ac_build_if_state
5400 {
5401 struct nir_to_llvm_context *ctx;
5402 LLVMValueRef condition;
5403 LLVMBasicBlockRef entry_block;
5404 LLVMBasicBlockRef true_block;
5405 LLVMBasicBlockRef false_block;
5406 LLVMBasicBlockRef merge_block;
5407 };
5408
5409 static LLVMBasicBlockRef
5410 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
5411 {
5412 LLVMBasicBlockRef current_block;
5413 LLVMBasicBlockRef next_block;
5414 LLVMBasicBlockRef new_block;
5415
5416 /* get current basic block */
5417 current_block = LLVMGetInsertBlock(ctx->builder);
5418
5419 /* chqeck if there's another block after this one */
5420 next_block = LLVMGetNextBasicBlock(current_block);
5421 if (next_block) {
5422 /* insert the new block before the next block */
5423 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
5424 }
5425 else {
5426 /* append new block after current block */
5427 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5428 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
5429 }
5430 return new_block;
5431 }
5432
5433 static void
5434 ac_nir_build_if(struct ac_build_if_state *ifthen,
5435 struct nir_to_llvm_context *ctx,
5436 LLVMValueRef condition)
5437 {
5438 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->builder);
5439
5440 memset(ifthen, 0, sizeof *ifthen);
5441 ifthen->ctx = ctx;
5442 ifthen->condition = condition;
5443 ifthen->entry_block = block;
5444
5445 /* create endif/merge basic block for the phi functions */
5446 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
5447
5448 /* create/insert true_block before merge_block */
5449 ifthen->true_block =
5450 LLVMInsertBasicBlockInContext(ctx->context,
5451 ifthen->merge_block,
5452 "if-true-block");
5453
5454 /* successive code goes into the true block */
5455 LLVMPositionBuilderAtEnd(ctx->builder, ifthen->true_block);
5456 }
5457
5458 /**
5459 * End a conditional.
5460 */
5461 static void
5462 ac_nir_build_endif(struct ac_build_if_state *ifthen)
5463 {
5464 LLVMBuilderRef builder = ifthen->ctx->builder;
5465
5466 /* Insert branch to the merge block from current block */
5467 LLVMBuildBr(builder, ifthen->merge_block);
5468
5469 /*
5470 * Now patch in the various branch instructions.
5471 */
5472
5473 /* Insert the conditional branch instruction at the end of entry_block */
5474 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
5475 if (ifthen->false_block) {
5476 /* we have an else clause */
5477 LLVMBuildCondBr(builder, ifthen->condition,
5478 ifthen->true_block, ifthen->false_block);
5479 }
5480 else {
5481 /* no else clause */
5482 LLVMBuildCondBr(builder, ifthen->condition,
5483 ifthen->true_block, ifthen->merge_block);
5484 }
5485
5486 /* Resume building code at end of the ifthen->merge_block */
5487 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
5488 }
5489
5490 static void
5491 write_tess_factors(struct nir_to_llvm_context *ctx)
5492 {
5493 unsigned stride, outer_comps, inner_comps;
5494 struct ac_build_if_state if_ctx, inner_if_ctx;
5495 LLVMValueRef invocation_id = unpack_param(ctx, ctx->tcs_rel_ids, 8, 5);
5496 LLVMValueRef rel_patch_id = unpack_param(ctx, ctx->tcs_rel_ids, 0, 8);
5497 unsigned tess_inner_index, tess_outer_index;
5498 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
5499 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
5500 int i;
5501 emit_barrier(ctx);
5502
5503 switch (ctx->options->key.tcs.primitive_mode) {
5504 case GL_ISOLINES:
5505 stride = 2;
5506 outer_comps = 2;
5507 inner_comps = 0;
5508 break;
5509 case GL_TRIANGLES:
5510 stride = 4;
5511 outer_comps = 3;
5512 inner_comps = 1;
5513 break;
5514 case GL_QUADS:
5515 stride = 6;
5516 outer_comps = 4;
5517 inner_comps = 2;
5518 break;
5519 default:
5520 return;
5521 }
5522
5523 ac_nir_build_if(&if_ctx, ctx,
5524 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5525 invocation_id, ctx->i32zero, ""));
5526
5527 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5528 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5529
5530 mark_tess_output(ctx, true, tess_inner_index);
5531 mark_tess_output(ctx, true, tess_outer_index);
5532 lds_base = get_tcs_out_current_patch_data_offset(ctx);
5533 lds_inner = LLVMBuildAdd(ctx->builder, lds_base,
5534 LLVMConstInt(ctx->i32, tess_inner_index * 4, false), "");
5535 lds_outer = LLVMBuildAdd(ctx->builder, lds_base,
5536 LLVMConstInt(ctx->i32, tess_outer_index * 4, false), "");
5537
5538 for (i = 0; i < 4; i++) {
5539 inner[i] = LLVMGetUndef(ctx->i32);
5540 outer[i] = LLVMGetUndef(ctx->i32);
5541 }
5542
5543 // LINES reverseal
5544 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
5545 outer[0] = out[1] = lds_load(ctx, lds_outer);
5546 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5547 LLVMConstInt(ctx->i32, 1, false), "");
5548 outer[1] = out[0] = lds_load(ctx, lds_outer);
5549 } else {
5550 for (i = 0; i < outer_comps; i++) {
5551 outer[i] = out[i] =
5552 lds_load(ctx, lds_outer);
5553 lds_outer = LLVMBuildAdd(ctx->builder, lds_outer,
5554 LLVMConstInt(ctx->i32, 1, false), "");
5555 }
5556 for (i = 0; i < inner_comps; i++) {
5557 inner[i] = out[outer_comps+i] =
5558 lds_load(ctx, lds_inner);
5559 lds_inner = LLVMBuildAdd(ctx->builder, lds_inner,
5560 LLVMConstInt(ctx->i32, 1, false), "");
5561 }
5562 }
5563
5564 /* Convert the outputs to vectors for stores. */
5565 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
5566 vec1 = NULL;
5567
5568 if (stride > 4)
5569 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
5570
5571
5572 buffer = ctx->hs_ring_tess_factor;
5573 tf_base = ctx->tess_factor_offset;
5574 byteoffset = LLVMBuildMul(ctx->builder, rel_patch_id,
5575 LLVMConstInt(ctx->i32, 4 * stride, false), "");
5576
5577 ac_nir_build_if(&inner_if_ctx, ctx,
5578 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
5579 rel_patch_id, ctx->i32zero, ""));
5580
5581 /* Store the dynamic HS control word. */
5582 ac_build_buffer_store_dword(&ctx->ac, buffer,
5583 LLVMConstInt(ctx->i32, 0x80000000, false),
5584 1, ctx->i32zero, tf_base,
5585 0, 1, 0, true, false);
5586 ac_nir_build_endif(&inner_if_ctx);
5587
5588 /* Store the tessellation factors. */
5589 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
5590 MIN2(stride, 4), byteoffset, tf_base,
5591 4, 1, 0, true, false);
5592 if (vec1)
5593 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
5594 stride - 4, byteoffset, tf_base,
5595 20, 1, 0, true, false);
5596
5597 //TODO store to offchip for TES to read - only if TES reads them
5598 if (1) {
5599 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
5600 LLVMValueRef tf_inner_offset;
5601 unsigned param_outer, param_inner;
5602
5603 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
5604 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
5605 LLVMConstInt(ctx->i32, param_outer, 0));
5606
5607 outer_vec = ac_build_gather_values(&ctx->ac, outer,
5608 util_next_power_of_two(outer_comps));
5609
5610 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
5611 outer_comps, tf_outer_offset,
5612 ctx->oc_lds, 0, 1, 0, true, false);
5613 if (inner_comps) {
5614 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
5615 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
5616 LLVMConstInt(ctx->i32, param_inner, 0));
5617
5618 inner_vec = inner_comps == 1 ? inner[0] :
5619 ac_build_gather_values(&ctx->ac, inner, inner_comps);
5620 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
5621 inner_comps, tf_inner_offset,
5622 ctx->oc_lds, 0, 1, 0, true, false);
5623 }
5624 }
5625 ac_nir_build_endif(&if_ctx);
5626 }
5627
5628 static void
5629 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
5630 {
5631 write_tess_factors(ctx);
5632 }
5633
5634 static bool
5635 si_export_mrt_color(struct nir_to_llvm_context *ctx,
5636 LLVMValueRef *color, unsigned param, bool is_last,
5637 struct ac_export_args *args)
5638 {
5639 /* Export */
5640 si_llvm_init_export_args(ctx, color, param,
5641 args);
5642
5643 if (is_last) {
5644 args->valid_mask = 1; /* whether the EXEC mask is valid */
5645 args->done = 1; /* DONE bit */
5646 } else if (!args->enabled_channels)
5647 return false; /* unnecessary NULL export */
5648
5649 return true;
5650 }
5651
5652 static void
5653 si_export_mrt_z(struct nir_to_llvm_context *ctx,
5654 LLVMValueRef depth, LLVMValueRef stencil,
5655 LLVMValueRef samplemask)
5656 {
5657 struct ac_export_args args;
5658
5659 args.enabled_channels = 0;
5660 args.valid_mask = 1;
5661 args.done = 1;
5662 args.target = V_008DFC_SQ_EXP_MRTZ;
5663 args.compr = false;
5664
5665 args.out[0] = LLVMGetUndef(ctx->f32); /* R, depth */
5666 args.out[1] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
5667 args.out[2] = LLVMGetUndef(ctx->f32); /* B, sample mask */
5668 args.out[3] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
5669
5670 if (depth) {
5671 args.out[0] = depth;
5672 args.enabled_channels |= 0x1;
5673 }
5674
5675 if (stencil) {
5676 args.out[1] = stencil;
5677 args.enabled_channels |= 0x2;
5678 }
5679
5680 if (samplemask) {
5681 args.out[2] = samplemask;
5682 args.enabled_channels |= 0x4;
5683 }
5684
5685 /* SI (except OLAND) has a bug that it only looks
5686 * at the X writemask component. */
5687 if (ctx->options->chip_class == SI &&
5688 ctx->options->family != CHIP_OLAND)
5689 args.enabled_channels |= 0x1;
5690
5691 ac_build_export(&ctx->ac, &args);
5692 }
5693
5694 static void
5695 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
5696 {
5697 unsigned index = 0;
5698 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
5699 struct ac_export_args color_args[8];
5700
5701 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
5702 LLVMValueRef values[4];
5703
5704 if (!(ctx->output_mask & (1ull << i)))
5705 continue;
5706
5707 if (i == FRAG_RESULT_DEPTH) {
5708 ctx->shader_info->fs.writes_z = true;
5709 depth = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5710 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5711 } else if (i == FRAG_RESULT_STENCIL) {
5712 ctx->shader_info->fs.writes_stencil = true;
5713 stencil = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5714 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5715 } else if (i == FRAG_RESULT_SAMPLE_MASK) {
5716 ctx->shader_info->fs.writes_sample_mask = true;
5717 samplemask = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5718 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
5719 } else {
5720 bool last = false;
5721 for (unsigned j = 0; j < 4; j++)
5722 values[j] = to_float(&ctx->ac, LLVMBuildLoad(ctx->builder,
5723 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
5724
5725 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
5726 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
5727
5728 bool ret = si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + (i - FRAG_RESULT_DATA0), last, &color_args[index]);
5729 if (ret)
5730 index++;
5731 }
5732 }
5733
5734 for (unsigned i = 0; i < index; i++)
5735 ac_build_export(&ctx->ac, &color_args[i]);
5736 if (depth || stencil || samplemask)
5737 si_export_mrt_z(ctx, depth, stencil, samplemask);
5738 else if (!index) {
5739 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, &color_args[0]);
5740 ac_build_export(&ctx->ac, &color_args[0]);
5741 }
5742
5743 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
5744 }
5745
5746 static void
5747 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
5748 {
5749 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
5750 }
5751
5752 static void
5753 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
5754 {
5755 switch (ctx->stage) {
5756 case MESA_SHADER_VERTEX:
5757 if (ctx->options->key.vs.as_ls)
5758 handle_ls_outputs_post(ctx);
5759 else if (ctx->options->key.vs.as_es)
5760 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
5761 else
5762 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
5763 &ctx->shader_info->vs.outinfo);
5764 break;
5765 case MESA_SHADER_FRAGMENT:
5766 handle_fs_outputs_post(ctx);
5767 break;
5768 case MESA_SHADER_GEOMETRY:
5769 emit_gs_epilogue(ctx);
5770 break;
5771 case MESA_SHADER_TESS_CTRL:
5772 handle_tcs_outputs_post(ctx);
5773 break;
5774 case MESA_SHADER_TESS_EVAL:
5775 if (ctx->options->key.tes.as_es)
5776 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
5777 else
5778 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
5779 &ctx->shader_info->tes.outinfo);
5780 break;
5781 default:
5782 break;
5783 }
5784 }
5785
5786 static void
5787 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
5788 struct nir_variable *variable, uint32_t *offset, int idx)
5789 {
5790 unsigned size = glsl_count_attribute_slots(variable->type, false);
5791 variable->data.driver_location = *offset;
5792 *offset += size;
5793 }
5794
5795 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
5796 {
5797 LLVMPassManagerRef passmgr;
5798 /* Create the pass manager */
5799 passmgr = LLVMCreateFunctionPassManagerForModule(
5800 ctx->module);
5801
5802 /* This pass should eliminate all the load and store instructions */
5803 LLVMAddPromoteMemoryToRegisterPass(passmgr);
5804
5805 /* Add some optimization passes */
5806 LLVMAddScalarReplAggregatesPass(passmgr);
5807 LLVMAddLICMPass(passmgr);
5808 LLVMAddAggressiveDCEPass(passmgr);
5809 LLVMAddCFGSimplificationPass(passmgr);
5810 LLVMAddInstructionCombiningPass(passmgr);
5811
5812 /* Run the pass */
5813 LLVMInitializeFunctionPassManager(passmgr);
5814 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
5815 LLVMFinalizeFunctionPassManager(passmgr);
5816
5817 LLVMDisposeBuilder(ctx->builder);
5818 LLVMDisposePassManager(passmgr);
5819 }
5820
5821 static void
5822 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
5823 {
5824 struct ac_vs_output_info *outinfo;
5825
5826 switch (ctx->stage) {
5827 case MESA_SHADER_FRAGMENT:
5828 case MESA_SHADER_COMPUTE:
5829 case MESA_SHADER_TESS_CTRL:
5830 case MESA_SHADER_GEOMETRY:
5831 return;
5832 case MESA_SHADER_VERTEX:
5833 if (ctx->options->key.vs.as_ls ||
5834 ctx->options->key.vs.as_es)
5835 return;
5836 outinfo = &ctx->shader_info->vs.outinfo;
5837 break;
5838 case MESA_SHADER_TESS_EVAL:
5839 if (ctx->options->key.vs.as_es)
5840 return;
5841 outinfo = &ctx->shader_info->tes.outinfo;
5842 break;
5843 default:
5844 unreachable("Unhandled shader type");
5845 }
5846
5847 ac_optimize_vs_outputs(&ctx->ac,
5848 ctx->main_function,
5849 outinfo->vs_output_param_offset,
5850 VARYING_SLOT_MAX,
5851 &outinfo->param_exports);
5852 }
5853
5854 static void
5855 ac_setup_rings(struct nir_to_llvm_context *ctx)
5856 {
5857 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
5858 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
5859 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_VS, false));
5860 }
5861
5862 if (ctx->is_gs_copy_shader) {
5863 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_VS, false));
5864 }
5865 if (ctx->stage == MESA_SHADER_GEOMETRY) {
5866 LLVMValueRef tmp;
5867 ctx->esgs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_ESGS_GS, false));
5868 ctx->gsvs_ring = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_GSVS_GS, false));
5869
5870 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
5871
5872 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
5873 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
5874 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
5875 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
5876 }
5877
5878 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
5879 ctx->stage == MESA_SHADER_TESS_EVAL) {
5880 ctx->hs_ring_tess_offchip = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_OFFCHIP, false));
5881 ctx->hs_ring_tess_factor = ac_build_indexed_load_const(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->i32, RING_HS_TESS_FACTOR, false));
5882 }
5883 }
5884
5885 static unsigned
5886 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
5887 const struct nir_shader *nir)
5888 {
5889 switch (nir->stage) {
5890 case MESA_SHADER_TESS_CTRL:
5891 return chip_class >= CIK ? 128 : 64;
5892 case MESA_SHADER_GEOMETRY:
5893 return 64;
5894 case MESA_SHADER_COMPUTE:
5895 break;
5896 default:
5897 return 0;
5898 }
5899
5900 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
5901 nir->info.cs.local_size[1] *
5902 nir->info.cs.local_size[2];
5903 return max_workgroup_size;
5904 }
5905
5906 static
5907 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
5908 struct nir_shader *nir,
5909 struct ac_shader_variant_info *shader_info,
5910 const struct ac_nir_compiler_options *options)
5911 {
5912 struct nir_to_llvm_context ctx = {0};
5913 struct nir_function *func;
5914 unsigned i;
5915 ctx.options = options;
5916 ctx.shader_info = shader_info;
5917 ctx.context = LLVMContextCreate();
5918 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5919
5920 ac_llvm_context_init(&ctx.ac, ctx.context);
5921 ctx.ac.module = ctx.module;
5922
5923 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
5924
5925 memset(shader_info, 0, sizeof(*shader_info));
5926
5927 ac_nir_shader_info_pass(nir, options, &shader_info->info);
5928
5929 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
5930
5931 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
5932 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
5933 LLVMSetDataLayout(ctx.module, data_layout_str);
5934 LLVMDisposeTargetData(data_layout);
5935 LLVMDisposeMessage(data_layout_str);
5936
5937 setup_types(&ctx);
5938
5939 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5940 ctx.ac.builder = ctx.builder;
5941 ctx.stage = nir->stage;
5942 ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, nir);
5943
5944 for (i = 0; i < AC_UD_MAX_SETS; i++)
5945 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
5946 for (i = 0; i < AC_UD_MAX_UD; i++)
5947 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
5948
5949 create_function(&ctx);
5950
5951 if (nir->stage == MESA_SHADER_COMPUTE) {
5952 int num_shared = 0;
5953 nir_foreach_variable(variable, &nir->shared)
5954 num_shared++;
5955 if (num_shared) {
5956 int idx = 0;
5957 uint32_t shared_size = 0;
5958 LLVMValueRef var;
5959 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
5960 nir_foreach_variable(variable, &nir->shared) {
5961 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
5962 idx++;
5963 }
5964
5965 shared_size *= 16;
5966 var = LLVMAddGlobalInAddressSpace(ctx.module,
5967 LLVMArrayType(ctx.i8, shared_size),
5968 "compute_lds",
5969 LOCAL_ADDR_SPACE);
5970 LLVMSetAlignment(var, 4);
5971 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
5972 }
5973 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
5974 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
5975
5976 ctx.gs_max_out_vertices = nir->info.gs.vertices_out;
5977 } else if (nir->stage == MESA_SHADER_TESS_EVAL) {
5978 ctx.tes_primitive_mode = nir->info.tess.primitive_mode;
5979 }
5980
5981 ac_setup_rings(&ctx);
5982
5983 nir_foreach_variable(variable, &nir->inputs)
5984 handle_shader_input_decl(&ctx, variable);
5985
5986 if (nir->stage == MESA_SHADER_FRAGMENT)
5987 handle_fs_inputs_pre(&ctx, nir);
5988
5989 ctx.num_output_clips = nir->info.clip_distance_array_size;
5990 ctx.num_output_culls = nir->info.cull_distance_array_size;
5991
5992 nir_foreach_variable(variable, &nir->outputs)
5993 handle_shader_output_decl(&ctx, variable);
5994
5995 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5996 _mesa_key_pointer_equal);
5997 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
5998 _mesa_key_pointer_equal);
5999
6000 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6001
6002 setup_locals(&ctx, func);
6003
6004 visit_cf_list(&ctx, &func->impl->body);
6005 phi_post_pass(&ctx);
6006
6007 handle_shader_outputs_post(&ctx);
6008 LLVMBuildRetVoid(ctx.builder);
6009
6010 ac_llvm_finalize_module(&ctx);
6011
6012 ac_nir_eliminate_const_vs_outputs(&ctx);
6013 free(ctx.locals);
6014 ralloc_free(ctx.defs);
6015 ralloc_free(ctx.phis);
6016
6017 if (nir->stage == MESA_SHADER_GEOMETRY) {
6018 unsigned addclip = ctx.num_output_clips + ctx.num_output_culls > 4;
6019 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6020 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6021 nir->info.gs.vertices_out;
6022 } else if (nir->stage == MESA_SHADER_TESS_CTRL) {
6023 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6024 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6025 } else if (nir->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6026 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6027 }
6028
6029 return ctx.module;
6030 }
6031
6032 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6033 {
6034 unsigned *retval = (unsigned *)context;
6035 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6036 char *description = LLVMGetDiagInfoDescription(di);
6037
6038 if (severity == LLVMDSError) {
6039 *retval = 1;
6040 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6041 description);
6042 }
6043
6044 LLVMDisposeMessage(description);
6045 }
6046
6047 static unsigned ac_llvm_compile(LLVMModuleRef M,
6048 struct ac_shader_binary *binary,
6049 LLVMTargetMachineRef tm)
6050 {
6051 unsigned retval = 0;
6052 char *err;
6053 LLVMContextRef llvm_ctx;
6054 LLVMMemoryBufferRef out_buffer;
6055 unsigned buffer_size;
6056 const char *buffer_data;
6057 LLVMBool mem_err;
6058
6059 /* Setup Diagnostic Handler*/
6060 llvm_ctx = LLVMGetModuleContext(M);
6061
6062 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6063 &retval);
6064
6065 /* Compile IR*/
6066 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6067 &err, &out_buffer);
6068
6069 /* Process Errors/Warnings */
6070 if (mem_err) {
6071 fprintf(stderr, "%s: %s", __FUNCTION__, err);
6072 free(err);
6073 retval = 1;
6074 goto out;
6075 }
6076
6077 /* Extract Shader Code*/
6078 buffer_size = LLVMGetBufferSize(out_buffer);
6079 buffer_data = LLVMGetBufferStart(out_buffer);
6080
6081 ac_elf_read(buffer_data, buffer_size, binary);
6082
6083 /* Clean up */
6084 LLVMDisposeMemoryBuffer(out_buffer);
6085
6086 out:
6087 return retval;
6088 }
6089
6090 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
6091 LLVMModuleRef llvm_module,
6092 struct ac_shader_binary *binary,
6093 struct ac_shader_config *config,
6094 struct ac_shader_variant_info *shader_info,
6095 gl_shader_stage stage,
6096 bool dump_shader, bool supports_spill)
6097 {
6098 if (dump_shader)
6099 ac_dump_module(llvm_module);
6100
6101 memset(binary, 0, sizeof(*binary));
6102 int v = ac_llvm_compile(llvm_module, binary, tm);
6103 if (v) {
6104 fprintf(stderr, "compile failed\n");
6105 }
6106
6107 if (dump_shader)
6108 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
6109
6110 ac_shader_binary_read_config(binary, config, 0, supports_spill);
6111
6112 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
6113 LLVMDisposeModule(llvm_module);
6114 LLVMContextDispose(ctx);
6115
6116 if (stage == MESA_SHADER_FRAGMENT) {
6117 shader_info->num_input_vgprs = 0;
6118 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
6119 shader_info->num_input_vgprs += 2;
6120 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
6121 shader_info->num_input_vgprs += 2;
6122 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
6123 shader_info->num_input_vgprs += 2;
6124 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
6125 shader_info->num_input_vgprs += 3;
6126 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
6127 shader_info->num_input_vgprs += 2;
6128 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
6129 shader_info->num_input_vgprs += 2;
6130 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
6131 shader_info->num_input_vgprs += 2;
6132 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
6133 shader_info->num_input_vgprs += 1;
6134 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
6135 shader_info->num_input_vgprs += 1;
6136 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
6137 shader_info->num_input_vgprs += 1;
6138 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
6139 shader_info->num_input_vgprs += 1;
6140 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
6141 shader_info->num_input_vgprs += 1;
6142 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
6143 shader_info->num_input_vgprs += 1;
6144 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
6145 shader_info->num_input_vgprs += 1;
6146 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
6147 shader_info->num_input_vgprs += 1;
6148 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
6149 shader_info->num_input_vgprs += 1;
6150 }
6151 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
6152
6153 /* +3 for scratch wave offset and VCC */
6154 config->num_sgprs = MAX2(config->num_sgprs,
6155 shader_info->num_input_sgprs + 3);
6156 }
6157
6158 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
6159 struct ac_shader_binary *binary,
6160 struct ac_shader_config *config,
6161 struct ac_shader_variant_info *shader_info,
6162 struct nir_shader *nir,
6163 const struct ac_nir_compiler_options *options,
6164 bool dump_shader)
6165 {
6166
6167 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
6168 options);
6169
6170 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
6171 switch (nir->stage) {
6172 case MESA_SHADER_COMPUTE:
6173 for (int i = 0; i < 3; ++i)
6174 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
6175 break;
6176 case MESA_SHADER_FRAGMENT:
6177 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
6178 break;
6179 case MESA_SHADER_GEOMETRY:
6180 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
6181 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
6182 shader_info->gs.output_prim = nir->info.gs.output_primitive;
6183 shader_info->gs.invocations = nir->info.gs.invocations;
6184 break;
6185 case MESA_SHADER_TESS_EVAL:
6186 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
6187 shader_info->tes.spacing = nir->info.tess.spacing;
6188 shader_info->tes.ccw = nir->info.tess.ccw;
6189 shader_info->tes.point_mode = nir->info.tess.point_mode;
6190 shader_info->tes.as_es = options->key.tes.as_es;
6191 break;
6192 case MESA_SHADER_TESS_CTRL:
6193 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
6194 break;
6195 case MESA_SHADER_VERTEX:
6196 shader_info->vs.as_es = options->key.vs.as_es;
6197 shader_info->vs.as_ls = options->key.vs.as_ls;
6198 /* in LS mode we need at least 1, invocation id needs 3, handled elsewhere */
6199 if (options->key.vs.as_ls)
6200 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
6201 break;
6202 default:
6203 break;
6204 }
6205 }
6206
6207 static void
6208 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
6209 {
6210 LLVMValueRef args[9];
6211 args[0] = ctx->gsvs_ring;
6212 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
6213 args[3] = ctx->i32zero;
6214 args[4] = ctx->i32one; /* OFFEN */
6215 args[5] = ctx->i32zero; /* IDXEN */
6216 args[6] = ctx->i32one; /* GLC */
6217 args[7] = ctx->i32one; /* SLC */
6218 args[8] = ctx->i32zero; /* TFE */
6219
6220 int idx = 0;
6221
6222 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
6223 int length = 4;
6224 int slot = idx;
6225 int slot_inc = 1;
6226 if (!(ctx->output_mask & (1ull << i)))
6227 continue;
6228
6229 if (i == VARYING_SLOT_CLIP_DIST0) {
6230 /* unpack clip and cull from a single set of slots */
6231 length = ctx->num_output_clips + ctx->num_output_culls;
6232 if (length > 4)
6233 slot_inc = 2;
6234 }
6235
6236 for (unsigned j = 0; j < length; j++) {
6237 LLVMValueRef value;
6238 args[2] = LLVMConstInt(ctx->i32,
6239 (slot * 4 + j) *
6240 ctx->gs_max_out_vertices * 16 * 4, false);
6241
6242 value = ac_build_intrinsic(&ctx->ac,
6243 "llvm.SI.buffer.load.dword.i32.i32",
6244 ctx->i32, args, 9,
6245 AC_FUNC_ATTR_READONLY |
6246 AC_FUNC_ATTR_LEGACY);
6247
6248 LLVMBuildStore(ctx->builder,
6249 to_float(&ctx->ac, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
6250 }
6251 idx += slot_inc;
6252 }
6253 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
6254 }
6255
6256 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
6257 struct nir_shader *geom_shader,
6258 struct ac_shader_binary *binary,
6259 struct ac_shader_config *config,
6260 struct ac_shader_variant_info *shader_info,
6261 const struct ac_nir_compiler_options *options,
6262 bool dump_shader)
6263 {
6264 struct nir_to_llvm_context ctx = {0};
6265 ctx.context = LLVMContextCreate();
6266 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6267 ctx.options = options;
6268 ctx.shader_info = shader_info;
6269
6270 ac_llvm_context_init(&ctx.ac, ctx.context);
6271 ctx.ac.module = ctx.module;
6272
6273 ctx.is_gs_copy_shader = true;
6274 LLVMSetTarget(ctx.module, "amdgcn--");
6275 setup_types(&ctx);
6276
6277 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
6278 ctx.ac.builder = ctx.builder;
6279 ctx.stage = MESA_SHADER_VERTEX;
6280
6281 create_function(&ctx);
6282
6283 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
6284 ac_setup_rings(&ctx);
6285
6286 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
6287 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
6288
6289 nir_foreach_variable(variable, &geom_shader->outputs)
6290 handle_shader_output_decl(&ctx, variable);
6291
6292 ac_gs_copy_shader_emit(&ctx);
6293
6294 LLVMBuildRetVoid(ctx.builder);
6295
6296 ac_llvm_finalize_module(&ctx);
6297
6298 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
6299 MESA_SHADER_VERTEX,
6300 dump_shader, options->supports_spill);
6301 }