src/amd/common/ac_nir_to_llvm.h

   1 /*
   2  * Copyright © 2016 Bas Nieuwenhuizen
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef AC_NIR_TO_LLVM_H
  25 #define AC_NIR_TO_LLVM_H
  26
  27 #include <stdbool.h>
  28 #include "llvm-c/Core.h"
  29 #include "llvm-c/TargetMachine.h"
  30 #include "amd_family.h"
  31 #include "../vulkan/radv_descriptor_set.h"
  32 #include "ac_shader_info.h"
  33 #include "compiler/shader_enums.h"
  34 struct ac_shader_binary;
  35 struct ac_shader_config;
  36 struct nir_shader;
  37 struct radv_pipeline_layout;
  38
  39 struct ac_llvm_context;
  40 struct ac_shader_abi;
  41
  42 struct ac_vs_variant_key {
  43         uint32_t instance_rate_inputs;
  44         uint32_t as_es:1;
  45         uint32_t as_ls:1;
  46         uint32_t export_prim_id:1;
  47 };
  48
  49 struct ac_tes_variant_key {
  50         uint32_t as_es:1;
  51         uint32_t export_prim_id:1;
  52 };
  53
  54 struct ac_tcs_variant_key {
  55         struct ac_vs_variant_key vs_key;
  56         unsigned primitive_mode;
  57         unsigned input_vertices;
  58         uint32_t tes_reads_tess_factors:1;
  59 };
  60
  61 struct ac_fs_variant_key {
  62         uint32_t col_format;
  63         uint32_t is_int8;
  64         uint32_t is_int10;
  65         uint32_t multisample : 1;
  66 };
  67
  68 struct ac_shader_variant_key {
  69         union {
  70                 struct ac_vs_variant_key vs;
  71                 struct ac_fs_variant_key fs;
  72                 struct ac_tes_variant_key tes;
  73                 struct ac_tcs_variant_key tcs;
  74         };
  75         bool has_multiview_view_index;
  76 };
  77
  78 struct ac_nir_compiler_options {
  79         struct radv_pipeline_layout *layout;
  80         struct ac_shader_variant_key key;
  81         bool unsafe_math;
  82         bool supports_spill;
  83         bool clamp_shadow_reference;
  84         enum radeon_family family;
  85         enum chip_class chip_class;
  86 };
  87
  88 struct ac_userdata_info {
  89         int8_t sgpr_idx;
  90         uint8_t num_sgprs;
  91         bool indirect;
  92         uint32_t indirect_offset;
  93 };
  94
  95 enum ac_ud_index {
  96         AC_UD_SCRATCH_RING_OFFSETS = 0,
  97         AC_UD_PUSH_CONSTANTS = 1,
  98         AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
  99         AC_UD_VIEW_INDEX = 3,
 100         AC_UD_SHADER_START = 4,
 101         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 102         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 103         AC_UD_VS_LS_TCS_IN_LAYOUT,
 104         AC_UD_VS_MAX_UD,
 105         AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
 106         AC_UD_PS_MAX_UD,
 107         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 108         AC_UD_CS_MAX_UD,
 109         AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
 110         AC_UD_GS_MAX_UD,
 111         AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
 112         AC_UD_TCS_MAX_UD,
 113         AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
 114         AC_UD_TES_MAX_UD,
 115         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 116 };
 117
 118 /* descriptor index into scratch ring offsets */
 119 #define RING_SCRATCH 0
 120 #define RING_ESGS_VS 1
 121 #define RING_ESGS_GS 2
 122 #define RING_GSVS_VS 3
 123 #define RING_GSVS_GS 4
 124 #define RING_HS_TESS_FACTOR 5
 125 #define RING_HS_TESS_OFFCHIP 6
 126 #define RING_PS_SAMPLE_POSITIONS 7
 127
 128 // Match MAX_SETS from radv_descriptor_set.h
 129 #define AC_UD_MAX_SETS MAX_SETS
 130
 131 struct ac_userdata_locations {
 132         struct ac_userdata_info descriptor_sets[AC_UD_MAX_SETS];
 133         struct ac_userdata_info shader_data[AC_UD_MAX_UD];
 134 };
 135
 136 struct ac_vs_output_info {
 137         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 138         uint8_t clip_dist_mask;
 139         uint8_t cull_dist_mask;
 140         uint8_t param_exports;
 141         bool writes_pointsize;
 142         bool writes_layer;
 143         bool writes_viewport_index;
 144         bool export_prim_id;
 145         uint32_t export_mask;
 146         unsigned pos_exports;
 147 };
 148
 149 struct ac_es_output_info {
 150         uint32_t esgs_itemsize;
 151 };
 152
 153 struct ac_shader_variant_info {
 154         struct ac_userdata_locations user_sgprs_locs;
 155         struct ac_shader_info info;
 156         unsigned num_user_sgprs;
 157         unsigned num_input_sgprs;
 158         unsigned num_input_vgprs;
 159         bool need_indirect_descriptor_sets;
 160         struct {
 161                 struct {
 162                         struct ac_vs_output_info outinfo;
 163                         struct ac_es_output_info es_info;
 164                         unsigned vgpr_comp_cnt;
 165                         bool as_es;
 166                         bool as_ls;
 167                         uint64_t outputs_written;
 168                 } vs;
 169                 struct {
 170                         unsigned num_interp;
 171                         uint32_t input_mask;
 172                         unsigned output_mask;
 173                         uint32_t flat_shaded_mask;
 174                         bool has_pcoord;
 175                         bool can_discard;
 176                         bool writes_z;
 177                         bool writes_stencil;
 178                         bool writes_sample_mask;
 179                         bool early_fragment_test;
 180                         bool writes_memory;
 181                         bool prim_id_input;
 182                         bool layer_input;
 183                 } fs;
 184                 struct {
 185                         unsigned block_size[3];
 186                 } cs;
 187                 struct {
 188                         unsigned vertices_in;
 189                         unsigned vertices_out;
 190                         unsigned output_prim;
 191                         unsigned invocations;
 192                         unsigned gsvs_vertex_size;
 193                         unsigned max_gsvs_emit_size;
 194                         bool uses_prim_id;
 195                 } gs;
 196                 struct {
 197                         bool uses_prim_id;
 198                         unsigned tcs_vertices_out;
 199                         /* Which outputs are actually written */
 200                         uint64_t outputs_written;
 201                         /* Which patch outputs are actually written */
 202                         uint32_t patch_outputs_written;
 203
 204                 } tcs;
 205                 struct {
 206                         struct ac_vs_output_info outinfo;
 207                         struct ac_es_output_info es_info;
 208                         bool as_es;
 209                         unsigned primitive_mode;
 210                         enum gl_tess_spacing spacing;
 211                         bool ccw;
 212                         bool point_mode;
 213                         bool uses_prim_id;
 214                 } tes;
 215         };
 216 };
 217
 218 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
 219                            struct ac_shader_binary *binary,
 220                            struct ac_shader_config *config,
 221                            struct ac_shader_variant_info *shader_info,
 222                            struct nir_shader *const *nir,
 223                            int nir_count,
 224                            const struct ac_nir_compiler_options *options,
 225                            bool dump_shader);
 226
 227 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
 228                               struct nir_shader *geom_shader,
 229                               struct ac_shader_binary *binary,
 230                               struct ac_shader_config *config,
 231                               struct ac_shader_variant_info *shader_info,
 232                               const struct ac_nir_compiler_options *options,
 233                               bool dump_shader);
 234
 235 struct nir_to_llvm_context;
 236 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
 237                       struct nir_shader *nir, struct nir_to_llvm_context *nctx);
 238
 239 #endif /* AC_NIR_TO_LLVM_H */