radv/ac: add tess changes to shader keys/info
[mesa.git] / src / amd / common / ac_nir_to_llvm.h
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef AC_NIR_TO_LLVM_H
25 #define AC_NIR_TO_LLVM_H
26
27 #include <stdbool.h>
28 #include "llvm-c/Core.h"
29 #include "llvm-c/TargetMachine.h"
30 #include "amd_family.h"
31 #include "../vulkan/radv_descriptor_set.h"
32
33 #include "shader_enums.h"
34 struct ac_shader_binary;
35 struct ac_shader_config;
36 struct nir_shader;
37 struct radv_pipeline_layout;
38
39
40 struct ac_vs_variant_key {
41 uint32_t instance_rate_inputs;
42 uint32_t as_es:1;
43 uint32_t as_ls:1;
44 };
45
46 struct ac_tes_variant_key {
47 uint32_t as_es:1;
48 };
49
50 struct ac_tcs_variant_key {
51 unsigned primitive_mode;
52 unsigned input_vertices;
53 };
54
55 struct ac_fs_variant_key {
56 uint32_t col_format;
57 uint32_t is_int8;
58 };
59
60 union ac_shader_variant_key {
61 struct ac_vs_variant_key vs;
62 struct ac_fs_variant_key fs;
63 struct ac_tes_variant_key tes;
64 struct ac_tcs_variant_key tcs;
65 };
66
67 struct ac_nir_compiler_options {
68 struct radv_pipeline_layout *layout;
69 union ac_shader_variant_key key;
70 bool unsafe_math;
71 bool supports_spill;
72 enum radeon_family family;
73 enum chip_class chip_class;
74 };
75
76 struct ac_userdata_info {
77 int8_t sgpr_idx;
78 uint8_t num_sgprs;
79 bool indirect;
80 uint32_t indirect_offset;
81 };
82
83 enum ac_ud_index {
84 AC_UD_SCRATCH_RING_OFFSETS = 0,
85 AC_UD_PUSH_CONSTANTS = 1,
86 AC_UD_SHADER_START = 2,
87 AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
88 AC_UD_VS_BASE_VERTEX_START_INSTANCE,
89 AC_UD_VS_LS_TCS_IN_LAYOUT,
90 AC_UD_VS_MAX_UD,
91 AC_UD_PS_SAMPLE_POS = AC_UD_SHADER_START,
92 AC_UD_PS_MAX_UD,
93 AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
94 AC_UD_CS_MAX_UD,
95 AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_SHADER_START,
96 AC_UD_GS_MAX_UD,
97 AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
98 AC_UD_TCS_MAX_UD,
99 AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
100 AC_UD_TES_MAX_UD,
101 AC_UD_MAX_UD = AC_UD_VS_MAX_UD,
102 };
103
104 /* descriptor index into scratch ring offsets */
105 #define RING_SCRATCH 0
106 #define RING_ESGS_VS 1
107 #define RING_ESGS_GS 2
108 #define RING_GSVS_VS 3
109 #define RING_GSVS_GS 4
110
111 // Match MAX_SETS from radv_descriptor_set.h
112 #define AC_UD_MAX_SETS MAX_SETS
113
114 struct ac_userdata_locations {
115 struct ac_userdata_info descriptor_sets[AC_UD_MAX_SETS];
116 struct ac_userdata_info shader_data[AC_UD_MAX_UD];
117 };
118
119 struct ac_vs_output_info {
120 uint8_t clip_dist_mask;
121 uint8_t cull_dist_mask;
122 bool writes_pointsize;
123 bool writes_layer;
124 bool writes_viewport_index;
125 uint32_t prim_id_output;
126 uint32_t layer_output;
127 uint32_t export_mask;
128 unsigned param_exports;
129 unsigned pos_exports;
130 };
131
132 struct ac_es_output_info {
133 uint32_t esgs_itemsize;
134 };
135
136 struct ac_shader_variant_info {
137 struct ac_userdata_locations user_sgprs_locs;
138 unsigned num_user_sgprs;
139 unsigned num_input_sgprs;
140 unsigned num_input_vgprs;
141
142 union {
143 struct {
144 struct ac_vs_output_info outinfo;
145 struct ac_es_output_info es_info;
146 unsigned vgpr_comp_cnt;
147 bool as_es;
148 bool as_ls;
149 uint64_t outputs_written;
150 } vs;
151 struct {
152 unsigned num_interp;
153 uint32_t input_mask;
154 unsigned output_mask;
155 uint32_t flat_shaded_mask;
156 bool has_pcoord;
157 bool can_discard;
158 bool writes_z;
159 bool writes_stencil;
160 bool writes_sample_mask;
161 bool early_fragment_test;
162 bool writes_memory;
163 bool force_persample;
164 bool prim_id_input;
165 bool layer_input;
166 } fs;
167 struct {
168 unsigned block_size[3];
169 } cs;
170 struct {
171 unsigned vertices_in;
172 unsigned vertices_out;
173 unsigned output_prim;
174 unsigned invocations;
175 unsigned gsvs_vertex_size;
176 unsigned max_gsvs_emit_size;
177 } gs;
178 struct {
179 bool uses_prim_id;
180 unsigned tcs_vertices_out;
181 /* Which outputs are actually written */
182 uint64_t outputs_written;
183 /* Which patch outputs are actually written */
184 uint32_t patch_outputs_written;
185
186 } tcs;
187 struct {
188 struct ac_vs_output_info outinfo;
189 struct ac_es_output_info es_info;
190 bool as_es;
191 unsigned primitive_mode;
192 enum gl_tess_spacing spacing;
193 bool ccw;
194 bool point_mode;
195 bool uses_prim_id;
196 } tes;
197 };
198 };
199
200 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
201 struct ac_shader_binary *binary,
202 struct ac_shader_config *config,
203 struct ac_shader_variant_info *shader_info,
204 struct nir_shader *nir,
205 const struct ac_nir_compiler_options *options,
206 bool dump_shader);
207
208 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
209 struct nir_shader *geom_shader,
210 struct ac_shader_binary *binary,
211 struct ac_shader_config *config,
212 struct ac_shader_variant_info *shader_info,
213 const struct ac_nir_compiler_options *options,
214 bool dump_shader);
215
216 #endif /* AC_NIR_TO_LLVM_H */