src/amd/common/ac_nir_to_llvm.h

   1 /*
   2  * Copyright © 2016 Bas Nieuwenhuizen
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef AC_NIR_TO_LLVM_H
  25 #define AC_NIR_TO_LLVM_H
  26
  27 #include <stdbool.h>
  28 #include "llvm-c/Core.h"
  29 #include "llvm-c/TargetMachine.h"
  30 #include "amd_family.h"
  31 #include "../vulkan/radv_descriptor_set.h"
  32 #include "ac_shader_info.h"
  33 #include "compiler/shader_enums.h"
  34 struct ac_shader_binary;
  35 struct ac_shader_config;
  36 struct nir_shader;
  37 struct nir_variable;
  38 struct radv_pipeline_layout;
  39
  40 struct ac_llvm_context;
  41 struct ac_shader_abi;
  42
  43 struct ac_vs_variant_key {
  44         uint32_t instance_rate_inputs;
  45         uint32_t as_es:1;
  46         uint32_t as_ls:1;
  47         uint32_t export_prim_id:1;
  48 };
  49
  50 struct ac_tes_variant_key {
  51         uint32_t as_es:1;
  52         uint32_t export_prim_id:1;
  53 };
  54
  55 struct ac_tcs_variant_key {
  56         struct ac_vs_variant_key vs_key;
  57         unsigned primitive_mode;
  58         unsigned input_vertices;
  59         uint32_t tes_reads_tess_factors:1;
  60 };
  61
  62 struct ac_fs_variant_key {
  63         uint32_t col_format;
  64         uint8_t log2_ps_iter_samples;
  65         uint8_t log2_num_samples;
  66         uint32_t is_int8;
  67         uint32_t is_int10;
  68         uint32_t multisample : 1;
  69 };
  70
  71 struct ac_shader_variant_key {
  72         union {
  73                 struct ac_vs_variant_key vs;
  74                 struct ac_fs_variant_key fs;
  75                 struct ac_tes_variant_key tes;
  76                 struct ac_tcs_variant_key tcs;
  77         };
  78         bool has_multiview_view_index;
  79 };
  80
  81 struct ac_nir_compiler_options {
  82         struct radv_pipeline_layout *layout;
  83         struct ac_shader_variant_key key;
  84         bool unsafe_math;
  85         bool supports_spill;
  86         bool clamp_shadow_reference;
  87         bool dump_preoptir;
  88         enum radeon_family family;
  89         enum chip_class chip_class;
  90 };
  91
  92 struct ac_userdata_info {
  93         int8_t sgpr_idx;
  94         uint8_t num_sgprs;
  95         bool indirect;
  96         uint32_t indirect_offset;
  97 };
  98
  99 enum ac_ud_index {
 100         AC_UD_SCRATCH_RING_OFFSETS = 0,
 101         AC_UD_PUSH_CONSTANTS = 1,
 102         AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
 103         AC_UD_VIEW_INDEX = 3,
 104         AC_UD_SHADER_START = 4,
 105         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 106         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 107         AC_UD_VS_LS_TCS_IN_LAYOUT,
 108         AC_UD_VS_MAX_UD,
 109         AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
 110         AC_UD_PS_MAX_UD,
 111         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 112         AC_UD_CS_MAX_UD,
 113         AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
 114         AC_UD_GS_MAX_UD,
 115         AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
 116         AC_UD_TCS_MAX_UD,
 117         AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
 118         AC_UD_TES_MAX_UD,
 119         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 120 };
 121
 122 /* Interpolation locations */
 123 #define INTERP_CENTER 0
 124 #define INTERP_CENTROID 1
 125 #define INTERP_SAMPLE 2
 126
 127 /* descriptor index into scratch ring offsets */
 128 #define RING_SCRATCH 0
 129 #define RING_ESGS_VS 1
 130 #define RING_ESGS_GS 2
 131 #define RING_GSVS_VS 3
 132 #define RING_GSVS_GS 4
 133 #define RING_HS_TESS_FACTOR 5
 134 #define RING_HS_TESS_OFFCHIP 6
 135 #define RING_PS_SAMPLE_POSITIONS 7
 136
 137 // Match MAX_SETS from radv_descriptor_set.h
 138 #define AC_UD_MAX_SETS MAX_SETS
 139
 140 struct ac_userdata_locations {
 141         struct ac_userdata_info descriptor_sets[AC_UD_MAX_SETS];
 142         struct ac_userdata_info shader_data[AC_UD_MAX_UD];
 143 };
 144
 145 struct ac_vs_output_info {
 146         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 147         uint8_t clip_dist_mask;
 148         uint8_t cull_dist_mask;
 149         uint8_t param_exports;
 150         bool writes_pointsize;
 151         bool writes_layer;
 152         bool writes_viewport_index;
 153         bool export_prim_id;
 154         unsigned pos_exports;
 155 };
 156
 157 struct ac_es_output_info {
 158         uint32_t esgs_itemsize;
 159 };
 160
 161 struct ac_shader_variant_info {
 162         struct ac_userdata_locations user_sgprs_locs;
 163         struct ac_shader_info info;
 164         unsigned num_user_sgprs;
 165         unsigned num_input_sgprs;
 166         unsigned num_input_vgprs;
 167         unsigned private_mem_vgprs;
 168         bool need_indirect_descriptor_sets;
 169         struct {
 170                 struct {
 171                         struct ac_vs_output_info outinfo;
 172                         struct ac_es_output_info es_info;
 173                         unsigned vgpr_comp_cnt;
 174                         bool as_es;
 175                         bool as_ls;
 176                         uint64_t outputs_written;
 177                 } vs;
 178                 struct {
 179                         unsigned num_interp;
 180                         uint32_t input_mask;
 181                         uint32_t flat_shaded_mask;
 182                         bool can_discard;
 183                         bool early_fragment_test;
 184                 } fs;
 185                 struct {
 186                         unsigned block_size[3];
 187                 } cs;
 188                 struct {
 189                         unsigned vertices_in;
 190                         unsigned vertices_out;
 191                         unsigned output_prim;
 192                         unsigned invocations;
 193                         unsigned gsvs_vertex_size;
 194                         unsigned max_gsvs_emit_size;
 195                         unsigned es_type; /* GFX9: VS or TES */
 196                 } gs;
 197                 struct {
 198                         unsigned tcs_vertices_out;
 199                         /* Which outputs are actually written */
 200                         uint64_t outputs_written;
 201                         /* Which patch outputs are actually written */
 202                         uint32_t patch_outputs_written;
 203
 204                 } tcs;
 205                 struct {
 206                         struct ac_vs_output_info outinfo;
 207                         struct ac_es_output_info es_info;
 208                         bool as_es;
 209                         unsigned primitive_mode;
 210                         enum gl_tess_spacing spacing;
 211                         bool ccw;
 212                         bool point_mode;
 213                 } tes;
 214         };
 215 };
 216
 217 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
 218                            struct ac_shader_binary *binary,
 219                            struct ac_shader_config *config,
 220                            struct ac_shader_variant_info *shader_info,
 221                            struct nir_shader *const *nir,
 222                            int nir_count,
 223                            const struct ac_nir_compiler_options *options,
 224                            bool dump_shader);
 225
 226 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
 227                               struct nir_shader *geom_shader,
 228                               struct ac_shader_binary *binary,
 229                               struct ac_shader_config *config,
 230                               struct ac_shader_variant_info *shader_info,
 231                               const struct ac_nir_compiler_options *options,
 232                               bool dump_shader);
 233
 234 void ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class);
 235
 236 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
 237                       struct nir_shader *nir);
 238
 239 void
 240 ac_handle_shader_output_decl(struct ac_llvm_context *ctx,
 241                              struct ac_shader_abi *abi,
 242                              struct nir_shader *nir,
 243                              struct nir_variable *variable,
 244                              gl_shader_stage stage);
 245
 246 bool ac_lower_subgroups(struct nir_shader *shader);
 247
 248 #endif /* AC_NIR_TO_LLVM_H */