radv: rework vertex/export shader output handling
[mesa.git] / src / amd / common / ac_nir_to_llvm.h
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef AC_NIR_TO_LLVM_H
25 #define AC_NIR_TO_LLVM_H
26
27 #include <stdbool.h>
28 #include "llvm-c/Core.h"
29 #include "llvm-c/TargetMachine.h"
30 #include "amd_family.h"
31 #include "../vulkan/radv_descriptor_set.h"
32
33 struct ac_shader_binary;
34 struct ac_shader_config;
35 struct nir_shader;
36 struct radv_pipeline_layout;
37
38
39 struct ac_vs_variant_key {
40 uint32_t instance_rate_inputs;
41 uint32_t as_es:1;
42 };
43
44 struct ac_fs_variant_key {
45 uint32_t col_format;
46 uint32_t is_int8;
47 };
48
49 union ac_shader_variant_key {
50 struct ac_vs_variant_key vs;
51 struct ac_fs_variant_key fs;
52 };
53
54 struct ac_nir_compiler_options {
55 struct radv_pipeline_layout *layout;
56 union ac_shader_variant_key key;
57 bool unsafe_math;
58 bool supports_spill;
59 enum radeon_family family;
60 enum chip_class chip_class;
61 };
62
63 struct ac_userdata_info {
64 int8_t sgpr_idx;
65 uint8_t num_sgprs;
66 bool indirect;
67 uint32_t indirect_offset;
68 };
69
70 enum ac_ud_index {
71 AC_UD_SCRATCH_RING_OFFSETS = 0,
72 AC_UD_PUSH_CONSTANTS = 1,
73 AC_UD_SHADER_START = 2,
74 AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
75 AC_UD_VS_BASE_VERTEX_START_INSTANCE,
76 AC_UD_VS_MAX_UD,
77 AC_UD_PS_SAMPLE_POS = AC_UD_SHADER_START,
78 AC_UD_PS_MAX_UD,
79 AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
80 AC_UD_CS_MAX_UD,
81 AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_SHADER_START,
82 AC_UD_GS_MAX_UD,
83 AC_UD_MAX_UD = AC_UD_VS_MAX_UD,
84 };
85
86 // Match MAX_SETS from radv_descriptor_set.h
87 #define AC_UD_MAX_SETS MAX_SETS
88
89 struct ac_userdata_locations {
90 struct ac_userdata_info descriptor_sets[AC_UD_MAX_SETS];
91 struct ac_userdata_info shader_data[AC_UD_MAX_UD];
92 };
93
94 struct ac_vs_output_info {
95 uint8_t clip_dist_mask;
96 uint8_t cull_dist_mask;
97 bool writes_pointsize;
98 bool writes_layer;
99 bool writes_viewport_index;
100 uint32_t prim_id_output;
101 uint32_t layer_output;
102 uint32_t export_mask;
103 unsigned param_exports;
104 unsigned pos_exports;
105 };
106
107 struct ac_es_output_info {
108 uint32_t esgs_itemsize;
109 };
110
111 struct ac_shader_variant_info {
112 struct ac_userdata_locations user_sgprs_locs;
113 unsigned num_user_sgprs;
114 unsigned num_input_sgprs;
115 unsigned num_input_vgprs;
116 union {
117 struct {
118 struct ac_vs_output_info outinfo;
119 struct ac_es_output_info es_info;
120 unsigned vgpr_comp_cnt;
121 bool as_es;
122 } vs;
123 struct {
124 unsigned num_interp;
125 uint32_t input_mask;
126 unsigned output_mask;
127 uint32_t flat_shaded_mask;
128 bool has_pcoord;
129 bool can_discard;
130 bool writes_z;
131 bool writes_stencil;
132 bool writes_sample_mask;
133 bool early_fragment_test;
134 bool writes_memory;
135 bool force_persample;
136 bool prim_id_input;
137 bool layer_input;
138 } fs;
139 struct {
140 unsigned block_size[3];
141 } cs;
142 struct {
143 unsigned vertices_in;
144 unsigned vertices_out;
145 unsigned output_prim;
146 unsigned invocations;
147 unsigned gsvs_vertex_size;
148 unsigned max_gsvs_emit_size;
149 } gs;
150 };
151 };
152
153 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
154 struct ac_shader_binary *binary,
155 struct ac_shader_config *config,
156 struct ac_shader_variant_info *shader_info,
157 struct nir_shader *nir,
158 const struct ac_nir_compiler_options *options,
159 bool dump_shader);
160
161 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
162 struct nir_shader *geom_shader,
163 struct ac_shader_binary *binary,
164 struct ac_shader_config *config,
165 struct ac_shader_variant_info *shader_info,
166 const struct ac_nir_compiler_options *options,
167 bool dump_shader);
168
169 #endif /* AC_NIR_TO_LLVM_H */