projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: add support for Vega12
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static unsigned get_first(unsigned x, unsigned y)
53 {
54 return x;
55 }
56
57 static void addrlib_family_rev_id(enum radeon_family family,
58 unsigned *addrlib_family,
59 unsigned *addrlib_revid)
60 {
61 switch (family) {
62 case CHIP_TAHITI:
63 *addrlib_family = FAMILY_SI;
64 *addrlib_revid = get_first(AMDGPU_TAHITI_RANGE);
65 break;
66 case CHIP_PITCAIRN:
67 *addrlib_family = FAMILY_SI;
68 *addrlib_revid = get_first(AMDGPU_PITCAIRN_RANGE);
69 break;
70 case CHIP_VERDE:
71 *addrlib_family = FAMILY_SI;
72 *addrlib_revid = get_first(AMDGPU_CAPEVERDE_RANGE);
73 break;
74 case CHIP_OLAND:
75 *addrlib_family = FAMILY_SI;
76 *addrlib_revid = get_first(AMDGPU_OLAND_RANGE);
77 break;
78 case CHIP_HAINAN:
79 *addrlib_family = FAMILY_SI;
80 *addrlib_revid = get_first(AMDGPU_HAINAN_RANGE);
81 break;
82 case CHIP_BONAIRE:
83 *addrlib_family = FAMILY_CI;
84 *addrlib_revid = get_first(AMDGPU_BONAIRE_RANGE);
85 break;
86 case CHIP_KAVERI:
87 *addrlib_family = FAMILY_KV;
88 *addrlib_revid = get_first(AMDGPU_SPECTRE_RANGE);
89 break;
90 case CHIP_KABINI:
91 *addrlib_family = FAMILY_KV;
92 *addrlib_revid = get_first(AMDGPU_KALINDI_RANGE);
93 break;
94 case CHIP_HAWAII:
95 *addrlib_family = FAMILY_CI;
96 *addrlib_revid = get_first(AMDGPU_HAWAII_RANGE);
97 break;
98 case CHIP_MULLINS:
99 *addrlib_family = FAMILY_KV;
100 *addrlib_revid = get_first(AMDGPU_GODAVARI_RANGE);
101 break;
102 case CHIP_TONGA:
103 *addrlib_family = FAMILY_VI;
104 *addrlib_revid = get_first(AMDGPU_TONGA_RANGE);
105 break;
106 case CHIP_ICELAND:
107 *addrlib_family = FAMILY_VI;
108 *addrlib_revid = get_first(AMDGPU_ICELAND_RANGE);
109 break;
110 case CHIP_CARRIZO:
111 *addrlib_family = FAMILY_CZ;
112 *addrlib_revid = get_first(AMDGPU_CARRIZO_RANGE);
113 break;
114 case CHIP_STONEY:
115 *addrlib_family = FAMILY_CZ;
116 *addrlib_revid = get_first(AMDGPU_STONEY_RANGE);
117 break;
118 case CHIP_FIJI:
119 *addrlib_family = FAMILY_VI;
120 *addrlib_revid = get_first(AMDGPU_FIJI_RANGE);
121 break;
122 case CHIP_POLARIS10:
123 *addrlib_family = FAMILY_VI;
124 *addrlib_revid = get_first(AMDGPU_POLARIS10_RANGE);
125 break;
126 case CHIP_POLARIS11:
127 *addrlib_family = FAMILY_VI;
128 *addrlib_revid = get_first(AMDGPU_POLARIS11_RANGE);
129 break;
130 case CHIP_POLARIS12:
131 *addrlib_family = FAMILY_VI;
132 *addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE);
133 break;
134 case CHIP_VEGA10:
135 *addrlib_family = FAMILY_AI;
136 *addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
137 break;
138 case CHIP_VEGA12:
139 *addrlib_family = FAMILY_AI;
140 *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
141 break;
142 case CHIP_RAVEN:
143 *addrlib_family = FAMILY_RV;
144 *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
145 break;
146 default:
147 fprintf(stderr, "amdgpu: Unknown family.\n");
148 }
149 }
150
151 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
152 {
153 return malloc(pInput->sizeInBytes);
154 }
155
156 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
157 {
158 free(pInput->pVirtAddr);
159 return ADDR_OK;
160 }
161
162 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
163 const struct amdgpu_gpu_info *amdinfo,
164 uint64_t *max_alignment)
165 {
166 ADDR_CREATE_INPUT addrCreateInput = {0};
167 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
168 ADDR_REGISTER_VALUE regValue = {0};
169 ADDR_CREATE_FLAGS createFlags = {{0}};
170 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
171 ADDR_E_RETURNCODE addrRet;
172
173 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
174 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
175
176 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
177 createFlags.value = 0;
178
179 addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
180 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
181 return NULL;
182
183 if (addrCreateInput.chipFamily >= FAMILY_AI) {
184 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
185 regValue.blockVarSizeLog2 = 0;
186 } else {
187 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
188 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
189
190 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
191 regValue.pTileConfig = amdinfo->gb_tile_mode;
192 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
193 if (addrCreateInput.chipFamily == FAMILY_SI) {
194 regValue.pMacroTileConfig = NULL;
195 regValue.noOfMacroEntries = 0;
196 } else {
197 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
198 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
199 }
200
201 createFlags.useTileIndex = 1;
202 createFlags.useHtileSliceAlign = 1;
203
204 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
205 }
206
207 addrCreateInput.callbacks.allocSysMem = allocSysMem;
208 addrCreateInput.callbacks.freeSysMem = freeSysMem;
209 addrCreateInput.callbacks.debugPrint = 0;
210 addrCreateInput.createFlags = createFlags;
211 addrCreateInput.regValue = regValue;
212
213 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
214 if (addrRet != ADDR_OK)
215 return NULL;
216
217 if (max_alignment) {
218 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
219 if (addrRet == ADDR_OK){
220 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
221 }
222 }
223 return addrCreateOutput.hLib;
224 }
225
226 static int surf_config_sanity(const struct ac_surf_config *config)
227 {
228 /* all dimension must be at least 1 ! */
229 if (!config->info.width || !config->info.height || !config->info.depth ||
230 !config->info.array_size || !config->info.levels)
231 return -EINVAL;
232
233 switch (config->info.samples) {
234 case 0:
235 case 1:
236 case 2:
237 case 4:
238 case 8:
239 break;
240 default:
241 return -EINVAL;
242 }
243
244 if (config->is_3d && config->info.array_size > 1)
245 return -EINVAL;
246 if (config->is_cube && config->info.depth > 1)
247 return -EINVAL;
248
249 return 0;
250 }
251
252 static int gfx6_compute_level(ADDR_HANDLE addrlib,
253 const struct ac_surf_config *config,
254 struct radeon_surf *surf, bool is_stencil,
255 unsigned level, bool compressed,
256 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
257 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
258 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
259 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
260 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
261 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
262 {
263 struct legacy_surf_level *surf_level;
264 ADDR_E_RETURNCODE ret;
265
266 AddrSurfInfoIn->mipLevel = level;
267 AddrSurfInfoIn->width = u_minify(config->info.width, level);
268 AddrSurfInfoIn->height = u_minify(config->info.height, level);
269
270 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
271 * because GFX9 needs linear alignment of 256 bytes.
272 */
273 if (config->info.levels == 1 &&
274 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
275 AddrSurfInfoIn->bpp) {
276 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
277
278 assert(util_is_power_of_two(AddrSurfInfoIn->bpp));
279 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
280 }
281
282 if (config->is_3d)
283 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
284 else if (config->is_cube)
285 AddrSurfInfoIn->numSlices = 6;
286 else
287 AddrSurfInfoIn->numSlices = config->info.array_size;
288
289 if (level > 0) {
290 /* Set the base level pitch. This is needed for calculation
291 * of non-zero levels. */
292 if (is_stencil)
293 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
294 else
295 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
296
297 /* Convert blocks to pixels for compressed formats. */
298 if (compressed)
299 AddrSurfInfoIn->basePitch *= surf->blk_w;
300 }
301
302 ret = AddrComputeSurfaceInfo(addrlib,
303 AddrSurfInfoIn,
304 AddrSurfInfoOut);
305 if (ret != ADDR_OK) {
306 return ret;
307 }
308
309 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
310 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
311 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
312 surf_level->nblk_x = AddrSurfInfoOut->pitch;
313 surf_level->nblk_y = AddrSurfInfoOut->height;
314
315 switch (AddrSurfInfoOut->tileMode) {
316 case ADDR_TM_LINEAR_ALIGNED:
317 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
318 break;
319 case ADDR_TM_1D_TILED_THIN1:
320 surf_level->mode = RADEON_SURF_MODE_1D;
321 break;
322 case ADDR_TM_2D_TILED_THIN1:
323 surf_level->mode = RADEON_SURF_MODE_2D;
324 break;
325 default:
326 assert(0);
327 }
328
329 if (is_stencil)
330 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
331 else
332 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
333
334 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
335
336 /* Clear DCC fields at the beginning. */
337 surf_level->dcc_offset = 0;
338
339 /* The previous level's flag tells us if we can use DCC for this level. */
340 if (AddrSurfInfoIn->flags.dccCompatible &&
341 (level == 0 || AddrDccOut->subLvlCompressible)) {
342 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
343 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
344 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
345 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
346 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
347
348 ret = AddrComputeDccInfo(addrlib,
349 AddrDccIn,
350 AddrDccOut);
351
352 if (ret == ADDR_OK) {
353 surf_level->dcc_offset = surf->dcc_size;
354 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
355 surf->num_dcc_levels = level + 1;
356 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
357 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
358 }
359 }
360
361 /* TC-compatible HTILE. */
362 if (!is_stencil &&
363 AddrSurfInfoIn->flags.depth &&
364 surf_level->mode == RADEON_SURF_MODE_2D &&
365 level == 0) {
366 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
367 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
368 AddrHtileIn->height = AddrSurfInfoOut->height;
369 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
370 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
371 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
372 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
373 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
374 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
375
376 ret = AddrComputeHtileInfo(addrlib,
377 AddrHtileIn,
378 AddrHtileOut);
379
380 if (ret == ADDR_OK) {
381 surf->htile_size = AddrHtileOut->htileBytes;
382 surf->htile_slice_size = AddrHtileOut->sliceSize;
383 surf->htile_alignment = AddrHtileOut->baseAlign;
384 }
385 }
386
387 return 0;
388 }
389
390 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
391 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
392
393 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
394 const struct radeon_info *info)
395 {
396 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
397
398 if (info->chip_class >= CIK)
399 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
400 else
401 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
402 }
403
404 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
405 {
406 unsigned index, tileb;
407
408 tileb = 8 * 8 * surf->bpe;
409 tileb = MIN2(surf->u.legacy.tile_split, tileb);
410
411 for (index = 0; tileb > 64; index++)
412 tileb >>= 1;
413
414 assert(index < 16);
415 return index;
416 }
417
418 /**
419 * This must be called after the first level is computed.
420 *
421 * Copy surface-global settings like pipe/bank config from level 0 surface
422 * computation, and compute tile swizzle.
423 */
424 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
425 const struct radeon_info *info,
426 const struct ac_surf_config *config,
427 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
428 struct radeon_surf *surf)
429 {
430 surf->surf_alignment = csio->baseAlign;
431 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
432 gfx6_set_micro_tile_mode(surf, info);
433
434 /* For 2D modes only. */
435 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
436 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
437 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
438 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
439 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
440 surf->u.legacy.num_banks = csio->pTileInfo->banks;
441 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
442 } else {
443 surf->u.legacy.macro_tile_index = 0;
444 }
445
446 /* Compute tile swizzle. */
447 /* TODO: fix tile swizzle with mipmapping for SI */
448 if ((info->chip_class >= CIK || config->info.levels == 1) &&
449 config->info.surf_index &&
450 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
451 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
452 (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
453 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
454 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
455
456 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
457 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
458
459 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
460 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
461 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
462 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
463 AddrBaseSwizzleIn.tileMode = csio->tileMode;
464
465 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
466 &AddrBaseSwizzleOut);
467 if (r != ADDR_OK)
468 return r;
469
470 assert(AddrBaseSwizzleOut.tileSwizzle <=
471 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
472 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
473 }
474 return 0;
475 }
476
477 /**
478 * Fill in the tiling information in \p surf based on the given surface config.
479 *
480 * The following fields of \p surf must be initialized by the caller:
481 * blk_w, blk_h, bpe, flags.
482 */
483 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
484 const struct radeon_info *info,
485 const struct ac_surf_config *config,
486 enum radeon_surf_mode mode,
487 struct radeon_surf *surf)
488 {
489 unsigned level;
490 bool compressed;
491 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
492 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
493 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
494 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
495 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
496 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
497 ADDR_TILEINFO AddrTileInfoIn = {0};
498 ADDR_TILEINFO AddrTileInfoOut = {0};
499 int r;
500
501 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
502 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
503 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
504 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
505 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
506 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
507 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
508
509 compressed = surf->blk_w == 4 && surf->blk_h == 4;
510
511 /* MSAA and FMASK require 2D tiling. */
512 if (config->info.samples > 1 ||
513 (surf->flags & RADEON_SURF_FMASK))
514 mode = RADEON_SURF_MODE_2D;
515
516 /* DB doesn't support linear layouts. */
517 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
518 mode < RADEON_SURF_MODE_1D)
519 mode = RADEON_SURF_MODE_1D;
520
521 /* Set the requested tiling mode. */
522 switch (mode) {
523 case RADEON_SURF_MODE_LINEAR_ALIGNED:
524 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
525 break;
526 case RADEON_SURF_MODE_1D:
527 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
528 break;
529 case RADEON_SURF_MODE_2D:
530 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
531 break;
532 default:
533 assert(0);
534 }
535
536 /* The format must be set correctly for the allocation of compressed
537 * textures to work. In other cases, setting the bpp is sufficient.
538 */
539 if (compressed) {
540 switch (surf->bpe) {
541 case 8:
542 AddrSurfInfoIn.format = ADDR_FMT_BC1;
543 break;
544 case 16:
545 AddrSurfInfoIn.format = ADDR_FMT_BC3;
546 break;
547 default:
548 assert(0);
549 }
550 }
551 else {
552 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
553 }
554
555 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
556 config->info.samples ? config->info.samples : 1;
557 AddrSurfInfoIn.tileIndex = -1;
558
559 /* Set the micro tile type. */
560 if (surf->flags & RADEON_SURF_SCANOUT)
561 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
562 else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
563 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
564 else
565 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
566
567 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
568 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
569 AddrSurfInfoIn.flags.cube = config->is_cube;
570 AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
571 AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
572 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
573 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
574
575 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
576 * requested, because TC-compatible HTILE requires 2D tiling.
577 */
578 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
579 !AddrSurfInfoIn.flags.fmask &&
580 config->info.samples <= 1 &&
581 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
582
583 /* DCC notes:
584 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
585 * with samples >= 4.
586 * - Mipmapped array textures have low performance (discovered by a closed
587 * driver team).
588 */
589 AddrSurfInfoIn.flags.dccCompatible =
590 info->chip_class >= VI &&
591 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
592 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
593 !compressed &&
594 ((config->info.array_size == 1 && config->info.depth == 1) ||
595 config->info.levels == 1);
596
597 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
598 AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
599
600 /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
601 * for Z and stencil. This can cause a number of problems which we work
602 * around here:
603 *
604 * - a depth part that is incompatible with mipmapped texturing
605 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
606 * incorrect tiling applied to the stencil part, stencil buffer
607 * memory accesses that go out of bounds) even without mipmapping
608 *
609 * Some piglit tests that are prone to different types of related
610 * failures:
611 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
612 * ./bin/framebuffer-blit-levels {draw,read} stencil
613 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
614 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
615 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
616 */
617 int stencil_tile_idx = -1;
618
619 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
620 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
621 /* Compute stencilTileIdx that is compatible with the (depth)
622 * tileIdx. This degrades the depth surface if necessary to
623 * ensure that a matching stencilTileIdx exists. */
624 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
625
626 /* Keep the depth mip-tail compatible with texturing. */
627 AddrSurfInfoIn.flags.noStencil = 1;
628 }
629
630 /* Set preferred macrotile parameters. This is usually required
631 * for shared resources. This is for 2D tiling only. */
632 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
633 surf->u.legacy.bankw && surf->u.legacy.bankh &&
634 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
635 assert(!(surf->flags & RADEON_SURF_FMASK));
636
637 /* If any of these parameters are incorrect, the calculation
638 * will fail. */
639 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
640 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
641 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
642 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
643 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
644 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
645 AddrSurfInfoIn.flags.opt4Space = 0;
646 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
647
648 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
649 * the tile index, because we are expected to know it if
650 * we know the other parameters.
651 *
652 * This is something that can easily be fixed in Addrlib.
653 * For now, just figure it out here.
654 * Note that only 2D_TILE_THIN1 is handled here.
655 */
656 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
657 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
658
659 if (info->chip_class == SI) {
660 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
661 if (surf->bpe == 2)
662 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
663 else
664 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
665 } else {
666 if (surf->bpe == 1)
667 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
668 else if (surf->bpe == 2)
669 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
670 else if (surf->bpe == 4)
671 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
672 else
673 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
674 }
675 } else {
676 /* CIK - VI */
677 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
678 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
679 else
680 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
681
682 /* Addrlib doesn't set this if tileIndex is forced like above. */
683 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
684 }
685 }
686
687 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
688 surf->num_dcc_levels = 0;
689 surf->surf_size = 0;
690 surf->dcc_size = 0;
691 surf->dcc_alignment = 1;
692 surf->htile_size = 0;
693 surf->htile_slice_size = 0;
694 surf->htile_alignment = 1;
695
696 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
697 !(surf->flags & RADEON_SURF_ZBUFFER);
698
699 /* Calculate texture layout information. */
700 if (!only_stencil) {
701 for (level = 0; level < config->info.levels; level++) {
702 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
703 &AddrSurfInfoIn, &AddrSurfInfoOut,
704 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
705 if (r)
706 return r;
707
708 if (level > 0)
709 continue;
710
711 /* Check that we actually got a TC-compatible HTILE if
712 * we requested it (only for level 0, since we're not
713 * supporting HTILE on higher mip levels anyway). */
714 assert(AddrSurfInfoOut.tcCompatible ||
715 !AddrSurfInfoIn.flags.tcCompatible ||
716 AddrSurfInfoIn.flags.matchStencilTileCfg);
717
718 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
719 if (!AddrSurfInfoOut.tcCompatible) {
720 AddrSurfInfoIn.flags.tcCompatible = 0;
721 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
722 }
723
724 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
725 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
726 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
727
728 assert(stencil_tile_idx >= 0);
729 }
730
731 r = gfx6_surface_settings(addrlib, info, config,
732 &AddrSurfInfoOut, surf);
733 if (r)
734 return r;
735 }
736 }
737
738 /* Calculate texture layout information for stencil. */
739 if (surf->flags & RADEON_SURF_SBUFFER) {
740 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
741 AddrSurfInfoIn.bpp = 8;
742 AddrSurfInfoIn.flags.depth = 0;
743 AddrSurfInfoIn.flags.stencil = 1;
744 AddrSurfInfoIn.flags.tcCompatible = 0;
745 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
746 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
747
748 for (level = 0; level < config->info.levels; level++) {
749 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
750 &AddrSurfInfoIn, &AddrSurfInfoOut,
751 &AddrDccIn, &AddrDccOut,
752 NULL, NULL);
753 if (r)
754 return r;
755
756 /* DB uses the depth pitch for both stencil and depth. */
757 if (!only_stencil) {
758 if (surf->u.legacy.stencil_level[level].nblk_x !=
759 surf->u.legacy.level[level].nblk_x)
760 surf->u.legacy.stencil_adjusted = true;
761 } else {
762 surf->u.legacy.level[level].nblk_x =
763 surf->u.legacy.stencil_level[level].nblk_x;
764 }
765
766 if (level == 0) {
767 if (only_stencil) {
768 r = gfx6_surface_settings(addrlib, info, config,
769 &AddrSurfInfoOut, surf);
770 if (r)
771 return r;
772 }
773
774 /* For 2D modes only. */
775 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
776 surf->u.legacy.stencil_tile_split =
777 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
778 }
779 }
780 }
781 }
782
783 /* Recalculate the whole DCC miptree size including disabled levels.
784 * This is what addrlib does, but calling addrlib would be a lot more
785 * complicated.
786 */
787 if (surf->dcc_size && config->info.levels > 1) {
788 /* The smallest miplevels that are never compressed by DCC
789 * still read the DCC buffer via TC if the base level uses DCC,
790 * and for some reason the DCC buffer needs to be larger if
791 * the miptree uses non-zero tile_swizzle. Otherwise there are
792 * VM faults.
793 *
794 * "dcc_alignment * 4" was determined by trial and error.
795 */
796 surf->dcc_size = align64(surf->surf_size >> 8,
797 surf->dcc_alignment * 4);
798 }
799
800 /* Make sure HTILE covers the whole miptree, because the shader reads
801 * TC-compatible HTILE even for levels where it's disabled by DB.
802 */
803 if (surf->htile_size && config->info.levels > 1)
804 surf->htile_size *= 2;
805
806 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
807 surf->is_displayable = surf->is_linear ||
808 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
809 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
810 return 0;
811 }
812
813 /* This is only called when expecting a tiled layout. */
814 static int
815 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
816 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
817 bool is_fmask, AddrSwizzleMode *swizzle_mode)
818 {
819 ADDR_E_RETURNCODE ret;
820 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
821 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
822
823 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
824 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
825
826 sin.flags = in->flags;
827 sin.resourceType = in->resourceType;
828 sin.format = in->format;
829 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
830 /* TODO: We could allow some of these: */
831 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
832 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
833 sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
834 sin.bpp = in->bpp;
835 sin.width = in->width;
836 sin.height = in->height;
837 sin.numSlices = in->numSlices;
838 sin.numMipLevels = in->numMipLevels;
839 sin.numSamples = in->numSamples;
840 sin.numFrags = in->numFrags;
841
842 if (is_fmask) {
843 sin.flags.color = 0;
844 sin.flags.fmask = 1;
845 }
846
847 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
848 if (ret != ADDR_OK)
849 return ret;
850
851 *swizzle_mode = sout.swizzleMode;
852 return 0;
853 }
854
855 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
856 const struct ac_surf_config *config,
857 struct radeon_surf *surf, bool compressed,
858 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
859 {
860 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
861 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
862 ADDR_E_RETURNCODE ret;
863
864 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
865 out.pMipInfo = mip_info;
866
867 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
868 if (ret != ADDR_OK)
869 return ret;
870
871 if (in->flags.stencil) {
872 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
873 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
874 out.mipChainPitch - 1;
875 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
876 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
877 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
878 return 0;
879 }
880
881 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
882 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
883 out.mipChainPitch - 1;
884
885 /* CMASK fast clear uses these even if FMASK isn't allocated.
886 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
887 */
888 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
889 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
890
891 surf->u.gfx9.surf_slice_size = out.sliceSize;
892 surf->u.gfx9.surf_pitch = out.pitch;
893 surf->u.gfx9.surf_height = out.height;
894 surf->surf_size = out.surfSize;
895 surf->surf_alignment = out.baseAlign;
896
897 if (in->swizzleMode == ADDR_SW_LINEAR) {
898 for (unsigned i = 0; i < in->numMipLevels; i++)
899 surf->u.gfx9.offset[i] = mip_info[i].offset;
900 }
901
902 if (in->flags.depth) {
903 assert(in->swizzleMode != ADDR_SW_LINEAR);
904
905 /* HTILE */
906 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
907 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
908
909 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
910 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
911
912 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
913 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
914 hin.depthFlags = in->flags;
915 hin.swizzleMode = in->swizzleMode;
916 hin.unalignedWidth = in->width;
917 hin.unalignedHeight = in->height;
918 hin.numSlices = in->numSlices;
919 hin.numMipLevels = in->numMipLevels;
920
921 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
922 if (ret != ADDR_OK)
923 return ret;
924
925 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
926 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
927 surf->htile_size = hout.htileBytes;
928 surf->htile_slice_size = hout.sliceSize;
929 surf->htile_alignment = hout.baseAlign;
930 } else {
931 /* Compute tile swizzle for the color surface.
932 * All *_X and *_T modes can use the swizzle.
933 */
934 if (config->info.surf_index &&
935 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
936 !out.mipChainInTail &&
937 !(surf->flags & RADEON_SURF_SHAREABLE) &&
938 (in->numSamples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
939 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
940 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
941
942 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
943 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
944
945 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
946 xin.flags = in->flags;
947 xin.swizzleMode = in->swizzleMode;
948 xin.resourceType = in->resourceType;
949 xin.format = in->format;
950 xin.numSamples = in->numSamples;
951 xin.numFrags = in->numFrags;
952
953 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
954 if (ret != ADDR_OK)
955 return ret;
956
957 assert(xout.pipeBankXor <=
958 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
959 surf->tile_swizzle = xout.pipeBankXor;
960 }
961
962 /* DCC */
963 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
964 !compressed &&
965 in->swizzleMode != ADDR_SW_LINEAR) {
966 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
967 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
968 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
969
970 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
971 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
972 dout.pMipInfo = meta_mip_info;
973
974 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
975 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
976 din.colorFlags = in->flags;
977 din.resourceType = in->resourceType;
978 din.swizzleMode = in->swizzleMode;
979 din.bpp = in->bpp;
980 din.unalignedWidth = in->width;
981 din.unalignedHeight = in->height;
982 din.numSlices = in->numSlices;
983 din.numFrags = in->numFrags;
984 din.numMipLevels = in->numMipLevels;
985 din.dataSurfaceSize = out.surfSize;
986
987 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
988 if (ret != ADDR_OK)
989 return ret;
990
991 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
992 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
993 surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
994 surf->dcc_size = dout.dccRamSize;
995 surf->dcc_alignment = dout.dccRamBaseAlign;
996 surf->num_dcc_levels = in->numMipLevels;
997
998 /* Disable DCC for levels that are in the mip tail.
999 *
1000 * There are two issues that this is intended to
1001 * address:
1002 *
1003 * 1. Multiple mip levels may share a cache line. This
1004 * can lead to corruption when switching between
1005 * rendering to different mip levels because the
1006 * RBs don't maintain coherency.
1007 *
1008 * 2. Texturing with metadata after rendering sometimes
1009 * fails with corruption, probably for a similar
1010 * reason.
1011 *
1012 * Working around these issues for all levels in the
1013 * mip tail may be overly conservative, but it's what
1014 * Vulkan does.
1015 *
1016 * Alternative solutions that also work but are worse:
1017 * - Disable DCC entirely.
1018 * - Flush TC L2 after rendering.
1019 */
1020 for (unsigned i = 0; i < in->numMipLevels; i++) {
1021 if (meta_mip_info[i].inMiptail) {
1022 surf->num_dcc_levels = i;
1023 break;
1024 }
1025 }
1026
1027 if (!surf->num_dcc_levels)
1028 surf->dcc_size = 0;
1029 }
1030
1031 /* FMASK */
1032 if (in->numSamples > 1) {
1033 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1034 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1035
1036 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1037 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1038
1039 ret = gfx9_get_preferred_swizzle_mode(addrlib, in, true, &fin.swizzleMode);
1040 if (ret != ADDR_OK)
1041 return ret;
1042
1043 fin.unalignedWidth = in->width;
1044 fin.unalignedHeight = in->height;
1045 fin.numSlices = in->numSlices;
1046 fin.numSamples = in->numSamples;
1047 fin.numFrags = in->numFrags;
1048
1049 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1050 if (ret != ADDR_OK)
1051 return ret;
1052
1053 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1054 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1055 surf->u.gfx9.fmask_size = fout.fmaskBytes;
1056 surf->u.gfx9.fmask_alignment = fout.baseAlign;
1057
1058 /* Compute tile swizzle for the FMASK surface. */
1059 if (config->info.fmask_surf_index &&
1060 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1061 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1062 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1063 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1064
1065 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1066 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1067
1068 /* This counter starts from 1 instead of 0. */
1069 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1070 xin.flags = in->flags;
1071 xin.swizzleMode = in->swizzleMode;
1072 xin.resourceType = in->resourceType;
1073 xin.format = in->format;
1074 xin.numSamples = in->numSamples;
1075 xin.numFrags = in->numFrags;
1076
1077 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1078 if (ret != ADDR_OK)
1079 return ret;
1080
1081 assert(xout.pipeBankXor <=
1082 u_bit_consecutive(0, sizeof(surf->u.gfx9.fmask_tile_swizzle) * 8));
1083 surf->u.gfx9.fmask_tile_swizzle = xout.pipeBankXor;
1084 }
1085 }
1086
1087 /* CMASK */
1088 if (in->swizzleMode != ADDR_SW_LINEAR) {
1089 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1090 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1091
1092 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1093 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1094
1095 if (in->numSamples) {
1096 /* FMASK is always aligned. */
1097 cin.cMaskFlags.pipeAligned = 1;
1098 cin.cMaskFlags.rbAligned = 1;
1099 } else {
1100 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1101 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1102 }
1103 cin.colorFlags = in->flags;
1104 cin.resourceType = in->resourceType;
1105 cin.unalignedWidth = in->width;
1106 cin.unalignedHeight = in->height;
1107 cin.numSlices = in->numSlices;
1108
1109 if (in->numSamples > 1)
1110 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1111 else
1112 cin.swizzleMode = in->swizzleMode;
1113
1114 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1115 if (ret != ADDR_OK)
1116 return ret;
1117
1118 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1119 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1120 surf->u.gfx9.cmask_size = cout.cmaskBytes;
1121 surf->u.gfx9.cmask_alignment = cout.baseAlign;
1122 }
1123 }
1124
1125 return 0;
1126 }
1127
1128 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1129 const struct radeon_info *info,
1130 const struct ac_surf_config *config,
1131 enum radeon_surf_mode mode,
1132 struct radeon_surf *surf)
1133 {
1134 bool compressed;
1135 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1136 int r;
1137
1138 assert(!(surf->flags & RADEON_SURF_FMASK));
1139
1140 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1141
1142 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1143
1144 /* The format must be set correctly for the allocation of compressed
1145 * textures to work. In other cases, setting the bpp is sufficient. */
1146 if (compressed) {
1147 switch (surf->bpe) {
1148 case 8:
1149 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1150 break;
1151 case 16:
1152 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1153 break;
1154 default:
1155 assert(0);
1156 }
1157 } else {
1158 switch (surf->bpe) {
1159 case 1:
1160 AddrSurfInfoIn.format = ADDR_FMT_8;
1161 break;
1162 case 2:
1163 AddrSurfInfoIn.format = ADDR_FMT_16;
1164 break;
1165 case 4:
1166 AddrSurfInfoIn.format = ADDR_FMT_32;
1167 break;
1168 case 8:
1169 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1170 break;
1171 case 16:
1172 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1173 break;
1174 default:
1175 assert(0);
1176 }
1177 AddrSurfInfoIn.bpp = surf->bpe * 8;
1178 }
1179
1180 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1181 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1182 AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
1183 /* flags.texture currently refers to TC-compatible HTILE */
1184 AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
1185 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1186 AddrSurfInfoIn.flags.opt4space = 1;
1187
1188 AddrSurfInfoIn.numMipLevels = config->info.levels;
1189 AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
1190 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1191
1192 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1193 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1194 * must sample 1D textures as 2D. */
1195 if (config->is_3d)
1196 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1197 else
1198 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1199
1200 AddrSurfInfoIn.width = config->info.width;
1201 AddrSurfInfoIn.height = config->info.height;
1202
1203 if (config->is_3d)
1204 AddrSurfInfoIn.numSlices = config->info.depth;
1205 else if (config->is_cube)
1206 AddrSurfInfoIn.numSlices = 6;
1207 else
1208 AddrSurfInfoIn.numSlices = config->info.array_size;
1209
1210 /* This is propagated to HTILE/DCC/CMASK. */
1211 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1212 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1213
1214 switch (mode) {
1215 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1216 assert(config->info.samples <= 1);
1217 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1218 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1219 break;
1220
1221 case RADEON_SURF_MODE_1D:
1222 case RADEON_SURF_MODE_2D:
1223 if (surf->flags & RADEON_SURF_IMPORTED) {
1224 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1225 break;
1226 }
1227
1228 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
1229 &AddrSurfInfoIn.swizzleMode);
1230 if (r)
1231 return r;
1232 break;
1233
1234 default:
1235 assert(0);
1236 }
1237
1238 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1239 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1240
1241 surf->num_dcc_levels = 0;
1242 surf->surf_size = 0;
1243 surf->dcc_size = 0;
1244 surf->htile_size = 0;
1245 surf->htile_slice_size = 0;
1246 surf->u.gfx9.surf_offset = 0;
1247 surf->u.gfx9.stencil_offset = 0;
1248 surf->u.gfx9.fmask_size = 0;
1249 surf->u.gfx9.cmask_size = 0;
1250
1251 /* Calculate texture layout information. */
1252 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1253 &AddrSurfInfoIn);
1254 if (r)
1255 return r;
1256
1257 /* Calculate texture layout information for stencil. */
1258 if (surf->flags & RADEON_SURF_SBUFFER) {
1259 AddrSurfInfoIn.flags.stencil = 1;
1260 AddrSurfInfoIn.bpp = 8;
1261
1262 if (!AddrSurfInfoIn.flags.depth) {
1263 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
1264 &AddrSurfInfoIn.swizzleMode);
1265 if (r)
1266 return r;
1267 } else
1268 AddrSurfInfoIn.flags.depth = 0;
1269
1270 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1271 &AddrSurfInfoIn);
1272 if (r)
1273 return r;
1274 }
1275
1276 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1277
1278 /* Query whether the surface is displayable. */
1279 bool displayable = false;
1280 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1281 surf->bpe * 8, &displayable);
1282 if (r)
1283 return r;
1284 surf->is_displayable = displayable;
1285
1286 switch (surf->u.gfx9.surf.swizzle_mode) {
1287 /* S = standard. */
1288 case ADDR_SW_256B_S:
1289 case ADDR_SW_4KB_S:
1290 case ADDR_SW_64KB_S:
1291 case ADDR_SW_VAR_S:
1292 case ADDR_SW_64KB_S_T:
1293 case ADDR_SW_4KB_S_X:
1294 case ADDR_SW_64KB_S_X:
1295 case ADDR_SW_VAR_S_X:
1296 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1297 break;
1298
1299 /* D = display. */
1300 case ADDR_SW_LINEAR:
1301 case ADDR_SW_256B_D:
1302 case ADDR_SW_4KB_D:
1303 case ADDR_SW_64KB_D:
1304 case ADDR_SW_VAR_D:
1305 case ADDR_SW_64KB_D_T:
1306 case ADDR_SW_4KB_D_X:
1307 case ADDR_SW_64KB_D_X:
1308 case ADDR_SW_VAR_D_X:
1309 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1310 break;
1311
1312 /* R = rotated. */
1313 case ADDR_SW_256B_R:
1314 case ADDR_SW_4KB_R:
1315 case ADDR_SW_64KB_R:
1316 case ADDR_SW_VAR_R:
1317 case ADDR_SW_64KB_R_T:
1318 case ADDR_SW_4KB_R_X:
1319 case ADDR_SW_64KB_R_X:
1320 case ADDR_SW_VAR_R_X:
1321 surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1322 break;
1323
1324 /* Z = depth. */
1325 case ADDR_SW_4KB_Z:
1326 case ADDR_SW_64KB_Z:
1327 case ADDR_SW_VAR_Z:
1328 case ADDR_SW_64KB_Z_T:
1329 case ADDR_SW_4KB_Z_X:
1330 case ADDR_SW_64KB_Z_X:
1331 case ADDR_SW_VAR_Z_X:
1332 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1333 break;
1334
1335 default:
1336 assert(0);
1337 }
1338
1339 /* Temporary workaround to prevent VM faults and hangs. */
1340 if (info->family == CHIP_VEGA12)
1341 surf->u.gfx9.fmask_size *= 8;
1342
1343 return 0;
1344 }
1345
1346 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1347 const struct ac_surf_config *config,
1348 enum radeon_surf_mode mode,
1349 struct radeon_surf *surf)
1350 {
1351 int r;
1352
1353 r = surf_config_sanity(config);
1354 if (r)
1355 return r;
1356
1357 if (info->chip_class >= GFX9)
1358 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1359 else
1360 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1361 }