2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "amdgpu_id.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_math.h"
39 #include <amdgpu_drm.h>
41 #include "addrlib/addrinterface.h"
43 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
44 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
47 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
48 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
51 static void addrlib_family_rev_id(enum radeon_family family
,
52 unsigned *addrlib_family
,
53 unsigned *addrlib_revid
)
57 *addrlib_family
= FAMILY_SI
;
58 *addrlib_revid
= SI_TAHITI_P_A0
;
61 *addrlib_family
= FAMILY_SI
;
62 *addrlib_revid
= SI_PITCAIRN_PM_A0
;
65 *addrlib_family
= FAMILY_SI
;
66 *addrlib_revid
= SI_CAPEVERDE_M_A0
;
69 *addrlib_family
= FAMILY_SI
;
70 *addrlib_revid
= SI_OLAND_M_A0
;
73 *addrlib_family
= FAMILY_SI
;
74 *addrlib_revid
= SI_HAINAN_V_A0
;
77 *addrlib_family
= FAMILY_CI
;
78 *addrlib_revid
= CI_BONAIRE_M_A0
;
81 *addrlib_family
= FAMILY_KV
;
82 *addrlib_revid
= KV_SPECTRE_A0
;
85 *addrlib_family
= FAMILY_KV
;
86 *addrlib_revid
= KB_KALINDI_A0
;
89 *addrlib_family
= FAMILY_CI
;
90 *addrlib_revid
= CI_HAWAII_P_A0
;
93 *addrlib_family
= FAMILY_KV
;
94 *addrlib_revid
= ML_GODAVARI_A0
;
97 *addrlib_family
= FAMILY_VI
;
98 *addrlib_revid
= VI_TONGA_P_A0
;
101 *addrlib_family
= FAMILY_VI
;
102 *addrlib_revid
= VI_ICELAND_M_A0
;
105 *addrlib_family
= FAMILY_CZ
;
106 *addrlib_revid
= CARRIZO_A0
;
109 *addrlib_family
= FAMILY_CZ
;
110 *addrlib_revid
= STONEY_A0
;
113 *addrlib_family
= FAMILY_VI
;
114 *addrlib_revid
= VI_FIJI_P_A0
;
117 *addrlib_family
= FAMILY_VI
;
118 *addrlib_revid
= VI_POLARIS10_P_A0
;
121 *addrlib_family
= FAMILY_VI
;
122 *addrlib_revid
= VI_POLARIS11_M_A0
;
125 *addrlib_family
= FAMILY_VI
;
126 *addrlib_revid
= VI_POLARIS12_V_A0
;
129 *addrlib_family
= FAMILY_AI
;
130 *addrlib_revid
= AI_VEGA10_P_A0
;
133 *addrlib_family
= FAMILY_RV
;
134 *addrlib_revid
= RAVEN_A0
;
137 fprintf(stderr
, "amdgpu: Unknown family.\n");
141 static void *ADDR_API
allocSysMem(const ADDR_ALLOCSYSMEM_INPUT
* pInput
)
143 return malloc(pInput
->sizeInBytes
);
146 static ADDR_E_RETURNCODE ADDR_API
freeSysMem(const ADDR_FREESYSMEM_INPUT
* pInput
)
148 free(pInput
->pVirtAddr
);
152 ADDR_HANDLE
amdgpu_addr_create(const struct radeon_info
*info
,
153 const struct amdgpu_gpu_info
*amdinfo
,
154 uint64_t *max_alignment
)
156 ADDR_CREATE_INPUT addrCreateInput
= {0};
157 ADDR_CREATE_OUTPUT addrCreateOutput
= {0};
158 ADDR_REGISTER_VALUE regValue
= {0};
159 ADDR_CREATE_FLAGS createFlags
= {{0}};
160 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput
= {0};
161 ADDR_E_RETURNCODE addrRet
;
163 addrCreateInput
.size
= sizeof(ADDR_CREATE_INPUT
);
164 addrCreateOutput
.size
= sizeof(ADDR_CREATE_OUTPUT
);
166 regValue
.gbAddrConfig
= amdinfo
->gb_addr_cfg
;
167 createFlags
.value
= 0;
169 addrlib_family_rev_id(info
->family
, &addrCreateInput
.chipFamily
, &addrCreateInput
.chipRevision
);
170 if (addrCreateInput
.chipFamily
== FAMILY_UNKNOWN
)
173 if (addrCreateInput
.chipFamily
>= FAMILY_AI
) {
174 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_ARCTICISLAND
;
175 regValue
.blockVarSizeLog2
= 0;
177 regValue
.noOfBanks
= amdinfo
->mc_arb_ramcfg
& 0x3;
178 regValue
.noOfRanks
= (amdinfo
->mc_arb_ramcfg
& 0x4) >> 2;
180 regValue
.backendDisables
= amdinfo
->enabled_rb_pipes_mask
;
181 regValue
.pTileConfig
= amdinfo
->gb_tile_mode
;
182 regValue
.noOfEntries
= ARRAY_SIZE(amdinfo
->gb_tile_mode
);
183 if (addrCreateInput
.chipFamily
== FAMILY_SI
) {
184 regValue
.pMacroTileConfig
= NULL
;
185 regValue
.noOfMacroEntries
= 0;
187 regValue
.pMacroTileConfig
= amdinfo
->gb_macro_tile_mode
;
188 regValue
.noOfMacroEntries
= ARRAY_SIZE(amdinfo
->gb_macro_tile_mode
);
191 createFlags
.useTileIndex
= 1;
192 createFlags
.useHtileSliceAlign
= 1;
194 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_SOUTHERNISLAND
;
197 addrCreateInput
.callbacks
.allocSysMem
= allocSysMem
;
198 addrCreateInput
.callbacks
.freeSysMem
= freeSysMem
;
199 addrCreateInput
.callbacks
.debugPrint
= 0;
200 addrCreateInput
.createFlags
= createFlags
;
201 addrCreateInput
.regValue
= regValue
;
203 addrRet
= AddrCreate(&addrCreateInput
, &addrCreateOutput
);
204 if (addrRet
!= ADDR_OK
)
208 addrRet
= AddrGetMaxAlignments(addrCreateOutput
.hLib
, &addrGetMaxAlignmentsOutput
);
209 if (addrRet
== ADDR_OK
){
210 *max_alignment
= addrGetMaxAlignmentsOutput
.baseAlign
;
213 return addrCreateOutput
.hLib
;
216 static int surf_config_sanity(const struct ac_surf_config
*config
)
218 /* all dimension must be at least 1 ! */
219 if (!config
->info
.width
|| !config
->info
.height
|| !config
->info
.depth
||
220 !config
->info
.array_size
|| !config
->info
.levels
)
223 switch (config
->info
.samples
) {
234 if (config
->is_3d
&& config
->info
.array_size
> 1)
236 if (config
->is_cube
&& config
->info
.depth
> 1)
242 static int gfx6_compute_level(ADDR_HANDLE addrlib
,
243 const struct ac_surf_config
*config
,
244 struct radeon_surf
*surf
, bool is_stencil
,
245 unsigned level
, bool compressed
,
246 ADDR_COMPUTE_SURFACE_INFO_INPUT
*AddrSurfInfoIn
,
247 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
*AddrSurfInfoOut
,
248 ADDR_COMPUTE_DCCINFO_INPUT
*AddrDccIn
,
249 ADDR_COMPUTE_DCCINFO_OUTPUT
*AddrDccOut
,
250 ADDR_COMPUTE_HTILE_INFO_INPUT
*AddrHtileIn
,
251 ADDR_COMPUTE_HTILE_INFO_OUTPUT
*AddrHtileOut
)
253 struct legacy_surf_level
*surf_level
;
254 ADDR_E_RETURNCODE ret
;
256 AddrSurfInfoIn
->mipLevel
= level
;
257 AddrSurfInfoIn
->width
= u_minify(config
->info
.width
, level
);
258 AddrSurfInfoIn
->height
= u_minify(config
->info
.height
, level
);
260 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
261 * because GFX9 needs linear alignment of 256 bytes.
263 if (config
->info
.levels
== 1 &&
264 AddrSurfInfoIn
->tileMode
== ADDR_TM_LINEAR_ALIGNED
&&
265 AddrSurfInfoIn
->bpp
) {
266 unsigned alignment
= 256 / (AddrSurfInfoIn
->bpp
/ 8);
268 assert(util_is_power_of_two(AddrSurfInfoIn
->bpp
));
269 AddrSurfInfoIn
->width
= align(AddrSurfInfoIn
->width
, alignment
);
273 AddrSurfInfoIn
->numSlices
= u_minify(config
->info
.depth
, level
);
274 else if (config
->is_cube
)
275 AddrSurfInfoIn
->numSlices
= 6;
277 AddrSurfInfoIn
->numSlices
= config
->info
.array_size
;
280 /* Set the base level pitch. This is needed for calculation
281 * of non-zero levels. */
283 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.stencil_level
[0].nblk_x
;
285 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.level
[0].nblk_x
;
287 /* Convert blocks to pixels for compressed formats. */
289 AddrSurfInfoIn
->basePitch
*= surf
->blk_w
;
292 ret
= AddrComputeSurfaceInfo(addrlib
,
295 if (ret
!= ADDR_OK
) {
299 surf_level
= is_stencil
? &surf
->u
.legacy
.stencil_level
[level
] : &surf
->u
.legacy
.level
[level
];
300 surf_level
->offset
= align64(surf
->surf_size
, AddrSurfInfoOut
->baseAlign
);
301 surf_level
->slice_size
= AddrSurfInfoOut
->sliceSize
;
302 surf_level
->nblk_x
= AddrSurfInfoOut
->pitch
;
303 surf_level
->nblk_y
= AddrSurfInfoOut
->height
;
305 switch (AddrSurfInfoOut
->tileMode
) {
306 case ADDR_TM_LINEAR_ALIGNED
:
307 surf_level
->mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
309 case ADDR_TM_1D_TILED_THIN1
:
310 surf_level
->mode
= RADEON_SURF_MODE_1D
;
312 case ADDR_TM_2D_TILED_THIN1
:
313 surf_level
->mode
= RADEON_SURF_MODE_2D
;
320 surf
->u
.legacy
.stencil_tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
322 surf
->u
.legacy
.tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
324 surf
->surf_size
= surf_level
->offset
+ AddrSurfInfoOut
->surfSize
;
326 /* Clear DCC fields at the beginning. */
327 surf_level
->dcc_offset
= 0;
329 /* The previous level's flag tells us if we can use DCC for this level. */
330 if (AddrSurfInfoIn
->flags
.dccCompatible
&&
331 (level
== 0 || AddrDccOut
->subLvlCompressible
)) {
332 AddrDccIn
->colorSurfSize
= AddrSurfInfoOut
->surfSize
;
333 AddrDccIn
->tileMode
= AddrSurfInfoOut
->tileMode
;
334 AddrDccIn
->tileInfo
= *AddrSurfInfoOut
->pTileInfo
;
335 AddrDccIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
336 AddrDccIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
338 ret
= AddrComputeDccInfo(addrlib
,
342 if (ret
== ADDR_OK
) {
343 surf_level
->dcc_offset
= surf
->dcc_size
;
344 surf_level
->dcc_fast_clear_size
= AddrDccOut
->dccFastClearSize
;
345 surf
->num_dcc_levels
= level
+ 1;
346 surf
->dcc_size
= surf_level
->dcc_offset
+ AddrDccOut
->dccRamSize
;
347 surf
->dcc_alignment
= MAX2(surf
->dcc_alignment
, AddrDccOut
->dccRamBaseAlign
);
351 /* TC-compatible HTILE. */
353 AddrSurfInfoIn
->flags
.depth
&&
354 surf_level
->mode
== RADEON_SURF_MODE_2D
&&
356 AddrHtileIn
->flags
.tcCompatible
= AddrSurfInfoIn
->flags
.tcCompatible
;
357 AddrHtileIn
->pitch
= AddrSurfInfoOut
->pitch
;
358 AddrHtileIn
->height
= AddrSurfInfoOut
->height
;
359 AddrHtileIn
->numSlices
= AddrSurfInfoOut
->depth
;
360 AddrHtileIn
->blockWidth
= ADDR_HTILE_BLOCKSIZE_8
;
361 AddrHtileIn
->blockHeight
= ADDR_HTILE_BLOCKSIZE_8
;
362 AddrHtileIn
->pTileInfo
= AddrSurfInfoOut
->pTileInfo
;
363 AddrHtileIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
364 AddrHtileIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
366 ret
= AddrComputeHtileInfo(addrlib
,
370 if (ret
== ADDR_OK
) {
371 surf
->htile_size
= AddrHtileOut
->htileBytes
;
372 surf
->htile_slice_size
= AddrHtileOut
->sliceSize
;
373 surf
->htile_alignment
= AddrHtileOut
->baseAlign
;
380 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
381 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
383 static void gfx6_set_micro_tile_mode(struct radeon_surf
*surf
,
384 const struct radeon_info
*info
)
386 uint32_t tile_mode
= info
->si_tile_mode_array
[surf
->u
.legacy
.tiling_index
[0]];
388 if (info
->chip_class
>= CIK
)
389 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE_NEW(tile_mode
);
391 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE(tile_mode
);
394 static unsigned cik_get_macro_tile_index(struct radeon_surf
*surf
)
396 unsigned index
, tileb
;
398 tileb
= 8 * 8 * surf
->bpe
;
399 tileb
= MIN2(surf
->u
.legacy
.tile_split
, tileb
);
401 for (index
= 0; tileb
> 64; index
++)
409 * Copy surface-global settings like pipe/bank config from level 0 surface
412 static void gfx6_surface_settings(const struct radeon_info
* info
,
413 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* csio
,
414 struct radeon_surf
*surf
)
416 surf
->surf_alignment
= csio
->baseAlign
;
417 surf
->u
.legacy
.pipe_config
= csio
->pTileInfo
->pipeConfig
- 1;
418 gfx6_set_micro_tile_mode(surf
, info
);
420 /* For 2D modes only. */
421 if (csio
->tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
422 surf
->u
.legacy
.bankw
= csio
->pTileInfo
->bankWidth
;
423 surf
->u
.legacy
.bankh
= csio
->pTileInfo
->bankHeight
;
424 surf
->u
.legacy
.mtilea
= csio
->pTileInfo
->macroAspectRatio
;
425 surf
->u
.legacy
.tile_split
= csio
->pTileInfo
->tileSplitBytes
;
426 surf
->u
.legacy
.num_banks
= csio
->pTileInfo
->banks
;
427 surf
->u
.legacy
.macro_tile_index
= csio
->macroModeIndex
;
429 surf
->u
.legacy
.macro_tile_index
= 0;
434 * Fill in the tiling information in \p surf based on the given surface config.
436 * The following fields of \p surf must be initialized by the caller:
437 * blk_w, blk_h, bpe, flags.
439 static int gfx6_compute_surface(ADDR_HANDLE addrlib
,
440 const struct radeon_info
*info
,
441 const struct ac_surf_config
*config
,
442 enum radeon_surf_mode mode
,
443 struct radeon_surf
*surf
)
447 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
448 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut
= {0};
449 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn
= {0};
450 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut
= {0};
451 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn
= {0};
452 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut
= {0};
453 ADDR_TILEINFO AddrTileInfoIn
= {0};
454 ADDR_TILEINFO AddrTileInfoOut
= {0};
457 AddrSurfInfoIn
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT
);
458 AddrSurfInfoOut
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT
);
459 AddrDccIn
.size
= sizeof(ADDR_COMPUTE_DCCINFO_INPUT
);
460 AddrDccOut
.size
= sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT
);
461 AddrHtileIn
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT
);
462 AddrHtileOut
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT
);
463 AddrSurfInfoOut
.pTileInfo
= &AddrTileInfoOut
;
465 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
467 /* MSAA and FMASK require 2D tiling. */
468 if (config
->info
.samples
> 1 ||
469 (surf
->flags
& RADEON_SURF_FMASK
))
470 mode
= RADEON_SURF_MODE_2D
;
472 /* DB doesn't support linear layouts. */
473 if (surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
) &&
474 mode
< RADEON_SURF_MODE_1D
)
475 mode
= RADEON_SURF_MODE_1D
;
477 /* Set the requested tiling mode. */
479 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
480 AddrSurfInfoIn
.tileMode
= ADDR_TM_LINEAR_ALIGNED
;
482 case RADEON_SURF_MODE_1D
:
483 AddrSurfInfoIn
.tileMode
= ADDR_TM_1D_TILED_THIN1
;
485 case RADEON_SURF_MODE_2D
:
486 AddrSurfInfoIn
.tileMode
= ADDR_TM_2D_TILED_THIN1
;
492 /* The format must be set correctly for the allocation of compressed
493 * textures to work. In other cases, setting the bpp is sufficient.
498 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
501 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
508 AddrDccIn
.bpp
= AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
511 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numSamples
=
512 config
->info
.samples
? config
->info
.samples
: 1;
513 AddrSurfInfoIn
.tileIndex
= -1;
515 /* Set the micro tile type. */
516 if (surf
->flags
& RADEON_SURF_SCANOUT
)
517 AddrSurfInfoIn
.tileType
= ADDR_DISPLAYABLE
;
518 else if (surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
| RADEON_SURF_FMASK
))
519 AddrSurfInfoIn
.tileType
= ADDR_DEPTH_SAMPLE_ORDER
;
521 AddrSurfInfoIn
.tileType
= ADDR_NON_DISPLAYABLE
;
523 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
524 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
525 AddrSurfInfoIn
.flags
.cube
= config
->is_cube
;
526 AddrSurfInfoIn
.flags
.fmask
= (surf
->flags
& RADEON_SURF_FMASK
) != 0;
527 AddrSurfInfoIn
.flags
.display
= (surf
->flags
& RADEON_SURF_SCANOUT
) != 0;
528 AddrSurfInfoIn
.flags
.pow2Pad
= config
->info
.levels
> 1;
529 AddrSurfInfoIn
.flags
.tcCompatible
= (surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) != 0;
531 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
532 * requested, because TC-compatible HTILE requires 2D tiling.
534 AddrSurfInfoIn
.flags
.opt4Space
= !AddrSurfInfoIn
.flags
.tcCompatible
&&
535 !AddrSurfInfoIn
.flags
.fmask
&&
536 config
->info
.samples
<= 1 &&
537 (surf
->flags
& RADEON_SURF_OPTIMIZE_FOR_SPACE
);
540 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
542 * - Mipmapped array textures have low performance (discovered by a closed
545 AddrSurfInfoIn
.flags
.dccCompatible
=
546 info
->chip_class
>= VI
&&
547 !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
548 !(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
549 !compressed
&& AddrDccIn
.numSamples
<= 1 &&
550 ((config
->info
.array_size
== 1 && config
->info
.depth
== 1) ||
551 config
->info
.levels
== 1);
553 AddrSurfInfoIn
.flags
.noStencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) == 0;
554 AddrSurfInfoIn
.flags
.compressZ
= AddrSurfInfoIn
.flags
.depth
;
556 /* noStencil = 0 can result in a depth part that is incompatible with
557 * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
558 * this case, we may end up setting stencil_adjusted).
560 * TODO: update addrlib to a newer version, remove this, and
561 * use flags.matchStencilTileCfg = 1 as an alternative fix.
563 if (config
->info
.levels
> 1)
564 AddrSurfInfoIn
.flags
.noStencil
= 1;
566 /* Set preferred macrotile parameters. This is usually required
567 * for shared resources. This is for 2D tiling only. */
568 if (AddrSurfInfoIn
.tileMode
>= ADDR_TM_2D_TILED_THIN1
&&
569 surf
->u
.legacy
.bankw
&& surf
->u
.legacy
.bankh
&&
570 surf
->u
.legacy
.mtilea
&& surf
->u
.legacy
.tile_split
) {
571 assert(!(surf
->flags
& RADEON_SURF_FMASK
));
573 /* If any of these parameters are incorrect, the calculation
575 AddrTileInfoIn
.banks
= surf
->u
.legacy
.num_banks
;
576 AddrTileInfoIn
.bankWidth
= surf
->u
.legacy
.bankw
;
577 AddrTileInfoIn
.bankHeight
= surf
->u
.legacy
.bankh
;
578 AddrTileInfoIn
.macroAspectRatio
= surf
->u
.legacy
.mtilea
;
579 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.tile_split
;
580 AddrTileInfoIn
.pipeConfig
= surf
->u
.legacy
.pipe_config
+ 1; /* +1 compared to GB_TILE_MODE */
581 AddrSurfInfoIn
.flags
.opt4Space
= 0;
582 AddrSurfInfoIn
.pTileInfo
= &AddrTileInfoIn
;
584 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
585 * the tile index, because we are expected to know it if
586 * we know the other parameters.
588 * This is something that can easily be fixed in Addrlib.
589 * For now, just figure it out here.
590 * Note that only 2D_TILE_THIN1 is handled here.
592 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
593 assert(AddrSurfInfoIn
.tileMode
== ADDR_TM_2D_TILED_THIN1
);
595 if (info
->chip_class
== SI
) {
596 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
) {
598 AddrSurfInfoIn
.tileIndex
= 11; /* 16bpp */
600 AddrSurfInfoIn
.tileIndex
= 12; /* 32bpp */
603 AddrSurfInfoIn
.tileIndex
= 14; /* 8bpp */
604 else if (surf
->bpe
== 2)
605 AddrSurfInfoIn
.tileIndex
= 15; /* 16bpp */
606 else if (surf
->bpe
== 4)
607 AddrSurfInfoIn
.tileIndex
= 16; /* 32bpp */
609 AddrSurfInfoIn
.tileIndex
= 17; /* 64bpp (and 128bpp) */
613 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
)
614 AddrSurfInfoIn
.tileIndex
= 10; /* 2D displayable */
616 AddrSurfInfoIn
.tileIndex
= 14; /* 2D non-displayable */
618 /* Addrlib doesn't set this if tileIndex is forced like above. */
619 AddrSurfInfoOut
.macroModeIndex
= cik_get_macro_tile_index(surf
);
623 surf
->num_dcc_levels
= 0;
626 surf
->dcc_alignment
= 1;
627 surf
->htile_size
= 0;
628 surf
->htile_slice_size
= 0;
629 surf
->htile_alignment
= 1;
631 const bool only_stencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) &&
632 !(surf
->flags
& RADEON_SURF_ZBUFFER
);
634 /* Calculate texture layout information. */
636 for (level
= 0; level
< config
->info
.levels
; level
++) {
637 r
= gfx6_compute_level(addrlib
, config
, surf
, false, level
, compressed
,
638 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
639 &AddrDccIn
, &AddrDccOut
, &AddrHtileIn
, &AddrHtileOut
);
646 gfx6_surface_settings(info
, &AddrSurfInfoOut
, surf
);
650 /* Calculate texture layout information for stencil. */
651 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
652 AddrSurfInfoIn
.bpp
= 8;
653 AddrSurfInfoIn
.flags
.depth
= 0;
654 AddrSurfInfoIn
.flags
.stencil
= 1;
655 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
656 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
657 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.stencil_tile_split
;
659 for (level
= 0; level
< config
->info
.levels
; level
++) {
660 r
= gfx6_compute_level(addrlib
, config
, surf
, true, level
, compressed
,
661 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
662 &AddrDccIn
, &AddrDccOut
,
667 /* DB uses the depth pitch for both stencil and depth. */
669 if (surf
->u
.legacy
.stencil_level
[level
].nblk_x
!=
670 surf
->u
.legacy
.level
[level
].nblk_x
)
671 surf
->u
.legacy
.stencil_adjusted
= true;
673 surf
->u
.legacy
.level
[level
].nblk_x
=
674 surf
->u
.legacy
.stencil_level
[level
].nblk_x
;
679 gfx6_surface_settings(info
, &AddrSurfInfoOut
, surf
);
681 /* For 2D modes only. */
682 if (AddrSurfInfoOut
.tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
683 surf
->u
.legacy
.stencil_tile_split
=
684 AddrSurfInfoOut
.pTileInfo
->tileSplitBytes
;
690 /* Recalculate the whole DCC miptree size including disabled levels.
691 * This is what addrlib does, but calling addrlib would be a lot more
694 if (surf
->dcc_size
&& config
->info
.levels
> 1) {
695 surf
->dcc_size
= align64(surf
->surf_size
>> 8,
696 info
->pipe_interleave_bytes
*
697 info
->num_tile_pipes
);
700 /* Make sure HTILE covers the whole miptree, because the shader reads
701 * TC-compatible HTILE even for levels where it's disabled by DB.
703 if (surf
->htile_size
&& config
->info
.levels
> 1)
704 surf
->htile_size
*= 2;
706 surf
->is_linear
= surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
;
708 /* workout base swizzle */
709 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)) {
710 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn
= {0};
711 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut
= {0};
713 AddrBaseSwizzleIn
.surfIndex
= config
->info
.surf_index
;
714 AddrBaseSwizzleIn
.tileIndex
= AddrSurfInfoIn
.tileIndex
;
715 AddrBaseSwizzleIn
.macroModeIndex
= AddrSurfInfoOut
.macroModeIndex
;
716 AddrBaseSwizzleIn
.pTileInfo
= AddrSurfInfoOut
.pTileInfo
;
717 AddrBaseSwizzleIn
.tileMode
= AddrSurfInfoOut
.tileMode
;
718 AddrComputeBaseSwizzle(addrlib
, &AddrBaseSwizzleIn
, &AddrBaseSwizzleOut
);
719 surf
->u
.legacy
.tile_swizzle
= AddrBaseSwizzleOut
.tileSwizzle
;
724 /* This is only called when expecting a tiled layout. */
726 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib
,
727 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
,
728 bool is_fmask
, AddrSwizzleMode
*swizzle_mode
)
730 ADDR_E_RETURNCODE ret
;
731 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin
= {0};
732 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout
= {0};
734 sin
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
);
735 sout
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
);
737 sin
.flags
= in
->flags
;
738 sin
.resourceType
= in
->resourceType
;
739 sin
.format
= in
->format
;
740 sin
.resourceLoction
= ADDR_RSRC_LOC_INVIS
;
741 /* TODO: We could allow some of these: */
742 sin
.forbiddenBlock
.micro
= 1; /* don't allow the 256B swizzle modes */
743 sin
.forbiddenBlock
.var
= 1; /* don't allow the variable-sized swizzle modes */
744 sin
.forbiddenBlock
.linear
= 1; /* don't allow linear swizzle modes */
746 sin
.width
= in
->width
;
747 sin
.height
= in
->height
;
748 sin
.numSlices
= in
->numSlices
;
749 sin
.numMipLevels
= in
->numMipLevels
;
750 sin
.numSamples
= in
->numSamples
;
751 sin
.numFrags
= in
->numFrags
;
758 ret
= Addr2GetPreferredSurfaceSetting(addrlib
, &sin
, &sout
);
762 *swizzle_mode
= sout
.swizzleMode
;
766 static int gfx9_compute_miptree(ADDR_HANDLE addrlib
,
767 struct radeon_surf
*surf
, bool compressed
,
768 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
)
770 ADDR2_MIP_INFO mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
771 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out
= {0};
772 ADDR_E_RETURNCODE ret
;
774 out
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
);
775 out
.pMipInfo
= mip_info
;
777 ret
= Addr2ComputeSurfaceInfo(addrlib
, in
, &out
);
781 if (in
->flags
.stencil
) {
782 surf
->u
.gfx9
.stencil
.swizzle_mode
= in
->swizzleMode
;
783 surf
->u
.gfx9
.stencil
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
784 out
.mipChainPitch
- 1;
785 surf
->surf_alignment
= MAX2(surf
->surf_alignment
, out
.baseAlign
);
786 surf
->u
.gfx9
.stencil_offset
= align(surf
->surf_size
, out
.baseAlign
);
787 surf
->surf_size
= surf
->u
.gfx9
.stencil_offset
+ out
.surfSize
;
791 surf
->u
.gfx9
.surf
.swizzle_mode
= in
->swizzleMode
;
792 surf
->u
.gfx9
.surf
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
793 out
.mipChainPitch
- 1;
795 /* CMASK fast clear uses these even if FMASK isn't allocated.
796 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
798 surf
->u
.gfx9
.fmask
.swizzle_mode
= surf
->u
.gfx9
.surf
.swizzle_mode
& ~0x3;
799 surf
->u
.gfx9
.fmask
.epitch
= surf
->u
.gfx9
.surf
.epitch
;
801 surf
->u
.gfx9
.surf_slice_size
= out
.sliceSize
;
802 surf
->u
.gfx9
.surf_pitch
= out
.pitch
;
803 surf
->u
.gfx9
.surf_height
= out
.height
;
804 surf
->surf_size
= out
.surfSize
;
805 surf
->surf_alignment
= out
.baseAlign
;
807 if (in
->swizzleMode
== ADDR_SW_LINEAR
) {
808 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++)
809 surf
->u
.gfx9
.offset
[i
] = mip_info
[i
].offset
;
812 if (in
->flags
.depth
) {
813 assert(in
->swizzleMode
!= ADDR_SW_LINEAR
);
816 ADDR2_COMPUTE_HTILE_INFO_INPUT hin
= {0};
817 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout
= {0};
819 hin
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT
);
820 hout
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT
);
822 hin
.hTileFlags
.pipeAligned
= 1;
823 hin
.hTileFlags
.rbAligned
= 1;
824 hin
.depthFlags
= in
->flags
;
825 hin
.swizzleMode
= in
->swizzleMode
;
826 hin
.unalignedWidth
= in
->width
;
827 hin
.unalignedHeight
= in
->height
;
828 hin
.numSlices
= in
->numSlices
;
829 hin
.numMipLevels
= in
->numMipLevels
;
831 ret
= Addr2ComputeHtileInfo(addrlib
, &hin
, &hout
);
835 surf
->u
.gfx9
.htile
.rb_aligned
= hin
.hTileFlags
.rbAligned
;
836 surf
->u
.gfx9
.htile
.pipe_aligned
= hin
.hTileFlags
.pipeAligned
;
837 surf
->htile_size
= hout
.htileBytes
;
838 surf
->htile_slice_size
= hout
.sliceSize
;
839 surf
->htile_alignment
= hout
.baseAlign
;
842 if (!(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
843 !(surf
->flags
& RADEON_SURF_SCANOUT
) &&
845 in
->swizzleMode
!= ADDR_SW_LINEAR
&&
846 /* TODO: We could support DCC with MSAA. */
847 in
->numSamples
== 1) {
848 ADDR2_COMPUTE_DCCINFO_INPUT din
= {0};
849 ADDR2_COMPUTE_DCCINFO_OUTPUT dout
= {0};
851 din
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_INPUT
);
852 dout
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT
);
854 din
.dccKeyFlags
.pipeAligned
= 1;
855 din
.dccKeyFlags
.rbAligned
= 1;
856 din
.colorFlags
= in
->flags
;
857 din
.resourceType
= in
->resourceType
;
858 din
.swizzleMode
= in
->swizzleMode
;
860 din
.unalignedWidth
= in
->width
;
861 din
.unalignedHeight
= in
->height
;
862 din
.numSlices
= in
->numSlices
;
863 din
.numFrags
= in
->numFrags
;
864 din
.numMipLevels
= in
->numMipLevels
;
865 din
.dataSurfaceSize
= out
.surfSize
;
867 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
871 surf
->u
.gfx9
.dcc
.rb_aligned
= din
.dccKeyFlags
.rbAligned
;
872 surf
->u
.gfx9
.dcc
.pipe_aligned
= din
.dccKeyFlags
.pipeAligned
;
873 surf
->u
.gfx9
.dcc_pitch_max
= dout
.pitch
- 1;
874 surf
->dcc_size
= dout
.dccRamSize
;
875 surf
->dcc_alignment
= dout
.dccRamBaseAlign
;
879 if (in
->numSamples
> 1) {
880 ADDR2_COMPUTE_FMASK_INFO_INPUT fin
= {0};
881 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
883 fin
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT
);
884 fout
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT
);
886 ret
= gfx9_get_preferred_swizzle_mode(addrlib
, in
, true, &fin
.swizzleMode
);
890 fin
.unalignedWidth
= in
->width
;
891 fin
.unalignedHeight
= in
->height
;
892 fin
.numSlices
= in
->numSlices
;
893 fin
.numSamples
= in
->numSamples
;
894 fin
.numFrags
= in
->numFrags
;
896 ret
= Addr2ComputeFmaskInfo(addrlib
, &fin
, &fout
);
900 surf
->u
.gfx9
.fmask
.swizzle_mode
= fin
.swizzleMode
;
901 surf
->u
.gfx9
.fmask
.epitch
= fout
.pitch
- 1;
902 surf
->u
.gfx9
.fmask_size
= fout
.fmaskBytes
;
903 surf
->u
.gfx9
.fmask_alignment
= fout
.baseAlign
;
907 if (in
->swizzleMode
!= ADDR_SW_LINEAR
) {
908 ADDR2_COMPUTE_CMASK_INFO_INPUT cin
= {0};
909 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout
= {0};
911 cin
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT
);
912 cout
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT
);
914 cin
.cMaskFlags
.pipeAligned
= 1;
915 cin
.cMaskFlags
.rbAligned
= 1;
916 cin
.colorFlags
= in
->flags
;
917 cin
.resourceType
= in
->resourceType
;
918 cin
.unalignedWidth
= in
->width
;
919 cin
.unalignedHeight
= in
->height
;
920 cin
.numSlices
= in
->numSlices
;
922 if (in
->numSamples
> 1)
923 cin
.swizzleMode
= surf
->u
.gfx9
.fmask
.swizzle_mode
;
925 cin
.swizzleMode
= in
->swizzleMode
;
927 ret
= Addr2ComputeCmaskInfo(addrlib
, &cin
, &cout
);
931 surf
->u
.gfx9
.cmask
.rb_aligned
= cin
.cMaskFlags
.rbAligned
;
932 surf
->u
.gfx9
.cmask
.pipe_aligned
= cin
.cMaskFlags
.pipeAligned
;
933 surf
->u
.gfx9
.cmask_size
= cout
.cmaskBytes
;
934 surf
->u
.gfx9
.cmask_alignment
= cout
.baseAlign
;
941 static int gfx9_compute_surface(ADDR_HANDLE addrlib
,
942 const struct ac_surf_config
*config
,
943 enum radeon_surf_mode mode
,
944 struct radeon_surf
*surf
)
947 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
950 assert(!(surf
->flags
& RADEON_SURF_FMASK
));
952 AddrSurfInfoIn
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT
);
954 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
956 /* The format must be set correctly for the allocation of compressed
957 * textures to work. In other cases, setting the bpp is sufficient. */
961 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
964 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
970 AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
973 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
974 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
975 AddrSurfInfoIn
.flags
.display
= (surf
->flags
& RADEON_SURF_SCANOUT
) != 0;
976 /* flags.texture currently refers to TC-compatible HTILE */
977 AddrSurfInfoIn
.flags
.texture
= AddrSurfInfoIn
.flags
.color
||
978 surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
979 AddrSurfInfoIn
.flags
.opt4space
= 1;
981 AddrSurfInfoIn
.numMipLevels
= config
->info
.levels
;
982 AddrSurfInfoIn
.numSamples
= config
->info
.samples
? config
->info
.samples
: 1;
983 AddrSurfInfoIn
.numFrags
= AddrSurfInfoIn
.numSamples
;
985 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
986 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
987 * must sample 1D textures as 2D. */
989 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_3D
;
991 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_2D
;
993 AddrSurfInfoIn
.width
= config
->info
.width
;
994 AddrSurfInfoIn
.height
= config
->info
.height
;
997 AddrSurfInfoIn
.numSlices
= config
->info
.depth
;
998 else if (config
->is_cube
)
999 AddrSurfInfoIn
.numSlices
= 6;
1001 AddrSurfInfoIn
.numSlices
= config
->info
.array_size
;
1004 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1005 assert(config
->info
.samples
<= 1);
1006 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1007 AddrSurfInfoIn
.swizzleMode
= ADDR_SW_LINEAR
;
1010 case RADEON_SURF_MODE_1D
:
1011 case RADEON_SURF_MODE_2D
:
1012 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
, false,
1013 &AddrSurfInfoIn
.swizzleMode
);
1022 surf
->u
.gfx9
.resource_type
= AddrSurfInfoIn
.resourceType
;
1024 surf
->surf_size
= 0;
1026 surf
->htile_size
= 0;
1027 surf
->htile_slice_size
= 0;
1028 surf
->u
.gfx9
.surf_offset
= 0;
1029 surf
->u
.gfx9
.stencil_offset
= 0;
1030 surf
->u
.gfx9
.fmask_size
= 0;
1031 surf
->u
.gfx9
.cmask_size
= 0;
1033 /* Calculate texture layout information. */
1034 r
= gfx9_compute_miptree(addrlib
, surf
, compressed
, &AddrSurfInfoIn
);
1038 /* Calculate texture layout information for stencil. */
1039 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
1040 AddrSurfInfoIn
.bpp
= 8;
1041 AddrSurfInfoIn
.flags
.depth
= 0;
1042 AddrSurfInfoIn
.flags
.stencil
= 1;
1044 r
= gfx9_compute_miptree(addrlib
, surf
, compressed
, &AddrSurfInfoIn
);
1049 surf
->is_linear
= surf
->u
.gfx9
.surf
.swizzle_mode
== ADDR_SW_LINEAR
;
1050 surf
->num_dcc_levels
= surf
->dcc_size
? config
->info
.levels
: 0;
1052 switch (surf
->u
.gfx9
.surf
.swizzle_mode
) {
1054 case ADDR_SW_256B_S
:
1056 case ADDR_SW_64KB_S
:
1058 case ADDR_SW_64KB_S_T
:
1059 case ADDR_SW_4KB_S_X
:
1060 case ADDR_SW_64KB_S_X
:
1061 case ADDR_SW_VAR_S_X
:
1062 surf
->micro_tile_mode
= RADEON_MICRO_MODE_THIN
;
1066 case ADDR_SW_LINEAR
:
1067 case ADDR_SW_256B_D
:
1069 case ADDR_SW_64KB_D
:
1071 case ADDR_SW_64KB_D_T
:
1072 case ADDR_SW_4KB_D_X
:
1073 case ADDR_SW_64KB_D_X
:
1074 case ADDR_SW_VAR_D_X
:
1075 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DISPLAY
;
1079 case ADDR_SW_256B_R
:
1081 case ADDR_SW_64KB_R
:
1083 case ADDR_SW_64KB_R_T
:
1084 case ADDR_SW_4KB_R_X
:
1085 case ADDR_SW_64KB_R_X
:
1086 case ADDR_SW_VAR_R_X
:
1087 surf
->micro_tile_mode
= RADEON_MICRO_MODE_ROTATED
;
1092 case ADDR_SW_64KB_Z
:
1094 case ADDR_SW_64KB_Z_T
:
1095 case ADDR_SW_4KB_Z_X
:
1096 case ADDR_SW_64KB_Z_X
:
1097 case ADDR_SW_VAR_Z_X
:
1098 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DEPTH
;
1108 int ac_compute_surface(ADDR_HANDLE addrlib
, const struct radeon_info
*info
,
1109 const struct ac_surf_config
*config
,
1110 enum radeon_surf_mode mode
,
1111 struct radeon_surf
*surf
)
1115 r
= surf_config_sanity(config
);
1119 if (info
->chip_class
>= GFX9
)
1120 return gfx9_compute_surface(addrlib
, config
, mode
, surf
);
1122 return gfx6_compute_surface(addrlib
, info
, config
, mode
, surf
);