2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
40 #include <amdgpu_drm.h>
42 #include "addrlib/addrinterface.h"
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
52 static unsigned get_first(unsigned x
, unsigned y
)
57 static void addrlib_family_rev_id(enum radeon_family family
,
58 unsigned *addrlib_family
,
59 unsigned *addrlib_revid
)
63 *addrlib_family
= FAMILY_SI
;
64 *addrlib_revid
= get_first(AMDGPU_TAHITI_RANGE
);
67 *addrlib_family
= FAMILY_SI
;
68 *addrlib_revid
= get_first(AMDGPU_PITCAIRN_RANGE
);
71 *addrlib_family
= FAMILY_SI
;
72 *addrlib_revid
= get_first(AMDGPU_CAPEVERDE_RANGE
);
75 *addrlib_family
= FAMILY_SI
;
76 *addrlib_revid
= get_first(AMDGPU_OLAND_RANGE
);
79 *addrlib_family
= FAMILY_SI
;
80 *addrlib_revid
= get_first(AMDGPU_HAINAN_RANGE
);
83 *addrlib_family
= FAMILY_CI
;
84 *addrlib_revid
= get_first(AMDGPU_BONAIRE_RANGE
);
87 *addrlib_family
= FAMILY_KV
;
88 *addrlib_revid
= get_first(AMDGPU_SPECTRE_RANGE
);
91 *addrlib_family
= FAMILY_KV
;
92 *addrlib_revid
= get_first(AMDGPU_KALINDI_RANGE
);
95 *addrlib_family
= FAMILY_CI
;
96 *addrlib_revid
= get_first(AMDGPU_HAWAII_RANGE
);
99 *addrlib_family
= FAMILY_KV
;
100 *addrlib_revid
= get_first(AMDGPU_GODAVARI_RANGE
);
103 *addrlib_family
= FAMILY_VI
;
104 *addrlib_revid
= get_first(AMDGPU_TONGA_RANGE
);
107 *addrlib_family
= FAMILY_VI
;
108 *addrlib_revid
= get_first(AMDGPU_ICELAND_RANGE
);
111 *addrlib_family
= FAMILY_CZ
;
112 *addrlib_revid
= get_first(AMDGPU_CARRIZO_RANGE
);
115 *addrlib_family
= FAMILY_CZ
;
116 *addrlib_revid
= get_first(AMDGPU_STONEY_RANGE
);
119 *addrlib_family
= FAMILY_VI
;
120 *addrlib_revid
= get_first(AMDGPU_FIJI_RANGE
);
123 *addrlib_family
= FAMILY_VI
;
124 *addrlib_revid
= get_first(AMDGPU_POLARIS10_RANGE
);
127 *addrlib_family
= FAMILY_VI
;
128 *addrlib_revid
= get_first(AMDGPU_POLARIS11_RANGE
);
131 *addrlib_family
= FAMILY_VI
;
132 *addrlib_revid
= get_first(AMDGPU_POLARIS12_RANGE
);
135 *addrlib_family
= FAMILY_AI
;
136 *addrlib_revid
= get_first(AMDGPU_VEGA10_RANGE
);
139 *addrlib_family
= FAMILY_RV
;
140 *addrlib_revid
= get_first(AMDGPU_RAVEN_RANGE
);
143 fprintf(stderr
, "amdgpu: Unknown family.\n");
147 static void *ADDR_API
allocSysMem(const ADDR_ALLOCSYSMEM_INPUT
* pInput
)
149 return malloc(pInput
->sizeInBytes
);
152 static ADDR_E_RETURNCODE ADDR_API
freeSysMem(const ADDR_FREESYSMEM_INPUT
* pInput
)
154 free(pInput
->pVirtAddr
);
158 ADDR_HANDLE
amdgpu_addr_create(const struct radeon_info
*info
,
159 const struct amdgpu_gpu_info
*amdinfo
,
160 uint64_t *max_alignment
)
162 ADDR_CREATE_INPUT addrCreateInput
= {0};
163 ADDR_CREATE_OUTPUT addrCreateOutput
= {0};
164 ADDR_REGISTER_VALUE regValue
= {0};
165 ADDR_CREATE_FLAGS createFlags
= {{0}};
166 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput
= {0};
167 ADDR_E_RETURNCODE addrRet
;
169 addrCreateInput
.size
= sizeof(ADDR_CREATE_INPUT
);
170 addrCreateOutput
.size
= sizeof(ADDR_CREATE_OUTPUT
);
172 regValue
.gbAddrConfig
= amdinfo
->gb_addr_cfg
;
173 createFlags
.value
= 0;
175 addrlib_family_rev_id(info
->family
, &addrCreateInput
.chipFamily
, &addrCreateInput
.chipRevision
);
176 if (addrCreateInput
.chipFamily
== FAMILY_UNKNOWN
)
179 if (addrCreateInput
.chipFamily
>= FAMILY_AI
) {
180 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_ARCTICISLAND
;
181 regValue
.blockVarSizeLog2
= 0;
183 regValue
.noOfBanks
= amdinfo
->mc_arb_ramcfg
& 0x3;
184 regValue
.noOfRanks
= (amdinfo
->mc_arb_ramcfg
& 0x4) >> 2;
186 regValue
.backendDisables
= amdinfo
->enabled_rb_pipes_mask
;
187 regValue
.pTileConfig
= amdinfo
->gb_tile_mode
;
188 regValue
.noOfEntries
= ARRAY_SIZE(amdinfo
->gb_tile_mode
);
189 if (addrCreateInput
.chipFamily
== FAMILY_SI
) {
190 regValue
.pMacroTileConfig
= NULL
;
191 regValue
.noOfMacroEntries
= 0;
193 regValue
.pMacroTileConfig
= amdinfo
->gb_macro_tile_mode
;
194 regValue
.noOfMacroEntries
= ARRAY_SIZE(amdinfo
->gb_macro_tile_mode
);
197 createFlags
.useTileIndex
= 1;
198 createFlags
.useHtileSliceAlign
= 1;
200 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_SOUTHERNISLAND
;
203 addrCreateInput
.callbacks
.allocSysMem
= allocSysMem
;
204 addrCreateInput
.callbacks
.freeSysMem
= freeSysMem
;
205 addrCreateInput
.callbacks
.debugPrint
= 0;
206 addrCreateInput
.createFlags
= createFlags
;
207 addrCreateInput
.regValue
= regValue
;
209 addrRet
= AddrCreate(&addrCreateInput
, &addrCreateOutput
);
210 if (addrRet
!= ADDR_OK
)
214 addrRet
= AddrGetMaxAlignments(addrCreateOutput
.hLib
, &addrGetMaxAlignmentsOutput
);
215 if (addrRet
== ADDR_OK
){
216 *max_alignment
= addrGetMaxAlignmentsOutput
.baseAlign
;
219 return addrCreateOutput
.hLib
;
222 static int surf_config_sanity(const struct ac_surf_config
*config
)
224 /* all dimension must be at least 1 ! */
225 if (!config
->info
.width
|| !config
->info
.height
|| !config
->info
.depth
||
226 !config
->info
.array_size
|| !config
->info
.levels
)
229 switch (config
->info
.samples
) {
240 if (config
->is_3d
&& config
->info
.array_size
> 1)
242 if (config
->is_cube
&& config
->info
.depth
> 1)
248 static int gfx6_compute_level(ADDR_HANDLE addrlib
,
249 const struct ac_surf_config
*config
,
250 struct radeon_surf
*surf
, bool is_stencil
,
251 unsigned level
, bool compressed
,
252 ADDR_COMPUTE_SURFACE_INFO_INPUT
*AddrSurfInfoIn
,
253 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
*AddrSurfInfoOut
,
254 ADDR_COMPUTE_DCCINFO_INPUT
*AddrDccIn
,
255 ADDR_COMPUTE_DCCINFO_OUTPUT
*AddrDccOut
,
256 ADDR_COMPUTE_HTILE_INFO_INPUT
*AddrHtileIn
,
257 ADDR_COMPUTE_HTILE_INFO_OUTPUT
*AddrHtileOut
)
259 struct legacy_surf_level
*surf_level
;
260 ADDR_E_RETURNCODE ret
;
262 AddrSurfInfoIn
->mipLevel
= level
;
263 AddrSurfInfoIn
->width
= u_minify(config
->info
.width
, level
);
264 AddrSurfInfoIn
->height
= u_minify(config
->info
.height
, level
);
266 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
267 * because GFX9 needs linear alignment of 256 bytes.
269 if (config
->info
.levels
== 1 &&
270 AddrSurfInfoIn
->tileMode
== ADDR_TM_LINEAR_ALIGNED
&&
271 AddrSurfInfoIn
->bpp
) {
272 unsigned alignment
= 256 / (AddrSurfInfoIn
->bpp
/ 8);
274 assert(util_is_power_of_two(AddrSurfInfoIn
->bpp
));
275 AddrSurfInfoIn
->width
= align(AddrSurfInfoIn
->width
, alignment
);
279 AddrSurfInfoIn
->numSlices
= u_minify(config
->info
.depth
, level
);
280 else if (config
->is_cube
)
281 AddrSurfInfoIn
->numSlices
= 6;
283 AddrSurfInfoIn
->numSlices
= config
->info
.array_size
;
286 /* Set the base level pitch. This is needed for calculation
287 * of non-zero levels. */
289 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.stencil_level
[0].nblk_x
;
291 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.level
[0].nblk_x
;
293 /* Convert blocks to pixels for compressed formats. */
295 AddrSurfInfoIn
->basePitch
*= surf
->blk_w
;
298 ret
= AddrComputeSurfaceInfo(addrlib
,
301 if (ret
!= ADDR_OK
) {
305 surf_level
= is_stencil
? &surf
->u
.legacy
.stencil_level
[level
] : &surf
->u
.legacy
.level
[level
];
306 surf_level
->offset
= align64(surf
->surf_size
, AddrSurfInfoOut
->baseAlign
);
307 surf_level
->slice_size_dw
= AddrSurfInfoOut
->sliceSize
/ 4;
308 surf_level
->nblk_x
= AddrSurfInfoOut
->pitch
;
309 surf_level
->nblk_y
= AddrSurfInfoOut
->height
;
311 switch (AddrSurfInfoOut
->tileMode
) {
312 case ADDR_TM_LINEAR_ALIGNED
:
313 surf_level
->mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
315 case ADDR_TM_1D_TILED_THIN1
:
316 surf_level
->mode
= RADEON_SURF_MODE_1D
;
318 case ADDR_TM_2D_TILED_THIN1
:
319 surf_level
->mode
= RADEON_SURF_MODE_2D
;
326 surf
->u
.legacy
.stencil_tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
328 surf
->u
.legacy
.tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
330 surf
->surf_size
= surf_level
->offset
+ AddrSurfInfoOut
->surfSize
;
332 /* Clear DCC fields at the beginning. */
333 surf_level
->dcc_offset
= 0;
335 /* The previous level's flag tells us if we can use DCC for this level. */
336 if (AddrSurfInfoIn
->flags
.dccCompatible
&&
337 (level
== 0 || AddrDccOut
->subLvlCompressible
)) {
338 AddrDccIn
->colorSurfSize
= AddrSurfInfoOut
->surfSize
;
339 AddrDccIn
->tileMode
= AddrSurfInfoOut
->tileMode
;
340 AddrDccIn
->tileInfo
= *AddrSurfInfoOut
->pTileInfo
;
341 AddrDccIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
342 AddrDccIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
344 ret
= AddrComputeDccInfo(addrlib
,
348 if (ret
== ADDR_OK
) {
349 surf_level
->dcc_offset
= surf
->dcc_size
;
350 surf_level
->dcc_fast_clear_size
= AddrDccOut
->dccFastClearSize
;
351 surf
->num_dcc_levels
= level
+ 1;
352 surf
->dcc_size
= surf_level
->dcc_offset
+ AddrDccOut
->dccRamSize
;
353 surf
->dcc_alignment
= MAX2(surf
->dcc_alignment
, AddrDccOut
->dccRamBaseAlign
);
357 /* TC-compatible HTILE. */
359 AddrSurfInfoIn
->flags
.depth
&&
360 surf_level
->mode
== RADEON_SURF_MODE_2D
&&
362 AddrHtileIn
->flags
.tcCompatible
= AddrSurfInfoIn
->flags
.tcCompatible
;
363 AddrHtileIn
->pitch
= AddrSurfInfoOut
->pitch
;
364 AddrHtileIn
->height
= AddrSurfInfoOut
->height
;
365 AddrHtileIn
->numSlices
= AddrSurfInfoOut
->depth
;
366 AddrHtileIn
->blockWidth
= ADDR_HTILE_BLOCKSIZE_8
;
367 AddrHtileIn
->blockHeight
= ADDR_HTILE_BLOCKSIZE_8
;
368 AddrHtileIn
->pTileInfo
= AddrSurfInfoOut
->pTileInfo
;
369 AddrHtileIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
370 AddrHtileIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
372 ret
= AddrComputeHtileInfo(addrlib
,
376 if (ret
== ADDR_OK
) {
377 surf
->htile_size
= AddrHtileOut
->htileBytes
;
378 surf
->htile_slice_size
= AddrHtileOut
->sliceSize
;
379 surf
->htile_alignment
= AddrHtileOut
->baseAlign
;
386 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
387 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
389 static void gfx6_set_micro_tile_mode(struct radeon_surf
*surf
,
390 const struct radeon_info
*info
)
392 uint32_t tile_mode
= info
->si_tile_mode_array
[surf
->u
.legacy
.tiling_index
[0]];
394 if (info
->chip_class
>= CIK
)
395 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE_NEW(tile_mode
);
397 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE(tile_mode
);
400 static unsigned cik_get_macro_tile_index(struct radeon_surf
*surf
)
402 unsigned index
, tileb
;
404 tileb
= 8 * 8 * surf
->bpe
;
405 tileb
= MIN2(surf
->u
.legacy
.tile_split
, tileb
);
407 for (index
= 0; tileb
> 64; index
++)
415 * This must be called after the first level is computed.
417 * Copy surface-global settings like pipe/bank config from level 0 surface
418 * computation, and compute tile swizzle.
420 static int gfx6_surface_settings(ADDR_HANDLE addrlib
,
421 const struct radeon_info
*info
,
422 const struct ac_surf_config
*config
,
423 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* csio
,
424 struct radeon_surf
*surf
)
426 surf
->surf_alignment
= csio
->baseAlign
;
427 surf
->u
.legacy
.pipe_config
= csio
->pTileInfo
->pipeConfig
- 1;
428 gfx6_set_micro_tile_mode(surf
, info
);
430 /* For 2D modes only. */
431 if (csio
->tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
432 surf
->u
.legacy
.bankw
= csio
->pTileInfo
->bankWidth
;
433 surf
->u
.legacy
.bankh
= csio
->pTileInfo
->bankHeight
;
434 surf
->u
.legacy
.mtilea
= csio
->pTileInfo
->macroAspectRatio
;
435 surf
->u
.legacy
.tile_split
= csio
->pTileInfo
->tileSplitBytes
;
436 surf
->u
.legacy
.num_banks
= csio
->pTileInfo
->banks
;
437 surf
->u
.legacy
.macro_tile_index
= csio
->macroModeIndex
;
439 surf
->u
.legacy
.macro_tile_index
= 0;
442 /* Compute tile swizzle. */
443 /* TODO: fix tile swizzle with mipmapping for SI */
444 if ((info
->chip_class
>= CIK
|| config
->info
.levels
== 1) &&
445 config
->info
.surf_index
&&
446 surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
&&
447 !(surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
| RADEON_SURF_SHAREABLE
)) &&
448 (config
->info
.samples
> 1 || !(surf
->flags
& RADEON_SURF_SCANOUT
))) {
449 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn
= {0};
450 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut
= {0};
452 AddrBaseSwizzleIn
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
453 AddrBaseSwizzleOut
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
455 AddrBaseSwizzleIn
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
456 AddrBaseSwizzleIn
.tileIndex
= csio
->tileIndex
;
457 AddrBaseSwizzleIn
.macroModeIndex
= csio
->macroModeIndex
;
458 AddrBaseSwizzleIn
.pTileInfo
= csio
->pTileInfo
;
459 AddrBaseSwizzleIn
.tileMode
= csio
->tileMode
;
461 int r
= AddrComputeBaseSwizzle(addrlib
, &AddrBaseSwizzleIn
,
462 &AddrBaseSwizzleOut
);
466 assert(AddrBaseSwizzleOut
.tileSwizzle
<=
467 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
468 surf
->tile_swizzle
= AddrBaseSwizzleOut
.tileSwizzle
;
474 * Fill in the tiling information in \p surf based on the given surface config.
476 * The following fields of \p surf must be initialized by the caller:
477 * blk_w, blk_h, bpe, flags.
479 static int gfx6_compute_surface(ADDR_HANDLE addrlib
,
480 const struct radeon_info
*info
,
481 const struct ac_surf_config
*config
,
482 enum radeon_surf_mode mode
,
483 struct radeon_surf
*surf
)
487 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
488 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut
= {0};
489 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn
= {0};
490 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut
= {0};
491 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn
= {0};
492 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut
= {0};
493 ADDR_TILEINFO AddrTileInfoIn
= {0};
494 ADDR_TILEINFO AddrTileInfoOut
= {0};
497 AddrSurfInfoIn
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT
);
498 AddrSurfInfoOut
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT
);
499 AddrDccIn
.size
= sizeof(ADDR_COMPUTE_DCCINFO_INPUT
);
500 AddrDccOut
.size
= sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT
);
501 AddrHtileIn
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT
);
502 AddrHtileOut
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT
);
503 AddrSurfInfoOut
.pTileInfo
= &AddrTileInfoOut
;
505 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
507 /* MSAA and FMASK require 2D tiling. */
508 if (config
->info
.samples
> 1 ||
509 (surf
->flags
& RADEON_SURF_FMASK
))
510 mode
= RADEON_SURF_MODE_2D
;
512 /* DB doesn't support linear layouts. */
513 if (surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
) &&
514 mode
< RADEON_SURF_MODE_1D
)
515 mode
= RADEON_SURF_MODE_1D
;
517 /* Set the requested tiling mode. */
519 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
520 AddrSurfInfoIn
.tileMode
= ADDR_TM_LINEAR_ALIGNED
;
522 case RADEON_SURF_MODE_1D
:
523 AddrSurfInfoIn
.tileMode
= ADDR_TM_1D_TILED_THIN1
;
525 case RADEON_SURF_MODE_2D
:
526 AddrSurfInfoIn
.tileMode
= ADDR_TM_2D_TILED_THIN1
;
532 /* The format must be set correctly for the allocation of compressed
533 * textures to work. In other cases, setting the bpp is sufficient.
538 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
541 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
548 AddrDccIn
.bpp
= AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
551 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numSamples
=
552 config
->info
.samples
? config
->info
.samples
: 1;
553 AddrSurfInfoIn
.tileIndex
= -1;
555 /* Set the micro tile type. */
556 if (surf
->flags
& RADEON_SURF_SCANOUT
)
557 AddrSurfInfoIn
.tileType
= ADDR_DISPLAYABLE
;
558 else if (surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
| RADEON_SURF_FMASK
))
559 AddrSurfInfoIn
.tileType
= ADDR_DEPTH_SAMPLE_ORDER
;
561 AddrSurfInfoIn
.tileType
= ADDR_NON_DISPLAYABLE
;
563 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
564 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
565 AddrSurfInfoIn
.flags
.cube
= config
->is_cube
;
566 AddrSurfInfoIn
.flags
.fmask
= (surf
->flags
& RADEON_SURF_FMASK
) != 0;
567 AddrSurfInfoIn
.flags
.display
= (surf
->flags
& RADEON_SURF_SCANOUT
) != 0;
568 AddrSurfInfoIn
.flags
.pow2Pad
= config
->info
.levels
> 1;
569 AddrSurfInfoIn
.flags
.tcCompatible
= (surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) != 0;
571 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
572 * requested, because TC-compatible HTILE requires 2D tiling.
574 AddrSurfInfoIn
.flags
.opt4Space
= !AddrSurfInfoIn
.flags
.tcCompatible
&&
575 !AddrSurfInfoIn
.flags
.fmask
&&
576 config
->info
.samples
<= 1 &&
577 (surf
->flags
& RADEON_SURF_OPTIMIZE_FOR_SPACE
);
580 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
582 * - Mipmapped array textures have low performance (discovered by a closed
585 AddrSurfInfoIn
.flags
.dccCompatible
=
586 info
->chip_class
>= VI
&&
587 !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
588 !(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
590 ((config
->info
.array_size
== 1 && config
->info
.depth
== 1) ||
591 config
->info
.levels
== 1);
593 AddrSurfInfoIn
.flags
.noStencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) == 0;
594 AddrSurfInfoIn
.flags
.compressZ
= AddrSurfInfoIn
.flags
.depth
;
596 /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
597 * for Z and stencil. This can cause a number of problems which we work
600 * - a depth part that is incompatible with mipmapped texturing
601 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
602 * incorrect tiling applied to the stencil part, stencil buffer
603 * memory accesses that go out of bounds) even without mipmapping
605 * Some piglit tests that are prone to different types of related
607 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
608 * ./bin/framebuffer-blit-levels {draw,read} stencil
609 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
610 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
611 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
613 int stencil_tile_idx
= -1;
615 if (AddrSurfInfoIn
.flags
.depth
&& !AddrSurfInfoIn
.flags
.noStencil
&&
616 (config
->info
.levels
> 1 || info
->family
== CHIP_STONEY
)) {
617 /* Compute stencilTileIdx that is compatible with the (depth)
618 * tileIdx. This degrades the depth surface if necessary to
619 * ensure that a matching stencilTileIdx exists. */
620 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 1;
622 /* Keep the depth mip-tail compatible with texturing. */
623 AddrSurfInfoIn
.flags
.noStencil
= 1;
626 /* Set preferred macrotile parameters. This is usually required
627 * for shared resources. This is for 2D tiling only. */
628 if (AddrSurfInfoIn
.tileMode
>= ADDR_TM_2D_TILED_THIN1
&&
629 surf
->u
.legacy
.bankw
&& surf
->u
.legacy
.bankh
&&
630 surf
->u
.legacy
.mtilea
&& surf
->u
.legacy
.tile_split
) {
631 assert(!(surf
->flags
& RADEON_SURF_FMASK
));
633 /* If any of these parameters are incorrect, the calculation
635 AddrTileInfoIn
.banks
= surf
->u
.legacy
.num_banks
;
636 AddrTileInfoIn
.bankWidth
= surf
->u
.legacy
.bankw
;
637 AddrTileInfoIn
.bankHeight
= surf
->u
.legacy
.bankh
;
638 AddrTileInfoIn
.macroAspectRatio
= surf
->u
.legacy
.mtilea
;
639 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.tile_split
;
640 AddrTileInfoIn
.pipeConfig
= surf
->u
.legacy
.pipe_config
+ 1; /* +1 compared to GB_TILE_MODE */
641 AddrSurfInfoIn
.flags
.opt4Space
= 0;
642 AddrSurfInfoIn
.pTileInfo
= &AddrTileInfoIn
;
644 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
645 * the tile index, because we are expected to know it if
646 * we know the other parameters.
648 * This is something that can easily be fixed in Addrlib.
649 * For now, just figure it out here.
650 * Note that only 2D_TILE_THIN1 is handled here.
652 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
653 assert(AddrSurfInfoIn
.tileMode
== ADDR_TM_2D_TILED_THIN1
);
655 if (info
->chip_class
== SI
) {
656 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
) {
658 AddrSurfInfoIn
.tileIndex
= 11; /* 16bpp */
660 AddrSurfInfoIn
.tileIndex
= 12; /* 32bpp */
663 AddrSurfInfoIn
.tileIndex
= 14; /* 8bpp */
664 else if (surf
->bpe
== 2)
665 AddrSurfInfoIn
.tileIndex
= 15; /* 16bpp */
666 else if (surf
->bpe
== 4)
667 AddrSurfInfoIn
.tileIndex
= 16; /* 32bpp */
669 AddrSurfInfoIn
.tileIndex
= 17; /* 64bpp (and 128bpp) */
673 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
)
674 AddrSurfInfoIn
.tileIndex
= 10; /* 2D displayable */
676 AddrSurfInfoIn
.tileIndex
= 14; /* 2D non-displayable */
678 /* Addrlib doesn't set this if tileIndex is forced like above. */
679 AddrSurfInfoOut
.macroModeIndex
= cik_get_macro_tile_index(surf
);
683 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
684 surf
->num_dcc_levels
= 0;
687 surf
->dcc_alignment
= 1;
688 surf
->htile_size
= 0;
689 surf
->htile_slice_size
= 0;
690 surf
->htile_alignment
= 1;
692 const bool only_stencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) &&
693 !(surf
->flags
& RADEON_SURF_ZBUFFER
);
695 /* Calculate texture layout information. */
697 for (level
= 0; level
< config
->info
.levels
; level
++) {
698 r
= gfx6_compute_level(addrlib
, config
, surf
, false, level
, compressed
,
699 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
700 &AddrDccIn
, &AddrDccOut
, &AddrHtileIn
, &AddrHtileOut
);
707 /* Check that we actually got a TC-compatible HTILE if
708 * we requested it (only for level 0, since we're not
709 * supporting HTILE on higher mip levels anyway). */
710 assert(AddrSurfInfoOut
.tcCompatible
||
711 !AddrSurfInfoIn
.flags
.tcCompatible
||
712 AddrSurfInfoIn
.flags
.matchStencilTileCfg
);
714 if (AddrSurfInfoIn
.flags
.matchStencilTileCfg
) {
715 if (!AddrSurfInfoOut
.tcCompatible
) {
716 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
717 surf
->flags
&= ~RADEON_SURF_TC_COMPATIBLE_HTILE
;
720 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 0;
721 AddrSurfInfoIn
.tileIndex
= AddrSurfInfoOut
.tileIndex
;
722 stencil_tile_idx
= AddrSurfInfoOut
.stencilTileIdx
;
724 assert(stencil_tile_idx
>= 0);
727 r
= gfx6_surface_settings(addrlib
, info
, config
,
728 &AddrSurfInfoOut
, surf
);
734 /* Calculate texture layout information for stencil. */
735 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
736 AddrSurfInfoIn
.tileIndex
= stencil_tile_idx
;
737 AddrSurfInfoIn
.bpp
= 8;
738 AddrSurfInfoIn
.flags
.depth
= 0;
739 AddrSurfInfoIn
.flags
.stencil
= 1;
740 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
741 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
742 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.stencil_tile_split
;
744 for (level
= 0; level
< config
->info
.levels
; level
++) {
745 r
= gfx6_compute_level(addrlib
, config
, surf
, true, level
, compressed
,
746 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
747 &AddrDccIn
, &AddrDccOut
,
752 /* DB uses the depth pitch for both stencil and depth. */
754 if (surf
->u
.legacy
.stencil_level
[level
].nblk_x
!=
755 surf
->u
.legacy
.level
[level
].nblk_x
)
756 surf
->u
.legacy
.stencil_adjusted
= true;
758 surf
->u
.legacy
.level
[level
].nblk_x
=
759 surf
->u
.legacy
.stencil_level
[level
].nblk_x
;
764 r
= gfx6_surface_settings(addrlib
, info
, config
,
765 &AddrSurfInfoOut
, surf
);
770 /* For 2D modes only. */
771 if (AddrSurfInfoOut
.tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
772 surf
->u
.legacy
.stencil_tile_split
=
773 AddrSurfInfoOut
.pTileInfo
->tileSplitBytes
;
779 /* Recalculate the whole DCC miptree size including disabled levels.
780 * This is what addrlib does, but calling addrlib would be a lot more
783 if (surf
->dcc_size
&& config
->info
.levels
> 1) {
784 /* The smallest miplevels that are never compressed by DCC
785 * still read the DCC buffer via TC if the base level uses DCC,
786 * and for some reason the DCC buffer needs to be larger if
787 * the miptree uses non-zero tile_swizzle. Otherwise there are
790 * "dcc_alignment * 4" was determined by trial and error.
792 surf
->dcc_size
= align64(surf
->surf_size
>> 8,
793 surf
->dcc_alignment
* 4);
796 /* Make sure HTILE covers the whole miptree, because the shader reads
797 * TC-compatible HTILE even for levels where it's disabled by DB.
799 if (surf
->htile_size
&& config
->info
.levels
> 1)
800 surf
->htile_size
*= 2;
802 surf
->is_linear
= surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
;
803 surf
->is_displayable
= surf
->is_linear
||
804 surf
->micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
||
805 surf
->micro_tile_mode
== RADEON_MICRO_MODE_ROTATED
;
809 /* This is only called when expecting a tiled layout. */
811 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib
,
812 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
,
813 bool is_fmask
, AddrSwizzleMode
*swizzle_mode
)
815 ADDR_E_RETURNCODE ret
;
816 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin
= {0};
817 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout
= {0};
819 sin
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
);
820 sout
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
);
822 sin
.flags
= in
->flags
;
823 sin
.resourceType
= in
->resourceType
;
824 sin
.format
= in
->format
;
825 sin
.resourceLoction
= ADDR_RSRC_LOC_INVIS
;
826 /* TODO: We could allow some of these: */
827 sin
.forbiddenBlock
.micro
= 1; /* don't allow the 256B swizzle modes */
828 sin
.forbiddenBlock
.var
= 1; /* don't allow the variable-sized swizzle modes */
829 sin
.forbiddenBlock
.linear
= 1; /* don't allow linear swizzle modes */
831 sin
.width
= in
->width
;
832 sin
.height
= in
->height
;
833 sin
.numSlices
= in
->numSlices
;
834 sin
.numMipLevels
= in
->numMipLevels
;
835 sin
.numSamples
= in
->numSamples
;
836 sin
.numFrags
= in
->numFrags
;
843 ret
= Addr2GetPreferredSurfaceSetting(addrlib
, &sin
, &sout
);
847 *swizzle_mode
= sout
.swizzleMode
;
851 static int gfx9_compute_miptree(ADDR_HANDLE addrlib
,
852 struct radeon_surf
*surf
, bool compressed
,
853 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
)
855 ADDR2_MIP_INFO mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
856 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out
= {0};
857 ADDR_E_RETURNCODE ret
;
859 out
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
);
860 out
.pMipInfo
= mip_info
;
862 ret
= Addr2ComputeSurfaceInfo(addrlib
, in
, &out
);
866 if (in
->flags
.stencil
) {
867 surf
->u
.gfx9
.stencil
.swizzle_mode
= in
->swizzleMode
;
868 surf
->u
.gfx9
.stencil
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
869 out
.mipChainPitch
- 1;
870 surf
->surf_alignment
= MAX2(surf
->surf_alignment
, out
.baseAlign
);
871 surf
->u
.gfx9
.stencil_offset
= align(surf
->surf_size
, out
.baseAlign
);
872 surf
->surf_size
= surf
->u
.gfx9
.stencil_offset
+ out
.surfSize
;
876 surf
->u
.gfx9
.surf
.swizzle_mode
= in
->swizzleMode
;
877 surf
->u
.gfx9
.surf
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
878 out
.mipChainPitch
- 1;
880 /* CMASK fast clear uses these even if FMASK isn't allocated.
881 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
883 surf
->u
.gfx9
.fmask
.swizzle_mode
= surf
->u
.gfx9
.surf
.swizzle_mode
& ~0x3;
884 surf
->u
.gfx9
.fmask
.epitch
= surf
->u
.gfx9
.surf
.epitch
;
886 surf
->u
.gfx9
.surf_slice_size
= out
.sliceSize
;
887 surf
->u
.gfx9
.surf_pitch
= out
.pitch
;
888 surf
->u
.gfx9
.surf_height
= out
.height
;
889 surf
->surf_size
= out
.surfSize
;
890 surf
->surf_alignment
= out
.baseAlign
;
892 if (in
->swizzleMode
== ADDR_SW_LINEAR
) {
893 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++)
894 surf
->u
.gfx9
.offset
[i
] = mip_info
[i
].offset
;
897 if (in
->flags
.depth
) {
898 assert(in
->swizzleMode
!= ADDR_SW_LINEAR
);
901 ADDR2_COMPUTE_HTILE_INFO_INPUT hin
= {0};
902 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout
= {0};
904 hin
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT
);
905 hout
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT
);
907 hin
.hTileFlags
.pipeAligned
= 1;
908 hin
.hTileFlags
.rbAligned
= 1;
909 hin
.depthFlags
= in
->flags
;
910 hin
.swizzleMode
= in
->swizzleMode
;
911 hin
.unalignedWidth
= in
->width
;
912 hin
.unalignedHeight
= in
->height
;
913 hin
.numSlices
= in
->numSlices
;
914 hin
.numMipLevels
= in
->numMipLevels
;
916 ret
= Addr2ComputeHtileInfo(addrlib
, &hin
, &hout
);
920 surf
->u
.gfx9
.htile
.rb_aligned
= hin
.hTileFlags
.rbAligned
;
921 surf
->u
.gfx9
.htile
.pipe_aligned
= hin
.hTileFlags
.pipeAligned
;
922 surf
->htile_size
= hout
.htileBytes
;
923 surf
->htile_slice_size
= hout
.sliceSize
;
924 surf
->htile_alignment
= hout
.baseAlign
;
927 if (!(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
929 in
->swizzleMode
!= ADDR_SW_LINEAR
) {
930 ADDR2_COMPUTE_DCCINFO_INPUT din
= {0};
931 ADDR2_COMPUTE_DCCINFO_OUTPUT dout
= {0};
932 ADDR2_META_MIP_INFO meta_mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
934 din
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_INPUT
);
935 dout
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT
);
936 dout
.pMipInfo
= meta_mip_info
;
938 din
.dccKeyFlags
.pipeAligned
= 1;
939 din
.dccKeyFlags
.rbAligned
= 1;
940 din
.colorFlags
= in
->flags
;
941 din
.resourceType
= in
->resourceType
;
942 din
.swizzleMode
= in
->swizzleMode
;
944 din
.unalignedWidth
= in
->width
;
945 din
.unalignedHeight
= in
->height
;
946 din
.numSlices
= in
->numSlices
;
947 din
.numFrags
= in
->numFrags
;
948 din
.numMipLevels
= in
->numMipLevels
;
949 din
.dataSurfaceSize
= out
.surfSize
;
951 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
955 surf
->u
.gfx9
.dcc
.rb_aligned
= din
.dccKeyFlags
.rbAligned
;
956 surf
->u
.gfx9
.dcc
.pipe_aligned
= din
.dccKeyFlags
.pipeAligned
;
957 surf
->u
.gfx9
.dcc_pitch_max
= dout
.pitch
- 1;
958 surf
->dcc_size
= dout
.dccRamSize
;
959 surf
->dcc_alignment
= dout
.dccRamBaseAlign
;
960 surf
->num_dcc_levels
= in
->numMipLevels
;
962 /* Disable DCC for levels that are in the mip tail.
964 * There are two issues that this is intended to
967 * 1. Multiple mip levels may share a cache line. This
968 * can lead to corruption when switching between
969 * rendering to different mip levels because the
970 * RBs don't maintain coherency.
972 * 2. Texturing with metadata after rendering sometimes
973 * fails with corruption, probably for a similar
976 * Working around these issues for all levels in the
977 * mip tail may be overly conservative, but it's what
980 * Alternative solutions that also work but are worse:
981 * - Disable DCC entirely.
982 * - Flush TC L2 after rendering.
984 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++) {
985 if (meta_mip_info
[i
].inMiptail
) {
986 surf
->num_dcc_levels
= i
;
991 if (!surf
->num_dcc_levels
)
996 if (in
->numSamples
> 1) {
997 ADDR2_COMPUTE_FMASK_INFO_INPUT fin
= {0};
998 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
1000 fin
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT
);
1001 fout
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT
);
1003 ret
= gfx9_get_preferred_swizzle_mode(addrlib
, in
, true, &fin
.swizzleMode
);
1007 fin
.unalignedWidth
= in
->width
;
1008 fin
.unalignedHeight
= in
->height
;
1009 fin
.numSlices
= in
->numSlices
;
1010 fin
.numSamples
= in
->numSamples
;
1011 fin
.numFrags
= in
->numFrags
;
1013 ret
= Addr2ComputeFmaskInfo(addrlib
, &fin
, &fout
);
1017 surf
->u
.gfx9
.fmask
.swizzle_mode
= fin
.swizzleMode
;
1018 surf
->u
.gfx9
.fmask
.epitch
= fout
.pitch
- 1;
1019 surf
->u
.gfx9
.fmask_size
= fout
.fmaskBytes
;
1020 surf
->u
.gfx9
.fmask_alignment
= fout
.baseAlign
;
1024 if (in
->swizzleMode
!= ADDR_SW_LINEAR
) {
1025 ADDR2_COMPUTE_CMASK_INFO_INPUT cin
= {0};
1026 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout
= {0};
1028 cin
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT
);
1029 cout
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT
);
1031 cin
.cMaskFlags
.pipeAligned
= 1;
1032 cin
.cMaskFlags
.rbAligned
= 1;
1033 cin
.colorFlags
= in
->flags
;
1034 cin
.resourceType
= in
->resourceType
;
1035 cin
.unalignedWidth
= in
->width
;
1036 cin
.unalignedHeight
= in
->height
;
1037 cin
.numSlices
= in
->numSlices
;
1039 if (in
->numSamples
> 1)
1040 cin
.swizzleMode
= surf
->u
.gfx9
.fmask
.swizzle_mode
;
1042 cin
.swizzleMode
= in
->swizzleMode
;
1044 ret
= Addr2ComputeCmaskInfo(addrlib
, &cin
, &cout
);
1048 surf
->u
.gfx9
.cmask
.rb_aligned
= cin
.cMaskFlags
.rbAligned
;
1049 surf
->u
.gfx9
.cmask
.pipe_aligned
= cin
.cMaskFlags
.pipeAligned
;
1050 surf
->u
.gfx9
.cmask_size
= cout
.cmaskBytes
;
1051 surf
->u
.gfx9
.cmask_alignment
= cout
.baseAlign
;
1058 static int gfx9_compute_surface(ADDR_HANDLE addrlib
,
1059 const struct ac_surf_config
*config
,
1060 enum radeon_surf_mode mode
,
1061 struct radeon_surf
*surf
)
1064 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
1067 assert(!(surf
->flags
& RADEON_SURF_FMASK
));
1069 AddrSurfInfoIn
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT
);
1071 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
1073 /* The format must be set correctly for the allocation of compressed
1074 * textures to work. In other cases, setting the bpp is sufficient. */
1076 switch (surf
->bpe
) {
1078 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
1081 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
1087 AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
1090 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
1091 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
1092 AddrSurfInfoIn
.flags
.display
= (surf
->flags
& RADEON_SURF_SCANOUT
) != 0;
1093 /* flags.texture currently refers to TC-compatible HTILE */
1094 AddrSurfInfoIn
.flags
.texture
= AddrSurfInfoIn
.flags
.color
||
1095 surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1096 AddrSurfInfoIn
.flags
.opt4space
= 1;
1098 AddrSurfInfoIn
.numMipLevels
= config
->info
.levels
;
1099 AddrSurfInfoIn
.numSamples
= config
->info
.samples
? config
->info
.samples
: 1;
1100 AddrSurfInfoIn
.numFrags
= AddrSurfInfoIn
.numSamples
;
1102 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1103 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1104 * must sample 1D textures as 2D. */
1106 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_3D
;
1108 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_2D
;
1110 AddrSurfInfoIn
.width
= config
->info
.width
;
1111 AddrSurfInfoIn
.height
= config
->info
.height
;
1114 AddrSurfInfoIn
.numSlices
= config
->info
.depth
;
1115 else if (config
->is_cube
)
1116 AddrSurfInfoIn
.numSlices
= 6;
1118 AddrSurfInfoIn
.numSlices
= config
->info
.array_size
;
1121 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1122 assert(config
->info
.samples
<= 1);
1123 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1124 AddrSurfInfoIn
.swizzleMode
= ADDR_SW_LINEAR
;
1127 case RADEON_SURF_MODE_1D
:
1128 case RADEON_SURF_MODE_2D
:
1129 if (surf
->flags
& RADEON_SURF_IMPORTED
) {
1130 AddrSurfInfoIn
.swizzleMode
= surf
->u
.gfx9
.surf
.swizzle_mode
;
1134 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
, false,
1135 &AddrSurfInfoIn
.swizzleMode
);
1144 surf
->u
.gfx9
.resource_type
= AddrSurfInfoIn
.resourceType
;
1145 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
1147 surf
->num_dcc_levels
= 0;
1148 surf
->surf_size
= 0;
1150 surf
->htile_size
= 0;
1151 surf
->htile_slice_size
= 0;
1152 surf
->u
.gfx9
.surf_offset
= 0;
1153 surf
->u
.gfx9
.stencil_offset
= 0;
1154 surf
->u
.gfx9
.fmask_size
= 0;
1155 surf
->u
.gfx9
.cmask_size
= 0;
1157 /* Calculate texture layout information. */
1158 r
= gfx9_compute_miptree(addrlib
, surf
, compressed
, &AddrSurfInfoIn
);
1162 /* Calculate texture layout information for stencil. */
1163 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
1164 AddrSurfInfoIn
.flags
.stencil
= 1;
1165 AddrSurfInfoIn
.bpp
= 8;
1167 if (!AddrSurfInfoIn
.flags
.depth
) {
1168 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
, false,
1169 &AddrSurfInfoIn
.swizzleMode
);
1173 AddrSurfInfoIn
.flags
.depth
= 0;
1175 r
= gfx9_compute_miptree(addrlib
, surf
, compressed
, &AddrSurfInfoIn
);
1180 surf
->is_linear
= surf
->u
.gfx9
.surf
.swizzle_mode
== ADDR_SW_LINEAR
;
1182 /* Query whether the surface is displayable. */
1183 bool displayable
= false;
1184 r
= Addr2IsValidDisplaySwizzleMode(addrlib
, surf
->u
.gfx9
.surf
.swizzle_mode
,
1185 surf
->bpe
* 8, &displayable
);
1188 surf
->is_displayable
= displayable
;
1190 switch (surf
->u
.gfx9
.surf
.swizzle_mode
) {
1192 case ADDR_SW_256B_S
:
1194 case ADDR_SW_64KB_S
:
1196 case ADDR_SW_64KB_S_T
:
1197 case ADDR_SW_4KB_S_X
:
1198 case ADDR_SW_64KB_S_X
:
1199 case ADDR_SW_VAR_S_X
:
1200 surf
->micro_tile_mode
= RADEON_MICRO_MODE_THIN
;
1204 case ADDR_SW_LINEAR
:
1205 case ADDR_SW_256B_D
:
1207 case ADDR_SW_64KB_D
:
1209 case ADDR_SW_64KB_D_T
:
1210 case ADDR_SW_4KB_D_X
:
1211 case ADDR_SW_64KB_D_X
:
1212 case ADDR_SW_VAR_D_X
:
1213 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DISPLAY
;
1217 case ADDR_SW_256B_R
:
1219 case ADDR_SW_64KB_R
:
1221 case ADDR_SW_64KB_R_T
:
1222 case ADDR_SW_4KB_R_X
:
1223 case ADDR_SW_64KB_R_X
:
1224 case ADDR_SW_VAR_R_X
:
1225 surf
->micro_tile_mode
= RADEON_MICRO_MODE_ROTATED
;
1230 case ADDR_SW_64KB_Z
:
1232 case ADDR_SW_64KB_Z_T
:
1233 case ADDR_SW_4KB_Z_X
:
1234 case ADDR_SW_64KB_Z_X
:
1235 case ADDR_SW_VAR_Z_X
:
1236 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DEPTH
;
1246 int ac_compute_surface(ADDR_HANDLE addrlib
, const struct radeon_info
*info
,
1247 const struct ac_surf_config
*config
,
1248 enum radeon_surf_mode mode
,
1249 struct radeon_surf
*surf
)
1253 r
= surf_config_sanity(config
);
1257 if (info
->chip_class
>= GFX9
)
1258 return gfx9_compute_surface(addrlib
, config
, mode
, surf
);
1260 return gfx6_compute_surface(addrlib
, info
, config
, mode
, surf
);