2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
40 #include "drm-uapi/amdgpu_drm.h"
42 #include "addrlib/inc/addrinterface.h"
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
52 static void *ADDR_API
allocSysMem(const ADDR_ALLOCSYSMEM_INPUT
* pInput
)
54 return malloc(pInput
->sizeInBytes
);
57 static ADDR_E_RETURNCODE ADDR_API
freeSysMem(const ADDR_FREESYSMEM_INPUT
* pInput
)
59 free(pInput
->pVirtAddr
);
63 ADDR_HANDLE
amdgpu_addr_create(const struct radeon_info
*info
,
64 const struct amdgpu_gpu_info
*amdinfo
,
65 uint64_t *max_alignment
)
67 ADDR_CREATE_INPUT addrCreateInput
= {0};
68 ADDR_CREATE_OUTPUT addrCreateOutput
= {0};
69 ADDR_REGISTER_VALUE regValue
= {0};
70 ADDR_CREATE_FLAGS createFlags
= {{0}};
71 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput
= {0};
72 ADDR_E_RETURNCODE addrRet
;
74 addrCreateInput
.size
= sizeof(ADDR_CREATE_INPUT
);
75 addrCreateOutput
.size
= sizeof(ADDR_CREATE_OUTPUT
);
77 regValue
.gbAddrConfig
= amdinfo
->gb_addr_cfg
;
78 createFlags
.value
= 0;
80 addrCreateInput
.chipFamily
= info
->family_id
;
81 addrCreateInput
.chipRevision
= info
->chip_external_rev
;
83 if (addrCreateInput
.chipFamily
== FAMILY_UNKNOWN
)
86 if (addrCreateInput
.chipFamily
>= FAMILY_AI
) {
87 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_ARCTICISLAND
;
89 regValue
.noOfBanks
= amdinfo
->mc_arb_ramcfg
& 0x3;
90 regValue
.noOfRanks
= (amdinfo
->mc_arb_ramcfg
& 0x4) >> 2;
92 regValue
.backendDisables
= amdinfo
->enabled_rb_pipes_mask
;
93 regValue
.pTileConfig
= amdinfo
->gb_tile_mode
;
94 regValue
.noOfEntries
= ARRAY_SIZE(amdinfo
->gb_tile_mode
);
95 if (addrCreateInput
.chipFamily
== FAMILY_SI
) {
96 regValue
.pMacroTileConfig
= NULL
;
97 regValue
.noOfMacroEntries
= 0;
99 regValue
.pMacroTileConfig
= amdinfo
->gb_macro_tile_mode
;
100 regValue
.noOfMacroEntries
= ARRAY_SIZE(amdinfo
->gb_macro_tile_mode
);
103 createFlags
.useTileIndex
= 1;
104 createFlags
.useHtileSliceAlign
= 1;
106 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_SOUTHERNISLAND
;
109 addrCreateInput
.callbacks
.allocSysMem
= allocSysMem
;
110 addrCreateInput
.callbacks
.freeSysMem
= freeSysMem
;
111 addrCreateInput
.callbacks
.debugPrint
= 0;
112 addrCreateInput
.createFlags
= createFlags
;
113 addrCreateInput
.regValue
= regValue
;
115 addrRet
= AddrCreate(&addrCreateInput
, &addrCreateOutput
);
116 if (addrRet
!= ADDR_OK
)
120 addrRet
= AddrGetMaxAlignments(addrCreateOutput
.hLib
, &addrGetMaxAlignmentsOutput
);
121 if (addrRet
== ADDR_OK
){
122 *max_alignment
= addrGetMaxAlignmentsOutput
.baseAlign
;
125 return addrCreateOutput
.hLib
;
128 static int surf_config_sanity(const struct ac_surf_config
*config
,
131 /* FMASK is allocated together with the color surface and can't be
132 * allocated separately.
134 assert(!(flags
& RADEON_SURF_FMASK
));
135 if (flags
& RADEON_SURF_FMASK
)
138 /* all dimension must be at least 1 ! */
139 if (!config
->info
.width
|| !config
->info
.height
|| !config
->info
.depth
||
140 !config
->info
.array_size
|| !config
->info
.levels
)
143 switch (config
->info
.samples
) {
151 if (flags
& RADEON_SURF_Z_OR_SBUFFER
)
158 if (!(flags
& RADEON_SURF_Z_OR_SBUFFER
)) {
159 switch (config
->info
.storage_samples
) {
171 if (config
->is_3d
&& config
->info
.array_size
> 1)
173 if (config
->is_cube
&& config
->info
.depth
> 1)
179 static int gfx6_compute_level(ADDR_HANDLE addrlib
,
180 const struct ac_surf_config
*config
,
181 struct radeon_surf
*surf
, bool is_stencil
,
182 unsigned level
, bool compressed
,
183 ADDR_COMPUTE_SURFACE_INFO_INPUT
*AddrSurfInfoIn
,
184 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
*AddrSurfInfoOut
,
185 ADDR_COMPUTE_DCCINFO_INPUT
*AddrDccIn
,
186 ADDR_COMPUTE_DCCINFO_OUTPUT
*AddrDccOut
,
187 ADDR_COMPUTE_HTILE_INFO_INPUT
*AddrHtileIn
,
188 ADDR_COMPUTE_HTILE_INFO_OUTPUT
*AddrHtileOut
)
190 struct legacy_surf_level
*surf_level
;
191 ADDR_E_RETURNCODE ret
;
193 AddrSurfInfoIn
->mipLevel
= level
;
194 AddrSurfInfoIn
->width
= u_minify(config
->info
.width
, level
);
195 AddrSurfInfoIn
->height
= u_minify(config
->info
.height
, level
);
197 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
198 * because GFX9 needs linear alignment of 256 bytes.
200 if (config
->info
.levels
== 1 &&
201 AddrSurfInfoIn
->tileMode
== ADDR_TM_LINEAR_ALIGNED
&&
202 AddrSurfInfoIn
->bpp
&&
203 util_is_power_of_two_or_zero(AddrSurfInfoIn
->bpp
)) {
204 unsigned alignment
= 256 / (AddrSurfInfoIn
->bpp
/ 8);
206 AddrSurfInfoIn
->width
= align(AddrSurfInfoIn
->width
, alignment
);
209 /* addrlib assumes the bytes/pixel is a divisor of 64, which is not
210 * true for r32g32b32 formats. */
211 if (AddrSurfInfoIn
->bpp
== 96) {
212 assert(config
->info
.levels
== 1);
213 assert(AddrSurfInfoIn
->tileMode
== ADDR_TM_LINEAR_ALIGNED
);
215 /* The least common multiple of 64 bytes and 12 bytes/pixel is
216 * 192 bytes, or 16 pixels. */
217 AddrSurfInfoIn
->width
= align(AddrSurfInfoIn
->width
, 16);
221 AddrSurfInfoIn
->numSlices
= u_minify(config
->info
.depth
, level
);
222 else if (config
->is_cube
)
223 AddrSurfInfoIn
->numSlices
= 6;
225 AddrSurfInfoIn
->numSlices
= config
->info
.array_size
;
228 /* Set the base level pitch. This is needed for calculation
229 * of non-zero levels. */
231 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.stencil_level
[0].nblk_x
;
233 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.level
[0].nblk_x
;
235 /* Convert blocks to pixels for compressed formats. */
237 AddrSurfInfoIn
->basePitch
*= surf
->blk_w
;
240 ret
= AddrComputeSurfaceInfo(addrlib
,
243 if (ret
!= ADDR_OK
) {
247 surf_level
= is_stencil
? &surf
->u
.legacy
.stencil_level
[level
] : &surf
->u
.legacy
.level
[level
];
248 surf_level
->offset
= align64(surf
->surf_size
, AddrSurfInfoOut
->baseAlign
);
249 surf_level
->slice_size_dw
= AddrSurfInfoOut
->sliceSize
/ 4;
250 surf_level
->nblk_x
= AddrSurfInfoOut
->pitch
;
251 surf_level
->nblk_y
= AddrSurfInfoOut
->height
;
253 switch (AddrSurfInfoOut
->tileMode
) {
254 case ADDR_TM_LINEAR_ALIGNED
:
255 surf_level
->mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
257 case ADDR_TM_1D_TILED_THIN1
:
258 surf_level
->mode
= RADEON_SURF_MODE_1D
;
260 case ADDR_TM_2D_TILED_THIN1
:
261 surf_level
->mode
= RADEON_SURF_MODE_2D
;
268 surf
->u
.legacy
.stencil_tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
270 surf
->u
.legacy
.tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
272 surf
->surf_size
= surf_level
->offset
+ AddrSurfInfoOut
->surfSize
;
274 /* Clear DCC fields at the beginning. */
275 surf_level
->dcc_offset
= 0;
277 /* The previous level's flag tells us if we can use DCC for this level. */
278 if (AddrSurfInfoIn
->flags
.dccCompatible
&&
279 (level
== 0 || AddrDccOut
->subLvlCompressible
)) {
280 bool prev_level_clearable
= level
== 0 ||
281 AddrDccOut
->dccRamSizeAligned
;
283 AddrDccIn
->colorSurfSize
= AddrSurfInfoOut
->surfSize
;
284 AddrDccIn
->tileMode
= AddrSurfInfoOut
->tileMode
;
285 AddrDccIn
->tileInfo
= *AddrSurfInfoOut
->pTileInfo
;
286 AddrDccIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
287 AddrDccIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
289 ret
= AddrComputeDccInfo(addrlib
,
293 if (ret
== ADDR_OK
) {
294 surf_level
->dcc_offset
= surf
->dcc_size
;
295 surf
->num_dcc_levels
= level
+ 1;
296 surf
->dcc_size
= surf_level
->dcc_offset
+ AddrDccOut
->dccRamSize
;
297 surf
->dcc_alignment
= MAX2(surf
->dcc_alignment
, AddrDccOut
->dccRamBaseAlign
);
299 /* If the DCC size of a subresource (1 mip level or 1 slice)
300 * is not aligned, the DCC memory layout is not contiguous for
301 * that subresource, which means we can't use fast clear.
303 * We only do fast clears for whole mipmap levels. If we did
304 * per-slice fast clears, the same restriction would apply.
305 * (i.e. only compute the slice size and see if it's aligned)
307 * The last level can be non-contiguous and still be clearable
308 * if it's interleaved with the next level that doesn't exist.
310 if (AddrDccOut
->dccRamSizeAligned
||
311 (prev_level_clearable
&& level
== config
->info
.levels
- 1))
312 surf_level
->dcc_fast_clear_size
= AddrDccOut
->dccFastClearSize
;
314 surf_level
->dcc_fast_clear_size
= 0;
316 /* Compute the DCC slice size because addrlib doesn't
317 * provide this info. As DCC memory is linear (each
318 * slice is the same size) it's easy to compute.
320 surf
->dcc_slice_size
= AddrDccOut
->dccRamSize
/ config
->info
.array_size
;
322 /* For arrays, we have to compute the DCC info again
323 * with one slice size to get a correct fast clear
326 if (config
->info
.array_size
> 1) {
327 AddrDccIn
->colorSurfSize
= AddrSurfInfoOut
->sliceSize
;
328 AddrDccIn
->tileMode
= AddrSurfInfoOut
->tileMode
;
329 AddrDccIn
->tileInfo
= *AddrSurfInfoOut
->pTileInfo
;
330 AddrDccIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
331 AddrDccIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
333 ret
= AddrComputeDccInfo(addrlib
,
334 AddrDccIn
, AddrDccOut
);
335 if (ret
== ADDR_OK
) {
336 /* If the DCC memory isn't properly
337 * aligned, the data are interleaved
340 if (AddrDccOut
->dccRamSizeAligned
)
341 surf_level
->dcc_slice_fast_clear_size
= AddrDccOut
->dccFastClearSize
;
343 surf_level
->dcc_slice_fast_clear_size
= 0;
346 surf_level
->dcc_slice_fast_clear_size
= surf_level
->dcc_fast_clear_size
;
353 AddrSurfInfoIn
->flags
.depth
&&
354 surf_level
->mode
== RADEON_SURF_MODE_2D
&&
356 !(surf
->flags
& RADEON_SURF_NO_HTILE
)) {
357 AddrHtileIn
->flags
.tcCompatible
= AddrSurfInfoOut
->tcCompatible
;
358 AddrHtileIn
->pitch
= AddrSurfInfoOut
->pitch
;
359 AddrHtileIn
->height
= AddrSurfInfoOut
->height
;
360 AddrHtileIn
->numSlices
= AddrSurfInfoOut
->depth
;
361 AddrHtileIn
->blockWidth
= ADDR_HTILE_BLOCKSIZE_8
;
362 AddrHtileIn
->blockHeight
= ADDR_HTILE_BLOCKSIZE_8
;
363 AddrHtileIn
->pTileInfo
= AddrSurfInfoOut
->pTileInfo
;
364 AddrHtileIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
365 AddrHtileIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
367 ret
= AddrComputeHtileInfo(addrlib
,
371 if (ret
== ADDR_OK
) {
372 surf
->htile_size
= AddrHtileOut
->htileBytes
;
373 surf
->htile_slice_size
= AddrHtileOut
->sliceSize
;
374 surf
->htile_alignment
= AddrHtileOut
->baseAlign
;
381 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
382 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
383 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
385 static void gfx6_set_micro_tile_mode(struct radeon_surf
*surf
,
386 const struct radeon_info
*info
)
388 uint32_t tile_mode
= info
->si_tile_mode_array
[surf
->u
.legacy
.tiling_index
[0]];
390 if (info
->chip_class
>= GFX7
)
391 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE_NEW(tile_mode
);
393 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE(tile_mode
);
396 static unsigned cik_get_macro_tile_index(struct radeon_surf
*surf
)
398 unsigned index
, tileb
;
400 tileb
= 8 * 8 * surf
->bpe
;
401 tileb
= MIN2(surf
->u
.legacy
.tile_split
, tileb
);
403 for (index
= 0; tileb
> 64; index
++)
410 static bool get_display_flag(const struct ac_surf_config
*config
,
411 const struct radeon_surf
*surf
)
413 unsigned num_channels
= config
->info
.num_channels
;
414 unsigned bpe
= surf
->bpe
;
416 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
417 surf
->flags
& RADEON_SURF_SCANOUT
&&
418 config
->info
.samples
<= 1 &&
419 surf
->blk_w
<= 2 && surf
->blk_h
== 1) {
421 if (surf
->blk_w
== 2 && surf
->blk_h
== 1)
424 if (/* RGBA8 or RGBA16F */
425 (bpe
>= 4 && bpe
<= 8 && num_channels
== 4) ||
426 /* R5G6B5 or R5G5B5A1 */
427 (bpe
== 2 && num_channels
>= 3) ||
429 (bpe
== 1 && num_channels
== 1))
436 * This must be called after the first level is computed.
438 * Copy surface-global settings like pipe/bank config from level 0 surface
439 * computation, and compute tile swizzle.
441 static int gfx6_surface_settings(ADDR_HANDLE addrlib
,
442 const struct radeon_info
*info
,
443 const struct ac_surf_config
*config
,
444 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* csio
,
445 struct radeon_surf
*surf
)
447 surf
->surf_alignment
= csio
->baseAlign
;
448 surf
->u
.legacy
.pipe_config
= csio
->pTileInfo
->pipeConfig
- 1;
449 gfx6_set_micro_tile_mode(surf
, info
);
451 /* For 2D modes only. */
452 if (csio
->tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
453 surf
->u
.legacy
.bankw
= csio
->pTileInfo
->bankWidth
;
454 surf
->u
.legacy
.bankh
= csio
->pTileInfo
->bankHeight
;
455 surf
->u
.legacy
.mtilea
= csio
->pTileInfo
->macroAspectRatio
;
456 surf
->u
.legacy
.tile_split
= csio
->pTileInfo
->tileSplitBytes
;
457 surf
->u
.legacy
.num_banks
= csio
->pTileInfo
->banks
;
458 surf
->u
.legacy
.macro_tile_index
= csio
->macroModeIndex
;
460 surf
->u
.legacy
.macro_tile_index
= 0;
463 /* Compute tile swizzle. */
464 /* TODO: fix tile swizzle with mipmapping for GFX6 */
465 if ((info
->chip_class
>= GFX7
|| config
->info
.levels
== 1) &&
466 config
->info
.surf_index
&&
467 surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
&&
468 !(surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
| RADEON_SURF_SHAREABLE
)) &&
469 !get_display_flag(config
, surf
)) {
470 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn
= {0};
471 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut
= {0};
473 AddrBaseSwizzleIn
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
474 AddrBaseSwizzleOut
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
476 AddrBaseSwizzleIn
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
477 AddrBaseSwizzleIn
.tileIndex
= csio
->tileIndex
;
478 AddrBaseSwizzleIn
.macroModeIndex
= csio
->macroModeIndex
;
479 AddrBaseSwizzleIn
.pTileInfo
= csio
->pTileInfo
;
480 AddrBaseSwizzleIn
.tileMode
= csio
->tileMode
;
482 int r
= AddrComputeBaseSwizzle(addrlib
, &AddrBaseSwizzleIn
,
483 &AddrBaseSwizzleOut
);
487 assert(AddrBaseSwizzleOut
.tileSwizzle
<=
488 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
489 surf
->tile_swizzle
= AddrBaseSwizzleOut
.tileSwizzle
;
494 static void ac_compute_cmask(const struct radeon_info
*info
,
495 const struct ac_surf_config
*config
,
496 struct radeon_surf
*surf
)
498 unsigned pipe_interleave_bytes
= info
->pipe_interleave_bytes
;
499 unsigned num_pipes
= info
->num_tile_pipes
;
500 unsigned cl_width
, cl_height
;
502 if (surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
||
503 (config
->info
.samples
>= 2 && !surf
->fmask_size
))
506 assert(info
->chip_class
<= GFX8
);
521 case 16: /* Hawaii */
530 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
532 unsigned width
= align(surf
->u
.legacy
.level
[0].nblk_x
, cl_width
*8);
533 unsigned height
= align(surf
->u
.legacy
.level
[0].nblk_y
, cl_height
*8);
534 unsigned slice_elements
= (width
* height
) / (8*8);
536 /* Each element of CMASK is a nibble. */
537 unsigned slice_bytes
= slice_elements
/ 2;
539 surf
->u
.legacy
.cmask_slice_tile_max
= (width
* height
) / (128*128);
540 if (surf
->u
.legacy
.cmask_slice_tile_max
)
541 surf
->u
.legacy
.cmask_slice_tile_max
-= 1;
545 num_layers
= config
->info
.depth
;
546 else if (config
->is_cube
)
549 num_layers
= config
->info
.array_size
;
551 surf
->cmask_alignment
= MAX2(256, base_align
);
552 surf
->cmask_slice_size
= align(slice_bytes
, base_align
);
553 surf
->cmask_size
= surf
->cmask_slice_size
* num_layers
;
557 * Fill in the tiling information in \p surf based on the given surface config.
559 * The following fields of \p surf must be initialized by the caller:
560 * blk_w, blk_h, bpe, flags.
562 static int gfx6_compute_surface(ADDR_HANDLE addrlib
,
563 const struct radeon_info
*info
,
564 const struct ac_surf_config
*config
,
565 enum radeon_surf_mode mode
,
566 struct radeon_surf
*surf
)
570 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
571 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut
= {0};
572 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn
= {0};
573 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut
= {0};
574 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn
= {0};
575 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut
= {0};
576 ADDR_TILEINFO AddrTileInfoIn
= {0};
577 ADDR_TILEINFO AddrTileInfoOut
= {0};
580 AddrSurfInfoIn
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT
);
581 AddrSurfInfoOut
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT
);
582 AddrDccIn
.size
= sizeof(ADDR_COMPUTE_DCCINFO_INPUT
);
583 AddrDccOut
.size
= sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT
);
584 AddrHtileIn
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT
);
585 AddrHtileOut
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT
);
586 AddrSurfInfoOut
.pTileInfo
= &AddrTileInfoOut
;
588 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
590 /* MSAA requires 2D tiling. */
591 if (config
->info
.samples
> 1)
592 mode
= RADEON_SURF_MODE_2D
;
594 /* DB doesn't support linear layouts. */
595 if (surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
) &&
596 mode
< RADEON_SURF_MODE_1D
)
597 mode
= RADEON_SURF_MODE_1D
;
599 /* Set the requested tiling mode. */
601 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
602 AddrSurfInfoIn
.tileMode
= ADDR_TM_LINEAR_ALIGNED
;
604 case RADEON_SURF_MODE_1D
:
605 AddrSurfInfoIn
.tileMode
= ADDR_TM_1D_TILED_THIN1
;
607 case RADEON_SURF_MODE_2D
:
608 AddrSurfInfoIn
.tileMode
= ADDR_TM_2D_TILED_THIN1
;
614 /* The format must be set correctly for the allocation of compressed
615 * textures to work. In other cases, setting the bpp is sufficient.
620 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
623 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
630 AddrDccIn
.bpp
= AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
633 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numSamples
=
634 MAX2(1, config
->info
.samples
);
635 AddrSurfInfoIn
.tileIndex
= -1;
637 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)) {
638 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numFrags
=
639 MAX2(1, config
->info
.storage_samples
);
642 /* Set the micro tile type. */
643 if (surf
->flags
& RADEON_SURF_SCANOUT
)
644 AddrSurfInfoIn
.tileType
= ADDR_DISPLAYABLE
;
645 else if (surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)
646 AddrSurfInfoIn
.tileType
= ADDR_DEPTH_SAMPLE_ORDER
;
648 AddrSurfInfoIn
.tileType
= ADDR_NON_DISPLAYABLE
;
650 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
651 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
652 AddrSurfInfoIn
.flags
.cube
= config
->is_cube
;
653 AddrSurfInfoIn
.flags
.display
= get_display_flag(config
, surf
);
654 AddrSurfInfoIn
.flags
.pow2Pad
= config
->info
.levels
> 1;
655 AddrSurfInfoIn
.flags
.tcCompatible
= info
->chip_class
>= GFX8
&&
656 AddrSurfInfoIn
.flags
.depth
;
658 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
659 * requested, because TC-compatible HTILE requires 2D tiling.
661 AddrSurfInfoIn
.flags
.opt4Space
= !AddrSurfInfoIn
.flags
.tcCompatible
&&
662 !AddrSurfInfoIn
.flags
.fmask
&&
663 config
->info
.samples
<= 1 &&
664 (surf
->flags
& RADEON_SURF_OPTIMIZE_FOR_SPACE
);
667 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
669 * - Mipmapped array textures have low performance (discovered by a closed
672 AddrSurfInfoIn
.flags
.dccCompatible
=
673 info
->chip_class
>= GFX8
&&
674 info
->has_graphics
&& /* disable DCC on compute-only chips */
675 !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
676 !(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
678 ((config
->info
.array_size
== 1 && config
->info
.depth
== 1) ||
679 config
->info
.levels
== 1);
681 AddrSurfInfoIn
.flags
.noStencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) == 0;
682 AddrSurfInfoIn
.flags
.compressZ
= !!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
684 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
685 * for Z and stencil. This can cause a number of problems which we work
688 * - a depth part that is incompatible with mipmapped texturing
689 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
690 * incorrect tiling applied to the stencil part, stencil buffer
691 * memory accesses that go out of bounds) even without mipmapping
693 * Some piglit tests that are prone to different types of related
695 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
696 * ./bin/framebuffer-blit-levels {draw,read} stencil
697 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
698 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
699 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
701 int stencil_tile_idx
= -1;
703 if (AddrSurfInfoIn
.flags
.depth
&& !AddrSurfInfoIn
.flags
.noStencil
&&
704 (config
->info
.levels
> 1 || info
->family
== CHIP_STONEY
)) {
705 /* Compute stencilTileIdx that is compatible with the (depth)
706 * tileIdx. This degrades the depth surface if necessary to
707 * ensure that a matching stencilTileIdx exists. */
708 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 1;
710 /* Keep the depth mip-tail compatible with texturing. */
711 AddrSurfInfoIn
.flags
.noStencil
= 1;
714 /* Set preferred macrotile parameters. This is usually required
715 * for shared resources. This is for 2D tiling only. */
716 if (AddrSurfInfoIn
.tileMode
>= ADDR_TM_2D_TILED_THIN1
&&
717 surf
->u
.legacy
.bankw
&& surf
->u
.legacy
.bankh
&&
718 surf
->u
.legacy
.mtilea
&& surf
->u
.legacy
.tile_split
) {
719 /* If any of these parameters are incorrect, the calculation
721 AddrTileInfoIn
.banks
= surf
->u
.legacy
.num_banks
;
722 AddrTileInfoIn
.bankWidth
= surf
->u
.legacy
.bankw
;
723 AddrTileInfoIn
.bankHeight
= surf
->u
.legacy
.bankh
;
724 AddrTileInfoIn
.macroAspectRatio
= surf
->u
.legacy
.mtilea
;
725 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.tile_split
;
726 AddrTileInfoIn
.pipeConfig
= surf
->u
.legacy
.pipe_config
+ 1; /* +1 compared to GB_TILE_MODE */
727 AddrSurfInfoIn
.flags
.opt4Space
= 0;
728 AddrSurfInfoIn
.pTileInfo
= &AddrTileInfoIn
;
730 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
731 * the tile index, because we are expected to know it if
732 * we know the other parameters.
734 * This is something that can easily be fixed in Addrlib.
735 * For now, just figure it out here.
736 * Note that only 2D_TILE_THIN1 is handled here.
738 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
739 assert(AddrSurfInfoIn
.tileMode
== ADDR_TM_2D_TILED_THIN1
);
741 if (info
->chip_class
== GFX6
) {
742 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
) {
744 AddrSurfInfoIn
.tileIndex
= 11; /* 16bpp */
746 AddrSurfInfoIn
.tileIndex
= 12; /* 32bpp */
749 AddrSurfInfoIn
.tileIndex
= 14; /* 8bpp */
750 else if (surf
->bpe
== 2)
751 AddrSurfInfoIn
.tileIndex
= 15; /* 16bpp */
752 else if (surf
->bpe
== 4)
753 AddrSurfInfoIn
.tileIndex
= 16; /* 32bpp */
755 AddrSurfInfoIn
.tileIndex
= 17; /* 64bpp (and 128bpp) */
759 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
)
760 AddrSurfInfoIn
.tileIndex
= 10; /* 2D displayable */
762 AddrSurfInfoIn
.tileIndex
= 14; /* 2D non-displayable */
764 /* Addrlib doesn't set this if tileIndex is forced like above. */
765 AddrSurfInfoOut
.macroModeIndex
= cik_get_macro_tile_index(surf
);
769 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
770 surf
->num_dcc_levels
= 0;
773 surf
->dcc_alignment
= 1;
774 surf
->htile_size
= 0;
775 surf
->htile_slice_size
= 0;
776 surf
->htile_alignment
= 1;
777 surf
->tc_compatible_htile_allowed
= AddrSurfInfoIn
.flags
.tcCompatible
;
779 const bool only_stencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) &&
780 !(surf
->flags
& RADEON_SURF_ZBUFFER
);
782 /* Calculate texture layout information. */
784 for (level
= 0; level
< config
->info
.levels
; level
++) {
785 r
= gfx6_compute_level(addrlib
, config
, surf
, false, level
, compressed
,
786 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
787 &AddrDccIn
, &AddrDccOut
, &AddrHtileIn
, &AddrHtileOut
);
794 if (!AddrSurfInfoOut
.tcCompatible
)
795 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
797 if (!AddrSurfInfoOut
.tcCompatible
|| !surf
->htile_size
)
798 surf
->tc_compatible_htile_allowed
= false;
800 if (AddrSurfInfoIn
.flags
.matchStencilTileCfg
) {
801 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 0;
802 AddrSurfInfoIn
.tileIndex
= AddrSurfInfoOut
.tileIndex
;
803 stencil_tile_idx
= AddrSurfInfoOut
.stencilTileIdx
;
805 assert(stencil_tile_idx
>= 0);
808 r
= gfx6_surface_settings(addrlib
, info
, config
,
809 &AddrSurfInfoOut
, surf
);
815 /* Calculate texture layout information for stencil. */
816 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
817 AddrSurfInfoIn
.tileIndex
= stencil_tile_idx
;
818 AddrSurfInfoIn
.bpp
= 8;
819 AddrSurfInfoIn
.flags
.depth
= 0;
820 AddrSurfInfoIn
.flags
.stencil
= 1;
821 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
822 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
823 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.stencil_tile_split
;
825 for (level
= 0; level
< config
->info
.levels
; level
++) {
826 r
= gfx6_compute_level(addrlib
, config
, surf
, true, level
, compressed
,
827 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
828 &AddrDccIn
, &AddrDccOut
,
833 /* DB uses the depth pitch for both stencil and depth. */
835 if (surf
->u
.legacy
.stencil_level
[level
].nblk_x
!=
836 surf
->u
.legacy
.level
[level
].nblk_x
)
837 surf
->u
.legacy
.stencil_adjusted
= true;
839 surf
->u
.legacy
.level
[level
].nblk_x
=
840 surf
->u
.legacy
.stencil_level
[level
].nblk_x
;
845 r
= gfx6_surface_settings(addrlib
, info
, config
,
846 &AddrSurfInfoOut
, surf
);
851 /* For 2D modes only. */
852 if (AddrSurfInfoOut
.tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
853 surf
->u
.legacy
.stencil_tile_split
=
854 AddrSurfInfoOut
.pTileInfo
->tileSplitBytes
;
861 if (config
->info
.samples
>= 2 && AddrSurfInfoIn
.flags
.color
&&
862 info
->has_graphics
&& !(surf
->flags
& RADEON_SURF_NO_FMASK
)) {
863 ADDR_COMPUTE_FMASK_INFO_INPUT fin
= {0};
864 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
865 ADDR_TILEINFO fmask_tile_info
= {};
867 fin
.size
= sizeof(fin
);
868 fout
.size
= sizeof(fout
);
870 fin
.tileMode
= AddrSurfInfoOut
.tileMode
;
871 fin
.pitch
= AddrSurfInfoOut
.pitch
;
872 fin
.height
= config
->info
.height
;
873 fin
.numSlices
= AddrSurfInfoIn
.numSlices
;
874 fin
.numSamples
= AddrSurfInfoIn
.numSamples
;
875 fin
.numFrags
= AddrSurfInfoIn
.numFrags
;
877 fout
.pTileInfo
= &fmask_tile_info
;
879 r
= AddrComputeFmaskInfo(addrlib
, &fin
, &fout
);
883 surf
->fmask_size
= fout
.fmaskBytes
;
884 surf
->fmask_alignment
= fout
.baseAlign
;
885 surf
->fmask_tile_swizzle
= 0;
887 surf
->u
.legacy
.fmask
.slice_tile_max
=
888 (fout
.pitch
* fout
.height
) / 64;
889 if (surf
->u
.legacy
.fmask
.slice_tile_max
)
890 surf
->u
.legacy
.fmask
.slice_tile_max
-= 1;
892 surf
->u
.legacy
.fmask
.tiling_index
= fout
.tileIndex
;
893 surf
->u
.legacy
.fmask
.bankh
= fout
.pTileInfo
->bankHeight
;
894 surf
->u
.legacy
.fmask
.pitch_in_pixels
= fout
.pitch
;
895 surf
->u
.legacy
.fmask
.slice_size
= fout
.sliceSize
;
897 /* Compute tile swizzle for FMASK. */
898 if (config
->info
.fmask_surf_index
&&
899 !(surf
->flags
& RADEON_SURF_SHAREABLE
)) {
900 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin
= {0};
901 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout
= {0};
903 xin
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
904 xout
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
906 /* This counter starts from 1 instead of 0. */
907 xin
.surfIndex
= p_atomic_inc_return(config
->info
.fmask_surf_index
);
908 xin
.tileIndex
= fout
.tileIndex
;
909 xin
.macroModeIndex
= fout
.macroModeIndex
;
910 xin
.pTileInfo
= fout
.pTileInfo
;
911 xin
.tileMode
= fin
.tileMode
;
913 int r
= AddrComputeBaseSwizzle(addrlib
, &xin
, &xout
);
917 assert(xout
.tileSwizzle
<=
918 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
919 surf
->fmask_tile_swizzle
= xout
.tileSwizzle
;
923 /* Recalculate the whole DCC miptree size including disabled levels.
924 * This is what addrlib does, but calling addrlib would be a lot more
927 if (surf
->dcc_size
&& config
->info
.levels
> 1) {
928 /* The smallest miplevels that are never compressed by DCC
929 * still read the DCC buffer via TC if the base level uses DCC,
930 * and for some reason the DCC buffer needs to be larger if
931 * the miptree uses non-zero tile_swizzle. Otherwise there are
934 * "dcc_alignment * 4" was determined by trial and error.
936 surf
->dcc_size
= align64(surf
->surf_size
>> 8,
937 surf
->dcc_alignment
* 4);
940 /* Make sure HTILE covers the whole miptree, because the shader reads
941 * TC-compatible HTILE even for levels where it's disabled by DB.
943 if (surf
->htile_size
&& config
->info
.levels
> 1 &&
944 surf
->tc_compatible_htile_allowed
) {
945 /* MSAA can't occur with levels > 1, so ignore the sample count. */
946 const unsigned total_pixels
= surf
->surf_size
/ surf
->bpe
;
947 const unsigned htile_block_size
= 8 * 8;
948 const unsigned htile_element_size
= 4;
950 surf
->htile_size
= (total_pixels
/ htile_block_size
) *
952 surf
->htile_size
= align(surf
->htile_size
, surf
->htile_alignment
);
955 surf
->is_linear
= surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
;
956 surf
->is_displayable
= surf
->is_linear
||
957 surf
->micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
||
958 surf
->micro_tile_mode
== RADEON_MICRO_MODE_RENDER
;
960 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
961 * used at the same time. This case is not currently expected to occur
962 * because we don't use rotated. Enforce this restriction on all chips
963 * to facilitate testing.
965 if (surf
->micro_tile_mode
== RADEON_MICRO_MODE_RENDER
) {
966 assert(!"rotate micro tile mode is unsupported");
970 ac_compute_cmask(info
, config
, surf
);
974 /* This is only called when expecting a tiled layout. */
976 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib
,
977 struct radeon_surf
*surf
,
978 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
,
979 bool is_fmask
, AddrSwizzleMode
*swizzle_mode
)
981 ADDR_E_RETURNCODE ret
;
982 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin
= {0};
983 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout
= {0};
985 sin
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
);
986 sout
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
);
988 sin
.flags
= in
->flags
;
989 sin
.resourceType
= in
->resourceType
;
990 sin
.format
= in
->format
;
991 sin
.resourceLoction
= ADDR_RSRC_LOC_INVIS
;
992 /* TODO: We could allow some of these: */
993 sin
.forbiddenBlock
.micro
= 1; /* don't allow the 256B swizzle modes */
994 sin
.forbiddenBlock
.var
= 1; /* don't allow the variable-sized swizzle modes */
996 sin
.width
= in
->width
;
997 sin
.height
= in
->height
;
998 sin
.numSlices
= in
->numSlices
;
999 sin
.numMipLevels
= in
->numMipLevels
;
1000 sin
.numSamples
= in
->numSamples
;
1001 sin
.numFrags
= in
->numFrags
;
1004 sin
.flags
.display
= 0;
1005 sin
.flags
.color
= 0;
1006 sin
.flags
.fmask
= 1;
1009 if (surf
->flags
& RADEON_SURF_FORCE_MICRO_TILE_MODE
) {
1010 sin
.forbiddenBlock
.linear
= 1;
1012 if (surf
->micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
)
1013 sin
.preferredSwSet
.sw_D
= 1;
1014 else if (surf
->micro_tile_mode
== RADEON_MICRO_MODE_STANDARD
)
1015 sin
.preferredSwSet
.sw_S
= 1;
1016 else if (surf
->micro_tile_mode
== RADEON_MICRO_MODE_DEPTH
)
1017 sin
.preferredSwSet
.sw_Z
= 1;
1018 else if (surf
->micro_tile_mode
== RADEON_MICRO_MODE_RENDER
)
1019 sin
.preferredSwSet
.sw_R
= 1;
1022 ret
= Addr2GetPreferredSurfaceSetting(addrlib
, &sin
, &sout
);
1026 *swizzle_mode
= sout
.swizzleMode
;
1030 static bool gfx9_is_dcc_capable(const struct radeon_info
*info
, unsigned sw_mode
)
1032 if (info
->chip_class
>= GFX10
)
1033 return sw_mode
== ADDR_SW_64KB_Z_X
|| sw_mode
== ADDR_SW_64KB_R_X
;
1035 return sw_mode
!= ADDR_SW_LINEAR
;
1038 static int gfx9_compute_miptree(ADDR_HANDLE addrlib
,
1039 const struct radeon_info
*info
,
1040 const struct ac_surf_config
*config
,
1041 struct radeon_surf
*surf
, bool compressed
,
1042 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
)
1044 ADDR2_MIP_INFO mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
1045 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out
= {0};
1046 ADDR_E_RETURNCODE ret
;
1048 out
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
);
1049 out
.pMipInfo
= mip_info
;
1051 ret
= Addr2ComputeSurfaceInfo(addrlib
, in
, &out
);
1055 if (in
->flags
.stencil
) {
1056 surf
->u
.gfx9
.stencil
.swizzle_mode
= in
->swizzleMode
;
1057 surf
->u
.gfx9
.stencil
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
1058 out
.mipChainPitch
- 1;
1059 surf
->surf_alignment
= MAX2(surf
->surf_alignment
, out
.baseAlign
);
1060 surf
->u
.gfx9
.stencil_offset
= align(surf
->surf_size
, out
.baseAlign
);
1061 surf
->surf_size
= surf
->u
.gfx9
.stencil_offset
+ out
.surfSize
;
1065 surf
->u
.gfx9
.surf
.swizzle_mode
= in
->swizzleMode
;
1066 surf
->u
.gfx9
.surf
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
1067 out
.mipChainPitch
- 1;
1069 /* CMASK fast clear uses these even if FMASK isn't allocated.
1070 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1072 surf
->u
.gfx9
.fmask
.swizzle_mode
= surf
->u
.gfx9
.surf
.swizzle_mode
& ~0x3;
1073 surf
->u
.gfx9
.fmask
.epitch
= surf
->u
.gfx9
.surf
.epitch
;
1075 surf
->u
.gfx9
.surf_slice_size
= out
.sliceSize
;
1076 surf
->u
.gfx9
.surf_pitch
= out
.pitch
;
1077 if (!compressed
&& surf
->blk_w
> 1 && out
.pitch
== out
.pixelPitch
) {
1078 /* Adjust surf_pitch to be in elements units,
1080 surf
->u
.gfx9
.surf_pitch
/= surf
->blk_w
;
1082 surf
->u
.gfx9
.surf_height
= out
.height
;
1083 surf
->surf_size
= out
.surfSize
;
1084 surf
->surf_alignment
= out
.baseAlign
;
1086 if (in
->swizzleMode
== ADDR_SW_LINEAR
) {
1087 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++) {
1088 surf
->u
.gfx9
.offset
[i
] = mip_info
[i
].offset
;
1089 surf
->u
.gfx9
.pitch
[i
] = mip_info
[i
].pitch
;
1093 if (in
->flags
.depth
) {
1094 assert(in
->swizzleMode
!= ADDR_SW_LINEAR
);
1096 if (surf
->flags
& RADEON_SURF_NO_HTILE
)
1100 ADDR2_COMPUTE_HTILE_INFO_INPUT hin
= {0};
1101 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout
= {0};
1103 hin
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT
);
1104 hout
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT
);
1106 hin
.hTileFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1107 hin
.hTileFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1108 hin
.depthFlags
= in
->flags
;
1109 hin
.swizzleMode
= in
->swizzleMode
;
1110 hin
.unalignedWidth
= in
->width
;
1111 hin
.unalignedHeight
= in
->height
;
1112 hin
.numSlices
= in
->numSlices
;
1113 hin
.numMipLevels
= in
->numMipLevels
;
1114 hin
.firstMipIdInTail
= out
.firstMipIdInTail
;
1116 ret
= Addr2ComputeHtileInfo(addrlib
, &hin
, &hout
);
1120 surf
->u
.gfx9
.htile
.rb_aligned
= hin
.hTileFlags
.rbAligned
;
1121 surf
->u
.gfx9
.htile
.pipe_aligned
= hin
.hTileFlags
.pipeAligned
;
1122 surf
->htile_size
= hout
.htileBytes
;
1123 surf
->htile_slice_size
= hout
.sliceSize
;
1124 surf
->htile_alignment
= hout
.baseAlign
;
1129 /* Compute tile swizzle for the color surface.
1130 * All *_X and *_T modes can use the swizzle.
1132 if (config
->info
.surf_index
&&
1133 in
->swizzleMode
>= ADDR_SW_64KB_Z_T
&&
1134 !out
.mipChainInTail
&&
1135 !(surf
->flags
& RADEON_SURF_SHAREABLE
) &&
1136 !in
->flags
.display
) {
1137 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
1138 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
1140 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
1141 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
1143 xin
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
1144 xin
.flags
= in
->flags
;
1145 xin
.swizzleMode
= in
->swizzleMode
;
1146 xin
.resourceType
= in
->resourceType
;
1147 xin
.format
= in
->format
;
1148 xin
.numSamples
= in
->numSamples
;
1149 xin
.numFrags
= in
->numFrags
;
1151 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
1155 assert(xout
.pipeBankXor
<=
1156 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
1157 surf
->tile_swizzle
= xout
.pipeBankXor
;
1161 if (info
->has_graphics
&&
1162 !(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
1164 gfx9_is_dcc_capable(info
, in
->swizzleMode
)) {
1165 ADDR2_COMPUTE_DCCINFO_INPUT din
= {0};
1166 ADDR2_COMPUTE_DCCINFO_OUTPUT dout
= {0};
1167 ADDR2_META_MIP_INFO meta_mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
1169 din
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_INPUT
);
1170 dout
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT
);
1171 dout
.pMipInfo
= meta_mip_info
;
1173 din
.dccKeyFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1174 din
.dccKeyFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1175 din
.colorFlags
= in
->flags
;
1176 din
.resourceType
= in
->resourceType
;
1177 din
.swizzleMode
= in
->swizzleMode
;
1179 din
.unalignedWidth
= in
->width
;
1180 din
.unalignedHeight
= in
->height
;
1181 din
.numSlices
= in
->numSlices
;
1182 din
.numFrags
= in
->numFrags
;
1183 din
.numMipLevels
= in
->numMipLevels
;
1184 din
.dataSurfaceSize
= out
.surfSize
;
1185 din
.firstMipIdInTail
= out
.firstMipIdInTail
;
1187 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
1191 surf
->u
.gfx9
.dcc
.rb_aligned
= din
.dccKeyFlags
.rbAligned
;
1192 surf
->u
.gfx9
.dcc
.pipe_aligned
= din
.dccKeyFlags
.pipeAligned
;
1193 surf
->dcc_size
= dout
.dccRamSize
;
1194 surf
->dcc_alignment
= dout
.dccRamBaseAlign
;
1195 surf
->num_dcc_levels
= in
->numMipLevels
;
1197 /* Disable DCC for levels that are in the mip tail.
1199 * There are two issues that this is intended to
1202 * 1. Multiple mip levels may share a cache line. This
1203 * can lead to corruption when switching between
1204 * rendering to different mip levels because the
1205 * RBs don't maintain coherency.
1207 * 2. Texturing with metadata after rendering sometimes
1208 * fails with corruption, probably for a similar
1211 * Working around these issues for all levels in the
1212 * mip tail may be overly conservative, but it's what
1215 * Alternative solutions that also work but are worse:
1216 * - Disable DCC entirely.
1217 * - Flush TC L2 after rendering.
1219 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++) {
1220 if (meta_mip_info
[i
].inMiptail
) {
1221 surf
->num_dcc_levels
= i
;
1226 if (!surf
->num_dcc_levels
)
1229 surf
->u
.gfx9
.display_dcc_size
= surf
->dcc_size
;
1230 surf
->u
.gfx9
.display_dcc_alignment
= surf
->dcc_alignment
;
1231 surf
->u
.gfx9
.display_dcc_pitch_max
= dout
.pitch
- 1;
1233 /* Compute displayable DCC. */
1234 if (in
->flags
.display
&&
1235 surf
->num_dcc_levels
&&
1236 info
->use_display_dcc_with_retile_blit
) {
1237 /* Compute displayable DCC info. */
1238 din
.dccKeyFlags
.pipeAligned
= 0;
1239 din
.dccKeyFlags
.rbAligned
= 0;
1241 assert(din
.numSlices
== 1);
1242 assert(din
.numMipLevels
== 1);
1243 assert(din
.numFrags
== 1);
1244 assert(surf
->tile_swizzle
== 0);
1245 assert(surf
->u
.gfx9
.dcc
.pipe_aligned
||
1246 surf
->u
.gfx9
.dcc
.rb_aligned
);
1248 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
1252 surf
->u
.gfx9
.display_dcc_size
= dout
.dccRamSize
;
1253 surf
->u
.gfx9
.display_dcc_alignment
= dout
.dccRamBaseAlign
;
1254 surf
->u
.gfx9
.display_dcc_pitch_max
= dout
.pitch
- 1;
1255 assert(surf
->u
.gfx9
.display_dcc_size
<= surf
->dcc_size
);
1257 /* Compute address mapping from non-displayable to displayable DCC. */
1258 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin
= {};
1259 addrin
.size
= sizeof(addrin
);
1260 addrin
.colorFlags
.color
= 1;
1261 addrin
.swizzleMode
= din
.swizzleMode
;
1262 addrin
.resourceType
= din
.resourceType
;
1263 addrin
.bpp
= din
.bpp
;
1264 addrin
.unalignedWidth
= din
.unalignedWidth
;
1265 addrin
.unalignedHeight
= din
.unalignedHeight
;
1266 addrin
.numSlices
= 1;
1267 addrin
.numMipLevels
= 1;
1268 addrin
.numFrags
= 1;
1270 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout
= {};
1271 addrout
.size
= sizeof(addrout
);
1273 surf
->u
.gfx9
.dcc_retile_num_elements
=
1274 DIV_ROUND_UP(in
->width
, dout
.compressBlkWidth
) *
1275 DIV_ROUND_UP(in
->height
, dout
.compressBlkHeight
) * 2;
1276 /* Align the size to 4 (for the compute shader). */
1277 surf
->u
.gfx9
.dcc_retile_num_elements
=
1278 align(surf
->u
.gfx9
.dcc_retile_num_elements
, 4);
1280 surf
->u
.gfx9
.dcc_retile_map
=
1281 malloc(surf
->u
.gfx9
.dcc_retile_num_elements
* 4);
1282 if (!surf
->u
.gfx9
.dcc_retile_map
)
1283 return ADDR_OUTOFMEMORY
;
1286 surf
->u
.gfx9
.dcc_retile_use_uint16
= true;
1288 for (unsigned y
= 0; y
< in
->height
; y
+= dout
.compressBlkHeight
) {
1291 for (unsigned x
= 0; x
< in
->width
; x
+= dout
.compressBlkWidth
) {
1294 /* Compute src DCC address */
1295 addrin
.dccKeyFlags
.pipeAligned
= surf
->u
.gfx9
.dcc
.pipe_aligned
;
1296 addrin
.dccKeyFlags
.rbAligned
= surf
->u
.gfx9
.dcc
.rb_aligned
;
1299 ret
= Addr2ComputeDccAddrFromCoord(addrlib
, &addrin
, &addrout
);
1303 surf
->u
.gfx9
.dcc_retile_map
[index
* 2] = addrout
.addr
;
1304 if (addrout
.addr
> UINT16_MAX
)
1305 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1307 /* Compute dst DCC address */
1308 addrin
.dccKeyFlags
.pipeAligned
= 0;
1309 addrin
.dccKeyFlags
.rbAligned
= 0;
1312 ret
= Addr2ComputeDccAddrFromCoord(addrlib
, &addrin
, &addrout
);
1316 surf
->u
.gfx9
.dcc_retile_map
[index
* 2 + 1] = addrout
.addr
;
1317 if (addrout
.addr
> UINT16_MAX
)
1318 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1320 assert(index
* 2 + 1 < surf
->u
.gfx9
.dcc_retile_num_elements
);
1324 /* Fill the remaining pairs with the last one (for the compute shader). */
1325 for (unsigned i
= index
* 2; i
< surf
->u
.gfx9
.dcc_retile_num_elements
; i
++)
1326 surf
->u
.gfx9
.dcc_retile_map
[i
] = surf
->u
.gfx9
.dcc_retile_map
[i
- 2];
1331 if (in
->numSamples
> 1 && info
->has_graphics
&&
1332 !(surf
->flags
& RADEON_SURF_NO_FMASK
)) {
1333 ADDR2_COMPUTE_FMASK_INFO_INPUT fin
= {0};
1334 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
1336 fin
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT
);
1337 fout
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT
);
1339 ret
= gfx9_get_preferred_swizzle_mode(addrlib
, surf
, in
,
1340 true, &fin
.swizzleMode
);
1344 fin
.unalignedWidth
= in
->width
;
1345 fin
.unalignedHeight
= in
->height
;
1346 fin
.numSlices
= in
->numSlices
;
1347 fin
.numSamples
= in
->numSamples
;
1348 fin
.numFrags
= in
->numFrags
;
1350 ret
= Addr2ComputeFmaskInfo(addrlib
, &fin
, &fout
);
1354 surf
->u
.gfx9
.fmask
.swizzle_mode
= fin
.swizzleMode
;
1355 surf
->u
.gfx9
.fmask
.epitch
= fout
.pitch
- 1;
1356 surf
->fmask_size
= fout
.fmaskBytes
;
1357 surf
->fmask_alignment
= fout
.baseAlign
;
1359 /* Compute tile swizzle for the FMASK surface. */
1360 if (config
->info
.fmask_surf_index
&&
1361 fin
.swizzleMode
>= ADDR_SW_64KB_Z_T
&&
1362 !(surf
->flags
& RADEON_SURF_SHAREABLE
)) {
1363 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
1364 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
1366 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
1367 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
1369 /* This counter starts from 1 instead of 0. */
1370 xin
.surfIndex
= p_atomic_inc_return(config
->info
.fmask_surf_index
);
1371 xin
.flags
= in
->flags
;
1372 xin
.swizzleMode
= fin
.swizzleMode
;
1373 xin
.resourceType
= in
->resourceType
;
1374 xin
.format
= in
->format
;
1375 xin
.numSamples
= in
->numSamples
;
1376 xin
.numFrags
= in
->numFrags
;
1378 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
1382 assert(xout
.pipeBankXor
<=
1383 u_bit_consecutive(0, sizeof(surf
->fmask_tile_swizzle
) * 8));
1384 surf
->fmask_tile_swizzle
= xout
.pipeBankXor
;
1388 /* CMASK -- on GFX10 only for FMASK */
1389 if (in
->swizzleMode
!= ADDR_SW_LINEAR
&&
1390 in
->resourceType
== ADDR_RSRC_TEX_2D
&&
1391 ((info
->chip_class
<= GFX9
&& in
->numSamples
== 1) ||
1392 (surf
->fmask_size
&& in
->numSamples
>= 2))) {
1393 ADDR2_COMPUTE_CMASK_INFO_INPUT cin
= {0};
1394 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout
= {0};
1396 cin
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT
);
1397 cout
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT
);
1399 if (in
->numSamples
> 1) {
1400 /* FMASK is always aligned. */
1401 cin
.cMaskFlags
.pipeAligned
= 1;
1402 cin
.cMaskFlags
.rbAligned
= 1;
1404 cin
.cMaskFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1405 cin
.cMaskFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1407 cin
.colorFlags
= in
->flags
;
1408 cin
.resourceType
= in
->resourceType
;
1409 cin
.unalignedWidth
= in
->width
;
1410 cin
.unalignedHeight
= in
->height
;
1411 cin
.numSlices
= in
->numSlices
;
1413 if (in
->numSamples
> 1)
1414 cin
.swizzleMode
= surf
->u
.gfx9
.fmask
.swizzle_mode
;
1416 cin
.swizzleMode
= in
->swizzleMode
;
1418 ret
= Addr2ComputeCmaskInfo(addrlib
, &cin
, &cout
);
1422 surf
->u
.gfx9
.cmask
.rb_aligned
= cin
.cMaskFlags
.rbAligned
;
1423 surf
->u
.gfx9
.cmask
.pipe_aligned
= cin
.cMaskFlags
.pipeAligned
;
1424 surf
->cmask_size
= cout
.cmaskBytes
;
1425 surf
->cmask_alignment
= cout
.baseAlign
;
1432 static int gfx9_compute_surface(ADDR_HANDLE addrlib
,
1433 const struct radeon_info
*info
,
1434 const struct ac_surf_config
*config
,
1435 enum radeon_surf_mode mode
,
1436 struct radeon_surf
*surf
)
1439 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
1442 AddrSurfInfoIn
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT
);
1444 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
1446 /* The format must be set correctly for the allocation of compressed
1447 * textures to work. In other cases, setting the bpp is sufficient. */
1449 switch (surf
->bpe
) {
1451 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
1454 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
1460 switch (surf
->bpe
) {
1462 assert(!(surf
->flags
& RADEON_SURF_ZBUFFER
));
1463 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1466 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1467 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1468 AddrSurfInfoIn
.format
= ADDR_FMT_16
;
1471 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1472 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1473 AddrSurfInfoIn
.format
= ADDR_FMT_32
;
1476 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1477 AddrSurfInfoIn
.format
= ADDR_FMT_32_32
;
1480 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1481 AddrSurfInfoIn
.format
= ADDR_FMT_32_32_32
;
1484 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1485 AddrSurfInfoIn
.format
= ADDR_FMT_32_32_32_32
;
1490 AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
1493 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
1494 !(surf
->flags
& RADEON_SURF_NO_RENDER_TARGET
);
1495 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
1496 AddrSurfInfoIn
.flags
.display
= get_display_flag(config
, surf
);
1497 /* flags.texture currently refers to TC-compatible HTILE */
1498 AddrSurfInfoIn
.flags
.texture
= 1;
1499 AddrSurfInfoIn
.flags
.opt4space
= 1;
1501 AddrSurfInfoIn
.numMipLevels
= config
->info
.levels
;
1502 AddrSurfInfoIn
.numSamples
= MAX2(1, config
->info
.samples
);
1503 AddrSurfInfoIn
.numFrags
= AddrSurfInfoIn
.numSamples
;
1505 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
))
1506 AddrSurfInfoIn
.numFrags
= MAX2(1, config
->info
.storage_samples
);
1508 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1509 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1510 * must sample 1D textures as 2D. */
1512 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_3D
;
1513 else if (info
->chip_class
!= GFX9
&& config
->is_1d
)
1514 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_1D
;
1516 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_2D
;
1518 AddrSurfInfoIn
.width
= config
->info
.width
;
1519 AddrSurfInfoIn
.height
= config
->info
.height
;
1522 AddrSurfInfoIn
.numSlices
= config
->info
.depth
;
1523 else if (config
->is_cube
)
1524 AddrSurfInfoIn
.numSlices
= 6;
1526 AddrSurfInfoIn
.numSlices
= config
->info
.array_size
;
1528 /* This is propagated to HTILE/DCC/CMASK. */
1529 AddrSurfInfoIn
.flags
.metaPipeUnaligned
= 0;
1530 AddrSurfInfoIn
.flags
.metaRbUnaligned
= 0;
1532 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1533 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1535 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1536 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1537 * after rendering, so PIPE_ALIGNED=1 is recommended.
1539 if (info
->use_display_dcc_unaligned
&&
1540 AddrSurfInfoIn
.flags
.display
) {
1541 AddrSurfInfoIn
.flags
.metaPipeUnaligned
= 1;
1542 AddrSurfInfoIn
.flags
.metaRbUnaligned
= 1;
1546 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1547 assert(config
->info
.samples
<= 1);
1548 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1549 AddrSurfInfoIn
.swizzleMode
= ADDR_SW_LINEAR
;
1552 case RADEON_SURF_MODE_1D
:
1553 case RADEON_SURF_MODE_2D
:
1554 if (surf
->flags
& (RADEON_SURF_IMPORTED
| RADEON_SURF_FORCE_SWIZZLE_MODE
)) {
1555 AddrSurfInfoIn
.swizzleMode
= surf
->u
.gfx9
.surf
.swizzle_mode
;
1559 r
= gfx9_get_preferred_swizzle_mode(addrlib
, surf
, &AddrSurfInfoIn
,
1560 false, &AddrSurfInfoIn
.swizzleMode
);
1569 surf
->u
.gfx9
.resource_type
= AddrSurfInfoIn
.resourceType
;
1570 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
1572 surf
->num_dcc_levels
= 0;
1573 surf
->surf_size
= 0;
1574 surf
->fmask_size
= 0;
1576 surf
->htile_size
= 0;
1577 surf
->htile_slice_size
= 0;
1578 surf
->u
.gfx9
.surf_offset
= 0;
1579 surf
->u
.gfx9
.stencil_offset
= 0;
1580 surf
->cmask_size
= 0;
1581 surf
->u
.gfx9
.dcc_retile_use_uint16
= false;
1582 surf
->u
.gfx9
.dcc_retile_num_elements
= 0;
1583 surf
->u
.gfx9
.dcc_retile_map
= NULL
;
1585 /* Calculate texture layout information. */
1586 r
= gfx9_compute_miptree(addrlib
, info
, config
, surf
, compressed
,
1591 /* Calculate texture layout information for stencil. */
1592 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
1593 AddrSurfInfoIn
.flags
.stencil
= 1;
1594 AddrSurfInfoIn
.bpp
= 8;
1595 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1597 if (!AddrSurfInfoIn
.flags
.depth
) {
1598 r
= gfx9_get_preferred_swizzle_mode(addrlib
, surf
, &AddrSurfInfoIn
,
1599 false, &AddrSurfInfoIn
.swizzleMode
);
1603 AddrSurfInfoIn
.flags
.depth
= 0;
1605 r
= gfx9_compute_miptree(addrlib
, info
, config
, surf
, compressed
,
1611 surf
->is_linear
= surf
->u
.gfx9
.surf
.swizzle_mode
== ADDR_SW_LINEAR
;
1612 surf
->tc_compatible_htile_allowed
= surf
->htile_size
!= 0;
1614 /* Query whether the surface is displayable. */
1615 bool displayable
= false;
1616 if (!config
->is_3d
&& !config
->is_cube
) {
1617 r
= Addr2IsValidDisplaySwizzleMode(addrlib
, surf
->u
.gfx9
.surf
.swizzle_mode
,
1618 surf
->bpe
* 8, &displayable
);
1622 /* Display needs unaligned DCC. */
1623 if (info
->use_display_dcc_unaligned
&&
1624 surf
->num_dcc_levels
&&
1625 (surf
->u
.gfx9
.dcc
.pipe_aligned
||
1626 surf
->u
.gfx9
.dcc
.rb_aligned
))
1627 displayable
= false;
1629 surf
->is_displayable
= displayable
;
1631 switch (surf
->u
.gfx9
.surf
.swizzle_mode
) {
1633 case ADDR_SW_256B_S
:
1635 case ADDR_SW_64KB_S
:
1636 case ADDR_SW_64KB_S_T
:
1637 case ADDR_SW_4KB_S_X
:
1638 case ADDR_SW_64KB_S_X
:
1639 surf
->micro_tile_mode
= RADEON_MICRO_MODE_STANDARD
;
1643 case ADDR_SW_LINEAR
:
1644 case ADDR_SW_256B_D
:
1646 case ADDR_SW_64KB_D
:
1647 case ADDR_SW_64KB_D_T
:
1648 case ADDR_SW_4KB_D_X
:
1649 case ADDR_SW_64KB_D_X
:
1650 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DISPLAY
;
1653 /* R = rotated (gfx9), render target (gfx10). */
1654 case ADDR_SW_256B_R
:
1656 case ADDR_SW_64KB_R
:
1657 case ADDR_SW_64KB_R_T
:
1658 case ADDR_SW_4KB_R_X
:
1659 case ADDR_SW_64KB_R_X
:
1660 case ADDR_SW_VAR_R_X
:
1661 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1662 * used at the same time. We currently do not use rotated
1665 assert(info
->chip_class
>= GFX10
||
1666 !"rotate micro tile mode is unsupported");
1667 surf
->micro_tile_mode
= RADEON_MICRO_MODE_RENDER
;
1672 case ADDR_SW_64KB_Z
:
1673 case ADDR_SW_64KB_Z_T
:
1674 case ADDR_SW_4KB_Z_X
:
1675 case ADDR_SW_64KB_Z_X
:
1676 case ADDR_SW_VAR_Z_X
:
1677 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DEPTH
;
1687 free(surf
->u
.gfx9
.dcc_retile_map
);
1688 surf
->u
.gfx9
.dcc_retile_map
= NULL
;
1692 int ac_compute_surface(ADDR_HANDLE addrlib
, const struct radeon_info
*info
,
1693 const struct ac_surf_config
*config
,
1694 enum radeon_surf_mode mode
,
1695 struct radeon_surf
*surf
)
1699 r
= surf_config_sanity(config
, surf
->flags
);
1703 if (info
->chip_class
>= GFX9
)
1704 r
= gfx9_compute_surface(addrlib
, info
, config
, mode
, surf
);
1706 r
= gfx6_compute_surface(addrlib
, info
, config
, mode
, surf
);
1711 /* Determine the memory layout of multiple allocations in one buffer. */
1712 surf
->total_size
= surf
->surf_size
;
1714 if (surf
->htile_size
) {
1715 surf
->htile_offset
= align64(surf
->total_size
, surf
->htile_alignment
);
1716 surf
->total_size
= surf
->htile_offset
+ surf
->htile_size
;
1719 if (surf
->fmask_size
) {
1720 assert(config
->info
.samples
>= 2);
1721 surf
->fmask_offset
= align64(surf
->total_size
, surf
->fmask_alignment
);
1722 surf
->total_size
= surf
->fmask_offset
+ surf
->fmask_size
;
1725 /* Single-sample CMASK is in a separate buffer. */
1726 if (surf
->cmask_size
&& config
->info
.samples
>= 2) {
1727 surf
->cmask_offset
= align64(surf
->total_size
, surf
->cmask_alignment
);
1728 surf
->total_size
= surf
->cmask_offset
+ surf
->cmask_size
;
1731 if (surf
->dcc_size
&&
1732 (info
->use_display_dcc_unaligned
||
1733 info
->use_display_dcc_with_retile_blit
||
1734 !(surf
->flags
& RADEON_SURF_SCANOUT
))) {
1735 surf
->dcc_offset
= align64(surf
->total_size
, surf
->dcc_alignment
);
1736 surf
->total_size
= surf
->dcc_offset
+ surf
->dcc_size
;
1738 if (info
->chip_class
>= GFX9
&&
1739 surf
->u
.gfx9
.dcc_retile_num_elements
) {
1740 /* Add space for the displayable DCC buffer. */
1741 surf
->display_dcc_offset
=
1742 align64(surf
->total_size
, surf
->u
.gfx9
.display_dcc_alignment
);
1743 surf
->total_size
= surf
->display_dcc_offset
+
1744 surf
->u
.gfx9
.display_dcc_size
;
1746 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1747 surf
->dcc_retile_map_offset
=
1748 align64(surf
->total_size
, info
->tcc_cache_line_size
);
1750 if (surf
->u
.gfx9
.dcc_retile_use_uint16
) {
1751 surf
->total_size
= surf
->dcc_retile_map_offset
+
1752 surf
->u
.gfx9
.dcc_retile_num_elements
* 2;
1754 surf
->total_size
= surf
->dcc_retile_map_offset
+
1755 surf
->u
.gfx9
.dcc_retile_num_elements
* 4;