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9eb63bab038fd5e8333a161e5344e19e1d0b843d
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static unsigned get_first(unsigned x, unsigned y)
53 {
54 return x;
55 }
56
57 static void addrlib_family_rev_id(enum radeon_family family,
58 unsigned *addrlib_family,
59 unsigned *addrlib_revid)
60 {
61 switch (family) {
62 case CHIP_TAHITI:
63 *addrlib_family = FAMILY_SI;
64 *addrlib_revid = get_first(AMDGPU_TAHITI_RANGE);
65 break;
66 case CHIP_PITCAIRN:
67 *addrlib_family = FAMILY_SI;
68 *addrlib_revid = get_first(AMDGPU_PITCAIRN_RANGE);
69 break;
70 case CHIP_VERDE:
71 *addrlib_family = FAMILY_SI;
72 *addrlib_revid = get_first(AMDGPU_CAPEVERDE_RANGE);
73 break;
74 case CHIP_OLAND:
75 *addrlib_family = FAMILY_SI;
76 *addrlib_revid = get_first(AMDGPU_OLAND_RANGE);
77 break;
78 case CHIP_HAINAN:
79 *addrlib_family = FAMILY_SI;
80 *addrlib_revid = get_first(AMDGPU_HAINAN_RANGE);
81 break;
82 case CHIP_BONAIRE:
83 *addrlib_family = FAMILY_CI;
84 *addrlib_revid = get_first(AMDGPU_BONAIRE_RANGE);
85 break;
86 case CHIP_KAVERI:
87 *addrlib_family = FAMILY_KV;
88 *addrlib_revid = get_first(AMDGPU_SPECTRE_RANGE);
89 break;
90 case CHIP_KABINI:
91 *addrlib_family = FAMILY_KV;
92 *addrlib_revid = get_first(AMDGPU_KALINDI_RANGE);
93 break;
94 case CHIP_HAWAII:
95 *addrlib_family = FAMILY_CI;
96 *addrlib_revid = get_first(AMDGPU_HAWAII_RANGE);
97 break;
98 case CHIP_MULLINS:
99 *addrlib_family = FAMILY_KV;
100 *addrlib_revid = get_first(AMDGPU_GODAVARI_RANGE);
101 break;
102 case CHIP_TONGA:
103 *addrlib_family = FAMILY_VI;
104 *addrlib_revid = get_first(AMDGPU_TONGA_RANGE);
105 break;
106 case CHIP_ICELAND:
107 *addrlib_family = FAMILY_VI;
108 *addrlib_revid = get_first(AMDGPU_ICELAND_RANGE);
109 break;
110 case CHIP_CARRIZO:
111 *addrlib_family = FAMILY_CZ;
112 *addrlib_revid = get_first(AMDGPU_CARRIZO_RANGE);
113 break;
114 case CHIP_STONEY:
115 *addrlib_family = FAMILY_CZ;
116 *addrlib_revid = get_first(AMDGPU_STONEY_RANGE);
117 break;
118 case CHIP_FIJI:
119 *addrlib_family = FAMILY_VI;
120 *addrlib_revid = get_first(AMDGPU_FIJI_RANGE);
121 break;
122 case CHIP_POLARIS10:
123 *addrlib_family = FAMILY_VI;
124 *addrlib_revid = get_first(AMDGPU_POLARIS10_RANGE);
125 break;
126 case CHIP_POLARIS11:
127 *addrlib_family = FAMILY_VI;
128 *addrlib_revid = get_first(AMDGPU_POLARIS11_RANGE);
129 break;
130 case CHIP_POLARIS12:
131 *addrlib_family = FAMILY_VI;
132 *addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE);
133 break;
134 case CHIP_VEGAM:
135 *addrlib_family = FAMILY_VI;
136 *addrlib_revid = get_first(AMDGPU_VEGAM_RANGE);
137 break;
138 case CHIP_VEGA10:
139 *addrlib_family = FAMILY_AI;
140 *addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
141 break;
142 case CHIP_VEGA12:
143 *addrlib_family = FAMILY_AI;
144 *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
145 break;
146 case CHIP_RAVEN:
147 *addrlib_family = FAMILY_RV;
148 *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
149 break;
150 default:
151 fprintf(stderr, "amdgpu: Unknown family.\n");
152 }
153 }
154
155 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
156 {
157 return malloc(pInput->sizeInBytes);
158 }
159
160 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
161 {
162 free(pInput->pVirtAddr);
163 return ADDR_OK;
164 }
165
166 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
167 const struct amdgpu_gpu_info *amdinfo,
168 uint64_t *max_alignment)
169 {
170 ADDR_CREATE_INPUT addrCreateInput = {0};
171 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
172 ADDR_REGISTER_VALUE regValue = {0};
173 ADDR_CREATE_FLAGS createFlags = {{0}};
174 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
175 ADDR_E_RETURNCODE addrRet;
176
177 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
178 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
179
180 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
181 createFlags.value = 0;
182
183 addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
184 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
185 return NULL;
186
187 if (addrCreateInput.chipFamily >= FAMILY_AI) {
188 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
189 regValue.blockVarSizeLog2 = 0;
190 } else {
191 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
192 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
193
194 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
195 regValue.pTileConfig = amdinfo->gb_tile_mode;
196 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
197 if (addrCreateInput.chipFamily == FAMILY_SI) {
198 regValue.pMacroTileConfig = NULL;
199 regValue.noOfMacroEntries = 0;
200 } else {
201 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
202 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
203 }
204
205 createFlags.useTileIndex = 1;
206 createFlags.useHtileSliceAlign = 1;
207
208 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
209 }
210
211 addrCreateInput.callbacks.allocSysMem = allocSysMem;
212 addrCreateInput.callbacks.freeSysMem = freeSysMem;
213 addrCreateInput.callbacks.debugPrint = 0;
214 addrCreateInput.createFlags = createFlags;
215 addrCreateInput.regValue = regValue;
216
217 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
218 if (addrRet != ADDR_OK)
219 return NULL;
220
221 if (max_alignment) {
222 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
223 if (addrRet == ADDR_OK){
224 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
225 }
226 }
227 return addrCreateOutput.hLib;
228 }
229
230 static int surf_config_sanity(const struct ac_surf_config *config,
231 unsigned flags)
232 {
233 /* FMASK is allocated together with the color surface and can't be
234 * allocated separately.
235 */
236 assert(!(flags & RADEON_SURF_FMASK));
237 if (flags & RADEON_SURF_FMASK)
238 return -EINVAL;
239
240 /* all dimension must be at least 1 ! */
241 if (!config->info.width || !config->info.height || !config->info.depth ||
242 !config->info.array_size || !config->info.levels)
243 return -EINVAL;
244
245 switch (config->info.samples) {
246 case 0:
247 case 1:
248 case 2:
249 case 4:
250 case 8:
251 break;
252 case 16:
253 if (flags & RADEON_SURF_Z_OR_SBUFFER)
254 return -EINVAL;
255 break;
256 default:
257 return -EINVAL;
258 }
259
260 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
261 switch (config->info.color_samples) {
262 case 0:
263 case 1:
264 case 2:
265 case 4:
266 case 8:
267 break;
268 default:
269 return -EINVAL;
270 }
271 }
272
273 if (config->is_3d && config->info.array_size > 1)
274 return -EINVAL;
275 if (config->is_cube && config->info.depth > 1)
276 return -EINVAL;
277
278 return 0;
279 }
280
281 static int gfx6_compute_level(ADDR_HANDLE addrlib,
282 const struct ac_surf_config *config,
283 struct radeon_surf *surf, bool is_stencil,
284 unsigned level, bool compressed,
285 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
286 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
287 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
288 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
289 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
290 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
291 {
292 struct legacy_surf_level *surf_level;
293 ADDR_E_RETURNCODE ret;
294
295 AddrSurfInfoIn->mipLevel = level;
296 AddrSurfInfoIn->width = u_minify(config->info.width, level);
297 AddrSurfInfoIn->height = u_minify(config->info.height, level);
298
299 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
300 * because GFX9 needs linear alignment of 256 bytes.
301 */
302 if (config->info.levels == 1 &&
303 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
304 AddrSurfInfoIn->bpp &&
305 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
306 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
307
308 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
309 }
310
311 if (config->is_3d)
312 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
313 else if (config->is_cube)
314 AddrSurfInfoIn->numSlices = 6;
315 else
316 AddrSurfInfoIn->numSlices = config->info.array_size;
317
318 if (level > 0) {
319 /* Set the base level pitch. This is needed for calculation
320 * of non-zero levels. */
321 if (is_stencil)
322 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
323 else
324 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
325
326 /* Convert blocks to pixels for compressed formats. */
327 if (compressed)
328 AddrSurfInfoIn->basePitch *= surf->blk_w;
329 }
330
331 ret = AddrComputeSurfaceInfo(addrlib,
332 AddrSurfInfoIn,
333 AddrSurfInfoOut);
334 if (ret != ADDR_OK) {
335 return ret;
336 }
337
338 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
339 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
340 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
341 surf_level->nblk_x = AddrSurfInfoOut->pitch;
342 surf_level->nblk_y = AddrSurfInfoOut->height;
343
344 switch (AddrSurfInfoOut->tileMode) {
345 case ADDR_TM_LINEAR_ALIGNED:
346 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
347 break;
348 case ADDR_TM_1D_TILED_THIN1:
349 surf_level->mode = RADEON_SURF_MODE_1D;
350 break;
351 case ADDR_TM_2D_TILED_THIN1:
352 surf_level->mode = RADEON_SURF_MODE_2D;
353 break;
354 default:
355 assert(0);
356 }
357
358 if (is_stencil)
359 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
360 else
361 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
362
363 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
364
365 /* Clear DCC fields at the beginning. */
366 surf_level->dcc_offset = 0;
367
368 /* The previous level's flag tells us if we can use DCC for this level. */
369 if (AddrSurfInfoIn->flags.dccCompatible &&
370 (level == 0 || AddrDccOut->subLvlCompressible)) {
371 bool prev_level_clearable = level == 0 ||
372 AddrDccOut->dccRamSizeAligned;
373
374 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
375 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
376 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
377 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
378 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
379
380 ret = AddrComputeDccInfo(addrlib,
381 AddrDccIn,
382 AddrDccOut);
383
384 if (ret == ADDR_OK) {
385 surf_level->dcc_offset = surf->dcc_size;
386 surf->num_dcc_levels = level + 1;
387 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
388 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
389
390 /* If the DCC size of a subresource (1 mip level or 1 slice)
391 * is not aligned, the DCC memory layout is not contiguous for
392 * that subresource, which means we can't use fast clear.
393 *
394 * We only do fast clears for whole mipmap levels. If we did
395 * per-slice fast clears, the same restriction would apply.
396 * (i.e. only compute the slice size and see if it's aligned)
397 *
398 * The last level can be non-contiguous and still be clearable
399 * if it's interleaved with the next level that doesn't exist.
400 */
401 if (AddrDccOut->dccRamSizeAligned ||
402 (prev_level_clearable && level == config->info.levels - 1))
403 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
404 else
405 surf_level->dcc_fast_clear_size = 0;
406 }
407 }
408
409 /* TC-compatible HTILE. */
410 if (!is_stencil &&
411 AddrSurfInfoIn->flags.depth &&
412 surf_level->mode == RADEON_SURF_MODE_2D &&
413 level == 0) {
414 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
415 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
416 AddrHtileIn->height = AddrSurfInfoOut->height;
417 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
418 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
419 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
420 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
421 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
422 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
423
424 ret = AddrComputeHtileInfo(addrlib,
425 AddrHtileIn,
426 AddrHtileOut);
427
428 if (ret == ADDR_OK) {
429 surf->htile_size = AddrHtileOut->htileBytes;
430 surf->htile_slice_size = AddrHtileOut->sliceSize;
431 surf->htile_alignment = AddrHtileOut->baseAlign;
432 }
433 }
434
435 return 0;
436 }
437
438 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
439 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
440 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
441
442 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
443 const struct radeon_info *info)
444 {
445 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
446
447 if (info->chip_class >= CIK)
448 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
449 else
450 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
451 }
452
453 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
454 {
455 unsigned index, tileb;
456
457 tileb = 8 * 8 * surf->bpe;
458 tileb = MIN2(surf->u.legacy.tile_split, tileb);
459
460 for (index = 0; tileb > 64; index++)
461 tileb >>= 1;
462
463 assert(index < 16);
464 return index;
465 }
466
467 static bool get_display_flag(const struct ac_surf_config *config,
468 const struct radeon_surf *surf)
469 {
470 unsigned num_channels = config->info.num_channels;
471 unsigned bpe = surf->bpe;
472
473 if (surf->flags & RADEON_SURF_SCANOUT &&
474 config->info.samples <= 1 &&
475 surf->blk_w <= 2 && surf->blk_h == 1) {
476 /* subsampled */
477 if (surf->blk_w == 2 && surf->blk_h == 1)
478 return true;
479
480 if (/* RGBA8 or RGBA16F */
481 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
482 /* R5G6B5 or R5G5B5A1 */
483 (bpe == 2 && num_channels >= 3) ||
484 /* C8 palette */
485 (bpe == 1 && num_channels == 1))
486 return true;
487 }
488 return false;
489 }
490
491 /**
492 * This must be called after the first level is computed.
493 *
494 * Copy surface-global settings like pipe/bank config from level 0 surface
495 * computation, and compute tile swizzle.
496 */
497 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
498 const struct radeon_info *info,
499 const struct ac_surf_config *config,
500 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
501 struct radeon_surf *surf)
502 {
503 surf->surf_alignment = csio->baseAlign;
504 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
505 gfx6_set_micro_tile_mode(surf, info);
506
507 /* For 2D modes only. */
508 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
509 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
510 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
511 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
512 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
513 surf->u.legacy.num_banks = csio->pTileInfo->banks;
514 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
515 } else {
516 surf->u.legacy.macro_tile_index = 0;
517 }
518
519 /* Compute tile swizzle. */
520 /* TODO: fix tile swizzle with mipmapping for SI */
521 if ((info->chip_class >= CIK || config->info.levels == 1) &&
522 config->info.surf_index &&
523 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
524 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
525 !get_display_flag(config, surf)) {
526 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
527 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
528
529 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
530 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
531
532 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
533 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
534 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
535 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
536 AddrBaseSwizzleIn.tileMode = csio->tileMode;
537
538 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
539 &AddrBaseSwizzleOut);
540 if (r != ADDR_OK)
541 return r;
542
543 assert(AddrBaseSwizzleOut.tileSwizzle <=
544 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
545 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
546 }
547 return 0;
548 }
549
550 void ac_compute_cmask(const struct radeon_info *info,
551 const struct ac_surf_config *config,
552 struct radeon_surf *surf)
553 {
554 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
555 unsigned num_pipes = info->num_tile_pipes;
556 unsigned cl_width, cl_height;
557
558 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
559 return;
560
561 assert(info->chip_class <= VI);
562
563 switch (num_pipes) {
564 case 2:
565 cl_width = 32;
566 cl_height = 16;
567 break;
568 case 4:
569 cl_width = 32;
570 cl_height = 32;
571 break;
572 case 8:
573 cl_width = 64;
574 cl_height = 32;
575 break;
576 case 16: /* Hawaii */
577 cl_width = 64;
578 cl_height = 64;
579 break;
580 default:
581 assert(0);
582 return;
583 }
584
585 unsigned base_align = num_pipes * pipe_interleave_bytes;
586
587 unsigned width = align(config->info.width, cl_width*8);
588 unsigned height = align(config->info.height, cl_height*8);
589 unsigned slice_elements = (width * height) / (8*8);
590
591 /* Each element of CMASK is a nibble. */
592 unsigned slice_bytes = slice_elements / 2;
593
594 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
595 if (surf->u.legacy.cmask_slice_tile_max)
596 surf->u.legacy.cmask_slice_tile_max -= 1;
597
598 unsigned num_layers;
599 if (config->is_3d)
600 num_layers = config->info.depth;
601 else if (config->is_cube)
602 num_layers = 6;
603 else
604 num_layers = config->info.array_size;
605
606 surf->cmask_alignment = MAX2(256, base_align);
607 surf->cmask_size = align(slice_bytes, base_align) * num_layers;
608 }
609
610 /**
611 * Fill in the tiling information in \p surf based on the given surface config.
612 *
613 * The following fields of \p surf must be initialized by the caller:
614 * blk_w, blk_h, bpe, flags.
615 */
616 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
617 const struct radeon_info *info,
618 const struct ac_surf_config *config,
619 enum radeon_surf_mode mode,
620 struct radeon_surf *surf)
621 {
622 unsigned level;
623 bool compressed;
624 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
625 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
626 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
627 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
628 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
629 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
630 ADDR_TILEINFO AddrTileInfoIn = {0};
631 ADDR_TILEINFO AddrTileInfoOut = {0};
632 int r;
633
634 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
635 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
636 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
637 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
638 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
639 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
640 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
641
642 compressed = surf->blk_w == 4 && surf->blk_h == 4;
643
644 /* MSAA requires 2D tiling. */
645 if (config->info.samples > 1)
646 mode = RADEON_SURF_MODE_2D;
647
648 /* DB doesn't support linear layouts. */
649 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
650 mode < RADEON_SURF_MODE_1D)
651 mode = RADEON_SURF_MODE_1D;
652
653 /* Set the requested tiling mode. */
654 switch (mode) {
655 case RADEON_SURF_MODE_LINEAR_ALIGNED:
656 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
657 break;
658 case RADEON_SURF_MODE_1D:
659 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
660 break;
661 case RADEON_SURF_MODE_2D:
662 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
663 break;
664 default:
665 assert(0);
666 }
667
668 /* The format must be set correctly for the allocation of compressed
669 * textures to work. In other cases, setting the bpp is sufficient.
670 */
671 if (compressed) {
672 switch (surf->bpe) {
673 case 8:
674 AddrSurfInfoIn.format = ADDR_FMT_BC1;
675 break;
676 case 16:
677 AddrSurfInfoIn.format = ADDR_FMT_BC3;
678 break;
679 default:
680 assert(0);
681 }
682 }
683 else {
684 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
685 }
686
687 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
688 MAX2(1, config->info.samples);
689 AddrSurfInfoIn.tileIndex = -1;
690
691 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
692 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
693 MAX2(1, config->info.color_samples);
694 }
695
696 /* Set the micro tile type. */
697 if (surf->flags & RADEON_SURF_SCANOUT)
698 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
699 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
700 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
701 else
702 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
703
704 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
705 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
706 AddrSurfInfoIn.flags.cube = config->is_cube;
707 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
708 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
709 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
710
711 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
712 * requested, because TC-compatible HTILE requires 2D tiling.
713 */
714 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
715 !AddrSurfInfoIn.flags.fmask &&
716 config->info.samples <= 1 &&
717 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
718
719 /* DCC notes:
720 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
721 * with samples >= 4.
722 * - Mipmapped array textures have low performance (discovered by a closed
723 * driver team).
724 */
725 AddrSurfInfoIn.flags.dccCompatible =
726 info->chip_class >= VI &&
727 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
728 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
729 !compressed &&
730 ((config->info.array_size == 1 && config->info.depth == 1) ||
731 config->info.levels == 1);
732
733 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
734 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
735
736 /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
737 * for Z and stencil. This can cause a number of problems which we work
738 * around here:
739 *
740 * - a depth part that is incompatible with mipmapped texturing
741 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
742 * incorrect tiling applied to the stencil part, stencil buffer
743 * memory accesses that go out of bounds) even without mipmapping
744 *
745 * Some piglit tests that are prone to different types of related
746 * failures:
747 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
748 * ./bin/framebuffer-blit-levels {draw,read} stencil
749 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
750 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
751 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
752 */
753 int stencil_tile_idx = -1;
754
755 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
756 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
757 /* Compute stencilTileIdx that is compatible with the (depth)
758 * tileIdx. This degrades the depth surface if necessary to
759 * ensure that a matching stencilTileIdx exists. */
760 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
761
762 /* Keep the depth mip-tail compatible with texturing. */
763 AddrSurfInfoIn.flags.noStencil = 1;
764 }
765
766 /* Set preferred macrotile parameters. This is usually required
767 * for shared resources. This is for 2D tiling only. */
768 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
769 surf->u.legacy.bankw && surf->u.legacy.bankh &&
770 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
771 /* If any of these parameters are incorrect, the calculation
772 * will fail. */
773 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
774 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
775 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
776 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
777 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
778 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
779 AddrSurfInfoIn.flags.opt4Space = 0;
780 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
781
782 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
783 * the tile index, because we are expected to know it if
784 * we know the other parameters.
785 *
786 * This is something that can easily be fixed in Addrlib.
787 * For now, just figure it out here.
788 * Note that only 2D_TILE_THIN1 is handled here.
789 */
790 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
791 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
792
793 if (info->chip_class == SI) {
794 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
795 if (surf->bpe == 2)
796 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
797 else
798 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
799 } else {
800 if (surf->bpe == 1)
801 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
802 else if (surf->bpe == 2)
803 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
804 else if (surf->bpe == 4)
805 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
806 else
807 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
808 }
809 } else {
810 /* CIK - VI */
811 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
812 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
813 else
814 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
815
816 /* Addrlib doesn't set this if tileIndex is forced like above. */
817 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
818 }
819 }
820
821 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
822 surf->num_dcc_levels = 0;
823 surf->surf_size = 0;
824 surf->dcc_size = 0;
825 surf->dcc_alignment = 1;
826 surf->htile_size = 0;
827 surf->htile_slice_size = 0;
828 surf->htile_alignment = 1;
829
830 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
831 !(surf->flags & RADEON_SURF_ZBUFFER);
832
833 /* Calculate texture layout information. */
834 if (!only_stencil) {
835 for (level = 0; level < config->info.levels; level++) {
836 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
837 &AddrSurfInfoIn, &AddrSurfInfoOut,
838 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
839 if (r)
840 return r;
841
842 if (level > 0)
843 continue;
844
845 /* Check that we actually got a TC-compatible HTILE if
846 * we requested it (only for level 0, since we're not
847 * supporting HTILE on higher mip levels anyway). */
848 assert(AddrSurfInfoOut.tcCompatible ||
849 !AddrSurfInfoIn.flags.tcCompatible ||
850 AddrSurfInfoIn.flags.matchStencilTileCfg);
851
852 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
853 if (!AddrSurfInfoOut.tcCompatible) {
854 AddrSurfInfoIn.flags.tcCompatible = 0;
855 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
856 }
857
858 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
859 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
860 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
861
862 assert(stencil_tile_idx >= 0);
863 }
864
865 r = gfx6_surface_settings(addrlib, info, config,
866 &AddrSurfInfoOut, surf);
867 if (r)
868 return r;
869 }
870 }
871
872 /* Calculate texture layout information for stencil. */
873 if (surf->flags & RADEON_SURF_SBUFFER) {
874 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
875 AddrSurfInfoIn.bpp = 8;
876 AddrSurfInfoIn.flags.depth = 0;
877 AddrSurfInfoIn.flags.stencil = 1;
878 AddrSurfInfoIn.flags.tcCompatible = 0;
879 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
880 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
881
882 for (level = 0; level < config->info.levels; level++) {
883 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
884 &AddrSurfInfoIn, &AddrSurfInfoOut,
885 &AddrDccIn, &AddrDccOut,
886 NULL, NULL);
887 if (r)
888 return r;
889
890 /* DB uses the depth pitch for both stencil and depth. */
891 if (!only_stencil) {
892 if (surf->u.legacy.stencil_level[level].nblk_x !=
893 surf->u.legacy.level[level].nblk_x)
894 surf->u.legacy.stencil_adjusted = true;
895 } else {
896 surf->u.legacy.level[level].nblk_x =
897 surf->u.legacy.stencil_level[level].nblk_x;
898 }
899
900 if (level == 0) {
901 if (only_stencil) {
902 r = gfx6_surface_settings(addrlib, info, config,
903 &AddrSurfInfoOut, surf);
904 if (r)
905 return r;
906 }
907
908 /* For 2D modes only. */
909 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
910 surf->u.legacy.stencil_tile_split =
911 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
912 }
913 }
914 }
915 }
916
917 /* Compute FMASK. */
918 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
919 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
920 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
921 ADDR_TILEINFO fmask_tile_info = {};
922
923 fin.size = sizeof(fin);
924 fout.size = sizeof(fout);
925
926 fin.tileMode = AddrSurfInfoOut.tileMode;
927 fin.pitch = AddrSurfInfoOut.pitch;
928 fin.height = config->info.height;
929 fin.numSlices = AddrSurfInfoIn.numSlices;
930 fin.numSamples = AddrSurfInfoIn.numSamples;
931 fin.numFrags = AddrSurfInfoIn.numFrags;
932 fin.tileIndex = -1;
933 fout.pTileInfo = &fmask_tile_info;
934
935 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
936 if (r)
937 return r;
938
939 surf->fmask_size = fout.fmaskBytes;
940 surf->fmask_alignment = fout.baseAlign;
941 surf->fmask_tile_swizzle = 0;
942
943 surf->u.legacy.fmask.slice_tile_max =
944 (fout.pitch * fout.height) / 64;
945 if (surf->u.legacy.fmask.slice_tile_max)
946 surf->u.legacy.fmask.slice_tile_max -= 1;
947
948 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
949 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
950 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
951
952 /* Compute tile swizzle for FMASK. */
953 if (config->info.fmask_surf_index &&
954 !(surf->flags & RADEON_SURF_SHAREABLE)) {
955 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
956 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
957
958 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
959 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
960
961 /* This counter starts from 1 instead of 0. */
962 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
963 xin.tileIndex = fout.tileIndex;
964 xin.macroModeIndex = fout.macroModeIndex;
965 xin.pTileInfo = fout.pTileInfo;
966 xin.tileMode = fin.tileMode;
967
968 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
969 if (r != ADDR_OK)
970 return r;
971
972 assert(xout.tileSwizzle <=
973 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
974 surf->fmask_tile_swizzle = xout.tileSwizzle;
975 }
976 }
977
978 /* Recalculate the whole DCC miptree size including disabled levels.
979 * This is what addrlib does, but calling addrlib would be a lot more
980 * complicated.
981 */
982 if (surf->dcc_size && config->info.levels > 1) {
983 /* The smallest miplevels that are never compressed by DCC
984 * still read the DCC buffer via TC if the base level uses DCC,
985 * and for some reason the DCC buffer needs to be larger if
986 * the miptree uses non-zero tile_swizzle. Otherwise there are
987 * VM faults.
988 *
989 * "dcc_alignment * 4" was determined by trial and error.
990 */
991 surf->dcc_size = align64(surf->surf_size >> 8,
992 surf->dcc_alignment * 4);
993 }
994
995 /* Make sure HTILE covers the whole miptree, because the shader reads
996 * TC-compatible HTILE even for levels where it's disabled by DB.
997 */
998 if (surf->htile_size && config->info.levels > 1 &&
999 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
1000 /* MSAA can't occur with levels > 1, so ignore the sample count. */
1001 const unsigned total_pixels = surf->surf_size / surf->bpe;
1002 const unsigned htile_block_size = 8 * 8;
1003 const unsigned htile_element_size = 4;
1004
1005 surf->htile_size = (total_pixels / htile_block_size) *
1006 htile_element_size;
1007 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
1008 }
1009
1010 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
1011 surf->is_displayable = surf->is_linear ||
1012 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
1013 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
1014
1015 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1016 * used at the same time. This case is not currently expected to occur
1017 * because we don't use rotated. Enforce this restriction on all chips
1018 * to facilitate testing.
1019 */
1020 if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
1021 assert(!"rotate micro tile mode is unsupported");
1022 return ADDR_ERROR;
1023 }
1024
1025 ac_compute_cmask(info, config, surf);
1026 return 0;
1027 }
1028
1029 /* This is only called when expecting a tiled layout. */
1030 static int
1031 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
1032 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
1033 bool is_fmask, unsigned flags,
1034 AddrSwizzleMode *swizzle_mode)
1035 {
1036 ADDR_E_RETURNCODE ret;
1037 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
1038 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
1039
1040 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
1041 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
1042
1043 sin.flags = in->flags;
1044 sin.resourceType = in->resourceType;
1045 sin.format = in->format;
1046 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
1047 /* TODO: We could allow some of these: */
1048 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
1049 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
1050 sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
1051 sin.bpp = in->bpp;
1052 sin.width = in->width;
1053 sin.height = in->height;
1054 sin.numSlices = in->numSlices;
1055 sin.numMipLevels = in->numMipLevels;
1056 sin.numSamples = in->numSamples;
1057 sin.numFrags = in->numFrags;
1058
1059 if (flags & RADEON_SURF_SCANOUT) {
1060 sin.preferredSwSet.sw_D = 1;
1061 /* Raven only allows S for displayable surfaces with < 64 bpp, so
1062 * allow it as fallback */
1063 sin.preferredSwSet.sw_S = 1;
1064 } else if (in->flags.depth || in->flags.stencil || is_fmask)
1065 sin.preferredSwSet.sw_Z = 1;
1066 else
1067 sin.preferredSwSet.sw_S = 1;
1068
1069 if (is_fmask) {
1070 sin.flags.display = 0;
1071 sin.flags.color = 0;
1072 sin.flags.fmask = 1;
1073 }
1074
1075 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
1076 if (ret != ADDR_OK)
1077 return ret;
1078
1079 *swizzle_mode = sout.swizzleMode;
1080 return 0;
1081 }
1082
1083 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
1084 const struct ac_surf_config *config,
1085 struct radeon_surf *surf, bool compressed,
1086 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
1087 {
1088 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
1089 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
1090 ADDR_E_RETURNCODE ret;
1091
1092 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
1093 out.pMipInfo = mip_info;
1094
1095 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
1096 if (ret != ADDR_OK)
1097 return ret;
1098
1099 if (in->flags.stencil) {
1100 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1101 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1102 out.mipChainPitch - 1;
1103 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1104 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1105 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1106 return 0;
1107 }
1108
1109 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1110 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1111 out.mipChainPitch - 1;
1112
1113 /* CMASK fast clear uses these even if FMASK isn't allocated.
1114 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1115 */
1116 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1117 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1118
1119 surf->u.gfx9.surf_slice_size = out.sliceSize;
1120 surf->u.gfx9.surf_pitch = out.pitch;
1121 surf->u.gfx9.surf_height = out.height;
1122 surf->surf_size = out.surfSize;
1123 surf->surf_alignment = out.baseAlign;
1124
1125 if (in->swizzleMode == ADDR_SW_LINEAR) {
1126 for (unsigned i = 0; i < in->numMipLevels; i++)
1127 surf->u.gfx9.offset[i] = mip_info[i].offset;
1128 }
1129
1130 if (in->flags.depth) {
1131 assert(in->swizzleMode != ADDR_SW_LINEAR);
1132
1133 /* HTILE */
1134 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1135 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1136
1137 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1138 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1139
1140 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1141 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1142 hin.depthFlags = in->flags;
1143 hin.swizzleMode = in->swizzleMode;
1144 hin.unalignedWidth = in->width;
1145 hin.unalignedHeight = in->height;
1146 hin.numSlices = in->numSlices;
1147 hin.numMipLevels = in->numMipLevels;
1148
1149 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1150 if (ret != ADDR_OK)
1151 return ret;
1152
1153 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1154 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1155 surf->htile_size = hout.htileBytes;
1156 surf->htile_slice_size = hout.sliceSize;
1157 surf->htile_alignment = hout.baseAlign;
1158 } else {
1159 /* Compute tile swizzle for the color surface.
1160 * All *_X and *_T modes can use the swizzle.
1161 */
1162 if (config->info.surf_index &&
1163 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1164 !out.mipChainInTail &&
1165 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1166 !in->flags.display) {
1167 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1168 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1169
1170 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1171 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1172
1173 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1174 xin.flags = in->flags;
1175 xin.swizzleMode = in->swizzleMode;
1176 xin.resourceType = in->resourceType;
1177 xin.format = in->format;
1178 xin.numSamples = in->numSamples;
1179 xin.numFrags = in->numFrags;
1180
1181 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1182 if (ret != ADDR_OK)
1183 return ret;
1184
1185 assert(xout.pipeBankXor <=
1186 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1187 surf->tile_swizzle = xout.pipeBankXor;
1188 }
1189
1190 /* DCC */
1191 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1192 !compressed &&
1193 in->swizzleMode != ADDR_SW_LINEAR) {
1194 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1195 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1196 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1197
1198 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1199 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1200 dout.pMipInfo = meta_mip_info;
1201
1202 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1203 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1204 din.colorFlags = in->flags;
1205 din.resourceType = in->resourceType;
1206 din.swizzleMode = in->swizzleMode;
1207 din.bpp = in->bpp;
1208 din.unalignedWidth = in->width;
1209 din.unalignedHeight = in->height;
1210 din.numSlices = in->numSlices;
1211 din.numFrags = in->numFrags;
1212 din.numMipLevels = in->numMipLevels;
1213 din.dataSurfaceSize = out.surfSize;
1214
1215 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1216 if (ret != ADDR_OK)
1217 return ret;
1218
1219 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1220 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1221 surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
1222 surf->dcc_size = dout.dccRamSize;
1223 surf->dcc_alignment = dout.dccRamBaseAlign;
1224 surf->num_dcc_levels = in->numMipLevels;
1225
1226 /* Disable DCC for levels that are in the mip tail.
1227 *
1228 * There are two issues that this is intended to
1229 * address:
1230 *
1231 * 1. Multiple mip levels may share a cache line. This
1232 * can lead to corruption when switching between
1233 * rendering to different mip levels because the
1234 * RBs don't maintain coherency.
1235 *
1236 * 2. Texturing with metadata after rendering sometimes
1237 * fails with corruption, probably for a similar
1238 * reason.
1239 *
1240 * Working around these issues for all levels in the
1241 * mip tail may be overly conservative, but it's what
1242 * Vulkan does.
1243 *
1244 * Alternative solutions that also work but are worse:
1245 * - Disable DCC entirely.
1246 * - Flush TC L2 after rendering.
1247 */
1248 for (unsigned i = 0; i < in->numMipLevels; i++) {
1249 if (meta_mip_info[i].inMiptail) {
1250 surf->num_dcc_levels = i;
1251 break;
1252 }
1253 }
1254
1255 if (!surf->num_dcc_levels)
1256 surf->dcc_size = 0;
1257 }
1258
1259 /* FMASK */
1260 if (in->numSamples > 1) {
1261 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1262 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1263
1264 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1265 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1266
1267 ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
1268 true, surf->flags,
1269 &fin.swizzleMode);
1270 if (ret != ADDR_OK)
1271 return ret;
1272
1273 fin.unalignedWidth = in->width;
1274 fin.unalignedHeight = in->height;
1275 fin.numSlices = in->numSlices;
1276 fin.numSamples = in->numSamples;
1277 fin.numFrags = in->numFrags;
1278
1279 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1280 if (ret != ADDR_OK)
1281 return ret;
1282
1283 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1284 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1285 surf->fmask_size = fout.fmaskBytes;
1286 surf->fmask_alignment = fout.baseAlign;
1287
1288 /* Compute tile swizzle for the FMASK surface. */
1289 if (config->info.fmask_surf_index &&
1290 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1291 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1292 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1293 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1294
1295 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1296 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1297
1298 /* This counter starts from 1 instead of 0. */
1299 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1300 xin.flags = in->flags;
1301 xin.swizzleMode = in->swizzleMode;
1302 xin.resourceType = in->resourceType;
1303 xin.format = in->format;
1304 xin.numSamples = in->numSamples;
1305 xin.numFrags = in->numFrags;
1306
1307 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1308 if (ret != ADDR_OK)
1309 return ret;
1310
1311 assert(xout.pipeBankXor <=
1312 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1313 surf->fmask_tile_swizzle = xout.pipeBankXor;
1314 }
1315 }
1316
1317 /* CMASK */
1318 if (in->swizzleMode != ADDR_SW_LINEAR) {
1319 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1320 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1321
1322 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1323 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1324
1325 if (in->numSamples > 1) {
1326 /* FMASK is always aligned. */
1327 cin.cMaskFlags.pipeAligned = 1;
1328 cin.cMaskFlags.rbAligned = 1;
1329 } else {
1330 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1331 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1332 }
1333 cin.colorFlags = in->flags;
1334 cin.resourceType = in->resourceType;
1335 cin.unalignedWidth = in->width;
1336 cin.unalignedHeight = in->height;
1337 cin.numSlices = in->numSlices;
1338
1339 if (in->numSamples > 1)
1340 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1341 else
1342 cin.swizzleMode = in->swizzleMode;
1343
1344 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1345 if (ret != ADDR_OK)
1346 return ret;
1347
1348 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1349 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1350 surf->cmask_size = cout.cmaskBytes;
1351 surf->cmask_alignment = cout.baseAlign;
1352 }
1353 }
1354
1355 return 0;
1356 }
1357
1358 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1359 const struct radeon_info *info,
1360 const struct ac_surf_config *config,
1361 enum radeon_surf_mode mode,
1362 struct radeon_surf *surf)
1363 {
1364 bool compressed;
1365 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1366 int r;
1367
1368 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1369
1370 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1371
1372 /* The format must be set correctly for the allocation of compressed
1373 * textures to work. In other cases, setting the bpp is sufficient. */
1374 if (compressed) {
1375 switch (surf->bpe) {
1376 case 8:
1377 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1378 break;
1379 case 16:
1380 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1381 break;
1382 default:
1383 assert(0);
1384 }
1385 } else {
1386 switch (surf->bpe) {
1387 case 1:
1388 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1389 AddrSurfInfoIn.format = ADDR_FMT_8;
1390 break;
1391 case 2:
1392 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1393 !(surf->flags & RADEON_SURF_SBUFFER));
1394 AddrSurfInfoIn.format = ADDR_FMT_16;
1395 break;
1396 case 4:
1397 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1398 !(surf->flags & RADEON_SURF_SBUFFER));
1399 AddrSurfInfoIn.format = ADDR_FMT_32;
1400 break;
1401 case 8:
1402 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1403 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1404 break;
1405 case 12:
1406 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1407 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1408 break;
1409 case 16:
1410 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1411 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1412 break;
1413 default:
1414 assert(0);
1415 }
1416 AddrSurfInfoIn.bpp = surf->bpe * 8;
1417 }
1418
1419 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1420 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1421 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1422 /* flags.texture currently refers to TC-compatible HTILE */
1423 AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
1424 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1425 AddrSurfInfoIn.flags.opt4space = 1;
1426
1427 AddrSurfInfoIn.numMipLevels = config->info.levels;
1428 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1429 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1430
1431 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1432 AddrSurfInfoIn.numFrags = MAX2(1, config->info.color_samples);
1433
1434 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1435 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1436 * must sample 1D textures as 2D. */
1437 if (config->is_3d)
1438 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1439 else
1440 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1441
1442 AddrSurfInfoIn.width = config->info.width;
1443 AddrSurfInfoIn.height = config->info.height;
1444
1445 if (config->is_3d)
1446 AddrSurfInfoIn.numSlices = config->info.depth;
1447 else if (config->is_cube)
1448 AddrSurfInfoIn.numSlices = 6;
1449 else
1450 AddrSurfInfoIn.numSlices = config->info.array_size;
1451
1452 /* This is propagated to HTILE/DCC/CMASK. */
1453 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1454 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1455
1456 switch (mode) {
1457 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1458 assert(config->info.samples <= 1);
1459 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1460 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1461 break;
1462
1463 case RADEON_SURF_MODE_1D:
1464 case RADEON_SURF_MODE_2D:
1465 if (surf->flags & RADEON_SURF_IMPORTED) {
1466 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1467 break;
1468 }
1469
1470 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1471 false, surf->flags,
1472 &AddrSurfInfoIn.swizzleMode);
1473 if (r)
1474 return r;
1475 break;
1476
1477 default:
1478 assert(0);
1479 }
1480
1481 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1482 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1483
1484 surf->num_dcc_levels = 0;
1485 surf->surf_size = 0;
1486 surf->fmask_size = 0;
1487 surf->dcc_size = 0;
1488 surf->htile_size = 0;
1489 surf->htile_slice_size = 0;
1490 surf->u.gfx9.surf_offset = 0;
1491 surf->u.gfx9.stencil_offset = 0;
1492 surf->cmask_size = 0;
1493
1494 /* Calculate texture layout information. */
1495 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1496 &AddrSurfInfoIn);
1497 if (r)
1498 return r;
1499
1500 /* Calculate texture layout information for stencil. */
1501 if (surf->flags & RADEON_SURF_SBUFFER) {
1502 AddrSurfInfoIn.flags.stencil = 1;
1503 AddrSurfInfoIn.bpp = 8;
1504 AddrSurfInfoIn.format = ADDR_FMT_8;
1505
1506 if (!AddrSurfInfoIn.flags.depth) {
1507 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1508 false, surf->flags,
1509 &AddrSurfInfoIn.swizzleMode);
1510 if (r)
1511 return r;
1512 } else
1513 AddrSurfInfoIn.flags.depth = 0;
1514
1515 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1516 &AddrSurfInfoIn);
1517 if (r)
1518 return r;
1519 }
1520
1521 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1522
1523 /* Query whether the surface is displayable. */
1524 bool displayable = false;
1525 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1526 surf->bpe * 8, &displayable);
1527 if (r)
1528 return r;
1529 surf->is_displayable = displayable;
1530
1531 switch (surf->u.gfx9.surf.swizzle_mode) {
1532 /* S = standard. */
1533 case ADDR_SW_256B_S:
1534 case ADDR_SW_4KB_S:
1535 case ADDR_SW_64KB_S:
1536 case ADDR_SW_VAR_S:
1537 case ADDR_SW_64KB_S_T:
1538 case ADDR_SW_4KB_S_X:
1539 case ADDR_SW_64KB_S_X:
1540 case ADDR_SW_VAR_S_X:
1541 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1542 break;
1543
1544 /* D = display. */
1545 case ADDR_SW_LINEAR:
1546 case ADDR_SW_256B_D:
1547 case ADDR_SW_4KB_D:
1548 case ADDR_SW_64KB_D:
1549 case ADDR_SW_VAR_D:
1550 case ADDR_SW_64KB_D_T:
1551 case ADDR_SW_4KB_D_X:
1552 case ADDR_SW_64KB_D_X:
1553 case ADDR_SW_VAR_D_X:
1554 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1555 break;
1556
1557 /* R = rotated. */
1558 case ADDR_SW_256B_R:
1559 case ADDR_SW_4KB_R:
1560 case ADDR_SW_64KB_R:
1561 case ADDR_SW_VAR_R:
1562 case ADDR_SW_64KB_R_T:
1563 case ADDR_SW_4KB_R_X:
1564 case ADDR_SW_64KB_R_X:
1565 case ADDR_SW_VAR_R_X:
1566 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1567 * used at the same time. This case is not currently expected to occur
1568 * because we don't use rotated. Enforce this restriction on all chips
1569 * to facilitate testing.
1570 */
1571 assert(!"rotate micro tile mode is unsupported");
1572 return ADDR_ERROR;
1573
1574 /* Z = depth. */
1575 case ADDR_SW_4KB_Z:
1576 case ADDR_SW_64KB_Z:
1577 case ADDR_SW_VAR_Z:
1578 case ADDR_SW_64KB_Z_T:
1579 case ADDR_SW_4KB_Z_X:
1580 case ADDR_SW_64KB_Z_X:
1581 case ADDR_SW_VAR_Z_X:
1582 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1583 break;
1584
1585 default:
1586 assert(0);
1587 }
1588
1589 /* Temporary workaround to prevent VM faults and hangs. */
1590 if (info->family == CHIP_VEGA12)
1591 surf->fmask_size *= 8;
1592
1593 return 0;
1594 }
1595
1596 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1597 const struct ac_surf_config *config,
1598 enum radeon_surf_mode mode,
1599 struct radeon_surf *surf)
1600 {
1601 int r;
1602
1603 r = surf_config_sanity(config, surf->flags);
1604 if (r)
1605 return r;
1606
1607 if (info->chip_class >= GFX9)
1608 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1609 else
1610 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1611 }