projects / mesa.git / blob
? search:


c64f9903aadf36763bbebfa5a4c66b751d471b71
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35 #include "sid.h"
36
37 #include <errno.h>
38 #include <stdio.h>
39 #include <stdlib.h>
40 #include <amdgpu.h>
41 #include "drm-uapi/amdgpu_drm.h"
42
43 #include "addrlib/inc/addrinterface.h"
44
45 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
46 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
47 #endif
48
49 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
50 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
51 #endif
52
53 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
54 {
55 return malloc(pInput->sizeInBytes);
56 }
57
58 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
59 {
60 free(pInput->pVirtAddr);
61 return ADDR_OK;
62 }
63
64 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
65 const struct amdgpu_gpu_info *amdinfo,
66 uint64_t *max_alignment)
67 {
68 ADDR_CREATE_INPUT addrCreateInput = {0};
69 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
70 ADDR_REGISTER_VALUE regValue = {0};
71 ADDR_CREATE_FLAGS createFlags = {{0}};
72 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
73 ADDR_E_RETURNCODE addrRet;
74
75 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
76 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
77
78 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
79 createFlags.value = 0;
80
81 addrCreateInput.chipFamily = info->family_id;
82 addrCreateInput.chipRevision = info->chip_external_rev;
83
84 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
85 return NULL;
86
87 if (addrCreateInput.chipFamily >= FAMILY_AI) {
88 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
89 } else {
90 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
91 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
92
93 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
94 regValue.pTileConfig = amdinfo->gb_tile_mode;
95 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
96 if (addrCreateInput.chipFamily == FAMILY_SI) {
97 regValue.pMacroTileConfig = NULL;
98 regValue.noOfMacroEntries = 0;
99 } else {
100 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
101 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
102 }
103
104 createFlags.useTileIndex = 1;
105 createFlags.useHtileSliceAlign = 1;
106
107 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
108 }
109
110 addrCreateInput.callbacks.allocSysMem = allocSysMem;
111 addrCreateInput.callbacks.freeSysMem = freeSysMem;
112 addrCreateInput.callbacks.debugPrint = 0;
113 addrCreateInput.createFlags = createFlags;
114 addrCreateInput.regValue = regValue;
115
116 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
117 if (addrRet != ADDR_OK)
118 return NULL;
119
120 if (max_alignment) {
121 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
122 if (addrRet == ADDR_OK){
123 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
124 }
125 }
126 return addrCreateOutput.hLib;
127 }
128
129 static int surf_config_sanity(const struct ac_surf_config *config,
130 unsigned flags)
131 {
132 /* FMASK is allocated together with the color surface and can't be
133 * allocated separately.
134 */
135 assert(!(flags & RADEON_SURF_FMASK));
136 if (flags & RADEON_SURF_FMASK)
137 return -EINVAL;
138
139 /* all dimension must be at least 1 ! */
140 if (!config->info.width || !config->info.height || !config->info.depth ||
141 !config->info.array_size || !config->info.levels)
142 return -EINVAL;
143
144 switch (config->info.samples) {
145 case 0:
146 case 1:
147 case 2:
148 case 4:
149 case 8:
150 break;
151 case 16:
152 if (flags & RADEON_SURF_Z_OR_SBUFFER)
153 return -EINVAL;
154 break;
155 default:
156 return -EINVAL;
157 }
158
159 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
160 switch (config->info.storage_samples) {
161 case 0:
162 case 1:
163 case 2:
164 case 4:
165 case 8:
166 break;
167 default:
168 return -EINVAL;
169 }
170 }
171
172 if (config->is_3d && config->info.array_size > 1)
173 return -EINVAL;
174 if (config->is_cube && config->info.depth > 1)
175 return -EINVAL;
176
177 return 0;
178 }
179
180 static int gfx6_compute_level(ADDR_HANDLE addrlib,
181 const struct ac_surf_config *config,
182 struct radeon_surf *surf, bool is_stencil,
183 unsigned level, bool compressed,
184 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
185 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
186 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
187 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
188 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
189 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
190 {
191 struct legacy_surf_level *surf_level;
192 ADDR_E_RETURNCODE ret;
193
194 AddrSurfInfoIn->mipLevel = level;
195 AddrSurfInfoIn->width = u_minify(config->info.width, level);
196 AddrSurfInfoIn->height = u_minify(config->info.height, level);
197
198 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
199 * because GFX9 needs linear alignment of 256 bytes.
200 */
201 if (config->info.levels == 1 &&
202 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
203 AddrSurfInfoIn->bpp &&
204 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
205 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
206
207 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
208 }
209
210 /* addrlib assumes the bytes/pixel is a divisor of 64, which is not
211 * true for r32g32b32 formats. */
212 if (AddrSurfInfoIn->bpp == 96) {
213 assert(config->info.levels == 1);
214 assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED);
215
216 /* The least common multiple of 64 bytes and 12 bytes/pixel is
217 * 192 bytes, or 16 pixels. */
218 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 16);
219 }
220
221 if (config->is_3d)
222 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
223 else if (config->is_cube)
224 AddrSurfInfoIn->numSlices = 6;
225 else
226 AddrSurfInfoIn->numSlices = config->info.array_size;
227
228 if (level > 0) {
229 /* Set the base level pitch. This is needed for calculation
230 * of non-zero levels. */
231 if (is_stencil)
232 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
233 else
234 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
235
236 /* Convert blocks to pixels for compressed formats. */
237 if (compressed)
238 AddrSurfInfoIn->basePitch *= surf->blk_w;
239 }
240
241 ret = AddrComputeSurfaceInfo(addrlib,
242 AddrSurfInfoIn,
243 AddrSurfInfoOut);
244 if (ret != ADDR_OK) {
245 return ret;
246 }
247
248 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
249 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
250 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
251 surf_level->nblk_x = AddrSurfInfoOut->pitch;
252 surf_level->nblk_y = AddrSurfInfoOut->height;
253
254 switch (AddrSurfInfoOut->tileMode) {
255 case ADDR_TM_LINEAR_ALIGNED:
256 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
257 break;
258 case ADDR_TM_1D_TILED_THIN1:
259 surf_level->mode = RADEON_SURF_MODE_1D;
260 break;
261 case ADDR_TM_2D_TILED_THIN1:
262 surf_level->mode = RADEON_SURF_MODE_2D;
263 break;
264 default:
265 assert(0);
266 }
267
268 if (is_stencil)
269 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
270 else
271 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
272
273 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
274
275 /* Clear DCC fields at the beginning. */
276 surf_level->dcc_offset = 0;
277
278 /* The previous level's flag tells us if we can use DCC for this level. */
279 if (AddrSurfInfoIn->flags.dccCompatible &&
280 (level == 0 || AddrDccOut->subLvlCompressible)) {
281 bool prev_level_clearable = level == 0 ||
282 AddrDccOut->dccRamSizeAligned;
283
284 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
285 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
286 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
287 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
288 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
289
290 ret = AddrComputeDccInfo(addrlib,
291 AddrDccIn,
292 AddrDccOut);
293
294 if (ret == ADDR_OK) {
295 surf_level->dcc_offset = surf->dcc_size;
296 surf->num_dcc_levels = level + 1;
297 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
298 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
299
300 /* If the DCC size of a subresource (1 mip level or 1 slice)
301 * is not aligned, the DCC memory layout is not contiguous for
302 * that subresource, which means we can't use fast clear.
303 *
304 * We only do fast clears for whole mipmap levels. If we did
305 * per-slice fast clears, the same restriction would apply.
306 * (i.e. only compute the slice size and see if it's aligned)
307 *
308 * The last level can be non-contiguous and still be clearable
309 * if it's interleaved with the next level that doesn't exist.
310 */
311 if (AddrDccOut->dccRamSizeAligned ||
312 (prev_level_clearable && level == config->info.levels - 1))
313 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
314 else
315 surf_level->dcc_fast_clear_size = 0;
316
317 /* Compute the DCC slice size because addrlib doesn't
318 * provide this info. As DCC memory is linear (each
319 * slice is the same size) it's easy to compute.
320 */
321 surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
322
323 /* For arrays, we have to compute the DCC info again
324 * with one slice size to get a correct fast clear
325 * size.
326 */
327 if (config->info.array_size > 1) {
328 AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize;
329 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
330 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
331 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
332 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
333
334 ret = AddrComputeDccInfo(addrlib,
335 AddrDccIn, AddrDccOut);
336 if (ret == ADDR_OK) {
337 /* If the DCC memory isn't properly
338 * aligned, the data are interleaved
339 * accross slices.
340 */
341 if (AddrDccOut->dccRamSizeAligned)
342 surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize;
343 else
344 surf_level->dcc_slice_fast_clear_size = 0;
345 }
346 } else {
347 surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
348 }
349 }
350 }
351
352 /* HTILE. */
353 if (!is_stencil &&
354 AddrSurfInfoIn->flags.depth &&
355 surf_level->mode == RADEON_SURF_MODE_2D &&
356 level == 0 &&
357 !(surf->flags & RADEON_SURF_NO_HTILE)) {
358 AddrHtileIn->flags.tcCompatible = AddrSurfInfoOut->tcCompatible;
359 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
360 AddrHtileIn->height = AddrSurfInfoOut->height;
361 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
362 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
363 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
364 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
365 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
366 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
367
368 ret = AddrComputeHtileInfo(addrlib,
369 AddrHtileIn,
370 AddrHtileOut);
371
372 if (ret == ADDR_OK) {
373 surf->htile_size = AddrHtileOut->htileBytes;
374 surf->htile_slice_size = AddrHtileOut->sliceSize;
375 surf->htile_alignment = AddrHtileOut->baseAlign;
376 }
377 }
378
379 return 0;
380 }
381
382 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
383 const struct radeon_info *info)
384 {
385 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
386
387 if (info->chip_class >= GFX7)
388 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
389 else
390 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
391 }
392
393 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
394 {
395 unsigned index, tileb;
396
397 tileb = 8 * 8 * surf->bpe;
398 tileb = MIN2(surf->u.legacy.tile_split, tileb);
399
400 for (index = 0; tileb > 64; index++)
401 tileb >>= 1;
402
403 assert(index < 16);
404 return index;
405 }
406
407 static bool get_display_flag(const struct ac_surf_config *config,
408 const struct radeon_surf *surf)
409 {
410 unsigned num_channels = config->info.num_channels;
411 unsigned bpe = surf->bpe;
412
413 if (!config->is_3d &&
414 !config->is_cube &&
415 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
416 surf->flags & RADEON_SURF_SCANOUT &&
417 config->info.samples <= 1 &&
418 surf->blk_w <= 2 && surf->blk_h == 1) {
419 /* subsampled */
420 if (surf->blk_w == 2 && surf->blk_h == 1)
421 return true;
422
423 if (/* RGBA8 or RGBA16F */
424 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
425 /* R5G6B5 or R5G5B5A1 */
426 (bpe == 2 && num_channels >= 3) ||
427 /* C8 palette */
428 (bpe == 1 && num_channels == 1))
429 return true;
430 }
431 return false;
432 }
433
434 /**
435 * This must be called after the first level is computed.
436 *
437 * Copy surface-global settings like pipe/bank config from level 0 surface
438 * computation, and compute tile swizzle.
439 */
440 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
441 const struct radeon_info *info,
442 const struct ac_surf_config *config,
443 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
444 struct radeon_surf *surf)
445 {
446 surf->surf_alignment = csio->baseAlign;
447 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
448 gfx6_set_micro_tile_mode(surf, info);
449
450 /* For 2D modes only. */
451 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
452 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
453 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
454 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
455 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
456 surf->u.legacy.num_banks = csio->pTileInfo->banks;
457 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
458 } else {
459 surf->u.legacy.macro_tile_index = 0;
460 }
461
462 /* Compute tile swizzle. */
463 /* TODO: fix tile swizzle with mipmapping for GFX6 */
464 if ((info->chip_class >= GFX7 || config->info.levels == 1) &&
465 config->info.surf_index &&
466 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
467 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
468 !get_display_flag(config, surf)) {
469 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
470 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
471
472 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
473 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
474
475 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
476 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
477 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
478 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
479 AddrBaseSwizzleIn.tileMode = csio->tileMode;
480
481 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
482 &AddrBaseSwizzleOut);
483 if (r != ADDR_OK)
484 return r;
485
486 assert(AddrBaseSwizzleOut.tileSwizzle <=
487 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
488 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
489 }
490 return 0;
491 }
492
493 static void ac_compute_cmask(const struct radeon_info *info,
494 const struct ac_surf_config *config,
495 struct radeon_surf *surf)
496 {
497 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
498 unsigned num_pipes = info->num_tile_pipes;
499 unsigned cl_width, cl_height;
500
501 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER ||
502 (config->info.samples >= 2 && !surf->fmask_size))
503 return;
504
505 assert(info->chip_class <= GFX8);
506
507 switch (num_pipes) {
508 case 2:
509 cl_width = 32;
510 cl_height = 16;
511 break;
512 case 4:
513 cl_width = 32;
514 cl_height = 32;
515 break;
516 case 8:
517 cl_width = 64;
518 cl_height = 32;
519 break;
520 case 16: /* Hawaii */
521 cl_width = 64;
522 cl_height = 64;
523 break;
524 default:
525 assert(0);
526 return;
527 }
528
529 unsigned base_align = num_pipes * pipe_interleave_bytes;
530
531 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
532 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
533 unsigned slice_elements = (width * height) / (8*8);
534
535 /* Each element of CMASK is a nibble. */
536 unsigned slice_bytes = slice_elements / 2;
537
538 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
539 if (surf->u.legacy.cmask_slice_tile_max)
540 surf->u.legacy.cmask_slice_tile_max -= 1;
541
542 unsigned num_layers;
543 if (config->is_3d)
544 num_layers = config->info.depth;
545 else if (config->is_cube)
546 num_layers = 6;
547 else
548 num_layers = config->info.array_size;
549
550 surf->cmask_alignment = MAX2(256, base_align);
551 surf->cmask_slice_size = align(slice_bytes, base_align);
552 surf->cmask_size = surf->cmask_slice_size * num_layers;
553 }
554
555 /**
556 * Fill in the tiling information in \p surf based on the given surface config.
557 *
558 * The following fields of \p surf must be initialized by the caller:
559 * blk_w, blk_h, bpe, flags.
560 */
561 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
562 const struct radeon_info *info,
563 const struct ac_surf_config *config,
564 enum radeon_surf_mode mode,
565 struct radeon_surf *surf)
566 {
567 unsigned level;
568 bool compressed;
569 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
570 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
571 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
572 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
573 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
574 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
575 ADDR_TILEINFO AddrTileInfoIn = {0};
576 ADDR_TILEINFO AddrTileInfoOut = {0};
577 int r;
578
579 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
580 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
581 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
582 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
583 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
584 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
585 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
586
587 compressed = surf->blk_w == 4 && surf->blk_h == 4;
588
589 /* MSAA requires 2D tiling. */
590 if (config->info.samples > 1)
591 mode = RADEON_SURF_MODE_2D;
592
593 /* DB doesn't support linear layouts. */
594 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
595 mode < RADEON_SURF_MODE_1D)
596 mode = RADEON_SURF_MODE_1D;
597
598 /* Set the requested tiling mode. */
599 switch (mode) {
600 case RADEON_SURF_MODE_LINEAR_ALIGNED:
601 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
602 break;
603 case RADEON_SURF_MODE_1D:
604 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
605 break;
606 case RADEON_SURF_MODE_2D:
607 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
608 break;
609 default:
610 assert(0);
611 }
612
613 /* The format must be set correctly for the allocation of compressed
614 * textures to work. In other cases, setting the bpp is sufficient.
615 */
616 if (compressed) {
617 switch (surf->bpe) {
618 case 8:
619 AddrSurfInfoIn.format = ADDR_FMT_BC1;
620 break;
621 case 16:
622 AddrSurfInfoIn.format = ADDR_FMT_BC3;
623 break;
624 default:
625 assert(0);
626 }
627 }
628 else {
629 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
630 }
631
632 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
633 MAX2(1, config->info.samples);
634 AddrSurfInfoIn.tileIndex = -1;
635
636 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
637 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
638 MAX2(1, config->info.storage_samples);
639 }
640
641 /* Set the micro tile type. */
642 if (surf->flags & RADEON_SURF_SCANOUT)
643 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
644 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
645 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
646 else
647 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
648
649 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
650 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
651 AddrSurfInfoIn.flags.cube = config->is_cube;
652 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
653 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
654 AddrSurfInfoIn.flags.tcCompatible = info->chip_class >= GFX8 &&
655 AddrSurfInfoIn.flags.depth;
656
657 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
658 * requested, because TC-compatible HTILE requires 2D tiling.
659 */
660 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
661 !AddrSurfInfoIn.flags.fmask &&
662 config->info.samples <= 1 &&
663 !(surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE);
664
665 /* DCC notes:
666 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
667 * with samples >= 4.
668 * - Mipmapped array textures have low performance (discovered by a closed
669 * driver team).
670 */
671 AddrSurfInfoIn.flags.dccCompatible =
672 info->chip_class >= GFX8 &&
673 info->has_graphics && /* disable DCC on compute-only chips */
674 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
675 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
676 !compressed &&
677 ((config->info.array_size == 1 && config->info.depth == 1) ||
678 config->info.levels == 1);
679
680 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
681 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
682
683 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
684 * for Z and stencil. This can cause a number of problems which we work
685 * around here:
686 *
687 * - a depth part that is incompatible with mipmapped texturing
688 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
689 * incorrect tiling applied to the stencil part, stencil buffer
690 * memory accesses that go out of bounds) even without mipmapping
691 *
692 * Some piglit tests that are prone to different types of related
693 * failures:
694 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
695 * ./bin/framebuffer-blit-levels {draw,read} stencil
696 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
697 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
698 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
699 */
700 int stencil_tile_idx = -1;
701
702 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
703 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
704 /* Compute stencilTileIdx that is compatible with the (depth)
705 * tileIdx. This degrades the depth surface if necessary to
706 * ensure that a matching stencilTileIdx exists. */
707 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
708
709 /* Keep the depth mip-tail compatible with texturing. */
710 AddrSurfInfoIn.flags.noStencil = 1;
711 }
712
713 /* Set preferred macrotile parameters. This is usually required
714 * for shared resources. This is for 2D tiling only. */
715 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
716 surf->u.legacy.bankw && surf->u.legacy.bankh &&
717 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
718 /* If any of these parameters are incorrect, the calculation
719 * will fail. */
720 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
721 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
722 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
723 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
724 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
725 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
726 AddrSurfInfoIn.flags.opt4Space = 0;
727 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
728
729 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
730 * the tile index, because we are expected to know it if
731 * we know the other parameters.
732 *
733 * This is something that can easily be fixed in Addrlib.
734 * For now, just figure it out here.
735 * Note that only 2D_TILE_THIN1 is handled here.
736 */
737 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
738 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
739
740 if (info->chip_class == GFX6) {
741 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
742 if (surf->bpe == 2)
743 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
744 else
745 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
746 } else {
747 if (surf->bpe == 1)
748 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
749 else if (surf->bpe == 2)
750 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
751 else if (surf->bpe == 4)
752 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
753 else
754 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
755 }
756 } else {
757 /* GFX7 - GFX8 */
758 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
759 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
760 else
761 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
762
763 /* Addrlib doesn't set this if tileIndex is forced like above. */
764 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
765 }
766 }
767
768 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
769 surf->num_dcc_levels = 0;
770 surf->surf_size = 0;
771 surf->dcc_size = 0;
772 surf->dcc_alignment = 1;
773 surf->htile_size = 0;
774 surf->htile_slice_size = 0;
775 surf->htile_alignment = 1;
776 surf->tc_compatible_htile_allowed = AddrSurfInfoIn.flags.tcCompatible;
777
778 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
779 !(surf->flags & RADEON_SURF_ZBUFFER);
780
781 /* Calculate texture layout information. */
782 if (!only_stencil) {
783 for (level = 0; level < config->info.levels; level++) {
784 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
785 &AddrSurfInfoIn, &AddrSurfInfoOut,
786 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
787 if (r)
788 return r;
789
790 if (level > 0)
791 continue;
792
793 if (!AddrSurfInfoOut.tcCompatible)
794 AddrSurfInfoIn.flags.tcCompatible = 0;
795
796 if (!AddrSurfInfoOut.tcCompatible || !surf->htile_size)
797 surf->tc_compatible_htile_allowed = false;
798
799 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
800 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
801 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
802 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
803
804 assert(stencil_tile_idx >= 0);
805 }
806
807 r = gfx6_surface_settings(addrlib, info, config,
808 &AddrSurfInfoOut, surf);
809 if (r)
810 return r;
811 }
812 }
813
814 /* Calculate texture layout information for stencil. */
815 if (surf->flags & RADEON_SURF_SBUFFER) {
816 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
817 AddrSurfInfoIn.bpp = 8;
818 AddrSurfInfoIn.flags.depth = 0;
819 AddrSurfInfoIn.flags.stencil = 1;
820 AddrSurfInfoIn.flags.tcCompatible = 0;
821 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
822 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
823
824 for (level = 0; level < config->info.levels; level++) {
825 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
826 &AddrSurfInfoIn, &AddrSurfInfoOut,
827 &AddrDccIn, &AddrDccOut,
828 NULL, NULL);
829 if (r)
830 return r;
831
832 /* DB uses the depth pitch for both stencil and depth. */
833 if (!only_stencil) {
834 if (surf->u.legacy.stencil_level[level].nblk_x !=
835 surf->u.legacy.level[level].nblk_x)
836 surf->u.legacy.stencil_adjusted = true;
837 } else {
838 surf->u.legacy.level[level].nblk_x =
839 surf->u.legacy.stencil_level[level].nblk_x;
840 }
841
842 if (level == 0) {
843 if (only_stencil) {
844 r = gfx6_surface_settings(addrlib, info, config,
845 &AddrSurfInfoOut, surf);
846 if (r)
847 return r;
848 }
849
850 /* For 2D modes only. */
851 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
852 surf->u.legacy.stencil_tile_split =
853 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
854 }
855 }
856 }
857 }
858
859 /* Compute FMASK. */
860 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color &&
861 info->has_graphics && !(surf->flags & RADEON_SURF_NO_FMASK)) {
862 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
863 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
864 ADDR_TILEINFO fmask_tile_info = {};
865
866 fin.size = sizeof(fin);
867 fout.size = sizeof(fout);
868
869 fin.tileMode = AddrSurfInfoOut.tileMode;
870 fin.pitch = AddrSurfInfoOut.pitch;
871 fin.height = config->info.height;
872 fin.numSlices = AddrSurfInfoIn.numSlices;
873 fin.numSamples = AddrSurfInfoIn.numSamples;
874 fin.numFrags = AddrSurfInfoIn.numFrags;
875 fin.tileIndex = -1;
876 fout.pTileInfo = &fmask_tile_info;
877
878 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
879 if (r)
880 return r;
881
882 surf->fmask_size = fout.fmaskBytes;
883 surf->fmask_alignment = fout.baseAlign;
884 surf->fmask_tile_swizzle = 0;
885
886 surf->u.legacy.fmask.slice_tile_max =
887 (fout.pitch * fout.height) / 64;
888 if (surf->u.legacy.fmask.slice_tile_max)
889 surf->u.legacy.fmask.slice_tile_max -= 1;
890
891 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
892 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
893 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
894 surf->u.legacy.fmask.slice_size = fout.sliceSize;
895
896 /* Compute tile swizzle for FMASK. */
897 if (config->info.fmask_surf_index &&
898 !(surf->flags & RADEON_SURF_SHAREABLE)) {
899 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
900 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
901
902 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
903 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
904
905 /* This counter starts from 1 instead of 0. */
906 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
907 xin.tileIndex = fout.tileIndex;
908 xin.macroModeIndex = fout.macroModeIndex;
909 xin.pTileInfo = fout.pTileInfo;
910 xin.tileMode = fin.tileMode;
911
912 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
913 if (r != ADDR_OK)
914 return r;
915
916 assert(xout.tileSwizzle <=
917 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
918 surf->fmask_tile_swizzle = xout.tileSwizzle;
919 }
920 }
921
922 /* Recalculate the whole DCC miptree size including disabled levels.
923 * This is what addrlib does, but calling addrlib would be a lot more
924 * complicated.
925 */
926 if (surf->dcc_size && config->info.levels > 1) {
927 /* The smallest miplevels that are never compressed by DCC
928 * still read the DCC buffer via TC if the base level uses DCC,
929 * and for some reason the DCC buffer needs to be larger if
930 * the miptree uses non-zero tile_swizzle. Otherwise there are
931 * VM faults.
932 *
933 * "dcc_alignment * 4" was determined by trial and error.
934 */
935 surf->dcc_size = align64(surf->surf_size >> 8,
936 surf->dcc_alignment * 4);
937 }
938
939 /* Make sure HTILE covers the whole miptree, because the shader reads
940 * TC-compatible HTILE even for levels where it's disabled by DB.
941 */
942 if (surf->htile_size && config->info.levels > 1 &&
943 surf->tc_compatible_htile_allowed) {
944 /* MSAA can't occur with levels > 1, so ignore the sample count. */
945 const unsigned total_pixels = surf->surf_size / surf->bpe;
946 const unsigned htile_block_size = 8 * 8;
947 const unsigned htile_element_size = 4;
948
949 surf->htile_size = (total_pixels / htile_block_size) *
950 htile_element_size;
951 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
952 }
953
954 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
955 surf->is_displayable = surf->is_linear ||
956 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
957 surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER;
958
959 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
960 * used at the same time. This case is not currently expected to occur
961 * because we don't use rotated. Enforce this restriction on all chips
962 * to facilitate testing.
963 */
964 if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER) {
965 assert(!"rotate micro tile mode is unsupported");
966 return ADDR_ERROR;
967 }
968
969 ac_compute_cmask(info, config, surf);
970 return 0;
971 }
972
973 /* This is only called when expecting a tiled layout. */
974 static int
975 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
976 struct radeon_surf *surf,
977 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
978 bool is_fmask, AddrSwizzleMode *swizzle_mode)
979 {
980 ADDR_E_RETURNCODE ret;
981 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
982 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
983
984 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
985 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
986
987 sin.flags = in->flags;
988 sin.resourceType = in->resourceType;
989 sin.format = in->format;
990 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
991 /* TODO: We could allow some of these: */
992 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
993 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
994 sin.bpp = in->bpp;
995 sin.width = in->width;
996 sin.height = in->height;
997 sin.numSlices = in->numSlices;
998 sin.numMipLevels = in->numMipLevels;
999 sin.numSamples = in->numSamples;
1000 sin.numFrags = in->numFrags;
1001
1002 if (is_fmask) {
1003 sin.flags.display = 0;
1004 sin.flags.color = 0;
1005 sin.flags.fmask = 1;
1006 }
1007
1008 if (surf->flags & RADEON_SURF_FORCE_MICRO_TILE_MODE) {
1009 sin.forbiddenBlock.linear = 1;
1010
1011 if (surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1012 sin.preferredSwSet.sw_D = 1;
1013 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_STANDARD)
1014 sin.preferredSwSet.sw_S = 1;
1015 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_DEPTH)
1016 sin.preferredSwSet.sw_Z = 1;
1017 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER)
1018 sin.preferredSwSet.sw_R = 1;
1019 }
1020
1021 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
1022 if (ret != ADDR_OK)
1023 return ret;
1024
1025 *swizzle_mode = sout.swizzleMode;
1026 return 0;
1027 }
1028
1029 static bool is_dcc_supported_by_CB(const struct radeon_info *info, unsigned sw_mode)
1030 {
1031 if (info->chip_class >= GFX10)
1032 return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X;
1033
1034 return sw_mode != ADDR_SW_LINEAR;
1035 }
1036
1037 static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
1038 const struct ac_surf_config *config,
1039 const struct radeon_surf *surf,
1040 bool rb_aligned, bool pipe_aligned)
1041 {
1042 if (!info->use_display_dcc_unaligned &&
1043 !info->use_display_dcc_with_retile_blit)
1044 return false;
1045
1046 /* 16bpp and 64bpp are more complicated, so they are disallowed for now. */
1047 if (surf->bpe != 4)
1048 return false;
1049
1050 /* Handle unaligned DCC. */
1051 if (info->use_display_dcc_unaligned &&
1052 (rb_aligned || pipe_aligned))
1053 return false;
1054
1055 switch (info->chip_class) {
1056 case GFX9:
1057 /* There are more constraints, but we always set
1058 * INDEPENDENT_64B_BLOCKS = 1 and MAX_COMPRESSED_BLOCK_SIZE = 64B,
1059 * which always works.
1060 */
1061 assert(surf->u.gfx9.dcc.independent_64B_blocks &&
1062 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
1063 return true;
1064 case GFX10:
1065 /* DCN requires INDEPENDENT_128B_BLOCKS = 0.
1066 * For 4K, it also requires INDEPENDENT_64B_BLOCKS = 1.
1067 */
1068 return !surf->u.gfx9.dcc.independent_128B_blocks &&
1069 ((config->info.width <= 2560 &&
1070 config->info.height <= 2560) ||
1071 (surf->u.gfx9.dcc.independent_64B_blocks &&
1072 surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B));
1073 default:
1074 unreachable("unhandled chip");
1075 return false;
1076 }
1077 }
1078
1079 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
1080 const struct radeon_info *info,
1081 const struct ac_surf_config *config,
1082 struct radeon_surf *surf, bool compressed,
1083 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
1084 {
1085 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
1086 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
1087 ADDR_E_RETURNCODE ret;
1088
1089 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
1090 out.pMipInfo = mip_info;
1091
1092 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
1093 if (ret != ADDR_OK)
1094 return ret;
1095
1096 if (in->flags.stencil) {
1097 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1098 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1099 out.mipChainPitch - 1;
1100 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1101 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1102 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1103 return 0;
1104 }
1105
1106 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1107 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1108 out.mipChainPitch - 1;
1109
1110 /* CMASK fast clear uses these even if FMASK isn't allocated.
1111 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1112 */
1113 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1114 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1115
1116 surf->u.gfx9.surf_slice_size = out.sliceSize;
1117 surf->u.gfx9.surf_pitch = out.pitch;
1118 if (!compressed && surf->blk_w > 1 && out.pitch == out.pixelPitch) {
1119 /* Adjust surf_pitch to be in elements units,
1120 * not in pixels */
1121 surf->u.gfx9.surf_pitch /= surf->blk_w;
1122 }
1123 surf->u.gfx9.surf_height = out.height;
1124 surf->surf_size = out.surfSize;
1125 surf->surf_alignment = out.baseAlign;
1126
1127 if (in->swizzleMode == ADDR_SW_LINEAR) {
1128 for (unsigned i = 0; i < in->numMipLevels; i++) {
1129 surf->u.gfx9.offset[i] = mip_info[i].offset;
1130 surf->u.gfx9.pitch[i] = mip_info[i].pitch;
1131 }
1132 }
1133
1134 if (in->flags.depth) {
1135 assert(in->swizzleMode != ADDR_SW_LINEAR);
1136
1137 if (surf->flags & RADEON_SURF_NO_HTILE)
1138 return 0;
1139
1140 /* HTILE */
1141 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1142 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1143
1144 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1145 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1146
1147 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1148 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1149 hin.depthFlags = in->flags;
1150 hin.swizzleMode = in->swizzleMode;
1151 hin.unalignedWidth = in->width;
1152 hin.unalignedHeight = in->height;
1153 hin.numSlices = in->numSlices;
1154 hin.numMipLevels = in->numMipLevels;
1155 hin.firstMipIdInTail = out.firstMipIdInTail;
1156
1157 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1158 if (ret != ADDR_OK)
1159 return ret;
1160
1161 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1162 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1163 surf->htile_size = hout.htileBytes;
1164 surf->htile_slice_size = hout.sliceSize;
1165 surf->htile_alignment = hout.baseAlign;
1166 return 0;
1167 }
1168
1169 {
1170 /* Compute tile swizzle for the color surface.
1171 * All *_X and *_T modes can use the swizzle.
1172 */
1173 if (config->info.surf_index &&
1174 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1175 !out.mipChainInTail &&
1176 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1177 !in->flags.display) {
1178 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1179 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1180
1181 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1182 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1183
1184 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1185 xin.flags = in->flags;
1186 xin.swizzleMode = in->swizzleMode;
1187 xin.resourceType = in->resourceType;
1188 xin.format = in->format;
1189 xin.numSamples = in->numSamples;
1190 xin.numFrags = in->numFrags;
1191
1192 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1193 if (ret != ADDR_OK)
1194 return ret;
1195
1196 assert(xout.pipeBankXor <=
1197 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1198 surf->tile_swizzle = xout.pipeBankXor;
1199 }
1200
1201 /* DCC */
1202 if (info->has_graphics &&
1203 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1204 !compressed &&
1205 is_dcc_supported_by_CB(info, in->swizzleMode) &&
1206 (!in->flags.display ||
1207 is_dcc_supported_by_DCN(info, config, surf,
1208 !in->flags.metaRbUnaligned,
1209 !in->flags.metaPipeUnaligned))) {
1210 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1211 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1212 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1213
1214 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1215 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1216 dout.pMipInfo = meta_mip_info;
1217
1218 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1219 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1220 din.colorFlags = in->flags;
1221 din.resourceType = in->resourceType;
1222 din.swizzleMode = in->swizzleMode;
1223 din.bpp = in->bpp;
1224 din.unalignedWidth = in->width;
1225 din.unalignedHeight = in->height;
1226 din.numSlices = in->numSlices;
1227 din.numFrags = in->numFrags;
1228 din.numMipLevels = in->numMipLevels;
1229 din.dataSurfaceSize = out.surfSize;
1230 din.firstMipIdInTail = out.firstMipIdInTail;
1231
1232 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1233 if (ret != ADDR_OK)
1234 return ret;
1235
1236 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1237 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1238 surf->dcc_size = dout.dccRamSize;
1239 surf->dcc_alignment = dout.dccRamBaseAlign;
1240 surf->num_dcc_levels = in->numMipLevels;
1241
1242 /* Disable DCC for levels that are in the mip tail.
1243 *
1244 * There are two issues that this is intended to
1245 * address:
1246 *
1247 * 1. Multiple mip levels may share a cache line. This
1248 * can lead to corruption when switching between
1249 * rendering to different mip levels because the
1250 * RBs don't maintain coherency.
1251 *
1252 * 2. Texturing with metadata after rendering sometimes
1253 * fails with corruption, probably for a similar
1254 * reason.
1255 *
1256 * Working around these issues for all levels in the
1257 * mip tail may be overly conservative, but it's what
1258 * Vulkan does.
1259 *
1260 * Alternative solutions that also work but are worse:
1261 * - Disable DCC entirely.
1262 * - Flush TC L2 after rendering.
1263 */
1264 for (unsigned i = 0; i < in->numMipLevels; i++) {
1265 if (meta_mip_info[i].inMiptail) {
1266 surf->num_dcc_levels = i;
1267 break;
1268 }
1269 }
1270
1271 if (!surf->num_dcc_levels)
1272 surf->dcc_size = 0;
1273
1274 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1275 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1276 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1277
1278 /* Compute displayable DCC. */
1279 if (in->flags.display &&
1280 surf->num_dcc_levels &&
1281 info->use_display_dcc_with_retile_blit) {
1282 /* Compute displayable DCC info. */
1283 din.dccKeyFlags.pipeAligned = 0;
1284 din.dccKeyFlags.rbAligned = 0;
1285
1286 assert(din.numSlices == 1);
1287 assert(din.numMipLevels == 1);
1288 assert(din.numFrags == 1);
1289 assert(surf->tile_swizzle == 0);
1290 assert(surf->u.gfx9.dcc.pipe_aligned ||
1291 surf->u.gfx9.dcc.rb_aligned);
1292
1293 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1294 if (ret != ADDR_OK)
1295 return ret;
1296
1297 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1298 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1299 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1300 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1301
1302 /* Compute address mapping from non-displayable to displayable DCC. */
1303 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
1304 addrin.size = sizeof(addrin);
1305 addrin.colorFlags.color = 1;
1306 addrin.swizzleMode = din.swizzleMode;
1307 addrin.resourceType = din.resourceType;
1308 addrin.bpp = din.bpp;
1309 addrin.unalignedWidth = din.unalignedWidth;
1310 addrin.unalignedHeight = din.unalignedHeight;
1311 addrin.numSlices = 1;
1312 addrin.numMipLevels = 1;
1313 addrin.numFrags = 1;
1314
1315 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
1316 addrout.size = sizeof(addrout);
1317
1318 surf->u.gfx9.dcc_retile_num_elements =
1319 DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
1320 DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
1321 /* Align the size to 4 (for the compute shader). */
1322 surf->u.gfx9.dcc_retile_num_elements =
1323 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1324
1325 surf->u.gfx9.dcc_retile_map =
1326 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1327 if (!surf->u.gfx9.dcc_retile_map)
1328 return ADDR_OUTOFMEMORY;
1329
1330 unsigned index = 0;
1331 surf->u.gfx9.dcc_retile_use_uint16 = true;
1332
1333 for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
1334 addrin.y = y;
1335
1336 for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
1337 addrin.x = x;
1338
1339 /* Compute src DCC address */
1340 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1341 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1342 addrout.addr = 0;
1343
1344 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1345 if (ret != ADDR_OK)
1346 return ret;
1347
1348 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1349 if (addrout.addr > UINT16_MAX)
1350 surf->u.gfx9.dcc_retile_use_uint16 = false;
1351
1352 /* Compute dst DCC address */
1353 addrin.dccKeyFlags.pipeAligned = 0;
1354 addrin.dccKeyFlags.rbAligned = 0;
1355 addrout.addr = 0;
1356
1357 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1358 if (ret != ADDR_OK)
1359 return ret;
1360
1361 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1362 if (addrout.addr > UINT16_MAX)
1363 surf->u.gfx9.dcc_retile_use_uint16 = false;
1364
1365 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1366 index++;
1367 }
1368 }
1369 /* Fill the remaining pairs with the last one (for the compute shader). */
1370 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1371 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1372 }
1373 }
1374
1375 /* FMASK */
1376 if (in->numSamples > 1 && info->has_graphics &&
1377 !(surf->flags & RADEON_SURF_NO_FMASK)) {
1378 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1379 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1380
1381 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1382 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1383
1384 ret = gfx9_get_preferred_swizzle_mode(addrlib, surf, in,
1385 true, &fin.swizzleMode);
1386 if (ret != ADDR_OK)
1387 return ret;
1388
1389 fin.unalignedWidth = in->width;
1390 fin.unalignedHeight = in->height;
1391 fin.numSlices = in->numSlices;
1392 fin.numSamples = in->numSamples;
1393 fin.numFrags = in->numFrags;
1394
1395 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1396 if (ret != ADDR_OK)
1397 return ret;
1398
1399 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1400 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1401 surf->fmask_size = fout.fmaskBytes;
1402 surf->fmask_alignment = fout.baseAlign;
1403
1404 /* Compute tile swizzle for the FMASK surface. */
1405 if (config->info.fmask_surf_index &&
1406 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1407 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1408 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1409 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1410
1411 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1412 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1413
1414 /* This counter starts from 1 instead of 0. */
1415 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1416 xin.flags = in->flags;
1417 xin.swizzleMode = fin.swizzleMode;
1418 xin.resourceType = in->resourceType;
1419 xin.format = in->format;
1420 xin.numSamples = in->numSamples;
1421 xin.numFrags = in->numFrags;
1422
1423 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1424 if (ret != ADDR_OK)
1425 return ret;
1426
1427 assert(xout.pipeBankXor <=
1428 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1429 surf->fmask_tile_swizzle = xout.pipeBankXor;
1430 }
1431 }
1432
1433 /* CMASK -- on GFX10 only for FMASK */
1434 if (in->swizzleMode != ADDR_SW_LINEAR &&
1435 in->resourceType == ADDR_RSRC_TEX_2D &&
1436 ((info->chip_class <= GFX9 && in->numSamples == 1) ||
1437 (surf->fmask_size && in->numSamples >= 2))) {
1438 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1439 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1440
1441 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1442 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1443
1444 if (in->numSamples > 1) {
1445 /* FMASK is always aligned. */
1446 cin.cMaskFlags.pipeAligned = 1;
1447 cin.cMaskFlags.rbAligned = 1;
1448 } else {
1449 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1450 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1451 }
1452 cin.colorFlags = in->flags;
1453 cin.resourceType = in->resourceType;
1454 cin.unalignedWidth = in->width;
1455 cin.unalignedHeight = in->height;
1456 cin.numSlices = in->numSlices;
1457
1458 if (in->numSamples > 1)
1459 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1460 else
1461 cin.swizzleMode = in->swizzleMode;
1462
1463 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1464 if (ret != ADDR_OK)
1465 return ret;
1466
1467 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1468 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1469 surf->cmask_size = cout.cmaskBytes;
1470 surf->cmask_alignment = cout.baseAlign;
1471 }
1472 }
1473
1474 return 0;
1475 }
1476
1477 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1478 const struct radeon_info *info,
1479 const struct ac_surf_config *config,
1480 enum radeon_surf_mode mode,
1481 struct radeon_surf *surf)
1482 {
1483 bool compressed;
1484 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1485 int r;
1486
1487 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1488
1489 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1490
1491 /* The format must be set correctly for the allocation of compressed
1492 * textures to work. In other cases, setting the bpp is sufficient. */
1493 if (compressed) {
1494 switch (surf->bpe) {
1495 case 8:
1496 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1497 break;
1498 case 16:
1499 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1500 break;
1501 default:
1502 assert(0);
1503 }
1504 } else {
1505 switch (surf->bpe) {
1506 case 1:
1507 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1508 AddrSurfInfoIn.format = ADDR_FMT_8;
1509 break;
1510 case 2:
1511 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1512 !(surf->flags & RADEON_SURF_SBUFFER));
1513 AddrSurfInfoIn.format = ADDR_FMT_16;
1514 break;
1515 case 4:
1516 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1517 !(surf->flags & RADEON_SURF_SBUFFER));
1518 AddrSurfInfoIn.format = ADDR_FMT_32;
1519 break;
1520 case 8:
1521 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1522 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1523 break;
1524 case 12:
1525 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1526 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1527 break;
1528 case 16:
1529 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1530 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1531 break;
1532 default:
1533 assert(0);
1534 }
1535 AddrSurfInfoIn.bpp = surf->bpe * 8;
1536 }
1537
1538 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
1539 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1540 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1541 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1542 /* flags.texture currently refers to TC-compatible HTILE */
1543 AddrSurfInfoIn.flags.texture = 1;
1544 AddrSurfInfoIn.flags.opt4space = 1;
1545
1546 AddrSurfInfoIn.numMipLevels = config->info.levels;
1547 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1548 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1549
1550 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1551 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1552
1553 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1554 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1555 * must sample 1D textures as 2D. */
1556 if (config->is_3d)
1557 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1558 else if (info->chip_class != GFX9 && config->is_1d)
1559 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
1560 else
1561 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1562
1563 AddrSurfInfoIn.width = config->info.width;
1564 AddrSurfInfoIn.height = config->info.height;
1565
1566 if (config->is_3d)
1567 AddrSurfInfoIn.numSlices = config->info.depth;
1568 else if (config->is_cube)
1569 AddrSurfInfoIn.numSlices = 6;
1570 else
1571 AddrSurfInfoIn.numSlices = config->info.array_size;
1572
1573 /* This is propagated to HTILE/DCC/CMASK. */
1574 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1575 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1576
1577 /* Optimal values for the L2 cache. */
1578 if (info->chip_class == GFX9) {
1579 surf->u.gfx9.dcc.independent_64B_blocks = 1;
1580 surf->u.gfx9.dcc.independent_128B_blocks = 0;
1581 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
1582 } else if (info->chip_class >= GFX10) {
1583 surf->u.gfx9.dcc.independent_64B_blocks = 0;
1584 surf->u.gfx9.dcc.independent_128B_blocks = 1;
1585 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
1586 }
1587
1588 if (AddrSurfInfoIn.flags.display) {
1589 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1590 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1591 *
1592 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1593 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1594 * after rendering, so PIPE_ALIGNED=1 is recommended.
1595 */
1596 if (info->use_display_dcc_unaligned) {
1597 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1598 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1599 }
1600
1601 /* Adjust DCC settings to meet DCN requirements. */
1602 if (info->use_display_dcc_unaligned ||
1603 info->use_display_dcc_with_retile_blit) {
1604 /* Only Navi12/14 support independent 64B blocks in L2,
1605 * but without DCC image stores.
1606 */
1607 if (info->family == CHIP_NAVI12 ||
1608 info->family == CHIP_NAVI14) {
1609 surf->u.gfx9.dcc.independent_64B_blocks = 1;
1610 surf->u.gfx9.dcc.independent_128B_blocks = 0;
1611 surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
1612 }
1613 }
1614 }
1615
1616 switch (mode) {
1617 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1618 assert(config->info.samples <= 1);
1619 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1620 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1621 break;
1622
1623 case RADEON_SURF_MODE_1D:
1624 case RADEON_SURF_MODE_2D:
1625 if (surf->flags & (RADEON_SURF_IMPORTED | RADEON_SURF_FORCE_SWIZZLE_MODE)) {
1626 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1627 break;
1628 }
1629
1630 r = gfx9_get_preferred_swizzle_mode(addrlib, surf, &AddrSurfInfoIn,
1631 false, &AddrSurfInfoIn.swizzleMode);
1632 if (r)
1633 return r;
1634 break;
1635
1636 default:
1637 assert(0);
1638 }
1639
1640 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1641 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1642
1643 surf->num_dcc_levels = 0;
1644 surf->surf_size = 0;
1645 surf->fmask_size = 0;
1646 surf->dcc_size = 0;
1647 surf->htile_size = 0;
1648 surf->htile_slice_size = 0;
1649 surf->u.gfx9.surf_offset = 0;
1650 surf->u.gfx9.stencil_offset = 0;
1651 surf->cmask_size = 0;
1652 surf->u.gfx9.dcc_retile_use_uint16 = false;
1653 surf->u.gfx9.dcc_retile_num_elements = 0;
1654 surf->u.gfx9.dcc_retile_map = NULL;
1655
1656 /* Calculate texture layout information. */
1657 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1658 &AddrSurfInfoIn);
1659 if (r)
1660 goto error;
1661
1662 /* Calculate texture layout information for stencil. */
1663 if (surf->flags & RADEON_SURF_SBUFFER) {
1664 AddrSurfInfoIn.flags.stencil = 1;
1665 AddrSurfInfoIn.bpp = 8;
1666 AddrSurfInfoIn.format = ADDR_FMT_8;
1667
1668 if (!AddrSurfInfoIn.flags.depth) {
1669 r = gfx9_get_preferred_swizzle_mode(addrlib, surf, &AddrSurfInfoIn,
1670 false, &AddrSurfInfoIn.swizzleMode);
1671 if (r)
1672 goto error;
1673 } else
1674 AddrSurfInfoIn.flags.depth = 0;
1675
1676 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1677 &AddrSurfInfoIn);
1678 if (r)
1679 goto error;
1680 }
1681
1682 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1683 surf->tc_compatible_htile_allowed = surf->htile_size != 0;
1684
1685 /* Query whether the surface is displayable. */
1686 /* This is only useful for surfaces that are allocated without SCANOUT. */
1687 bool displayable = false;
1688 if (!config->is_3d && !config->is_cube) {
1689 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1690 surf->bpe * 8, &displayable);
1691 if (r)
1692 goto error;
1693
1694 /* Display needs unaligned DCC. */
1695 if (surf->num_dcc_levels &&
1696 !is_dcc_supported_by_DCN(info, config, surf,
1697 surf->u.gfx9.dcc.rb_aligned,
1698 surf->u.gfx9.dcc.pipe_aligned))
1699 displayable = false;
1700 }
1701 surf->is_displayable = displayable;
1702
1703 /* Validate that we allocated a displayable surface if requested. */
1704 assert(!AddrSurfInfoIn.flags.display || surf->is_displayable);
1705
1706 switch (surf->u.gfx9.surf.swizzle_mode) {
1707 /* S = standard. */
1708 case ADDR_SW_256B_S:
1709 case ADDR_SW_4KB_S:
1710 case ADDR_SW_64KB_S:
1711 case ADDR_SW_64KB_S_T:
1712 case ADDR_SW_4KB_S_X:
1713 case ADDR_SW_64KB_S_X:
1714 surf->micro_tile_mode = RADEON_MICRO_MODE_STANDARD;
1715 break;
1716
1717 /* D = display. */
1718 case ADDR_SW_LINEAR:
1719 case ADDR_SW_256B_D:
1720 case ADDR_SW_4KB_D:
1721 case ADDR_SW_64KB_D:
1722 case ADDR_SW_64KB_D_T:
1723 case ADDR_SW_4KB_D_X:
1724 case ADDR_SW_64KB_D_X:
1725 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1726 break;
1727
1728 /* R = rotated (gfx9), render target (gfx10). */
1729 case ADDR_SW_256B_R:
1730 case ADDR_SW_4KB_R:
1731 case ADDR_SW_64KB_R:
1732 case ADDR_SW_64KB_R_T:
1733 case ADDR_SW_4KB_R_X:
1734 case ADDR_SW_64KB_R_X:
1735 case ADDR_SW_VAR_R_X:
1736 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1737 * used at the same time. We currently do not use rotated
1738 * in gfx9.
1739 */
1740 assert(info->chip_class >= GFX10 ||
1741 !"rotate micro tile mode is unsupported");
1742 surf->micro_tile_mode = RADEON_MICRO_MODE_RENDER;
1743 break;
1744
1745 /* Z = depth. */
1746 case ADDR_SW_4KB_Z:
1747 case ADDR_SW_64KB_Z:
1748 case ADDR_SW_64KB_Z_T:
1749 case ADDR_SW_4KB_Z_X:
1750 case ADDR_SW_64KB_Z_X:
1751 case ADDR_SW_VAR_Z_X:
1752 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1753 break;
1754
1755 default:
1756 assert(0);
1757 }
1758
1759 return 0;
1760
1761 error:
1762 free(surf->u.gfx9.dcc_retile_map);
1763 surf->u.gfx9.dcc_retile_map = NULL;
1764 return r;
1765 }
1766
1767 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1768 const struct ac_surf_config *config,
1769 enum radeon_surf_mode mode,
1770 struct radeon_surf *surf)
1771 {
1772 int r;
1773
1774 r = surf_config_sanity(config, surf->flags);
1775 if (r)
1776 return r;
1777
1778 if (info->chip_class >= GFX9)
1779 r = gfx9_compute_surface(addrlib, info, config, mode, surf);
1780 else
1781 r = gfx6_compute_surface(addrlib, info, config, mode, surf);
1782
1783 if (r)
1784 return r;
1785
1786 /* Determine the memory layout of multiple allocations in one buffer. */
1787 surf->total_size = surf->surf_size;
1788
1789 if (surf->htile_size) {
1790 surf->htile_offset = align64(surf->total_size, surf->htile_alignment);
1791 surf->total_size = surf->htile_offset + surf->htile_size;
1792 }
1793
1794 if (surf->fmask_size) {
1795 assert(config->info.samples >= 2);
1796 surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment);
1797 surf->total_size = surf->fmask_offset + surf->fmask_size;
1798 }
1799
1800 /* Single-sample CMASK is in a separate buffer. */
1801 if (surf->cmask_size && config->info.samples >= 2) {
1802 surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
1803 surf->total_size = surf->cmask_offset + surf->cmask_size;
1804 }
1805
1806 if (surf->dcc_size &&
1807 /* dcc_size is computed on GFX9+ only if it's displayable. */
1808 (info->chip_class >= GFX9 || !get_display_flag(config, surf))) {
1809 /* It's better when displayable DCC is immediately after
1810 * the image due to hw-specific reasons.
1811 */
1812 if (info->chip_class >= GFX9 &&
1813 surf->u.gfx9.dcc_retile_num_elements) {
1814 /* Add space for the displayable DCC buffer. */
1815 surf->display_dcc_offset =
1816 align64(surf->total_size, surf->u.gfx9.display_dcc_alignment);
1817 surf->total_size = surf->display_dcc_offset +
1818 surf->u.gfx9.display_dcc_size;
1819
1820 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1821 surf->dcc_retile_map_offset =
1822 align64(surf->total_size, info->tcc_cache_line_size);
1823
1824 if (surf->u.gfx9.dcc_retile_use_uint16) {
1825 surf->total_size = surf->dcc_retile_map_offset +
1826 surf->u.gfx9.dcc_retile_num_elements * 2;
1827 } else {
1828 surf->total_size = surf->dcc_retile_map_offset +
1829 surf->u.gfx9.dcc_retile_num_elements * 4;
1830 }
1831 }
1832
1833 surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment);
1834 surf->total_size = surf->dcc_offset + surf->dcc_size;
1835 }
1836
1837 return 0;
1838 }