src/amd/common/ac_surface.c

   1 /*
   2  * Copyright © 2011 Red Hat All Rights Reserved.
   3  * Copyright © 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 #include "ac_surface.h"
  29 #include "amd_family.h"
  30 #include "amdgpu_id.h"
  31 #include "ac_gpu_info.h"
  32 #include "util/macros.h"
  33 #include "util/u_atomic.h"
  34 #include "util/u_math.h"
  35
  36 #include <errno.h>
  37 #include <stdio.h>
  38 #include <stdlib.h>
  39 #include <amdgpu.h>
  40 #include <amdgpu_drm.h>
  41
  42 #include "addrlib/addrinterface.h"
  43
  44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  46 #endif
  47
  48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
  49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
  50 #endif
  51
  52 static void addrlib_family_rev_id(enum radeon_family family,
  53                                   unsigned *addrlib_family,
  54                                   unsigned *addrlib_revid)
  55 {
  56         switch (family) {
  57         case CHIP_TAHITI:
  58                 *addrlib_family = FAMILY_SI;
  59                 *addrlib_revid = SI_TAHITI_P_A0;
  60                 break;
  61         case CHIP_PITCAIRN:
  62                 *addrlib_family = FAMILY_SI;
  63                 *addrlib_revid = SI_PITCAIRN_PM_A0;
  64                 break;
  65         case CHIP_VERDE:
  66                 *addrlib_family = FAMILY_SI;
  67                 *addrlib_revid = SI_CAPEVERDE_M_A0;
  68                 break;
  69         case CHIP_OLAND:
  70                 *addrlib_family = FAMILY_SI;
  71                 *addrlib_revid = SI_OLAND_M_A0;
  72                 break;
  73         case CHIP_HAINAN:
  74                 *addrlib_family = FAMILY_SI;
  75                 *addrlib_revid = SI_HAINAN_V_A0;
  76                 break;
  77         case CHIP_BONAIRE:
  78                 *addrlib_family = FAMILY_CI;
  79                 *addrlib_revid = CI_BONAIRE_M_A0;
  80                 break;
  81         case CHIP_KAVERI:
  82                 *addrlib_family = FAMILY_KV;
  83                 *addrlib_revid = KV_SPECTRE_A0;
  84                 break;
  85         case CHIP_KABINI:
  86                 *addrlib_family = FAMILY_KV;
  87                 *addrlib_revid = KB_KALINDI_A0;
  88                 break;
  89         case CHIP_HAWAII:
  90                 *addrlib_family = FAMILY_CI;
  91                 *addrlib_revid = CI_HAWAII_P_A0;
  92                 break;
  93         case CHIP_MULLINS:
  94                 *addrlib_family = FAMILY_KV;
  95                 *addrlib_revid = ML_GODAVARI_A0;
  96                 break;
  97         case CHIP_TONGA:
  98                 *addrlib_family = FAMILY_VI;
  99                 *addrlib_revid = VI_TONGA_P_A0;
 100                 break;
 101         case CHIP_ICELAND:
 102                 *addrlib_family = FAMILY_VI;
 103                 *addrlib_revid = VI_ICELAND_M_A0;
 104                 break;
 105         case CHIP_CARRIZO:
 106                 *addrlib_family = FAMILY_CZ;
 107                 *addrlib_revid = CARRIZO_A0;
 108                 break;
 109         case CHIP_STONEY:
 110                 *addrlib_family = FAMILY_CZ;
 111                 *addrlib_revid = STONEY_A0;
 112                 break;
 113         case CHIP_FIJI:
 114                 *addrlib_family = FAMILY_VI;
 115                 *addrlib_revid = VI_FIJI_P_A0;
 116                 break;
 117         case CHIP_POLARIS10:
 118                 *addrlib_family = FAMILY_VI;
 119                 *addrlib_revid = VI_POLARIS10_P_A0;
 120                 break;
 121         case CHIP_POLARIS11:
 122                 *addrlib_family = FAMILY_VI;
 123                 *addrlib_revid = VI_POLARIS11_M_A0;
 124                 break;
 125         case CHIP_POLARIS12:
 126                 *addrlib_family = FAMILY_VI;
 127                 *addrlib_revid = VI_POLARIS12_V_A0;
 128                 break;
 129         case CHIP_VEGA10:
 130                 *addrlib_family = FAMILY_AI;
 131                 *addrlib_revid = AI_VEGA10_P_A0;
 132                 break;
 133         case CHIP_RAVEN:
 134                 *addrlib_family = FAMILY_RV;
 135                 *addrlib_revid = RAVEN_A0;
 136                 break;
 137         default:
 138                 fprintf(stderr, "amdgpu: Unknown family.\n");
 139         }
 140 }
 141
 142 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
 143 {
 144         return malloc(pInput->sizeInBytes);
 145 }
 146
 147 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
 148 {
 149         free(pInput->pVirtAddr);
 150         return ADDR_OK;
 151 }
 152
 153 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 154                                const struct amdgpu_gpu_info *amdinfo,
 155                                uint64_t *max_alignment)
 156 {
 157         ADDR_CREATE_INPUT addrCreateInput = {0};
 158         ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 159         ADDR_REGISTER_VALUE regValue = {0};
 160         ADDR_CREATE_FLAGS createFlags = {{0}};
 161         ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
 162         ADDR_E_RETURNCODE addrRet;
 163
 164         addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 165         addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 166
 167         regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
 168         createFlags.value = 0;
 169
 170         addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
 171         if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
 172                 return NULL;
 173
 174         if (addrCreateInput.chipFamily >= FAMILY_AI) {
 175                 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
 176                 regValue.blockVarSizeLog2 = 0;
 177         } else {
 178                 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
 179                 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
 180
 181                 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
 182                 regValue.pTileConfig = amdinfo->gb_tile_mode;
 183                 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
 184                 if (addrCreateInput.chipFamily == FAMILY_SI) {
 185                         regValue.pMacroTileConfig = NULL;
 186                         regValue.noOfMacroEntries = 0;
 187                 } else {
 188                         regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
 189                         regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
 190                 }
 191
 192                 createFlags.useTileIndex = 1;
 193                 createFlags.useHtileSliceAlign = 1;
 194
 195                 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 196         }
 197
 198         addrCreateInput.callbacks.allocSysMem = allocSysMem;
 199         addrCreateInput.callbacks.freeSysMem = freeSysMem;
 200         addrCreateInput.callbacks.debugPrint = 0;
 201         addrCreateInput.createFlags = createFlags;
 202         addrCreateInput.regValue = regValue;
 203
 204         addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 205         if (addrRet != ADDR_OK)
 206                 return NULL;
 207
 208         if (max_alignment) {
 209                 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
 210                 if (addrRet == ADDR_OK){
 211                         *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
 212                 }
 213         }
 214         return addrCreateOutput.hLib;
 215 }
 216
 217 static int surf_config_sanity(const struct ac_surf_config *config)
 218 {
 219         /* all dimension must be at least 1 ! */
 220         if (!config->info.width || !config->info.height || !config->info.depth ||
 221             !config->info.array_size || !config->info.levels)
 222                 return -EINVAL;
 223
 224         switch (config->info.samples) {
 225         case 0:
 226         case 1:
 227         case 2:
 228         case 4:
 229         case 8:
 230                 break;
 231         default:
 232                 return -EINVAL;
 233         }
 234
 235         if (config->is_3d && config->info.array_size > 1)
 236                 return -EINVAL;
 237         if (config->is_cube && config->info.depth > 1)
 238                 return -EINVAL;
 239
 240         return 0;
 241 }
 242
 243 static int gfx6_compute_level(ADDR_HANDLE addrlib,
 244                               const struct ac_surf_config *config,
 245                               struct radeon_surf *surf, bool is_stencil,
 246                               unsigned level, bool compressed,
 247                               ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 248                               ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 249                               ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 250                               ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
 251                               ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
 252                               ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
 253 {
 254         struct legacy_surf_level *surf_level;
 255         ADDR_E_RETURNCODE ret;
 256
 257         AddrSurfInfoIn->mipLevel = level;
 258         AddrSurfInfoIn->width = u_minify(config->info.width, level);
 259         AddrSurfInfoIn->height = u_minify(config->info.height, level);
 260
 261         /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
 262          * because GFX9 needs linear alignment of 256 bytes.
 263          */
 264         if (config->info.levels == 1 &&
 265             AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
 266             AddrSurfInfoIn->bpp) {
 267                 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
 268
 269                 assert(util_is_power_of_two(AddrSurfInfoIn->bpp));
 270                 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
 271         }
 272
 273         if (config->is_3d)
 274                 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
 275         else if (config->is_cube)
 276                 AddrSurfInfoIn->numSlices = 6;
 277         else
 278                 AddrSurfInfoIn->numSlices = config->info.array_size;
 279
 280         if (level > 0) {
 281                 /* Set the base level pitch. This is needed for calculation
 282                  * of non-zero levels. */
 283                 if (is_stencil)
 284                         AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
 285                 else
 286                         AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
 287
 288                 /* Convert blocks to pixels for compressed formats. */
 289                 if (compressed)
 290                         AddrSurfInfoIn->basePitch *= surf->blk_w;
 291         }
 292
 293         ret = AddrComputeSurfaceInfo(addrlib,
 294                                      AddrSurfInfoIn,
 295                                      AddrSurfInfoOut);
 296         if (ret != ADDR_OK) {
 297                 return ret;
 298         }
 299
 300         surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
 301         surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
 302         surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 303         surf_level->nblk_x = AddrSurfInfoOut->pitch;
 304         surf_level->nblk_y = AddrSurfInfoOut->height;
 305
 306         switch (AddrSurfInfoOut->tileMode) {
 307         case ADDR_TM_LINEAR_ALIGNED:
 308                 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 309                 break;
 310         case ADDR_TM_1D_TILED_THIN1:
 311                 surf_level->mode = RADEON_SURF_MODE_1D;
 312                 break;
 313         case ADDR_TM_2D_TILED_THIN1:
 314                 surf_level->mode = RADEON_SURF_MODE_2D;
 315                 break;
 316         default:
 317                 assert(0);
 318         }
 319
 320         if (is_stencil)
 321                 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 322         else
 323                 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
 324
 325         surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 326
 327         /* Clear DCC fields at the beginning. */
 328         surf_level->dcc_offset = 0;
 329
 330         /* The previous level's flag tells us if we can use DCC for this level. */
 331         if (AddrSurfInfoIn->flags.dccCompatible &&
 332             (level == 0 || AddrDccOut->subLvlCompressible)) {
 333                 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 334                 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 335                 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 336                 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 337                 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 338
 339                 ret = AddrComputeDccInfo(addrlib,
 340                                          AddrDccIn,
 341                                          AddrDccOut);
 342
 343                 if (ret == ADDR_OK) {
 344                         surf_level->dcc_offset = surf->dcc_size;
 345                         surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 346                         surf->num_dcc_levels = level + 1;
 347                         surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 348                         surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 349                 }
 350         }
 351
 352         /* TC-compatible HTILE. */
 353         if (!is_stencil &&
 354             AddrSurfInfoIn->flags.depth &&
 355             surf_level->mode == RADEON_SURF_MODE_2D &&
 356             level == 0) {
 357                 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
 358                 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
 359                 AddrHtileIn->height = AddrSurfInfoOut->height;
 360                 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
 361                 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
 362                 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
 363                 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
 364                 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
 365                 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 366
 367                 ret = AddrComputeHtileInfo(addrlib,
 368                                            AddrHtileIn,
 369                                            AddrHtileOut);
 370
 371                 if (ret == ADDR_OK) {
 372                         surf->htile_size = AddrHtileOut->htileBytes;
 373                         surf->htile_slice_size = AddrHtileOut->sliceSize;
 374                         surf->htile_alignment = AddrHtileOut->baseAlign;
 375                 }
 376         }
 377
 378         return 0;
 379 }
 380
 381 #define   G_009910_MICRO_TILE_MODE(x)          (((x) >> 0) & 0x03)
 382 #define   G_009910_MICRO_TILE_MODE_NEW(x)      (((x) >> 22) & 0x07)
 383
 384 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
 385                                      const struct radeon_info *info)
 386 {
 387         uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
 388
 389         if (info->chip_class >= CIK)
 390                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 391         else
 392                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 393 }
 394
 395 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 396 {
 397         unsigned index, tileb;
 398
 399         tileb = 8 * 8 * surf->bpe;
 400         tileb = MIN2(surf->u.legacy.tile_split, tileb);
 401
 402         for (index = 0; tileb > 64; index++)
 403                 tileb >>= 1;
 404
 405         assert(index < 16);
 406         return index;
 407 }
 408
 409 /**
 410  * This must be called after the first level is computed.
 411  *
 412  * Copy surface-global settings like pipe/bank config from level 0 surface
 413  * computation, and compute tile swizzle.
 414  */
 415 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
 416                                  const struct radeon_info *info,
 417                                  const struct ac_surf_config *config,
 418                                  ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
 419                                  struct radeon_surf *surf)
 420 {
 421         surf->surf_alignment = csio->baseAlign;
 422         surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
 423         gfx6_set_micro_tile_mode(surf, info);
 424
 425         /* For 2D modes only. */
 426         if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
 427                 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
 428                 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
 429                 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
 430                 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
 431                 surf->u.legacy.num_banks = csio->pTileInfo->banks;
 432                 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
 433         } else {
 434                 surf->u.legacy.macro_tile_index = 0;
 435         }
 436
 437         /* Compute tile swizzle. */
 438         if (config->info.surf_index &&
 439             surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
 440             !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
 441             (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
 442                 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
 443                 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
 444
 445                 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
 446                 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
 447
 448                 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
 449                 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
 450                 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
 451                 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
 452                 AddrBaseSwizzleIn.tileMode = csio->tileMode;
 453
 454                 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
 455                                                &AddrBaseSwizzleOut);
 456                 if (r != ADDR_OK)
 457                         return r;
 458
 459                 assert(AddrBaseSwizzleOut.tileSwizzle <=
 460                        u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
 461                 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
 462         }
 463         return 0;
 464 }
 465
 466 /**
 467  * Fill in the tiling information in \p surf based on the given surface config.
 468  *
 469  * The following fields of \p surf must be initialized by the caller:
 470  * blk_w, blk_h, bpe, flags.
 471  */
 472 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 473                                 const struct radeon_info *info,
 474                                 const struct ac_surf_config *config,
 475                                 enum radeon_surf_mode mode,
 476                                 struct radeon_surf *surf)
 477 {
 478         unsigned level;
 479         bool compressed;
 480         ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 481         ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 482         ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 483         ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 484         ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 485         ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 486         ADDR_TILEINFO AddrTileInfoIn = {0};
 487         ADDR_TILEINFO AddrTileInfoOut = {0};
 488         int r;
 489
 490         AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 491         AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 492         AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 493         AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 494         AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
 495         AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
 496         AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 497
 498         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 499
 500         /* MSAA and FMASK require 2D tiling. */
 501         if (config->info.samples > 1 ||
 502             (surf->flags & RADEON_SURF_FMASK))
 503                 mode = RADEON_SURF_MODE_2D;
 504
 505         /* DB doesn't support linear layouts. */
 506         if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 507             mode < RADEON_SURF_MODE_1D)
 508                 mode = RADEON_SURF_MODE_1D;
 509
 510         /* Set the requested tiling mode. */
 511         switch (mode) {
 512         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 513                 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 514                 break;
 515         case RADEON_SURF_MODE_1D:
 516                 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 517                 break;
 518         case RADEON_SURF_MODE_2D:
 519                 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 520                 break;
 521         default:
 522                 assert(0);
 523         }
 524
 525         /* The format must be set correctly for the allocation of compressed
 526          * textures to work. In other cases, setting the bpp is sufficient.
 527          */
 528         if (compressed) {
 529                 switch (surf->bpe) {
 530                 case 8:
 531                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 532                         break;
 533                 case 16:
 534                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 535                         break;
 536                 default:
 537                         assert(0);
 538                 }
 539         }
 540         else {
 541                 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 542         }
 543
 544         AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
 545                 config->info.samples ? config->info.samples : 1;
 546         AddrSurfInfoIn.tileIndex = -1;
 547
 548         /* Set the micro tile type. */
 549         if (surf->flags & RADEON_SURF_SCANOUT)
 550                 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 551         else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
 552                 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 553         else
 554                 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 555
 556         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 557         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 558         AddrSurfInfoIn.flags.cube = config->is_cube;
 559         AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
 560         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 561         AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
 562         AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 563
 564         /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
 565          * requested, because TC-compatible HTILE requires 2D tiling.
 566          */
 567         AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
 568                                          !AddrSurfInfoIn.flags.fmask &&
 569                                          config->info.samples <= 1 &&
 570                                          (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
 571
 572         /* DCC notes:
 573          * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 574          *   with samples >= 4.
 575          * - Mipmapped array textures have low performance (discovered by a closed
 576          *   driver team).
 577          */
 578         AddrSurfInfoIn.flags.dccCompatible =
 579                 info->chip_class >= VI &&
 580                 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 581                 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 582                 !compressed && AddrDccIn.numSamples <= 1 &&
 583                 ((config->info.array_size == 1 && config->info.depth == 1) ||
 584                  config->info.levels == 1);
 585
 586         AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 587         AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 588
 589         /* noStencil = 0 can result in a depth part that is incompatible with
 590          * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 591          * this case, we may end up setting stencil_adjusted).
 592          *
 593          * TODO: update addrlib to a newer version, remove this, and
 594          * use flags.matchStencilTileCfg = 1 as an alternative fix.
 595          */
 596         if (config->info.levels > 1)
 597                 AddrSurfInfoIn.flags.noStencil = 1;
 598
 599         /* Set preferred macrotile parameters. This is usually required
 600          * for shared resources. This is for 2D tiling only. */
 601         if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 602             surf->u.legacy.bankw && surf->u.legacy.bankh &&
 603             surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
 604                 assert(!(surf->flags & RADEON_SURF_FMASK));
 605
 606                 /* If any of these parameters are incorrect, the calculation
 607                  * will fail. */
 608                 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
 609                 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
 610                 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
 611                 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
 612                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
 613                 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 614                 AddrSurfInfoIn.flags.opt4Space = 0;
 615                 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 616
 617                 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 618                  * the tile index, because we are expected to know it if
 619                  * we know the other parameters.
 620                  *
 621                  * This is something that can easily be fixed in Addrlib.
 622                  * For now, just figure it out here.
 623                  * Note that only 2D_TILE_THIN1 is handled here.
 624                  */
 625                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 626                 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 627
 628                 if (info->chip_class == SI) {
 629                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 630                                 if (surf->bpe == 2)
 631                                         AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 632                                 else
 633                                         AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 634                         } else {
 635                                 if (surf->bpe == 1)
 636                                         AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 637                                 else if (surf->bpe == 2)
 638                                         AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 639                                 else if (surf->bpe == 4)
 640                                         AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 641                                 else
 642                                         AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 643                         }
 644                 } else {
 645                         /* CIK - VI */
 646                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 647                                 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 648                         else
 649                                 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 650
 651                         /* Addrlib doesn't set this if tileIndex is forced like above. */
 652                         AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 653                 }
 654         }
 655
 656         surf->num_dcc_levels = 0;
 657         surf->surf_size = 0;
 658         surf->dcc_size = 0;
 659         surf->dcc_alignment = 1;
 660         surf->htile_size = 0;
 661         surf->htile_slice_size = 0;
 662         surf->htile_alignment = 1;
 663
 664         const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
 665                                   !(surf->flags & RADEON_SURF_ZBUFFER);
 666
 667         /* Calculate texture layout information. */
 668         if (!only_stencil) {
 669                 for (level = 0; level < config->info.levels; level++) {
 670                         r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
 671                                                &AddrSurfInfoIn, &AddrSurfInfoOut,
 672                                                &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
 673                         if (r)
 674                                 return r;
 675
 676                         if (level > 0)
 677                                 continue;
 678
 679                         r = gfx6_surface_settings(addrlib, info, config,
 680                                                   &AddrSurfInfoOut, surf);
 681                         if (r)
 682                                 return r;
 683                 }
 684         }
 685
 686         /* Calculate texture layout information for stencil. */
 687         if (surf->flags & RADEON_SURF_SBUFFER) {
 688                 AddrSurfInfoIn.bpp = 8;
 689                 AddrSurfInfoIn.flags.depth = 0;
 690                 AddrSurfInfoIn.flags.stencil = 1;
 691                 AddrSurfInfoIn.flags.tcCompatible = 0;
 692                 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 693                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
 694
 695                 for (level = 0; level < config->info.levels; level++) {
 696                         r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
 697                                                &AddrSurfInfoIn, &AddrSurfInfoOut,
 698                                                &AddrDccIn, &AddrDccOut,
 699                                                NULL, NULL);
 700                         if (r)
 701                                 return r;
 702
 703                         /* DB uses the depth pitch for both stencil and depth. */
 704                         if (!only_stencil) {
 705                                 if (surf->u.legacy.stencil_level[level].nblk_x !=
 706                                     surf->u.legacy.level[level].nblk_x)
 707                                         surf->u.legacy.stencil_adjusted = true;
 708                         } else {
 709                                 surf->u.legacy.level[level].nblk_x =
 710                                         surf->u.legacy.stencil_level[level].nblk_x;
 711                         }
 712
 713                         if (level == 0) {
 714                                 if (only_stencil) {
 715                                         r = gfx6_surface_settings(addrlib, info, config,
 716                                                                   &AddrSurfInfoOut, surf);
 717                                         if (r)
 718                                                 return r;
 719                                 }
 720
 721                                 /* For 2D modes only. */
 722                                 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 723                                         surf->u.legacy.stencil_tile_split =
 724                                                 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 725                                 }
 726                         }
 727                 }
 728         }
 729
 730         /* Recalculate the whole DCC miptree size including disabled levels.
 731          * This is what addrlib does, but calling addrlib would be a lot more
 732          * complicated.
 733          */
 734         if (surf->dcc_size && config->info.levels > 1) {
 735                 surf->dcc_size = align64(surf->surf_size >> 8,
 736                                          info->pipe_interleave_bytes *
 737                                          info->num_tile_pipes);
 738         }
 739
 740         /* Make sure HTILE covers the whole miptree, because the shader reads
 741          * TC-compatible HTILE even for levels where it's disabled by DB.
 742          */
 743         if (surf->htile_size && config->info.levels > 1)
 744                 surf->htile_size *= 2;
 745
 746         surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 747         return 0;
 748 }
 749
 750 /* This is only called when expecting a tiled layout. */
 751 static int
 752 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
 753                                 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
 754                                 bool is_fmask, AddrSwizzleMode *swizzle_mode)
 755 {
 756         ADDR_E_RETURNCODE ret;
 757         ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
 758         ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
 759
 760         sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
 761         sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
 762
 763         sin.flags = in->flags;
 764         sin.resourceType = in->resourceType;
 765         sin.format = in->format;
 766         sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
 767         /* TODO: We could allow some of these: */
 768         sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
 769         sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
 770         sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
 771         sin.bpp = in->bpp;
 772         sin.width = in->width;
 773         sin.height = in->height;
 774         sin.numSlices = in->numSlices;
 775         sin.numMipLevels = in->numMipLevels;
 776         sin.numSamples = in->numSamples;
 777         sin.numFrags = in->numFrags;
 778
 779         if (is_fmask) {
 780                 sin.flags.color = 0;
 781                 sin.flags.fmask = 1;
 782         }
 783
 784         ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
 785         if (ret != ADDR_OK)
 786                 return ret;
 787
 788         *swizzle_mode = sout.swizzleMode;
 789         return 0;
 790 }
 791
 792 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 793                                 struct radeon_surf *surf, bool compressed,
 794                                 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
 795 {
 796         ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
 797         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
 798         ADDR_E_RETURNCODE ret;
 799
 800         out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
 801         out.pMipInfo = mip_info;
 802
 803         ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
 804         if (ret != ADDR_OK)
 805         return ret;
 806
 807         if (in->flags.stencil) {
 808                 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
 809                 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
 810                                                                    out.mipChainPitch - 1;
 811                 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
 812                 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
 813                 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
 814                 return 0;
 815         }
 816
 817         surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
 818         surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
 819                                                         out.mipChainPitch - 1;
 820
 821         /* CMASK fast clear uses these even if FMASK isn't allocated.
 822          * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
 823          */
 824         surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
 825         surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
 826
 827         surf->u.gfx9.surf_slice_size = out.sliceSize;
 828         surf->u.gfx9.surf_pitch = out.pitch;
 829         surf->u.gfx9.surf_height = out.height;
 830         surf->surf_size = out.surfSize;
 831         surf->surf_alignment = out.baseAlign;
 832
 833         if (in->swizzleMode == ADDR_SW_LINEAR) {
 834                 for (unsigned i = 0; i < in->numMipLevels; i++)
 835                         surf->u.gfx9.offset[i] = mip_info[i].offset;
 836         }
 837
 838         if (in->flags.depth) {
 839                 assert(in->swizzleMode != ADDR_SW_LINEAR);
 840
 841                 /* HTILE */
 842                 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
 843                 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
 844
 845                 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
 846                 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
 847
 848                 hin.hTileFlags.pipeAligned = 1;
 849                 hin.hTileFlags.rbAligned = 1;
 850                 hin.depthFlags = in->flags;
 851                 hin.swizzleMode = in->swizzleMode;
 852                 hin.unalignedWidth = in->width;
 853                 hin.unalignedHeight = in->height;
 854                 hin.numSlices = in->numSlices;
 855                 hin.numMipLevels = in->numMipLevels;
 856
 857                 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
 858                 if (ret != ADDR_OK)
 859                         return ret;
 860
 861                 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
 862                 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
 863                 surf->htile_size = hout.htileBytes;
 864                 surf->htile_slice_size = hout.sliceSize;
 865                 surf->htile_alignment = hout.baseAlign;
 866         } else {
 867                 /* DCC */
 868                 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 869                     !(surf->flags & RADEON_SURF_SCANOUT) &&
 870                     !compressed &&
 871                     in->swizzleMode != ADDR_SW_LINEAR &&
 872                     /* TODO: We could support DCC with MSAA. */
 873                     in->numSamples == 1) {
 874                         ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
 875                         ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
 876
 877                         din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
 878                         dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
 879
 880                         din.dccKeyFlags.pipeAligned = 1;
 881                         din.dccKeyFlags.rbAligned = 1;
 882                         din.colorFlags = in->flags;
 883                         din.resourceType = in->resourceType;
 884                         din.swizzleMode = in->swizzleMode;
 885                         din.bpp = in->bpp;
 886                         din.unalignedWidth = in->width;
 887                         din.unalignedHeight = in->height;
 888                         din.numSlices = in->numSlices;
 889                         din.numFrags = in->numFrags;
 890                         din.numMipLevels = in->numMipLevels;
 891                         din.dataSurfaceSize = out.surfSize;
 892
 893                         ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
 894                         if (ret != ADDR_OK)
 895                                 return ret;
 896
 897                         surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
 898                         surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
 899                         surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
 900                         surf->dcc_size = dout.dccRamSize;
 901                         surf->dcc_alignment = dout.dccRamBaseAlign;
 902                 }
 903
 904                 /* FMASK */
 905                 if (in->numSamples > 1) {
 906                         ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
 907                         ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
 908
 909                         fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
 910                         fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
 911
 912                         ret = gfx9_get_preferred_swizzle_mode(addrlib, in, true, &fin.swizzleMode);
 913                         if (ret != ADDR_OK)
 914                                 return ret;
 915
 916                         fin.unalignedWidth = in->width;
 917                         fin.unalignedHeight = in->height;
 918                         fin.numSlices = in->numSlices;
 919                         fin.numSamples = in->numSamples;
 920                         fin.numFrags = in->numFrags;
 921
 922                         ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
 923                         if (ret != ADDR_OK)
 924                                 return ret;
 925
 926                         surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
 927                         surf->u.gfx9.fmask.epitch = fout.pitch - 1;
 928                         surf->u.gfx9.fmask_size = fout.fmaskBytes;
 929                         surf->u.gfx9.fmask_alignment = fout.baseAlign;
 930                 }
 931
 932                 /* CMASK */
 933                 if (in->swizzleMode != ADDR_SW_LINEAR) {
 934                         ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
 935                         ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
 936
 937                         cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
 938                         cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
 939
 940                         cin.cMaskFlags.pipeAligned = 1;
 941                         cin.cMaskFlags.rbAligned = 1;
 942                         cin.colorFlags = in->flags;
 943                         cin.resourceType = in->resourceType;
 944                         cin.unalignedWidth = in->width;
 945                         cin.unalignedHeight = in->height;
 946                         cin.numSlices = in->numSlices;
 947
 948                         if (in->numSamples > 1)
 949                                 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
 950                         else
 951                                 cin.swizzleMode = in->swizzleMode;
 952
 953                         ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
 954                         if (ret != ADDR_OK)
 955                                 return ret;
 956
 957                         surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
 958                         surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
 959                         surf->u.gfx9.cmask_size = cout.cmaskBytes;
 960                         surf->u.gfx9.cmask_alignment = cout.baseAlign;
 961                 }
 962         }
 963
 964         return 0;
 965 }
 966
 967 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 968                                 const struct ac_surf_config *config,
 969                                 enum radeon_surf_mode mode,
 970                                 struct radeon_surf *surf)
 971 {
 972         bool compressed;
 973         ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 974         int r;
 975
 976         assert(!(surf->flags & RADEON_SURF_FMASK));
 977
 978         AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
 979
 980         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 981
 982         /* The format must be set correctly for the allocation of compressed
 983          * textures to work. In other cases, setting the bpp is sufficient. */
 984         if (compressed) {
 985                 switch (surf->bpe) {
 986                 case 8:
 987                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 988                         break;
 989                 case 16:
 990                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 991                         break;
 992                 default:
 993                         assert(0);
 994                 }
 995         } else {
 996                 AddrSurfInfoIn.bpp = surf->bpe * 8;
 997         }
 998
 999         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1000         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1001         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
1002         /* flags.texture currently refers to TC-compatible HTILE */
1003         AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
1004                                        surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1005         AddrSurfInfoIn.flags.opt4space = 1;
1006
1007         AddrSurfInfoIn.numMipLevels = config->info.levels;
1008         AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
1009         AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1010
1011         /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1012          * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1013          * must sample 1D textures as 2D. */
1014         if (config->is_3d)
1015                 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1016         else
1017                 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1018
1019         AddrSurfInfoIn.width = config->info.width;
1020         AddrSurfInfoIn.height = config->info.height;
1021
1022         if (config->is_3d)
1023                 AddrSurfInfoIn.numSlices = config->info.depth;
1024         else if (config->is_cube)
1025                 AddrSurfInfoIn.numSlices = 6;
1026         else
1027                 AddrSurfInfoIn.numSlices = config->info.array_size;
1028
1029         switch (mode) {
1030         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1031                 assert(config->info.samples <= 1);
1032                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1033                 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1034                 break;
1035
1036         case RADEON_SURF_MODE_1D:
1037         case RADEON_SURF_MODE_2D:
1038                 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
1039                                                     &AddrSurfInfoIn.swizzleMode);
1040                 if (r)
1041                         return r;
1042                 break;
1043
1044         default:
1045                 assert(0);
1046         }
1047
1048         surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1049
1050         surf->surf_size = 0;
1051         surf->dcc_size = 0;
1052         surf->htile_size = 0;
1053         surf->htile_slice_size = 0;
1054         surf->u.gfx9.surf_offset = 0;
1055         surf->u.gfx9.stencil_offset = 0;
1056         surf->u.gfx9.fmask_size = 0;
1057         surf->u.gfx9.cmask_size = 0;
1058
1059         /* Calculate texture layout information. */
1060         r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1061         if (r)
1062                 return r;
1063
1064         /* Calculate texture layout information for stencil. */
1065         if (surf->flags & RADEON_SURF_SBUFFER) {
1066                 AddrSurfInfoIn.bpp = 8;
1067                 AddrSurfInfoIn.flags.depth = 0;
1068                 AddrSurfInfoIn.flags.stencil = 1;
1069
1070                 r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1071                 if (r)
1072                         return r;
1073         }
1074
1075         surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1076         surf->num_dcc_levels = surf->dcc_size ? config->info.levels : 0;
1077
1078         switch (surf->u.gfx9.surf.swizzle_mode) {
1079                 /* S = standard. */
1080                 case ADDR_SW_256B_S:
1081                 case ADDR_SW_4KB_S:
1082                 case ADDR_SW_64KB_S:
1083                 case ADDR_SW_VAR_S:
1084                 case ADDR_SW_64KB_S_T:
1085                 case ADDR_SW_4KB_S_X:
1086                 case ADDR_SW_64KB_S_X:
1087                 case ADDR_SW_VAR_S_X:
1088                         surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1089                         break;
1090
1091                 /* D = display. */
1092                 case ADDR_SW_LINEAR:
1093                 case ADDR_SW_256B_D:
1094                 case ADDR_SW_4KB_D:
1095                 case ADDR_SW_64KB_D:
1096                 case ADDR_SW_VAR_D:
1097                 case ADDR_SW_64KB_D_T:
1098                 case ADDR_SW_4KB_D_X:
1099                 case ADDR_SW_64KB_D_X:
1100                 case ADDR_SW_VAR_D_X:
1101                         surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1102                         break;
1103
1104                 /* R = rotated. */
1105                 case ADDR_SW_256B_R:
1106                 case ADDR_SW_4KB_R:
1107                 case ADDR_SW_64KB_R:
1108                 case ADDR_SW_VAR_R:
1109                 case ADDR_SW_64KB_R_T:
1110                 case ADDR_SW_4KB_R_X:
1111                 case ADDR_SW_64KB_R_X:
1112                 case ADDR_SW_VAR_R_X:
1113                         surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1114                         break;
1115
1116                 /* Z = depth. */
1117                 case ADDR_SW_4KB_Z:
1118                 case ADDR_SW_64KB_Z:
1119                 case ADDR_SW_VAR_Z:
1120                 case ADDR_SW_64KB_Z_T:
1121                 case ADDR_SW_4KB_Z_X:
1122                 case ADDR_SW_64KB_Z_X:
1123                 case ADDR_SW_VAR_Z_X:
1124                         surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1125                         break;
1126
1127                 default:
1128                         assert(0);
1129         }
1130
1131         return 0;
1132 }
1133
1134 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1135                        const struct ac_surf_config *config,
1136                        enum radeon_surf_mode mode,
1137                        struct radeon_surf *surf)
1138 {
1139         int r;
1140
1141         r = surf_config_sanity(config);
1142         if (r)
1143                 return r;
1144
1145         if (info->chip_class >= GFX9)
1146                 return gfx9_compute_surface(addrlib, config, mode, surf);
1147         else
1148                 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1149 }