src/amd/common/ac_surface.c

   1 /*
   2  * Copyright © 2011 Red Hat All Rights Reserved.
   3  * Copyright © 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 #include "ac_surface.h"
  29 #include "amd_family.h"
  30 #include "amdgpu_id.h"
  31 #include "ac_gpu_info.h"
  32 #include "util/macros.h"
  33 #include "util/u_atomic.h"
  34 #include "util/u_math.h"
  35
  36 #include <errno.h>
  37 #include <stdio.h>
  38 #include <stdlib.h>
  39 #include <amdgpu.h>
  40 #include <amdgpu_drm.h>
  41
  42 #include "addrlib/addrinterface.h"
  43
  44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  46 #endif
  47
  48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
  49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
  50 #endif
  51
  52 static void addrlib_family_rev_id(enum radeon_family family,
  53                                   unsigned *addrlib_family,
  54                                   unsigned *addrlib_revid)
  55 {
  56         switch (family) {
  57         case CHIP_TAHITI:
  58                 *addrlib_family = FAMILY_SI;
  59                 *addrlib_revid = SI_TAHITI_P_A0;
  60                 break;
  61         case CHIP_PITCAIRN:
  62                 *addrlib_family = FAMILY_SI;
  63                 *addrlib_revid = SI_PITCAIRN_PM_A0;
  64                 break;
  65         case CHIP_VERDE:
  66                 *addrlib_family = FAMILY_SI;
  67                 *addrlib_revid = SI_CAPEVERDE_M_A0;
  68                 break;
  69         case CHIP_OLAND:
  70                 *addrlib_family = FAMILY_SI;
  71                 *addrlib_revid = SI_OLAND_M_A0;
  72                 break;
  73         case CHIP_HAINAN:
  74                 *addrlib_family = FAMILY_SI;
  75                 *addrlib_revid = SI_HAINAN_V_A0;
  76                 break;
  77         case CHIP_BONAIRE:
  78                 *addrlib_family = FAMILY_CI;
  79                 *addrlib_revid = CI_BONAIRE_M_A0;
  80                 break;
  81         case CHIP_KAVERI:
  82                 *addrlib_family = FAMILY_KV;
  83                 *addrlib_revid = KV_SPECTRE_A0;
  84                 break;
  85         case CHIP_KABINI:
  86                 *addrlib_family = FAMILY_KV;
  87                 *addrlib_revid = KB_KALINDI_A0;
  88                 break;
  89         case CHIP_HAWAII:
  90                 *addrlib_family = FAMILY_CI;
  91                 *addrlib_revid = CI_HAWAII_P_A0;
  92                 break;
  93         case CHIP_MULLINS:
  94                 *addrlib_family = FAMILY_KV;
  95                 *addrlib_revid = ML_GODAVARI_A0;
  96                 break;
  97         case CHIP_TONGA:
  98                 *addrlib_family = FAMILY_VI;
  99                 *addrlib_revid = VI_TONGA_P_A0;
 100                 break;
 101         case CHIP_ICELAND:
 102                 *addrlib_family = FAMILY_VI;
 103                 *addrlib_revid = VI_ICELAND_M_A0;
 104                 break;
 105         case CHIP_CARRIZO:
 106                 *addrlib_family = FAMILY_CZ;
 107                 *addrlib_revid = CARRIZO_A0;
 108                 break;
 109         case CHIP_STONEY:
 110                 *addrlib_family = FAMILY_CZ;
 111                 *addrlib_revid = STONEY_A0;
 112                 break;
 113         case CHIP_FIJI:
 114                 *addrlib_family = FAMILY_VI;
 115                 *addrlib_revid = VI_FIJI_P_A0;
 116                 break;
 117         case CHIP_POLARIS10:
 118                 *addrlib_family = FAMILY_VI;
 119                 *addrlib_revid = VI_POLARIS10_P_A0;
 120                 break;
 121         case CHIP_POLARIS11:
 122                 *addrlib_family = FAMILY_VI;
 123                 *addrlib_revid = VI_POLARIS11_M_A0;
 124                 break;
 125         case CHIP_POLARIS12:
 126                 *addrlib_family = FAMILY_VI;
 127                 *addrlib_revid = VI_POLARIS12_V_A0;
 128                 break;
 129         case CHIP_VEGA10:
 130                 *addrlib_family = FAMILY_AI;
 131                 *addrlib_revid = AI_VEGA10_P_A0;
 132                 break;
 133         case CHIP_RAVEN:
 134                 *addrlib_family = FAMILY_RV;
 135                 *addrlib_revid = RAVEN_A0;
 136                 break;
 137         default:
 138                 fprintf(stderr, "amdgpu: Unknown family.\n");
 139         }
 140 }
 141
 142 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
 143 {
 144         return malloc(pInput->sizeInBytes);
 145 }
 146
 147 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
 148 {
 149         free(pInput->pVirtAddr);
 150         return ADDR_OK;
 151 }
 152
 153 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 154                                const struct amdgpu_gpu_info *amdinfo,
 155                                uint64_t *max_alignment)
 156 {
 157         ADDR_CREATE_INPUT addrCreateInput = {0};
 158         ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 159         ADDR_REGISTER_VALUE regValue = {0};
 160         ADDR_CREATE_FLAGS createFlags = {{0}};
 161         ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
 162         ADDR_E_RETURNCODE addrRet;
 163
 164         addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 165         addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 166
 167         regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
 168         createFlags.value = 0;
 169
 170         addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
 171         if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
 172                 return NULL;
 173
 174         if (addrCreateInput.chipFamily >= FAMILY_AI) {
 175                 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
 176                 regValue.blockVarSizeLog2 = 0;
 177         } else {
 178                 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
 179                 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
 180
 181                 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
 182                 regValue.pTileConfig = amdinfo->gb_tile_mode;
 183                 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
 184                 if (addrCreateInput.chipFamily == FAMILY_SI) {
 185                         regValue.pMacroTileConfig = NULL;
 186                         regValue.noOfMacroEntries = 0;
 187                 } else {
 188                         regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
 189                         regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
 190                 }
 191
 192                 createFlags.useTileIndex = 1;
 193                 createFlags.useHtileSliceAlign = 1;
 194
 195                 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 196         }
 197
 198         addrCreateInput.callbacks.allocSysMem = allocSysMem;
 199         addrCreateInput.callbacks.freeSysMem = freeSysMem;
 200         addrCreateInput.callbacks.debugPrint = 0;
 201         addrCreateInput.createFlags = createFlags;
 202         addrCreateInput.regValue = regValue;
 203
 204         addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 205         if (addrRet != ADDR_OK)
 206                 return NULL;
 207
 208         if (max_alignment) {
 209                 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
 210                 if (addrRet == ADDR_OK){
 211                         *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
 212                 }
 213         }
 214         return addrCreateOutput.hLib;
 215 }
 216
 217 static int surf_config_sanity(const struct ac_surf_config *config)
 218 {
 219         /* all dimension must be at least 1 ! */
 220         if (!config->info.width || !config->info.height || !config->info.depth ||
 221             !config->info.array_size || !config->info.levels)
 222                 return -EINVAL;
 223
 224         switch (config->info.samples) {
 225         case 0:
 226         case 1:
 227         case 2:
 228         case 4:
 229         case 8:
 230                 break;
 231         default:
 232                 return -EINVAL;
 233         }
 234
 235         if (config->is_3d && config->info.array_size > 1)
 236                 return -EINVAL;
 237         if (config->is_cube && config->info.depth > 1)
 238                 return -EINVAL;
 239
 240         return 0;
 241 }
 242
 243 static int gfx6_compute_level(ADDR_HANDLE addrlib,
 244                               const struct ac_surf_config *config,
 245                               struct radeon_surf *surf, bool is_stencil,
 246                               unsigned level, bool compressed,
 247                               ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 248                               ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 249                               ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 250                               ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
 251                               ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
 252                               ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
 253 {
 254         struct legacy_surf_level *surf_level;
 255         ADDR_E_RETURNCODE ret;
 256
 257         AddrSurfInfoIn->mipLevel = level;
 258         AddrSurfInfoIn->width = u_minify(config->info.width, level);
 259         AddrSurfInfoIn->height = u_minify(config->info.height, level);
 260
 261         /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
 262          * because GFX9 needs linear alignment of 256 bytes.
 263          */
 264         if (config->info.levels == 1 &&
 265             AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
 266             AddrSurfInfoIn->bpp) {
 267                 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
 268
 269                 assert(util_is_power_of_two(AddrSurfInfoIn->bpp));
 270                 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
 271         }
 272
 273         if (config->is_3d)
 274                 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
 275         else if (config->is_cube)
 276                 AddrSurfInfoIn->numSlices = 6;
 277         else
 278                 AddrSurfInfoIn->numSlices = config->info.array_size;
 279
 280         if (level > 0) {
 281                 /* Set the base level pitch. This is needed for calculation
 282                  * of non-zero levels. */
 283                 if (is_stencil)
 284                         AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
 285                 else
 286                         AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
 287
 288                 /* Convert blocks to pixels for compressed formats. */
 289                 if (compressed)
 290                         AddrSurfInfoIn->basePitch *= surf->blk_w;
 291         }
 292
 293         ret = AddrComputeSurfaceInfo(addrlib,
 294                                      AddrSurfInfoIn,
 295                                      AddrSurfInfoOut);
 296         if (ret != ADDR_OK) {
 297                 return ret;
 298         }
 299
 300         surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
 301         surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
 302         surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 303         surf_level->nblk_x = AddrSurfInfoOut->pitch;
 304         surf_level->nblk_y = AddrSurfInfoOut->height;
 305
 306         switch (AddrSurfInfoOut->tileMode) {
 307         case ADDR_TM_LINEAR_ALIGNED:
 308                 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 309                 break;
 310         case ADDR_TM_1D_TILED_THIN1:
 311                 surf_level->mode = RADEON_SURF_MODE_1D;
 312                 break;
 313         case ADDR_TM_2D_TILED_THIN1:
 314                 surf_level->mode = RADEON_SURF_MODE_2D;
 315                 break;
 316         default:
 317                 assert(0);
 318         }
 319
 320         if (is_stencil)
 321                 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 322         else
 323                 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
 324
 325         surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 326
 327         /* Clear DCC fields at the beginning. */
 328         surf_level->dcc_offset = 0;
 329
 330         /* The previous level's flag tells us if we can use DCC for this level. */
 331         if (AddrSurfInfoIn->flags.dccCompatible &&
 332             (level == 0 || AddrDccOut->subLvlCompressible)) {
 333                 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 334                 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 335                 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 336                 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 337                 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 338
 339                 ret = AddrComputeDccInfo(addrlib,
 340                                          AddrDccIn,
 341                                          AddrDccOut);
 342
 343                 if (ret == ADDR_OK) {
 344                         surf_level->dcc_offset = surf->dcc_size;
 345                         surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 346                         surf->num_dcc_levels = level + 1;
 347                         surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 348                         surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 349                 }
 350         }
 351
 352         /* TC-compatible HTILE. */
 353         if (!is_stencil &&
 354             AddrSurfInfoIn->flags.depth &&
 355             surf_level->mode == RADEON_SURF_MODE_2D &&
 356             level == 0) {
 357                 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
 358                 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
 359                 AddrHtileIn->height = AddrSurfInfoOut->height;
 360                 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
 361                 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
 362                 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
 363                 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
 364                 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
 365                 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 366
 367                 ret = AddrComputeHtileInfo(addrlib,
 368                                            AddrHtileIn,
 369                                            AddrHtileOut);
 370
 371                 if (ret == ADDR_OK) {
 372                         surf->htile_size = AddrHtileOut->htileBytes;
 373                         surf->htile_slice_size = AddrHtileOut->sliceSize;
 374                         surf->htile_alignment = AddrHtileOut->baseAlign;
 375                 }
 376         }
 377
 378         return 0;
 379 }
 380
 381 #define   G_009910_MICRO_TILE_MODE(x)          (((x) >> 0) & 0x03)
 382 #define   G_009910_MICRO_TILE_MODE_NEW(x)      (((x) >> 22) & 0x07)
 383
 384 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
 385                                      const struct radeon_info *info)
 386 {
 387         uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
 388
 389         if (info->chip_class >= CIK)
 390                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 391         else
 392                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 393 }
 394
 395 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 396 {
 397         unsigned index, tileb;
 398
 399         tileb = 8 * 8 * surf->bpe;
 400         tileb = MIN2(surf->u.legacy.tile_split, tileb);
 401
 402         for (index = 0; tileb > 64; index++)
 403                 tileb >>= 1;
 404
 405         assert(index < 16);
 406         return index;
 407 }
 408
 409 /**
 410  * This must be called after the first level is computed.
 411  *
 412  * Copy surface-global settings like pipe/bank config from level 0 surface
 413  * computation, and compute tile swizzle.
 414  */
 415 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
 416                                  const struct radeon_info *info,
 417                                  const struct ac_surf_config *config,
 418                                  ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
 419                                  struct radeon_surf *surf)
 420 {
 421         surf->surf_alignment = csio->baseAlign;
 422         surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
 423         gfx6_set_micro_tile_mode(surf, info);
 424
 425         /* For 2D modes only. */
 426         if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
 427                 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
 428                 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
 429                 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
 430                 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
 431                 surf->u.legacy.num_banks = csio->pTileInfo->banks;
 432                 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
 433         } else {
 434                 surf->u.legacy.macro_tile_index = 0;
 435         }
 436
 437         /* Compute tile swizzle. */
 438         /* TODO: fix tile swizzle with mipmapping for SI */
 439         if ((info->chip_class >= CIK || config->info.levels == 1) &&
 440             config->info.surf_index &&
 441             surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
 442             !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
 443             (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
 444                 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
 445                 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
 446
 447                 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
 448                 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
 449
 450                 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
 451                 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
 452                 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
 453                 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
 454                 AddrBaseSwizzleIn.tileMode = csio->tileMode;
 455
 456                 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
 457                                                &AddrBaseSwizzleOut);
 458                 if (r != ADDR_OK)
 459                         return r;
 460
 461                 assert(AddrBaseSwizzleOut.tileSwizzle <=
 462                        u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
 463                 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
 464         }
 465         return 0;
 466 }
 467
 468 /**
 469  * Fill in the tiling information in \p surf based on the given surface config.
 470  *
 471  * The following fields of \p surf must be initialized by the caller:
 472  * blk_w, blk_h, bpe, flags.
 473  */
 474 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 475                                 const struct radeon_info *info,
 476                                 const struct ac_surf_config *config,
 477                                 enum radeon_surf_mode mode,
 478                                 struct radeon_surf *surf)
 479 {
 480         unsigned level;
 481         bool compressed;
 482         ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 483         ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 484         ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 485         ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 486         ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 487         ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 488         ADDR_TILEINFO AddrTileInfoIn = {0};
 489         ADDR_TILEINFO AddrTileInfoOut = {0};
 490         int r;
 491
 492         AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 493         AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 494         AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 495         AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 496         AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
 497         AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
 498         AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 499
 500         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 501
 502         /* MSAA and FMASK require 2D tiling. */
 503         if (config->info.samples > 1 ||
 504             (surf->flags & RADEON_SURF_FMASK))
 505                 mode = RADEON_SURF_MODE_2D;
 506
 507         /* DB doesn't support linear layouts. */
 508         if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 509             mode < RADEON_SURF_MODE_1D)
 510                 mode = RADEON_SURF_MODE_1D;
 511
 512         /* Set the requested tiling mode. */
 513         switch (mode) {
 514         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 515                 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 516                 break;
 517         case RADEON_SURF_MODE_1D:
 518                 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 519                 break;
 520         case RADEON_SURF_MODE_2D:
 521                 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 522                 break;
 523         default:
 524                 assert(0);
 525         }
 526
 527         /* The format must be set correctly for the allocation of compressed
 528          * textures to work. In other cases, setting the bpp is sufficient.
 529          */
 530         if (compressed) {
 531                 switch (surf->bpe) {
 532                 case 8:
 533                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 534                         break;
 535                 case 16:
 536                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 537                         break;
 538                 default:
 539                         assert(0);
 540                 }
 541         }
 542         else {
 543                 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 544         }
 545
 546         AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
 547                 config->info.samples ? config->info.samples : 1;
 548         AddrSurfInfoIn.tileIndex = -1;
 549
 550         /* Set the micro tile type. */
 551         if (surf->flags & RADEON_SURF_SCANOUT)
 552                 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 553         else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
 554                 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 555         else
 556                 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 557
 558         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 559         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 560         AddrSurfInfoIn.flags.cube = config->is_cube;
 561         AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
 562         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 563         AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
 564         AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 565
 566         /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
 567          * requested, because TC-compatible HTILE requires 2D tiling.
 568          */
 569         AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
 570                                          !AddrSurfInfoIn.flags.fmask &&
 571                                          config->info.samples <= 1 &&
 572                                          (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
 573
 574         /* DCC notes:
 575          * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 576          *   with samples >= 4.
 577          * - Mipmapped array textures have low performance (discovered by a closed
 578          *   driver team).
 579          */
 580         AddrSurfInfoIn.flags.dccCompatible =
 581                 info->chip_class >= VI &&
 582                 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 583                 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 584                 !compressed && AddrDccIn.numSamples <= 1 &&
 585                 ((config->info.array_size == 1 && config->info.depth == 1) ||
 586                  config->info.levels == 1);
 587
 588         AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 589         AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 590
 591         /* noStencil = 0 can result in a depth part that is incompatible with
 592          * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 593          * this case, we may end up setting stencil_adjusted).
 594          *
 595          * TODO: update addrlib to a newer version, remove this, and
 596          * use flags.matchStencilTileCfg = 1 as an alternative fix.
 597          */
 598         if (config->info.levels > 1)
 599                 AddrSurfInfoIn.flags.noStencil = 1;
 600
 601         /* Set preferred macrotile parameters. This is usually required
 602          * for shared resources. This is for 2D tiling only. */
 603         if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 604             surf->u.legacy.bankw && surf->u.legacy.bankh &&
 605             surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
 606                 assert(!(surf->flags & RADEON_SURF_FMASK));
 607
 608                 /* If any of these parameters are incorrect, the calculation
 609                  * will fail. */
 610                 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
 611                 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
 612                 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
 613                 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
 614                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
 615                 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 616                 AddrSurfInfoIn.flags.opt4Space = 0;
 617                 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 618
 619                 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 620                  * the tile index, because we are expected to know it if
 621                  * we know the other parameters.
 622                  *
 623                  * This is something that can easily be fixed in Addrlib.
 624                  * For now, just figure it out here.
 625                  * Note that only 2D_TILE_THIN1 is handled here.
 626                  */
 627                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 628                 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 629
 630                 if (info->chip_class == SI) {
 631                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 632                                 if (surf->bpe == 2)
 633                                         AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 634                                 else
 635                                         AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 636                         } else {
 637                                 if (surf->bpe == 1)
 638                                         AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 639                                 else if (surf->bpe == 2)
 640                                         AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 641                                 else if (surf->bpe == 4)
 642                                         AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 643                                 else
 644                                         AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 645                         }
 646                 } else {
 647                         /* CIK - VI */
 648                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 649                                 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 650                         else
 651                                 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 652
 653                         /* Addrlib doesn't set this if tileIndex is forced like above. */
 654                         AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 655                 }
 656         }
 657
 658         surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
 659         surf->num_dcc_levels = 0;
 660         surf->surf_size = 0;
 661         surf->dcc_size = 0;
 662         surf->dcc_alignment = 1;
 663         surf->htile_size = 0;
 664         surf->htile_slice_size = 0;
 665         surf->htile_alignment = 1;
 666
 667         const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
 668                                   !(surf->flags & RADEON_SURF_ZBUFFER);
 669
 670         /* Calculate texture layout information. */
 671         if (!only_stencil) {
 672                 for (level = 0; level < config->info.levels; level++) {
 673                         r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
 674                                                &AddrSurfInfoIn, &AddrSurfInfoOut,
 675                                                &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
 676                         if (r)
 677                                 return r;
 678
 679                         if (level > 0)
 680                                 continue;
 681
 682                         r = gfx6_surface_settings(addrlib, info, config,
 683                                                   &AddrSurfInfoOut, surf);
 684                         if (r)
 685                                 return r;
 686                 }
 687         }
 688
 689         /* Calculate texture layout information for stencil. */
 690         if (surf->flags & RADEON_SURF_SBUFFER) {
 691                 AddrSurfInfoIn.bpp = 8;
 692                 AddrSurfInfoIn.flags.depth = 0;
 693                 AddrSurfInfoIn.flags.stencil = 1;
 694                 AddrSurfInfoIn.flags.tcCompatible = 0;
 695                 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 696                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
 697
 698                 for (level = 0; level < config->info.levels; level++) {
 699                         r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
 700                                                &AddrSurfInfoIn, &AddrSurfInfoOut,
 701                                                &AddrDccIn, &AddrDccOut,
 702                                                NULL, NULL);
 703                         if (r)
 704                                 return r;
 705
 706                         /* DB uses the depth pitch for both stencil and depth. */
 707                         if (!only_stencil) {
 708                                 if (surf->u.legacy.stencil_level[level].nblk_x !=
 709                                     surf->u.legacy.level[level].nblk_x)
 710                                         surf->u.legacy.stencil_adjusted = true;
 711                         } else {
 712                                 surf->u.legacy.level[level].nblk_x =
 713                                         surf->u.legacy.stencil_level[level].nblk_x;
 714                         }
 715
 716                         if (level == 0) {
 717                                 if (only_stencil) {
 718                                         r = gfx6_surface_settings(addrlib, info, config,
 719                                                                   &AddrSurfInfoOut, surf);
 720                                         if (r)
 721                                                 return r;
 722                                 }
 723
 724                                 /* For 2D modes only. */
 725                                 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 726                                         surf->u.legacy.stencil_tile_split =
 727                                                 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 728                                 }
 729                         }
 730                 }
 731         }
 732
 733         /* Recalculate the whole DCC miptree size including disabled levels.
 734          * This is what addrlib does, but calling addrlib would be a lot more
 735          * complicated.
 736          */
 737         if (surf->dcc_size && config->info.levels > 1) {
 738                 /* The smallest miplevels that are never compressed by DCC
 739                  * still read the DCC buffer via TC if the base level uses DCC,
 740                  * and for some reason the DCC buffer needs to be larger if
 741                  * the miptree uses non-zero tile_swizzle. Otherwise there are
 742                  * VM faults.
 743                  *
 744                  * "dcc_alignment * 4" was determined by trial and error.
 745                  */
 746                 surf->dcc_size = align64(surf->surf_size >> 8,
 747                                          surf->dcc_alignment * 4);
 748         }
 749
 750         /* Make sure HTILE covers the whole miptree, because the shader reads
 751          * TC-compatible HTILE even for levels where it's disabled by DB.
 752          */
 753         if (surf->htile_size && config->info.levels > 1)
 754                 surf->htile_size *= 2;
 755
 756         surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 757         return 0;
 758 }
 759
 760 /* This is only called when expecting a tiled layout. */
 761 static int
 762 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
 763                                 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
 764                                 bool is_fmask, AddrSwizzleMode *swizzle_mode)
 765 {
 766         ADDR_E_RETURNCODE ret;
 767         ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
 768         ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
 769
 770         sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
 771         sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
 772
 773         sin.flags = in->flags;
 774         sin.resourceType = in->resourceType;
 775         sin.format = in->format;
 776         sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
 777         /* TODO: We could allow some of these: */
 778         sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
 779         sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
 780         sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
 781         sin.bpp = in->bpp;
 782         sin.width = in->width;
 783         sin.height = in->height;
 784         sin.numSlices = in->numSlices;
 785         sin.numMipLevels = in->numMipLevels;
 786         sin.numSamples = in->numSamples;
 787         sin.numFrags = in->numFrags;
 788
 789         if (is_fmask) {
 790                 sin.flags.color = 0;
 791                 sin.flags.fmask = 1;
 792         }
 793
 794         ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
 795         if (ret != ADDR_OK)
 796                 return ret;
 797
 798         *swizzle_mode = sout.swizzleMode;
 799         return 0;
 800 }
 801
 802 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 803                                 struct radeon_surf *surf, bool compressed,
 804                                 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
 805 {
 806         ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
 807         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
 808         ADDR_E_RETURNCODE ret;
 809
 810         out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
 811         out.pMipInfo = mip_info;
 812
 813         ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
 814         if (ret != ADDR_OK)
 815         return ret;
 816
 817         if (in->flags.stencil) {
 818                 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
 819                 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
 820                                                                    out.mipChainPitch - 1;
 821                 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
 822                 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
 823                 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
 824                 return 0;
 825         }
 826
 827         surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
 828         surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
 829                                                         out.mipChainPitch - 1;
 830
 831         /* CMASK fast clear uses these even if FMASK isn't allocated.
 832          * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
 833          */
 834         surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
 835         surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
 836
 837         surf->u.gfx9.surf_slice_size = out.sliceSize;
 838         surf->u.gfx9.surf_pitch = out.pitch;
 839         surf->u.gfx9.surf_height = out.height;
 840         surf->surf_size = out.surfSize;
 841         surf->surf_alignment = out.baseAlign;
 842
 843         if (in->swizzleMode == ADDR_SW_LINEAR) {
 844                 for (unsigned i = 0; i < in->numMipLevels; i++)
 845                         surf->u.gfx9.offset[i] = mip_info[i].offset;
 846         }
 847
 848         if (in->flags.depth) {
 849                 assert(in->swizzleMode != ADDR_SW_LINEAR);
 850
 851                 /* HTILE */
 852                 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
 853                 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
 854
 855                 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
 856                 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
 857
 858                 hin.hTileFlags.pipeAligned = 1;
 859                 hin.hTileFlags.rbAligned = 1;
 860                 hin.depthFlags = in->flags;
 861                 hin.swizzleMode = in->swizzleMode;
 862                 hin.unalignedWidth = in->width;
 863                 hin.unalignedHeight = in->height;
 864                 hin.numSlices = in->numSlices;
 865                 hin.numMipLevels = in->numMipLevels;
 866
 867                 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
 868                 if (ret != ADDR_OK)
 869                         return ret;
 870
 871                 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
 872                 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
 873                 surf->htile_size = hout.htileBytes;
 874                 surf->htile_slice_size = hout.sliceSize;
 875                 surf->htile_alignment = hout.baseAlign;
 876         } else {
 877                 /* DCC */
 878                 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 879                     !(surf->flags & RADEON_SURF_SCANOUT) &&
 880                     !compressed &&
 881                     in->swizzleMode != ADDR_SW_LINEAR &&
 882                     /* TODO: We could support DCC with MSAA. */
 883                     in->numSamples == 1) {
 884                         ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
 885                         ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
 886
 887                         din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
 888                         dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
 889
 890                         din.dccKeyFlags.pipeAligned = 1;
 891                         din.dccKeyFlags.rbAligned = 1;
 892                         din.colorFlags = in->flags;
 893                         din.resourceType = in->resourceType;
 894                         din.swizzleMode = in->swizzleMode;
 895                         din.bpp = in->bpp;
 896                         din.unalignedWidth = in->width;
 897                         din.unalignedHeight = in->height;
 898                         din.numSlices = in->numSlices;
 899                         din.numFrags = in->numFrags;
 900                         din.numMipLevels = in->numMipLevels;
 901                         din.dataSurfaceSize = out.surfSize;
 902
 903                         ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
 904                         if (ret != ADDR_OK)
 905                                 return ret;
 906
 907                         surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
 908                         surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
 909                         surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
 910                         surf->dcc_size = dout.dccRamSize;
 911                         surf->dcc_alignment = dout.dccRamBaseAlign;
 912                         surf->num_dcc_levels = in->numMipLevels;
 913
 914                         /* Disable DCC for the smallest levels. It seems to be
 915                          * required for DCC readability between CB and shaders
 916                          * when TC L2 isn't flushed. This was guessed.
 917                          *
 918                          * Alternative solutions that also work but are worse:
 919                          * - Disable DCC.
 920                          * - Flush TC L2 after rendering.
 921                          */
 922                         for (unsigned i = 1; i < in->numMipLevels; i++) {
 923                                 if (mip_info[i].pitch *
 924                                     mip_info[i].height * surf->bpe < 1024) {
 925                                         surf->num_dcc_levels = i;
 926                                         break;
 927                                 }
 928                         }
 929                 }
 930
 931                 /* FMASK */
 932                 if (in->numSamples > 1) {
 933                         ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
 934                         ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
 935
 936                         fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
 937                         fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
 938
 939                         ret = gfx9_get_preferred_swizzle_mode(addrlib, in, true, &fin.swizzleMode);
 940                         if (ret != ADDR_OK)
 941                                 return ret;
 942
 943                         fin.unalignedWidth = in->width;
 944                         fin.unalignedHeight = in->height;
 945                         fin.numSlices = in->numSlices;
 946                         fin.numSamples = in->numSamples;
 947                         fin.numFrags = in->numFrags;
 948
 949                         ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
 950                         if (ret != ADDR_OK)
 951                                 return ret;
 952
 953                         surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
 954                         surf->u.gfx9.fmask.epitch = fout.pitch - 1;
 955                         surf->u.gfx9.fmask_size = fout.fmaskBytes;
 956                         surf->u.gfx9.fmask_alignment = fout.baseAlign;
 957                 }
 958
 959                 /* CMASK */
 960                 if (in->swizzleMode != ADDR_SW_LINEAR) {
 961                         ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
 962                         ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
 963
 964                         cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
 965                         cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
 966
 967                         cin.cMaskFlags.pipeAligned = 1;
 968                         cin.cMaskFlags.rbAligned = 1;
 969                         cin.colorFlags = in->flags;
 970                         cin.resourceType = in->resourceType;
 971                         cin.unalignedWidth = in->width;
 972                         cin.unalignedHeight = in->height;
 973                         cin.numSlices = in->numSlices;
 974
 975                         if (in->numSamples > 1)
 976                                 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
 977                         else
 978                                 cin.swizzleMode = in->swizzleMode;
 979
 980                         ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
 981                         if (ret != ADDR_OK)
 982                                 return ret;
 983
 984                         surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
 985                         surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
 986                         surf->u.gfx9.cmask_size = cout.cmaskBytes;
 987                         surf->u.gfx9.cmask_alignment = cout.baseAlign;
 988                 }
 989         }
 990
 991         return 0;
 992 }
 993
 994 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 995                                 const struct ac_surf_config *config,
 996                                 enum radeon_surf_mode mode,
 997                                 struct radeon_surf *surf)
 998 {
 999         bool compressed;
1000         ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1001         int r;
1002
1003         assert(!(surf->flags & RADEON_SURF_FMASK));
1004
1005         AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1006
1007         compressed = surf->blk_w == 4 && surf->blk_h == 4;
1008
1009         /* The format must be set correctly for the allocation of compressed
1010          * textures to work. In other cases, setting the bpp is sufficient. */
1011         if (compressed) {
1012                 switch (surf->bpe) {
1013                 case 8:
1014                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
1015                         break;
1016                 case 16:
1017                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
1018                         break;
1019                 default:
1020                         assert(0);
1021                 }
1022         } else {
1023                 AddrSurfInfoIn.bpp = surf->bpe * 8;
1024         }
1025
1026         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1027         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1028         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
1029         /* flags.texture currently refers to TC-compatible HTILE */
1030         AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
1031                                        surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1032         AddrSurfInfoIn.flags.opt4space = 1;
1033
1034         AddrSurfInfoIn.numMipLevels = config->info.levels;
1035         AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
1036         AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1037
1038         /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1039          * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1040          * must sample 1D textures as 2D. */
1041         if (config->is_3d)
1042                 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1043         else
1044                 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1045
1046         AddrSurfInfoIn.width = config->info.width;
1047         AddrSurfInfoIn.height = config->info.height;
1048
1049         if (config->is_3d)
1050                 AddrSurfInfoIn.numSlices = config->info.depth;
1051         else if (config->is_cube)
1052                 AddrSurfInfoIn.numSlices = 6;
1053         else
1054                 AddrSurfInfoIn.numSlices = config->info.array_size;
1055
1056         switch (mode) {
1057         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1058                 assert(config->info.samples <= 1);
1059                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1060                 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1061                 break;
1062
1063         case RADEON_SURF_MODE_1D:
1064         case RADEON_SURF_MODE_2D:
1065                 if (surf->flags & RADEON_SURF_IMPORTED) {
1066                         AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1067                         break;
1068                 }
1069
1070                 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
1071                                                     &AddrSurfInfoIn.swizzleMode);
1072                 if (r)
1073                         return r;
1074                 break;
1075
1076         default:
1077                 assert(0);
1078         }
1079
1080         surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1081         surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1082
1083         surf->num_dcc_levels = 0;
1084         surf->surf_size = 0;
1085         surf->dcc_size = 0;
1086         surf->htile_size = 0;
1087         surf->htile_slice_size = 0;
1088         surf->u.gfx9.surf_offset = 0;
1089         surf->u.gfx9.stencil_offset = 0;
1090         surf->u.gfx9.fmask_size = 0;
1091         surf->u.gfx9.cmask_size = 0;
1092
1093         /* Calculate texture layout information. */
1094         r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1095         if (r)
1096                 return r;
1097
1098         /* Calculate texture layout information for stencil. */
1099         if (surf->flags & RADEON_SURF_SBUFFER) {
1100                 AddrSurfInfoIn.bpp = 8;
1101                 AddrSurfInfoIn.flags.depth = 0;
1102                 AddrSurfInfoIn.flags.stencil = 1;
1103
1104                 r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1105                 if (r)
1106                         return r;
1107         }
1108
1109         surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1110
1111         switch (surf->u.gfx9.surf.swizzle_mode) {
1112                 /* S = standard. */
1113                 case ADDR_SW_256B_S:
1114                 case ADDR_SW_4KB_S:
1115                 case ADDR_SW_64KB_S:
1116                 case ADDR_SW_VAR_S:
1117                 case ADDR_SW_64KB_S_T:
1118                 case ADDR_SW_4KB_S_X:
1119                 case ADDR_SW_64KB_S_X:
1120                 case ADDR_SW_VAR_S_X:
1121                         surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1122                         break;
1123
1124                 /* D = display. */
1125                 case ADDR_SW_LINEAR:
1126                 case ADDR_SW_256B_D:
1127                 case ADDR_SW_4KB_D:
1128                 case ADDR_SW_64KB_D:
1129                 case ADDR_SW_VAR_D:
1130                 case ADDR_SW_64KB_D_T:
1131                 case ADDR_SW_4KB_D_X:
1132                 case ADDR_SW_64KB_D_X:
1133                 case ADDR_SW_VAR_D_X:
1134                         surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1135                         break;
1136
1137                 /* R = rotated. */
1138                 case ADDR_SW_256B_R:
1139                 case ADDR_SW_4KB_R:
1140                 case ADDR_SW_64KB_R:
1141                 case ADDR_SW_VAR_R:
1142                 case ADDR_SW_64KB_R_T:
1143                 case ADDR_SW_4KB_R_X:
1144                 case ADDR_SW_64KB_R_X:
1145                 case ADDR_SW_VAR_R_X:
1146                         surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1147                         break;
1148
1149                 /* Z = depth. */
1150                 case ADDR_SW_4KB_Z:
1151                 case ADDR_SW_64KB_Z:
1152                 case ADDR_SW_VAR_Z:
1153                 case ADDR_SW_64KB_Z_T:
1154                 case ADDR_SW_4KB_Z_X:
1155                 case ADDR_SW_64KB_Z_X:
1156                 case ADDR_SW_VAR_Z_X:
1157                         surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1158                         break;
1159
1160                 default:
1161                         assert(0);
1162         }
1163
1164         return 0;
1165 }
1166
1167 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1168                        const struct ac_surf_config *config,
1169                        enum radeon_surf_mode mode,
1170                        struct radeon_surf *surf)
1171 {
1172         int r;
1173
1174         r = surf_config_sanity(config);
1175         if (r)
1176                 return r;
1177
1178         if (info->chip_class >= GFX9)
1179                 return gfx9_compute_surface(addrlib, config, mode, surf);
1180         else
1181                 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1182 }