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ac: compute the size of one DCC slice on GFX8
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/inc/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
53 {
54 return malloc(pInput->sizeInBytes);
55 }
56
57 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
58 {
59 free(pInput->pVirtAddr);
60 return ADDR_OK;
61 }
62
63 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
64 const struct amdgpu_gpu_info *amdinfo,
65 uint64_t *max_alignment)
66 {
67 ADDR_CREATE_INPUT addrCreateInput = {0};
68 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
69 ADDR_REGISTER_VALUE regValue = {0};
70 ADDR_CREATE_FLAGS createFlags = {{0}};
71 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
72 ADDR_E_RETURNCODE addrRet;
73
74 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
75 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
76
77 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
78 createFlags.value = 0;
79
80 addrCreateInput.chipFamily = info->family_id;
81 addrCreateInput.chipRevision = info->chip_external_rev;
82
83 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
84 return NULL;
85
86 if (addrCreateInput.chipFamily >= FAMILY_AI) {
87 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
88 regValue.blockVarSizeLog2 = 0;
89 } else {
90 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
91 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
92
93 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
94 regValue.pTileConfig = amdinfo->gb_tile_mode;
95 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
96 if (addrCreateInput.chipFamily == FAMILY_SI) {
97 regValue.pMacroTileConfig = NULL;
98 regValue.noOfMacroEntries = 0;
99 } else {
100 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
101 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
102 }
103
104 createFlags.useTileIndex = 1;
105 createFlags.useHtileSliceAlign = 1;
106
107 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
108 }
109
110 addrCreateInput.callbacks.allocSysMem = allocSysMem;
111 addrCreateInput.callbacks.freeSysMem = freeSysMem;
112 addrCreateInput.callbacks.debugPrint = 0;
113 addrCreateInput.createFlags = createFlags;
114 addrCreateInput.regValue = regValue;
115
116 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
117 if (addrRet != ADDR_OK)
118 return NULL;
119
120 if (max_alignment) {
121 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
122 if (addrRet == ADDR_OK){
123 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
124 }
125 }
126 return addrCreateOutput.hLib;
127 }
128
129 static int surf_config_sanity(const struct ac_surf_config *config,
130 unsigned flags)
131 {
132 /* FMASK is allocated together with the color surface and can't be
133 * allocated separately.
134 */
135 assert(!(flags & RADEON_SURF_FMASK));
136 if (flags & RADEON_SURF_FMASK)
137 return -EINVAL;
138
139 /* all dimension must be at least 1 ! */
140 if (!config->info.width || !config->info.height || !config->info.depth ||
141 !config->info.array_size || !config->info.levels)
142 return -EINVAL;
143
144 switch (config->info.samples) {
145 case 0:
146 case 1:
147 case 2:
148 case 4:
149 case 8:
150 break;
151 case 16:
152 if (flags & RADEON_SURF_Z_OR_SBUFFER)
153 return -EINVAL;
154 break;
155 default:
156 return -EINVAL;
157 }
158
159 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
160 switch (config->info.storage_samples) {
161 case 0:
162 case 1:
163 case 2:
164 case 4:
165 case 8:
166 break;
167 default:
168 return -EINVAL;
169 }
170 }
171
172 if (config->is_3d && config->info.array_size > 1)
173 return -EINVAL;
174 if (config->is_cube && config->info.depth > 1)
175 return -EINVAL;
176
177 return 0;
178 }
179
180 static int gfx6_compute_level(ADDR_HANDLE addrlib,
181 const struct ac_surf_config *config,
182 struct radeon_surf *surf, bool is_stencil,
183 unsigned level, bool compressed,
184 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
185 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
186 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
187 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
188 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
189 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
190 {
191 struct legacy_surf_level *surf_level;
192 ADDR_E_RETURNCODE ret;
193
194 AddrSurfInfoIn->mipLevel = level;
195 AddrSurfInfoIn->width = u_minify(config->info.width, level);
196 AddrSurfInfoIn->height = u_minify(config->info.height, level);
197
198 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
199 * because GFX9 needs linear alignment of 256 bytes.
200 */
201 if (config->info.levels == 1 &&
202 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
203 AddrSurfInfoIn->bpp &&
204 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
205 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
206
207 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
208 }
209
210 if (config->is_3d)
211 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
212 else if (config->is_cube)
213 AddrSurfInfoIn->numSlices = 6;
214 else
215 AddrSurfInfoIn->numSlices = config->info.array_size;
216
217 if (level > 0) {
218 /* Set the base level pitch. This is needed for calculation
219 * of non-zero levels. */
220 if (is_stencil)
221 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
222 else
223 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
224
225 /* Convert blocks to pixels for compressed formats. */
226 if (compressed)
227 AddrSurfInfoIn->basePitch *= surf->blk_w;
228 }
229
230 ret = AddrComputeSurfaceInfo(addrlib,
231 AddrSurfInfoIn,
232 AddrSurfInfoOut);
233 if (ret != ADDR_OK) {
234 return ret;
235 }
236
237 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
238 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
239 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
240 surf_level->nblk_x = AddrSurfInfoOut->pitch;
241 surf_level->nblk_y = AddrSurfInfoOut->height;
242
243 switch (AddrSurfInfoOut->tileMode) {
244 case ADDR_TM_LINEAR_ALIGNED:
245 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
246 break;
247 case ADDR_TM_1D_TILED_THIN1:
248 surf_level->mode = RADEON_SURF_MODE_1D;
249 break;
250 case ADDR_TM_2D_TILED_THIN1:
251 surf_level->mode = RADEON_SURF_MODE_2D;
252 break;
253 default:
254 assert(0);
255 }
256
257 if (is_stencil)
258 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
259 else
260 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
261
262 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
263
264 /* Clear DCC fields at the beginning. */
265 surf_level->dcc_offset = 0;
266
267 /* The previous level's flag tells us if we can use DCC for this level. */
268 if (AddrSurfInfoIn->flags.dccCompatible &&
269 (level == 0 || AddrDccOut->subLvlCompressible)) {
270 bool prev_level_clearable = level == 0 ||
271 AddrDccOut->dccRamSizeAligned;
272
273 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
274 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
275 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
276 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
277 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
278
279 ret = AddrComputeDccInfo(addrlib,
280 AddrDccIn,
281 AddrDccOut);
282
283 if (ret == ADDR_OK) {
284 surf_level->dcc_offset = surf->dcc_size;
285 surf->num_dcc_levels = level + 1;
286 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
287 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
288
289 /* If the DCC size of a subresource (1 mip level or 1 slice)
290 * is not aligned, the DCC memory layout is not contiguous for
291 * that subresource, which means we can't use fast clear.
292 *
293 * We only do fast clears for whole mipmap levels. If we did
294 * per-slice fast clears, the same restriction would apply.
295 * (i.e. only compute the slice size and see if it's aligned)
296 *
297 * The last level can be non-contiguous and still be clearable
298 * if it's interleaved with the next level that doesn't exist.
299 */
300 if (AddrDccOut->dccRamSizeAligned ||
301 (prev_level_clearable && level == config->info.levels - 1))
302 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
303 else
304 surf_level->dcc_fast_clear_size = 0;
305
306 /* Compute the DCC slice size because addrlib doesn't
307 * provide this info. As DCC memory is linear (each
308 * slice is the same size) it's easy to compute.
309 */
310 surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
311 }
312 }
313
314 /* TC-compatible HTILE. */
315 if (!is_stencil &&
316 AddrSurfInfoIn->flags.depth &&
317 surf_level->mode == RADEON_SURF_MODE_2D &&
318 level == 0) {
319 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
320 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
321 AddrHtileIn->height = AddrSurfInfoOut->height;
322 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
323 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
324 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
325 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
326 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
327 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
328
329 ret = AddrComputeHtileInfo(addrlib,
330 AddrHtileIn,
331 AddrHtileOut);
332
333 if (ret == ADDR_OK) {
334 surf->htile_size = AddrHtileOut->htileBytes;
335 surf->htile_slice_size = AddrHtileOut->sliceSize;
336 surf->htile_alignment = AddrHtileOut->baseAlign;
337 }
338 }
339
340 return 0;
341 }
342
343 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
344 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
345 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
346
347 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
348 const struct radeon_info *info)
349 {
350 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
351
352 if (info->chip_class >= GFX7)
353 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
354 else
355 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
356 }
357
358 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
359 {
360 unsigned index, tileb;
361
362 tileb = 8 * 8 * surf->bpe;
363 tileb = MIN2(surf->u.legacy.tile_split, tileb);
364
365 for (index = 0; tileb > 64; index++)
366 tileb >>= 1;
367
368 assert(index < 16);
369 return index;
370 }
371
372 static bool get_display_flag(const struct ac_surf_config *config,
373 const struct radeon_surf *surf)
374 {
375 unsigned num_channels = config->info.num_channels;
376 unsigned bpe = surf->bpe;
377
378 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
379 surf->flags & RADEON_SURF_SCANOUT &&
380 config->info.samples <= 1 &&
381 surf->blk_w <= 2 && surf->blk_h == 1) {
382 /* subsampled */
383 if (surf->blk_w == 2 && surf->blk_h == 1)
384 return true;
385
386 if (/* RGBA8 or RGBA16F */
387 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
388 /* R5G6B5 or R5G5B5A1 */
389 (bpe == 2 && num_channels >= 3) ||
390 /* C8 palette */
391 (bpe == 1 && num_channels == 1))
392 return true;
393 }
394 return false;
395 }
396
397 /**
398 * This must be called after the first level is computed.
399 *
400 * Copy surface-global settings like pipe/bank config from level 0 surface
401 * computation, and compute tile swizzle.
402 */
403 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
404 const struct radeon_info *info,
405 const struct ac_surf_config *config,
406 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
407 struct radeon_surf *surf)
408 {
409 surf->surf_alignment = csio->baseAlign;
410 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
411 gfx6_set_micro_tile_mode(surf, info);
412
413 /* For 2D modes only. */
414 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
415 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
416 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
417 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
418 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
419 surf->u.legacy.num_banks = csio->pTileInfo->banks;
420 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
421 } else {
422 surf->u.legacy.macro_tile_index = 0;
423 }
424
425 /* Compute tile swizzle. */
426 /* TODO: fix tile swizzle with mipmapping for GFX6 */
427 if ((info->chip_class >= GFX7 || config->info.levels == 1) &&
428 config->info.surf_index &&
429 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
430 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
431 !get_display_flag(config, surf)) {
432 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
433 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
434
435 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
436 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
437
438 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
439 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
440 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
441 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
442 AddrBaseSwizzleIn.tileMode = csio->tileMode;
443
444 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
445 &AddrBaseSwizzleOut);
446 if (r != ADDR_OK)
447 return r;
448
449 assert(AddrBaseSwizzleOut.tileSwizzle <=
450 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
451 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
452 }
453 return 0;
454 }
455
456 static void ac_compute_cmask(const struct radeon_info *info,
457 const struct ac_surf_config *config,
458 struct radeon_surf *surf)
459 {
460 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
461 unsigned num_pipes = info->num_tile_pipes;
462 unsigned cl_width, cl_height;
463
464 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
465 return;
466
467 assert(info->chip_class <= GFX8);
468
469 switch (num_pipes) {
470 case 2:
471 cl_width = 32;
472 cl_height = 16;
473 break;
474 case 4:
475 cl_width = 32;
476 cl_height = 32;
477 break;
478 case 8:
479 cl_width = 64;
480 cl_height = 32;
481 break;
482 case 16: /* Hawaii */
483 cl_width = 64;
484 cl_height = 64;
485 break;
486 default:
487 assert(0);
488 return;
489 }
490
491 unsigned base_align = num_pipes * pipe_interleave_bytes;
492
493 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
494 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
495 unsigned slice_elements = (width * height) / (8*8);
496
497 /* Each element of CMASK is a nibble. */
498 unsigned slice_bytes = slice_elements / 2;
499
500 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
501 if (surf->u.legacy.cmask_slice_tile_max)
502 surf->u.legacy.cmask_slice_tile_max -= 1;
503
504 unsigned num_layers;
505 if (config->is_3d)
506 num_layers = config->info.depth;
507 else if (config->is_cube)
508 num_layers = 6;
509 else
510 num_layers = config->info.array_size;
511
512 surf->cmask_alignment = MAX2(256, base_align);
513 surf->cmask_slice_size = align(slice_bytes, base_align);
514 surf->cmask_size = surf->cmask_slice_size * num_layers;
515 }
516
517 /**
518 * Fill in the tiling information in \p surf based on the given surface config.
519 *
520 * The following fields of \p surf must be initialized by the caller:
521 * blk_w, blk_h, bpe, flags.
522 */
523 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
524 const struct radeon_info *info,
525 const struct ac_surf_config *config,
526 enum radeon_surf_mode mode,
527 struct radeon_surf *surf)
528 {
529 unsigned level;
530 bool compressed;
531 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
532 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
533 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
534 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
535 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
536 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
537 ADDR_TILEINFO AddrTileInfoIn = {0};
538 ADDR_TILEINFO AddrTileInfoOut = {0};
539 int r;
540
541 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
542 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
543 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
544 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
545 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
546 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
547 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
548
549 compressed = surf->blk_w == 4 && surf->blk_h == 4;
550
551 /* MSAA requires 2D tiling. */
552 if (config->info.samples > 1)
553 mode = RADEON_SURF_MODE_2D;
554
555 /* DB doesn't support linear layouts. */
556 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
557 mode < RADEON_SURF_MODE_1D)
558 mode = RADEON_SURF_MODE_1D;
559
560 /* Set the requested tiling mode. */
561 switch (mode) {
562 case RADEON_SURF_MODE_LINEAR_ALIGNED:
563 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
564 break;
565 case RADEON_SURF_MODE_1D:
566 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
567 break;
568 case RADEON_SURF_MODE_2D:
569 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
570 break;
571 default:
572 assert(0);
573 }
574
575 /* The format must be set correctly for the allocation of compressed
576 * textures to work. In other cases, setting the bpp is sufficient.
577 */
578 if (compressed) {
579 switch (surf->bpe) {
580 case 8:
581 AddrSurfInfoIn.format = ADDR_FMT_BC1;
582 break;
583 case 16:
584 AddrSurfInfoIn.format = ADDR_FMT_BC3;
585 break;
586 default:
587 assert(0);
588 }
589 }
590 else {
591 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
592 }
593
594 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
595 MAX2(1, config->info.samples);
596 AddrSurfInfoIn.tileIndex = -1;
597
598 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
599 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
600 MAX2(1, config->info.storage_samples);
601 }
602
603 /* Set the micro tile type. */
604 if (surf->flags & RADEON_SURF_SCANOUT)
605 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
606 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
607 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
608 else
609 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
610
611 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
612 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
613 AddrSurfInfoIn.flags.cube = config->is_cube;
614 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
615 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
616 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
617
618 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
619 * requested, because TC-compatible HTILE requires 2D tiling.
620 */
621 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
622 !AddrSurfInfoIn.flags.fmask &&
623 config->info.samples <= 1 &&
624 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
625
626 /* DCC notes:
627 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
628 * with samples >= 4.
629 * - Mipmapped array textures have low performance (discovered by a closed
630 * driver team).
631 */
632 AddrSurfInfoIn.flags.dccCompatible =
633 info->chip_class >= GFX8 &&
634 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
635 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
636 !compressed &&
637 ((config->info.array_size == 1 && config->info.depth == 1) ||
638 config->info.levels == 1);
639
640 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
641 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
642
643 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
644 * for Z and stencil. This can cause a number of problems which we work
645 * around here:
646 *
647 * - a depth part that is incompatible with mipmapped texturing
648 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
649 * incorrect tiling applied to the stencil part, stencil buffer
650 * memory accesses that go out of bounds) even without mipmapping
651 *
652 * Some piglit tests that are prone to different types of related
653 * failures:
654 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
655 * ./bin/framebuffer-blit-levels {draw,read} stencil
656 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
657 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
658 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
659 */
660 int stencil_tile_idx = -1;
661
662 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
663 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
664 /* Compute stencilTileIdx that is compatible with the (depth)
665 * tileIdx. This degrades the depth surface if necessary to
666 * ensure that a matching stencilTileIdx exists. */
667 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
668
669 /* Keep the depth mip-tail compatible with texturing. */
670 AddrSurfInfoIn.flags.noStencil = 1;
671 }
672
673 /* Set preferred macrotile parameters. This is usually required
674 * for shared resources. This is for 2D tiling only. */
675 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
676 surf->u.legacy.bankw && surf->u.legacy.bankh &&
677 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
678 /* If any of these parameters are incorrect, the calculation
679 * will fail. */
680 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
681 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
682 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
683 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
684 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
685 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
686 AddrSurfInfoIn.flags.opt4Space = 0;
687 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
688
689 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
690 * the tile index, because we are expected to know it if
691 * we know the other parameters.
692 *
693 * This is something that can easily be fixed in Addrlib.
694 * For now, just figure it out here.
695 * Note that only 2D_TILE_THIN1 is handled here.
696 */
697 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
698 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
699
700 if (info->chip_class == GFX6) {
701 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
702 if (surf->bpe == 2)
703 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
704 else
705 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
706 } else {
707 if (surf->bpe == 1)
708 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
709 else if (surf->bpe == 2)
710 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
711 else if (surf->bpe == 4)
712 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
713 else
714 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
715 }
716 } else {
717 /* GFX7 - GFX8 */
718 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
719 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
720 else
721 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
722
723 /* Addrlib doesn't set this if tileIndex is forced like above. */
724 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
725 }
726 }
727
728 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
729 surf->num_dcc_levels = 0;
730 surf->surf_size = 0;
731 surf->dcc_size = 0;
732 surf->dcc_alignment = 1;
733 surf->htile_size = 0;
734 surf->htile_slice_size = 0;
735 surf->htile_alignment = 1;
736
737 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
738 !(surf->flags & RADEON_SURF_ZBUFFER);
739
740 /* Calculate texture layout information. */
741 if (!only_stencil) {
742 for (level = 0; level < config->info.levels; level++) {
743 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
744 &AddrSurfInfoIn, &AddrSurfInfoOut,
745 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
746 if (r)
747 return r;
748
749 if (level > 0)
750 continue;
751
752 /* Check that we actually got a TC-compatible HTILE if
753 * we requested it (only for level 0, since we're not
754 * supporting HTILE on higher mip levels anyway). */
755 assert(AddrSurfInfoOut.tcCompatible ||
756 !AddrSurfInfoIn.flags.tcCompatible ||
757 AddrSurfInfoIn.flags.matchStencilTileCfg);
758
759 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
760 if (!AddrSurfInfoOut.tcCompatible) {
761 AddrSurfInfoIn.flags.tcCompatible = 0;
762 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
763 }
764
765 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
766 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
767 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
768
769 assert(stencil_tile_idx >= 0);
770 }
771
772 r = gfx6_surface_settings(addrlib, info, config,
773 &AddrSurfInfoOut, surf);
774 if (r)
775 return r;
776 }
777 }
778
779 /* Calculate texture layout information for stencil. */
780 if (surf->flags & RADEON_SURF_SBUFFER) {
781 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
782 AddrSurfInfoIn.bpp = 8;
783 AddrSurfInfoIn.flags.depth = 0;
784 AddrSurfInfoIn.flags.stencil = 1;
785 AddrSurfInfoIn.flags.tcCompatible = 0;
786 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
787 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
788
789 for (level = 0; level < config->info.levels; level++) {
790 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
791 &AddrSurfInfoIn, &AddrSurfInfoOut,
792 &AddrDccIn, &AddrDccOut,
793 NULL, NULL);
794 if (r)
795 return r;
796
797 /* DB uses the depth pitch for both stencil and depth. */
798 if (!only_stencil) {
799 if (surf->u.legacy.stencil_level[level].nblk_x !=
800 surf->u.legacy.level[level].nblk_x)
801 surf->u.legacy.stencil_adjusted = true;
802 } else {
803 surf->u.legacy.level[level].nblk_x =
804 surf->u.legacy.stencil_level[level].nblk_x;
805 }
806
807 if (level == 0) {
808 if (only_stencil) {
809 r = gfx6_surface_settings(addrlib, info, config,
810 &AddrSurfInfoOut, surf);
811 if (r)
812 return r;
813 }
814
815 /* For 2D modes only. */
816 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
817 surf->u.legacy.stencil_tile_split =
818 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
819 }
820 }
821 }
822 }
823
824 /* Compute FMASK. */
825 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
826 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
827 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
828 ADDR_TILEINFO fmask_tile_info = {};
829
830 fin.size = sizeof(fin);
831 fout.size = sizeof(fout);
832
833 fin.tileMode = AddrSurfInfoOut.tileMode;
834 fin.pitch = AddrSurfInfoOut.pitch;
835 fin.height = config->info.height;
836 fin.numSlices = AddrSurfInfoIn.numSlices;
837 fin.numSamples = AddrSurfInfoIn.numSamples;
838 fin.numFrags = AddrSurfInfoIn.numFrags;
839 fin.tileIndex = -1;
840 fout.pTileInfo = &fmask_tile_info;
841
842 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
843 if (r)
844 return r;
845
846 surf->fmask_size = fout.fmaskBytes;
847 surf->fmask_alignment = fout.baseAlign;
848 surf->fmask_tile_swizzle = 0;
849
850 surf->u.legacy.fmask.slice_tile_max =
851 (fout.pitch * fout.height) / 64;
852 if (surf->u.legacy.fmask.slice_tile_max)
853 surf->u.legacy.fmask.slice_tile_max -= 1;
854
855 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
856 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
857 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
858 surf->u.legacy.fmask.slice_size = fout.sliceSize;
859
860 /* Compute tile swizzle for FMASK. */
861 if (config->info.fmask_surf_index &&
862 !(surf->flags & RADEON_SURF_SHAREABLE)) {
863 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
864 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
865
866 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
867 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
868
869 /* This counter starts from 1 instead of 0. */
870 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
871 xin.tileIndex = fout.tileIndex;
872 xin.macroModeIndex = fout.macroModeIndex;
873 xin.pTileInfo = fout.pTileInfo;
874 xin.tileMode = fin.tileMode;
875
876 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
877 if (r != ADDR_OK)
878 return r;
879
880 assert(xout.tileSwizzle <=
881 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
882 surf->fmask_tile_swizzle = xout.tileSwizzle;
883 }
884 }
885
886 /* Recalculate the whole DCC miptree size including disabled levels.
887 * This is what addrlib does, but calling addrlib would be a lot more
888 * complicated.
889 */
890 if (surf->dcc_size && config->info.levels > 1) {
891 /* The smallest miplevels that are never compressed by DCC
892 * still read the DCC buffer via TC if the base level uses DCC,
893 * and for some reason the DCC buffer needs to be larger if
894 * the miptree uses non-zero tile_swizzle. Otherwise there are
895 * VM faults.
896 *
897 * "dcc_alignment * 4" was determined by trial and error.
898 */
899 surf->dcc_size = align64(surf->surf_size >> 8,
900 surf->dcc_alignment * 4);
901 }
902
903 /* Make sure HTILE covers the whole miptree, because the shader reads
904 * TC-compatible HTILE even for levels where it's disabled by DB.
905 */
906 if (surf->htile_size && config->info.levels > 1 &&
907 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
908 /* MSAA can't occur with levels > 1, so ignore the sample count. */
909 const unsigned total_pixels = surf->surf_size / surf->bpe;
910 const unsigned htile_block_size = 8 * 8;
911 const unsigned htile_element_size = 4;
912
913 surf->htile_size = (total_pixels / htile_block_size) *
914 htile_element_size;
915 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
916 }
917
918 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
919 surf->is_displayable = surf->is_linear ||
920 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
921 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
922
923 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
924 * used at the same time. This case is not currently expected to occur
925 * because we don't use rotated. Enforce this restriction on all chips
926 * to facilitate testing.
927 */
928 if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
929 assert(!"rotate micro tile mode is unsupported");
930 return ADDR_ERROR;
931 }
932
933 ac_compute_cmask(info, config, surf);
934 return 0;
935 }
936
937 /* This is only called when expecting a tiled layout. */
938 static int
939 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
940 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
941 bool is_fmask, AddrSwizzleMode *swizzle_mode)
942 {
943 ADDR_E_RETURNCODE ret;
944 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
945 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
946
947 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
948 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
949
950 sin.flags = in->flags;
951 sin.resourceType = in->resourceType;
952 sin.format = in->format;
953 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
954 /* TODO: We could allow some of these: */
955 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
956 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
957 sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
958 sin.bpp = in->bpp;
959 sin.width = in->width;
960 sin.height = in->height;
961 sin.numSlices = in->numSlices;
962 sin.numMipLevels = in->numMipLevels;
963 sin.numSamples = in->numSamples;
964 sin.numFrags = in->numFrags;
965
966 if (is_fmask) {
967 sin.flags.display = 0;
968 sin.flags.color = 0;
969 sin.flags.fmask = 1;
970 }
971
972 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
973 if (ret != ADDR_OK)
974 return ret;
975
976 *swizzle_mode = sout.swizzleMode;
977 return 0;
978 }
979
980 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
981 const struct radeon_info *info,
982 const struct ac_surf_config *config,
983 struct radeon_surf *surf, bool compressed,
984 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
985 {
986 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
987 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
988 ADDR_E_RETURNCODE ret;
989
990 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
991 out.pMipInfo = mip_info;
992
993 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
994 if (ret != ADDR_OK)
995 return ret;
996
997 if (in->flags.stencil) {
998 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
999 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1000 out.mipChainPitch - 1;
1001 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1002 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1003 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1004 return 0;
1005 }
1006
1007 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1008 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1009 out.mipChainPitch - 1;
1010
1011 /* CMASK fast clear uses these even if FMASK isn't allocated.
1012 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1013 */
1014 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1015 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1016
1017 surf->u.gfx9.surf_slice_size = out.sliceSize;
1018 surf->u.gfx9.surf_pitch = out.pitch;
1019 surf->u.gfx9.surf_height = out.height;
1020 surf->surf_size = out.surfSize;
1021 surf->surf_alignment = out.baseAlign;
1022
1023 if (in->swizzleMode == ADDR_SW_LINEAR) {
1024 for (unsigned i = 0; i < in->numMipLevels; i++)
1025 surf->u.gfx9.offset[i] = mip_info[i].offset;
1026 }
1027
1028 if (in->flags.depth) {
1029 assert(in->swizzleMode != ADDR_SW_LINEAR);
1030
1031 /* HTILE */
1032 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1033 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1034
1035 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1036 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1037
1038 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1039 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1040 hin.depthFlags = in->flags;
1041 hin.swizzleMode = in->swizzleMode;
1042 hin.unalignedWidth = in->width;
1043 hin.unalignedHeight = in->height;
1044 hin.numSlices = in->numSlices;
1045 hin.numMipLevels = in->numMipLevels;
1046 hin.firstMipIdInTail = out.firstMipIdInTail;
1047
1048 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1049 if (ret != ADDR_OK)
1050 return ret;
1051
1052 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1053 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1054 surf->htile_size = hout.htileBytes;
1055 surf->htile_slice_size = hout.sliceSize;
1056 surf->htile_alignment = hout.baseAlign;
1057 } else {
1058 /* Compute tile swizzle for the color surface.
1059 * All *_X and *_T modes can use the swizzle.
1060 */
1061 if (config->info.surf_index &&
1062 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1063 !out.mipChainInTail &&
1064 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1065 !in->flags.display) {
1066 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1067 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1068
1069 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1070 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1071
1072 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1073 xin.flags = in->flags;
1074 xin.swizzleMode = in->swizzleMode;
1075 xin.resourceType = in->resourceType;
1076 xin.format = in->format;
1077 xin.numSamples = in->numSamples;
1078 xin.numFrags = in->numFrags;
1079
1080 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1081 if (ret != ADDR_OK)
1082 return ret;
1083
1084 assert(xout.pipeBankXor <=
1085 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1086 surf->tile_swizzle = xout.pipeBankXor;
1087 }
1088
1089 /* DCC */
1090 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1091 !compressed &&
1092 in->swizzleMode != ADDR_SW_LINEAR) {
1093 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1094 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1095 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1096
1097 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1098 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1099 dout.pMipInfo = meta_mip_info;
1100
1101 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1102 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1103 din.colorFlags = in->flags;
1104 din.resourceType = in->resourceType;
1105 din.swizzleMode = in->swizzleMode;
1106 din.bpp = in->bpp;
1107 din.unalignedWidth = in->width;
1108 din.unalignedHeight = in->height;
1109 din.numSlices = in->numSlices;
1110 din.numFrags = in->numFrags;
1111 din.numMipLevels = in->numMipLevels;
1112 din.dataSurfaceSize = out.surfSize;
1113 din.firstMipIdInTail = out.firstMipIdInTail;
1114
1115 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1116 if (ret != ADDR_OK)
1117 return ret;
1118
1119 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1120 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1121 surf->dcc_size = dout.dccRamSize;
1122 surf->dcc_alignment = dout.dccRamBaseAlign;
1123 surf->num_dcc_levels = in->numMipLevels;
1124
1125 /* Disable DCC for levels that are in the mip tail.
1126 *
1127 * There are two issues that this is intended to
1128 * address:
1129 *
1130 * 1. Multiple mip levels may share a cache line. This
1131 * can lead to corruption when switching between
1132 * rendering to different mip levels because the
1133 * RBs don't maintain coherency.
1134 *
1135 * 2. Texturing with metadata after rendering sometimes
1136 * fails with corruption, probably for a similar
1137 * reason.
1138 *
1139 * Working around these issues for all levels in the
1140 * mip tail may be overly conservative, but it's what
1141 * Vulkan does.
1142 *
1143 * Alternative solutions that also work but are worse:
1144 * - Disable DCC entirely.
1145 * - Flush TC L2 after rendering.
1146 */
1147 for (unsigned i = 0; i < in->numMipLevels; i++) {
1148 if (meta_mip_info[i].inMiptail) {
1149 surf->num_dcc_levels = i;
1150 break;
1151 }
1152 }
1153
1154 if (!surf->num_dcc_levels)
1155 surf->dcc_size = 0;
1156
1157 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1158 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1159 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1160
1161 /* Compute displayable DCC. */
1162 if (in->flags.display &&
1163 surf->num_dcc_levels &&
1164 info->use_display_dcc_with_retile_blit) {
1165 /* Compute displayable DCC info. */
1166 din.dccKeyFlags.pipeAligned = 0;
1167 din.dccKeyFlags.rbAligned = 0;
1168
1169 assert(din.numSlices == 1);
1170 assert(din.numMipLevels == 1);
1171 assert(din.numFrags == 1);
1172 assert(surf->tile_swizzle == 0);
1173 assert(surf->u.gfx9.dcc.pipe_aligned ||
1174 surf->u.gfx9.dcc.rb_aligned);
1175
1176 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1177 if (ret != ADDR_OK)
1178 return ret;
1179
1180 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1181 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1182 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1183 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1184
1185 /* Compute address mapping from non-displayable to displayable DCC. */
1186 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
1187 addrin.size = sizeof(addrin);
1188 addrin.colorFlags.color = 1;
1189 addrin.swizzleMode = din.swizzleMode;
1190 addrin.resourceType = din.resourceType;
1191 addrin.bpp = din.bpp;
1192 addrin.unalignedWidth = din.unalignedWidth;
1193 addrin.unalignedHeight = din.unalignedHeight;
1194 addrin.numSlices = 1;
1195 addrin.numMipLevels = 1;
1196 addrin.numFrags = 1;
1197
1198 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
1199 addrout.size = sizeof(addrout);
1200
1201 surf->u.gfx9.dcc_retile_num_elements =
1202 DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
1203 DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
1204 /* Align the size to 4 (for the compute shader). */
1205 surf->u.gfx9.dcc_retile_num_elements =
1206 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1207
1208 surf->u.gfx9.dcc_retile_map =
1209 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1210 if (!surf->u.gfx9.dcc_retile_map)
1211 return ADDR_OUTOFMEMORY;
1212
1213 unsigned index = 0;
1214 surf->u.gfx9.dcc_retile_use_uint16 = true;
1215
1216 for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
1217 addrin.y = y;
1218
1219 for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
1220 addrin.x = x;
1221
1222 /* Compute src DCC address */
1223 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1224 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1225 addrout.addr = 0;
1226
1227 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1228 if (ret != ADDR_OK)
1229 return ret;
1230
1231 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1232 if (addrout.addr > USHRT_MAX)
1233 surf->u.gfx9.dcc_retile_use_uint16 = false;
1234
1235 /* Compute dst DCC address */
1236 addrin.dccKeyFlags.pipeAligned = 0;
1237 addrin.dccKeyFlags.rbAligned = 0;
1238 addrout.addr = 0;
1239
1240 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1241 if (ret != ADDR_OK)
1242 return ret;
1243
1244 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1245 if (addrout.addr > USHRT_MAX)
1246 surf->u.gfx9.dcc_retile_use_uint16 = false;
1247
1248 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1249 index++;
1250 }
1251 }
1252 /* Fill the remaining pairs with the last one (for the compute shader). */
1253 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1254 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1255 }
1256 }
1257
1258 /* FMASK */
1259 if (in->numSamples > 1) {
1260 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1261 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1262
1263 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1264 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1265
1266 ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
1267 true, &fin.swizzleMode);
1268 if (ret != ADDR_OK)
1269 return ret;
1270
1271 fin.unalignedWidth = in->width;
1272 fin.unalignedHeight = in->height;
1273 fin.numSlices = in->numSlices;
1274 fin.numSamples = in->numSamples;
1275 fin.numFrags = in->numFrags;
1276
1277 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1278 if (ret != ADDR_OK)
1279 return ret;
1280
1281 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1282 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1283 surf->fmask_size = fout.fmaskBytes;
1284 surf->fmask_alignment = fout.baseAlign;
1285
1286 /* Compute tile swizzle for the FMASK surface. */
1287 if (config->info.fmask_surf_index &&
1288 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1289 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1290 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1291 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1292
1293 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1294 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1295
1296 /* This counter starts from 1 instead of 0. */
1297 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1298 xin.flags = in->flags;
1299 xin.swizzleMode = fin.swizzleMode;
1300 xin.resourceType = in->resourceType;
1301 xin.format = in->format;
1302 xin.numSamples = in->numSamples;
1303 xin.numFrags = in->numFrags;
1304
1305 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1306 if (ret != ADDR_OK)
1307 return ret;
1308
1309 assert(xout.pipeBankXor <=
1310 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1311 surf->fmask_tile_swizzle = xout.pipeBankXor;
1312 }
1313 }
1314
1315 /* CMASK */
1316 if (in->swizzleMode != ADDR_SW_LINEAR) {
1317 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1318 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1319
1320 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1321 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1322
1323 if (in->numSamples > 1) {
1324 /* FMASK is always aligned. */
1325 cin.cMaskFlags.pipeAligned = 1;
1326 cin.cMaskFlags.rbAligned = 1;
1327 } else {
1328 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1329 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1330 }
1331 cin.colorFlags = in->flags;
1332 cin.resourceType = in->resourceType;
1333 cin.unalignedWidth = in->width;
1334 cin.unalignedHeight = in->height;
1335 cin.numSlices = in->numSlices;
1336
1337 if (in->numSamples > 1)
1338 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1339 else
1340 cin.swizzleMode = in->swizzleMode;
1341
1342 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1343 if (ret != ADDR_OK)
1344 return ret;
1345
1346 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1347 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1348 surf->cmask_size = cout.cmaskBytes;
1349 surf->cmask_alignment = cout.baseAlign;
1350 }
1351 }
1352
1353 return 0;
1354 }
1355
1356 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1357 const struct radeon_info *info,
1358 const struct ac_surf_config *config,
1359 enum radeon_surf_mode mode,
1360 struct radeon_surf *surf)
1361 {
1362 bool compressed;
1363 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1364 int r;
1365
1366 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1367
1368 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1369
1370 /* The format must be set correctly for the allocation of compressed
1371 * textures to work. In other cases, setting the bpp is sufficient. */
1372 if (compressed) {
1373 switch (surf->bpe) {
1374 case 8:
1375 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1376 break;
1377 case 16:
1378 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1379 break;
1380 default:
1381 assert(0);
1382 }
1383 } else {
1384 switch (surf->bpe) {
1385 case 1:
1386 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1387 AddrSurfInfoIn.format = ADDR_FMT_8;
1388 break;
1389 case 2:
1390 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1391 !(surf->flags & RADEON_SURF_SBUFFER));
1392 AddrSurfInfoIn.format = ADDR_FMT_16;
1393 break;
1394 case 4:
1395 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1396 !(surf->flags & RADEON_SURF_SBUFFER));
1397 AddrSurfInfoIn.format = ADDR_FMT_32;
1398 break;
1399 case 8:
1400 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1401 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1402 break;
1403 case 12:
1404 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1405 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1406 break;
1407 case 16:
1408 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1409 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1410 break;
1411 default:
1412 assert(0);
1413 }
1414 AddrSurfInfoIn.bpp = surf->bpe * 8;
1415 }
1416
1417 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1418 AddrSurfInfoIn.flags.color = is_color_surface &&
1419 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1420 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1421 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1422 /* flags.texture currently refers to TC-compatible HTILE */
1423 AddrSurfInfoIn.flags.texture = is_color_surface ||
1424 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1425 AddrSurfInfoIn.flags.opt4space = 1;
1426
1427 AddrSurfInfoIn.numMipLevels = config->info.levels;
1428 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1429 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1430
1431 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1432 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1433
1434 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1435 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1436 * must sample 1D textures as 2D. */
1437 if (config->is_3d)
1438 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1439 else
1440 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1441
1442 AddrSurfInfoIn.width = config->info.width;
1443 AddrSurfInfoIn.height = config->info.height;
1444
1445 if (config->is_3d)
1446 AddrSurfInfoIn.numSlices = config->info.depth;
1447 else if (config->is_cube)
1448 AddrSurfInfoIn.numSlices = 6;
1449 else
1450 AddrSurfInfoIn.numSlices = config->info.array_size;
1451
1452 /* This is propagated to HTILE/DCC/CMASK. */
1453 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1454 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1455
1456 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1457 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1458 *
1459 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1460 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1461 * after rendering, so PIPE_ALIGNED=1 is recommended.
1462 */
1463 if (info->use_display_dcc_unaligned && is_color_surface &&
1464 AddrSurfInfoIn.flags.display) {
1465 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1466 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1467 }
1468
1469 switch (mode) {
1470 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1471 assert(config->info.samples <= 1);
1472 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1473 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1474 break;
1475
1476 case RADEON_SURF_MODE_1D:
1477 case RADEON_SURF_MODE_2D:
1478 if (surf->flags & RADEON_SURF_IMPORTED) {
1479 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1480 break;
1481 }
1482
1483 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1484 false, &AddrSurfInfoIn.swizzleMode);
1485 if (r)
1486 return r;
1487 break;
1488
1489 default:
1490 assert(0);
1491 }
1492
1493 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1494 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1495
1496 surf->num_dcc_levels = 0;
1497 surf->surf_size = 0;
1498 surf->fmask_size = 0;
1499 surf->dcc_size = 0;
1500 surf->htile_size = 0;
1501 surf->htile_slice_size = 0;
1502 surf->u.gfx9.surf_offset = 0;
1503 surf->u.gfx9.stencil_offset = 0;
1504 surf->cmask_size = 0;
1505 surf->u.gfx9.dcc_retile_use_uint16 = false;
1506 surf->u.gfx9.dcc_retile_num_elements = 0;
1507 surf->u.gfx9.dcc_retile_map = NULL;
1508
1509 /* Calculate texture layout information. */
1510 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1511 &AddrSurfInfoIn);
1512 if (r)
1513 goto error;
1514
1515 /* Calculate texture layout information for stencil. */
1516 if (surf->flags & RADEON_SURF_SBUFFER) {
1517 AddrSurfInfoIn.flags.stencil = 1;
1518 AddrSurfInfoIn.bpp = 8;
1519 AddrSurfInfoIn.format = ADDR_FMT_8;
1520
1521 if (!AddrSurfInfoIn.flags.depth) {
1522 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1523 false, &AddrSurfInfoIn.swizzleMode);
1524 if (r)
1525 goto error;
1526 } else
1527 AddrSurfInfoIn.flags.depth = 0;
1528
1529 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1530 &AddrSurfInfoIn);
1531 if (r)
1532 goto error;
1533 }
1534
1535 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1536
1537 /* Query whether the surface is displayable. */
1538 bool displayable = false;
1539 if (!config->is_3d && !config->is_cube) {
1540 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1541 surf->bpe * 8, &displayable);
1542 if (r)
1543 goto error;
1544
1545 /* Display needs unaligned DCC. */
1546 if (info->use_display_dcc_unaligned &&
1547 surf->num_dcc_levels &&
1548 (surf->u.gfx9.dcc.pipe_aligned ||
1549 surf->u.gfx9.dcc.rb_aligned))
1550 displayable = false;
1551 }
1552 surf->is_displayable = displayable;
1553
1554 switch (surf->u.gfx9.surf.swizzle_mode) {
1555 /* S = standard. */
1556 case ADDR_SW_256B_S:
1557 case ADDR_SW_4KB_S:
1558 case ADDR_SW_64KB_S:
1559 case ADDR_SW_VAR_S:
1560 case ADDR_SW_64KB_S_T:
1561 case ADDR_SW_4KB_S_X:
1562 case ADDR_SW_64KB_S_X:
1563 case ADDR_SW_VAR_S_X:
1564 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1565 break;
1566
1567 /* D = display. */
1568 case ADDR_SW_LINEAR:
1569 case ADDR_SW_256B_D:
1570 case ADDR_SW_4KB_D:
1571 case ADDR_SW_64KB_D:
1572 case ADDR_SW_VAR_D:
1573 case ADDR_SW_64KB_D_T:
1574 case ADDR_SW_4KB_D_X:
1575 case ADDR_SW_64KB_D_X:
1576 case ADDR_SW_VAR_D_X:
1577 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1578 break;
1579
1580 /* R = rotated. */
1581 case ADDR_SW_256B_R:
1582 case ADDR_SW_4KB_R:
1583 case ADDR_SW_64KB_R:
1584 case ADDR_SW_VAR_R:
1585 case ADDR_SW_64KB_R_T:
1586 case ADDR_SW_4KB_R_X:
1587 case ADDR_SW_64KB_R_X:
1588 case ADDR_SW_VAR_R_X:
1589 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1590 * used at the same time. This case is not currently expected to occur
1591 * because we don't use rotated. Enforce this restriction on all chips
1592 * to facilitate testing.
1593 */
1594 assert(!"rotate micro tile mode is unsupported");
1595 r = ADDR_ERROR;
1596 goto error;
1597
1598 /* Z = depth. */
1599 case ADDR_SW_4KB_Z:
1600 case ADDR_SW_64KB_Z:
1601 case ADDR_SW_VAR_Z:
1602 case ADDR_SW_64KB_Z_T:
1603 case ADDR_SW_4KB_Z_X:
1604 case ADDR_SW_64KB_Z_X:
1605 case ADDR_SW_VAR_Z_X:
1606 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1607 break;
1608
1609 default:
1610 assert(0);
1611 }
1612
1613 return 0;
1614
1615 error:
1616 free(surf->u.gfx9.dcc_retile_map);
1617 surf->u.gfx9.dcc_retile_map = NULL;
1618 return r;
1619 }
1620
1621 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1622 const struct ac_surf_config *config,
1623 enum radeon_surf_mode mode,
1624 struct radeon_surf *surf)
1625 {
1626 int r;
1627
1628 r = surf_config_sanity(config, surf->flags);
1629 if (r)
1630 return r;
1631
1632 if (info->chip_class >= GFX9)
1633 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1634 else
1635 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1636 }