src/amd/common/ac_surface.c

   1 /*
   2  * Copyright © 2011 Red Hat All Rights Reserved.
   3  * Copyright © 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 #include "ac_surface.h"
  29 #include "amd_family.h"
  30 #include "amdgpu_id.h"
  31 #include "ac_gpu_info.h"
  32 #include "util/macros.h"
  33 #include "util/u_atomic.h"
  34 #include "util/u_math.h"
  35
  36 #include <errno.h>
  37 #include <stdio.h>
  38 #include <stdlib.h>
  39 #include <amdgpu.h>
  40 #include <amdgpu_drm.h>
  41
  42 #include "addrlib/addrinterface.h"
  43
  44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  46 #endif
  47
  48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
  49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
  50 #endif
  51
  52 static void addrlib_family_rev_id(enum radeon_family family,
  53                                   unsigned *addrlib_family,
  54                                   unsigned *addrlib_revid)
  55 {
  56         switch (family) {
  57         case CHIP_TAHITI:
  58                 *addrlib_family = FAMILY_SI;
  59                 *addrlib_revid = SI_TAHITI_P_A0;
  60                 break;
  61         case CHIP_PITCAIRN:
  62                 *addrlib_family = FAMILY_SI;
  63                 *addrlib_revid = SI_PITCAIRN_PM_A0;
  64                 break;
  65         case CHIP_VERDE:
  66                 *addrlib_family = FAMILY_SI;
  67                 *addrlib_revid = SI_CAPEVERDE_M_A0;
  68                 break;
  69         case CHIP_OLAND:
  70                 *addrlib_family = FAMILY_SI;
  71                 *addrlib_revid = SI_OLAND_M_A0;
  72                 break;
  73         case CHIP_HAINAN:
  74                 *addrlib_family = FAMILY_SI;
  75                 *addrlib_revid = SI_HAINAN_V_A0;
  76                 break;
  77         case CHIP_BONAIRE:
  78                 *addrlib_family = FAMILY_CI;
  79                 *addrlib_revid = CI_BONAIRE_M_A0;
  80                 break;
  81         case CHIP_KAVERI:
  82                 *addrlib_family = FAMILY_KV;
  83                 *addrlib_revid = KV_SPECTRE_A0;
  84                 break;
  85         case CHIP_KABINI:
  86                 *addrlib_family = FAMILY_KV;
  87                 *addrlib_revid = KB_KALINDI_A0;
  88                 break;
  89         case CHIP_HAWAII:
  90                 *addrlib_family = FAMILY_CI;
  91                 *addrlib_revid = CI_HAWAII_P_A0;
  92                 break;
  93         case CHIP_MULLINS:
  94                 *addrlib_family = FAMILY_KV;
  95                 *addrlib_revid = ML_GODAVARI_A0;
  96                 break;
  97         case CHIP_TONGA:
  98                 *addrlib_family = FAMILY_VI;
  99                 *addrlib_revid = VI_TONGA_P_A0;
 100                 break;
 101         case CHIP_ICELAND:
 102                 *addrlib_family = FAMILY_VI;
 103                 *addrlib_revid = VI_ICELAND_M_A0;
 104                 break;
 105         case CHIP_CARRIZO:
 106                 *addrlib_family = FAMILY_CZ;
 107                 *addrlib_revid = CARRIZO_A0;
 108                 break;
 109         case CHIP_STONEY:
 110                 *addrlib_family = FAMILY_CZ;
 111                 *addrlib_revid = STONEY_A0;
 112                 break;
 113         case CHIP_FIJI:
 114                 *addrlib_family = FAMILY_VI;
 115                 *addrlib_revid = VI_FIJI_P_A0;
 116                 break;
 117         case CHIP_POLARIS10:
 118                 *addrlib_family = FAMILY_VI;
 119                 *addrlib_revid = VI_POLARIS10_P_A0;
 120                 break;
 121         case CHIP_POLARIS11:
 122                 *addrlib_family = FAMILY_VI;
 123                 *addrlib_revid = VI_POLARIS11_M_A0;
 124                 break;
 125         case CHIP_POLARIS12:
 126                 *addrlib_family = FAMILY_VI;
 127                 *addrlib_revid = VI_POLARIS12_V_A0;
 128                 break;
 129         case CHIP_VEGA10:
 130                 *addrlib_family = FAMILY_AI;
 131                 *addrlib_revid = AI_VEGA10_P_A0;
 132                 break;
 133         case CHIP_RAVEN:
 134                 *addrlib_family = FAMILY_RV;
 135                 *addrlib_revid = RAVEN_A0;
 136                 break;
 137         default:
 138                 fprintf(stderr, "amdgpu: Unknown family.\n");
 139         }
 140 }
 141
 142 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
 143 {
 144         return malloc(pInput->sizeInBytes);
 145 }
 146
 147 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
 148 {
 149         free(pInput->pVirtAddr);
 150         return ADDR_OK;
 151 }
 152
 153 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 154                                const struct amdgpu_gpu_info *amdinfo,
 155                                uint64_t *max_alignment)
 156 {
 157         ADDR_CREATE_INPUT addrCreateInput = {0};
 158         ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 159         ADDR_REGISTER_VALUE regValue = {0};
 160         ADDR_CREATE_FLAGS createFlags = {{0}};
 161         ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
 162         ADDR_E_RETURNCODE addrRet;
 163
 164         addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 165         addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 166
 167         regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
 168         createFlags.value = 0;
 169
 170         addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
 171         if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
 172                 return NULL;
 173
 174         if (addrCreateInput.chipFamily >= FAMILY_AI) {
 175                 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
 176                 regValue.blockVarSizeLog2 = 0;
 177         } else {
 178                 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
 179                 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
 180
 181                 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
 182                 regValue.pTileConfig = amdinfo->gb_tile_mode;
 183                 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
 184                 if (addrCreateInput.chipFamily == FAMILY_SI) {
 185                         regValue.pMacroTileConfig = NULL;
 186                         regValue.noOfMacroEntries = 0;
 187                 } else {
 188                         regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
 189                         regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
 190                 }
 191
 192                 createFlags.useTileIndex = 1;
 193                 createFlags.useHtileSliceAlign = 1;
 194
 195                 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 196         }
 197
 198         addrCreateInput.callbacks.allocSysMem = allocSysMem;
 199         addrCreateInput.callbacks.freeSysMem = freeSysMem;
 200         addrCreateInput.callbacks.debugPrint = 0;
 201         addrCreateInput.createFlags = createFlags;
 202         addrCreateInput.regValue = regValue;
 203
 204         addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 205         if (addrRet != ADDR_OK)
 206                 return NULL;
 207
 208         if (max_alignment) {
 209                 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
 210                 if (addrRet == ADDR_OK){
 211                         *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
 212                 }
 213         }
 214         return addrCreateOutput.hLib;
 215 }
 216
 217 static int surf_config_sanity(const struct ac_surf_config *config)
 218 {
 219         /* all dimension must be at least 1 ! */
 220         if (!config->info.width || !config->info.height || !config->info.depth ||
 221             !config->info.array_size || !config->info.levels)
 222                 return -EINVAL;
 223
 224         switch (config->info.samples) {
 225         case 0:
 226         case 1:
 227         case 2:
 228         case 4:
 229         case 8:
 230                 break;
 231         default:
 232                 return -EINVAL;
 233         }
 234
 235         if (config->is_3d && config->info.array_size > 1)
 236                 return -EINVAL;
 237         if (config->is_cube && config->info.depth > 1)
 238                 return -EINVAL;
 239
 240         return 0;
 241 }
 242
 243 static int gfx6_compute_level(ADDR_HANDLE addrlib,
 244                               const struct ac_surf_config *config,
 245                               struct radeon_surf *surf, bool is_stencil,
 246                               unsigned level, bool compressed,
 247                               ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 248                               ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 249                               ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 250                               ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
 251                               ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
 252                               ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
 253 {
 254         struct legacy_surf_level *surf_level;
 255         ADDR_E_RETURNCODE ret;
 256
 257         AddrSurfInfoIn->mipLevel = level;
 258         AddrSurfInfoIn->width = u_minify(config->info.width, level);
 259         AddrSurfInfoIn->height = u_minify(config->info.height, level);
 260
 261         /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
 262          * because GFX9 needs linear alignment of 256 bytes.
 263          */
 264         if (config->info.levels == 1 &&
 265             AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
 266             AddrSurfInfoIn->bpp) {
 267                 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
 268
 269                 assert(util_is_power_of_two(AddrSurfInfoIn->bpp));
 270                 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
 271         }
 272
 273         if (config->is_3d)
 274                 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
 275         else if (config->is_cube)
 276                 AddrSurfInfoIn->numSlices = 6;
 277         else
 278                 AddrSurfInfoIn->numSlices = config->info.array_size;
 279
 280         if (level > 0) {
 281                 /* Set the base level pitch. This is needed for calculation
 282                  * of non-zero levels. */
 283                 if (is_stencil)
 284                         AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
 285                 else
 286                         AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
 287
 288                 /* Convert blocks to pixels for compressed formats. */
 289                 if (compressed)
 290                         AddrSurfInfoIn->basePitch *= surf->blk_w;
 291         }
 292
 293         ret = AddrComputeSurfaceInfo(addrlib,
 294                                      AddrSurfInfoIn,
 295                                      AddrSurfInfoOut);
 296         if (ret != ADDR_OK) {
 297                 return ret;
 298         }
 299
 300         surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
 301         surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
 302         surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 303         surf_level->nblk_x = AddrSurfInfoOut->pitch;
 304         surf_level->nblk_y = AddrSurfInfoOut->height;
 305
 306         switch (AddrSurfInfoOut->tileMode) {
 307         case ADDR_TM_LINEAR_ALIGNED:
 308                 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 309                 break;
 310         case ADDR_TM_1D_TILED_THIN1:
 311                 surf_level->mode = RADEON_SURF_MODE_1D;
 312                 break;
 313         case ADDR_TM_2D_TILED_THIN1:
 314                 surf_level->mode = RADEON_SURF_MODE_2D;
 315                 break;
 316         default:
 317                 assert(0);
 318         }
 319
 320         if (is_stencil)
 321                 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 322         else
 323                 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
 324
 325         surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 326
 327         /* Clear DCC fields at the beginning. */
 328         surf_level->dcc_offset = 0;
 329
 330         /* The previous level's flag tells us if we can use DCC for this level. */
 331         if (AddrSurfInfoIn->flags.dccCompatible &&
 332             (level == 0 || AddrDccOut->subLvlCompressible)) {
 333                 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 334                 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 335                 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 336                 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 337                 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 338
 339                 ret = AddrComputeDccInfo(addrlib,
 340                                          AddrDccIn,
 341                                          AddrDccOut);
 342
 343                 if (ret == ADDR_OK) {
 344                         surf_level->dcc_offset = surf->dcc_size;
 345                         surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 346                         surf->num_dcc_levels = level + 1;
 347                         surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 348                         surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 349                 }
 350         }
 351
 352         /* TC-compatible HTILE. */
 353         if (!is_stencil &&
 354             AddrSurfInfoIn->flags.depth &&
 355             surf_level->mode == RADEON_SURF_MODE_2D &&
 356             level == 0) {
 357                 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
 358                 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
 359                 AddrHtileIn->height = AddrSurfInfoOut->height;
 360                 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
 361                 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
 362                 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
 363                 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
 364                 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
 365                 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 366
 367                 ret = AddrComputeHtileInfo(addrlib,
 368                                            AddrHtileIn,
 369                                            AddrHtileOut);
 370
 371                 if (ret == ADDR_OK) {
 372                         surf->htile_size = AddrHtileOut->htileBytes;
 373                         surf->htile_slice_size = AddrHtileOut->sliceSize;
 374                         surf->htile_alignment = AddrHtileOut->baseAlign;
 375                 }
 376         }
 377
 378         return 0;
 379 }
 380
 381 #define   G_009910_MICRO_TILE_MODE(x)          (((x) >> 0) & 0x03)
 382 #define   G_009910_MICRO_TILE_MODE_NEW(x)      (((x) >> 22) & 0x07)
 383
 384 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
 385                                      const struct radeon_info *info)
 386 {
 387         uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
 388
 389         if (info->chip_class >= CIK)
 390                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 391         else
 392                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 393 }
 394
 395 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 396 {
 397         unsigned index, tileb;
 398
 399         tileb = 8 * 8 * surf->bpe;
 400         tileb = MIN2(surf->u.legacy.tile_split, tileb);
 401
 402         for (index = 0; tileb > 64; index++)
 403                 tileb >>= 1;
 404
 405         assert(index < 16);
 406         return index;
 407 }
 408
 409 /**
 410  * Copy surface-global settings like pipe/bank config from level 0 surface
 411  * computation.
 412  */
 413 static void gfx6_surface_settings(const struct radeon_info* info,
 414                                   ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
 415                                   struct radeon_surf *surf)
 416 {
 417         surf->surf_alignment = csio->baseAlign;
 418         surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
 419         gfx6_set_micro_tile_mode(surf, info);
 420
 421         /* For 2D modes only. */
 422         if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
 423                 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
 424                 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
 425                 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
 426                 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
 427                 surf->u.legacy.num_banks = csio->pTileInfo->banks;
 428                 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
 429         } else {
 430                 surf->u.legacy.macro_tile_index = 0;
 431         }
 432 }
 433
 434 /**
 435  * Fill in the tiling information in \p surf based on the given surface config.
 436  *
 437  * The following fields of \p surf must be initialized by the caller:
 438  * blk_w, blk_h, bpe, flags.
 439  */
 440 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 441                                 const struct radeon_info *info,
 442                                 const struct ac_surf_config *config,
 443                                 enum radeon_surf_mode mode,
 444                                 struct radeon_surf *surf)
 445 {
 446         unsigned level;
 447         bool compressed;
 448         ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 449         ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 450         ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 451         ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 452         ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 453         ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 454         ADDR_TILEINFO AddrTileInfoIn = {0};
 455         ADDR_TILEINFO AddrTileInfoOut = {0};
 456         int r;
 457
 458         AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 459         AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 460         AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 461         AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 462         AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
 463         AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
 464         AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 465
 466         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 467
 468         /* MSAA and FMASK require 2D tiling. */
 469         if (config->info.samples > 1 ||
 470             (surf->flags & RADEON_SURF_FMASK))
 471                 mode = RADEON_SURF_MODE_2D;
 472
 473         /* DB doesn't support linear layouts. */
 474         if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 475             mode < RADEON_SURF_MODE_1D)
 476                 mode = RADEON_SURF_MODE_1D;
 477
 478         /* Set the requested tiling mode. */
 479         switch (mode) {
 480         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 481                 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 482                 break;
 483         case RADEON_SURF_MODE_1D:
 484                 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 485                 break;
 486         case RADEON_SURF_MODE_2D:
 487                 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 488                 break;
 489         default:
 490                 assert(0);
 491         }
 492
 493         /* The format must be set correctly for the allocation of compressed
 494          * textures to work. In other cases, setting the bpp is sufficient.
 495          */
 496         if (compressed) {
 497                 switch (surf->bpe) {
 498                 case 8:
 499                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 500                         break;
 501                 case 16:
 502                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 503                         break;
 504                 default:
 505                         assert(0);
 506                 }
 507         }
 508         else {
 509                 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 510         }
 511
 512         AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
 513                 config->info.samples ? config->info.samples : 1;
 514         AddrSurfInfoIn.tileIndex = -1;
 515
 516         /* Set the micro tile type. */
 517         if (surf->flags & RADEON_SURF_SCANOUT)
 518                 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 519         else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
 520                 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 521         else
 522                 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 523
 524         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 525         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 526         AddrSurfInfoIn.flags.cube = config->is_cube;
 527         AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
 528         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 529         AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
 530         AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 531
 532         /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
 533          * requested, because TC-compatible HTILE requires 2D tiling.
 534          */
 535         AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
 536                                          !AddrSurfInfoIn.flags.fmask &&
 537                                          config->info.samples <= 1 &&
 538                                          (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
 539
 540         /* DCC notes:
 541          * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 542          *   with samples >= 4.
 543          * - Mipmapped array textures have low performance (discovered by a closed
 544          *   driver team).
 545          */
 546         AddrSurfInfoIn.flags.dccCompatible =
 547                 info->chip_class >= VI &&
 548                 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 549                 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 550                 !compressed && AddrDccIn.numSamples <= 1 &&
 551                 ((config->info.array_size == 1 && config->info.depth == 1) ||
 552                  config->info.levels == 1);
 553
 554         AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 555         AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 556
 557         /* noStencil = 0 can result in a depth part that is incompatible with
 558          * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 559          * this case, we may end up setting stencil_adjusted).
 560          *
 561          * TODO: update addrlib to a newer version, remove this, and
 562          * use flags.matchStencilTileCfg = 1 as an alternative fix.
 563          */
 564         if (config->info.levels > 1)
 565                 AddrSurfInfoIn.flags.noStencil = 1;
 566
 567         /* Set preferred macrotile parameters. This is usually required
 568          * for shared resources. This is for 2D tiling only. */
 569         if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 570             surf->u.legacy.bankw && surf->u.legacy.bankh &&
 571             surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
 572                 assert(!(surf->flags & RADEON_SURF_FMASK));
 573
 574                 /* If any of these parameters are incorrect, the calculation
 575                  * will fail. */
 576                 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
 577                 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
 578                 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
 579                 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
 580                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
 581                 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 582                 AddrSurfInfoIn.flags.opt4Space = 0;
 583                 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 584
 585                 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 586                  * the tile index, because we are expected to know it if
 587                  * we know the other parameters.
 588                  *
 589                  * This is something that can easily be fixed in Addrlib.
 590                  * For now, just figure it out here.
 591                  * Note that only 2D_TILE_THIN1 is handled here.
 592                  */
 593                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 594                 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 595
 596                 if (info->chip_class == SI) {
 597                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 598                                 if (surf->bpe == 2)
 599                                         AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 600                                 else
 601                                         AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 602                         } else {
 603                                 if (surf->bpe == 1)
 604                                         AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 605                                 else if (surf->bpe == 2)
 606                                         AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 607                                 else if (surf->bpe == 4)
 608                                         AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 609                                 else
 610                                         AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 611                         }
 612                 } else {
 613                         /* CIK - VI */
 614                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 615                                 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 616                         else
 617                                 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 618
 619                         /* Addrlib doesn't set this if tileIndex is forced like above. */
 620                         AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 621                 }
 622         }
 623
 624         surf->num_dcc_levels = 0;
 625         surf->surf_size = 0;
 626         surf->dcc_size = 0;
 627         surf->dcc_alignment = 1;
 628         surf->htile_size = 0;
 629         surf->htile_slice_size = 0;
 630         surf->htile_alignment = 1;
 631
 632         const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
 633                                   !(surf->flags & RADEON_SURF_ZBUFFER);
 634
 635         /* Calculate texture layout information. */
 636         if (!only_stencil) {
 637                 for (level = 0; level < config->info.levels; level++) {
 638                         r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
 639                                                &AddrSurfInfoIn, &AddrSurfInfoOut,
 640                                                &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
 641                         if (r)
 642                                 return r;
 643
 644                         if (level > 0)
 645                                 continue;
 646
 647                         gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
 648                 }
 649         }
 650
 651         /* Calculate texture layout information for stencil. */
 652         if (surf->flags & RADEON_SURF_SBUFFER) {
 653                 AddrSurfInfoIn.bpp = 8;
 654                 AddrSurfInfoIn.flags.depth = 0;
 655                 AddrSurfInfoIn.flags.stencil = 1;
 656                 AddrSurfInfoIn.flags.tcCompatible = 0;
 657                 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 658                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
 659
 660                 for (level = 0; level < config->info.levels; level++) {
 661                         r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
 662                                                &AddrSurfInfoIn, &AddrSurfInfoOut,
 663                                                &AddrDccIn, &AddrDccOut,
 664                                                NULL, NULL);
 665                         if (r)
 666                                 return r;
 667
 668                         /* DB uses the depth pitch for both stencil and depth. */
 669                         if (!only_stencil) {
 670                                 if (surf->u.legacy.stencil_level[level].nblk_x !=
 671                                     surf->u.legacy.level[level].nblk_x)
 672                                         surf->u.legacy.stencil_adjusted = true;
 673                         } else {
 674                                 surf->u.legacy.level[level].nblk_x =
 675                                         surf->u.legacy.stencil_level[level].nblk_x;
 676                         }
 677
 678                         if (level == 0) {
 679                                 if (only_stencil)
 680                                         gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
 681
 682                                 /* For 2D modes only. */
 683                                 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 684                                         surf->u.legacy.stencil_tile_split =
 685                                                 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 686                                 }
 687                         }
 688                 }
 689         }
 690
 691         /* Recalculate the whole DCC miptree size including disabled levels.
 692          * This is what addrlib does, but calling addrlib would be a lot more
 693          * complicated.
 694          */
 695         if (surf->dcc_size && config->info.levels > 1) {
 696                 surf->dcc_size = align64(surf->surf_size >> 8,
 697                                          info->pipe_interleave_bytes *
 698                                          info->num_tile_pipes);
 699         }
 700
 701         /* Make sure HTILE covers the whole miptree, because the shader reads
 702          * TC-compatible HTILE even for levels where it's disabled by DB.
 703          */
 704         if (surf->htile_size && config->info.levels > 1)
 705                 surf->htile_size *= 2;
 706
 707         surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 708
 709         /* Work out tile swizzle. */
 710         if (config->info.surf_index &&
 711             surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
 712             !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
 713             (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) {
 714                 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
 715                 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
 716
 717                 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
 718                 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
 719
 720                 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
 721                 AddrBaseSwizzleIn.tileIndex = AddrSurfInfoIn.tileIndex;
 722                 AddrBaseSwizzleIn.macroModeIndex = AddrSurfInfoOut.macroModeIndex;
 723                 AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo;
 724                 AddrBaseSwizzleIn.tileMode = AddrSurfInfoOut.tileMode;
 725
 726                 r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
 727                                            &AddrBaseSwizzleOut);
 728                 if (r != ADDR_OK)
 729                         return r;
 730
 731                 assert(AddrBaseSwizzleOut.tileSwizzle <=
 732                        u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
 733                 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
 734         }
 735         return 0;
 736 }
 737
 738 /* This is only called when expecting a tiled layout. */
 739 static int
 740 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
 741                                 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
 742                                 bool is_fmask, AddrSwizzleMode *swizzle_mode)
 743 {
 744         ADDR_E_RETURNCODE ret;
 745         ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
 746         ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
 747
 748         sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
 749         sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
 750
 751         sin.flags = in->flags;
 752         sin.resourceType = in->resourceType;
 753         sin.format = in->format;
 754         sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
 755         /* TODO: We could allow some of these: */
 756         sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
 757         sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
 758         sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
 759         sin.bpp = in->bpp;
 760         sin.width = in->width;
 761         sin.height = in->height;
 762         sin.numSlices = in->numSlices;
 763         sin.numMipLevels = in->numMipLevels;
 764         sin.numSamples = in->numSamples;
 765         sin.numFrags = in->numFrags;
 766
 767         if (is_fmask) {
 768                 sin.flags.color = 0;
 769                 sin.flags.fmask = 1;
 770         }
 771
 772         ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
 773         if (ret != ADDR_OK)
 774                 return ret;
 775
 776         *swizzle_mode = sout.swizzleMode;
 777         return 0;
 778 }
 779
 780 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 781                                 struct radeon_surf *surf, bool compressed,
 782                                 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
 783 {
 784         ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
 785         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
 786         ADDR_E_RETURNCODE ret;
 787
 788         out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
 789         out.pMipInfo = mip_info;
 790
 791         ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
 792         if (ret != ADDR_OK)
 793         return ret;
 794
 795         if (in->flags.stencil) {
 796                 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
 797                 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
 798                                                                    out.mipChainPitch - 1;
 799                 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
 800                 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
 801                 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
 802                 return 0;
 803         }
 804
 805         surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
 806         surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
 807                                                         out.mipChainPitch - 1;
 808
 809         /* CMASK fast clear uses these even if FMASK isn't allocated.
 810          * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
 811          */
 812         surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
 813         surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
 814
 815         surf->u.gfx9.surf_slice_size = out.sliceSize;
 816         surf->u.gfx9.surf_pitch = out.pitch;
 817         surf->u.gfx9.surf_height = out.height;
 818         surf->surf_size = out.surfSize;
 819         surf->surf_alignment = out.baseAlign;
 820
 821         if (in->swizzleMode == ADDR_SW_LINEAR) {
 822                 for (unsigned i = 0; i < in->numMipLevels; i++)
 823                         surf->u.gfx9.offset[i] = mip_info[i].offset;
 824         }
 825
 826         if (in->flags.depth) {
 827                 assert(in->swizzleMode != ADDR_SW_LINEAR);
 828
 829                 /* HTILE */
 830                 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
 831                 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
 832
 833                 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
 834                 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
 835
 836                 hin.hTileFlags.pipeAligned = 1;
 837                 hin.hTileFlags.rbAligned = 1;
 838                 hin.depthFlags = in->flags;
 839                 hin.swizzleMode = in->swizzleMode;
 840                 hin.unalignedWidth = in->width;
 841                 hin.unalignedHeight = in->height;
 842                 hin.numSlices = in->numSlices;
 843                 hin.numMipLevels = in->numMipLevels;
 844
 845                 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
 846                 if (ret != ADDR_OK)
 847                         return ret;
 848
 849                 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
 850                 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
 851                 surf->htile_size = hout.htileBytes;
 852                 surf->htile_slice_size = hout.sliceSize;
 853                 surf->htile_alignment = hout.baseAlign;
 854         } else {
 855                 /* DCC */
 856                 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 857                     !(surf->flags & RADEON_SURF_SCANOUT) &&
 858                     !compressed &&
 859                     in->swizzleMode != ADDR_SW_LINEAR &&
 860                     /* TODO: We could support DCC with MSAA. */
 861                     in->numSamples == 1) {
 862                         ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
 863                         ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
 864
 865                         din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
 866                         dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
 867
 868                         din.dccKeyFlags.pipeAligned = 1;
 869                         din.dccKeyFlags.rbAligned = 1;
 870                         din.colorFlags = in->flags;
 871                         din.resourceType = in->resourceType;
 872                         din.swizzleMode = in->swizzleMode;
 873                         din.bpp = in->bpp;
 874                         din.unalignedWidth = in->width;
 875                         din.unalignedHeight = in->height;
 876                         din.numSlices = in->numSlices;
 877                         din.numFrags = in->numFrags;
 878                         din.numMipLevels = in->numMipLevels;
 879                         din.dataSurfaceSize = out.surfSize;
 880
 881                         ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
 882                         if (ret != ADDR_OK)
 883                                 return ret;
 884
 885                         surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
 886                         surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
 887                         surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
 888                         surf->dcc_size = dout.dccRamSize;
 889                         surf->dcc_alignment = dout.dccRamBaseAlign;
 890                 }
 891
 892                 /* FMASK */
 893                 if (in->numSamples > 1) {
 894                         ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
 895                         ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
 896
 897                         fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
 898                         fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
 899
 900                         ret = gfx9_get_preferred_swizzle_mode(addrlib, in, true, &fin.swizzleMode);
 901                         if (ret != ADDR_OK)
 902                                 return ret;
 903
 904                         fin.unalignedWidth = in->width;
 905                         fin.unalignedHeight = in->height;
 906                         fin.numSlices = in->numSlices;
 907                         fin.numSamples = in->numSamples;
 908                         fin.numFrags = in->numFrags;
 909
 910                         ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
 911                         if (ret != ADDR_OK)
 912                                 return ret;
 913
 914                         surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
 915                         surf->u.gfx9.fmask.epitch = fout.pitch - 1;
 916                         surf->u.gfx9.fmask_size = fout.fmaskBytes;
 917                         surf->u.gfx9.fmask_alignment = fout.baseAlign;
 918                 }
 919
 920                 /* CMASK */
 921                 if (in->swizzleMode != ADDR_SW_LINEAR) {
 922                         ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
 923                         ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
 924
 925                         cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
 926                         cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
 927
 928                         cin.cMaskFlags.pipeAligned = 1;
 929                         cin.cMaskFlags.rbAligned = 1;
 930                         cin.colorFlags = in->flags;
 931                         cin.resourceType = in->resourceType;
 932                         cin.unalignedWidth = in->width;
 933                         cin.unalignedHeight = in->height;
 934                         cin.numSlices = in->numSlices;
 935
 936                         if (in->numSamples > 1)
 937                                 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
 938                         else
 939                                 cin.swizzleMode = in->swizzleMode;
 940
 941                         ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
 942                         if (ret != ADDR_OK)
 943                                 return ret;
 944
 945                         surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
 946                         surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
 947                         surf->u.gfx9.cmask_size = cout.cmaskBytes;
 948                         surf->u.gfx9.cmask_alignment = cout.baseAlign;
 949                 }
 950         }
 951
 952         return 0;
 953 }
 954
 955 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 956                                 const struct ac_surf_config *config,
 957                                 enum radeon_surf_mode mode,
 958                                 struct radeon_surf *surf)
 959 {
 960         bool compressed;
 961         ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 962         int r;
 963
 964         assert(!(surf->flags & RADEON_SURF_FMASK));
 965
 966         AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
 967
 968         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 969
 970         /* The format must be set correctly for the allocation of compressed
 971          * textures to work. In other cases, setting the bpp is sufficient. */
 972         if (compressed) {
 973                 switch (surf->bpe) {
 974                 case 8:
 975                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 976                         break;
 977                 case 16:
 978                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 979                         break;
 980                 default:
 981                         assert(0);
 982                 }
 983         } else {
 984                 AddrSurfInfoIn.bpp = surf->bpe * 8;
 985         }
 986
 987         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 988         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 989         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 990         /* flags.texture currently refers to TC-compatible HTILE */
 991         AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
 992                                        surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
 993         AddrSurfInfoIn.flags.opt4space = 1;
 994
 995         AddrSurfInfoIn.numMipLevels = config->info.levels;
 996         AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
 997         AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
 998
 999         /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1000          * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1001          * must sample 1D textures as 2D. */
1002         if (config->is_3d)
1003                 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1004         else
1005                 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1006
1007         AddrSurfInfoIn.width = config->info.width;
1008         AddrSurfInfoIn.height = config->info.height;
1009
1010         if (config->is_3d)
1011                 AddrSurfInfoIn.numSlices = config->info.depth;
1012         else if (config->is_cube)
1013                 AddrSurfInfoIn.numSlices = 6;
1014         else
1015                 AddrSurfInfoIn.numSlices = config->info.array_size;
1016
1017         switch (mode) {
1018         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1019                 assert(config->info.samples <= 1);
1020                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1021                 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1022                 break;
1023
1024         case RADEON_SURF_MODE_1D:
1025         case RADEON_SURF_MODE_2D:
1026                 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
1027                                                     &AddrSurfInfoIn.swizzleMode);
1028                 if (r)
1029                         return r;
1030                 break;
1031
1032         default:
1033                 assert(0);
1034         }
1035
1036         surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1037
1038         surf->surf_size = 0;
1039         surf->dcc_size = 0;
1040         surf->htile_size = 0;
1041         surf->htile_slice_size = 0;
1042         surf->u.gfx9.surf_offset = 0;
1043         surf->u.gfx9.stencil_offset = 0;
1044         surf->u.gfx9.fmask_size = 0;
1045         surf->u.gfx9.cmask_size = 0;
1046
1047         /* Calculate texture layout information. */
1048         r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1049         if (r)
1050                 return r;
1051
1052         /* Calculate texture layout information for stencil. */
1053         if (surf->flags & RADEON_SURF_SBUFFER) {
1054                 AddrSurfInfoIn.bpp = 8;
1055                 AddrSurfInfoIn.flags.depth = 0;
1056                 AddrSurfInfoIn.flags.stencil = 1;
1057
1058                 r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1059                 if (r)
1060                         return r;
1061         }
1062
1063         surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1064         surf->num_dcc_levels = surf->dcc_size ? config->info.levels : 0;
1065
1066         switch (surf->u.gfx9.surf.swizzle_mode) {
1067                 /* S = standard. */
1068                 case ADDR_SW_256B_S:
1069                 case ADDR_SW_4KB_S:
1070                 case ADDR_SW_64KB_S:
1071                 case ADDR_SW_VAR_S:
1072                 case ADDR_SW_64KB_S_T:
1073                 case ADDR_SW_4KB_S_X:
1074                 case ADDR_SW_64KB_S_X:
1075                 case ADDR_SW_VAR_S_X:
1076                         surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1077                         break;
1078
1079                 /* D = display. */
1080                 case ADDR_SW_LINEAR:
1081                 case ADDR_SW_256B_D:
1082                 case ADDR_SW_4KB_D:
1083                 case ADDR_SW_64KB_D:
1084                 case ADDR_SW_VAR_D:
1085                 case ADDR_SW_64KB_D_T:
1086                 case ADDR_SW_4KB_D_X:
1087                 case ADDR_SW_64KB_D_X:
1088                 case ADDR_SW_VAR_D_X:
1089                         surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1090                         break;
1091
1092                 /* R = rotated. */
1093                 case ADDR_SW_256B_R:
1094                 case ADDR_SW_4KB_R:
1095                 case ADDR_SW_64KB_R:
1096                 case ADDR_SW_VAR_R:
1097                 case ADDR_SW_64KB_R_T:
1098                 case ADDR_SW_4KB_R_X:
1099                 case ADDR_SW_64KB_R_X:
1100                 case ADDR_SW_VAR_R_X:
1101                         surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1102                         break;
1103
1104                 /* Z = depth. */
1105                 case ADDR_SW_4KB_Z:
1106                 case ADDR_SW_64KB_Z:
1107                 case ADDR_SW_VAR_Z:
1108                 case ADDR_SW_64KB_Z_T:
1109                 case ADDR_SW_4KB_Z_X:
1110                 case ADDR_SW_64KB_Z_X:
1111                 case ADDR_SW_VAR_Z_X:
1112                         surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1113                         break;
1114
1115                 default:
1116                         assert(0);
1117         }
1118
1119         return 0;
1120 }
1121
1122 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1123                        const struct ac_surf_config *config,
1124                        enum radeon_surf_mode mode,
1125                        struct radeon_surf *surf)
1126 {
1127         int r;
1128
1129         r = surf_config_sanity(config);
1130         if (r)
1131                 return r;
1132
1133         if (info->chip_class >= GFX9)
1134                 return gfx9_compute_surface(addrlib, config, mode, surf);
1135         else
1136                 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1137 }