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ac/surface: don't compute DCC if it's unsupported by DCN on gfx9+
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/src/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include "drm-uapi/amdgpu_drm.h"
41
42 #include "addrlib/inc/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
53 {
54 return malloc(pInput->sizeInBytes);
55 }
56
57 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
58 {
59 free(pInput->pVirtAddr);
60 return ADDR_OK;
61 }
62
63 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
64 const struct amdgpu_gpu_info *amdinfo,
65 uint64_t *max_alignment)
66 {
67 ADDR_CREATE_INPUT addrCreateInput = {0};
68 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
69 ADDR_REGISTER_VALUE regValue = {0};
70 ADDR_CREATE_FLAGS createFlags = {{0}};
71 ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
72 ADDR_E_RETURNCODE addrRet;
73
74 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
75 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
76
77 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
78 createFlags.value = 0;
79
80 addrCreateInput.chipFamily = info->family_id;
81 addrCreateInput.chipRevision = info->chip_external_rev;
82
83 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
84 return NULL;
85
86 if (addrCreateInput.chipFamily >= FAMILY_AI) {
87 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
88 } else {
89 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
90 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
91
92 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
93 regValue.pTileConfig = amdinfo->gb_tile_mode;
94 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
95 if (addrCreateInput.chipFamily == FAMILY_SI) {
96 regValue.pMacroTileConfig = NULL;
97 regValue.noOfMacroEntries = 0;
98 } else {
99 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
100 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
101 }
102
103 createFlags.useTileIndex = 1;
104 createFlags.useHtileSliceAlign = 1;
105
106 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
107 }
108
109 addrCreateInput.callbacks.allocSysMem = allocSysMem;
110 addrCreateInput.callbacks.freeSysMem = freeSysMem;
111 addrCreateInput.callbacks.debugPrint = 0;
112 addrCreateInput.createFlags = createFlags;
113 addrCreateInput.regValue = regValue;
114
115 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
116 if (addrRet != ADDR_OK)
117 return NULL;
118
119 if (max_alignment) {
120 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
121 if (addrRet == ADDR_OK){
122 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
123 }
124 }
125 return addrCreateOutput.hLib;
126 }
127
128 static int surf_config_sanity(const struct ac_surf_config *config,
129 unsigned flags)
130 {
131 /* FMASK is allocated together with the color surface and can't be
132 * allocated separately.
133 */
134 assert(!(flags & RADEON_SURF_FMASK));
135 if (flags & RADEON_SURF_FMASK)
136 return -EINVAL;
137
138 /* all dimension must be at least 1 ! */
139 if (!config->info.width || !config->info.height || !config->info.depth ||
140 !config->info.array_size || !config->info.levels)
141 return -EINVAL;
142
143 switch (config->info.samples) {
144 case 0:
145 case 1:
146 case 2:
147 case 4:
148 case 8:
149 break;
150 case 16:
151 if (flags & RADEON_SURF_Z_OR_SBUFFER)
152 return -EINVAL;
153 break;
154 default:
155 return -EINVAL;
156 }
157
158 if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
159 switch (config->info.storage_samples) {
160 case 0:
161 case 1:
162 case 2:
163 case 4:
164 case 8:
165 break;
166 default:
167 return -EINVAL;
168 }
169 }
170
171 if (config->is_3d && config->info.array_size > 1)
172 return -EINVAL;
173 if (config->is_cube && config->info.depth > 1)
174 return -EINVAL;
175
176 return 0;
177 }
178
179 static int gfx6_compute_level(ADDR_HANDLE addrlib,
180 const struct ac_surf_config *config,
181 struct radeon_surf *surf, bool is_stencil,
182 unsigned level, bool compressed,
183 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
184 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
185 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
186 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
187 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
188 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
189 {
190 struct legacy_surf_level *surf_level;
191 ADDR_E_RETURNCODE ret;
192
193 AddrSurfInfoIn->mipLevel = level;
194 AddrSurfInfoIn->width = u_minify(config->info.width, level);
195 AddrSurfInfoIn->height = u_minify(config->info.height, level);
196
197 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
198 * because GFX9 needs linear alignment of 256 bytes.
199 */
200 if (config->info.levels == 1 &&
201 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
202 AddrSurfInfoIn->bpp &&
203 util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
204 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
205
206 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
207 }
208
209 /* addrlib assumes the bytes/pixel is a divisor of 64, which is not
210 * true for r32g32b32 formats. */
211 if (AddrSurfInfoIn->bpp == 96) {
212 assert(config->info.levels == 1);
213 assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED);
214
215 /* The least common multiple of 64 bytes and 12 bytes/pixel is
216 * 192 bytes, or 16 pixels. */
217 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 16);
218 }
219
220 if (config->is_3d)
221 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
222 else if (config->is_cube)
223 AddrSurfInfoIn->numSlices = 6;
224 else
225 AddrSurfInfoIn->numSlices = config->info.array_size;
226
227 if (level > 0) {
228 /* Set the base level pitch. This is needed for calculation
229 * of non-zero levels. */
230 if (is_stencil)
231 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
232 else
233 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
234
235 /* Convert blocks to pixels for compressed formats. */
236 if (compressed)
237 AddrSurfInfoIn->basePitch *= surf->blk_w;
238 }
239
240 ret = AddrComputeSurfaceInfo(addrlib,
241 AddrSurfInfoIn,
242 AddrSurfInfoOut);
243 if (ret != ADDR_OK) {
244 return ret;
245 }
246
247 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
248 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
249 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
250 surf_level->nblk_x = AddrSurfInfoOut->pitch;
251 surf_level->nblk_y = AddrSurfInfoOut->height;
252
253 switch (AddrSurfInfoOut->tileMode) {
254 case ADDR_TM_LINEAR_ALIGNED:
255 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
256 break;
257 case ADDR_TM_1D_TILED_THIN1:
258 surf_level->mode = RADEON_SURF_MODE_1D;
259 break;
260 case ADDR_TM_2D_TILED_THIN1:
261 surf_level->mode = RADEON_SURF_MODE_2D;
262 break;
263 default:
264 assert(0);
265 }
266
267 if (is_stencil)
268 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
269 else
270 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
271
272 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
273
274 /* Clear DCC fields at the beginning. */
275 surf_level->dcc_offset = 0;
276
277 /* The previous level's flag tells us if we can use DCC for this level. */
278 if (AddrSurfInfoIn->flags.dccCompatible &&
279 (level == 0 || AddrDccOut->subLvlCompressible)) {
280 bool prev_level_clearable = level == 0 ||
281 AddrDccOut->dccRamSizeAligned;
282
283 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
284 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
285 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
286 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
287 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
288
289 ret = AddrComputeDccInfo(addrlib,
290 AddrDccIn,
291 AddrDccOut);
292
293 if (ret == ADDR_OK) {
294 surf_level->dcc_offset = surf->dcc_size;
295 surf->num_dcc_levels = level + 1;
296 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
297 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
298
299 /* If the DCC size of a subresource (1 mip level or 1 slice)
300 * is not aligned, the DCC memory layout is not contiguous for
301 * that subresource, which means we can't use fast clear.
302 *
303 * We only do fast clears for whole mipmap levels. If we did
304 * per-slice fast clears, the same restriction would apply.
305 * (i.e. only compute the slice size and see if it's aligned)
306 *
307 * The last level can be non-contiguous and still be clearable
308 * if it's interleaved with the next level that doesn't exist.
309 */
310 if (AddrDccOut->dccRamSizeAligned ||
311 (prev_level_clearable && level == config->info.levels - 1))
312 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
313 else
314 surf_level->dcc_fast_clear_size = 0;
315
316 /* Compute the DCC slice size because addrlib doesn't
317 * provide this info. As DCC memory is linear (each
318 * slice is the same size) it's easy to compute.
319 */
320 surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
321
322 /* For arrays, we have to compute the DCC info again
323 * with one slice size to get a correct fast clear
324 * size.
325 */
326 if (config->info.array_size > 1) {
327 AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize;
328 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
329 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
330 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
331 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
332
333 ret = AddrComputeDccInfo(addrlib,
334 AddrDccIn, AddrDccOut);
335 if (ret == ADDR_OK) {
336 /* If the DCC memory isn't properly
337 * aligned, the data are interleaved
338 * accross slices.
339 */
340 if (AddrDccOut->dccRamSizeAligned)
341 surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize;
342 else
343 surf_level->dcc_slice_fast_clear_size = 0;
344 }
345 } else {
346 surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size;
347 }
348 }
349 }
350
351 /* HTILE. */
352 if (!is_stencil &&
353 AddrSurfInfoIn->flags.depth &&
354 surf_level->mode == RADEON_SURF_MODE_2D &&
355 level == 0 &&
356 !(surf->flags & RADEON_SURF_NO_HTILE)) {
357 AddrHtileIn->flags.tcCompatible = AddrSurfInfoOut->tcCompatible;
358 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
359 AddrHtileIn->height = AddrSurfInfoOut->height;
360 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
361 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
362 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
363 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
364 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
365 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
366
367 ret = AddrComputeHtileInfo(addrlib,
368 AddrHtileIn,
369 AddrHtileOut);
370
371 if (ret == ADDR_OK) {
372 surf->htile_size = AddrHtileOut->htileBytes;
373 surf->htile_slice_size = AddrHtileOut->sliceSize;
374 surf->htile_alignment = AddrHtileOut->baseAlign;
375 }
376 }
377
378 return 0;
379 }
380
381 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
382 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
383 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
384
385 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
386 const struct radeon_info *info)
387 {
388 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
389
390 if (info->chip_class >= GFX7)
391 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
392 else
393 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
394 }
395
396 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
397 {
398 unsigned index, tileb;
399
400 tileb = 8 * 8 * surf->bpe;
401 tileb = MIN2(surf->u.legacy.tile_split, tileb);
402
403 for (index = 0; tileb > 64; index++)
404 tileb >>= 1;
405
406 assert(index < 16);
407 return index;
408 }
409
410 static bool get_display_flag(const struct ac_surf_config *config,
411 const struct radeon_surf *surf)
412 {
413 unsigned num_channels = config->info.num_channels;
414 unsigned bpe = surf->bpe;
415
416 if (!config->is_3d &&
417 !config->is_cube &&
418 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
419 surf->flags & RADEON_SURF_SCANOUT &&
420 config->info.samples <= 1 &&
421 surf->blk_w <= 2 && surf->blk_h == 1) {
422 /* subsampled */
423 if (surf->blk_w == 2 && surf->blk_h == 1)
424 return true;
425
426 if (/* RGBA8 or RGBA16F */
427 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
428 /* R5G6B5 or R5G5B5A1 */
429 (bpe == 2 && num_channels >= 3) ||
430 /* C8 palette */
431 (bpe == 1 && num_channels == 1))
432 return true;
433 }
434 return false;
435 }
436
437 /**
438 * This must be called after the first level is computed.
439 *
440 * Copy surface-global settings like pipe/bank config from level 0 surface
441 * computation, and compute tile swizzle.
442 */
443 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
444 const struct radeon_info *info,
445 const struct ac_surf_config *config,
446 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
447 struct radeon_surf *surf)
448 {
449 surf->surf_alignment = csio->baseAlign;
450 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
451 gfx6_set_micro_tile_mode(surf, info);
452
453 /* For 2D modes only. */
454 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
455 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
456 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
457 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
458 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
459 surf->u.legacy.num_banks = csio->pTileInfo->banks;
460 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
461 } else {
462 surf->u.legacy.macro_tile_index = 0;
463 }
464
465 /* Compute tile swizzle. */
466 /* TODO: fix tile swizzle with mipmapping for GFX6 */
467 if ((info->chip_class >= GFX7 || config->info.levels == 1) &&
468 config->info.surf_index &&
469 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
470 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
471 !get_display_flag(config, surf)) {
472 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
473 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
474
475 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
476 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
477
478 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
479 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
480 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
481 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
482 AddrBaseSwizzleIn.tileMode = csio->tileMode;
483
484 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
485 &AddrBaseSwizzleOut);
486 if (r != ADDR_OK)
487 return r;
488
489 assert(AddrBaseSwizzleOut.tileSwizzle <=
490 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
491 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
492 }
493 return 0;
494 }
495
496 static void ac_compute_cmask(const struct radeon_info *info,
497 const struct ac_surf_config *config,
498 struct radeon_surf *surf)
499 {
500 unsigned pipe_interleave_bytes = info->pipe_interleave_bytes;
501 unsigned num_pipes = info->num_tile_pipes;
502 unsigned cl_width, cl_height;
503
504 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER ||
505 (config->info.samples >= 2 && !surf->fmask_size))
506 return;
507
508 assert(info->chip_class <= GFX8);
509
510 switch (num_pipes) {
511 case 2:
512 cl_width = 32;
513 cl_height = 16;
514 break;
515 case 4:
516 cl_width = 32;
517 cl_height = 32;
518 break;
519 case 8:
520 cl_width = 64;
521 cl_height = 32;
522 break;
523 case 16: /* Hawaii */
524 cl_width = 64;
525 cl_height = 64;
526 break;
527 default:
528 assert(0);
529 return;
530 }
531
532 unsigned base_align = num_pipes * pipe_interleave_bytes;
533
534 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
535 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
536 unsigned slice_elements = (width * height) / (8*8);
537
538 /* Each element of CMASK is a nibble. */
539 unsigned slice_bytes = slice_elements / 2;
540
541 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
542 if (surf->u.legacy.cmask_slice_tile_max)
543 surf->u.legacy.cmask_slice_tile_max -= 1;
544
545 unsigned num_layers;
546 if (config->is_3d)
547 num_layers = config->info.depth;
548 else if (config->is_cube)
549 num_layers = 6;
550 else
551 num_layers = config->info.array_size;
552
553 surf->cmask_alignment = MAX2(256, base_align);
554 surf->cmask_slice_size = align(slice_bytes, base_align);
555 surf->cmask_size = surf->cmask_slice_size * num_layers;
556 }
557
558 /**
559 * Fill in the tiling information in \p surf based on the given surface config.
560 *
561 * The following fields of \p surf must be initialized by the caller:
562 * blk_w, blk_h, bpe, flags.
563 */
564 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
565 const struct radeon_info *info,
566 const struct ac_surf_config *config,
567 enum radeon_surf_mode mode,
568 struct radeon_surf *surf)
569 {
570 unsigned level;
571 bool compressed;
572 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
573 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
574 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
575 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
576 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
577 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
578 ADDR_TILEINFO AddrTileInfoIn = {0};
579 ADDR_TILEINFO AddrTileInfoOut = {0};
580 int r;
581
582 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
583 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
584 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
585 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
586 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
587 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
588 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
589
590 compressed = surf->blk_w == 4 && surf->blk_h == 4;
591
592 /* MSAA requires 2D tiling. */
593 if (config->info.samples > 1)
594 mode = RADEON_SURF_MODE_2D;
595
596 /* DB doesn't support linear layouts. */
597 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
598 mode < RADEON_SURF_MODE_1D)
599 mode = RADEON_SURF_MODE_1D;
600
601 /* Set the requested tiling mode. */
602 switch (mode) {
603 case RADEON_SURF_MODE_LINEAR_ALIGNED:
604 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
605 break;
606 case RADEON_SURF_MODE_1D:
607 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
608 break;
609 case RADEON_SURF_MODE_2D:
610 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
611 break;
612 default:
613 assert(0);
614 }
615
616 /* The format must be set correctly for the allocation of compressed
617 * textures to work. In other cases, setting the bpp is sufficient.
618 */
619 if (compressed) {
620 switch (surf->bpe) {
621 case 8:
622 AddrSurfInfoIn.format = ADDR_FMT_BC1;
623 break;
624 case 16:
625 AddrSurfInfoIn.format = ADDR_FMT_BC3;
626 break;
627 default:
628 assert(0);
629 }
630 }
631 else {
632 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
633 }
634
635 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
636 MAX2(1, config->info.samples);
637 AddrSurfInfoIn.tileIndex = -1;
638
639 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
640 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
641 MAX2(1, config->info.storage_samples);
642 }
643
644 /* Set the micro tile type. */
645 if (surf->flags & RADEON_SURF_SCANOUT)
646 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
647 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
648 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
649 else
650 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
651
652 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
653 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
654 AddrSurfInfoIn.flags.cube = config->is_cube;
655 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
656 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
657 AddrSurfInfoIn.flags.tcCompatible = info->chip_class >= GFX8 &&
658 AddrSurfInfoIn.flags.depth;
659
660 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
661 * requested, because TC-compatible HTILE requires 2D tiling.
662 */
663 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
664 !AddrSurfInfoIn.flags.fmask &&
665 config->info.samples <= 1 &&
666 !(surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE);
667
668 /* DCC notes:
669 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
670 * with samples >= 4.
671 * - Mipmapped array textures have low performance (discovered by a closed
672 * driver team).
673 */
674 AddrSurfInfoIn.flags.dccCompatible =
675 info->chip_class >= GFX8 &&
676 info->has_graphics && /* disable DCC on compute-only chips */
677 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
678 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
679 !compressed &&
680 ((config->info.array_size == 1 && config->info.depth == 1) ||
681 config->info.levels == 1);
682
683 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
684 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
685
686 /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit)
687 * for Z and stencil. This can cause a number of problems which we work
688 * around here:
689 *
690 * - a depth part that is incompatible with mipmapped texturing
691 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
692 * incorrect tiling applied to the stencil part, stencil buffer
693 * memory accesses that go out of bounds) even without mipmapping
694 *
695 * Some piglit tests that are prone to different types of related
696 * failures:
697 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
698 * ./bin/framebuffer-blit-levels {draw,read} stencil
699 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
700 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
701 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
702 */
703 int stencil_tile_idx = -1;
704
705 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
706 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
707 /* Compute stencilTileIdx that is compatible with the (depth)
708 * tileIdx. This degrades the depth surface if necessary to
709 * ensure that a matching stencilTileIdx exists. */
710 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
711
712 /* Keep the depth mip-tail compatible with texturing. */
713 AddrSurfInfoIn.flags.noStencil = 1;
714 }
715
716 /* Set preferred macrotile parameters. This is usually required
717 * for shared resources. This is for 2D tiling only. */
718 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
719 surf->u.legacy.bankw && surf->u.legacy.bankh &&
720 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
721 /* If any of these parameters are incorrect, the calculation
722 * will fail. */
723 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
724 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
725 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
726 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
727 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
728 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
729 AddrSurfInfoIn.flags.opt4Space = 0;
730 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
731
732 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
733 * the tile index, because we are expected to know it if
734 * we know the other parameters.
735 *
736 * This is something that can easily be fixed in Addrlib.
737 * For now, just figure it out here.
738 * Note that only 2D_TILE_THIN1 is handled here.
739 */
740 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
741 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
742
743 if (info->chip_class == GFX6) {
744 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
745 if (surf->bpe == 2)
746 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
747 else
748 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
749 } else {
750 if (surf->bpe == 1)
751 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
752 else if (surf->bpe == 2)
753 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
754 else if (surf->bpe == 4)
755 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
756 else
757 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
758 }
759 } else {
760 /* GFX7 - GFX8 */
761 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
762 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
763 else
764 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
765
766 /* Addrlib doesn't set this if tileIndex is forced like above. */
767 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
768 }
769 }
770
771 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
772 surf->num_dcc_levels = 0;
773 surf->surf_size = 0;
774 surf->dcc_size = 0;
775 surf->dcc_alignment = 1;
776 surf->htile_size = 0;
777 surf->htile_slice_size = 0;
778 surf->htile_alignment = 1;
779 surf->tc_compatible_htile_allowed = AddrSurfInfoIn.flags.tcCompatible;
780
781 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
782 !(surf->flags & RADEON_SURF_ZBUFFER);
783
784 /* Calculate texture layout information. */
785 if (!only_stencil) {
786 for (level = 0; level < config->info.levels; level++) {
787 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
788 &AddrSurfInfoIn, &AddrSurfInfoOut,
789 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
790 if (r)
791 return r;
792
793 if (level > 0)
794 continue;
795
796 if (!AddrSurfInfoOut.tcCompatible)
797 AddrSurfInfoIn.flags.tcCompatible = 0;
798
799 if (!AddrSurfInfoOut.tcCompatible || !surf->htile_size)
800 surf->tc_compatible_htile_allowed = false;
801
802 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
803 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
804 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
805 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
806
807 assert(stencil_tile_idx >= 0);
808 }
809
810 r = gfx6_surface_settings(addrlib, info, config,
811 &AddrSurfInfoOut, surf);
812 if (r)
813 return r;
814 }
815 }
816
817 /* Calculate texture layout information for stencil. */
818 if (surf->flags & RADEON_SURF_SBUFFER) {
819 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
820 AddrSurfInfoIn.bpp = 8;
821 AddrSurfInfoIn.flags.depth = 0;
822 AddrSurfInfoIn.flags.stencil = 1;
823 AddrSurfInfoIn.flags.tcCompatible = 0;
824 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
825 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
826
827 for (level = 0; level < config->info.levels; level++) {
828 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
829 &AddrSurfInfoIn, &AddrSurfInfoOut,
830 &AddrDccIn, &AddrDccOut,
831 NULL, NULL);
832 if (r)
833 return r;
834
835 /* DB uses the depth pitch for both stencil and depth. */
836 if (!only_stencil) {
837 if (surf->u.legacy.stencil_level[level].nblk_x !=
838 surf->u.legacy.level[level].nblk_x)
839 surf->u.legacy.stencil_adjusted = true;
840 } else {
841 surf->u.legacy.level[level].nblk_x =
842 surf->u.legacy.stencil_level[level].nblk_x;
843 }
844
845 if (level == 0) {
846 if (only_stencil) {
847 r = gfx6_surface_settings(addrlib, info, config,
848 &AddrSurfInfoOut, surf);
849 if (r)
850 return r;
851 }
852
853 /* For 2D modes only. */
854 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
855 surf->u.legacy.stencil_tile_split =
856 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
857 }
858 }
859 }
860 }
861
862 /* Compute FMASK. */
863 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color &&
864 info->has_graphics && !(surf->flags & RADEON_SURF_NO_FMASK)) {
865 ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
866 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
867 ADDR_TILEINFO fmask_tile_info = {};
868
869 fin.size = sizeof(fin);
870 fout.size = sizeof(fout);
871
872 fin.tileMode = AddrSurfInfoOut.tileMode;
873 fin.pitch = AddrSurfInfoOut.pitch;
874 fin.height = config->info.height;
875 fin.numSlices = AddrSurfInfoIn.numSlices;
876 fin.numSamples = AddrSurfInfoIn.numSamples;
877 fin.numFrags = AddrSurfInfoIn.numFrags;
878 fin.tileIndex = -1;
879 fout.pTileInfo = &fmask_tile_info;
880
881 r = AddrComputeFmaskInfo(addrlib, &fin, &fout);
882 if (r)
883 return r;
884
885 surf->fmask_size = fout.fmaskBytes;
886 surf->fmask_alignment = fout.baseAlign;
887 surf->fmask_tile_swizzle = 0;
888
889 surf->u.legacy.fmask.slice_tile_max =
890 (fout.pitch * fout.height) / 64;
891 if (surf->u.legacy.fmask.slice_tile_max)
892 surf->u.legacy.fmask.slice_tile_max -= 1;
893
894 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
895 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
896 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
897 surf->u.legacy.fmask.slice_size = fout.sliceSize;
898
899 /* Compute tile swizzle for FMASK. */
900 if (config->info.fmask_surf_index &&
901 !(surf->flags & RADEON_SURF_SHAREABLE)) {
902 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0};
903 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0};
904
905 xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
906 xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
907
908 /* This counter starts from 1 instead of 0. */
909 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
910 xin.tileIndex = fout.tileIndex;
911 xin.macroModeIndex = fout.macroModeIndex;
912 xin.pTileInfo = fout.pTileInfo;
913 xin.tileMode = fin.tileMode;
914
915 int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout);
916 if (r != ADDR_OK)
917 return r;
918
919 assert(xout.tileSwizzle <=
920 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
921 surf->fmask_tile_swizzle = xout.tileSwizzle;
922 }
923 }
924
925 /* Recalculate the whole DCC miptree size including disabled levels.
926 * This is what addrlib does, but calling addrlib would be a lot more
927 * complicated.
928 */
929 if (surf->dcc_size && config->info.levels > 1) {
930 /* The smallest miplevels that are never compressed by DCC
931 * still read the DCC buffer via TC if the base level uses DCC,
932 * and for some reason the DCC buffer needs to be larger if
933 * the miptree uses non-zero tile_swizzle. Otherwise there are
934 * VM faults.
935 *
936 * "dcc_alignment * 4" was determined by trial and error.
937 */
938 surf->dcc_size = align64(surf->surf_size >> 8,
939 surf->dcc_alignment * 4);
940 }
941
942 /* Make sure HTILE covers the whole miptree, because the shader reads
943 * TC-compatible HTILE even for levels where it's disabled by DB.
944 */
945 if (surf->htile_size && config->info.levels > 1 &&
946 surf->tc_compatible_htile_allowed) {
947 /* MSAA can't occur with levels > 1, so ignore the sample count. */
948 const unsigned total_pixels = surf->surf_size / surf->bpe;
949 const unsigned htile_block_size = 8 * 8;
950 const unsigned htile_element_size = 4;
951
952 surf->htile_size = (total_pixels / htile_block_size) *
953 htile_element_size;
954 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
955 }
956
957 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
958 surf->is_displayable = surf->is_linear ||
959 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
960 surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER;
961
962 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
963 * used at the same time. This case is not currently expected to occur
964 * because we don't use rotated. Enforce this restriction on all chips
965 * to facilitate testing.
966 */
967 if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER) {
968 assert(!"rotate micro tile mode is unsupported");
969 return ADDR_ERROR;
970 }
971
972 ac_compute_cmask(info, config, surf);
973 return 0;
974 }
975
976 /* This is only called when expecting a tiled layout. */
977 static int
978 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
979 struct radeon_surf *surf,
980 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
981 bool is_fmask, AddrSwizzleMode *swizzle_mode)
982 {
983 ADDR_E_RETURNCODE ret;
984 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
985 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
986
987 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
988 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
989
990 sin.flags = in->flags;
991 sin.resourceType = in->resourceType;
992 sin.format = in->format;
993 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
994 /* TODO: We could allow some of these: */
995 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
996 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
997 sin.bpp = in->bpp;
998 sin.width = in->width;
999 sin.height = in->height;
1000 sin.numSlices = in->numSlices;
1001 sin.numMipLevels = in->numMipLevels;
1002 sin.numSamples = in->numSamples;
1003 sin.numFrags = in->numFrags;
1004
1005 if (is_fmask) {
1006 sin.flags.display = 0;
1007 sin.flags.color = 0;
1008 sin.flags.fmask = 1;
1009 }
1010
1011 if (surf->flags & RADEON_SURF_FORCE_MICRO_TILE_MODE) {
1012 sin.forbiddenBlock.linear = 1;
1013
1014 if (surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1015 sin.preferredSwSet.sw_D = 1;
1016 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_STANDARD)
1017 sin.preferredSwSet.sw_S = 1;
1018 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_DEPTH)
1019 sin.preferredSwSet.sw_Z = 1;
1020 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER)
1021 sin.preferredSwSet.sw_R = 1;
1022 }
1023
1024 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
1025 if (ret != ADDR_OK)
1026 return ret;
1027
1028 *swizzle_mode = sout.swizzleMode;
1029 return 0;
1030 }
1031
1032 static bool is_dcc_supported_by_CB(const struct radeon_info *info, unsigned sw_mode)
1033 {
1034 if (info->chip_class >= GFX10)
1035 return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X;
1036
1037 return sw_mode != ADDR_SW_LINEAR;
1038 }
1039
1040 static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
1041 const struct ac_surf_config *config,
1042 const struct radeon_surf *surf,
1043 bool rb_aligned, bool pipe_aligned)
1044 {
1045 if (!info->use_display_dcc_unaligned &&
1046 !info->use_display_dcc_with_retile_blit)
1047 return false;
1048
1049 /* Handle unaligned DCC. */
1050 if (info->use_display_dcc_unaligned &&
1051 (rb_aligned || pipe_aligned))
1052 return false;
1053
1054 return true;
1055 }
1056
1057 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
1058 const struct radeon_info *info,
1059 const struct ac_surf_config *config,
1060 struct radeon_surf *surf, bool compressed,
1061 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
1062 {
1063 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
1064 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
1065 ADDR_E_RETURNCODE ret;
1066
1067 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
1068 out.pMipInfo = mip_info;
1069
1070 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
1071 if (ret != ADDR_OK)
1072 return ret;
1073
1074 if (in->flags.stencil) {
1075 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1076 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1077 out.mipChainPitch - 1;
1078 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1079 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1080 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1081 return 0;
1082 }
1083
1084 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1085 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1086 out.mipChainPitch - 1;
1087
1088 /* CMASK fast clear uses these even if FMASK isn't allocated.
1089 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1090 */
1091 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1092 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1093
1094 surf->u.gfx9.surf_slice_size = out.sliceSize;
1095 surf->u.gfx9.surf_pitch = out.pitch;
1096 if (!compressed && surf->blk_w > 1 && out.pitch == out.pixelPitch) {
1097 /* Adjust surf_pitch to be in elements units,
1098 * not in pixels */
1099 surf->u.gfx9.surf_pitch /= surf->blk_w;
1100 }
1101 surf->u.gfx9.surf_height = out.height;
1102 surf->surf_size = out.surfSize;
1103 surf->surf_alignment = out.baseAlign;
1104
1105 if (in->swizzleMode == ADDR_SW_LINEAR) {
1106 for (unsigned i = 0; i < in->numMipLevels; i++) {
1107 surf->u.gfx9.offset[i] = mip_info[i].offset;
1108 surf->u.gfx9.pitch[i] = mip_info[i].pitch;
1109 }
1110 }
1111
1112 if (in->flags.depth) {
1113 assert(in->swizzleMode != ADDR_SW_LINEAR);
1114
1115 if (surf->flags & RADEON_SURF_NO_HTILE)
1116 return 0;
1117
1118 /* HTILE */
1119 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
1120 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
1121
1122 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
1123 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
1124
1125 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1126 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
1127 hin.depthFlags = in->flags;
1128 hin.swizzleMode = in->swizzleMode;
1129 hin.unalignedWidth = in->width;
1130 hin.unalignedHeight = in->height;
1131 hin.numSlices = in->numSlices;
1132 hin.numMipLevels = in->numMipLevels;
1133 hin.firstMipIdInTail = out.firstMipIdInTail;
1134
1135 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
1136 if (ret != ADDR_OK)
1137 return ret;
1138
1139 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1140 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1141 surf->htile_size = hout.htileBytes;
1142 surf->htile_slice_size = hout.sliceSize;
1143 surf->htile_alignment = hout.baseAlign;
1144 return 0;
1145 }
1146
1147 {
1148 /* Compute tile swizzle for the color surface.
1149 * All *_X and *_T modes can use the swizzle.
1150 */
1151 if (config->info.surf_index &&
1152 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
1153 !out.mipChainInTail &&
1154 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1155 !in->flags.display) {
1156 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1157 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1158
1159 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1160 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1161
1162 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
1163 xin.flags = in->flags;
1164 xin.swizzleMode = in->swizzleMode;
1165 xin.resourceType = in->resourceType;
1166 xin.format = in->format;
1167 xin.numSamples = in->numSamples;
1168 xin.numFrags = in->numFrags;
1169
1170 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1171 if (ret != ADDR_OK)
1172 return ret;
1173
1174 assert(xout.pipeBankXor <=
1175 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1176 surf->tile_swizzle = xout.pipeBankXor;
1177 }
1178
1179 /* DCC */
1180 if (info->has_graphics &&
1181 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1182 !compressed &&
1183 is_dcc_supported_by_CB(info, in->swizzleMode) &&
1184 (!in->flags.display ||
1185 is_dcc_supported_by_DCN(info, config, surf,
1186 !in->flags.metaRbUnaligned,
1187 !in->flags.metaPipeUnaligned))) {
1188 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1189 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1190 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1191
1192 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1193 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1194 dout.pMipInfo = meta_mip_info;
1195
1196 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1197 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1198 din.colorFlags = in->flags;
1199 din.resourceType = in->resourceType;
1200 din.swizzleMode = in->swizzleMode;
1201 din.bpp = in->bpp;
1202 din.unalignedWidth = in->width;
1203 din.unalignedHeight = in->height;
1204 din.numSlices = in->numSlices;
1205 din.numFrags = in->numFrags;
1206 din.numMipLevels = in->numMipLevels;
1207 din.dataSurfaceSize = out.surfSize;
1208 din.firstMipIdInTail = out.firstMipIdInTail;
1209
1210 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1211 if (ret != ADDR_OK)
1212 return ret;
1213
1214 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1215 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1216 surf->dcc_size = dout.dccRamSize;
1217 surf->dcc_alignment = dout.dccRamBaseAlign;
1218 surf->num_dcc_levels = in->numMipLevels;
1219
1220 /* Disable DCC for levels that are in the mip tail.
1221 *
1222 * There are two issues that this is intended to
1223 * address:
1224 *
1225 * 1. Multiple mip levels may share a cache line. This
1226 * can lead to corruption when switching between
1227 * rendering to different mip levels because the
1228 * RBs don't maintain coherency.
1229 *
1230 * 2. Texturing with metadata after rendering sometimes
1231 * fails with corruption, probably for a similar
1232 * reason.
1233 *
1234 * Working around these issues for all levels in the
1235 * mip tail may be overly conservative, but it's what
1236 * Vulkan does.
1237 *
1238 * Alternative solutions that also work but are worse:
1239 * - Disable DCC entirely.
1240 * - Flush TC L2 after rendering.
1241 */
1242 for (unsigned i = 0; i < in->numMipLevels; i++) {
1243 if (meta_mip_info[i].inMiptail) {
1244 surf->num_dcc_levels = i;
1245 break;
1246 }
1247 }
1248
1249 if (!surf->num_dcc_levels)
1250 surf->dcc_size = 0;
1251
1252 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1253 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1254 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1255
1256 /* Compute displayable DCC. */
1257 if (in->flags.display &&
1258 surf->num_dcc_levels &&
1259 info->use_display_dcc_with_retile_blit) {
1260 /* Compute displayable DCC info. */
1261 din.dccKeyFlags.pipeAligned = 0;
1262 din.dccKeyFlags.rbAligned = 0;
1263
1264 assert(din.numSlices == 1);
1265 assert(din.numMipLevels == 1);
1266 assert(din.numFrags == 1);
1267 assert(surf->tile_swizzle == 0);
1268 assert(surf->u.gfx9.dcc.pipe_aligned ||
1269 surf->u.gfx9.dcc.rb_aligned);
1270
1271 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1272 if (ret != ADDR_OK)
1273 return ret;
1274
1275 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1276 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1277 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1278 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1279
1280 /* Compute address mapping from non-displayable to displayable DCC. */
1281 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {};
1282 addrin.size = sizeof(addrin);
1283 addrin.colorFlags.color = 1;
1284 addrin.swizzleMode = din.swizzleMode;
1285 addrin.resourceType = din.resourceType;
1286 addrin.bpp = din.bpp;
1287 addrin.unalignedWidth = din.unalignedWidth;
1288 addrin.unalignedHeight = din.unalignedHeight;
1289 addrin.numSlices = 1;
1290 addrin.numMipLevels = 1;
1291 addrin.numFrags = 1;
1292
1293 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {};
1294 addrout.size = sizeof(addrout);
1295
1296 surf->u.gfx9.dcc_retile_num_elements =
1297 DIV_ROUND_UP(in->width, dout.compressBlkWidth) *
1298 DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2;
1299 /* Align the size to 4 (for the compute shader). */
1300 surf->u.gfx9.dcc_retile_num_elements =
1301 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1302
1303 surf->u.gfx9.dcc_retile_map =
1304 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1305 if (!surf->u.gfx9.dcc_retile_map)
1306 return ADDR_OUTOFMEMORY;
1307
1308 unsigned index = 0;
1309 surf->u.gfx9.dcc_retile_use_uint16 = true;
1310
1311 for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) {
1312 addrin.y = y;
1313
1314 for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) {
1315 addrin.x = x;
1316
1317 /* Compute src DCC address */
1318 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1319 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1320 addrout.addr = 0;
1321
1322 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1323 if (ret != ADDR_OK)
1324 return ret;
1325
1326 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1327 if (addrout.addr > UINT16_MAX)
1328 surf->u.gfx9.dcc_retile_use_uint16 = false;
1329
1330 /* Compute dst DCC address */
1331 addrin.dccKeyFlags.pipeAligned = 0;
1332 addrin.dccKeyFlags.rbAligned = 0;
1333 addrout.addr = 0;
1334
1335 ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout);
1336 if (ret != ADDR_OK)
1337 return ret;
1338
1339 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1340 if (addrout.addr > UINT16_MAX)
1341 surf->u.gfx9.dcc_retile_use_uint16 = false;
1342
1343 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1344 index++;
1345 }
1346 }
1347 /* Fill the remaining pairs with the last one (for the compute shader). */
1348 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1349 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1350 }
1351 }
1352
1353 /* FMASK */
1354 if (in->numSamples > 1 && info->has_graphics &&
1355 !(surf->flags & RADEON_SURF_NO_FMASK)) {
1356 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1357 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1358
1359 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1360 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1361
1362 ret = gfx9_get_preferred_swizzle_mode(addrlib, surf, in,
1363 true, &fin.swizzleMode);
1364 if (ret != ADDR_OK)
1365 return ret;
1366
1367 fin.unalignedWidth = in->width;
1368 fin.unalignedHeight = in->height;
1369 fin.numSlices = in->numSlices;
1370 fin.numSamples = in->numSamples;
1371 fin.numFrags = in->numFrags;
1372
1373 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1374 if (ret != ADDR_OK)
1375 return ret;
1376
1377 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1378 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1379 surf->fmask_size = fout.fmaskBytes;
1380 surf->fmask_alignment = fout.baseAlign;
1381
1382 /* Compute tile swizzle for the FMASK surface. */
1383 if (config->info.fmask_surf_index &&
1384 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1385 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1386 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1387 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1388
1389 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1390 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1391
1392 /* This counter starts from 1 instead of 0. */
1393 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1394 xin.flags = in->flags;
1395 xin.swizzleMode = fin.swizzleMode;
1396 xin.resourceType = in->resourceType;
1397 xin.format = in->format;
1398 xin.numSamples = in->numSamples;
1399 xin.numFrags = in->numFrags;
1400
1401 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1402 if (ret != ADDR_OK)
1403 return ret;
1404
1405 assert(xout.pipeBankXor <=
1406 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1407 surf->fmask_tile_swizzle = xout.pipeBankXor;
1408 }
1409 }
1410
1411 /* CMASK -- on GFX10 only for FMASK */
1412 if (in->swizzleMode != ADDR_SW_LINEAR &&
1413 in->resourceType == ADDR_RSRC_TEX_2D &&
1414 ((info->chip_class <= GFX9 && in->numSamples == 1) ||
1415 (surf->fmask_size && in->numSamples >= 2))) {
1416 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1417 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1418
1419 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1420 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1421
1422 if (in->numSamples > 1) {
1423 /* FMASK is always aligned. */
1424 cin.cMaskFlags.pipeAligned = 1;
1425 cin.cMaskFlags.rbAligned = 1;
1426 } else {
1427 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1428 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1429 }
1430 cin.colorFlags = in->flags;
1431 cin.resourceType = in->resourceType;
1432 cin.unalignedWidth = in->width;
1433 cin.unalignedHeight = in->height;
1434 cin.numSlices = in->numSlices;
1435
1436 if (in->numSamples > 1)
1437 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1438 else
1439 cin.swizzleMode = in->swizzleMode;
1440
1441 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1442 if (ret != ADDR_OK)
1443 return ret;
1444
1445 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1446 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1447 surf->cmask_size = cout.cmaskBytes;
1448 surf->cmask_alignment = cout.baseAlign;
1449 }
1450 }
1451
1452 return 0;
1453 }
1454
1455 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1456 const struct radeon_info *info,
1457 const struct ac_surf_config *config,
1458 enum radeon_surf_mode mode,
1459 struct radeon_surf *surf)
1460 {
1461 bool compressed;
1462 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1463 int r;
1464
1465 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1466
1467 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1468
1469 /* The format must be set correctly for the allocation of compressed
1470 * textures to work. In other cases, setting the bpp is sufficient. */
1471 if (compressed) {
1472 switch (surf->bpe) {
1473 case 8:
1474 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1475 break;
1476 case 16:
1477 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1478 break;
1479 default:
1480 assert(0);
1481 }
1482 } else {
1483 switch (surf->bpe) {
1484 case 1:
1485 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1486 AddrSurfInfoIn.format = ADDR_FMT_8;
1487 break;
1488 case 2:
1489 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1490 !(surf->flags & RADEON_SURF_SBUFFER));
1491 AddrSurfInfoIn.format = ADDR_FMT_16;
1492 break;
1493 case 4:
1494 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1495 !(surf->flags & RADEON_SURF_SBUFFER));
1496 AddrSurfInfoIn.format = ADDR_FMT_32;
1497 break;
1498 case 8:
1499 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1500 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1501 break;
1502 case 12:
1503 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1504 AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
1505 break;
1506 case 16:
1507 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1508 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1509 break;
1510 default:
1511 assert(0);
1512 }
1513 AddrSurfInfoIn.bpp = surf->bpe * 8;
1514 }
1515
1516 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
1517 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1518 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1519 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1520 /* flags.texture currently refers to TC-compatible HTILE */
1521 AddrSurfInfoIn.flags.texture = 1;
1522 AddrSurfInfoIn.flags.opt4space = 1;
1523
1524 AddrSurfInfoIn.numMipLevels = config->info.levels;
1525 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1526 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1527
1528 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1529 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1530
1531 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1532 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1533 * must sample 1D textures as 2D. */
1534 if (config->is_3d)
1535 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1536 else if (info->chip_class != GFX9 && config->is_1d)
1537 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
1538 else
1539 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1540
1541 AddrSurfInfoIn.width = config->info.width;
1542 AddrSurfInfoIn.height = config->info.height;
1543
1544 if (config->is_3d)
1545 AddrSurfInfoIn.numSlices = config->info.depth;
1546 else if (config->is_cube)
1547 AddrSurfInfoIn.numSlices = 6;
1548 else
1549 AddrSurfInfoIn.numSlices = config->info.array_size;
1550
1551 /* This is propagated to HTILE/DCC/CMASK. */
1552 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1553 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1554
1555 /* The display hardware can only read DCC with RB_ALIGNED=0 and
1556 * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED.
1557 *
1558 * The CB block requires RB_ALIGNED=1 except 1 RB chips.
1559 * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
1560 * after rendering, so PIPE_ALIGNED=1 is recommended.
1561 */
1562 if (info->use_display_dcc_unaligned &&
1563 AddrSurfInfoIn.flags.display) {
1564 AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
1565 AddrSurfInfoIn.flags.metaRbUnaligned = 1;
1566 }
1567
1568 switch (mode) {
1569 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1570 assert(config->info.samples <= 1);
1571 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1572 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1573 break;
1574
1575 case RADEON_SURF_MODE_1D:
1576 case RADEON_SURF_MODE_2D:
1577 if (surf->flags & (RADEON_SURF_IMPORTED | RADEON_SURF_FORCE_SWIZZLE_MODE)) {
1578 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1579 break;
1580 }
1581
1582 r = gfx9_get_preferred_swizzle_mode(addrlib, surf, &AddrSurfInfoIn,
1583 false, &AddrSurfInfoIn.swizzleMode);
1584 if (r)
1585 return r;
1586 break;
1587
1588 default:
1589 assert(0);
1590 }
1591
1592 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1593 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1594
1595 surf->num_dcc_levels = 0;
1596 surf->surf_size = 0;
1597 surf->fmask_size = 0;
1598 surf->dcc_size = 0;
1599 surf->htile_size = 0;
1600 surf->htile_slice_size = 0;
1601 surf->u.gfx9.surf_offset = 0;
1602 surf->u.gfx9.stencil_offset = 0;
1603 surf->cmask_size = 0;
1604 surf->u.gfx9.dcc_retile_use_uint16 = false;
1605 surf->u.gfx9.dcc_retile_num_elements = 0;
1606 surf->u.gfx9.dcc_retile_map = NULL;
1607
1608 /* Calculate texture layout information. */
1609 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1610 &AddrSurfInfoIn);
1611 if (r)
1612 goto error;
1613
1614 /* Calculate texture layout information for stencil. */
1615 if (surf->flags & RADEON_SURF_SBUFFER) {
1616 AddrSurfInfoIn.flags.stencil = 1;
1617 AddrSurfInfoIn.bpp = 8;
1618 AddrSurfInfoIn.format = ADDR_FMT_8;
1619
1620 if (!AddrSurfInfoIn.flags.depth) {
1621 r = gfx9_get_preferred_swizzle_mode(addrlib, surf, &AddrSurfInfoIn,
1622 false, &AddrSurfInfoIn.swizzleMode);
1623 if (r)
1624 goto error;
1625 } else
1626 AddrSurfInfoIn.flags.depth = 0;
1627
1628 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1629 &AddrSurfInfoIn);
1630 if (r)
1631 goto error;
1632 }
1633
1634 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1635 surf->tc_compatible_htile_allowed = surf->htile_size != 0;
1636
1637 /* Query whether the surface is displayable. */
1638 /* This is only useful for surfaces that are allocated without SCANOUT. */
1639 bool displayable = false;
1640 if (!config->is_3d && !config->is_cube) {
1641 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1642 surf->bpe * 8, &displayable);
1643 if (r)
1644 goto error;
1645
1646 /* Display needs unaligned DCC. */
1647 if (surf->num_dcc_levels &&
1648 !is_dcc_supported_by_DCN(info, config, surf,
1649 surf->u.gfx9.dcc.rb_aligned,
1650 surf->u.gfx9.dcc.pipe_aligned))
1651 displayable = false;
1652 }
1653 surf->is_displayable = displayable;
1654
1655 /* Validate that we allocated a displayable surface if requested. */
1656 assert(!AddrSurfInfoIn.flags.display || surf->is_displayable);
1657
1658 switch (surf->u.gfx9.surf.swizzle_mode) {
1659 /* S = standard. */
1660 case ADDR_SW_256B_S:
1661 case ADDR_SW_4KB_S:
1662 case ADDR_SW_64KB_S:
1663 case ADDR_SW_64KB_S_T:
1664 case ADDR_SW_4KB_S_X:
1665 case ADDR_SW_64KB_S_X:
1666 surf->micro_tile_mode = RADEON_MICRO_MODE_STANDARD;
1667 break;
1668
1669 /* D = display. */
1670 case ADDR_SW_LINEAR:
1671 case ADDR_SW_256B_D:
1672 case ADDR_SW_4KB_D:
1673 case ADDR_SW_64KB_D:
1674 case ADDR_SW_64KB_D_T:
1675 case ADDR_SW_4KB_D_X:
1676 case ADDR_SW_64KB_D_X:
1677 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1678 break;
1679
1680 /* R = rotated (gfx9), render target (gfx10). */
1681 case ADDR_SW_256B_R:
1682 case ADDR_SW_4KB_R:
1683 case ADDR_SW_64KB_R:
1684 case ADDR_SW_64KB_R_T:
1685 case ADDR_SW_4KB_R_X:
1686 case ADDR_SW_64KB_R_X:
1687 case ADDR_SW_VAR_R_X:
1688 /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
1689 * used at the same time. We currently do not use rotated
1690 * in gfx9.
1691 */
1692 assert(info->chip_class >= GFX10 ||
1693 !"rotate micro tile mode is unsupported");
1694 surf->micro_tile_mode = RADEON_MICRO_MODE_RENDER;
1695 break;
1696
1697 /* Z = depth. */
1698 case ADDR_SW_4KB_Z:
1699 case ADDR_SW_64KB_Z:
1700 case ADDR_SW_64KB_Z_T:
1701 case ADDR_SW_4KB_Z_X:
1702 case ADDR_SW_64KB_Z_X:
1703 case ADDR_SW_VAR_Z_X:
1704 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1705 break;
1706
1707 default:
1708 assert(0);
1709 }
1710
1711 return 0;
1712
1713 error:
1714 free(surf->u.gfx9.dcc_retile_map);
1715 surf->u.gfx9.dcc_retile_map = NULL;
1716 return r;
1717 }
1718
1719 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1720 const struct ac_surf_config *config,
1721 enum radeon_surf_mode mode,
1722 struct radeon_surf *surf)
1723 {
1724 int r;
1725
1726 r = surf_config_sanity(config, surf->flags);
1727 if (r)
1728 return r;
1729
1730 if (info->chip_class >= GFX9)
1731 r = gfx9_compute_surface(addrlib, info, config, mode, surf);
1732 else
1733 r = gfx6_compute_surface(addrlib, info, config, mode, surf);
1734
1735 if (r)
1736 return r;
1737
1738 /* Determine the memory layout of multiple allocations in one buffer. */
1739 surf->total_size = surf->surf_size;
1740
1741 if (surf->htile_size) {
1742 surf->htile_offset = align64(surf->total_size, surf->htile_alignment);
1743 surf->total_size = surf->htile_offset + surf->htile_size;
1744 }
1745
1746 if (surf->fmask_size) {
1747 assert(config->info.samples >= 2);
1748 surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment);
1749 surf->total_size = surf->fmask_offset + surf->fmask_size;
1750 }
1751
1752 /* Single-sample CMASK is in a separate buffer. */
1753 if (surf->cmask_size && config->info.samples >= 2) {
1754 surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
1755 surf->total_size = surf->cmask_offset + surf->cmask_size;
1756 }
1757
1758 if (surf->dcc_size &&
1759 /* dcc_size is computed on GFX9+ only if it's displayable. */
1760 (info->chip_class >= GFX9 || !get_display_flag(config, surf))) {
1761 surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment);
1762 surf->total_size = surf->dcc_offset + surf->dcc_size;
1763
1764 if (info->chip_class >= GFX9 &&
1765 surf->u.gfx9.dcc_retile_num_elements) {
1766 /* Add space for the displayable DCC buffer. */
1767 surf->display_dcc_offset =
1768 align64(surf->total_size, surf->u.gfx9.display_dcc_alignment);
1769 surf->total_size = surf->display_dcc_offset +
1770 surf->u.gfx9.display_dcc_size;
1771
1772 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1773 surf->dcc_retile_map_offset =
1774 align64(surf->total_size, info->tcc_cache_line_size);
1775
1776 if (surf->u.gfx9.dcc_retile_use_uint16) {
1777 surf->total_size = surf->dcc_retile_map_offset +
1778 surf->u.gfx9.dcc_retile_num_elements * 2;
1779 } else {
1780 surf->total_size = surf->dcc_retile_map_offset +
1781 surf->u.gfx9.dcc_retile_num_elements * 4;
1782 }
1783 }
1784 }
1785
1786 return 0;
1787 }