2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
40 #include <amdgpu_drm.h>
42 #include "addrlib/addrinterface.h"
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
52 static unsigned get_first(unsigned x
, unsigned y
)
57 static void addrlib_family_rev_id(enum radeon_family family
,
58 unsigned *addrlib_family
,
59 unsigned *addrlib_revid
)
63 *addrlib_family
= FAMILY_SI
;
64 *addrlib_revid
= get_first(AMDGPU_TAHITI_RANGE
);
67 *addrlib_family
= FAMILY_SI
;
68 *addrlib_revid
= get_first(AMDGPU_PITCAIRN_RANGE
);
71 *addrlib_family
= FAMILY_SI
;
72 *addrlib_revid
= get_first(AMDGPU_CAPEVERDE_RANGE
);
75 *addrlib_family
= FAMILY_SI
;
76 *addrlib_revid
= get_first(AMDGPU_OLAND_RANGE
);
79 *addrlib_family
= FAMILY_SI
;
80 *addrlib_revid
= get_first(AMDGPU_HAINAN_RANGE
);
83 *addrlib_family
= FAMILY_CI
;
84 *addrlib_revid
= get_first(AMDGPU_BONAIRE_RANGE
);
87 *addrlib_family
= FAMILY_KV
;
88 *addrlib_revid
= get_first(AMDGPU_SPECTRE_RANGE
);
91 *addrlib_family
= FAMILY_KV
;
92 *addrlib_revid
= get_first(AMDGPU_KALINDI_RANGE
);
95 *addrlib_family
= FAMILY_CI
;
96 *addrlib_revid
= get_first(AMDGPU_HAWAII_RANGE
);
99 *addrlib_family
= FAMILY_KV
;
100 *addrlib_revid
= get_first(AMDGPU_GODAVARI_RANGE
);
103 *addrlib_family
= FAMILY_VI
;
104 *addrlib_revid
= get_first(AMDGPU_TONGA_RANGE
);
107 *addrlib_family
= FAMILY_VI
;
108 *addrlib_revid
= get_first(AMDGPU_ICELAND_RANGE
);
111 *addrlib_family
= FAMILY_CZ
;
112 *addrlib_revid
= get_first(AMDGPU_CARRIZO_RANGE
);
115 *addrlib_family
= FAMILY_CZ
;
116 *addrlib_revid
= get_first(AMDGPU_STONEY_RANGE
);
119 *addrlib_family
= FAMILY_VI
;
120 *addrlib_revid
= get_first(AMDGPU_FIJI_RANGE
);
123 *addrlib_family
= FAMILY_VI
;
124 *addrlib_revid
= get_first(AMDGPU_POLARIS10_RANGE
);
127 *addrlib_family
= FAMILY_VI
;
128 *addrlib_revid
= get_first(AMDGPU_POLARIS11_RANGE
);
131 *addrlib_family
= FAMILY_VI
;
132 *addrlib_revid
= get_first(AMDGPU_POLARIS12_RANGE
);
135 *addrlib_family
= FAMILY_AI
;
136 *addrlib_revid
= get_first(AMDGPU_VEGA10_RANGE
);
139 *addrlib_family
= FAMILY_AI
;
140 *addrlib_revid
= get_first(AMDGPU_VEGA12_RANGE
);
143 *addrlib_family
= FAMILY_RV
;
144 *addrlib_revid
= get_first(AMDGPU_RAVEN_RANGE
);
147 fprintf(stderr
, "amdgpu: Unknown family.\n");
151 static void *ADDR_API
allocSysMem(const ADDR_ALLOCSYSMEM_INPUT
* pInput
)
153 return malloc(pInput
->sizeInBytes
);
156 static ADDR_E_RETURNCODE ADDR_API
freeSysMem(const ADDR_FREESYSMEM_INPUT
* pInput
)
158 free(pInput
->pVirtAddr
);
162 ADDR_HANDLE
amdgpu_addr_create(const struct radeon_info
*info
,
163 const struct amdgpu_gpu_info
*amdinfo
,
164 uint64_t *max_alignment
)
166 ADDR_CREATE_INPUT addrCreateInput
= {0};
167 ADDR_CREATE_OUTPUT addrCreateOutput
= {0};
168 ADDR_REGISTER_VALUE regValue
= {0};
169 ADDR_CREATE_FLAGS createFlags
= {{0}};
170 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput
= {0};
171 ADDR_E_RETURNCODE addrRet
;
173 addrCreateInput
.size
= sizeof(ADDR_CREATE_INPUT
);
174 addrCreateOutput
.size
= sizeof(ADDR_CREATE_OUTPUT
);
176 regValue
.gbAddrConfig
= amdinfo
->gb_addr_cfg
;
177 createFlags
.value
= 0;
179 addrlib_family_rev_id(info
->family
, &addrCreateInput
.chipFamily
, &addrCreateInput
.chipRevision
);
180 if (addrCreateInput
.chipFamily
== FAMILY_UNKNOWN
)
183 if (addrCreateInput
.chipFamily
>= FAMILY_AI
) {
184 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_ARCTICISLAND
;
185 regValue
.blockVarSizeLog2
= 0;
187 regValue
.noOfBanks
= amdinfo
->mc_arb_ramcfg
& 0x3;
188 regValue
.noOfRanks
= (amdinfo
->mc_arb_ramcfg
& 0x4) >> 2;
190 regValue
.backendDisables
= amdinfo
->enabled_rb_pipes_mask
;
191 regValue
.pTileConfig
= amdinfo
->gb_tile_mode
;
192 regValue
.noOfEntries
= ARRAY_SIZE(amdinfo
->gb_tile_mode
);
193 if (addrCreateInput
.chipFamily
== FAMILY_SI
) {
194 regValue
.pMacroTileConfig
= NULL
;
195 regValue
.noOfMacroEntries
= 0;
197 regValue
.pMacroTileConfig
= amdinfo
->gb_macro_tile_mode
;
198 regValue
.noOfMacroEntries
= ARRAY_SIZE(amdinfo
->gb_macro_tile_mode
);
201 createFlags
.useTileIndex
= 1;
202 createFlags
.useHtileSliceAlign
= 1;
204 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_SOUTHERNISLAND
;
207 addrCreateInput
.callbacks
.allocSysMem
= allocSysMem
;
208 addrCreateInput
.callbacks
.freeSysMem
= freeSysMem
;
209 addrCreateInput
.callbacks
.debugPrint
= 0;
210 addrCreateInput
.createFlags
= createFlags
;
211 addrCreateInput
.regValue
= regValue
;
213 addrRet
= AddrCreate(&addrCreateInput
, &addrCreateOutput
);
214 if (addrRet
!= ADDR_OK
)
218 addrRet
= AddrGetMaxAlignments(addrCreateOutput
.hLib
, &addrGetMaxAlignmentsOutput
);
219 if (addrRet
== ADDR_OK
){
220 *max_alignment
= addrGetMaxAlignmentsOutput
.baseAlign
;
223 return addrCreateOutput
.hLib
;
226 static int surf_config_sanity(const struct ac_surf_config
*config
)
228 /* all dimension must be at least 1 ! */
229 if (!config
->info
.width
|| !config
->info
.height
|| !config
->info
.depth
||
230 !config
->info
.array_size
|| !config
->info
.levels
)
233 switch (config
->info
.samples
) {
244 if (config
->is_3d
&& config
->info
.array_size
> 1)
246 if (config
->is_cube
&& config
->info
.depth
> 1)
252 static int gfx6_compute_level(ADDR_HANDLE addrlib
,
253 const struct ac_surf_config
*config
,
254 struct radeon_surf
*surf
, bool is_stencil
,
255 unsigned level
, bool compressed
,
256 ADDR_COMPUTE_SURFACE_INFO_INPUT
*AddrSurfInfoIn
,
257 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
*AddrSurfInfoOut
,
258 ADDR_COMPUTE_DCCINFO_INPUT
*AddrDccIn
,
259 ADDR_COMPUTE_DCCINFO_OUTPUT
*AddrDccOut
,
260 ADDR_COMPUTE_HTILE_INFO_INPUT
*AddrHtileIn
,
261 ADDR_COMPUTE_HTILE_INFO_OUTPUT
*AddrHtileOut
)
263 struct legacy_surf_level
*surf_level
;
264 ADDR_E_RETURNCODE ret
;
266 AddrSurfInfoIn
->mipLevel
= level
;
267 AddrSurfInfoIn
->width
= u_minify(config
->info
.width
, level
);
268 AddrSurfInfoIn
->height
= u_minify(config
->info
.height
, level
);
270 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
271 * because GFX9 needs linear alignment of 256 bytes.
273 if (config
->info
.levels
== 1 &&
274 AddrSurfInfoIn
->tileMode
== ADDR_TM_LINEAR_ALIGNED
&&
275 AddrSurfInfoIn
->bpp
) {
276 unsigned alignment
= 256 / (AddrSurfInfoIn
->bpp
/ 8);
278 assert(util_is_power_of_two_or_zero(AddrSurfInfoIn
->bpp
));
279 AddrSurfInfoIn
->width
= align(AddrSurfInfoIn
->width
, alignment
);
283 AddrSurfInfoIn
->numSlices
= u_minify(config
->info
.depth
, level
);
284 else if (config
->is_cube
)
285 AddrSurfInfoIn
->numSlices
= 6;
287 AddrSurfInfoIn
->numSlices
= config
->info
.array_size
;
290 /* Set the base level pitch. This is needed for calculation
291 * of non-zero levels. */
293 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.stencil_level
[0].nblk_x
;
295 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.level
[0].nblk_x
;
297 /* Convert blocks to pixels for compressed formats. */
299 AddrSurfInfoIn
->basePitch
*= surf
->blk_w
;
302 ret
= AddrComputeSurfaceInfo(addrlib
,
305 if (ret
!= ADDR_OK
) {
309 surf_level
= is_stencil
? &surf
->u
.legacy
.stencil_level
[level
] : &surf
->u
.legacy
.level
[level
];
310 surf_level
->offset
= align64(surf
->surf_size
, AddrSurfInfoOut
->baseAlign
);
311 surf_level
->slice_size_dw
= AddrSurfInfoOut
->sliceSize
/ 4;
312 surf_level
->nblk_x
= AddrSurfInfoOut
->pitch
;
313 surf_level
->nblk_y
= AddrSurfInfoOut
->height
;
315 switch (AddrSurfInfoOut
->tileMode
) {
316 case ADDR_TM_LINEAR_ALIGNED
:
317 surf_level
->mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
319 case ADDR_TM_1D_TILED_THIN1
:
320 surf_level
->mode
= RADEON_SURF_MODE_1D
;
322 case ADDR_TM_2D_TILED_THIN1
:
323 surf_level
->mode
= RADEON_SURF_MODE_2D
;
330 surf
->u
.legacy
.stencil_tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
332 surf
->u
.legacy
.tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
334 surf
->surf_size
= surf_level
->offset
+ AddrSurfInfoOut
->surfSize
;
336 /* Clear DCC fields at the beginning. */
337 surf_level
->dcc_offset
= 0;
339 /* The previous level's flag tells us if we can use DCC for this level. */
340 if (AddrSurfInfoIn
->flags
.dccCompatible
&&
341 (level
== 0 || AddrDccOut
->subLvlCompressible
)) {
342 AddrDccIn
->colorSurfSize
= AddrSurfInfoOut
->surfSize
;
343 AddrDccIn
->tileMode
= AddrSurfInfoOut
->tileMode
;
344 AddrDccIn
->tileInfo
= *AddrSurfInfoOut
->pTileInfo
;
345 AddrDccIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
346 AddrDccIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
348 ret
= AddrComputeDccInfo(addrlib
,
352 if (ret
== ADDR_OK
) {
353 surf_level
->dcc_offset
= surf
->dcc_size
;
354 surf_level
->dcc_fast_clear_size
= AddrDccOut
->dccFastClearSize
;
355 surf
->num_dcc_levels
= level
+ 1;
356 surf
->dcc_size
= surf_level
->dcc_offset
+ AddrDccOut
->dccRamSize
;
357 surf
->dcc_alignment
= MAX2(surf
->dcc_alignment
, AddrDccOut
->dccRamBaseAlign
);
361 /* TC-compatible HTILE. */
363 AddrSurfInfoIn
->flags
.depth
&&
364 surf_level
->mode
== RADEON_SURF_MODE_2D
&&
366 AddrHtileIn
->flags
.tcCompatible
= AddrSurfInfoIn
->flags
.tcCompatible
;
367 AddrHtileIn
->pitch
= AddrSurfInfoOut
->pitch
;
368 AddrHtileIn
->height
= AddrSurfInfoOut
->height
;
369 AddrHtileIn
->numSlices
= AddrSurfInfoOut
->depth
;
370 AddrHtileIn
->blockWidth
= ADDR_HTILE_BLOCKSIZE_8
;
371 AddrHtileIn
->blockHeight
= ADDR_HTILE_BLOCKSIZE_8
;
372 AddrHtileIn
->pTileInfo
= AddrSurfInfoOut
->pTileInfo
;
373 AddrHtileIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
374 AddrHtileIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
376 ret
= AddrComputeHtileInfo(addrlib
,
380 if (ret
== ADDR_OK
) {
381 surf
->htile_size
= AddrHtileOut
->htileBytes
;
382 surf
->htile_slice_size
= AddrHtileOut
->sliceSize
;
383 surf
->htile_alignment
= AddrHtileOut
->baseAlign
;
390 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
391 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
393 static void gfx6_set_micro_tile_mode(struct radeon_surf
*surf
,
394 const struct radeon_info
*info
)
396 uint32_t tile_mode
= info
->si_tile_mode_array
[surf
->u
.legacy
.tiling_index
[0]];
398 if (info
->chip_class
>= CIK
)
399 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE_NEW(tile_mode
);
401 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE(tile_mode
);
404 static unsigned cik_get_macro_tile_index(struct radeon_surf
*surf
)
406 unsigned index
, tileb
;
408 tileb
= 8 * 8 * surf
->bpe
;
409 tileb
= MIN2(surf
->u
.legacy
.tile_split
, tileb
);
411 for (index
= 0; tileb
> 64; index
++)
419 * This must be called after the first level is computed.
421 * Copy surface-global settings like pipe/bank config from level 0 surface
422 * computation, and compute tile swizzle.
424 static int gfx6_surface_settings(ADDR_HANDLE addrlib
,
425 const struct radeon_info
*info
,
426 const struct ac_surf_config
*config
,
427 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* csio
,
428 struct radeon_surf
*surf
)
430 surf
->surf_alignment
= csio
->baseAlign
;
431 surf
->u
.legacy
.pipe_config
= csio
->pTileInfo
->pipeConfig
- 1;
432 gfx6_set_micro_tile_mode(surf
, info
);
434 /* For 2D modes only. */
435 if (csio
->tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
436 surf
->u
.legacy
.bankw
= csio
->pTileInfo
->bankWidth
;
437 surf
->u
.legacy
.bankh
= csio
->pTileInfo
->bankHeight
;
438 surf
->u
.legacy
.mtilea
= csio
->pTileInfo
->macroAspectRatio
;
439 surf
->u
.legacy
.tile_split
= csio
->pTileInfo
->tileSplitBytes
;
440 surf
->u
.legacy
.num_banks
= csio
->pTileInfo
->banks
;
441 surf
->u
.legacy
.macro_tile_index
= csio
->macroModeIndex
;
443 surf
->u
.legacy
.macro_tile_index
= 0;
446 /* Compute tile swizzle. */
447 /* TODO: fix tile swizzle with mipmapping for SI */
448 if ((info
->chip_class
>= CIK
|| config
->info
.levels
== 1) &&
449 config
->info
.surf_index
&&
450 surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
&&
451 !(surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
| RADEON_SURF_SHAREABLE
)) &&
452 (config
->info
.samples
> 1 || !(surf
->flags
& RADEON_SURF_SCANOUT
))) {
453 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn
= {0};
454 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut
= {0};
456 AddrBaseSwizzleIn
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
457 AddrBaseSwizzleOut
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
459 AddrBaseSwizzleIn
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
460 AddrBaseSwizzleIn
.tileIndex
= csio
->tileIndex
;
461 AddrBaseSwizzleIn
.macroModeIndex
= csio
->macroModeIndex
;
462 AddrBaseSwizzleIn
.pTileInfo
= csio
->pTileInfo
;
463 AddrBaseSwizzleIn
.tileMode
= csio
->tileMode
;
465 int r
= AddrComputeBaseSwizzle(addrlib
, &AddrBaseSwizzleIn
,
466 &AddrBaseSwizzleOut
);
470 assert(AddrBaseSwizzleOut
.tileSwizzle
<=
471 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
472 surf
->tile_swizzle
= AddrBaseSwizzleOut
.tileSwizzle
;
478 * Fill in the tiling information in \p surf based on the given surface config.
480 * The following fields of \p surf must be initialized by the caller:
481 * blk_w, blk_h, bpe, flags.
483 static int gfx6_compute_surface(ADDR_HANDLE addrlib
,
484 const struct radeon_info
*info
,
485 const struct ac_surf_config
*config
,
486 enum radeon_surf_mode mode
,
487 struct radeon_surf
*surf
)
491 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
492 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut
= {0};
493 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn
= {0};
494 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut
= {0};
495 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn
= {0};
496 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut
= {0};
497 ADDR_TILEINFO AddrTileInfoIn
= {0};
498 ADDR_TILEINFO AddrTileInfoOut
= {0};
501 AddrSurfInfoIn
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT
);
502 AddrSurfInfoOut
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT
);
503 AddrDccIn
.size
= sizeof(ADDR_COMPUTE_DCCINFO_INPUT
);
504 AddrDccOut
.size
= sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT
);
505 AddrHtileIn
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT
);
506 AddrHtileOut
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT
);
507 AddrSurfInfoOut
.pTileInfo
= &AddrTileInfoOut
;
509 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
511 /* MSAA and FMASK require 2D tiling. */
512 if (config
->info
.samples
> 1 ||
513 (surf
->flags
& RADEON_SURF_FMASK
))
514 mode
= RADEON_SURF_MODE_2D
;
516 /* DB doesn't support linear layouts. */
517 if (surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
) &&
518 mode
< RADEON_SURF_MODE_1D
)
519 mode
= RADEON_SURF_MODE_1D
;
521 /* Set the requested tiling mode. */
523 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
524 AddrSurfInfoIn
.tileMode
= ADDR_TM_LINEAR_ALIGNED
;
526 case RADEON_SURF_MODE_1D
:
527 AddrSurfInfoIn
.tileMode
= ADDR_TM_1D_TILED_THIN1
;
529 case RADEON_SURF_MODE_2D
:
530 AddrSurfInfoIn
.tileMode
= ADDR_TM_2D_TILED_THIN1
;
536 /* The format must be set correctly for the allocation of compressed
537 * textures to work. In other cases, setting the bpp is sufficient.
542 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
545 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
552 AddrDccIn
.bpp
= AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
555 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numSamples
=
556 config
->info
.samples
? config
->info
.samples
: 1;
557 AddrSurfInfoIn
.tileIndex
= -1;
559 /* Set the micro tile type. */
560 if (surf
->flags
& RADEON_SURF_SCANOUT
)
561 AddrSurfInfoIn
.tileType
= ADDR_DISPLAYABLE
;
562 else if (surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
| RADEON_SURF_FMASK
))
563 AddrSurfInfoIn
.tileType
= ADDR_DEPTH_SAMPLE_ORDER
;
565 AddrSurfInfoIn
.tileType
= ADDR_NON_DISPLAYABLE
;
567 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
568 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
569 AddrSurfInfoIn
.flags
.cube
= config
->is_cube
;
570 AddrSurfInfoIn
.flags
.fmask
= (surf
->flags
& RADEON_SURF_FMASK
) != 0;
571 AddrSurfInfoIn
.flags
.display
= (surf
->flags
& RADEON_SURF_SCANOUT
) != 0;
572 AddrSurfInfoIn
.flags
.pow2Pad
= config
->info
.levels
> 1;
573 AddrSurfInfoIn
.flags
.tcCompatible
= (surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) != 0;
575 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
576 * requested, because TC-compatible HTILE requires 2D tiling.
578 AddrSurfInfoIn
.flags
.opt4Space
= !AddrSurfInfoIn
.flags
.tcCompatible
&&
579 !AddrSurfInfoIn
.flags
.fmask
&&
580 config
->info
.samples
<= 1 &&
581 (surf
->flags
& RADEON_SURF_OPTIMIZE_FOR_SPACE
);
584 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
586 * - Mipmapped array textures have low performance (discovered by a closed
589 AddrSurfInfoIn
.flags
.dccCompatible
=
590 info
->chip_class
>= VI
&&
591 !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
592 !(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
594 ((config
->info
.array_size
== 1 && config
->info
.depth
== 1) ||
595 config
->info
.levels
== 1);
597 AddrSurfInfoIn
.flags
.noStencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) == 0;
598 AddrSurfInfoIn
.flags
.compressZ
= AddrSurfInfoIn
.flags
.depth
;
600 /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
601 * for Z and stencil. This can cause a number of problems which we work
604 * - a depth part that is incompatible with mipmapped texturing
605 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
606 * incorrect tiling applied to the stencil part, stencil buffer
607 * memory accesses that go out of bounds) even without mipmapping
609 * Some piglit tests that are prone to different types of related
611 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
612 * ./bin/framebuffer-blit-levels {draw,read} stencil
613 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
614 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
615 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
617 int stencil_tile_idx
= -1;
619 if (AddrSurfInfoIn
.flags
.depth
&& !AddrSurfInfoIn
.flags
.noStencil
&&
620 (config
->info
.levels
> 1 || info
->family
== CHIP_STONEY
)) {
621 /* Compute stencilTileIdx that is compatible with the (depth)
622 * tileIdx. This degrades the depth surface if necessary to
623 * ensure that a matching stencilTileIdx exists. */
624 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 1;
626 /* Keep the depth mip-tail compatible with texturing. */
627 AddrSurfInfoIn
.flags
.noStencil
= 1;
630 /* Set preferred macrotile parameters. This is usually required
631 * for shared resources. This is for 2D tiling only. */
632 if (AddrSurfInfoIn
.tileMode
>= ADDR_TM_2D_TILED_THIN1
&&
633 surf
->u
.legacy
.bankw
&& surf
->u
.legacy
.bankh
&&
634 surf
->u
.legacy
.mtilea
&& surf
->u
.legacy
.tile_split
) {
635 assert(!(surf
->flags
& RADEON_SURF_FMASK
));
637 /* If any of these parameters are incorrect, the calculation
639 AddrTileInfoIn
.banks
= surf
->u
.legacy
.num_banks
;
640 AddrTileInfoIn
.bankWidth
= surf
->u
.legacy
.bankw
;
641 AddrTileInfoIn
.bankHeight
= surf
->u
.legacy
.bankh
;
642 AddrTileInfoIn
.macroAspectRatio
= surf
->u
.legacy
.mtilea
;
643 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.tile_split
;
644 AddrTileInfoIn
.pipeConfig
= surf
->u
.legacy
.pipe_config
+ 1; /* +1 compared to GB_TILE_MODE */
645 AddrSurfInfoIn
.flags
.opt4Space
= 0;
646 AddrSurfInfoIn
.pTileInfo
= &AddrTileInfoIn
;
648 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
649 * the tile index, because we are expected to know it if
650 * we know the other parameters.
652 * This is something that can easily be fixed in Addrlib.
653 * For now, just figure it out here.
654 * Note that only 2D_TILE_THIN1 is handled here.
656 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
657 assert(AddrSurfInfoIn
.tileMode
== ADDR_TM_2D_TILED_THIN1
);
659 if (info
->chip_class
== SI
) {
660 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
) {
662 AddrSurfInfoIn
.tileIndex
= 11; /* 16bpp */
664 AddrSurfInfoIn
.tileIndex
= 12; /* 32bpp */
667 AddrSurfInfoIn
.tileIndex
= 14; /* 8bpp */
668 else if (surf
->bpe
== 2)
669 AddrSurfInfoIn
.tileIndex
= 15; /* 16bpp */
670 else if (surf
->bpe
== 4)
671 AddrSurfInfoIn
.tileIndex
= 16; /* 32bpp */
673 AddrSurfInfoIn
.tileIndex
= 17; /* 64bpp (and 128bpp) */
677 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
)
678 AddrSurfInfoIn
.tileIndex
= 10; /* 2D displayable */
680 AddrSurfInfoIn
.tileIndex
= 14; /* 2D non-displayable */
682 /* Addrlib doesn't set this if tileIndex is forced like above. */
683 AddrSurfInfoOut
.macroModeIndex
= cik_get_macro_tile_index(surf
);
687 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
688 surf
->num_dcc_levels
= 0;
691 surf
->dcc_alignment
= 1;
692 surf
->htile_size
= 0;
693 surf
->htile_slice_size
= 0;
694 surf
->htile_alignment
= 1;
696 const bool only_stencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) &&
697 !(surf
->flags
& RADEON_SURF_ZBUFFER
);
699 /* Calculate texture layout information. */
701 for (level
= 0; level
< config
->info
.levels
; level
++) {
702 r
= gfx6_compute_level(addrlib
, config
, surf
, false, level
, compressed
,
703 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
704 &AddrDccIn
, &AddrDccOut
, &AddrHtileIn
, &AddrHtileOut
);
711 /* Check that we actually got a TC-compatible HTILE if
712 * we requested it (only for level 0, since we're not
713 * supporting HTILE on higher mip levels anyway). */
714 assert(AddrSurfInfoOut
.tcCompatible
||
715 !AddrSurfInfoIn
.flags
.tcCompatible
||
716 AddrSurfInfoIn
.flags
.matchStencilTileCfg
);
718 if (AddrSurfInfoIn
.flags
.matchStencilTileCfg
) {
719 if (!AddrSurfInfoOut
.tcCompatible
) {
720 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
721 surf
->flags
&= ~RADEON_SURF_TC_COMPATIBLE_HTILE
;
724 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 0;
725 AddrSurfInfoIn
.tileIndex
= AddrSurfInfoOut
.tileIndex
;
726 stencil_tile_idx
= AddrSurfInfoOut
.stencilTileIdx
;
728 assert(stencil_tile_idx
>= 0);
731 r
= gfx6_surface_settings(addrlib
, info
, config
,
732 &AddrSurfInfoOut
, surf
);
738 /* Calculate texture layout information for stencil. */
739 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
740 AddrSurfInfoIn
.tileIndex
= stencil_tile_idx
;
741 AddrSurfInfoIn
.bpp
= 8;
742 AddrSurfInfoIn
.flags
.depth
= 0;
743 AddrSurfInfoIn
.flags
.stencil
= 1;
744 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
745 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
746 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.stencil_tile_split
;
748 for (level
= 0; level
< config
->info
.levels
; level
++) {
749 r
= gfx6_compute_level(addrlib
, config
, surf
, true, level
, compressed
,
750 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
751 &AddrDccIn
, &AddrDccOut
,
756 /* DB uses the depth pitch for both stencil and depth. */
758 if (surf
->u
.legacy
.stencil_level
[level
].nblk_x
!=
759 surf
->u
.legacy
.level
[level
].nblk_x
)
760 surf
->u
.legacy
.stencil_adjusted
= true;
762 surf
->u
.legacy
.level
[level
].nblk_x
=
763 surf
->u
.legacy
.stencil_level
[level
].nblk_x
;
768 r
= gfx6_surface_settings(addrlib
, info
, config
,
769 &AddrSurfInfoOut
, surf
);
774 /* For 2D modes only. */
775 if (AddrSurfInfoOut
.tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
776 surf
->u
.legacy
.stencil_tile_split
=
777 AddrSurfInfoOut
.pTileInfo
->tileSplitBytes
;
783 /* Recalculate the whole DCC miptree size including disabled levels.
784 * This is what addrlib does, but calling addrlib would be a lot more
787 if (surf
->dcc_size
&& config
->info
.levels
> 1) {
788 /* The smallest miplevels that are never compressed by DCC
789 * still read the DCC buffer via TC if the base level uses DCC,
790 * and for some reason the DCC buffer needs to be larger if
791 * the miptree uses non-zero tile_swizzle. Otherwise there are
794 * "dcc_alignment * 4" was determined by trial and error.
796 surf
->dcc_size
= align64(surf
->surf_size
>> 8,
797 surf
->dcc_alignment
* 4);
800 /* Make sure HTILE covers the whole miptree, because the shader reads
801 * TC-compatible HTILE even for levels where it's disabled by DB.
803 if (surf
->htile_size
&& config
->info
.levels
> 1)
804 surf
->htile_size
*= 2;
806 surf
->is_linear
= surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
;
807 surf
->is_displayable
= surf
->is_linear
||
808 surf
->micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
||
809 surf
->micro_tile_mode
== RADEON_MICRO_MODE_ROTATED
;
813 /* This is only called when expecting a tiled layout. */
815 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib
,
816 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
,
817 bool is_fmask
, unsigned flags
,
818 AddrSwizzleMode
*swizzle_mode
)
820 ADDR_E_RETURNCODE ret
;
821 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin
= {0};
822 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout
= {0};
824 sin
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
);
825 sout
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
);
827 sin
.flags
= in
->flags
;
828 sin
.resourceType
= in
->resourceType
;
829 sin
.format
= in
->format
;
830 sin
.resourceLoction
= ADDR_RSRC_LOC_INVIS
;
831 /* TODO: We could allow some of these: */
832 sin
.forbiddenBlock
.micro
= 1; /* don't allow the 256B swizzle modes */
833 sin
.forbiddenBlock
.var
= 1; /* don't allow the variable-sized swizzle modes */
834 sin
.forbiddenBlock
.linear
= 1; /* don't allow linear swizzle modes */
836 sin
.width
= in
->width
;
837 sin
.height
= in
->height
;
838 sin
.numSlices
= in
->numSlices
;
839 sin
.numMipLevels
= in
->numMipLevels
;
840 sin
.numSamples
= in
->numSamples
;
841 sin
.numFrags
= in
->numFrags
;
843 if (flags
& RADEON_SURF_SCANOUT
)
844 sin
.preferredSwSet
.sw_D
= 1;
845 else if (in
->flags
.depth
|| in
->flags
.stencil
|| is_fmask
)
846 sin
.preferredSwSet
.sw_Z
= 1;
848 sin
.preferredSwSet
.sw_S
= 1;
855 ret
= Addr2GetPreferredSurfaceSetting(addrlib
, &sin
, &sout
);
859 *swizzle_mode
= sout
.swizzleMode
;
863 static int gfx9_compute_miptree(ADDR_HANDLE addrlib
,
864 const struct ac_surf_config
*config
,
865 struct radeon_surf
*surf
, bool compressed
,
866 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
)
868 ADDR2_MIP_INFO mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
869 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out
= {0};
870 ADDR_E_RETURNCODE ret
;
872 out
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
);
873 out
.pMipInfo
= mip_info
;
875 ret
= Addr2ComputeSurfaceInfo(addrlib
, in
, &out
);
879 if (in
->flags
.stencil
) {
880 surf
->u
.gfx9
.stencil
.swizzle_mode
= in
->swizzleMode
;
881 surf
->u
.gfx9
.stencil
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
882 out
.mipChainPitch
- 1;
883 surf
->surf_alignment
= MAX2(surf
->surf_alignment
, out
.baseAlign
);
884 surf
->u
.gfx9
.stencil_offset
= align(surf
->surf_size
, out
.baseAlign
);
885 surf
->surf_size
= surf
->u
.gfx9
.stencil_offset
+ out
.surfSize
;
889 surf
->u
.gfx9
.surf
.swizzle_mode
= in
->swizzleMode
;
890 surf
->u
.gfx9
.surf
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
891 out
.mipChainPitch
- 1;
893 /* CMASK fast clear uses these even if FMASK isn't allocated.
894 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
896 surf
->u
.gfx9
.fmask
.swizzle_mode
= surf
->u
.gfx9
.surf
.swizzle_mode
& ~0x3;
897 surf
->u
.gfx9
.fmask
.epitch
= surf
->u
.gfx9
.surf
.epitch
;
899 surf
->u
.gfx9
.surf_slice_size
= out
.sliceSize
;
900 surf
->u
.gfx9
.surf_pitch
= out
.pitch
;
901 surf
->u
.gfx9
.surf_height
= out
.height
;
902 surf
->surf_size
= out
.surfSize
;
903 surf
->surf_alignment
= out
.baseAlign
;
905 if (in
->swizzleMode
== ADDR_SW_LINEAR
) {
906 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++)
907 surf
->u
.gfx9
.offset
[i
] = mip_info
[i
].offset
;
910 if (in
->flags
.depth
) {
911 assert(in
->swizzleMode
!= ADDR_SW_LINEAR
);
914 ADDR2_COMPUTE_HTILE_INFO_INPUT hin
= {0};
915 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout
= {0};
917 hin
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT
);
918 hout
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT
);
920 hin
.hTileFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
921 hin
.hTileFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
922 hin
.depthFlags
= in
->flags
;
923 hin
.swizzleMode
= in
->swizzleMode
;
924 hin
.unalignedWidth
= in
->width
;
925 hin
.unalignedHeight
= in
->height
;
926 hin
.numSlices
= in
->numSlices
;
927 hin
.numMipLevels
= in
->numMipLevels
;
929 ret
= Addr2ComputeHtileInfo(addrlib
, &hin
, &hout
);
933 surf
->u
.gfx9
.htile
.rb_aligned
= hin
.hTileFlags
.rbAligned
;
934 surf
->u
.gfx9
.htile
.pipe_aligned
= hin
.hTileFlags
.pipeAligned
;
935 surf
->htile_size
= hout
.htileBytes
;
936 surf
->htile_slice_size
= hout
.sliceSize
;
937 surf
->htile_alignment
= hout
.baseAlign
;
939 /* Compute tile swizzle for the color surface.
940 * All *_X and *_T modes can use the swizzle.
942 if (config
->info
.surf_index
&&
943 in
->swizzleMode
>= ADDR_SW_64KB_Z_T
&&
944 !out
.mipChainInTail
&&
945 !(surf
->flags
& RADEON_SURF_SHAREABLE
) &&
946 (in
->numSamples
> 1 || !(surf
->flags
& RADEON_SURF_SCANOUT
))) {
947 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
948 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
950 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
951 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
953 xin
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
954 xin
.flags
= in
->flags
;
955 xin
.swizzleMode
= in
->swizzleMode
;
956 xin
.resourceType
= in
->resourceType
;
957 xin
.format
= in
->format
;
958 xin
.numSamples
= in
->numSamples
;
959 xin
.numFrags
= in
->numFrags
;
961 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
965 assert(xout
.pipeBankXor
<=
966 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
967 surf
->tile_swizzle
= xout
.pipeBankXor
;
971 if (!(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
973 in
->swizzleMode
!= ADDR_SW_LINEAR
) {
974 ADDR2_COMPUTE_DCCINFO_INPUT din
= {0};
975 ADDR2_COMPUTE_DCCINFO_OUTPUT dout
= {0};
976 ADDR2_META_MIP_INFO meta_mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
978 din
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_INPUT
);
979 dout
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT
);
980 dout
.pMipInfo
= meta_mip_info
;
982 din
.dccKeyFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
983 din
.dccKeyFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
984 din
.colorFlags
= in
->flags
;
985 din
.resourceType
= in
->resourceType
;
986 din
.swizzleMode
= in
->swizzleMode
;
988 din
.unalignedWidth
= in
->width
;
989 din
.unalignedHeight
= in
->height
;
990 din
.numSlices
= in
->numSlices
;
991 din
.numFrags
= in
->numFrags
;
992 din
.numMipLevels
= in
->numMipLevels
;
993 din
.dataSurfaceSize
= out
.surfSize
;
995 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
999 surf
->u
.gfx9
.dcc
.rb_aligned
= din
.dccKeyFlags
.rbAligned
;
1000 surf
->u
.gfx9
.dcc
.pipe_aligned
= din
.dccKeyFlags
.pipeAligned
;
1001 surf
->u
.gfx9
.dcc_pitch_max
= dout
.pitch
- 1;
1002 surf
->dcc_size
= dout
.dccRamSize
;
1003 surf
->dcc_alignment
= dout
.dccRamBaseAlign
;
1004 surf
->num_dcc_levels
= in
->numMipLevels
;
1006 /* Disable DCC for levels that are in the mip tail.
1008 * There are two issues that this is intended to
1011 * 1. Multiple mip levels may share a cache line. This
1012 * can lead to corruption when switching between
1013 * rendering to different mip levels because the
1014 * RBs don't maintain coherency.
1016 * 2. Texturing with metadata after rendering sometimes
1017 * fails with corruption, probably for a similar
1020 * Working around these issues for all levels in the
1021 * mip tail may be overly conservative, but it's what
1024 * Alternative solutions that also work but are worse:
1025 * - Disable DCC entirely.
1026 * - Flush TC L2 after rendering.
1028 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++) {
1029 if (meta_mip_info
[i
].inMiptail
) {
1030 surf
->num_dcc_levels
= i
;
1035 if (!surf
->num_dcc_levels
)
1040 if (in
->numSamples
> 1) {
1041 ADDR2_COMPUTE_FMASK_INFO_INPUT fin
= {0};
1042 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
1044 fin
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT
);
1045 fout
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT
);
1047 ret
= gfx9_get_preferred_swizzle_mode(addrlib
, in
,
1053 fin
.unalignedWidth
= in
->width
;
1054 fin
.unalignedHeight
= in
->height
;
1055 fin
.numSlices
= in
->numSlices
;
1056 fin
.numSamples
= in
->numSamples
;
1057 fin
.numFrags
= in
->numFrags
;
1059 ret
= Addr2ComputeFmaskInfo(addrlib
, &fin
, &fout
);
1063 surf
->u
.gfx9
.fmask
.swizzle_mode
= fin
.swizzleMode
;
1064 surf
->u
.gfx9
.fmask
.epitch
= fout
.pitch
- 1;
1065 surf
->u
.gfx9
.fmask_size
= fout
.fmaskBytes
;
1066 surf
->u
.gfx9
.fmask_alignment
= fout
.baseAlign
;
1068 /* Compute tile swizzle for the FMASK surface. */
1069 if (config
->info
.fmask_surf_index
&&
1070 fin
.swizzleMode
>= ADDR_SW_64KB_Z_T
&&
1071 !(surf
->flags
& RADEON_SURF_SHAREABLE
)) {
1072 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
1073 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
1075 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
1076 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
1078 /* This counter starts from 1 instead of 0. */
1079 xin
.surfIndex
= p_atomic_inc_return(config
->info
.fmask_surf_index
);
1080 xin
.flags
= in
->flags
;
1081 xin
.swizzleMode
= in
->swizzleMode
;
1082 xin
.resourceType
= in
->resourceType
;
1083 xin
.format
= in
->format
;
1084 xin
.numSamples
= in
->numSamples
;
1085 xin
.numFrags
= in
->numFrags
;
1087 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
1091 assert(xout
.pipeBankXor
<=
1092 u_bit_consecutive(0, sizeof(surf
->u
.gfx9
.fmask_tile_swizzle
) * 8));
1093 surf
->u
.gfx9
.fmask_tile_swizzle
= xout
.pipeBankXor
;
1098 if (in
->swizzleMode
!= ADDR_SW_LINEAR
) {
1099 ADDR2_COMPUTE_CMASK_INFO_INPUT cin
= {0};
1100 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout
= {0};
1102 cin
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT
);
1103 cout
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT
);
1105 if (in
->numSamples
) {
1106 /* FMASK is always aligned. */
1107 cin
.cMaskFlags
.pipeAligned
= 1;
1108 cin
.cMaskFlags
.rbAligned
= 1;
1110 cin
.cMaskFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1111 cin
.cMaskFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1113 cin
.colorFlags
= in
->flags
;
1114 cin
.resourceType
= in
->resourceType
;
1115 cin
.unalignedWidth
= in
->width
;
1116 cin
.unalignedHeight
= in
->height
;
1117 cin
.numSlices
= in
->numSlices
;
1119 if (in
->numSamples
> 1)
1120 cin
.swizzleMode
= surf
->u
.gfx9
.fmask
.swizzle_mode
;
1122 cin
.swizzleMode
= in
->swizzleMode
;
1124 ret
= Addr2ComputeCmaskInfo(addrlib
, &cin
, &cout
);
1128 surf
->u
.gfx9
.cmask
.rb_aligned
= cin
.cMaskFlags
.rbAligned
;
1129 surf
->u
.gfx9
.cmask
.pipe_aligned
= cin
.cMaskFlags
.pipeAligned
;
1130 surf
->u
.gfx9
.cmask_size
= cout
.cmaskBytes
;
1131 surf
->u
.gfx9
.cmask_alignment
= cout
.baseAlign
;
1138 static int gfx9_compute_surface(ADDR_HANDLE addrlib
,
1139 const struct radeon_info
*info
,
1140 const struct ac_surf_config
*config
,
1141 enum radeon_surf_mode mode
,
1142 struct radeon_surf
*surf
)
1145 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
1148 assert(!(surf
->flags
& RADEON_SURF_FMASK
));
1150 AddrSurfInfoIn
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT
);
1152 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
1154 /* The format must be set correctly for the allocation of compressed
1155 * textures to work. In other cases, setting the bpp is sufficient. */
1157 switch (surf
->bpe
) {
1159 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
1162 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
1168 switch (surf
->bpe
) {
1170 assert(!(surf
->flags
& RADEON_SURF_ZBUFFER
));
1171 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1174 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1175 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1176 AddrSurfInfoIn
.format
= ADDR_FMT_16
;
1179 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1180 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1181 AddrSurfInfoIn
.format
= ADDR_FMT_32
;
1184 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1185 AddrSurfInfoIn
.format
= ADDR_FMT_32_32
;
1188 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1189 AddrSurfInfoIn
.format
= ADDR_FMT_32_32_32_32
;
1194 AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
1197 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
1198 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
1199 AddrSurfInfoIn
.flags
.display
= (surf
->flags
& RADEON_SURF_SCANOUT
) != 0;
1200 /* flags.texture currently refers to TC-compatible HTILE */
1201 AddrSurfInfoIn
.flags
.texture
= AddrSurfInfoIn
.flags
.color
||
1202 surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1203 AddrSurfInfoIn
.flags
.opt4space
= 1;
1205 AddrSurfInfoIn
.numMipLevels
= config
->info
.levels
;
1206 AddrSurfInfoIn
.numSamples
= config
->info
.samples
? config
->info
.samples
: 1;
1207 AddrSurfInfoIn
.numFrags
= AddrSurfInfoIn
.numSamples
;
1209 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1210 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1211 * must sample 1D textures as 2D. */
1213 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_3D
;
1215 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_2D
;
1217 AddrSurfInfoIn
.width
= config
->info
.width
;
1218 AddrSurfInfoIn
.height
= config
->info
.height
;
1221 AddrSurfInfoIn
.numSlices
= config
->info
.depth
;
1222 else if (config
->is_cube
)
1223 AddrSurfInfoIn
.numSlices
= 6;
1225 AddrSurfInfoIn
.numSlices
= config
->info
.array_size
;
1227 /* This is propagated to HTILE/DCC/CMASK. */
1228 AddrSurfInfoIn
.flags
.metaPipeUnaligned
= 0;
1229 AddrSurfInfoIn
.flags
.metaRbUnaligned
= 0;
1232 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1233 assert(config
->info
.samples
<= 1);
1234 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1235 AddrSurfInfoIn
.swizzleMode
= ADDR_SW_LINEAR
;
1238 case RADEON_SURF_MODE_1D
:
1239 case RADEON_SURF_MODE_2D
:
1240 if (surf
->flags
& RADEON_SURF_IMPORTED
) {
1241 AddrSurfInfoIn
.swizzleMode
= surf
->u
.gfx9
.surf
.swizzle_mode
;
1245 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
,
1247 &AddrSurfInfoIn
.swizzleMode
);
1256 surf
->u
.gfx9
.resource_type
= AddrSurfInfoIn
.resourceType
;
1257 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
1259 surf
->num_dcc_levels
= 0;
1260 surf
->surf_size
= 0;
1262 surf
->htile_size
= 0;
1263 surf
->htile_slice_size
= 0;
1264 surf
->u
.gfx9
.surf_offset
= 0;
1265 surf
->u
.gfx9
.stencil_offset
= 0;
1266 surf
->u
.gfx9
.fmask_size
= 0;
1267 surf
->u
.gfx9
.cmask_size
= 0;
1269 /* Calculate texture layout information. */
1270 r
= gfx9_compute_miptree(addrlib
, config
, surf
, compressed
,
1275 /* Calculate texture layout information for stencil. */
1276 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
1277 AddrSurfInfoIn
.flags
.stencil
= 1;
1278 AddrSurfInfoIn
.bpp
= 8;
1279 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1281 if (!AddrSurfInfoIn
.flags
.depth
) {
1282 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
,
1284 &AddrSurfInfoIn
.swizzleMode
);
1288 AddrSurfInfoIn
.flags
.depth
= 0;
1290 r
= gfx9_compute_miptree(addrlib
, config
, surf
, compressed
,
1296 surf
->is_linear
= surf
->u
.gfx9
.surf
.swizzle_mode
== ADDR_SW_LINEAR
;
1298 /* Query whether the surface is displayable. */
1299 bool displayable
= false;
1300 r
= Addr2IsValidDisplaySwizzleMode(addrlib
, surf
->u
.gfx9
.surf
.swizzle_mode
,
1301 surf
->bpe
* 8, &displayable
);
1304 surf
->is_displayable
= displayable
;
1306 switch (surf
->u
.gfx9
.surf
.swizzle_mode
) {
1308 case ADDR_SW_256B_S
:
1310 case ADDR_SW_64KB_S
:
1312 case ADDR_SW_64KB_S_T
:
1313 case ADDR_SW_4KB_S_X
:
1314 case ADDR_SW_64KB_S_X
:
1315 case ADDR_SW_VAR_S_X
:
1316 surf
->micro_tile_mode
= RADEON_MICRO_MODE_THIN
;
1320 case ADDR_SW_LINEAR
:
1321 case ADDR_SW_256B_D
:
1323 case ADDR_SW_64KB_D
:
1325 case ADDR_SW_64KB_D_T
:
1326 case ADDR_SW_4KB_D_X
:
1327 case ADDR_SW_64KB_D_X
:
1328 case ADDR_SW_VAR_D_X
:
1329 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DISPLAY
;
1333 case ADDR_SW_256B_R
:
1335 case ADDR_SW_64KB_R
:
1337 case ADDR_SW_64KB_R_T
:
1338 case ADDR_SW_4KB_R_X
:
1339 case ADDR_SW_64KB_R_X
:
1340 case ADDR_SW_VAR_R_X
:
1341 surf
->micro_tile_mode
= RADEON_MICRO_MODE_ROTATED
;
1346 case ADDR_SW_64KB_Z
:
1348 case ADDR_SW_64KB_Z_T
:
1349 case ADDR_SW_4KB_Z_X
:
1350 case ADDR_SW_64KB_Z_X
:
1351 case ADDR_SW_VAR_Z_X
:
1352 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DEPTH
;
1359 /* Temporary workaround to prevent VM faults and hangs. */
1360 if (info
->family
== CHIP_VEGA12
)
1361 surf
->u
.gfx9
.fmask_size
*= 8;
1366 int ac_compute_surface(ADDR_HANDLE addrlib
, const struct radeon_info
*info
,
1367 const struct ac_surf_config
*config
,
1368 enum radeon_surf_mode mode
,
1369 struct radeon_surf
*surf
)
1373 r
= surf_config_sanity(config
);
1377 if (info
->chip_class
>= GFX9
)
1378 return gfx9_compute_surface(addrlib
, info
, config
, mode
, surf
);
1380 return gfx6_compute_surface(addrlib
, info
, config
, mode
, surf
);