src/amd/common/ac_surface.c

   1 /*
   2  * Copyright © 2011 Red Hat All Rights Reserved.
   3  * Copyright © 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 #include "ac_surface.h"
  29 #include "amd_family.h"
  30 #include "amdgpu_id.h"
  31 #include "ac_gpu_info.h"
  32 #include "util/macros.h"
  33 #include "util/u_math.h"
  34
  35 #include <errno.h>
  36 #include <stdio.h>
  37 #include <stdlib.h>
  38 #include <amdgpu.h>
  39 #include <amdgpu_drm.h>
  40
  41 #include "addrlib/addrinterface.h"
  42
  43 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  44 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  45 #endif
  46
  47 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
  48 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
  49 #endif
  50
  51 static void addrlib_family_rev_id(enum radeon_family family,
  52                                   unsigned *addrlib_family,
  53                                   unsigned *addrlib_revid)
  54 {
  55         switch (family) {
  56         case CHIP_TAHITI:
  57                 *addrlib_family = FAMILY_SI;
  58                 *addrlib_revid = SI_TAHITI_P_A0;
  59                 break;
  60         case CHIP_PITCAIRN:
  61                 *addrlib_family = FAMILY_SI;
  62                 *addrlib_revid = SI_PITCAIRN_PM_A0;
  63                 break;
  64         case CHIP_VERDE:
  65                 *addrlib_family = FAMILY_SI;
  66                 *addrlib_revid = SI_CAPEVERDE_M_A0;
  67                 break;
  68         case CHIP_OLAND:
  69                 *addrlib_family = FAMILY_SI;
  70                 *addrlib_revid = SI_OLAND_M_A0;
  71                 break;
  72         case CHIP_HAINAN:
  73                 *addrlib_family = FAMILY_SI;
  74                 *addrlib_revid = SI_HAINAN_V_A0;
  75                 break;
  76         case CHIP_BONAIRE:
  77                 *addrlib_family = FAMILY_CI;
  78                 *addrlib_revid = CI_BONAIRE_M_A0;
  79                 break;
  80         case CHIP_KAVERI:
  81                 *addrlib_family = FAMILY_KV;
  82                 *addrlib_revid = KV_SPECTRE_A0;
  83                 break;
  84         case CHIP_KABINI:
  85                 *addrlib_family = FAMILY_KV;
  86                 *addrlib_revid = KB_KALINDI_A0;
  87                 break;
  88         case CHIP_HAWAII:
  89                 *addrlib_family = FAMILY_CI;
  90                 *addrlib_revid = CI_HAWAII_P_A0;
  91                 break;
  92         case CHIP_MULLINS:
  93                 *addrlib_family = FAMILY_KV;
  94                 *addrlib_revid = ML_GODAVARI_A0;
  95                 break;
  96         case CHIP_TONGA:
  97                 *addrlib_family = FAMILY_VI;
  98                 *addrlib_revid = VI_TONGA_P_A0;
  99                 break;
 100         case CHIP_ICELAND:
 101                 *addrlib_family = FAMILY_VI;
 102                 *addrlib_revid = VI_ICELAND_M_A0;
 103                 break;
 104         case CHIP_CARRIZO:
 105                 *addrlib_family = FAMILY_CZ;
 106                 *addrlib_revid = CARRIZO_A0;
 107                 break;
 108         case CHIP_STONEY:
 109                 *addrlib_family = FAMILY_CZ;
 110                 *addrlib_revid = STONEY_A0;
 111                 break;
 112         case CHIP_FIJI:
 113                 *addrlib_family = FAMILY_VI;
 114                 *addrlib_revid = VI_FIJI_P_A0;
 115                 break;
 116         case CHIP_POLARIS10:
 117                 *addrlib_family = FAMILY_VI;
 118                 *addrlib_revid = VI_POLARIS10_P_A0;
 119                 break;
 120         case CHIP_POLARIS11:
 121                 *addrlib_family = FAMILY_VI;
 122                 *addrlib_revid = VI_POLARIS11_M_A0;
 123                 break;
 124         case CHIP_POLARIS12:
 125                 *addrlib_family = FAMILY_VI;
 126                 *addrlib_revid = VI_POLARIS12_V_A0;
 127                 break;
 128         case CHIP_VEGA10:
 129                 *addrlib_family = FAMILY_AI;
 130                 *addrlib_revid = AI_VEGA10_P_A0;
 131                 break;
 132         case CHIP_RAVEN:
 133                 *addrlib_family = FAMILY_RV;
 134                 *addrlib_revid = RAVEN_A0;
 135                 break;
 136         default:
 137                 fprintf(stderr, "amdgpu: Unknown family.\n");
 138         }
 139 }
 140
 141 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
 142 {
 143         return malloc(pInput->sizeInBytes);
 144 }
 145
 146 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
 147 {
 148         free(pInput->pVirtAddr);
 149         return ADDR_OK;
 150 }
 151
 152 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 153                                const struct amdgpu_gpu_info *amdinfo)
 154 {
 155         ADDR_CREATE_INPUT addrCreateInput = {0};
 156         ADDR_CREATE_OUTPUT addrCreateOutput = {0};
 157         ADDR_REGISTER_VALUE regValue = {0};
 158         ADDR_CREATE_FLAGS createFlags = {{0}};
 159         ADDR_E_RETURNCODE addrRet;
 160
 161         addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
 162         addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 163
 164         regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
 165         createFlags.value = 0;
 166
 167         addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
 168         if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
 169                 return NULL;
 170
 171         if (addrCreateInput.chipFamily >= FAMILY_AI) {
 172                 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
 173                 regValue.blockVarSizeLog2 = 0;
 174         } else {
 175                 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
 176                 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
 177
 178                 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
 179                 regValue.pTileConfig = amdinfo->gb_tile_mode;
 180                 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
 181                 if (addrCreateInput.chipFamily == FAMILY_SI) {
 182                         regValue.pMacroTileConfig = NULL;
 183                         regValue.noOfMacroEntries = 0;
 184                 } else {
 185                         regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
 186                         regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
 187                 }
 188
 189                 createFlags.useTileIndex = 1;
 190                 createFlags.useHtileSliceAlign = 1;
 191
 192                 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 193         }
 194
 195         addrCreateInput.callbacks.allocSysMem = allocSysMem;
 196         addrCreateInput.callbacks.freeSysMem = freeSysMem;
 197         addrCreateInput.callbacks.debugPrint = 0;
 198         addrCreateInput.createFlags = createFlags;
 199         addrCreateInput.regValue = regValue;
 200
 201         addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
 202         if (addrRet != ADDR_OK)
 203                 return NULL;
 204
 205         return addrCreateOutput.hLib;
 206 }
 207
 208 static int surf_config_sanity(const struct ac_surf_config *config)
 209 {
 210         /* all dimension must be at least 1 ! */
 211         if (!config->info.width || !config->info.height || !config->info.depth ||
 212             !config->info.array_size || !config->info.levels)
 213                 return -EINVAL;
 214
 215         switch (config->info.samples) {
 216         case 0:
 217         case 1:
 218         case 2:
 219         case 4:
 220         case 8:
 221                 break;
 222         default:
 223                 return -EINVAL;
 224         }
 225
 226         if (config->is_3d && config->info.array_size > 1)
 227                 return -EINVAL;
 228         if (config->is_cube && config->info.depth > 1)
 229                 return -EINVAL;
 230
 231         return 0;
 232 }
 233
 234 static int gfx6_compute_level(ADDR_HANDLE addrlib,
 235                               const struct ac_surf_config *config,
 236                               struct radeon_surf *surf, bool is_stencil,
 237                               unsigned level, bool compressed,
 238                               ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
 239                               ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
 240                               ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
 241                               ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
 242                               ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
 243                               ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
 244 {
 245         struct legacy_surf_level *surf_level;
 246         ADDR_E_RETURNCODE ret;
 247
 248         AddrSurfInfoIn->mipLevel = level;
 249         AddrSurfInfoIn->width = u_minify(config->info.width, level);
 250         AddrSurfInfoIn->height = u_minify(config->info.height, level);
 251
 252         if (config->is_3d)
 253                 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
 254         else if (config->is_cube)
 255                 AddrSurfInfoIn->numSlices = 6;
 256         else
 257                 AddrSurfInfoIn->numSlices = config->info.array_size;
 258
 259         if (level > 0) {
 260                 /* Set the base level pitch. This is needed for calculation
 261                  * of non-zero levels. */
 262                 if (is_stencil)
 263                         AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
 264                 else
 265                         AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
 266
 267                 /* Convert blocks to pixels for compressed formats. */
 268                 if (compressed)
 269                         AddrSurfInfoIn->basePitch *= surf->blk_w;
 270         }
 271
 272         ret = AddrComputeSurfaceInfo(addrlib,
 273                                      AddrSurfInfoIn,
 274                                      AddrSurfInfoOut);
 275         if (ret != ADDR_OK) {
 276                 return ret;
 277         }
 278
 279         surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
 280         surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
 281         surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 282         surf_level->nblk_x = AddrSurfInfoOut->pitch;
 283         surf_level->nblk_y = AddrSurfInfoOut->height;
 284
 285         switch (AddrSurfInfoOut->tileMode) {
 286         case ADDR_TM_LINEAR_ALIGNED:
 287                 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 288                 break;
 289         case ADDR_TM_1D_TILED_THIN1:
 290                 surf_level->mode = RADEON_SURF_MODE_1D;
 291                 break;
 292         case ADDR_TM_2D_TILED_THIN1:
 293                 surf_level->mode = RADEON_SURF_MODE_2D;
 294                 break;
 295         default:
 296                 assert(0);
 297         }
 298
 299         if (is_stencil)
 300                 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
 301         else
 302                 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
 303
 304         surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
 305
 306         /* Clear DCC fields at the beginning. */
 307         surf_level->dcc_offset = 0;
 308
 309         /* The previous level's flag tells us if we can use DCC for this level. */
 310         if (AddrSurfInfoIn->flags.dccCompatible &&
 311             (level == 0 || AddrDccOut->subLvlCompressible)) {
 312                 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
 313                 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
 314                 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
 315                 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
 316                 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 317
 318                 ret = AddrComputeDccInfo(addrlib,
 319                                          AddrDccIn,
 320                                          AddrDccOut);
 321
 322                 if (ret == ADDR_OK) {
 323                         surf_level->dcc_offset = surf->dcc_size;
 324                         surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
 325                         surf->num_dcc_levels = level + 1;
 326                         surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
 327                         surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
 328                 }
 329         }
 330
 331         /* TC-compatible HTILE. */
 332         if (!is_stencil &&
 333             AddrSurfInfoIn->flags.depth &&
 334             AddrSurfInfoIn->flags.tcCompatible &&
 335             surf_level->mode == RADEON_SURF_MODE_2D &&
 336             level == 0) {
 337                 AddrHtileIn->flags.tcCompatible = 1;
 338                 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
 339                 AddrHtileIn->height = AddrSurfInfoOut->height;
 340                 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
 341                 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
 342                 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
 343                 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
 344                 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
 345                 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
 346
 347                 ret = AddrComputeHtileInfo(addrlib,
 348                                            AddrHtileIn,
 349                                            AddrHtileOut);
 350
 351                 if (ret == ADDR_OK) {
 352                         surf->htile_size = AddrHtileOut->htileBytes;
 353                         surf->htile_slice_size = AddrHtileOut->sliceSize;
 354                         surf->htile_alignment = AddrHtileOut->baseAlign;
 355                 }
 356         }
 357
 358         return 0;
 359 }
 360
 361 #define   G_009910_MICRO_TILE_MODE(x)          (((x) >> 0) & 0x03)
 362 #define   G_009910_MICRO_TILE_MODE_NEW(x)      (((x) >> 22) & 0x07)
 363
 364 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
 365                                      const struct radeon_info *info)
 366 {
 367         uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
 368
 369         if (info->chip_class >= CIK)
 370                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
 371         else
 372                 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 373 }
 374
 375 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
 376 {
 377         unsigned index, tileb;
 378
 379         tileb = 8 * 8 * surf->bpe;
 380         tileb = MIN2(surf->u.legacy.tile_split, tileb);
 381
 382         for (index = 0; tileb > 64; index++)
 383                 tileb >>= 1;
 384
 385         assert(index < 16);
 386         return index;
 387 }
 388
 389 /**
 390  * Copy surface-global settings like pipe/bank config from level 0 surface
 391  * computation.
 392  */
 393 static void gfx6_surface_settings(const struct radeon_info* info,
 394                                   ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
 395                                   struct radeon_surf *surf)
 396 {
 397         surf->surf_alignment = csio->baseAlign;
 398         surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
 399         gfx6_set_micro_tile_mode(surf, info);
 400
 401         /* For 2D modes only. */
 402         if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
 403                 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
 404                 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
 405                 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
 406                 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
 407                 surf->u.legacy.num_banks = csio->pTileInfo->banks;
 408                 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
 409         } else {
 410                 surf->u.legacy.macro_tile_index = 0;
 411         }
 412 }
 413
 414 /**
 415  * Fill in the tiling information in \p surf based on the given surface config.
 416  *
 417  * The following fields of \p surf must be initialized by the caller:
 418  * blk_w, blk_h, bpe, flags.
 419  */
 420 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 421                                 const struct radeon_info *info,
 422                                 const struct ac_surf_config *config,
 423                                 enum radeon_surf_mode mode,
 424                                 struct radeon_surf *surf)
 425 {
 426         unsigned level;
 427         bool compressed;
 428         ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 429         ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
 430         ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
 431         ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
 432         ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
 433         ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
 434         ADDR_TILEINFO AddrTileInfoIn = {0};
 435         ADDR_TILEINFO AddrTileInfoOut = {0};
 436         int r;
 437
 438         AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 439         AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 440         AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
 441         AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
 442         AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
 443         AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
 444         AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
 445
 446         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 447
 448         /* MSAA and FMASK require 2D tiling. */
 449         if (config->info.samples > 1 ||
 450             (surf->flags & RADEON_SURF_FMASK))
 451                 mode = RADEON_SURF_MODE_2D;
 452
 453         /* DB doesn't support linear layouts. */
 454         if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
 455             mode < RADEON_SURF_MODE_1D)
 456                 mode = RADEON_SURF_MODE_1D;
 457
 458         /* Set the requested tiling mode. */
 459         switch (mode) {
 460         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 461                 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
 462                 break;
 463         case RADEON_SURF_MODE_1D:
 464                 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
 465                 break;
 466         case RADEON_SURF_MODE_2D:
 467                 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
 468                 break;
 469         default:
 470                 assert(0);
 471         }
 472
 473         /* The format must be set correctly for the allocation of compressed
 474          * textures to work. In other cases, setting the bpp is sufficient.
 475          */
 476         if (compressed) {
 477                 switch (surf->bpe) {
 478                 case 8:
 479                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 480                         break;
 481                 case 16:
 482                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 483                         break;
 484                 default:
 485                         assert(0);
 486                 }
 487         }
 488         else {
 489                 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
 490         }
 491
 492         AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
 493                 config->info.samples ? config->info.samples : 1;
 494         AddrSurfInfoIn.tileIndex = -1;
 495
 496         /* Set the micro tile type. */
 497         if (surf->flags & RADEON_SURF_SCANOUT)
 498                 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
 499         else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
 500                 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
 501         else
 502                 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 503
 504         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 505         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 506         AddrSurfInfoIn.flags.cube = config->is_cube;
 507         AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
 508         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 509         AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
 510         AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 511
 512         /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
 513          * requested, because TC-compatible HTILE requires 2D tiling.
 514          */
 515         AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
 516                                          !AddrSurfInfoIn.flags.fmask &&
 517                                          config->info.samples <= 1 &&
 518                                          (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
 519
 520         /* DCC notes:
 521          * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 522          *   with samples >= 4.
 523          * - Mipmapped array textures have low performance (discovered by a closed
 524          *   driver team).
 525          */
 526         AddrSurfInfoIn.flags.dccCompatible =
 527                 info->chip_class >= VI &&
 528                 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 529                 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 530                 !compressed && AddrDccIn.numSamples <= 1 &&
 531                 ((config->info.array_size == 1 && config->info.depth == 1) ||
 532                  config->info.levels == 1);
 533
 534         AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 535         AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 536
 537         /* noStencil = 0 can result in a depth part that is incompatible with
 538          * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
 539          * this case, we may end up setting stencil_adjusted).
 540          *
 541          * TODO: update addrlib to a newer version, remove this, and
 542          * use flags.matchStencilTileCfg = 1 as an alternative fix.
 543          */
 544         if (config->info.levels > 1)
 545                 AddrSurfInfoIn.flags.noStencil = 1;
 546
 547         /* Set preferred macrotile parameters. This is usually required
 548          * for shared resources. This is for 2D tiling only. */
 549         if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
 550             surf->u.legacy.bankw && surf->u.legacy.bankh &&
 551             surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
 552                 assert(!(surf->flags & RADEON_SURF_FMASK));
 553
 554                 /* If any of these parameters are incorrect, the calculation
 555                  * will fail. */
 556                 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
 557                 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
 558                 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
 559                 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
 560                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
 561                 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
 562                 AddrSurfInfoIn.flags.opt4Space = 0;
 563                 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
 564
 565                 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
 566                  * the tile index, because we are expected to know it if
 567                  * we know the other parameters.
 568                  *
 569                  * This is something that can easily be fixed in Addrlib.
 570                  * For now, just figure it out here.
 571                  * Note that only 2D_TILE_THIN1 is handled here.
 572                  */
 573                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 574                 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 575
 576                 if (info->chip_class == SI) {
 577                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
 578                                 if (surf->bpe == 2)
 579                                         AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
 580                                 else
 581                                         AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
 582                         } else {
 583                                 if (surf->bpe == 1)
 584                                         AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
 585                                 else if (surf->bpe == 2)
 586                                         AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
 587                                 else if (surf->bpe == 4)
 588                                         AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 589                                 else
 590                                         AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
 591                         }
 592                 } else {
 593                         /* CIK - VI */
 594                         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 595                                 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
 596                         else
 597                                 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
 598
 599                         /* Addrlib doesn't set this if tileIndex is forced like above. */
 600                         AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
 601                 }
 602         }
 603
 604         surf->num_dcc_levels = 0;
 605         surf->surf_size = 0;
 606         surf->dcc_size = 0;
 607         surf->dcc_alignment = 1;
 608         surf->htile_size = 0;
 609         surf->htile_slice_size = 0;
 610         surf->htile_alignment = 1;
 611
 612         const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
 613                                   !(surf->flags & RADEON_SURF_ZBUFFER);
 614
 615         /* Calculate texture layout information. */
 616         if (!only_stencil) {
 617                 for (level = 0; level < config->info.levels; level++) {
 618                         r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
 619                                                &AddrSurfInfoIn, &AddrSurfInfoOut,
 620                                                &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
 621                         if (r)
 622                                 return r;
 623
 624                         if (level > 0)
 625                                 continue;
 626
 627                         gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
 628                 }
 629         }
 630
 631         /* Calculate texture layout information for stencil. */
 632         if (surf->flags & RADEON_SURF_SBUFFER) {
 633                 AddrSurfInfoIn.bpp = 8;
 634                 AddrSurfInfoIn.flags.depth = 0;
 635                 AddrSurfInfoIn.flags.stencil = 1;
 636                 AddrSurfInfoIn.flags.tcCompatible = 0;
 637                 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
 638                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
 639
 640                 for (level = 0; level < config->info.levels; level++) {
 641                         r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
 642                                                &AddrSurfInfoIn, &AddrSurfInfoOut,
 643                                                &AddrDccIn, &AddrDccOut,
 644                                                NULL, NULL);
 645                         if (r)
 646                                 return r;
 647
 648                         /* DB uses the depth pitch for both stencil and depth. */
 649                         if (!only_stencil) {
 650                                 if (surf->u.legacy.stencil_level[level].nblk_x !=
 651                                     surf->u.legacy.level[level].nblk_x)
 652                                         surf->u.legacy.stencil_adjusted = true;
 653                         } else {
 654                                 surf->u.legacy.level[level].nblk_x =
 655                                         surf->u.legacy.stencil_level[level].nblk_x;
 656                         }
 657
 658                         if (level == 0) {
 659                                 if (only_stencil)
 660                                         gfx6_surface_settings(info, &AddrSurfInfoOut, surf);
 661
 662                                 /* For 2D modes only. */
 663                                 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
 664                                         surf->u.legacy.stencil_tile_split =
 665                                                 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
 666                                 }
 667                         }
 668                 }
 669         }
 670
 671         /* Recalculate the whole DCC miptree size including disabled levels.
 672          * This is what addrlib does, but calling addrlib would be a lot more
 673          * complicated.
 674          */
 675         if (surf->dcc_size && config->info.levels > 1) {
 676                 surf->dcc_size = align64(surf->surf_size >> 8,
 677                                          info->pipe_interleave_bytes *
 678                                          info->num_tile_pipes);
 679         }
 680
 681         /* Make sure HTILE covers the whole miptree, because the shader reads
 682          * TC-compatible HTILE even for levels where it's disabled by DB.
 683          */
 684         if (surf->htile_size && config->info.levels > 1)
 685                 surf->htile_size *= 2;
 686
 687         surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 688         return 0;
 689 }
 690
 691 /* This is only called when expecting a tiled layout. */
 692 static int
 693 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
 694                                 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
 695                                 bool is_fmask, AddrSwizzleMode *swizzle_mode)
 696 {
 697         ADDR_E_RETURNCODE ret;
 698         ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
 699         ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
 700
 701         sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
 702         sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
 703
 704         sin.flags = in->flags;
 705         sin.resourceType = in->resourceType;
 706         sin.format = in->format;
 707         sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
 708         /* TODO: We could allow some of these: */
 709         sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
 710         sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
 711         sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
 712         sin.bpp = in->bpp;
 713         sin.width = in->width;
 714         sin.height = in->height;
 715         sin.numSlices = in->numSlices;
 716         sin.numMipLevels = in->numMipLevels;
 717         sin.numSamples = in->numSamples;
 718         sin.numFrags = in->numFrags;
 719
 720         if (is_fmask) {
 721                 sin.flags.color = 0;
 722                 sin.flags.fmask = 1;
 723         }
 724
 725         ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
 726         if (ret != ADDR_OK)
 727                 return ret;
 728
 729         *swizzle_mode = sout.swizzleMode;
 730         return 0;
 731 }
 732
 733 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 734                                 struct radeon_surf *surf, bool compressed,
 735                                 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
 736 {
 737         ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
 738         ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
 739         ADDR_E_RETURNCODE ret;
 740
 741         out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
 742         out.pMipInfo = mip_info;
 743
 744         ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
 745         if (ret != ADDR_OK)
 746         return ret;
 747
 748         if (in->flags.stencil) {
 749                 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
 750                 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
 751                                                                    out.mipChainPitch - 1;
 752                 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
 753                 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
 754                 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
 755                 return 0;
 756         }
 757
 758         surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
 759         surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
 760                                                         out.mipChainPitch - 1;
 761
 762         /* CMASK fast clear uses these even if FMASK isn't allocated.
 763          * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
 764          */
 765         surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
 766         surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
 767
 768         surf->u.gfx9.surf_slice_size = out.sliceSize;
 769         surf->u.gfx9.surf_pitch = out.pitch;
 770         surf->u.gfx9.surf_height = out.height;
 771         surf->surf_size = out.surfSize;
 772         surf->surf_alignment = out.baseAlign;
 773
 774         if (in->swizzleMode == ADDR_SW_LINEAR) {
 775                 for (unsigned i = 0; i < in->numMipLevels; i++)
 776                         surf->u.gfx9.offset[i] = mip_info[i].offset;
 777         }
 778
 779         if (in->flags.depth) {
 780                 assert(in->swizzleMode != ADDR_SW_LINEAR);
 781
 782                 /* HTILE */
 783                 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
 784                 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
 785
 786                 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
 787                 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
 788
 789                 hin.hTileFlags.pipeAligned = 1;
 790                 hin.hTileFlags.rbAligned = 1;
 791                 hin.depthFlags = in->flags;
 792                 hin.swizzleMode = in->swizzleMode;
 793                 hin.unalignedWidth = in->width;
 794                 hin.unalignedHeight = in->height;
 795                 hin.numSlices = in->numSlices;
 796                 hin.numMipLevels = in->numMipLevels;
 797
 798                 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
 799                 if (ret != ADDR_OK)
 800                         return ret;
 801
 802                 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
 803                 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
 804                 surf->htile_size = hout.htileBytes;
 805                 surf->htile_slice_size = hout.sliceSize;
 806                 surf->htile_alignment = hout.baseAlign;
 807         } else {
 808                 /* DCC */
 809                 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 810                     !(surf->flags & RADEON_SURF_SCANOUT) &&
 811                     !compressed &&
 812                     in->swizzleMode != ADDR_SW_LINEAR &&
 813                     /* TODO: We could support DCC with MSAA. */
 814                     in->numSamples == 1) {
 815                         ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
 816                         ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
 817
 818                         din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
 819                         dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
 820
 821                         din.dccKeyFlags.pipeAligned = 1;
 822                         din.dccKeyFlags.rbAligned = 1;
 823                         din.colorFlags = in->flags;
 824                         din.resourceType = in->resourceType;
 825                         din.swizzleMode = in->swizzleMode;
 826                         din.bpp = in->bpp;
 827                         din.unalignedWidth = in->width;
 828                         din.unalignedHeight = in->height;
 829                         din.numSlices = in->numSlices;
 830                         din.numFrags = in->numFrags;
 831                         din.numMipLevels = in->numMipLevels;
 832                         din.dataSurfaceSize = out.surfSize;
 833
 834                         ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
 835                         if (ret != ADDR_OK)
 836                                 return ret;
 837
 838                         surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
 839                         surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
 840                         surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
 841                         surf->dcc_size = dout.dccRamSize;
 842                         surf->dcc_alignment = dout.dccRamBaseAlign;
 843                 }
 844
 845                 /* FMASK */
 846                 if (in->numSamples > 1) {
 847                         ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
 848                         ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
 849
 850                         fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
 851                         fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
 852
 853                         ret = gfx9_get_preferred_swizzle_mode(addrlib, in, true, &fin.swizzleMode);
 854                         if (ret != ADDR_OK)
 855                                 return ret;
 856
 857                         fin.unalignedWidth = in->width;
 858                         fin.unalignedHeight = in->height;
 859                         fin.numSlices = in->numSlices;
 860                         fin.numSamples = in->numSamples;
 861                         fin.numFrags = in->numFrags;
 862
 863                         ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
 864                         if (ret != ADDR_OK)
 865                                 return ret;
 866
 867                         surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
 868                         surf->u.gfx9.fmask.epitch = fout.pitch - 1;
 869                         surf->u.gfx9.fmask_size = fout.fmaskBytes;
 870                         surf->u.gfx9.fmask_alignment = fout.baseAlign;
 871                 }
 872
 873                 /* CMASK */
 874                 if (in->swizzleMode != ADDR_SW_LINEAR) {
 875                         ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
 876                         ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
 877
 878                         cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
 879                         cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
 880
 881                         cin.cMaskFlags.pipeAligned = 1;
 882                         cin.cMaskFlags.rbAligned = 1;
 883                         cin.colorFlags = in->flags;
 884                         cin.resourceType = in->resourceType;
 885                         cin.unalignedWidth = in->width;
 886                         cin.unalignedHeight = in->height;
 887                         cin.numSlices = in->numSlices;
 888
 889                         if (in->numSamples > 1)
 890                                 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
 891                         else
 892                                 cin.swizzleMode = in->swizzleMode;
 893
 894                         ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
 895                         if (ret != ADDR_OK)
 896                                 return ret;
 897
 898                         surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
 899                         surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
 900                         surf->u.gfx9.cmask_size = cout.cmaskBytes;
 901                         surf->u.gfx9.cmask_alignment = cout.baseAlign;
 902                 }
 903         }
 904
 905         return 0;
 906 }
 907
 908 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 909                                 const struct ac_surf_config *config,
 910                                 enum radeon_surf_mode mode,
 911                                 struct radeon_surf *surf)
 912 {
 913         bool compressed;
 914         ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
 915         int r;
 916
 917         assert(!(surf->flags & RADEON_SURF_FMASK));
 918
 919         AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
 920
 921         compressed = surf->blk_w == 4 && surf->blk_h == 4;
 922
 923         /* The format must be set correctly for the allocation of compressed
 924          * textures to work. In other cases, setting the bpp is sufficient. */
 925         if (compressed) {
 926                 switch (surf->bpe) {
 927                 case 8:
 928                         AddrSurfInfoIn.format = ADDR_FMT_BC1;
 929                         break;
 930                 case 16:
 931                         AddrSurfInfoIn.format = ADDR_FMT_BC3;
 932                         break;
 933                 default:
 934                         assert(0);
 935                 }
 936         } else {
 937                 AddrSurfInfoIn.bpp = surf->bpe * 8;
 938         }
 939
 940         AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
 941         AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 942         AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
 943         AddrSurfInfoIn.flags.texture = 1;
 944         AddrSurfInfoIn.flags.opt4space = 1;
 945
 946         AddrSurfInfoIn.numMipLevels = config->info.levels;
 947         AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
 948         AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
 949
 950         /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
 951          * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
 952          * must sample 1D textures as 2D. */
 953         if (config->is_3d)
 954                 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
 955         else
 956                 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
 957
 958         AddrSurfInfoIn.width = config->info.width;
 959         AddrSurfInfoIn.height = config->info.height;
 960
 961         if (config->is_3d)
 962                 AddrSurfInfoIn.numSlices = config->info.depth;
 963         else if (config->is_cube)
 964                 AddrSurfInfoIn.numSlices = 6;
 965         else
 966                 AddrSurfInfoIn.numSlices = config->info.array_size;
 967
 968         switch (mode) {
 969         case RADEON_SURF_MODE_LINEAR_ALIGNED:
 970                 assert(config->info.samples <= 1);
 971                 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
 972                 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
 973                 break;
 974
 975         case RADEON_SURF_MODE_1D:
 976         case RADEON_SURF_MODE_2D:
 977                 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, false,
 978                                                     &AddrSurfInfoIn.swizzleMode);
 979                 if (r)
 980                         return r;
 981                 break;
 982
 983         default:
 984                 assert(0);
 985         }
 986
 987         surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
 988
 989         surf->surf_size = 0;
 990         surf->dcc_size = 0;
 991         surf->htile_size = 0;
 992         surf->htile_slice_size = 0;
 993         surf->u.gfx9.surf_offset = 0;
 994         surf->u.gfx9.stencil_offset = 0;
 995         surf->u.gfx9.fmask_size = 0;
 996         surf->u.gfx9.cmask_size = 0;
 997
 998         /* Calculate texture layout information. */
 999         r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1000         if (r)
1001                 return r;
1002
1003         /* Calculate texture layout information for stencil. */
1004         if (surf->flags & RADEON_SURF_SBUFFER) {
1005                 AddrSurfInfoIn.bpp = 8;
1006                 AddrSurfInfoIn.flags.depth = 0;
1007                 AddrSurfInfoIn.flags.stencil = 1;
1008
1009                 r = gfx9_compute_miptree(addrlib, surf, compressed, &AddrSurfInfoIn);
1010                 if (r)
1011                         return r;
1012         }
1013
1014         surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1015         surf->num_dcc_levels = surf->dcc_size ? config->info.levels : 0;
1016
1017         switch (surf->u.gfx9.surf.swizzle_mode) {
1018                 /* S = standard. */
1019                 case ADDR_SW_256B_S:
1020                 case ADDR_SW_4KB_S:
1021                 case ADDR_SW_64KB_S:
1022                 case ADDR_SW_VAR_S:
1023                 case ADDR_SW_64KB_S_T:
1024                 case ADDR_SW_4KB_S_X:
1025                 case ADDR_SW_64KB_S_X:
1026                 case ADDR_SW_VAR_S_X:
1027                         surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1028                         break;
1029
1030                 /* D = display. */
1031                 case ADDR_SW_LINEAR:
1032                 case ADDR_SW_256B_D:
1033                 case ADDR_SW_4KB_D:
1034                 case ADDR_SW_64KB_D:
1035                 case ADDR_SW_VAR_D:
1036                 case ADDR_SW_64KB_D_T:
1037                 case ADDR_SW_4KB_D_X:
1038                 case ADDR_SW_64KB_D_X:
1039                 case ADDR_SW_VAR_D_X:
1040                         surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1041                         break;
1042
1043                 /* R = rotated. */
1044                 case ADDR_SW_256B_R:
1045                 case ADDR_SW_4KB_R:
1046                 case ADDR_SW_64KB_R:
1047                 case ADDR_SW_VAR_R:
1048                 case ADDR_SW_64KB_R_T:
1049                 case ADDR_SW_4KB_R_X:
1050                 case ADDR_SW_64KB_R_X:
1051                 case ADDR_SW_VAR_R_X:
1052                         surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1053                         break;
1054
1055                 /* Z = depth. */
1056                 case ADDR_SW_4KB_Z:
1057                 case ADDR_SW_64KB_Z:
1058                 case ADDR_SW_VAR_Z:
1059                 case ADDR_SW_64KB_Z_T:
1060                 case ADDR_SW_4KB_Z_X:
1061                 case ADDR_SW_64KB_Z_X:
1062                 case ADDR_SW_VAR_Z_X:
1063                         surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1064                         break;
1065
1066                 default:
1067                         assert(0);
1068         }
1069
1070         return 0;
1071 }
1072
1073 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1074                        const struct ac_surf_config *config,
1075                        enum radeon_surf_mode mode,
1076                        struct radeon_surf *surf)
1077 {
1078         int r;
1079
1080         r = surf_config_sanity(config);
1081         if (r)
1082                 return r;
1083
1084         if (info->chip_class >= GFX9)
1085                 return gfx9_compute_surface(addrlib, config, mode, surf);
1086         else
1087                 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1088 }