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ac/surface: don't set the display flag for obviously unsupported cases (v2)
[mesa.git] / src / amd / common / ac_surface.c
1 /*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
35
36 #include <errno.h>
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41
42 #include "addrlib/addrinterface.h"
43
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
46 #endif
47
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
50 #endif
51
52 static unsigned get_first(unsigned x, unsigned y)
53 {
54 return x;
55 }
56
57 static void addrlib_family_rev_id(enum radeon_family family,
58 unsigned *addrlib_family,
59 unsigned *addrlib_revid)
60 {
61 switch (family) {
62 case CHIP_TAHITI:
63 *addrlib_family = FAMILY_SI;
64 *addrlib_revid = get_first(AMDGPU_TAHITI_RANGE);
65 break;
66 case CHIP_PITCAIRN:
67 *addrlib_family = FAMILY_SI;
68 *addrlib_revid = get_first(AMDGPU_PITCAIRN_RANGE);
69 break;
70 case CHIP_VERDE:
71 *addrlib_family = FAMILY_SI;
72 *addrlib_revid = get_first(AMDGPU_CAPEVERDE_RANGE);
73 break;
74 case CHIP_OLAND:
75 *addrlib_family = FAMILY_SI;
76 *addrlib_revid = get_first(AMDGPU_OLAND_RANGE);
77 break;
78 case CHIP_HAINAN:
79 *addrlib_family = FAMILY_SI;
80 *addrlib_revid = get_first(AMDGPU_HAINAN_RANGE);
81 break;
82 case CHIP_BONAIRE:
83 *addrlib_family = FAMILY_CI;
84 *addrlib_revid = get_first(AMDGPU_BONAIRE_RANGE);
85 break;
86 case CHIP_KAVERI:
87 *addrlib_family = FAMILY_KV;
88 *addrlib_revid = get_first(AMDGPU_SPECTRE_RANGE);
89 break;
90 case CHIP_KABINI:
91 *addrlib_family = FAMILY_KV;
92 *addrlib_revid = get_first(AMDGPU_KALINDI_RANGE);
93 break;
94 case CHIP_HAWAII:
95 *addrlib_family = FAMILY_CI;
96 *addrlib_revid = get_first(AMDGPU_HAWAII_RANGE);
97 break;
98 case CHIP_MULLINS:
99 *addrlib_family = FAMILY_KV;
100 *addrlib_revid = get_first(AMDGPU_GODAVARI_RANGE);
101 break;
102 case CHIP_TONGA:
103 *addrlib_family = FAMILY_VI;
104 *addrlib_revid = get_first(AMDGPU_TONGA_RANGE);
105 break;
106 case CHIP_ICELAND:
107 *addrlib_family = FAMILY_VI;
108 *addrlib_revid = get_first(AMDGPU_ICELAND_RANGE);
109 break;
110 case CHIP_CARRIZO:
111 *addrlib_family = FAMILY_CZ;
112 *addrlib_revid = get_first(AMDGPU_CARRIZO_RANGE);
113 break;
114 case CHIP_STONEY:
115 *addrlib_family = FAMILY_CZ;
116 *addrlib_revid = get_first(AMDGPU_STONEY_RANGE);
117 break;
118 case CHIP_FIJI:
119 *addrlib_family = FAMILY_VI;
120 *addrlib_revid = get_first(AMDGPU_FIJI_RANGE);
121 break;
122 case CHIP_POLARIS10:
123 *addrlib_family = FAMILY_VI;
124 *addrlib_revid = get_first(AMDGPU_POLARIS10_RANGE);
125 break;
126 case CHIP_POLARIS11:
127 *addrlib_family = FAMILY_VI;
128 *addrlib_revid = get_first(AMDGPU_POLARIS11_RANGE);
129 break;
130 case CHIP_POLARIS12:
131 *addrlib_family = FAMILY_VI;
132 *addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE);
133 break;
134 case CHIP_VEGA10:
135 *addrlib_family = FAMILY_AI;
136 *addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
137 break;
138 case CHIP_VEGA12:
139 *addrlib_family = FAMILY_AI;
140 *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
141 break;
142 case CHIP_RAVEN:
143 *addrlib_family = FAMILY_RV;
144 *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
145 break;
146 default:
147 fprintf(stderr, "amdgpu: Unknown family.\n");
148 }
149 }
150
151 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
152 {
153 return malloc(pInput->sizeInBytes);
154 }
155
156 static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
157 {
158 free(pInput->pVirtAddr);
159 return ADDR_OK;
160 }
161
162 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
163 const struct amdgpu_gpu_info *amdinfo,
164 uint64_t *max_alignment)
165 {
166 ADDR_CREATE_INPUT addrCreateInput = {0};
167 ADDR_CREATE_OUTPUT addrCreateOutput = {0};
168 ADDR_REGISTER_VALUE regValue = {0};
169 ADDR_CREATE_FLAGS createFlags = {{0}};
170 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
171 ADDR_E_RETURNCODE addrRet;
172
173 addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
174 addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
175
176 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
177 createFlags.value = 0;
178
179 addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
180 if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
181 return NULL;
182
183 if (addrCreateInput.chipFamily >= FAMILY_AI) {
184 addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
185 regValue.blockVarSizeLog2 = 0;
186 } else {
187 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
188 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
189
190 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask;
191 regValue.pTileConfig = amdinfo->gb_tile_mode;
192 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
193 if (addrCreateInput.chipFamily == FAMILY_SI) {
194 regValue.pMacroTileConfig = NULL;
195 regValue.noOfMacroEntries = 0;
196 } else {
197 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
198 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
199 }
200
201 createFlags.useTileIndex = 1;
202 createFlags.useHtileSliceAlign = 1;
203
204 addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
205 }
206
207 addrCreateInput.callbacks.allocSysMem = allocSysMem;
208 addrCreateInput.callbacks.freeSysMem = freeSysMem;
209 addrCreateInput.callbacks.debugPrint = 0;
210 addrCreateInput.createFlags = createFlags;
211 addrCreateInput.regValue = regValue;
212
213 addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
214 if (addrRet != ADDR_OK)
215 return NULL;
216
217 if (max_alignment) {
218 addrRet = AddrGetMaxAlignments(addrCreateOutput.hLib, &addrGetMaxAlignmentsOutput);
219 if (addrRet == ADDR_OK){
220 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
221 }
222 }
223 return addrCreateOutput.hLib;
224 }
225
226 static int surf_config_sanity(const struct ac_surf_config *config)
227 {
228 /* all dimension must be at least 1 ! */
229 if (!config->info.width || !config->info.height || !config->info.depth ||
230 !config->info.array_size || !config->info.levels)
231 return -EINVAL;
232
233 switch (config->info.samples) {
234 case 0:
235 case 1:
236 case 2:
237 case 4:
238 case 8:
239 break;
240 default:
241 return -EINVAL;
242 }
243
244 if (config->is_3d && config->info.array_size > 1)
245 return -EINVAL;
246 if (config->is_cube && config->info.depth > 1)
247 return -EINVAL;
248
249 return 0;
250 }
251
252 static int gfx6_compute_level(ADDR_HANDLE addrlib,
253 const struct ac_surf_config *config,
254 struct radeon_surf *surf, bool is_stencil,
255 unsigned level, bool compressed,
256 ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
257 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
258 ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
259 ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
260 ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
261 ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
262 {
263 struct legacy_surf_level *surf_level;
264 ADDR_E_RETURNCODE ret;
265
266 AddrSurfInfoIn->mipLevel = level;
267 AddrSurfInfoIn->width = u_minify(config->info.width, level);
268 AddrSurfInfoIn->height = u_minify(config->info.height, level);
269
270 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
271 * because GFX9 needs linear alignment of 256 bytes.
272 */
273 if (config->info.levels == 1 &&
274 AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
275 AddrSurfInfoIn->bpp) {
276 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
277
278 assert(util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp));
279 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
280 }
281
282 if (config->is_3d)
283 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
284 else if (config->is_cube)
285 AddrSurfInfoIn->numSlices = 6;
286 else
287 AddrSurfInfoIn->numSlices = config->info.array_size;
288
289 if (level > 0) {
290 /* Set the base level pitch. This is needed for calculation
291 * of non-zero levels. */
292 if (is_stencil)
293 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
294 else
295 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
296
297 /* Convert blocks to pixels for compressed formats. */
298 if (compressed)
299 AddrSurfInfoIn->basePitch *= surf->blk_w;
300 }
301
302 ret = AddrComputeSurfaceInfo(addrlib,
303 AddrSurfInfoIn,
304 AddrSurfInfoOut);
305 if (ret != ADDR_OK) {
306 return ret;
307 }
308
309 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
310 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
311 surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4;
312 surf_level->nblk_x = AddrSurfInfoOut->pitch;
313 surf_level->nblk_y = AddrSurfInfoOut->height;
314
315 switch (AddrSurfInfoOut->tileMode) {
316 case ADDR_TM_LINEAR_ALIGNED:
317 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
318 break;
319 case ADDR_TM_1D_TILED_THIN1:
320 surf_level->mode = RADEON_SURF_MODE_1D;
321 break;
322 case ADDR_TM_2D_TILED_THIN1:
323 surf_level->mode = RADEON_SURF_MODE_2D;
324 break;
325 default:
326 assert(0);
327 }
328
329 if (is_stencil)
330 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
331 else
332 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
333
334 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
335
336 /* Clear DCC fields at the beginning. */
337 surf_level->dcc_offset = 0;
338
339 /* The previous level's flag tells us if we can use DCC for this level. */
340 if (AddrSurfInfoIn->flags.dccCompatible &&
341 (level == 0 || AddrDccOut->subLvlCompressible)) {
342 AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
343 AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
344 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
345 AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
346 AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
347
348 ret = AddrComputeDccInfo(addrlib,
349 AddrDccIn,
350 AddrDccOut);
351
352 if (ret == ADDR_OK) {
353 surf_level->dcc_offset = surf->dcc_size;
354 surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
355 surf->num_dcc_levels = level + 1;
356 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
357 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
358 }
359 }
360
361 /* TC-compatible HTILE. */
362 if (!is_stencil &&
363 AddrSurfInfoIn->flags.depth &&
364 surf_level->mode == RADEON_SURF_MODE_2D &&
365 level == 0) {
366 AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
367 AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
368 AddrHtileIn->height = AddrSurfInfoOut->height;
369 AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
370 AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
371 AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
372 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
373 AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
374 AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
375
376 ret = AddrComputeHtileInfo(addrlib,
377 AddrHtileIn,
378 AddrHtileOut);
379
380 if (ret == ADDR_OK) {
381 surf->htile_size = AddrHtileOut->htileBytes;
382 surf->htile_slice_size = AddrHtileOut->sliceSize;
383 surf->htile_alignment = AddrHtileOut->baseAlign;
384 }
385 }
386
387 return 0;
388 }
389
390 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
391 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
392
393 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
394 const struct radeon_info *info)
395 {
396 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
397
398 if (info->chip_class >= CIK)
399 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
400 else
401 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
402 }
403
404 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
405 {
406 unsigned index, tileb;
407
408 tileb = 8 * 8 * surf->bpe;
409 tileb = MIN2(surf->u.legacy.tile_split, tileb);
410
411 for (index = 0; tileb > 64; index++)
412 tileb >>= 1;
413
414 assert(index < 16);
415 return index;
416 }
417
418 static bool get_display_flag(const struct ac_surf_config *config,
419 const struct radeon_surf *surf)
420 {
421 unsigned num_channels = config->info.num_channels;
422 unsigned bpe = surf->bpe;
423
424 if (surf->flags & RADEON_SURF_SCANOUT &&
425 !(surf->flags & RADEON_SURF_FMASK) &&
426 config->info.samples <= 1 &&
427 surf->blk_w <= 2 && surf->blk_h == 1) {
428 /* subsampled */
429 if (surf->blk_w == 2 && surf->blk_h == 1)
430 return true;
431
432 if (/* RGBA8 or RGBA16F */
433 (bpe >= 4 && bpe <= 8 && num_channels == 4) ||
434 /* R5G6B5 or R5G5B5A1 */
435 (bpe == 2 && num_channels >= 3) ||
436 /* C8 palette */
437 (bpe == 1 && num_channels == 1))
438 return true;
439 }
440 return false;
441 }
442
443 /**
444 * This must be called after the first level is computed.
445 *
446 * Copy surface-global settings like pipe/bank config from level 0 surface
447 * computation, and compute tile swizzle.
448 */
449 static int gfx6_surface_settings(ADDR_HANDLE addrlib,
450 const struct radeon_info *info,
451 const struct ac_surf_config *config,
452 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* csio,
453 struct radeon_surf *surf)
454 {
455 surf->surf_alignment = csio->baseAlign;
456 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
457 gfx6_set_micro_tile_mode(surf, info);
458
459 /* For 2D modes only. */
460 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) {
461 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
462 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
463 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
464 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
465 surf->u.legacy.num_banks = csio->pTileInfo->banks;
466 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
467 } else {
468 surf->u.legacy.macro_tile_index = 0;
469 }
470
471 /* Compute tile swizzle. */
472 /* TODO: fix tile swizzle with mipmapping for SI */
473 if ((info->chip_class >= CIK || config->info.levels == 1) &&
474 config->info.surf_index &&
475 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
476 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
477 !get_display_flag(config, surf)) {
478 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
479 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
480
481 AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
482 AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
483
484 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
485 AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
486 AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
487 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
488 AddrBaseSwizzleIn.tileMode = csio->tileMode;
489
490 int r = AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
491 &AddrBaseSwizzleOut);
492 if (r != ADDR_OK)
493 return r;
494
495 assert(AddrBaseSwizzleOut.tileSwizzle <=
496 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
497 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
498 }
499 return 0;
500 }
501
502 /**
503 * Fill in the tiling information in \p surf based on the given surface config.
504 *
505 * The following fields of \p surf must be initialized by the caller:
506 * blk_w, blk_h, bpe, flags.
507 */
508 static int gfx6_compute_surface(ADDR_HANDLE addrlib,
509 const struct radeon_info *info,
510 const struct ac_surf_config *config,
511 enum radeon_surf_mode mode,
512 struct radeon_surf *surf)
513 {
514 unsigned level;
515 bool compressed;
516 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
517 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
518 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
519 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
520 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
521 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
522 ADDR_TILEINFO AddrTileInfoIn = {0};
523 ADDR_TILEINFO AddrTileInfoOut = {0};
524 int r;
525
526 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
527 AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
528 AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
529 AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
530 AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
531 AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
532 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
533
534 compressed = surf->blk_w == 4 && surf->blk_h == 4;
535
536 /* MSAA and FMASK require 2D tiling. */
537 if (config->info.samples > 1 ||
538 (surf->flags & RADEON_SURF_FMASK))
539 mode = RADEON_SURF_MODE_2D;
540
541 /* DB doesn't support linear layouts. */
542 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
543 mode < RADEON_SURF_MODE_1D)
544 mode = RADEON_SURF_MODE_1D;
545
546 /* Set the requested tiling mode. */
547 switch (mode) {
548 case RADEON_SURF_MODE_LINEAR_ALIGNED:
549 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
550 break;
551 case RADEON_SURF_MODE_1D:
552 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
553 break;
554 case RADEON_SURF_MODE_2D:
555 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
556 break;
557 default:
558 assert(0);
559 }
560
561 /* The format must be set correctly for the allocation of compressed
562 * textures to work. In other cases, setting the bpp is sufficient.
563 */
564 if (compressed) {
565 switch (surf->bpe) {
566 case 8:
567 AddrSurfInfoIn.format = ADDR_FMT_BC1;
568 break;
569 case 16:
570 AddrSurfInfoIn.format = ADDR_FMT_BC3;
571 break;
572 default:
573 assert(0);
574 }
575 }
576 else {
577 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
578 }
579
580 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
581 config->info.samples ? config->info.samples : 1;
582 AddrSurfInfoIn.tileIndex = -1;
583
584 /* Set the micro tile type. */
585 if (surf->flags & RADEON_SURF_SCANOUT)
586 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
587 else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
588 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
589 else
590 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
591
592 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
593 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
594 AddrSurfInfoIn.flags.cube = config->is_cube;
595 AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
596 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
597 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
598 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
599
600 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
601 * requested, because TC-compatible HTILE requires 2D tiling.
602 */
603 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
604 !AddrSurfInfoIn.flags.fmask &&
605 config->info.samples <= 1 &&
606 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
607
608 /* DCC notes:
609 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
610 * with samples >= 4.
611 * - Mipmapped array textures have low performance (discovered by a closed
612 * driver team).
613 */
614 AddrSurfInfoIn.flags.dccCompatible =
615 info->chip_class >= VI &&
616 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
617 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
618 !compressed &&
619 ((config->info.array_size == 1 && config->info.depth == 1) ||
620 config->info.levels == 1);
621
622 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
623 AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
624
625 /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
626 * for Z and stencil. This can cause a number of problems which we work
627 * around here:
628 *
629 * - a depth part that is incompatible with mipmapped texturing
630 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
631 * incorrect tiling applied to the stencil part, stencil buffer
632 * memory accesses that go out of bounds) even without mipmapping
633 *
634 * Some piglit tests that are prone to different types of related
635 * failures:
636 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
637 * ./bin/framebuffer-blit-levels {draw,read} stencil
638 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
639 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
640 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
641 */
642 int stencil_tile_idx = -1;
643
644 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
645 (config->info.levels > 1 || info->family == CHIP_STONEY)) {
646 /* Compute stencilTileIdx that is compatible with the (depth)
647 * tileIdx. This degrades the depth surface if necessary to
648 * ensure that a matching stencilTileIdx exists. */
649 AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
650
651 /* Keep the depth mip-tail compatible with texturing. */
652 AddrSurfInfoIn.flags.noStencil = 1;
653 }
654
655 /* Set preferred macrotile parameters. This is usually required
656 * for shared resources. This is for 2D tiling only. */
657 if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
658 surf->u.legacy.bankw && surf->u.legacy.bankh &&
659 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
660 assert(!(surf->flags & RADEON_SURF_FMASK));
661
662 /* If any of these parameters are incorrect, the calculation
663 * will fail. */
664 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
665 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
666 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
667 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
668 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
669 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
670 AddrSurfInfoIn.flags.opt4Space = 0;
671 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
672
673 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
674 * the tile index, because we are expected to know it if
675 * we know the other parameters.
676 *
677 * This is something that can easily be fixed in Addrlib.
678 * For now, just figure it out here.
679 * Note that only 2D_TILE_THIN1 is handled here.
680 */
681 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
682 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
683
684 if (info->chip_class == SI) {
685 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
686 if (surf->bpe == 2)
687 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
688 else
689 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
690 } else {
691 if (surf->bpe == 1)
692 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
693 else if (surf->bpe == 2)
694 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
695 else if (surf->bpe == 4)
696 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
697 else
698 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
699 }
700 } else {
701 /* CIK - VI */
702 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
703 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
704 else
705 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
706
707 /* Addrlib doesn't set this if tileIndex is forced like above. */
708 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
709 }
710 }
711
712 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
713 surf->num_dcc_levels = 0;
714 surf->surf_size = 0;
715 surf->dcc_size = 0;
716 surf->dcc_alignment = 1;
717 surf->htile_size = 0;
718 surf->htile_slice_size = 0;
719 surf->htile_alignment = 1;
720
721 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
722 !(surf->flags & RADEON_SURF_ZBUFFER);
723
724 /* Calculate texture layout information. */
725 if (!only_stencil) {
726 for (level = 0; level < config->info.levels; level++) {
727 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
728 &AddrSurfInfoIn, &AddrSurfInfoOut,
729 &AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
730 if (r)
731 return r;
732
733 if (level > 0)
734 continue;
735
736 /* Check that we actually got a TC-compatible HTILE if
737 * we requested it (only for level 0, since we're not
738 * supporting HTILE on higher mip levels anyway). */
739 assert(AddrSurfInfoOut.tcCompatible ||
740 !AddrSurfInfoIn.flags.tcCompatible ||
741 AddrSurfInfoIn.flags.matchStencilTileCfg);
742
743 if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
744 if (!AddrSurfInfoOut.tcCompatible) {
745 AddrSurfInfoIn.flags.tcCompatible = 0;
746 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
747 }
748
749 AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
750 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
751 stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
752
753 assert(stencil_tile_idx >= 0);
754 }
755
756 r = gfx6_surface_settings(addrlib, info, config,
757 &AddrSurfInfoOut, surf);
758 if (r)
759 return r;
760 }
761 }
762
763 /* Calculate texture layout information for stencil. */
764 if (surf->flags & RADEON_SURF_SBUFFER) {
765 AddrSurfInfoIn.tileIndex = stencil_tile_idx;
766 AddrSurfInfoIn.bpp = 8;
767 AddrSurfInfoIn.flags.depth = 0;
768 AddrSurfInfoIn.flags.stencil = 1;
769 AddrSurfInfoIn.flags.tcCompatible = 0;
770 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
771 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
772
773 for (level = 0; level < config->info.levels; level++) {
774 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
775 &AddrSurfInfoIn, &AddrSurfInfoOut,
776 &AddrDccIn, &AddrDccOut,
777 NULL, NULL);
778 if (r)
779 return r;
780
781 /* DB uses the depth pitch for both stencil and depth. */
782 if (!only_stencil) {
783 if (surf->u.legacy.stencil_level[level].nblk_x !=
784 surf->u.legacy.level[level].nblk_x)
785 surf->u.legacy.stencil_adjusted = true;
786 } else {
787 surf->u.legacy.level[level].nblk_x =
788 surf->u.legacy.stencil_level[level].nblk_x;
789 }
790
791 if (level == 0) {
792 if (only_stencil) {
793 r = gfx6_surface_settings(addrlib, info, config,
794 &AddrSurfInfoOut, surf);
795 if (r)
796 return r;
797 }
798
799 /* For 2D modes only. */
800 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
801 surf->u.legacy.stencil_tile_split =
802 AddrSurfInfoOut.pTileInfo->tileSplitBytes;
803 }
804 }
805 }
806 }
807
808 /* Recalculate the whole DCC miptree size including disabled levels.
809 * This is what addrlib does, but calling addrlib would be a lot more
810 * complicated.
811 */
812 if (surf->dcc_size && config->info.levels > 1) {
813 /* The smallest miplevels that are never compressed by DCC
814 * still read the DCC buffer via TC if the base level uses DCC,
815 * and for some reason the DCC buffer needs to be larger if
816 * the miptree uses non-zero tile_swizzle. Otherwise there are
817 * VM faults.
818 *
819 * "dcc_alignment * 4" was determined by trial and error.
820 */
821 surf->dcc_size = align64(surf->surf_size >> 8,
822 surf->dcc_alignment * 4);
823 }
824
825 /* Make sure HTILE covers the whole miptree, because the shader reads
826 * TC-compatible HTILE even for levels where it's disabled by DB.
827 */
828 if (surf->htile_size && config->info.levels > 1)
829 surf->htile_size *= 2;
830
831 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
832 surf->is_displayable = surf->is_linear ||
833 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
834 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
835 return 0;
836 }
837
838 /* This is only called when expecting a tiled layout. */
839 static int
840 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
841 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
842 bool is_fmask, unsigned flags,
843 AddrSwizzleMode *swizzle_mode)
844 {
845 ADDR_E_RETURNCODE ret;
846 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
847 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout = {0};
848
849 sin.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT);
850 sout.size = sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT);
851
852 sin.flags = in->flags;
853 sin.resourceType = in->resourceType;
854 sin.format = in->format;
855 sin.resourceLoction = ADDR_RSRC_LOC_INVIS;
856 /* TODO: We could allow some of these: */
857 sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */
858 sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */
859 sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */
860 sin.bpp = in->bpp;
861 sin.width = in->width;
862 sin.height = in->height;
863 sin.numSlices = in->numSlices;
864 sin.numMipLevels = in->numMipLevels;
865 sin.numSamples = in->numSamples;
866 sin.numFrags = in->numFrags;
867
868 if (flags & RADEON_SURF_SCANOUT)
869 sin.preferredSwSet.sw_D = 1;
870 else if (in->flags.depth || in->flags.stencil || is_fmask)
871 sin.preferredSwSet.sw_Z = 1;
872 else
873 sin.preferredSwSet.sw_S = 1;
874
875 if (is_fmask) {
876 sin.flags.display = 0;
877 sin.flags.color = 0;
878 sin.flags.fmask = 1;
879 }
880
881 ret = Addr2GetPreferredSurfaceSetting(addrlib, &sin, &sout);
882 if (ret != ADDR_OK)
883 return ret;
884
885 *swizzle_mode = sout.swizzleMode;
886 return 0;
887 }
888
889 static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
890 const struct ac_surf_config *config,
891 struct radeon_surf *surf, bool compressed,
892 ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
893 {
894 ADDR2_MIP_INFO mip_info[RADEON_SURF_MAX_LEVELS] = {};
895 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
896 ADDR_E_RETURNCODE ret;
897
898 out.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT);
899 out.pMipInfo = mip_info;
900
901 ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
902 if (ret != ADDR_OK)
903 return ret;
904
905 if (in->flags.stencil) {
906 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
907 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
908 out.mipChainPitch - 1;
909 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
910 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
911 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
912 return 0;
913 }
914
915 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
916 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
917 out.mipChainPitch - 1;
918
919 /* CMASK fast clear uses these even if FMASK isn't allocated.
920 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
921 */
922 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
923 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
924
925 surf->u.gfx9.surf_slice_size = out.sliceSize;
926 surf->u.gfx9.surf_pitch = out.pitch;
927 surf->u.gfx9.surf_height = out.height;
928 surf->surf_size = out.surfSize;
929 surf->surf_alignment = out.baseAlign;
930
931 if (in->swizzleMode == ADDR_SW_LINEAR) {
932 for (unsigned i = 0; i < in->numMipLevels; i++)
933 surf->u.gfx9.offset[i] = mip_info[i].offset;
934 }
935
936 if (in->flags.depth) {
937 assert(in->swizzleMode != ADDR_SW_LINEAR);
938
939 /* HTILE */
940 ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
941 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
942
943 hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
944 hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
945
946 hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
947 hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
948 hin.depthFlags = in->flags;
949 hin.swizzleMode = in->swizzleMode;
950 hin.unalignedWidth = in->width;
951 hin.unalignedHeight = in->height;
952 hin.numSlices = in->numSlices;
953 hin.numMipLevels = in->numMipLevels;
954
955 ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
956 if (ret != ADDR_OK)
957 return ret;
958
959 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
960 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
961 surf->htile_size = hout.htileBytes;
962 surf->htile_slice_size = hout.sliceSize;
963 surf->htile_alignment = hout.baseAlign;
964 } else {
965 /* Compute tile swizzle for the color surface.
966 * All *_X and *_T modes can use the swizzle.
967 */
968 if (config->info.surf_index &&
969 in->swizzleMode >= ADDR_SW_64KB_Z_T &&
970 !out.mipChainInTail &&
971 !(surf->flags & RADEON_SURF_SHAREABLE) &&
972 !in->flags.display) {
973 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
974 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
975
976 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
977 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
978
979 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
980 xin.flags = in->flags;
981 xin.swizzleMode = in->swizzleMode;
982 xin.resourceType = in->resourceType;
983 xin.format = in->format;
984 xin.numSamples = in->numSamples;
985 xin.numFrags = in->numFrags;
986
987 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
988 if (ret != ADDR_OK)
989 return ret;
990
991 assert(xout.pipeBankXor <=
992 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
993 surf->tile_swizzle = xout.pipeBankXor;
994 }
995
996 /* DCC */
997 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
998 !compressed &&
999 in->swizzleMode != ADDR_SW_LINEAR) {
1000 ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
1001 ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
1002 ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
1003
1004 din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
1005 dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
1006 dout.pMipInfo = meta_mip_info;
1007
1008 din.dccKeyFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1009 din.dccKeyFlags.rbAligned = !in->flags.metaRbUnaligned;
1010 din.colorFlags = in->flags;
1011 din.resourceType = in->resourceType;
1012 din.swizzleMode = in->swizzleMode;
1013 din.bpp = in->bpp;
1014 din.unalignedWidth = in->width;
1015 din.unalignedHeight = in->height;
1016 din.numSlices = in->numSlices;
1017 din.numFrags = in->numFrags;
1018 din.numMipLevels = in->numMipLevels;
1019 din.dataSurfaceSize = out.surfSize;
1020
1021 ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
1022 if (ret != ADDR_OK)
1023 return ret;
1024
1025 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1026 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1027 surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
1028 surf->dcc_size = dout.dccRamSize;
1029 surf->dcc_alignment = dout.dccRamBaseAlign;
1030 surf->num_dcc_levels = in->numMipLevels;
1031
1032 /* Disable DCC for levels that are in the mip tail.
1033 *
1034 * There are two issues that this is intended to
1035 * address:
1036 *
1037 * 1. Multiple mip levels may share a cache line. This
1038 * can lead to corruption when switching between
1039 * rendering to different mip levels because the
1040 * RBs don't maintain coherency.
1041 *
1042 * 2. Texturing with metadata after rendering sometimes
1043 * fails with corruption, probably for a similar
1044 * reason.
1045 *
1046 * Working around these issues for all levels in the
1047 * mip tail may be overly conservative, but it's what
1048 * Vulkan does.
1049 *
1050 * Alternative solutions that also work but are worse:
1051 * - Disable DCC entirely.
1052 * - Flush TC L2 after rendering.
1053 */
1054 for (unsigned i = 0; i < in->numMipLevels; i++) {
1055 if (meta_mip_info[i].inMiptail) {
1056 surf->num_dcc_levels = i;
1057 break;
1058 }
1059 }
1060
1061 if (!surf->num_dcc_levels)
1062 surf->dcc_size = 0;
1063 }
1064
1065 /* FMASK */
1066 if (in->numSamples > 1) {
1067 ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
1068 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
1069
1070 fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
1071 fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
1072
1073 ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
1074 true, surf->flags,
1075 &fin.swizzleMode);
1076 if (ret != ADDR_OK)
1077 return ret;
1078
1079 fin.unalignedWidth = in->width;
1080 fin.unalignedHeight = in->height;
1081 fin.numSlices = in->numSlices;
1082 fin.numSamples = in->numSamples;
1083 fin.numFrags = in->numFrags;
1084
1085 ret = Addr2ComputeFmaskInfo(addrlib, &fin, &fout);
1086 if (ret != ADDR_OK)
1087 return ret;
1088
1089 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1090 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1091 surf->u.gfx9.fmask_size = fout.fmaskBytes;
1092 surf->u.gfx9.fmask_alignment = fout.baseAlign;
1093
1094 /* Compute tile swizzle for the FMASK surface. */
1095 if (config->info.fmask_surf_index &&
1096 fin.swizzleMode >= ADDR_SW_64KB_Z_T &&
1097 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1098 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
1099 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
1100
1101 xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
1102 xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
1103
1104 /* This counter starts from 1 instead of 0. */
1105 xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
1106 xin.flags = in->flags;
1107 xin.swizzleMode = in->swizzleMode;
1108 xin.resourceType = in->resourceType;
1109 xin.format = in->format;
1110 xin.numSamples = in->numSamples;
1111 xin.numFrags = in->numFrags;
1112
1113 ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
1114 if (ret != ADDR_OK)
1115 return ret;
1116
1117 assert(xout.pipeBankXor <=
1118 u_bit_consecutive(0, sizeof(surf->u.gfx9.fmask_tile_swizzle) * 8));
1119 surf->u.gfx9.fmask_tile_swizzle = xout.pipeBankXor;
1120 }
1121 }
1122
1123 /* CMASK */
1124 if (in->swizzleMode != ADDR_SW_LINEAR) {
1125 ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
1126 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
1127
1128 cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT);
1129 cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT);
1130
1131 if (in->numSamples) {
1132 /* FMASK is always aligned. */
1133 cin.cMaskFlags.pipeAligned = 1;
1134 cin.cMaskFlags.rbAligned = 1;
1135 } else {
1136 cin.cMaskFlags.pipeAligned = !in->flags.metaPipeUnaligned;
1137 cin.cMaskFlags.rbAligned = !in->flags.metaRbUnaligned;
1138 }
1139 cin.colorFlags = in->flags;
1140 cin.resourceType = in->resourceType;
1141 cin.unalignedWidth = in->width;
1142 cin.unalignedHeight = in->height;
1143 cin.numSlices = in->numSlices;
1144
1145 if (in->numSamples > 1)
1146 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1147 else
1148 cin.swizzleMode = in->swizzleMode;
1149
1150 ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
1151 if (ret != ADDR_OK)
1152 return ret;
1153
1154 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1155 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1156 surf->u.gfx9.cmask_size = cout.cmaskBytes;
1157 surf->u.gfx9.cmask_alignment = cout.baseAlign;
1158 }
1159 }
1160
1161 return 0;
1162 }
1163
1164 static int gfx9_compute_surface(ADDR_HANDLE addrlib,
1165 const struct radeon_info *info,
1166 const struct ac_surf_config *config,
1167 enum radeon_surf_mode mode,
1168 struct radeon_surf *surf)
1169 {
1170 bool compressed;
1171 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
1172 int r;
1173
1174 assert(!(surf->flags & RADEON_SURF_FMASK));
1175
1176 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
1177
1178 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1179
1180 /* The format must be set correctly for the allocation of compressed
1181 * textures to work. In other cases, setting the bpp is sufficient. */
1182 if (compressed) {
1183 switch (surf->bpe) {
1184 case 8:
1185 AddrSurfInfoIn.format = ADDR_FMT_BC1;
1186 break;
1187 case 16:
1188 AddrSurfInfoIn.format = ADDR_FMT_BC3;
1189 break;
1190 default:
1191 assert(0);
1192 }
1193 } else {
1194 switch (surf->bpe) {
1195 case 1:
1196 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1197 AddrSurfInfoIn.format = ADDR_FMT_8;
1198 break;
1199 case 2:
1200 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1201 !(surf->flags & RADEON_SURF_SBUFFER));
1202 AddrSurfInfoIn.format = ADDR_FMT_16;
1203 break;
1204 case 4:
1205 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1206 !(surf->flags & RADEON_SURF_SBUFFER));
1207 AddrSurfInfoIn.format = ADDR_FMT_32;
1208 break;
1209 case 8:
1210 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1211 AddrSurfInfoIn.format = ADDR_FMT_32_32;
1212 break;
1213 case 16:
1214 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1215 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
1216 break;
1217 default:
1218 assert(0);
1219 }
1220 AddrSurfInfoIn.bpp = surf->bpe * 8;
1221 }
1222
1223 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1224 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1225 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1226 /* flags.texture currently refers to TC-compatible HTILE */
1227 AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
1228 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1229 AddrSurfInfoIn.flags.opt4space = 1;
1230
1231 AddrSurfInfoIn.numMipLevels = config->info.levels;
1232 AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1;
1233 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
1234
1235 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1236 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1237 * must sample 1D textures as 2D. */
1238 if (config->is_3d)
1239 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
1240 else
1241 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
1242
1243 AddrSurfInfoIn.width = config->info.width;
1244 AddrSurfInfoIn.height = config->info.height;
1245
1246 if (config->is_3d)
1247 AddrSurfInfoIn.numSlices = config->info.depth;
1248 else if (config->is_cube)
1249 AddrSurfInfoIn.numSlices = 6;
1250 else
1251 AddrSurfInfoIn.numSlices = config->info.array_size;
1252
1253 /* This is propagated to HTILE/DCC/CMASK. */
1254 AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
1255 AddrSurfInfoIn.flags.metaRbUnaligned = 0;
1256
1257 switch (mode) {
1258 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1259 assert(config->info.samples <= 1);
1260 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1261 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
1262 break;
1263
1264 case RADEON_SURF_MODE_1D:
1265 case RADEON_SURF_MODE_2D:
1266 if (surf->flags & RADEON_SURF_IMPORTED) {
1267 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1268 break;
1269 }
1270
1271 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1272 false, surf->flags,
1273 &AddrSurfInfoIn.swizzleMode);
1274 if (r)
1275 return r;
1276 break;
1277
1278 default:
1279 assert(0);
1280 }
1281
1282 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1283 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1284
1285 surf->num_dcc_levels = 0;
1286 surf->surf_size = 0;
1287 surf->dcc_size = 0;
1288 surf->htile_size = 0;
1289 surf->htile_slice_size = 0;
1290 surf->u.gfx9.surf_offset = 0;
1291 surf->u.gfx9.stencil_offset = 0;
1292 surf->u.gfx9.fmask_size = 0;
1293 surf->u.gfx9.cmask_size = 0;
1294
1295 /* Calculate texture layout information. */
1296 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1297 &AddrSurfInfoIn);
1298 if (r)
1299 return r;
1300
1301 /* Calculate texture layout information for stencil. */
1302 if (surf->flags & RADEON_SURF_SBUFFER) {
1303 AddrSurfInfoIn.flags.stencil = 1;
1304 AddrSurfInfoIn.bpp = 8;
1305 AddrSurfInfoIn.format = ADDR_FMT_8;
1306
1307 if (!AddrSurfInfoIn.flags.depth) {
1308 r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn,
1309 false, surf->flags,
1310 &AddrSurfInfoIn.swizzleMode);
1311 if (r)
1312 return r;
1313 } else
1314 AddrSurfInfoIn.flags.depth = 0;
1315
1316 r = gfx9_compute_miptree(addrlib, config, surf, compressed,
1317 &AddrSurfInfoIn);
1318 if (r)
1319 return r;
1320 }
1321
1322 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1323
1324 /* Query whether the surface is displayable. */
1325 bool displayable = false;
1326 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1327 surf->bpe * 8, &displayable);
1328 if (r)
1329 return r;
1330 surf->is_displayable = displayable;
1331
1332 switch (surf->u.gfx9.surf.swizzle_mode) {
1333 /* S = standard. */
1334 case ADDR_SW_256B_S:
1335 case ADDR_SW_4KB_S:
1336 case ADDR_SW_64KB_S:
1337 case ADDR_SW_VAR_S:
1338 case ADDR_SW_64KB_S_T:
1339 case ADDR_SW_4KB_S_X:
1340 case ADDR_SW_64KB_S_X:
1341 case ADDR_SW_VAR_S_X:
1342 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1343 break;
1344
1345 /* D = display. */
1346 case ADDR_SW_LINEAR:
1347 case ADDR_SW_256B_D:
1348 case ADDR_SW_4KB_D:
1349 case ADDR_SW_64KB_D:
1350 case ADDR_SW_VAR_D:
1351 case ADDR_SW_64KB_D_T:
1352 case ADDR_SW_4KB_D_X:
1353 case ADDR_SW_64KB_D_X:
1354 case ADDR_SW_VAR_D_X:
1355 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1356 break;
1357
1358 /* R = rotated. */
1359 case ADDR_SW_256B_R:
1360 case ADDR_SW_4KB_R:
1361 case ADDR_SW_64KB_R:
1362 case ADDR_SW_VAR_R:
1363 case ADDR_SW_64KB_R_T:
1364 case ADDR_SW_4KB_R_X:
1365 case ADDR_SW_64KB_R_X:
1366 case ADDR_SW_VAR_R_X:
1367 surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
1368 break;
1369
1370 /* Z = depth. */
1371 case ADDR_SW_4KB_Z:
1372 case ADDR_SW_64KB_Z:
1373 case ADDR_SW_VAR_Z:
1374 case ADDR_SW_64KB_Z_T:
1375 case ADDR_SW_4KB_Z_X:
1376 case ADDR_SW_64KB_Z_X:
1377 case ADDR_SW_VAR_Z_X:
1378 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1379 break;
1380
1381 default:
1382 assert(0);
1383 }
1384
1385 /* Temporary workaround to prevent VM faults and hangs. */
1386 if (info->family == CHIP_VEGA12)
1387 surf->u.gfx9.fmask_size *= 8;
1388
1389 return 0;
1390 }
1391
1392 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
1393 const struct ac_surf_config *config,
1394 enum radeon_surf_mode mode,
1395 struct radeon_surf *surf)
1396 {
1397 int r;
1398
1399 r = surf_config_sanity(config);
1400 if (r)
1401 return r;
1402
1403 if (info->chip_class >= GFX9)
1404 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1405 else
1406 return gfx6_compute_surface(addrlib, info, config, mode, surf);
1407 }