2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
28 #include "ac_surface.h"
29 #include "amd_family.h"
30 #include "addrlib/amdgpu_asic_addr.h"
31 #include "ac_gpu_info.h"
32 #include "util/macros.h"
33 #include "util/u_atomic.h"
34 #include "util/u_math.h"
40 #include <amdgpu_drm.h>
42 #include "addrlib/addrinterface.h"
44 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
45 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
48 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
49 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
52 static unsigned get_first(unsigned x
, unsigned y
)
57 static void addrlib_family_rev_id(enum radeon_family family
,
58 unsigned *addrlib_family
,
59 unsigned *addrlib_revid
)
63 *addrlib_family
= FAMILY_SI
;
64 *addrlib_revid
= get_first(AMDGPU_TAHITI_RANGE
);
67 *addrlib_family
= FAMILY_SI
;
68 *addrlib_revid
= get_first(AMDGPU_PITCAIRN_RANGE
);
71 *addrlib_family
= FAMILY_SI
;
72 *addrlib_revid
= get_first(AMDGPU_CAPEVERDE_RANGE
);
75 *addrlib_family
= FAMILY_SI
;
76 *addrlib_revid
= get_first(AMDGPU_OLAND_RANGE
);
79 *addrlib_family
= FAMILY_SI
;
80 *addrlib_revid
= get_first(AMDGPU_HAINAN_RANGE
);
83 *addrlib_family
= FAMILY_CI
;
84 *addrlib_revid
= get_first(AMDGPU_BONAIRE_RANGE
);
87 *addrlib_family
= FAMILY_KV
;
88 *addrlib_revid
= get_first(AMDGPU_SPECTRE_RANGE
);
91 *addrlib_family
= FAMILY_KV
;
92 *addrlib_revid
= get_first(AMDGPU_KALINDI_RANGE
);
95 *addrlib_family
= FAMILY_CI
;
96 *addrlib_revid
= get_first(AMDGPU_HAWAII_RANGE
);
99 *addrlib_family
= FAMILY_KV
;
100 *addrlib_revid
= get_first(AMDGPU_GODAVARI_RANGE
);
103 *addrlib_family
= FAMILY_VI
;
104 *addrlib_revid
= get_first(AMDGPU_TONGA_RANGE
);
107 *addrlib_family
= FAMILY_VI
;
108 *addrlib_revid
= get_first(AMDGPU_ICELAND_RANGE
);
111 *addrlib_family
= FAMILY_CZ
;
112 *addrlib_revid
= get_first(AMDGPU_CARRIZO_RANGE
);
115 *addrlib_family
= FAMILY_CZ
;
116 *addrlib_revid
= get_first(AMDGPU_STONEY_RANGE
);
119 *addrlib_family
= FAMILY_VI
;
120 *addrlib_revid
= get_first(AMDGPU_FIJI_RANGE
);
123 *addrlib_family
= FAMILY_VI
;
124 *addrlib_revid
= get_first(AMDGPU_POLARIS10_RANGE
);
127 *addrlib_family
= FAMILY_VI
;
128 *addrlib_revid
= get_first(AMDGPU_POLARIS11_RANGE
);
131 *addrlib_family
= FAMILY_VI
;
132 *addrlib_revid
= get_first(AMDGPU_POLARIS12_RANGE
);
135 *addrlib_family
= FAMILY_VI
;
136 *addrlib_revid
= get_first(AMDGPU_VEGAM_RANGE
);
139 *addrlib_family
= FAMILY_AI
;
140 *addrlib_revid
= get_first(AMDGPU_VEGA10_RANGE
);
143 *addrlib_family
= FAMILY_AI
;
144 *addrlib_revid
= get_first(AMDGPU_VEGA12_RANGE
);
147 *addrlib_family
= FAMILY_RV
;
148 *addrlib_revid
= get_first(AMDGPU_RAVEN_RANGE
);
151 fprintf(stderr
, "amdgpu: Unknown family.\n");
155 static void *ADDR_API
allocSysMem(const ADDR_ALLOCSYSMEM_INPUT
* pInput
)
157 return malloc(pInput
->sizeInBytes
);
160 static ADDR_E_RETURNCODE ADDR_API
freeSysMem(const ADDR_FREESYSMEM_INPUT
* pInput
)
162 free(pInput
->pVirtAddr
);
166 ADDR_HANDLE
amdgpu_addr_create(const struct radeon_info
*info
,
167 const struct amdgpu_gpu_info
*amdinfo
,
168 uint64_t *max_alignment
)
170 ADDR_CREATE_INPUT addrCreateInput
= {0};
171 ADDR_CREATE_OUTPUT addrCreateOutput
= {0};
172 ADDR_REGISTER_VALUE regValue
= {0};
173 ADDR_CREATE_FLAGS createFlags
= {{0}};
174 ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput
= {0};
175 ADDR_E_RETURNCODE addrRet
;
177 addrCreateInput
.size
= sizeof(ADDR_CREATE_INPUT
);
178 addrCreateOutput
.size
= sizeof(ADDR_CREATE_OUTPUT
);
180 regValue
.gbAddrConfig
= amdinfo
->gb_addr_cfg
;
181 createFlags
.value
= 0;
183 addrlib_family_rev_id(info
->family
, &addrCreateInput
.chipFamily
, &addrCreateInput
.chipRevision
);
184 if (addrCreateInput
.chipFamily
== FAMILY_UNKNOWN
)
187 if (addrCreateInput
.chipFamily
>= FAMILY_AI
) {
188 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_ARCTICISLAND
;
189 regValue
.blockVarSizeLog2
= 0;
191 regValue
.noOfBanks
= amdinfo
->mc_arb_ramcfg
& 0x3;
192 regValue
.noOfRanks
= (amdinfo
->mc_arb_ramcfg
& 0x4) >> 2;
194 regValue
.backendDisables
= amdinfo
->enabled_rb_pipes_mask
;
195 regValue
.pTileConfig
= amdinfo
->gb_tile_mode
;
196 regValue
.noOfEntries
= ARRAY_SIZE(amdinfo
->gb_tile_mode
);
197 if (addrCreateInput
.chipFamily
== FAMILY_SI
) {
198 regValue
.pMacroTileConfig
= NULL
;
199 regValue
.noOfMacroEntries
= 0;
201 regValue
.pMacroTileConfig
= amdinfo
->gb_macro_tile_mode
;
202 regValue
.noOfMacroEntries
= ARRAY_SIZE(amdinfo
->gb_macro_tile_mode
);
205 createFlags
.useTileIndex
= 1;
206 createFlags
.useHtileSliceAlign
= 1;
208 addrCreateInput
.chipEngine
= CIASICIDGFXENGINE_SOUTHERNISLAND
;
211 addrCreateInput
.callbacks
.allocSysMem
= allocSysMem
;
212 addrCreateInput
.callbacks
.freeSysMem
= freeSysMem
;
213 addrCreateInput
.callbacks
.debugPrint
= 0;
214 addrCreateInput
.createFlags
= createFlags
;
215 addrCreateInput
.regValue
= regValue
;
217 addrRet
= AddrCreate(&addrCreateInput
, &addrCreateOutput
);
218 if (addrRet
!= ADDR_OK
)
222 addrRet
= AddrGetMaxAlignments(addrCreateOutput
.hLib
, &addrGetMaxAlignmentsOutput
);
223 if (addrRet
== ADDR_OK
){
224 *max_alignment
= addrGetMaxAlignmentsOutput
.baseAlign
;
227 return addrCreateOutput
.hLib
;
230 static int surf_config_sanity(const struct ac_surf_config
*config
,
233 /* FMASK is allocated together with the color surface and can't be
234 * allocated separately.
236 assert(!(flags
& RADEON_SURF_FMASK
));
237 if (flags
& RADEON_SURF_FMASK
)
240 /* all dimension must be at least 1 ! */
241 if (!config
->info
.width
|| !config
->info
.height
|| !config
->info
.depth
||
242 !config
->info
.array_size
|| !config
->info
.levels
)
245 switch (config
->info
.samples
) {
253 if (flags
& RADEON_SURF_Z_OR_SBUFFER
)
260 if (!(flags
& RADEON_SURF_Z_OR_SBUFFER
)) {
261 switch (config
->info
.color_samples
) {
273 if (config
->is_3d
&& config
->info
.array_size
> 1)
275 if (config
->is_cube
&& config
->info
.depth
> 1)
281 static int gfx6_compute_level(ADDR_HANDLE addrlib
,
282 const struct ac_surf_config
*config
,
283 struct radeon_surf
*surf
, bool is_stencil
,
284 unsigned level
, bool compressed
,
285 ADDR_COMPUTE_SURFACE_INFO_INPUT
*AddrSurfInfoIn
,
286 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
*AddrSurfInfoOut
,
287 ADDR_COMPUTE_DCCINFO_INPUT
*AddrDccIn
,
288 ADDR_COMPUTE_DCCINFO_OUTPUT
*AddrDccOut
,
289 ADDR_COMPUTE_HTILE_INFO_INPUT
*AddrHtileIn
,
290 ADDR_COMPUTE_HTILE_INFO_OUTPUT
*AddrHtileOut
)
292 struct legacy_surf_level
*surf_level
;
293 ADDR_E_RETURNCODE ret
;
295 AddrSurfInfoIn
->mipLevel
= level
;
296 AddrSurfInfoIn
->width
= u_minify(config
->info
.width
, level
);
297 AddrSurfInfoIn
->height
= u_minify(config
->info
.height
, level
);
299 /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
300 * because GFX9 needs linear alignment of 256 bytes.
302 if (config
->info
.levels
== 1 &&
303 AddrSurfInfoIn
->tileMode
== ADDR_TM_LINEAR_ALIGNED
&&
304 AddrSurfInfoIn
->bpp
) {
305 unsigned alignment
= 256 / (AddrSurfInfoIn
->bpp
/ 8);
307 assert(util_is_power_of_two_or_zero(AddrSurfInfoIn
->bpp
));
308 AddrSurfInfoIn
->width
= align(AddrSurfInfoIn
->width
, alignment
);
312 AddrSurfInfoIn
->numSlices
= u_minify(config
->info
.depth
, level
);
313 else if (config
->is_cube
)
314 AddrSurfInfoIn
->numSlices
= 6;
316 AddrSurfInfoIn
->numSlices
= config
->info
.array_size
;
319 /* Set the base level pitch. This is needed for calculation
320 * of non-zero levels. */
322 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.stencil_level
[0].nblk_x
;
324 AddrSurfInfoIn
->basePitch
= surf
->u
.legacy
.level
[0].nblk_x
;
326 /* Convert blocks to pixels for compressed formats. */
328 AddrSurfInfoIn
->basePitch
*= surf
->blk_w
;
331 ret
= AddrComputeSurfaceInfo(addrlib
,
334 if (ret
!= ADDR_OK
) {
338 surf_level
= is_stencil
? &surf
->u
.legacy
.stencil_level
[level
] : &surf
->u
.legacy
.level
[level
];
339 surf_level
->offset
= align64(surf
->surf_size
, AddrSurfInfoOut
->baseAlign
);
340 surf_level
->slice_size_dw
= AddrSurfInfoOut
->sliceSize
/ 4;
341 surf_level
->nblk_x
= AddrSurfInfoOut
->pitch
;
342 surf_level
->nblk_y
= AddrSurfInfoOut
->height
;
344 switch (AddrSurfInfoOut
->tileMode
) {
345 case ADDR_TM_LINEAR_ALIGNED
:
346 surf_level
->mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
348 case ADDR_TM_1D_TILED_THIN1
:
349 surf_level
->mode
= RADEON_SURF_MODE_1D
;
351 case ADDR_TM_2D_TILED_THIN1
:
352 surf_level
->mode
= RADEON_SURF_MODE_2D
;
359 surf
->u
.legacy
.stencil_tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
361 surf
->u
.legacy
.tiling_index
[level
] = AddrSurfInfoOut
->tileIndex
;
363 surf
->surf_size
= surf_level
->offset
+ AddrSurfInfoOut
->surfSize
;
365 /* Clear DCC fields at the beginning. */
366 surf_level
->dcc_offset
= 0;
368 /* The previous level's flag tells us if we can use DCC for this level. */
369 if (AddrSurfInfoIn
->flags
.dccCompatible
&&
370 (level
== 0 || AddrDccOut
->subLvlCompressible
)) {
371 bool prev_level_clearable
= level
== 0 ||
372 AddrDccOut
->dccRamSizeAligned
;
374 AddrDccIn
->colorSurfSize
= AddrSurfInfoOut
->surfSize
;
375 AddrDccIn
->tileMode
= AddrSurfInfoOut
->tileMode
;
376 AddrDccIn
->tileInfo
= *AddrSurfInfoOut
->pTileInfo
;
377 AddrDccIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
378 AddrDccIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
380 ret
= AddrComputeDccInfo(addrlib
,
384 if (ret
== ADDR_OK
) {
385 surf_level
->dcc_offset
= surf
->dcc_size
;
386 surf
->num_dcc_levels
= level
+ 1;
387 surf
->dcc_size
= surf_level
->dcc_offset
+ AddrDccOut
->dccRamSize
;
388 surf
->dcc_alignment
= MAX2(surf
->dcc_alignment
, AddrDccOut
->dccRamBaseAlign
);
390 /* If the DCC size of a subresource (1 mip level or 1 slice)
391 * is not aligned, the DCC memory layout is not contiguous for
392 * that subresource, which means we can't use fast clear.
394 * We only do fast clears for whole mipmap levels. If we did
395 * per-slice fast clears, the same restriction would apply.
396 * (i.e. only compute the slice size and see if it's aligned)
398 * The last level can be non-contiguous and still be clearable
399 * if it's interleaved with the next level that doesn't exist.
401 if (AddrDccOut
->dccRamSizeAligned
||
402 (prev_level_clearable
&& level
== config
->info
.levels
- 1))
403 surf_level
->dcc_fast_clear_size
= AddrDccOut
->dccFastClearSize
;
405 surf_level
->dcc_fast_clear_size
= 0;
409 /* TC-compatible HTILE. */
411 AddrSurfInfoIn
->flags
.depth
&&
412 surf_level
->mode
== RADEON_SURF_MODE_2D
&&
414 AddrHtileIn
->flags
.tcCompatible
= AddrSurfInfoIn
->flags
.tcCompatible
;
415 AddrHtileIn
->pitch
= AddrSurfInfoOut
->pitch
;
416 AddrHtileIn
->height
= AddrSurfInfoOut
->height
;
417 AddrHtileIn
->numSlices
= AddrSurfInfoOut
->depth
;
418 AddrHtileIn
->blockWidth
= ADDR_HTILE_BLOCKSIZE_8
;
419 AddrHtileIn
->blockHeight
= ADDR_HTILE_BLOCKSIZE_8
;
420 AddrHtileIn
->pTileInfo
= AddrSurfInfoOut
->pTileInfo
;
421 AddrHtileIn
->tileIndex
= AddrSurfInfoOut
->tileIndex
;
422 AddrHtileIn
->macroModeIndex
= AddrSurfInfoOut
->macroModeIndex
;
424 ret
= AddrComputeHtileInfo(addrlib
,
428 if (ret
== ADDR_OK
) {
429 surf
->htile_size
= AddrHtileOut
->htileBytes
;
430 surf
->htile_slice_size
= AddrHtileOut
->sliceSize
;
431 surf
->htile_alignment
= AddrHtileOut
->baseAlign
;
438 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
439 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
441 static void gfx6_set_micro_tile_mode(struct radeon_surf
*surf
,
442 const struct radeon_info
*info
)
444 uint32_t tile_mode
= info
->si_tile_mode_array
[surf
->u
.legacy
.tiling_index
[0]];
446 if (info
->chip_class
>= CIK
)
447 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE_NEW(tile_mode
);
449 surf
->micro_tile_mode
= G_009910_MICRO_TILE_MODE(tile_mode
);
452 static unsigned cik_get_macro_tile_index(struct radeon_surf
*surf
)
454 unsigned index
, tileb
;
456 tileb
= 8 * 8 * surf
->bpe
;
457 tileb
= MIN2(surf
->u
.legacy
.tile_split
, tileb
);
459 for (index
= 0; tileb
> 64; index
++)
466 static bool get_display_flag(const struct ac_surf_config
*config
,
467 const struct radeon_surf
*surf
)
469 unsigned num_channels
= config
->info
.num_channels
;
470 unsigned bpe
= surf
->bpe
;
472 if (surf
->flags
& RADEON_SURF_SCANOUT
&&
473 config
->info
.samples
<= 1 &&
474 surf
->blk_w
<= 2 && surf
->blk_h
== 1) {
476 if (surf
->blk_w
== 2 && surf
->blk_h
== 1)
479 if (/* RGBA8 or RGBA16F */
480 (bpe
>= 4 && bpe
<= 8 && num_channels
== 4) ||
481 /* R5G6B5 or R5G5B5A1 */
482 (bpe
== 2 && num_channels
>= 3) ||
484 (bpe
== 1 && num_channels
== 1))
491 * This must be called after the first level is computed.
493 * Copy surface-global settings like pipe/bank config from level 0 surface
494 * computation, and compute tile swizzle.
496 static int gfx6_surface_settings(ADDR_HANDLE addrlib
,
497 const struct radeon_info
*info
,
498 const struct ac_surf_config
*config
,
499 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* csio
,
500 struct radeon_surf
*surf
)
502 surf
->surf_alignment
= csio
->baseAlign
;
503 surf
->u
.legacy
.pipe_config
= csio
->pTileInfo
->pipeConfig
- 1;
504 gfx6_set_micro_tile_mode(surf
, info
);
506 /* For 2D modes only. */
507 if (csio
->tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
508 surf
->u
.legacy
.bankw
= csio
->pTileInfo
->bankWidth
;
509 surf
->u
.legacy
.bankh
= csio
->pTileInfo
->bankHeight
;
510 surf
->u
.legacy
.mtilea
= csio
->pTileInfo
->macroAspectRatio
;
511 surf
->u
.legacy
.tile_split
= csio
->pTileInfo
->tileSplitBytes
;
512 surf
->u
.legacy
.num_banks
= csio
->pTileInfo
->banks
;
513 surf
->u
.legacy
.macro_tile_index
= csio
->macroModeIndex
;
515 surf
->u
.legacy
.macro_tile_index
= 0;
518 /* Compute tile swizzle. */
519 /* TODO: fix tile swizzle with mipmapping for SI */
520 if ((info
->chip_class
>= CIK
|| config
->info
.levels
== 1) &&
521 config
->info
.surf_index
&&
522 surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
&&
523 !(surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
| RADEON_SURF_SHAREABLE
)) &&
524 !get_display_flag(config
, surf
)) {
525 ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn
= {0};
526 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut
= {0};
528 AddrBaseSwizzleIn
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
529 AddrBaseSwizzleOut
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
531 AddrBaseSwizzleIn
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
532 AddrBaseSwizzleIn
.tileIndex
= csio
->tileIndex
;
533 AddrBaseSwizzleIn
.macroModeIndex
= csio
->macroModeIndex
;
534 AddrBaseSwizzleIn
.pTileInfo
= csio
->pTileInfo
;
535 AddrBaseSwizzleIn
.tileMode
= csio
->tileMode
;
537 int r
= AddrComputeBaseSwizzle(addrlib
, &AddrBaseSwizzleIn
,
538 &AddrBaseSwizzleOut
);
542 assert(AddrBaseSwizzleOut
.tileSwizzle
<=
543 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
544 surf
->tile_swizzle
= AddrBaseSwizzleOut
.tileSwizzle
;
550 * Fill in the tiling information in \p surf based on the given surface config.
552 * The following fields of \p surf must be initialized by the caller:
553 * blk_w, blk_h, bpe, flags.
555 static int gfx6_compute_surface(ADDR_HANDLE addrlib
,
556 const struct radeon_info
*info
,
557 const struct ac_surf_config
*config
,
558 enum radeon_surf_mode mode
,
559 struct radeon_surf
*surf
)
563 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
564 ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut
= {0};
565 ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn
= {0};
566 ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut
= {0};
567 ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn
= {0};
568 ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut
= {0};
569 ADDR_TILEINFO AddrTileInfoIn
= {0};
570 ADDR_TILEINFO AddrTileInfoOut
= {0};
573 AddrSurfInfoIn
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT
);
574 AddrSurfInfoOut
.size
= sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT
);
575 AddrDccIn
.size
= sizeof(ADDR_COMPUTE_DCCINFO_INPUT
);
576 AddrDccOut
.size
= sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT
);
577 AddrHtileIn
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT
);
578 AddrHtileOut
.size
= sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT
);
579 AddrSurfInfoOut
.pTileInfo
= &AddrTileInfoOut
;
581 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
583 /* MSAA requires 2D tiling. */
584 if (config
->info
.samples
> 1)
585 mode
= RADEON_SURF_MODE_2D
;
587 /* DB doesn't support linear layouts. */
588 if (surf
->flags
& (RADEON_SURF_Z_OR_SBUFFER
) &&
589 mode
< RADEON_SURF_MODE_1D
)
590 mode
= RADEON_SURF_MODE_1D
;
592 /* Set the requested tiling mode. */
594 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
595 AddrSurfInfoIn
.tileMode
= ADDR_TM_LINEAR_ALIGNED
;
597 case RADEON_SURF_MODE_1D
:
598 AddrSurfInfoIn
.tileMode
= ADDR_TM_1D_TILED_THIN1
;
600 case RADEON_SURF_MODE_2D
:
601 AddrSurfInfoIn
.tileMode
= ADDR_TM_2D_TILED_THIN1
;
607 /* The format must be set correctly for the allocation of compressed
608 * textures to work. In other cases, setting the bpp is sufficient.
613 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
616 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
623 AddrDccIn
.bpp
= AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
626 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numSamples
=
627 MAX2(1, config
->info
.samples
);
628 AddrSurfInfoIn
.tileIndex
= -1;
630 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)) {
631 AddrDccIn
.numSamples
= AddrSurfInfoIn
.numFrags
=
632 MAX2(1, config
->info
.color_samples
);
635 /* Set the micro tile type. */
636 if (surf
->flags
& RADEON_SURF_SCANOUT
)
637 AddrSurfInfoIn
.tileType
= ADDR_DISPLAYABLE
;
638 else if (surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
)
639 AddrSurfInfoIn
.tileType
= ADDR_DEPTH_SAMPLE_ORDER
;
641 AddrSurfInfoIn
.tileType
= ADDR_NON_DISPLAYABLE
;
643 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
644 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
645 AddrSurfInfoIn
.flags
.cube
= config
->is_cube
;
646 AddrSurfInfoIn
.flags
.display
= get_display_flag(config
, surf
);
647 AddrSurfInfoIn
.flags
.pow2Pad
= config
->info
.levels
> 1;
648 AddrSurfInfoIn
.flags
.tcCompatible
= (surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) != 0;
650 /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
651 * requested, because TC-compatible HTILE requires 2D tiling.
653 AddrSurfInfoIn
.flags
.opt4Space
= !AddrSurfInfoIn
.flags
.tcCompatible
&&
654 !AddrSurfInfoIn
.flags
.fmask
&&
655 config
->info
.samples
<= 1 &&
656 (surf
->flags
& RADEON_SURF_OPTIMIZE_FOR_SPACE
);
659 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
661 * - Mipmapped array textures have low performance (discovered by a closed
664 AddrSurfInfoIn
.flags
.dccCompatible
=
665 info
->chip_class
>= VI
&&
666 !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
) &&
667 !(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
669 ((config
->info
.array_size
== 1 && config
->info
.depth
== 1) ||
670 config
->info
.levels
== 1);
672 AddrSurfInfoIn
.flags
.noStencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) == 0;
673 AddrSurfInfoIn
.flags
.compressZ
= AddrSurfInfoIn
.flags
.depth
;
675 /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
676 * for Z and stencil. This can cause a number of problems which we work
679 * - a depth part that is incompatible with mipmapped texturing
680 * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
681 * incorrect tiling applied to the stencil part, stencil buffer
682 * memory accesses that go out of bounds) even without mipmapping
684 * Some piglit tests that are prone to different types of related
686 * ./bin/ext_framebuffer_multisample-upsample 2 stencil
687 * ./bin/framebuffer-blit-levels {draw,read} stencil
688 * ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
689 * ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
690 * ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
692 int stencil_tile_idx
= -1;
694 if (AddrSurfInfoIn
.flags
.depth
&& !AddrSurfInfoIn
.flags
.noStencil
&&
695 (config
->info
.levels
> 1 || info
->family
== CHIP_STONEY
)) {
696 /* Compute stencilTileIdx that is compatible with the (depth)
697 * tileIdx. This degrades the depth surface if necessary to
698 * ensure that a matching stencilTileIdx exists. */
699 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 1;
701 /* Keep the depth mip-tail compatible with texturing. */
702 AddrSurfInfoIn
.flags
.noStencil
= 1;
705 /* Set preferred macrotile parameters. This is usually required
706 * for shared resources. This is for 2D tiling only. */
707 if (AddrSurfInfoIn
.tileMode
>= ADDR_TM_2D_TILED_THIN1
&&
708 surf
->u
.legacy
.bankw
&& surf
->u
.legacy
.bankh
&&
709 surf
->u
.legacy
.mtilea
&& surf
->u
.legacy
.tile_split
) {
710 /* If any of these parameters are incorrect, the calculation
712 AddrTileInfoIn
.banks
= surf
->u
.legacy
.num_banks
;
713 AddrTileInfoIn
.bankWidth
= surf
->u
.legacy
.bankw
;
714 AddrTileInfoIn
.bankHeight
= surf
->u
.legacy
.bankh
;
715 AddrTileInfoIn
.macroAspectRatio
= surf
->u
.legacy
.mtilea
;
716 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.tile_split
;
717 AddrTileInfoIn
.pipeConfig
= surf
->u
.legacy
.pipe_config
+ 1; /* +1 compared to GB_TILE_MODE */
718 AddrSurfInfoIn
.flags
.opt4Space
= 0;
719 AddrSurfInfoIn
.pTileInfo
= &AddrTileInfoIn
;
721 /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
722 * the tile index, because we are expected to know it if
723 * we know the other parameters.
725 * This is something that can easily be fixed in Addrlib.
726 * For now, just figure it out here.
727 * Note that only 2D_TILE_THIN1 is handled here.
729 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
730 assert(AddrSurfInfoIn
.tileMode
== ADDR_TM_2D_TILED_THIN1
);
732 if (info
->chip_class
== SI
) {
733 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
) {
735 AddrSurfInfoIn
.tileIndex
= 11; /* 16bpp */
737 AddrSurfInfoIn
.tileIndex
= 12; /* 32bpp */
740 AddrSurfInfoIn
.tileIndex
= 14; /* 8bpp */
741 else if (surf
->bpe
== 2)
742 AddrSurfInfoIn
.tileIndex
= 15; /* 16bpp */
743 else if (surf
->bpe
== 4)
744 AddrSurfInfoIn
.tileIndex
= 16; /* 32bpp */
746 AddrSurfInfoIn
.tileIndex
= 17; /* 64bpp (and 128bpp) */
750 if (AddrSurfInfoIn
.tileType
== ADDR_DISPLAYABLE
)
751 AddrSurfInfoIn
.tileIndex
= 10; /* 2D displayable */
753 AddrSurfInfoIn
.tileIndex
= 14; /* 2D non-displayable */
755 /* Addrlib doesn't set this if tileIndex is forced like above. */
756 AddrSurfInfoOut
.macroModeIndex
= cik_get_macro_tile_index(surf
);
760 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
761 surf
->num_dcc_levels
= 0;
764 surf
->dcc_alignment
= 1;
765 surf
->htile_size
= 0;
766 surf
->htile_slice_size
= 0;
767 surf
->htile_alignment
= 1;
769 const bool only_stencil
= (surf
->flags
& RADEON_SURF_SBUFFER
) &&
770 !(surf
->flags
& RADEON_SURF_ZBUFFER
);
772 /* Calculate texture layout information. */
774 for (level
= 0; level
< config
->info
.levels
; level
++) {
775 r
= gfx6_compute_level(addrlib
, config
, surf
, false, level
, compressed
,
776 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
777 &AddrDccIn
, &AddrDccOut
, &AddrHtileIn
, &AddrHtileOut
);
784 /* Check that we actually got a TC-compatible HTILE if
785 * we requested it (only for level 0, since we're not
786 * supporting HTILE on higher mip levels anyway). */
787 assert(AddrSurfInfoOut
.tcCompatible
||
788 !AddrSurfInfoIn
.flags
.tcCompatible
||
789 AddrSurfInfoIn
.flags
.matchStencilTileCfg
);
791 if (AddrSurfInfoIn
.flags
.matchStencilTileCfg
) {
792 if (!AddrSurfInfoOut
.tcCompatible
) {
793 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
794 surf
->flags
&= ~RADEON_SURF_TC_COMPATIBLE_HTILE
;
797 AddrSurfInfoIn
.flags
.matchStencilTileCfg
= 0;
798 AddrSurfInfoIn
.tileIndex
= AddrSurfInfoOut
.tileIndex
;
799 stencil_tile_idx
= AddrSurfInfoOut
.stencilTileIdx
;
801 assert(stencil_tile_idx
>= 0);
804 r
= gfx6_surface_settings(addrlib
, info
, config
,
805 &AddrSurfInfoOut
, surf
);
811 /* Calculate texture layout information for stencil. */
812 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
813 AddrSurfInfoIn
.tileIndex
= stencil_tile_idx
;
814 AddrSurfInfoIn
.bpp
= 8;
815 AddrSurfInfoIn
.flags
.depth
= 0;
816 AddrSurfInfoIn
.flags
.stencil
= 1;
817 AddrSurfInfoIn
.flags
.tcCompatible
= 0;
818 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
819 AddrTileInfoIn
.tileSplitBytes
= surf
->u
.legacy
.stencil_tile_split
;
821 for (level
= 0; level
< config
->info
.levels
; level
++) {
822 r
= gfx6_compute_level(addrlib
, config
, surf
, true, level
, compressed
,
823 &AddrSurfInfoIn
, &AddrSurfInfoOut
,
824 &AddrDccIn
, &AddrDccOut
,
829 /* DB uses the depth pitch for both stencil and depth. */
831 if (surf
->u
.legacy
.stencil_level
[level
].nblk_x
!=
832 surf
->u
.legacy
.level
[level
].nblk_x
)
833 surf
->u
.legacy
.stencil_adjusted
= true;
835 surf
->u
.legacy
.level
[level
].nblk_x
=
836 surf
->u
.legacy
.stencil_level
[level
].nblk_x
;
841 r
= gfx6_surface_settings(addrlib
, info
, config
,
842 &AddrSurfInfoOut
, surf
);
847 /* For 2D modes only. */
848 if (AddrSurfInfoOut
.tileMode
>= ADDR_TM_2D_TILED_THIN1
) {
849 surf
->u
.legacy
.stencil_tile_split
=
850 AddrSurfInfoOut
.pTileInfo
->tileSplitBytes
;
857 if (config
->info
.samples
>= 2 && AddrSurfInfoIn
.flags
.color
) {
858 ADDR_COMPUTE_FMASK_INFO_INPUT fin
= {0};
859 ADDR_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
860 ADDR_TILEINFO fmask_tile_info
= {};
862 fin
.size
= sizeof(fin
);
863 fout
.size
= sizeof(fout
);
865 fin
.tileMode
= AddrSurfInfoOut
.tileMode
;
866 fin
.pitch
= AddrSurfInfoOut
.pitch
;
867 fin
.height
= config
->info
.height
;
868 fin
.numSlices
= AddrSurfInfoIn
.numSlices
;
869 fin
.numSamples
= AddrSurfInfoIn
.numSamples
;
870 fin
.numFrags
= AddrSurfInfoIn
.numFrags
;
871 fin
.tileIndex
= AddrSurfInfoOut
.tileIndex
;
872 fout
.pTileInfo
= &fmask_tile_info
;
874 r
= AddrComputeFmaskInfo(addrlib
, &fin
, &fout
);
878 surf
->fmask_size
= fout
.fmaskBytes
;
879 surf
->fmask_alignment
= fout
.baseAlign
;
880 surf
->fmask_tile_swizzle
= 0;
882 surf
->u
.legacy
.fmask
.slice_tile_max
=
883 (fout
.pitch
* fout
.height
) / 64;
884 if (surf
->u
.legacy
.fmask
.slice_tile_max
)
885 surf
->u
.legacy
.fmask
.slice_tile_max
-= 1;
887 surf
->u
.legacy
.fmask
.tiling_index
= fout
.tileIndex
;
888 surf
->u
.legacy
.fmask
.bankh
= fout
.pTileInfo
->bankHeight
;
889 surf
->u
.legacy
.fmask
.pitch_in_pixels
= fout
.pitch
;
891 /* Compute tile swizzle for FMASK. */
892 if (config
->info
.fmask_surf_index
&&
893 !(surf
->flags
& RADEON_SURF_SHAREABLE
)) {
894 ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin
= {0};
895 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout
= {0};
897 xin
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT
);
898 xout
.size
= sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
);
900 /* This counter starts from 1 instead of 0. */
901 xin
.surfIndex
= p_atomic_inc_return(config
->info
.fmask_surf_index
);
902 xin
.tileIndex
= fout
.tileIndex
;
903 xin
.macroModeIndex
= fout
.macroModeIndex
;
904 xin
.pTileInfo
= fout
.pTileInfo
;
905 xin
.tileMode
= fin
.tileMode
;
907 int r
= AddrComputeBaseSwizzle(addrlib
, &xin
, &xout
);
911 assert(xout
.tileSwizzle
<=
912 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
913 surf
->fmask_tile_swizzle
= xout
.tileSwizzle
;
917 /* Recalculate the whole DCC miptree size including disabled levels.
918 * This is what addrlib does, but calling addrlib would be a lot more
921 if (surf
->dcc_size
&& config
->info
.levels
> 1) {
922 /* The smallest miplevels that are never compressed by DCC
923 * still read the DCC buffer via TC if the base level uses DCC,
924 * and for some reason the DCC buffer needs to be larger if
925 * the miptree uses non-zero tile_swizzle. Otherwise there are
928 * "dcc_alignment * 4" was determined by trial and error.
930 surf
->dcc_size
= align64(surf
->surf_size
>> 8,
931 surf
->dcc_alignment
* 4);
934 /* Make sure HTILE covers the whole miptree, because the shader reads
935 * TC-compatible HTILE even for levels where it's disabled by DB.
937 if (surf
->htile_size
&& config
->info
.levels
> 1)
938 surf
->htile_size
*= 2;
940 surf
->is_linear
= surf
->u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
;
941 surf
->is_displayable
= surf
->is_linear
||
942 surf
->micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
||
943 surf
->micro_tile_mode
== RADEON_MICRO_MODE_ROTATED
;
947 /* This is only called when expecting a tiled layout. */
949 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib
,
950 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
,
951 bool is_fmask
, unsigned flags
,
952 AddrSwizzleMode
*swizzle_mode
)
954 ADDR_E_RETURNCODE ret
;
955 ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin
= {0};
956 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT sout
= {0};
958 sin
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
);
959 sout
.size
= sizeof(ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
);
961 sin
.flags
= in
->flags
;
962 sin
.resourceType
= in
->resourceType
;
963 sin
.format
= in
->format
;
964 sin
.resourceLoction
= ADDR_RSRC_LOC_INVIS
;
965 /* TODO: We could allow some of these: */
966 sin
.forbiddenBlock
.micro
= 1; /* don't allow the 256B swizzle modes */
967 sin
.forbiddenBlock
.var
= 1; /* don't allow the variable-sized swizzle modes */
968 sin
.forbiddenBlock
.linear
= 1; /* don't allow linear swizzle modes */
970 sin
.width
= in
->width
;
971 sin
.height
= in
->height
;
972 sin
.numSlices
= in
->numSlices
;
973 sin
.numMipLevels
= in
->numMipLevels
;
974 sin
.numSamples
= in
->numSamples
;
975 sin
.numFrags
= in
->numFrags
;
977 if (flags
& RADEON_SURF_SCANOUT
) {
978 sin
.preferredSwSet
.sw_D
= 1;
979 /* Raven only allows S for displayable surfaces with < 64 bpp, so
980 * allow it as fallback */
981 sin
.preferredSwSet
.sw_S
= 1;
982 } else if (in
->flags
.depth
|| in
->flags
.stencil
|| is_fmask
)
983 sin
.preferredSwSet
.sw_Z
= 1;
985 sin
.preferredSwSet
.sw_S
= 1;
988 sin
.flags
.display
= 0;
993 ret
= Addr2GetPreferredSurfaceSetting(addrlib
, &sin
, &sout
);
997 *swizzle_mode
= sout
.swizzleMode
;
1001 static int gfx9_compute_miptree(ADDR_HANDLE addrlib
,
1002 const struct ac_surf_config
*config
,
1003 struct radeon_surf
*surf
, bool compressed
,
1004 ADDR2_COMPUTE_SURFACE_INFO_INPUT
*in
)
1006 ADDR2_MIP_INFO mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
1007 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT out
= {0};
1008 ADDR_E_RETURNCODE ret
;
1010 out
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
);
1011 out
.pMipInfo
= mip_info
;
1013 ret
= Addr2ComputeSurfaceInfo(addrlib
, in
, &out
);
1017 if (in
->flags
.stencil
) {
1018 surf
->u
.gfx9
.stencil
.swizzle_mode
= in
->swizzleMode
;
1019 surf
->u
.gfx9
.stencil
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
1020 out
.mipChainPitch
- 1;
1021 surf
->surf_alignment
= MAX2(surf
->surf_alignment
, out
.baseAlign
);
1022 surf
->u
.gfx9
.stencil_offset
= align(surf
->surf_size
, out
.baseAlign
);
1023 surf
->surf_size
= surf
->u
.gfx9
.stencil_offset
+ out
.surfSize
;
1027 surf
->u
.gfx9
.surf
.swizzle_mode
= in
->swizzleMode
;
1028 surf
->u
.gfx9
.surf
.epitch
= out
.epitchIsHeight
? out
.mipChainHeight
- 1 :
1029 out
.mipChainPitch
- 1;
1031 /* CMASK fast clear uses these even if FMASK isn't allocated.
1032 * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
1034 surf
->u
.gfx9
.fmask
.swizzle_mode
= surf
->u
.gfx9
.surf
.swizzle_mode
& ~0x3;
1035 surf
->u
.gfx9
.fmask
.epitch
= surf
->u
.gfx9
.surf
.epitch
;
1037 surf
->u
.gfx9
.surf_slice_size
= out
.sliceSize
;
1038 surf
->u
.gfx9
.surf_pitch
= out
.pitch
;
1039 surf
->u
.gfx9
.surf_height
= out
.height
;
1040 surf
->surf_size
= out
.surfSize
;
1041 surf
->surf_alignment
= out
.baseAlign
;
1043 if (in
->swizzleMode
== ADDR_SW_LINEAR
) {
1044 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++)
1045 surf
->u
.gfx9
.offset
[i
] = mip_info
[i
].offset
;
1048 if (in
->flags
.depth
) {
1049 assert(in
->swizzleMode
!= ADDR_SW_LINEAR
);
1052 ADDR2_COMPUTE_HTILE_INFO_INPUT hin
= {0};
1053 ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout
= {0};
1055 hin
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT
);
1056 hout
.size
= sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT
);
1058 hin
.hTileFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1059 hin
.hTileFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1060 hin
.depthFlags
= in
->flags
;
1061 hin
.swizzleMode
= in
->swizzleMode
;
1062 hin
.unalignedWidth
= in
->width
;
1063 hin
.unalignedHeight
= in
->height
;
1064 hin
.numSlices
= in
->numSlices
;
1065 hin
.numMipLevels
= in
->numMipLevels
;
1067 ret
= Addr2ComputeHtileInfo(addrlib
, &hin
, &hout
);
1071 surf
->u
.gfx9
.htile
.rb_aligned
= hin
.hTileFlags
.rbAligned
;
1072 surf
->u
.gfx9
.htile
.pipe_aligned
= hin
.hTileFlags
.pipeAligned
;
1073 surf
->htile_size
= hout
.htileBytes
;
1074 surf
->htile_slice_size
= hout
.sliceSize
;
1075 surf
->htile_alignment
= hout
.baseAlign
;
1077 /* Compute tile swizzle for the color surface.
1078 * All *_X and *_T modes can use the swizzle.
1080 if (config
->info
.surf_index
&&
1081 in
->swizzleMode
>= ADDR_SW_64KB_Z_T
&&
1082 !out
.mipChainInTail
&&
1083 !(surf
->flags
& RADEON_SURF_SHAREABLE
) &&
1084 !in
->flags
.display
) {
1085 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
1086 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
1088 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
1089 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
1091 xin
.surfIndex
= p_atomic_inc_return(config
->info
.surf_index
) - 1;
1092 xin
.flags
= in
->flags
;
1093 xin
.swizzleMode
= in
->swizzleMode
;
1094 xin
.resourceType
= in
->resourceType
;
1095 xin
.format
= in
->format
;
1096 xin
.numSamples
= in
->numSamples
;
1097 xin
.numFrags
= in
->numFrags
;
1099 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
1103 assert(xout
.pipeBankXor
<=
1104 u_bit_consecutive(0, sizeof(surf
->tile_swizzle
) * 8));
1105 surf
->tile_swizzle
= xout
.pipeBankXor
;
1109 if (!(surf
->flags
& RADEON_SURF_DISABLE_DCC
) &&
1111 in
->swizzleMode
!= ADDR_SW_LINEAR
) {
1112 ADDR2_COMPUTE_DCCINFO_INPUT din
= {0};
1113 ADDR2_COMPUTE_DCCINFO_OUTPUT dout
= {0};
1114 ADDR2_META_MIP_INFO meta_mip_info
[RADEON_SURF_MAX_LEVELS
] = {};
1116 din
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_INPUT
);
1117 dout
.size
= sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT
);
1118 dout
.pMipInfo
= meta_mip_info
;
1120 din
.dccKeyFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1121 din
.dccKeyFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1122 din
.colorFlags
= in
->flags
;
1123 din
.resourceType
= in
->resourceType
;
1124 din
.swizzleMode
= in
->swizzleMode
;
1126 din
.unalignedWidth
= in
->width
;
1127 din
.unalignedHeight
= in
->height
;
1128 din
.numSlices
= in
->numSlices
;
1129 din
.numFrags
= in
->numFrags
;
1130 din
.numMipLevels
= in
->numMipLevels
;
1131 din
.dataSurfaceSize
= out
.surfSize
;
1133 ret
= Addr2ComputeDccInfo(addrlib
, &din
, &dout
);
1137 surf
->u
.gfx9
.dcc
.rb_aligned
= din
.dccKeyFlags
.rbAligned
;
1138 surf
->u
.gfx9
.dcc
.pipe_aligned
= din
.dccKeyFlags
.pipeAligned
;
1139 surf
->u
.gfx9
.dcc_pitch_max
= dout
.pitch
- 1;
1140 surf
->dcc_size
= dout
.dccRamSize
;
1141 surf
->dcc_alignment
= dout
.dccRamBaseAlign
;
1142 surf
->num_dcc_levels
= in
->numMipLevels
;
1144 /* Disable DCC for levels that are in the mip tail.
1146 * There are two issues that this is intended to
1149 * 1. Multiple mip levels may share a cache line. This
1150 * can lead to corruption when switching between
1151 * rendering to different mip levels because the
1152 * RBs don't maintain coherency.
1154 * 2. Texturing with metadata after rendering sometimes
1155 * fails with corruption, probably for a similar
1158 * Working around these issues for all levels in the
1159 * mip tail may be overly conservative, but it's what
1162 * Alternative solutions that also work but are worse:
1163 * - Disable DCC entirely.
1164 * - Flush TC L2 after rendering.
1166 for (unsigned i
= 0; i
< in
->numMipLevels
; i
++) {
1167 if (meta_mip_info
[i
].inMiptail
) {
1168 surf
->num_dcc_levels
= i
;
1173 if (!surf
->num_dcc_levels
)
1178 if (in
->numSamples
> 1) {
1179 ADDR2_COMPUTE_FMASK_INFO_INPUT fin
= {0};
1180 ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout
= {0};
1182 fin
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT
);
1183 fout
.size
= sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT
);
1185 ret
= gfx9_get_preferred_swizzle_mode(addrlib
, in
,
1191 fin
.unalignedWidth
= in
->width
;
1192 fin
.unalignedHeight
= in
->height
;
1193 fin
.numSlices
= in
->numSlices
;
1194 fin
.numSamples
= in
->numSamples
;
1195 fin
.numFrags
= in
->numFrags
;
1197 ret
= Addr2ComputeFmaskInfo(addrlib
, &fin
, &fout
);
1201 surf
->u
.gfx9
.fmask
.swizzle_mode
= fin
.swizzleMode
;
1202 surf
->u
.gfx9
.fmask
.epitch
= fout
.pitch
- 1;
1203 surf
->fmask_size
= fout
.fmaskBytes
;
1204 surf
->fmask_alignment
= fout
.baseAlign
;
1206 /* Compute tile swizzle for the FMASK surface. */
1207 if (config
->info
.fmask_surf_index
&&
1208 fin
.swizzleMode
>= ADDR_SW_64KB_Z_T
&&
1209 !(surf
->flags
& RADEON_SURF_SHAREABLE
)) {
1210 ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin
= {0};
1211 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout
= {0};
1213 xin
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT
);
1214 xout
.size
= sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
);
1216 /* This counter starts from 1 instead of 0. */
1217 xin
.surfIndex
= p_atomic_inc_return(config
->info
.fmask_surf_index
);
1218 xin
.flags
= in
->flags
;
1219 xin
.swizzleMode
= in
->swizzleMode
;
1220 xin
.resourceType
= in
->resourceType
;
1221 xin
.format
= in
->format
;
1222 xin
.numSamples
= in
->numSamples
;
1223 xin
.numFrags
= in
->numFrags
;
1225 ret
= Addr2ComputePipeBankXor(addrlib
, &xin
, &xout
);
1229 assert(xout
.pipeBankXor
<=
1230 u_bit_consecutive(0, sizeof(surf
->fmask_tile_swizzle
) * 8));
1231 surf
->fmask_tile_swizzle
= xout
.pipeBankXor
;
1236 if (in
->swizzleMode
!= ADDR_SW_LINEAR
) {
1237 ADDR2_COMPUTE_CMASK_INFO_INPUT cin
= {0};
1238 ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout
= {0};
1240 cin
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT
);
1241 cout
.size
= sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT
);
1243 if (in
->numSamples
> 1) {
1244 /* FMASK is always aligned. */
1245 cin
.cMaskFlags
.pipeAligned
= 1;
1246 cin
.cMaskFlags
.rbAligned
= 1;
1248 cin
.cMaskFlags
.pipeAligned
= !in
->flags
.metaPipeUnaligned
;
1249 cin
.cMaskFlags
.rbAligned
= !in
->flags
.metaRbUnaligned
;
1251 cin
.colorFlags
= in
->flags
;
1252 cin
.resourceType
= in
->resourceType
;
1253 cin
.unalignedWidth
= in
->width
;
1254 cin
.unalignedHeight
= in
->height
;
1255 cin
.numSlices
= in
->numSlices
;
1257 if (in
->numSamples
> 1)
1258 cin
.swizzleMode
= surf
->u
.gfx9
.fmask
.swizzle_mode
;
1260 cin
.swizzleMode
= in
->swizzleMode
;
1262 ret
= Addr2ComputeCmaskInfo(addrlib
, &cin
, &cout
);
1266 surf
->u
.gfx9
.cmask
.rb_aligned
= cin
.cMaskFlags
.rbAligned
;
1267 surf
->u
.gfx9
.cmask
.pipe_aligned
= cin
.cMaskFlags
.pipeAligned
;
1268 surf
->u
.gfx9
.cmask_size
= cout
.cmaskBytes
;
1269 surf
->u
.gfx9
.cmask_alignment
= cout
.baseAlign
;
1276 static int gfx9_compute_surface(ADDR_HANDLE addrlib
,
1277 const struct radeon_info
*info
,
1278 const struct ac_surf_config
*config
,
1279 enum radeon_surf_mode mode
,
1280 struct radeon_surf
*surf
)
1283 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn
= {0};
1286 AddrSurfInfoIn
.size
= sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT
);
1288 compressed
= surf
->blk_w
== 4 && surf
->blk_h
== 4;
1290 /* The format must be set correctly for the allocation of compressed
1291 * textures to work. In other cases, setting the bpp is sufficient. */
1293 switch (surf
->bpe
) {
1295 AddrSurfInfoIn
.format
= ADDR_FMT_BC1
;
1298 AddrSurfInfoIn
.format
= ADDR_FMT_BC3
;
1304 switch (surf
->bpe
) {
1306 assert(!(surf
->flags
& RADEON_SURF_ZBUFFER
));
1307 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1310 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1311 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1312 AddrSurfInfoIn
.format
= ADDR_FMT_16
;
1315 assert(surf
->flags
& RADEON_SURF_ZBUFFER
||
1316 !(surf
->flags
& RADEON_SURF_SBUFFER
));
1317 AddrSurfInfoIn
.format
= ADDR_FMT_32
;
1320 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1321 AddrSurfInfoIn
.format
= ADDR_FMT_32_32
;
1324 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1325 AddrSurfInfoIn
.format
= ADDR_FMT_32_32_32
;
1328 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1329 AddrSurfInfoIn
.format
= ADDR_FMT_32_32_32_32
;
1334 AddrSurfInfoIn
.bpp
= surf
->bpe
* 8;
1337 AddrSurfInfoIn
.flags
.color
= !(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
);
1338 AddrSurfInfoIn
.flags
.depth
= (surf
->flags
& RADEON_SURF_ZBUFFER
) != 0;
1339 AddrSurfInfoIn
.flags
.display
= get_display_flag(config
, surf
);
1340 /* flags.texture currently refers to TC-compatible HTILE */
1341 AddrSurfInfoIn
.flags
.texture
= AddrSurfInfoIn
.flags
.color
||
1342 surf
->flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1343 AddrSurfInfoIn
.flags
.opt4space
= 1;
1345 AddrSurfInfoIn
.numMipLevels
= config
->info
.levels
;
1346 AddrSurfInfoIn
.numSamples
= MAX2(1, config
->info
.samples
);
1347 AddrSurfInfoIn
.numFrags
= AddrSurfInfoIn
.numSamples
;
1349 if (!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
))
1350 AddrSurfInfoIn
.numFrags
= MAX2(1, config
->info
.color_samples
);
1352 /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
1353 * as 2D to avoid having shader variants for 1D vs 2D, so all shaders
1354 * must sample 1D textures as 2D. */
1356 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_3D
;
1358 AddrSurfInfoIn
.resourceType
= ADDR_RSRC_TEX_2D
;
1360 AddrSurfInfoIn
.width
= config
->info
.width
;
1361 AddrSurfInfoIn
.height
= config
->info
.height
;
1364 AddrSurfInfoIn
.numSlices
= config
->info
.depth
;
1365 else if (config
->is_cube
)
1366 AddrSurfInfoIn
.numSlices
= 6;
1368 AddrSurfInfoIn
.numSlices
= config
->info
.array_size
;
1370 /* This is propagated to HTILE/DCC/CMASK. */
1371 AddrSurfInfoIn
.flags
.metaPipeUnaligned
= 0;
1372 AddrSurfInfoIn
.flags
.metaRbUnaligned
= 0;
1375 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1376 assert(config
->info
.samples
<= 1);
1377 assert(!(surf
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
1378 AddrSurfInfoIn
.swizzleMode
= ADDR_SW_LINEAR
;
1381 case RADEON_SURF_MODE_1D
:
1382 case RADEON_SURF_MODE_2D
:
1383 if (surf
->flags
& RADEON_SURF_IMPORTED
) {
1384 AddrSurfInfoIn
.swizzleMode
= surf
->u
.gfx9
.surf
.swizzle_mode
;
1388 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
,
1390 &AddrSurfInfoIn
.swizzleMode
);
1399 surf
->u
.gfx9
.resource_type
= AddrSurfInfoIn
.resourceType
;
1400 surf
->has_stencil
= !!(surf
->flags
& RADEON_SURF_SBUFFER
);
1402 surf
->num_dcc_levels
= 0;
1403 surf
->surf_size
= 0;
1404 surf
->fmask_size
= 0;
1406 surf
->htile_size
= 0;
1407 surf
->htile_slice_size
= 0;
1408 surf
->u
.gfx9
.surf_offset
= 0;
1409 surf
->u
.gfx9
.stencil_offset
= 0;
1410 surf
->u
.gfx9
.cmask_size
= 0;
1412 /* Calculate texture layout information. */
1413 r
= gfx9_compute_miptree(addrlib
, config
, surf
, compressed
,
1418 /* Calculate texture layout information for stencil. */
1419 if (surf
->flags
& RADEON_SURF_SBUFFER
) {
1420 AddrSurfInfoIn
.flags
.stencil
= 1;
1421 AddrSurfInfoIn
.bpp
= 8;
1422 AddrSurfInfoIn
.format
= ADDR_FMT_8
;
1424 if (!AddrSurfInfoIn
.flags
.depth
) {
1425 r
= gfx9_get_preferred_swizzle_mode(addrlib
, &AddrSurfInfoIn
,
1427 &AddrSurfInfoIn
.swizzleMode
);
1431 AddrSurfInfoIn
.flags
.depth
= 0;
1433 r
= gfx9_compute_miptree(addrlib
, config
, surf
, compressed
,
1439 surf
->is_linear
= surf
->u
.gfx9
.surf
.swizzle_mode
== ADDR_SW_LINEAR
;
1441 /* Query whether the surface is displayable. */
1442 bool displayable
= false;
1443 r
= Addr2IsValidDisplaySwizzleMode(addrlib
, surf
->u
.gfx9
.surf
.swizzle_mode
,
1444 surf
->bpe
* 8, &displayable
);
1447 surf
->is_displayable
= displayable
;
1449 switch (surf
->u
.gfx9
.surf
.swizzle_mode
) {
1451 case ADDR_SW_256B_S
:
1453 case ADDR_SW_64KB_S
:
1455 case ADDR_SW_64KB_S_T
:
1456 case ADDR_SW_4KB_S_X
:
1457 case ADDR_SW_64KB_S_X
:
1458 case ADDR_SW_VAR_S_X
:
1459 surf
->micro_tile_mode
= RADEON_MICRO_MODE_THIN
;
1463 case ADDR_SW_LINEAR
:
1464 case ADDR_SW_256B_D
:
1466 case ADDR_SW_64KB_D
:
1468 case ADDR_SW_64KB_D_T
:
1469 case ADDR_SW_4KB_D_X
:
1470 case ADDR_SW_64KB_D_X
:
1471 case ADDR_SW_VAR_D_X
:
1472 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DISPLAY
;
1476 case ADDR_SW_256B_R
:
1478 case ADDR_SW_64KB_R
:
1480 case ADDR_SW_64KB_R_T
:
1481 case ADDR_SW_4KB_R_X
:
1482 case ADDR_SW_64KB_R_X
:
1483 case ADDR_SW_VAR_R_X
:
1484 surf
->micro_tile_mode
= RADEON_MICRO_MODE_ROTATED
;
1489 case ADDR_SW_64KB_Z
:
1491 case ADDR_SW_64KB_Z_T
:
1492 case ADDR_SW_4KB_Z_X
:
1493 case ADDR_SW_64KB_Z_X
:
1494 case ADDR_SW_VAR_Z_X
:
1495 surf
->micro_tile_mode
= RADEON_MICRO_MODE_DEPTH
;
1502 /* Temporary workaround to prevent VM faults and hangs. */
1503 if (info
->family
== CHIP_VEGA12
)
1504 surf
->fmask_size
*= 8;
1509 int ac_compute_surface(ADDR_HANDLE addrlib
, const struct radeon_info
*info
,
1510 const struct ac_surf_config
*config
,
1511 enum radeon_surf_mode mode
,
1512 struct radeon_surf
*surf
)
1516 r
= surf_config_sanity(config
, surf
->flags
);
1520 if (info
->chip_class
>= GFX9
)
1521 return gfx9_compute_surface(addrlib
, info
, config
, mode
, surf
);
1523 return gfx6_compute_surface(addrlib
, info
, config
, mode
, surf
);