src/amd/common/ac_surface.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_SURFACE_H
  27 #define AC_SURFACE_H
  28
  29 #include <stdint.h>
  30
  31 #define RADEON_SURF_MAX_LEVELS                  15
  32
  33 enum radeon_surf_mode {
  34     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
  35     RADEON_SURF_MODE_1D = 2,
  36     RADEON_SURF_MODE_2D = 3,
  37 };
  38
  39 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
  40 enum radeon_micro_mode {
  41     RADEON_MICRO_MODE_DISPLAY = 0,
  42     RADEON_MICRO_MODE_THIN = 1,
  43     RADEON_MICRO_MODE_DEPTH = 2,
  44     RADEON_MICRO_MODE_ROTATED = 3,
  45 };
  46
  47 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
  48 #define RADEON_SURF_SCANOUT                     (1 << 16)
  49 #define RADEON_SURF_ZBUFFER                     (1 << 17)
  50 #define RADEON_SURF_SBUFFER                     (1 << 18)
  51 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
  52 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
  53 #define RADEON_SURF_FMASK                       (1 << 21)
  54 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
  55 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
  56 #define RADEON_SURF_IMPORTED                    (1 << 24)
  57 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
  58
  59 struct legacy_surf_level {
  60     uint64_t                    offset;
  61     uint64_t                    slice_size;
  62     uint64_t                    dcc_offset;
  63     uint64_t                    dcc_fast_clear_size;
  64     uint16_t                    nblk_x;
  65     uint16_t                    nblk_y;
  66     enum radeon_surf_mode       mode;
  67 };
  68
  69 struct legacy_surf_layout {
  70     unsigned                    bankw:4;  /* max 8 */
  71     unsigned                    bankh:4;  /* max 8 */
  72     unsigned                    mtilea:4; /* max 8 */
  73     unsigned                    tile_split:13;         /* max 4K */
  74     unsigned                    stencil_tile_split:13; /* max 4K */
  75     unsigned                    pipe_config:5;      /* max 17 */
  76     unsigned                    num_banks:5;        /* max 16 */
  77     unsigned                    macro_tile_index:4; /* max 15 */
  78
  79     /* Whether the depth miptree or stencil miptree as used by the DB are
  80      * adjusted from their TC compatible form to ensure depth/stencil
  81      * compatibility. If either is true, the corresponding plane cannot be
  82      * sampled from.
  83      */
  84     unsigned                    depth_adjusted:1;
  85     unsigned                    stencil_adjusted:1;
  86
  87     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
  88     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
  89     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
  90     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
  91 };
  92
  93 /* Same as addrlib - AddrResourceType. */
  94 enum gfx9_resource_type {
  95     RADEON_RESOURCE_1D = 0,
  96     RADEON_RESOURCE_2D,
  97     RADEON_RESOURCE_3D,
  98 };
  99
 100 struct gfx9_surf_flags {
 101     uint16_t                    swizzle_mode; /* tile mode */
 102     uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
 103 };
 104
 105 struct gfx9_surf_meta_flags {
 106     unsigned                    rb_aligned:1;   /* optimal for RBs */
 107     unsigned                    pipe_aligned:1; /* optimal for TC */
 108 };
 109
 110 struct gfx9_surf_layout {
 111     struct gfx9_surf_flags      surf;    /* color or depth surface */
 112     struct gfx9_surf_flags      fmask;   /* not added to surf_size */
 113     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 114
 115     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
 116     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 117     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 118
 119     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
 120     uint64_t                    surf_offset; /* 0 unless imported with an offset */
 121     /* The size of the 2D plane containing all mipmap levels. */
 122     uint64_t                    surf_slice_size;
 123     uint16_t                    surf_pitch; /* in blocks */
 124     uint16_t                    surf_height;
 125     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
 126     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 127
 128     uint16_t                    dcc_pitch_max;  /* (mip chain pitch - 1) */
 129
 130     uint64_t                    stencil_offset; /* separate stencil */
 131     uint64_t                    fmask_size;
 132     uint64_t                    cmask_size;
 133
 134     uint32_t                    fmask_alignment;
 135     uint32_t                    cmask_alignment;
 136 };
 137
 138 struct radeon_surf {
 139     /* Format properties. */
 140     unsigned                    blk_w:4;
 141     unsigned                    blk_h:4;
 142     unsigned                    bpe:5;
 143     /* Number of mipmap levels where DCC is enabled starting from level 0.
 144      * Non-zero levels may be disabled due to alignment constraints, but not
 145      * the first level.
 146      */
 147     unsigned                    num_dcc_levels:4;
 148     unsigned                    is_linear:1;
 149     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
 150     unsigned                    micro_tile_mode:3;
 151     uint32_t                    flags;
 152
 153     /* These are return values. Some of them can be set by the caller, but
 154      * they will be treated as hints (e.g. bankw, bankh) and might be
 155      * changed by the calculator.
 156      */
 157     uint64_t                    surf_size;
 158     uint64_t                    dcc_size;
 159     uint64_t                    htile_size;
 160
 161     uint32_t                    surf_alignment;
 162     uint32_t                    dcc_alignment;
 163     uint32_t                    htile_alignment;
 164
 165     union {
 166         /* R600-VI return values.
 167          *
 168          * Some of them can be set by the caller if certain parameters are
 169          * desirable. The allocator will try to obey them.
 170          */
 171         struct legacy_surf_layout legacy;
 172
 173         /* GFX9+ return values. */
 174         struct gfx9_surf_layout gfx9;
 175     } u;
 176 };
 177
 178 #endif /* AC_SURFACE_H */