src/amd/common/ac_surface.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_SURFACE_H
  27 #define AC_SURFACE_H
  28
  29 #include <stdint.h>
  30 #include <stdbool.h>
  31
  32 #include "amd_family.h"
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 /* Forward declarations. */
  39 typedef void* ADDR_HANDLE;
  40
  41 struct amdgpu_gpu_info;
  42 struct radeon_info;
  43
  44 #define RADEON_SURF_MAX_LEVELS                  15
  45
  46 enum radeon_surf_mode {
  47     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
  48     RADEON_SURF_MODE_1D = 2,
  49     RADEON_SURF_MODE_2D = 3,
  50 };
  51
  52 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
  53 enum radeon_micro_mode {
  54     RADEON_MICRO_MODE_DISPLAY = 0,
  55     RADEON_MICRO_MODE_THIN = 1,
  56     RADEON_MICRO_MODE_DEPTH = 2,
  57     RADEON_MICRO_MODE_ROTATED = 3,
  58 };
  59
  60 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
  61 #define RADEON_SURF_SCANOUT                     (1 << 16)
  62 #define RADEON_SURF_ZBUFFER                     (1 << 17)
  63 #define RADEON_SURF_SBUFFER                     (1 << 18)
  64 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
  65 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
  66 #define RADEON_SURF_FMASK                       (1 << 21)
  67 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
  68 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
  69 #define RADEON_SURF_IMPORTED                    (1 << 24)
  70 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
  71 #define RADEON_SURF_SHAREABLE                   (1 << 26)
  72 #define RADEON_SURF_NO_RENDER_TARGET            (1 << 27)
  73
  74 struct legacy_surf_level {
  75     uint64_t                    offset;
  76     uint32_t                    slice_size_dw; /* in dwords; max = 4GB / 4. */
  77     uint32_t                    dcc_offset; /* relative offset within DCC mip tree */
  78     uint32_t                    dcc_fast_clear_size;
  79     unsigned                    nblk_x:15;
  80     unsigned                    nblk_y:15;
  81     enum radeon_surf_mode       mode:2;
  82 };
  83
  84 struct legacy_surf_fmask {
  85     unsigned slice_tile_max; /* max 4M */
  86     uint8_t tiling_index;    /* max 31 */
  87     uint8_t bankh;           /* max 8 */
  88     uint16_t pitch_in_pixels;
  89 };
  90
  91 struct legacy_surf_layout {
  92     unsigned                    bankw:4;  /* max 8 */
  93     unsigned                    bankh:4;  /* max 8 */
  94     unsigned                    mtilea:4; /* max 8 */
  95     unsigned                    tile_split:13;         /* max 4K */
  96     unsigned                    stencil_tile_split:13; /* max 4K */
  97     unsigned                    pipe_config:5;      /* max 17 */
  98     unsigned                    num_banks:5;        /* max 16 */
  99     unsigned                    macro_tile_index:4; /* max 15 */
 100
 101     /* Whether the depth miptree or stencil miptree as used by the DB are
 102      * adjusted from their TC compatible form to ensure depth/stencil
 103      * compatibility. If either is true, the corresponding plane cannot be
 104      * sampled from.
 105      */
 106     unsigned                    depth_adjusted:1;
 107     unsigned                    stencil_adjusted:1;
 108
 109     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
 110     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 111     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 112     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 113     struct legacy_surf_fmask    fmask;
 114     unsigned                    cmask_slice_tile_max;
 115 };
 116
 117 /* Same as addrlib - AddrResourceType. */
 118 enum gfx9_resource_type {
 119     RADEON_RESOURCE_1D = 0,
 120     RADEON_RESOURCE_2D,
 121     RADEON_RESOURCE_3D,
 122 };
 123
 124 struct gfx9_surf_flags {
 125     uint16_t                    swizzle_mode; /* tile mode */
 126     uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
 127 };
 128
 129 struct gfx9_surf_meta_flags {
 130     unsigned                    rb_aligned:1;   /* optimal for RBs */
 131     unsigned                    pipe_aligned:1; /* optimal for TC */
 132 };
 133
 134 struct gfx9_surf_layout {
 135     struct gfx9_surf_flags      surf;    /* color or depth surface */
 136     struct gfx9_surf_flags      fmask;   /* not added to surf_size */
 137     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 138
 139     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
 140     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 141     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 142
 143     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
 144     uint16_t                    surf_pitch; /* in blocks */
 145     uint16_t                    surf_height;
 146
 147     uint64_t                    surf_offset; /* 0 unless imported with an offset */
 148     /* The size of the 2D plane containing all mipmap levels. */
 149     uint64_t                    surf_slice_size;
 150     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
 151     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 152
 153     uint64_t                    stencil_offset; /* separate stencil */
 154
 155     /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
 156      * The 3D engine doesn't support that layout except for chips with 1 RB.
 157      * All other chips must set rb_aligned=1.
 158      * A compute shader needs to convert from aligned DCC to unaligned.
 159      */
 160     uint32_t                    display_dcc_size;
 161     uint32_t                    display_dcc_alignment;
 162     uint16_t                    display_dcc_pitch_max;  /* (mip chain pitch - 1) */
 163     bool                        dcc_retile_use_uint16; /* if all values fit into uint16_t */
 164     uint32_t                    dcc_retile_num_elements;
 165     uint32_t                    *dcc_retile_map;
 166 };
 167
 168 struct radeon_surf {
 169     /* Format properties. */
 170     unsigned                    blk_w:4;
 171     unsigned                    blk_h:4;
 172     unsigned                    bpe:5;
 173     /* Number of mipmap levels where DCC is enabled starting from level 0.
 174      * Non-zero levels may be disabled due to alignment constraints, but not
 175      * the first level.
 176      */
 177     unsigned                    num_dcc_levels:4;
 178     unsigned                    is_linear:1;
 179     unsigned                    has_stencil:1;
 180     /* This might be true even if micro_tile_mode isn't displayable or rotated. */
 181     unsigned                    is_displayable:1;
 182     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
 183     unsigned                    micro_tile_mode:3;
 184     uint32_t                    flags;
 185
 186     /* These are return values. Some of them can be set by the caller, but
 187      * they will be treated as hints (e.g. bankw, bankh) and might be
 188      * changed by the calculator.
 189      */
 190
 191     /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
 192      * The value is the same for all mipmap levels. Supported tile modes:
 193      * - GFX6: Only macro tiling.
 194      * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip
 195      *   tail.
 196      *
 197      * Only these surfaces are allowed to set it:
 198      * - color (if it doesn't have to be displayable)
 199      * - DCC (same tile swizzle as color)
 200      * - FMASK
 201      * - CMASK if it's TC-compatible or if the gen is GFX9
 202      * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
 203      */
 204     uint8_t                     tile_swizzle;
 205     uint8_t                     fmask_tile_swizzle;
 206
 207     uint64_t                    surf_size;
 208     uint64_t                    fmask_size;
 209     uint32_t                    surf_alignment;
 210     uint32_t                    fmask_alignment;
 211
 212     /* DCC and HTILE are very small. */
 213     uint32_t                    dcc_size;
 214     uint32_t                    dcc_alignment;
 215
 216     uint32_t                    htile_size;
 217     uint32_t                    htile_slice_size;
 218     uint32_t                    htile_alignment;
 219
 220     uint32_t                    cmask_size;
 221     uint32_t                    cmask_alignment;
 222
 223     union {
 224         /* Return values for GFX8 and older.
 225          *
 226          * Some of them can be set by the caller if certain parameters are
 227          * desirable. The allocator will try to obey them.
 228          */
 229         struct legacy_surf_layout legacy;
 230
 231         /* GFX9+ return values. */
 232         struct gfx9_surf_layout gfx9;
 233     } u;
 234 };
 235
 236 struct ac_surf_info {
 237         uint32_t width;
 238         uint32_t height;
 239         uint32_t depth;
 240         uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */
 241         uint8_t storage_samples; /* For color: allocated samples */
 242         uint8_t levels;
 243         uint8_t num_channels; /* heuristic for displayability */
 244         uint16_t array_size;
 245         uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
 246         uint32_t *fmask_surf_index;
 247 };
 248
 249 struct ac_surf_config {
 250         struct ac_surf_info info;
 251         unsigned is_3d : 1;
 252         unsigned is_cube : 1;
 253 };
 254
 255 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 256                                const struct amdgpu_gpu_info *amdinfo,
 257                                uint64_t *max_alignment);
 258
 259 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 260                        const struct ac_surf_config * config,
 261                        enum radeon_surf_mode mode,
 262                        struct radeon_surf *surf);
 263
 264 #ifdef __cplusplus
 265 }
 266 #endif
 267
 268 #endif /* AC_SURFACE_H */