src/amd/common/ac_surface.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_SURFACE_H
  27 #define AC_SURFACE_H
  28
  29 #include <stdint.h>
  30 #include <stdbool.h>
  31
  32 #include "amd_family.h"
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 /* Forward declarations. */
  39 typedef void* ADDR_HANDLE;
  40
  41 struct amdgpu_gpu_info;
  42 struct radeon_info;
  43
  44 #define RADEON_SURF_MAX_LEVELS                  15
  45
  46 enum radeon_surf_mode {
  47     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
  48     RADEON_SURF_MODE_1D = 2,
  49     RADEON_SURF_MODE_2D = 3,
  50 };
  51
  52 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
  53 enum radeon_micro_mode {
  54     RADEON_MICRO_MODE_DISPLAY = 0,
  55     RADEON_MICRO_MODE_THIN = 1,
  56     RADEON_MICRO_MODE_DEPTH = 2,
  57     RADEON_MICRO_MODE_ROTATED = 3, /* gfx10+: render target */
  58 };
  59
  60 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
  61 #define RADEON_SURF_SCANOUT                     (1 << 16)
  62 #define RADEON_SURF_ZBUFFER                     (1 << 17)
  63 #define RADEON_SURF_SBUFFER                     (1 << 18)
  64 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
  65 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
  66 #define RADEON_SURF_FMASK                       (1 << 21)
  67 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
  68 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
  69 #define RADEON_SURF_IMPORTED                    (1 << 24)
  70 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
  71 #define RADEON_SURF_SHAREABLE                   (1 << 26)
  72 #define RADEON_SURF_NO_RENDER_TARGET            (1 << 27)
  73 #define RADEON_SURF_FORCE_SWIZZLE_MODE          (1 << 28)
  74 #define RADEON_SURF_NO_FMASK                    (1 << 29)
  75 #define RADEON_SURF_NO_HTILE                    (1 << 30)
  76
  77 struct legacy_surf_level {
  78     uint64_t                    offset;
  79     uint32_t                    slice_size_dw; /* in dwords; max = 4GB / 4. */
  80     uint32_t                    dcc_offset; /* relative offset within DCC mip tree */
  81     uint32_t                    dcc_fast_clear_size;
  82     uint32_t                    dcc_slice_fast_clear_size;
  83     unsigned                    nblk_x:15;
  84     unsigned                    nblk_y:15;
  85     enum radeon_surf_mode       mode:2;
  86 };
  87
  88 struct legacy_surf_fmask {
  89     unsigned slice_tile_max; /* max 4M */
  90     uint8_t tiling_index;    /* max 31 */
  91     uint8_t bankh;           /* max 8 */
  92     uint16_t pitch_in_pixels;
  93     uint64_t slice_size;
  94 };
  95
  96 struct legacy_surf_layout {
  97     unsigned                    bankw:4;  /* max 8 */
  98     unsigned                    bankh:4;  /* max 8 */
  99     unsigned                    mtilea:4; /* max 8 */
 100     unsigned                    tile_split:13;         /* max 4K */
 101     unsigned                    stencil_tile_split:13; /* max 4K */
 102     unsigned                    pipe_config:5;      /* max 17 */
 103     unsigned                    num_banks:5;        /* max 16 */
 104     unsigned                    macro_tile_index:4; /* max 15 */
 105
 106     /* Whether the depth miptree or stencil miptree as used by the DB are
 107      * adjusted from their TC compatible form to ensure depth/stencil
 108      * compatibility. If either is true, the corresponding plane cannot be
 109      * sampled from.
 110      */
 111     unsigned                    depth_adjusted:1;
 112     unsigned                    stencil_adjusted:1;
 113
 114     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
 115     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 116     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 117     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 118     struct legacy_surf_fmask    fmask;
 119     unsigned                    cmask_slice_tile_max;
 120 };
 121
 122 /* Same as addrlib - AddrResourceType. */
 123 enum gfx9_resource_type {
 124     RADEON_RESOURCE_1D = 0,
 125     RADEON_RESOURCE_2D,
 126     RADEON_RESOURCE_3D,
 127 };
 128
 129 struct gfx9_surf_flags {
 130     uint16_t                    swizzle_mode; /* tile mode */
 131     uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
 132 };
 133
 134 struct gfx9_surf_meta_flags {
 135     unsigned                    rb_aligned:1;   /* optimal for RBs */
 136     unsigned                    pipe_aligned:1; /* optimal for TC */
 137 };
 138
 139 struct gfx9_surf_layout {
 140     struct gfx9_surf_flags      surf;    /* color or depth surface */
 141     struct gfx9_surf_flags      fmask;   /* not added to surf_size */
 142     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 143
 144     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
 145     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 146     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 147
 148     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
 149     uint16_t                    surf_pitch; /* in blocks */
 150     uint16_t                    surf_height;
 151
 152     uint64_t                    surf_offset; /* 0 unless imported with an offset */
 153     /* The size of the 2D plane containing all mipmap levels. */
 154     uint64_t                    surf_slice_size;
 155     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
 156     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 157
 158     uint64_t                    stencil_offset; /* separate stencil */
 159
 160     /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
 161      * The 3D engine doesn't support that layout except for chips with 1 RB.
 162      * All other chips must set rb_aligned=1.
 163      * A compute shader needs to convert from aligned DCC to unaligned.
 164      */
 165     uint32_t                    display_dcc_size;
 166     uint32_t                    display_dcc_alignment;
 167     uint16_t                    display_dcc_pitch_max;  /* (mip chain pitch - 1) */
 168     bool                        dcc_retile_use_uint16; /* if all values fit into uint16_t */
 169     uint32_t                    dcc_retile_num_elements;
 170     uint32_t                    *dcc_retile_map;
 171 };
 172
 173 struct radeon_surf {
 174     /* Format properties. */
 175     unsigned                    blk_w:4;
 176     unsigned                    blk_h:4;
 177     unsigned                    bpe:5;
 178     /* Number of mipmap levels where DCC is enabled starting from level 0.
 179      * Non-zero levels may be disabled due to alignment constraints, but not
 180      * the first level.
 181      */
 182     unsigned                    num_dcc_levels:4;
 183     unsigned                    is_linear:1;
 184     unsigned                    has_stencil:1;
 185     /* This might be true even if micro_tile_mode isn't displayable or rotated. */
 186     unsigned                    is_displayable:1;
 187     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
 188     unsigned                    micro_tile_mode:3;
 189     uint32_t                    flags;
 190
 191     /* These are return values. Some of them can be set by the caller, but
 192      * they will be treated as hints (e.g. bankw, bankh) and might be
 193      * changed by the calculator.
 194      */
 195
 196     /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
 197      * The value is the same for all mipmap levels. Supported tile modes:
 198      * - GFX6: Only macro tiling.
 199      * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip
 200      *   tail.
 201      *
 202      * Only these surfaces are allowed to set it:
 203      * - color (if it doesn't have to be displayable)
 204      * - DCC (same tile swizzle as color)
 205      * - FMASK
 206      * - CMASK if it's TC-compatible or if the gen is GFX9
 207      * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
 208      */
 209     uint8_t                     tile_swizzle;
 210     uint8_t                     fmask_tile_swizzle;
 211
 212     uint64_t                    surf_size;
 213     uint64_t                    fmask_size;
 214     uint32_t                    surf_alignment;
 215     uint32_t                    fmask_alignment;
 216
 217     /* DCC and HTILE are very small. */
 218     uint32_t                    dcc_size;
 219     uint32_t                    dcc_slice_size;
 220     uint32_t                    dcc_alignment;
 221
 222     uint32_t                    htile_size;
 223     uint32_t                    htile_slice_size;
 224     uint32_t                    htile_alignment;
 225
 226     uint32_t                    cmask_size;
 227     uint32_t                    cmask_slice_size;
 228     uint32_t                    cmask_alignment;
 229
 230     /* All buffers combined. */
 231     uint64_t                    htile_offset;
 232     uint64_t                    fmask_offset;
 233     uint64_t                    cmask_offset;
 234     uint64_t                    dcc_offset;
 235     uint64_t                    display_dcc_offset;
 236     uint64_t                    dcc_retile_map_offset;
 237     uint64_t                    total_size;
 238
 239     union {
 240         /* Return values for GFX8 and older.
 241          *
 242          * Some of them can be set by the caller if certain parameters are
 243          * desirable. The allocator will try to obey them.
 244          */
 245         struct legacy_surf_layout legacy;
 246
 247         /* GFX9+ return values. */
 248         struct gfx9_surf_layout gfx9;
 249     } u;
 250 };
 251
 252 struct ac_surf_info {
 253         uint32_t width;
 254         uint32_t height;
 255         uint32_t depth;
 256         uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */
 257         uint8_t storage_samples; /* For color: allocated samples */
 258         uint8_t levels;
 259         uint8_t num_channels; /* heuristic for displayability */
 260         uint16_t array_size;
 261         uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
 262         uint32_t *fmask_surf_index;
 263 };
 264
 265 struct ac_surf_config {
 266         struct ac_surf_info info;
 267         unsigned is_1d : 1;
 268         unsigned is_3d : 1;
 269         unsigned is_cube : 1;
 270 };
 271
 272 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 273                                const struct amdgpu_gpu_info *amdinfo,
 274                                uint64_t *max_alignment);
 275
 276 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 277                        const struct ac_surf_config * config,
 278                        enum radeon_surf_mode mode,
 279                        struct radeon_surf *surf);
 280
 281 #ifdef __cplusplus
 282 }
 283 #endif
 284
 285 #endif /* AC_SURFACE_H */