src/amd/common/ac_surface.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_SURFACE_H
  27 #define AC_SURFACE_H
  28
  29 #include <stdint.h>
  30
  31 #include "amd_family.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 /* Forward declarations. */
  38 typedef void* ADDR_HANDLE;
  39
  40 struct amdgpu_gpu_info;
  41 struct radeon_info;
  42
  43 #define RADEON_SURF_MAX_LEVELS                  15
  44
  45 enum radeon_surf_mode {
  46     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
  47     RADEON_SURF_MODE_1D = 2,
  48     RADEON_SURF_MODE_2D = 3,
  49 };
  50
  51 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
  52 enum radeon_micro_mode {
  53     RADEON_MICRO_MODE_DISPLAY = 0,
  54     RADEON_MICRO_MODE_THIN = 1,
  55     RADEON_MICRO_MODE_DEPTH = 2,
  56     RADEON_MICRO_MODE_ROTATED = 3,
  57 };
  58
  59 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
  60 #define RADEON_SURF_SCANOUT                     (1 << 16)
  61 #define RADEON_SURF_ZBUFFER                     (1 << 17)
  62 #define RADEON_SURF_SBUFFER                     (1 << 18)
  63 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
  64 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
  65 #define RADEON_SURF_FMASK                       (1 << 21)
  66 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
  67 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
  68 #define RADEON_SURF_IMPORTED                    (1 << 24)
  69 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
  70 #define RADEON_SURF_SHAREABLE                   (1 << 26)
  71 #define RADEON_SURF_NO_RENDER_TARGET            (1 << 27)
  72
  73 struct legacy_surf_level {
  74     uint64_t                    offset;
  75     uint32_t                    slice_size_dw; /* in dwords; max = 4GB / 4. */
  76     uint32_t                    dcc_offset; /* relative offset within DCC mip tree */
  77     uint32_t                    dcc_fast_clear_size;
  78     unsigned                    nblk_x:15;
  79     unsigned                    nblk_y:15;
  80     enum radeon_surf_mode       mode:2;
  81 };
  82
  83 struct legacy_surf_fmask {
  84     unsigned slice_tile_max; /* max 4M */
  85     uint8_t tiling_index;    /* max 31 */
  86     uint8_t bankh;           /* max 8 */
  87     uint16_t pitch_in_pixels;
  88 };
  89
  90 struct legacy_surf_layout {
  91     unsigned                    bankw:4;  /* max 8 */
  92     unsigned                    bankh:4;  /* max 8 */
  93     unsigned                    mtilea:4; /* max 8 */
  94     unsigned                    tile_split:13;         /* max 4K */
  95     unsigned                    stencil_tile_split:13; /* max 4K */
  96     unsigned                    pipe_config:5;      /* max 17 */
  97     unsigned                    num_banks:5;        /* max 16 */
  98     unsigned                    macro_tile_index:4; /* max 15 */
  99
 100     /* Whether the depth miptree or stencil miptree as used by the DB are
 101      * adjusted from their TC compatible form to ensure depth/stencil
 102      * compatibility. If either is true, the corresponding plane cannot be
 103      * sampled from.
 104      */
 105     unsigned                    depth_adjusted:1;
 106     unsigned                    stencil_adjusted:1;
 107
 108     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
 109     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 110     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 111     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 112     struct legacy_surf_fmask    fmask;
 113     unsigned                    cmask_slice_tile_max;
 114 };
 115
 116 /* Same as addrlib - AddrResourceType. */
 117 enum gfx9_resource_type {
 118     RADEON_RESOURCE_1D = 0,
 119     RADEON_RESOURCE_2D,
 120     RADEON_RESOURCE_3D,
 121 };
 122
 123 struct gfx9_surf_flags {
 124     uint16_t                    swizzle_mode; /* tile mode */
 125     uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
 126 };
 127
 128 struct gfx9_surf_meta_flags {
 129     unsigned                    rb_aligned:1;   /* optimal for RBs */
 130     unsigned                    pipe_aligned:1; /* optimal for TC */
 131 };
 132
 133 struct gfx9_surf_layout {
 134     struct gfx9_surf_flags      surf;    /* color or depth surface */
 135     struct gfx9_surf_flags      fmask;   /* not added to surf_size */
 136     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 137
 138     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
 139     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 140     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 141
 142     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
 143     uint16_t                    surf_pitch; /* in blocks */
 144     uint16_t                    surf_height;
 145
 146     uint64_t                    surf_offset; /* 0 unless imported with an offset */
 147     /* The size of the 2D plane containing all mipmap levels. */
 148     uint64_t                    surf_slice_size;
 149     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
 150     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 151
 152     uint16_t                    display_dcc_pitch_max;  /* (mip chain pitch - 1) */
 153
 154     uint64_t                    stencil_offset; /* separate stencil */
 155 };
 156
 157 struct radeon_surf {
 158     /* Format properties. */
 159     unsigned                    blk_w:4;
 160     unsigned                    blk_h:4;
 161     unsigned                    bpe:5;
 162     /* Number of mipmap levels where DCC is enabled starting from level 0.
 163      * Non-zero levels may be disabled due to alignment constraints, but not
 164      * the first level.
 165      */
 166     unsigned                    num_dcc_levels:4;
 167     unsigned                    is_linear:1;
 168     unsigned                    has_stencil:1;
 169     /* This might be true even if micro_tile_mode isn't displayable or rotated. */
 170     unsigned                    is_displayable:1;
 171     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
 172     unsigned                    micro_tile_mode:3;
 173     uint32_t                    flags;
 174
 175     /* These are return values. Some of them can be set by the caller, but
 176      * they will be treated as hints (e.g. bankw, bankh) and might be
 177      * changed by the calculator.
 178      */
 179
 180     /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
 181      * The value is the same for all mipmap levels. Supported tile modes:
 182      * - GFX6: Only macro tiling.
 183      * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip
 184      *   tail.
 185      *
 186      * Only these surfaces are allowed to set it:
 187      * - color (if it doesn't have to be displayable)
 188      * - DCC (same tile swizzle as color)
 189      * - FMASK
 190      * - CMASK if it's TC-compatible or if the gen is GFX9
 191      * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
 192      */
 193     uint8_t                     tile_swizzle;
 194     uint8_t                     fmask_tile_swizzle;
 195
 196     uint64_t                    surf_size;
 197     uint64_t                    fmask_size;
 198     uint32_t                    surf_alignment;
 199     uint32_t                    fmask_alignment;
 200
 201     /* DCC and HTILE are very small. */
 202     uint32_t                    dcc_size;
 203     uint32_t                    dcc_alignment;
 204
 205     uint32_t                    htile_size;
 206     uint32_t                    htile_slice_size;
 207     uint32_t                    htile_alignment;
 208
 209     uint32_t                    cmask_size;
 210     uint32_t                    cmask_alignment;
 211
 212     union {
 213         /* R600-VI return values.
 214          *
 215          * Some of them can be set by the caller if certain parameters are
 216          * desirable. The allocator will try to obey them.
 217          */
 218         struct legacy_surf_layout legacy;
 219
 220         /* GFX9+ return values. */
 221         struct gfx9_surf_layout gfx9;
 222     } u;
 223 };
 224
 225 struct ac_surf_info {
 226         uint32_t width;
 227         uint32_t height;
 228         uint32_t depth;
 229         uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */
 230         uint8_t storage_samples; /* For color: allocated samples */
 231         uint8_t levels;
 232         uint8_t num_channels; /* heuristic for displayability */
 233         uint16_t array_size;
 234         uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
 235         uint32_t *fmask_surf_index;
 236 };
 237
 238 struct ac_surf_config {
 239         struct ac_surf_info info;
 240         unsigned is_3d : 1;
 241         unsigned is_cube : 1;
 242 };
 243
 244 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 245                                const struct amdgpu_gpu_info *amdinfo,
 246                                uint64_t *max_alignment);
 247
 248 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 249                        const struct ac_surf_config * config,
 250                        enum radeon_surf_mode mode,
 251                        struct radeon_surf *surf);
 252
 253 void ac_compute_cmask(const struct radeon_info *info,
 254                       const struct ac_surf_config *config,
 255                       struct radeon_surf *surf);
 256
 257 #ifdef __cplusplus
 258 }
 259 #endif
 260
 261 #endif /* AC_SURFACE_H */