src/amd/common/ac_surface.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_SURFACE_H
  27 #define AC_SURFACE_H
  28
  29 #include <stdint.h>
  30 #include <stdbool.h>
  31
  32 #include "amd_family.h"
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 /* Forward declarations. */
  39 typedef void* ADDR_HANDLE;
  40
  41 struct amdgpu_gpu_info;
  42 struct radeon_info;
  43
  44 #define RADEON_SURF_MAX_LEVELS                  15
  45
  46 enum radeon_surf_mode {
  47     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
  48     RADEON_SURF_MODE_1D = 2,
  49     RADEON_SURF_MODE_2D = 3,
  50 };
  51
  52 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
  53 enum radeon_micro_mode {
  54     RADEON_MICRO_MODE_DISPLAY = 0,
  55     RADEON_MICRO_MODE_THIN = 1,
  56     RADEON_MICRO_MODE_DEPTH = 2,
  57     RADEON_MICRO_MODE_ROTATED = 3,
  58 };
  59
  60 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
  61 #define RADEON_SURF_SCANOUT                     (1 << 16)
  62 #define RADEON_SURF_ZBUFFER                     (1 << 17)
  63 #define RADEON_SURF_SBUFFER                     (1 << 18)
  64 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
  65 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
  66 #define RADEON_SURF_FMASK                       (1 << 21)
  67 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
  68 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
  69 #define RADEON_SURF_IMPORTED                    (1 << 24)
  70 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
  71 #define RADEON_SURF_SHAREABLE                   (1 << 26)
  72 #define RADEON_SURF_NO_RENDER_TARGET            (1 << 27)
  73
  74 struct legacy_surf_level {
  75     uint64_t                    offset;
  76     uint32_t                    slice_size_dw; /* in dwords; max = 4GB / 4. */
  77     uint32_t                    dcc_offset; /* relative offset within DCC mip tree */
  78     uint32_t                    dcc_fast_clear_size;
  79     unsigned                    nblk_x:15;
  80     unsigned                    nblk_y:15;
  81     enum radeon_surf_mode       mode:2;
  82 };
  83
  84 struct legacy_surf_fmask {
  85     unsigned slice_tile_max; /* max 4M */
  86     uint8_t tiling_index;    /* max 31 */
  87     uint8_t bankh;           /* max 8 */
  88     uint16_t pitch_in_pixels;
  89     uint64_t slice_size;
  90 };
  91
  92 struct legacy_surf_layout {
  93     unsigned                    bankw:4;  /* max 8 */
  94     unsigned                    bankh:4;  /* max 8 */
  95     unsigned                    mtilea:4; /* max 8 */
  96     unsigned                    tile_split:13;         /* max 4K */
  97     unsigned                    stencil_tile_split:13; /* max 4K */
  98     unsigned                    pipe_config:5;      /* max 17 */
  99     unsigned                    num_banks:5;        /* max 16 */
 100     unsigned                    macro_tile_index:4; /* max 15 */
 101
 102     /* Whether the depth miptree or stencil miptree as used by the DB are
 103      * adjusted from their TC compatible form to ensure depth/stencil
 104      * compatibility. If either is true, the corresponding plane cannot be
 105      * sampled from.
 106      */
 107     unsigned                    depth_adjusted:1;
 108     unsigned                    stencil_adjusted:1;
 109
 110     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
 111     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 112     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 113     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 114     struct legacy_surf_fmask    fmask;
 115     unsigned                    cmask_slice_tile_max;
 116 };
 117
 118 /* Same as addrlib - AddrResourceType. */
 119 enum gfx9_resource_type {
 120     RADEON_RESOURCE_1D = 0,
 121     RADEON_RESOURCE_2D,
 122     RADEON_RESOURCE_3D,
 123 };
 124
 125 struct gfx9_surf_flags {
 126     uint16_t                    swizzle_mode; /* tile mode */
 127     uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
 128 };
 129
 130 struct gfx9_surf_meta_flags {
 131     unsigned                    rb_aligned:1;   /* optimal for RBs */
 132     unsigned                    pipe_aligned:1; /* optimal for TC */
 133 };
 134
 135 struct gfx9_surf_layout {
 136     struct gfx9_surf_flags      surf;    /* color or depth surface */
 137     struct gfx9_surf_flags      fmask;   /* not added to surf_size */
 138     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 139
 140     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
 141     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 142     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 143
 144     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
 145     uint16_t                    surf_pitch; /* in blocks */
 146     uint16_t                    surf_height;
 147
 148     uint64_t                    surf_offset; /* 0 unless imported with an offset */
 149     /* The size of the 2D plane containing all mipmap levels. */
 150     uint64_t                    surf_slice_size;
 151     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
 152     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 153
 154     uint64_t                    stencil_offset; /* separate stencil */
 155
 156     /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
 157      * The 3D engine doesn't support that layout except for chips with 1 RB.
 158      * All other chips must set rb_aligned=1.
 159      * A compute shader needs to convert from aligned DCC to unaligned.
 160      */
 161     uint32_t                    display_dcc_size;
 162     uint32_t                    display_dcc_alignment;
 163     uint16_t                    display_dcc_pitch_max;  /* (mip chain pitch - 1) */
 164     bool                        dcc_retile_use_uint16; /* if all values fit into uint16_t */
 165     uint32_t                    dcc_retile_num_elements;
 166     uint32_t                    *dcc_retile_map;
 167 };
 168
 169 struct radeon_surf {
 170     /* Format properties. */
 171     unsigned                    blk_w:4;
 172     unsigned                    blk_h:4;
 173     unsigned                    bpe:5;
 174     /* Number of mipmap levels where DCC is enabled starting from level 0.
 175      * Non-zero levels may be disabled due to alignment constraints, but not
 176      * the first level.
 177      */
 178     unsigned                    num_dcc_levels:4;
 179     unsigned                    is_linear:1;
 180     unsigned                    has_stencil:1;
 181     /* This might be true even if micro_tile_mode isn't displayable or rotated. */
 182     unsigned                    is_displayable:1;
 183     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
 184     unsigned                    micro_tile_mode:3;
 185     uint32_t                    flags;
 186
 187     /* These are return values. Some of them can be set by the caller, but
 188      * they will be treated as hints (e.g. bankw, bankh) and might be
 189      * changed by the calculator.
 190      */
 191
 192     /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
 193      * The value is the same for all mipmap levels. Supported tile modes:
 194      * - GFX6: Only macro tiling.
 195      * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip
 196      *   tail.
 197      *
 198      * Only these surfaces are allowed to set it:
 199      * - color (if it doesn't have to be displayable)
 200      * - DCC (same tile swizzle as color)
 201      * - FMASK
 202      * - CMASK if it's TC-compatible or if the gen is GFX9
 203      * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
 204      */
 205     uint8_t                     tile_swizzle;
 206     uint8_t                     fmask_tile_swizzle;
 207
 208     uint64_t                    surf_size;
 209     uint64_t                    fmask_size;
 210     uint32_t                    surf_alignment;
 211     uint32_t                    fmask_alignment;
 212
 213     /* DCC and HTILE are very small. */
 214     uint32_t                    dcc_size;
 215     uint32_t                    dcc_alignment;
 216
 217     uint32_t                    htile_size;
 218     uint32_t                    htile_slice_size;
 219     uint32_t                    htile_alignment;
 220
 221     uint32_t                    cmask_size;
 222     uint32_t                    cmask_slice_size;
 223     uint32_t                    cmask_alignment;
 224
 225     union {
 226         /* Return values for GFX8 and older.
 227          *
 228          * Some of them can be set by the caller if certain parameters are
 229          * desirable. The allocator will try to obey them.
 230          */
 231         struct legacy_surf_layout legacy;
 232
 233         /* GFX9+ return values. */
 234         struct gfx9_surf_layout gfx9;
 235     } u;
 236 };
 237
 238 struct ac_surf_info {
 239         uint32_t width;
 240         uint32_t height;
 241         uint32_t depth;
 242         uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */
 243         uint8_t storage_samples; /* For color: allocated samples */
 244         uint8_t levels;
 245         uint8_t num_channels; /* heuristic for displayability */
 246         uint16_t array_size;
 247         uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
 248         uint32_t *fmask_surf_index;
 249 };
 250
 251 struct ac_surf_config {
 252         struct ac_surf_info info;
 253         unsigned is_3d : 1;
 254         unsigned is_cube : 1;
 255 };
 256
 257 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 258                                const struct amdgpu_gpu_info *amdinfo,
 259                                uint64_t *max_alignment);
 260
 261 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 262                        const struct ac_surf_config * config,
 263                        enum radeon_surf_mode mode,
 264                        struct radeon_surf *surf);
 265
 266 #ifdef __cplusplus
 267 }
 268 #endif
 269
 270 #endif /* AC_SURFACE_H */