src/amd/common/ac_surface.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_SURFACE_H
  27 #define AC_SURFACE_H
  28
  29 #include <stdint.h>
  30
  31 #include "amd_family.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 /* Forward declarations. */
  38 typedef void* ADDR_HANDLE;
  39
  40 struct amdgpu_gpu_info;
  41 struct radeon_info;
  42
  43 #define RADEON_SURF_MAX_LEVELS                  15
  44
  45 enum radeon_surf_mode {
  46     RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
  47     RADEON_SURF_MODE_1D = 2,
  48     RADEON_SURF_MODE_2D = 3,
  49 };
  50
  51 /* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
  52 enum radeon_micro_mode {
  53     RADEON_MICRO_MODE_DISPLAY = 0,
  54     RADEON_MICRO_MODE_THIN = 1,
  55     RADEON_MICRO_MODE_DEPTH = 2,
  56     RADEON_MICRO_MODE_ROTATED = 3,
  57 };
  58
  59 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
  60 #define RADEON_SURF_SCANOUT                     (1 << 16)
  61 #define RADEON_SURF_ZBUFFER                     (1 << 17)
  62 #define RADEON_SURF_SBUFFER                     (1 << 18)
  63 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
  64 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
  65 #define RADEON_SURF_FMASK                       (1 << 21)
  66 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
  67 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
  68 #define RADEON_SURF_IMPORTED                    (1 << 24)
  69 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
  70
  71 struct legacy_surf_level {
  72     uint64_t                    offset;
  73     uint64_t                    slice_size;
  74     uint64_t                    dcc_offset;
  75     uint64_t                    dcc_fast_clear_size;
  76     uint16_t                    nblk_x;
  77     uint16_t                    nblk_y;
  78     enum radeon_surf_mode       mode;
  79 };
  80
  81 struct legacy_surf_layout {
  82     unsigned                    bankw:4;  /* max 8 */
  83     unsigned                    bankh:4;  /* max 8 */
  84     unsigned                    mtilea:4; /* max 8 */
  85     unsigned                    tile_split:13;         /* max 4K */
  86     unsigned                    stencil_tile_split:13; /* max 4K */
  87     unsigned                    pipe_config:5;      /* max 17 */
  88     unsigned                    num_banks:5;        /* max 16 */
  89     unsigned                    macro_tile_index:4; /* max 15 */
  90
  91     /* Whether the depth miptree or stencil miptree as used by the DB are
  92      * adjusted from their TC compatible form to ensure depth/stencil
  93      * compatibility. If either is true, the corresponding plane cannot be
  94      * sampled from.
  95      */
  96     unsigned                    depth_adjusted:1;
  97     unsigned                    stencil_adjusted:1;
  98
  99     struct legacy_surf_level    level[RADEON_SURF_MAX_LEVELS];
 100     struct legacy_surf_level    stencil_level[RADEON_SURF_MAX_LEVELS];
 101     uint8_t                     tiling_index[RADEON_SURF_MAX_LEVELS];
 102     uint8_t                     stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
 103 };
 104
 105 /* Same as addrlib - AddrResourceType. */
 106 enum gfx9_resource_type {
 107     RADEON_RESOURCE_1D = 0,
 108     RADEON_RESOURCE_2D,
 109     RADEON_RESOURCE_3D,
 110 };
 111
 112 struct gfx9_surf_flags {
 113     uint16_t                    swizzle_mode; /* tile mode */
 114     uint16_t                    epitch; /* (pitch - 1) or (height - 1) */
 115 };
 116
 117 struct gfx9_surf_meta_flags {
 118     unsigned                    rb_aligned:1;   /* optimal for RBs */
 119     unsigned                    pipe_aligned:1; /* optimal for TC */
 120 };
 121
 122 struct gfx9_surf_layout {
 123     struct gfx9_surf_flags      surf;    /* color or depth surface */
 124     struct gfx9_surf_flags      fmask;   /* not added to surf_size */
 125     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 126
 127     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
 128     struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 129     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 130
 131     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
 132     uint64_t                    surf_offset; /* 0 unless imported with an offset */
 133     /* The size of the 2D plane containing all mipmap levels. */
 134     uint64_t                    surf_slice_size;
 135     uint16_t                    surf_pitch; /* in blocks */
 136     uint16_t                    surf_height;
 137     /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
 138     uint32_t                    offset[RADEON_SURF_MAX_LEVELS];
 139
 140     uint16_t                    dcc_pitch_max;  /* (mip chain pitch - 1) */
 141
 142     uint64_t                    stencil_offset; /* separate stencil */
 143     uint64_t                    fmask_size;
 144     uint64_t                    cmask_size;
 145
 146     uint32_t                    fmask_alignment;
 147     uint32_t                    cmask_alignment;
 148 };
 149
 150 struct radeon_surf {
 151     /* Format properties. */
 152     unsigned                    blk_w:4;
 153     unsigned                    blk_h:4;
 154     unsigned                    bpe:5;
 155     /* Number of mipmap levels where DCC is enabled starting from level 0.
 156      * Non-zero levels may be disabled due to alignment constraints, but not
 157      * the first level.
 158      */
 159     unsigned                    num_dcc_levels:4;
 160     unsigned                    is_linear:1;
 161     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
 162     unsigned                    micro_tile_mode:3;
 163     uint32_t                    flags;
 164
 165     /* These are return values. Some of them can be set by the caller, but
 166      * they will be treated as hints (e.g. bankw, bankh) and might be
 167      * changed by the calculator.
 168      */
 169     uint64_t                    surf_size;
 170     uint64_t                    dcc_size;
 171     uint64_t                    htile_size;
 172
 173     uint32_t                    htile_slice_size;
 174
 175     uint32_t                    surf_alignment;
 176     uint32_t                    dcc_alignment;
 177     uint32_t                    htile_alignment;
 178
 179     union {
 180         /* R600-VI return values.
 181          *
 182          * Some of them can be set by the caller if certain parameters are
 183          * desirable. The allocator will try to obey them.
 184          */
 185         struct legacy_surf_layout legacy;
 186
 187         /* GFX9+ return values. */
 188         struct gfx9_surf_layout gfx9;
 189     } u;
 190 };
 191
 192 struct ac_surf_info {
 193         uint32_t width;
 194         uint32_t height;
 195         uint32_t depth;
 196         uint8_t samples;
 197         uint8_t levels;
 198         uint16_t array_size;
 199 };
 200
 201 struct ac_surf_config {
 202         struct ac_surf_info info;
 203         unsigned is_3d : 1;
 204         unsigned is_cube : 1;
 205 };
 206
 207 ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
 208                                const struct amdgpu_gpu_info *amdinfo);
 209
 210 int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info,
 211                        const struct ac_surf_config * config,
 212                        enum radeon_surf_mode mode,
 213                        struct radeon_surf *surf);
 214
 215 #ifdef __cplusplus
 216 }
 217 #endif
 218
 219 #endif /* AC_SURFACE_H */