2 * Copyright © 2014 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
28 * This file is included by addrlib. It adds GPU family definitions and
29 * macros compatible with addrlib.
35 #include "util/u_endian.h"
37 #if defined(PIPE_ARCH_LITTLE_ENDIAN)
38 #define LITTLEENDIAN_CPU
39 #elif defined(PIPE_ARCH_BIG_ENDIAN)
56 /* SI specific rev IDs */
59 SI_TAHITI_P_A0
= SI_TAHITI_P_A11
, /*A0 is alias of A11*/
61 SI_TAHITI_P_B0
= SI_TAHITI_P_A21
, /*B0 is alias of A21*/
63 SI_TAHITI_P_B1
= SI_TAHITI_P_A22
, /*B1 is alias of A22*/
65 SI_PITCAIRN_PM_A11
= 20,
66 SI_PITCAIRN_PM_A0
= SI_PITCAIRN_PM_A11
, /*A0 is alias of A11*/
67 SI_PITCAIRN_PM_A12
= 21,
68 SI_PITCAIRN_PM_A1
= SI_PITCAIRN_PM_A12
, /*A1 is alias of A12*/
70 SI_CAPEVERDE_M_A11
= 40,
71 SI_CAPEVERDE_M_A0
= SI_CAPEVERDE_M_A11
, /*A0 is alias of A11*/
72 SI_CAPEVERDE_M_A12
= 41,
73 SI_CAPEVERDE_M_A1
= SI_CAPEVERDE_M_A12
, /*A1 is alias of A12*/
83 #define ASICREV_IS_TAHITI_P(eChipRev) \
84 (eChipRev < SI_PITCAIRN_PM_A11)
85 #define ASICREV_IS_PITCAIRN_PM(eChipRev) \
86 ((eChipRev >= SI_PITCAIRN_PM_A11) && (eChipRev < SI_CAPEVERDE_M_A11))
87 #define ASICREV_IS_CAPEVERDE_M(eChipRev) \
88 ((eChipRev >= SI_CAPEVERDE_M_A11) && (eChipRev < SI_OLAND_M_A0))
89 #define ASICREV_IS_OLAND_M(eChipRev) \
90 ((eChipRev >= SI_OLAND_M_A0) && (eChipRev < SI_HAINAN_V_A0))
91 #define ASICREV_IS_HAINAN_V(eChipRev) \
92 (eChipRev >= SI_HAINAN_V_A0)
94 /* CI specific revIDs */
104 #define ASICREV_IS_BONAIRE_M(eChipRev) \
105 ((eChipRev >= CI_BONAIRE_M_A0) && (eChipRev < CI_HAWAII_P_A0))
106 #define ASICREV_IS_HAWAII_P(eChipRev) \
107 (eChipRev >= CI_HAWAII_P_A0)
109 /* KV specific rev IDs */
111 KV_SPECTRE_A0
= 0x01, /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
112 KV_SPOOKY_A0
= 0x41, /* KV2 with Spooky GFX core, including downgraded from Spectre core, 3-4-1-1 (CU-Pix-Primitive-RB) */
113 KB_KALINDI_A0
= 0x81, /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
114 KB_KALINDI_A1
= 0x82, /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
115 BV_KALINDI_A2
= 0x85, /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
116 ML_GODAVARI_A0
= 0xa1, /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
117 ML_GODAVARI_A1
= 0xa2, /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
121 #define ASICREV_IS_SPECTRE(eChipRev) \
122 ((eChipRev >= KV_SPECTRE_A0) && (eChipRev < KV_SPOOKY_A0)) /* identify all versions of SPRECTRE and supported features set */
123 #define ASICREV_IS_SPOOKY(eChipRev) \
124 ((eChipRev >= KV_SPOOKY_A0) && (eChipRev < KB_KALINDI_A0)) /* identify all versions of SPOOKY and supported features set */
125 #define ASICREV_IS_KALINDI(eChipRev) \
126 ((eChipRev >= KB_KALINDI_A0) && (eChipRev < KV_UNKNOWN)) /* identify all versions of KALINDI and supported features set */
128 /* Following macros are subset of ASICREV_IS_KALINDI macro */
129 #define ASICREV_IS_KALINDI_BHAVANI(eChipRev) \
130 ((eChipRev >= BV_KALINDI_A2) && (eChipRev < ML_GODAVARI_A0)) /* identify all versions of BHAVANI and supported features set */
131 #define ASICREV_IS_KALINDI_GODAVARI(eChipRev) \
132 ((eChipRev >= ML_GODAVARI_A0) && (eChipRev < KV_UNKNOWN)) /* identify all versions of GODAVARI and supported features set */
134 /* VI specific rev IDs */
143 VI_POLARIS10_P_A0
= 80,
145 VI_POLARIS11_M_A0
= 90,
147 VI_POLARIS12_V_A0
= 100,
153 #define ASICREV_IS_ICELAND_M(eChipRev) \
154 (eChipRev < VI_TONGA_P_A0)
155 #define ASICREV_IS_TONGA_P(eChipRev) \
156 ((eChipRev >= VI_TONGA_P_A0) && (eChipRev < VI_FIJI_P_A0))
157 #define ASICREV_IS_FIJI_P(eChipRev) \
158 ((eChipRev >= VI_FIJI_P_A0) && (eChipRev < VI_POLARIS10_P_A0))
159 #define ASICREV_IS_POLARIS10_P(eChipRev)\
160 ((eChipRev >= VI_POLARIS10_P_A0) && (eChipRev < VI_POLARIS11_M_A0))
161 #define ASICREV_IS_POLARIS11_M(eChipRev) \
162 (eChipRev >= VI_POLARIS11_M_A0 && eChipRev < VI_POLARIS12_V_A0)
163 #define ASICREV_IS_POLARIS12_V(eChipRev)\
164 (eChipRev >= VI_POLARIS12_V_A0)
166 /* CZ specific rev IDs */
173 #define ASICREV_IS_CARRIZO(eChipRev) \
174 ((eChipRev >= CARRIZO_A0) && (eChipRev < STONEY_A0))
176 #define ASICREV_IS_STONEY(eChipRev) \
177 ((eChipRev >= STONEY_A0) && (eChipRev < CZ_UNKNOWN))
179 /* AI specific rev IDs */
181 AI_VEGA10_P_A0
= 0x01,
186 #define ASICREV_IS_VEGA10_P(eChipRev) \
187 ((eChipRev) >= AI_VEGA10_P_A0 && (eChipRev) < AI_UNKNOWN)
189 /* RV specific rev IDs */
195 #define ASICREV_IS_RAVEN(eChipRev) \
196 ((eChipRev) >= RAVEN_A0 && (eChipRev) < RAVEN_UNKNOWN)
198 #endif /* AMDGPU_ID_H */