d77d2ff57509a39633e5f9d513eda3bdc73cdbd3
2 * Southern Islands Register documentation
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "amdgfxregs.h"
30 #define SI_CONFIG_REG_OFFSET 0x00008000
31 #define SI_CONFIG_REG_END 0x0000B000
32 #define SI_SH_REG_OFFSET 0x0000B000
33 #define SI_SH_REG_END 0x0000C000
34 #define SI_CONTEXT_REG_OFFSET 0x00028000
35 #define SI_CONTEXT_REG_END 0x00030000
36 #define CIK_UCONFIG_REG_OFFSET 0x00030000
37 #define CIK_UCONFIG_REG_END 0x00040000
40 #define EVENT_TYPE_CACHE_FLUSH 0x6
41 #define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10
42 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
43 #define EVENT_TYPE_ZPASS_DONE 0x15
44 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
45 #define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f
46 #define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20
47 #define EVENT_TYPE(x) ((x) << 0)
48 #define EVENT_INDEX(x) ((x) << 8)
49 /* 0 - any non-TS event
51 * 2 - SAMPLE_PIPELINESTAT
52 * 3 - SAMPLE_STREAMOUTSTAT*
53 * 4 - *S_PARTIAL_FLUSH
57 /* EVENT_WRITE_EOP (SI-VI) & RELEASE_MEM (GFX9) */
58 #define EVENT_TCL1_VOL_ACTION_ENA (1 << 12)
59 #define EVENT_TC_VOL_ACTION_ENA (1 << 13)
60 #define EVENT_TC_WB_ACTION_ENA (1 << 15)
61 #define EVENT_TCL1_ACTION_ENA (1 << 16)
62 #define EVENT_TC_ACTION_ENA (1 << 17)
63 #define EVENT_TC_NC_ACTION_ENA (1 << 19) /* GFX9+ */
64 #define EVENT_TC_WC_ACTION_ENA (1 << 20) /* GFX9+ */
65 #define EVENT_TC_MD_ACTION_ENA (1 << 21) /* GFX9+ */
68 #define PREDICATION_OP_CLEAR 0x0
69 #define PREDICATION_OP_ZPASS 0x1
70 #define PREDICATION_OP_PRIMCOUNT 0x2
71 #define PREDICATION_OP_BOOL64 0x3
73 #define PRED_OP(x) ((x) << 16)
75 #define PREDICATION_CONTINUE (1 << 31)
77 #define PREDICATION_HINT_WAIT (0 << 12)
78 #define PREDICATION_HINT_NOWAIT_DRAW (1 << 12)
80 #define PREDICATION_DRAW_NOT_VISIBLE (0 << 8)
81 #define PREDICATION_DRAW_VISIBLE (1 << 8)
83 #define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7
85 /* All registers defined in this packet section don't exist and the only
86 * purpose of these definitions is to define packet encoding that
87 * the IB parser understands, and also to have an accurate documentation.
90 #define PKT3_SET_BASE 0x11
91 #define PKT3_CLEAR_STATE 0x12
92 #define PKT3_INDEX_BUFFER_SIZE 0x13
93 #define PKT3_DISPATCH_DIRECT 0x15
94 #define PKT3_DISPATCH_INDIRECT 0x16
95 #define PKT3_OCCLUSION_QUERY 0x1F /* new for CIK */
96 #define PKT3_SET_PREDICATION 0x20
97 #define PKT3_COND_EXEC 0x22
98 #define PKT3_PRED_EXEC 0x23
99 #define PKT3_DRAW_INDIRECT 0x24
100 #define PKT3_DRAW_INDEX_INDIRECT 0x25
101 #define PKT3_INDEX_BASE 0x26
102 #define PKT3_DRAW_INDEX_2 0x27
103 #define PKT3_CONTEXT_CONTROL 0x28
104 #define CC0_LOAD_GLOBAL_CONFIG(x) (((unsigned)(x) & 0x1) << 0)
105 #define CC0_LOAD_PER_CONTEXT_STATE(x) (((unsigned)(x) & 0x1) << 1)
106 #define CC0_LOAD_GLOBAL_UCONFIG(x) (((unsigned)(x) & 0x1) << 15)
107 #define CC0_LOAD_GFX_SH_REGS(x) (((unsigned)(x) & 0x1) << 16)
108 #define CC0_LOAD_CS_SH_REGS(x) (((unsigned)(x) & 0x1) << 24)
109 #define CC0_LOAD_CE_RAM(x) (((unsigned)(x) & 0x1) << 28)
110 #define CC0_UPDATE_LOAD_ENABLES(x) (((unsigned)(x) & 0x1) << 31)
111 #define CC1_SHADOW_GLOBAL_CONFIG(x) (((unsigned)(x) & 0x1) << 0)
112 #define CC1_SHADOW_PER_CONTEXT_STATE(x) (((unsigned)(x) & 0x1) << 1)
113 #define CC1_SHADOW_GLOBAL_UCONFIG(x) (((unsigned)(x) & 0x1) << 15)
114 #define CC1_SHADOW_GFX_SH_REGS(x) (((unsigned)(x) & 0x1) << 16)
115 #define CC1_SHADOW_CS_SH_REGS(x) (((unsigned)(x) & 0x1) << 24)
116 #define CC1_UPDATE_SHADOW_ENABLES(x) (((unsigned)(x) & 0x1) << 31)
117 #define PKT3_INDEX_TYPE 0x2A /* not on GFX9 */
118 #define PKT3_DRAW_INDIRECT_MULTI 0x2C
119 #define R_2C3_DRAW_INDEX_LOC 0x2C3
120 #define S_2C3_COUNT_INDIRECT_ENABLE(x) (((unsigned)(x) & 0x1) << 30)
121 #define S_2C3_DRAW_INDEX_ENABLE(x) (((unsigned)(x) & 0x1) << 31)
122 #define PKT3_DRAW_INDEX_AUTO 0x2D
123 #define PKT3_DRAW_INDEX_IMMD 0x2E /* not on CIK */
124 #define PKT3_NUM_INSTANCES 0x2F
125 #define PKT3_DRAW_INDEX_MULTI_AUTO 0x30
126 #define PKT3_INDIRECT_BUFFER_SI 0x32 /* not on CIK */
127 #define PKT3_INDIRECT_BUFFER_CONST 0x33
128 #define PKT3_STRMOUT_BUFFER_UPDATE 0x34
129 #define STRMOUT_STORE_BUFFER_FILLED_SIZE 1
130 #define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x) & 0x3) << 1)
131 #define STRMOUT_OFFSET_FROM_PACKET 0
132 #define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1
133 #define STRMOUT_OFFSET_FROM_MEM 2
134 #define STRMOUT_OFFSET_NONE 3
135 #define STRMOUT_DATA_TYPE(x) (((unsigned)(x) & 0x1) << 7)
136 #define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x) & 0x3) << 8)
137 #define PKT3_DRAW_INDEX_OFFSET_2 0x35
138 #define PKT3_WRITE_DATA 0x37
139 #define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38
140 #define PKT3_MEM_SEMAPHORE 0x39
141 #define PKT3_MPEG_INDEX 0x3A /* not on CIK */
142 #define PKT3_WAIT_REG_MEM 0x3C
143 #define WAIT_REG_MEM_EQUAL 3
144 #define WAIT_REG_MEM_NOT_EQUAL 4
145 #define WAIT_REG_MEM_GREATER_OR_EQUAL 5
146 #define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x) & 0x3) << 4)
147 #define WAIT_REG_MEM_PFP (1 << 8)
148 #define PKT3_MEM_WRITE 0x3D /* not on CIK */
149 #define PKT3_INDIRECT_BUFFER_CIK 0x3F /* new on CIK */
151 #define PKT3_COPY_DATA 0x40
152 #define COPY_DATA_SRC_SEL(x) ((x) & 0xf)
153 #define COPY_DATA_REG 0
154 #define COPY_DATA_SRC_MEM 1 /* only valid as source */
155 #define COPY_DATA_TC_L2 2
156 #define COPY_DATA_GDS 3
157 #define COPY_DATA_PERF 4
158 #define COPY_DATA_IMM 5
159 #define COPY_DATA_TIMESTAMP 9
160 #define COPY_DATA_DST_SEL(x) (((unsigned)(x) & 0xf) << 8)
161 #define COPY_DATA_DST_MEM_GRBM 1 /* sync across GRBM, deprecated */
162 #define COPY_DATA_TC_L2 2
163 #define COPY_DATA_GDS 3
164 #define COPY_DATA_PERF 4
165 #define COPY_DATA_DST_MEM 5
166 #define COPY_DATA_COUNT_SEL (1 << 16)
167 #define COPY_DATA_WR_CONFIRM (1 << 20)
168 #define COPY_DATA_ENGINE_PFP (1 << 30)
169 #define PKT3_PFP_SYNC_ME 0x42
170 #define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK, use ACQUIRE_MEM */
171 #define PKT3_ME_INITIALIZE 0x44 /* not on CIK */
172 #define PKT3_COND_WRITE 0x45
173 #define PKT3_EVENT_WRITE 0x46
174 #define PKT3_EVENT_WRITE_EOP 0x47 /* not on GFX9 */
175 #define EOP_DST_SEL(x) ((x) << 16)
176 #define EOP_DST_SEL_MEM 0
177 #define EOP_DST_SEL_TC_L2 1
178 #define EOP_INT_SEL(x) ((x) << 24)
179 #define EOP_INT_SEL_NONE 0
180 #define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3
181 #define EOP_DATA_SEL(x) ((x) << 29)
182 #define EOP_DATA_SEL_DISCARD 0
183 #define EOP_DATA_SEL_VALUE_32BIT 1
184 #define EOP_DATA_SEL_VALUE_64BIT 2
185 #define EOP_DATA_SEL_TIMESTAMP 3
186 #define EOP_DATA_SEL_GDS 5
187 #define EOP_DATA_GDS(dw_offset, num_dwords) ((dw_offset) | ((unsigned)(num_dwords) << 16))
188 /* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets
189 * are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and
190 * DST_SEL=MC. Only CIK chips are affected.
192 /* fix CP DMA before uncommenting: */
193 /*#define PKT3_EVENT_WRITE_EOS 0x48*/ /* not on GFX9 */
194 #define PKT3_RELEASE_MEM 0x49 /* GFX9+ [any ring] or GFX8 [compute ring only] */
195 #define PKT3_CONTEXT_REG_RMW 0x51 /* older firmware versions on older chips don't have this */
196 #define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */
197 #define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */
198 #define PKT3_REWIND 0x59 /* VI+ [any ring] or CIK [compute ring only] */
199 #define PKT3_LOAD_UCONFIG_REG 0x5E /* GFX7+ */
200 #define PKT3_LOAD_SH_REG 0x5F
201 #define PKT3_LOAD_CONTEXT_REG 0x61
202 #define PKT3_SET_CONFIG_REG 0x68
203 #define PKT3_SET_CONTEXT_REG 0x69
204 #define PKT3_SET_SH_REG 0x76
205 #define PKT3_SET_SH_REG_OFFSET 0x77
206 #define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */
207 #define PKT3_SET_UCONFIG_REG_INDEX 0x7A /* new for GFX9, CP ucode version >= 26 */
208 #define PKT3_LOAD_CONST_RAM 0x80
209 #define PKT3_WRITE_CONST_RAM 0x81
210 #define PKT3_DUMP_CONST_RAM 0x83
211 #define PKT3_INCREMENT_CE_COUNTER 0x84
212 #define PKT3_INCREMENT_DE_COUNTER 0x85
213 #define PKT3_WAIT_ON_CE_COUNTER 0x86
214 #define PKT3_SET_SH_REG_INDEX 0x9B
215 #define PKT3_LOAD_CONTEXT_REG_INDEX 0x9F /* new for VI */
217 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
218 #define PKT_TYPE_G(x) (((x) >> 30) & 0x3)
219 #define PKT_TYPE_C 0x3FFFFFFF
220 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
221 #define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF)
222 #define PKT_COUNT_C 0xC000FFFF
223 #define PKT0_BASE_INDEX_S(x) (((unsigned)(x) & 0xFFFF) << 0)
224 #define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF)
225 #define PKT0_BASE_INDEX_C 0xFFFF0000
226 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
227 #define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF)
228 #define PKT3_IT_OPCODE_C 0xFFFF00FF
229 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
230 #define PKT3_SHADER_TYPE_S(x) (((unsigned)(x) & 0x1) << 1)
231 #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
232 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
234 #define PKT3_CP_DMA 0x41
236 * 2. SRC_ADDR_LO [31:0] or DATA [31:0]
237 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | SRC_ADDR_HI [15:0]
238 * 4. DST_ADDR_LO [31:0]
239 * 5. DST_ADDR_HI [15:0]
240 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
243 #define PKT3_DMA_DATA 0x50 /* new for CIK */
245 * 2. CP_SYNC [31] | SRC_SEL [30:29] | DST_SEL [21:20] | ENGINE [0]
246 * 2. SRC_ADDR_LO [31:0] or DATA [31:0]
247 * 3. SRC_ADDR_HI [31:0]
248 * 4. DST_ADDR_LO [31:0]
249 * 5. DST_ADDR_HI [31:0]
250 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
253 /* SI async DMA packets */
254 #define SI_DMA_PACKET(cmd, sub_cmd, n) ((((unsigned)(cmd) & 0xF) << 28) | \
255 (((unsigned)(sub_cmd) & 0xFF) << 20) |\
256 (((unsigned)(n) & 0xFFFFF) << 0))
257 /* SI async DMA Packet types */
258 #define SI_DMA_PACKET_WRITE 0x2
259 #define SI_DMA_PACKET_COPY 0x3
260 #define SI_DMA_COPY_MAX_BYTE_ALIGNED_SIZE 0xfffe0
261 /* The documentation says 0xffff8 is the maximum size in dwords, which is
262 * 0x3fffe0 in bytes. */
263 #define SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE 0x3fffe0
264 #define SI_DMA_COPY_DWORD_ALIGNED 0x00
265 #define SI_DMA_COPY_BYTE_ALIGNED 0x40
266 #define SI_DMA_COPY_TILED 0x8
267 #define SI_DMA_PACKET_INDIRECT_BUFFER 0x4
268 #define SI_DMA_PACKET_SEMAPHORE 0x5
269 #define SI_DMA_PACKET_FENCE 0x6
270 #define SI_DMA_PACKET_TRAP 0x7
271 #define SI_DMA_PACKET_SRBM_WRITE 0x9
272 #define SI_DMA_PACKET_CONSTANT_FILL 0xd
273 #define SI_DMA_PACKET_NOP 0xf
275 /* CIK async DMA packets */
276 #define CIK_SDMA_PACKET(op, sub_op, n) ((((unsigned)(n) & 0xFFFF) << 16) | \
277 (((unsigned)(sub_op) & 0xFF) << 8) | \
278 (((unsigned)(op) & 0xFF) << 0))
279 /* CIK async DMA packet types */
280 #define CIK_SDMA_OPCODE_NOP 0x0
281 #define CIK_SDMA_OPCODE_COPY 0x1
282 #define CIK_SDMA_COPY_SUB_OPCODE_LINEAR 0x0
283 #define CIK_SDMA_COPY_SUB_OPCODE_TILED 0x1
284 #define CIK_SDMA_COPY_SUB_OPCODE_SOA 0x3
285 #define CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 0x4
286 #define CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 0x5
287 #define CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 0x6
288 #define CIK_SDMA_OPCODE_WRITE 0x2
289 #define SDMA_WRITE_SUB_OPCODE_LINEAR 0x0
290 #define SDMA_WRTIE_SUB_OPCODE_TILED 0x1
291 #define CIK_SDMA_OPCODE_INDIRECT_BUFFER 0x4
292 #define CIK_SDMA_PACKET_FENCE 0x5
293 #define CIK_SDMA_PACKET_TRAP 0x6
294 #define CIK_SDMA_PACKET_SEMAPHORE 0x7
295 #define CIK_SDMA_PACKET_CONSTANT_FILL 0xb
296 #define CIK_SDMA_OPCODE_TIMESTAMP 0xd
297 #define SDMA_TS_SUB_OPCODE_SET_LOCAL_TIMESTAMP 0x0
298 #define SDMA_TS_SUB_OPCODE_GET_LOCAL_TIMESTAMP 0x1
299 #define SDMA_TS_SUB_OPCODE_GET_GLOBAL_TIMESTAMP 0x2
300 #define CIK_SDMA_PACKET_SRBM_WRITE 0xe
301 /* There is apparently an undocumented HW limitation that
302 prevents the HW from copying the last 255 bytes of (1 << 22) - 1 */
303 #define CIK_SDMA_COPY_MAX_SIZE 0x3fff00 /* almost 4 MB*/
304 #define GFX103_SDMA_COPY_MAX_SIZE 0x3fffff00 /* almost 1 GB */
306 enum amd_cmp_class_flags
{
307 S_NAN
= 1 << 0, // Signaling NaN
308 Q_NAN
= 1 << 1, // Quiet NaN
309 N_INFINITY
= 1 << 2, // Negative infinity
310 N_NORMAL
= 1 << 3, // Negative normal
311 N_SUBNORMAL
= 1 << 4, // Negative subnormal
312 N_ZERO
= 1 << 5, // Negative zero
313 P_ZERO
= 1 << 6, // Positive zero
314 P_SUBNORMAL
= 1 << 7, // Positive subnormal
315 P_NORMAL
= 1 << 8, // Positive normal
316 P_INFINITY
= 1 << 9 // Positive infinity
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