1 # Unofficial GCN/RDNA ISA reference errata
5 The Vega ISA reference writes it's behaviour as:
7 D.u = abs(S0.i - S1.i) + S2.u.
9 This is incorrect. The actual behaviour is what is written in the GCN3 reference
12 ABS_DIFF (A,B) = (A>B) ? (A-B) : (B-A)
13 D.u = ABS_DIFF (S0.u,S1.u) + S2.u
15 The instruction doesn't subtract the S0 and S1 and use the absolute value (the
16 _signed_ distance), it uses the _unsigned_ distance between the operands. So
17 `v_sad_u32(-5, 0, 0)` would return `4294967291` (`-5` interpreted as unsigned),
22 Both the Vega and GCN3 ISA references write that these instructions don't write
27 The Vega ISA reference writes it's behaviour as:
31 D.u += (S0.u[i] == 1 ? 1 : 0);
34 This is incorrect. The actual behaviour (and number of operands) is what
35 is written in the GCN3 reference guide:
37 D.u = CountOneBits(S0.u) + S1.u.
42 The Vega ISA references doesn't say this (or doesn't make it clear), but
43 the offset for SMEM stores must be in m0 if IMM == 0.
45 The RDNA ISA doesn't mention SMEM stores at all, but they seem to be supported
46 by the chip and are present in LLVM. AMD devs however highly recommend avoiding
51 RDNA ISA: same as the SMEM stores, the ISA pretends they don't exist, but they
56 All reference guides say (under "Vector Memory Instruction Data Dependencies"):
57 > When a VM instruction is issued, the address is immediately read out of VGPRs
58 > and sent to the texture cache. Any texture or buffer resources and samplers
59 > are also sent immediately. However, write-data is not immediately sent to the
61 Reading that, one might think that waitcnts need to be added when writing to
62 the registers used for a VMEM store's data. Experimentation has shown that this
63 does not seem to be the case on GFX8 and GFX9 (GFX6 and GFX7 are untested). It
64 also seems unlikely, since NOPs are apparently needed in a subset of these
67 ## MIMG opcodes on GFX8/GCN3
69 The `image_atomic_{swap,cmpswap,add,sub}` opcodes in the GCN3 ISA reference
70 guide are incorrect. The Vega ISA reference guide has the correct ones.
74 VEGA ISA doc says the encoding should be `110010` but `110101` works.
76 ## VOP1 instructions encoded as VOP3
78 RDNA ISA doc says that `0x140` should be added to the opcode, but that doesn't
79 work. What works is adding `0x180`, which LLVM also does.
81 ## FLAT, Scratch, Global instructions
83 The NV bit was removed in RDNA, but some parts of the doc still mention it.
85 RDNA ISA doc 13.8.1 says that SADDR should be set to 0x7f when ADDR is used, but
86 9.3.1 says it should be set to NULL. We assume 9.3.1 is correct and set it to
89 ## Legacy instructions
91 Some instructions have a `_LEGACY` variant which implements "DX9 rules", in which
92 the zero "wins" in multiplications, ie. `0.0*x` is always `0.0`. The VEGA ISA
93 mentions `V_MAC_LEGACY_F32` but this instruction is not really there on VEGA.
95 ## RDNA L0, L1 cache and DLC, GLC bits
97 The old L1 cache was renamed to L0, and a new L1 cache was added to RDNA. The
98 L1 cache is 1 cache per shader array. Some instruction encodings have DLC and
99 GLC bits that interact with the cache.
101 * DLC ("device level coherent") bit: controls the L1 cache
102 * GLC ("globally coherent") bit: controls the L0 cache
104 The recommendation from AMD devs is to always set these two bits at the same time,
105 as it doesn't make too much sense to set them independently, aside from some
106 circumstances (eg. we needn't set DLC when only one shader array is used).
108 Stores and atomics always bypass the L1 cache, so they don't support the DLC bit,
109 and it shouldn't be set in these cases. Setting the DLC for these cases can result
110 in graphical glitches.
114 The S_DCACHE_WB is not mentioned in the RDNA ISA doc, but it is needed in order
115 to achieve correct behavior in some SSBO CTS tests.
117 ## RDNA subvector mode
119 The documentation of S_SUBVECTOR_LOOP_BEGIN and S_SUBVECTOR_LOOP_END is not clear
120 on what sort of addressing should be used, but it says that it
121 "is equivalent to an S_CBRANCH with extra math", so the subvector loop handling
122 in ACO is done according to the S_CBRANCH doc.
126 ## SMEM corrupts VCCZ on SI/CI
128 https://github.com/llvm/llvm-project/blob/acb089e12ae48b82c0b05c42326196a030df9b82/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp#L580-L616
129 After issuing a SMEM instructions, we need to wait for the SMEM instructions to
130 finish and then write to vcc (for example, `s_mov_b64 vcc, vcc`) to correct vccz
132 Currently, we don't do this.