src/amd/compiler/README

   1 # Unofficial GCN/RDNA ISA reference errata
   2
   3 ## v_sad_u32
   4
   5 The Vega ISA reference writes it's behaviour as:
   6 ```
   7 D.u = abs(S0.i - S1.i) + S2.u.
   8 ```
   9 This is incorrect. The actual behaviour is what is written in the GCN3 reference
  10 guide:
  11 ```
  12 ABS_DIFF (A,B) = (A>B) ? (A-B) : (B-A)
  13 D.u = ABS_DIFF (S0.u,S1.u) + S2.u
  14 ```
  15 The instruction doesn't subtract the S0 and S1 and use the absolute value (the
  16 _signed_ distance), it uses the _unsigned_ distance between the operands. So
  17 `v_sad_u32(-5, 0, 0)` would return `4294967291` (`-5` interpreted as unsigned),
  18 not `5`.
  19
  20 ## s_bfe_*
  21
  22 Both the Vega and GCN3 ISA references write that these instructions don't write
  23 SCC. They do.
  24
  25 ## v_bcnt_u32_b32
  26
  27 The Vega ISA reference writes it's behaviour as:
  28 ```
  29 D.u = 0;
  30 for i in 0 ... 31 do
  31 D.u += (S0.u[i] == 1 ? 1 : 0);
  32 endfor.
  33 ```
  34 This is incorrect. The actual behaviour (and number of operands) is what
  35 is written in the GCN3 reference guide:
  36 ```
  37 D.u = CountOneBits(S0.u) + S1.u.
  38 ```
  39
  40 ## SMEM stores
  41
  42 The Vega ISA references doesn't say this (or doesn't make it clear), but
  43 the offset for SMEM stores must be in m0 if IMM == 0.
  44
  45 The RDNA ISA doesn't mention SMEM stores at all, but they seem to be supported
  46 by the chip and are present in LLVM. AMD devs however highly recommend avoiding
  47 these instructions.
  48
  49 ## SMEM atomics
  50
  51 RDNA ISA: same as the SMEM stores, the ISA pretends they don't exist, but they
  52 are there in LLVM.
  53
  54 ## VMEM stores
  55
  56 All reference guides say (under "Vector Memory Instruction Data Dependencies"):
  57 > When a VM instruction is issued, the address is immediately read out of VGPRs
  58 > and sent to the texture cache. Any texture or buffer resources and samplers
  59 > are also sent immediately. However, write-data is not immediately sent to the
  60 > texture cache.
  61 Reading that, one might think that waitcnts need to be added when writing to
  62 the registers used for a VMEM store's data. Experimentation has shown that this
  63 does not seem to be the case on GFX8 and GFX9 (GFX6 and GFX7 are untested). It
  64 also seems unlikely, since NOPs are apparently needed in a subset of these
  65 situations.
  66
  67 ## MIMG opcodes on GFX8/GCN3
  68
  69 The `image_atomic_{swap,cmpswap,add,sub}` opcodes in the GCN3 ISA reference
  70 guide are incorrect. The Vega ISA reference guide has the correct ones.
  71
  72 ## Legacy instructions
  73
  74 Some instructions have a `_LEGACY` variant which implements "DX9 rules", in which
  75 the zero "wins" in multiplications, ie. `0.0*x` is always `0.0`. The VEGA ISA
  76 mentions `V_MAC_LEGACY_F32` but this instruction is not really there on VEGA.
  77
  78 # Hardware Bugs
  79
  80 ## SMEM corrupts VCCZ on SI/CI
  81
  82 https://github.com/llvm/llvm-project/blob/acb089e12ae48b82c0b05c42326196a030df9b82/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp#L580-L616
  83 After issuing a SMEM instructions, we need to wait for the SMEM instructions to
  84 finish and then write to vcc (for example, `s_mov_b64 vcc, vcc`) to correct vccz
  85
  86 Currently, we don't do this.
  87