src/amd/compiler/aco_builder_h.py

   1
   2 template = """\
   3 /*
   4  * Copyright (c) 2019 Valve Corporation
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  *
  25  * This file was generated by aco_builder_h.py
  26  */
  27
  28 #ifndef _ACO_BUILDER_
  29 #define _ACO_BUILDER_
  30
  31 #include "aco_ir.h"
  32 #include "util/u_math.h"
  33 #include "util/bitscan.h"
  34
  35 namespace aco {
  36 enum dpp_ctrl {
  37     _dpp_quad_perm = 0x000,
  38     _dpp_row_sl = 0x100,
  39     _dpp_row_sr = 0x110,
  40     _dpp_row_rr = 0x120,
  41     dpp_wf_sl1 = 0x130,
  42     dpp_wf_rl1 = 0x134,
  43     dpp_wf_sr1 = 0x138,
  44     dpp_wf_rr1 = 0x13C,
  45     dpp_row_mirror = 0x140,
  46     dpp_row_half_mirror = 0x141,
  47     dpp_row_bcast15 = 0x142,
  48     dpp_row_bcast31 = 0x143
  49 };
  50
  51 inline dpp_ctrl
  52 dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3)
  53 {
  54     assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4);
  55     return (dpp_ctrl)(lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6));
  56 }
  57
  58 inline dpp_ctrl
  59 dpp_row_sl(unsigned amount)
  60 {
  61     assert(amount > 0 && amount < 16);
  62     return (dpp_ctrl)(((unsigned) _dpp_row_sl) | amount);
  63 }
  64
  65 inline dpp_ctrl
  66 dpp_row_sr(unsigned amount)
  67 {
  68     assert(amount > 0 && amount < 16);
  69     return (dpp_ctrl)(((unsigned) _dpp_row_sr) | amount);
  70 }
  71
  72 inline unsigned
  73 ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask)
  74 {
  75     assert(and_mask < 32 && or_mask < 32 && xor_mask < 32);
  76     return and_mask | (or_mask << 5) | (xor_mask << 10);
  77 }
  78
  79 aco_ptr<Instruction> create_s_mov(Definition dst, Operand src);
  80
  81 class Builder {
  82 public:
  83    struct Result {
  84       Instruction *instr;
  85
  86       Result(Instruction *instr) : instr(instr) {}
  87
  88       operator Instruction *() const {
  89          return instr;
  90       }
  91
  92       operator Temp() const {
  93          return instr->definitions[0].getTemp();
  94       }
  95
  96       operator Operand() const {
  97          return Operand((Temp)*this);
  98       }
  99
 100       Definition& def(unsigned index) const {
 101          return instr->definitions[index];
 102       }
 103
 104       aco_ptr<Instruction> get_ptr() const {
 105         return aco_ptr<Instruction>(instr);
 106       }
 107    };
 108
 109    struct Op {
 110       Operand op;
 111       Op(Temp tmp) : op(tmp) {}
 112       Op(Operand op_) : op(op_) {}
 113       Op(Result res) : op((Temp)res) {}
 114    };
 115
 116    enum WaveSpecificOpcode {
 117       s_cselect = (unsigned) aco_opcode::s_cselect_b64,
 118       s_cmp_lg = (unsigned) aco_opcode::s_cmp_lg_u64,
 119       s_and = (unsigned) aco_opcode::s_and_b64,
 120       s_andn2 = (unsigned) aco_opcode::s_andn2_b64,
 121       s_or = (unsigned) aco_opcode::s_or_b64,
 122       s_orn2 = (unsigned) aco_opcode::s_orn2_b64,
 123       s_not = (unsigned) aco_opcode::s_not_b64,
 124       s_mov = (unsigned) aco_opcode::s_mov_b64,
 125       s_wqm = (unsigned) aco_opcode::s_wqm_b64,
 126       s_and_saveexec = (unsigned) aco_opcode::s_and_saveexec_b64,
 127       s_or_saveexec = (unsigned) aco_opcode::s_or_saveexec_b64,
 128       s_xnor = (unsigned) aco_opcode::s_xnor_b64,
 129       s_xor = (unsigned) aco_opcode::s_xor_b64,
 130       s_bcnt1_i32 = (unsigned) aco_opcode::s_bcnt1_i32_b64,
 131       s_bitcmp1 = (unsigned) aco_opcode::s_bitcmp1_b64,
 132       s_ff1_i32 = (unsigned) aco_opcode::s_ff1_i32_b64,
 133    };
 134
 135    Program *program;
 136    bool use_iterator;
 137    bool start; // only when use_iterator == false
 138    RegClass lm;
 139
 140    std::vector<aco_ptr<Instruction>> *instructions;
 141    std::vector<aco_ptr<Instruction>>::iterator it;
 142
 143    Builder(Program *pgm) : program(pgm), use_iterator(false), start(false), lm(pgm->lane_mask), instructions(NULL) {}
 144    Builder(Program *pgm, Block *block) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(&block->instructions) {}
 145    Builder(Program *pgm, std::vector<aco_ptr<Instruction>> *instrs) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(instrs) {}
 146
 147    void moveEnd(Block *block) {
 148       instructions = &block->instructions;
 149    }
 150
 151    void reset() {
 152       use_iterator = false;
 153       start = false;
 154       instructions = NULL;
 155    }
 156
 157    void reset(Block *block) {
 158       use_iterator = false;
 159       start = false;
 160       instructions = &block->instructions;
 161    }
 162
 163    void reset(std::vector<aco_ptr<Instruction>> *instrs) {
 164       use_iterator = false;
 165       start = false;
 166       instructions = instrs;
 167    }
 168
 169    void reset(std::vector<aco_ptr<Instruction>> *instrs, std::vector<aco_ptr<Instruction>>::iterator instr_it) {
 170       use_iterator = true;
 171       start = false;
 172       instructions = instrs;
 173       it = instr_it;
 174    }
 175
 176    Result insert(aco_ptr<Instruction> instr) {
 177       Instruction *instr_ptr = instr.get();
 178       if (instructions) {
 179          if (use_iterator) {
 180             it = instructions->emplace(it, std::move(instr));
 181             it = std::next(it);
 182          } else if (!start) {
 183             instructions->emplace_back(std::move(instr));
 184          } else {
 185             instructions->emplace(instructions->begin(), std::move(instr));
 186          }
 187       }
 188       return Result(instr_ptr);
 189    }
 190
 191    Result insert(Instruction* instr) {
 192       if (instructions) {
 193          if (use_iterator) {
 194             it = instructions->emplace(it, aco_ptr<Instruction>(instr));
 195             it = std::next(it);
 196          } else if (!start) {
 197             instructions->emplace_back(aco_ptr<Instruction>(instr));
 198          } else {
 199             instructions->emplace(instructions->begin(), aco_ptr<Instruction>(instr));
 200          }
 201       }
 202       return Result(instr);
 203    }
 204
 205    Temp tmp(RegClass rc) {
 206       return (Temp){program->allocateId(), rc};
 207    }
 208
 209    Temp tmp(RegType type, unsigned size) {
 210       return (Temp){program->allocateId(), RegClass(type, size)};
 211    }
 212
 213    Definition def(RegClass rc) {
 214       return Definition((Temp){program->allocateId(), rc});
 215    }
 216
 217    Definition def(RegType type, unsigned size) {
 218       return Definition((Temp){program->allocateId(), RegClass(type, size)});
 219    }
 220
 221    Definition def(RegClass rc, PhysReg reg) {
 222       return Definition(program->allocateId(), reg, rc);
 223    }
 224
 225    inline aco_opcode w64or32(WaveSpecificOpcode opcode) const {
 226       if (program->wave_size == 64)
 227          return (aco_opcode) opcode;
 228
 229       switch (opcode) {
 230       case s_cselect:
 231          return aco_opcode::s_cselect_b32;
 232       case s_cmp_lg:
 233          return aco_opcode::s_cmp_lg_u32;
 234       case s_and:
 235          return aco_opcode::s_and_b32;
 236       case s_andn2:
 237          return aco_opcode::s_andn2_b32;
 238       case s_or:
 239          return aco_opcode::s_or_b32;
 240       case s_orn2:
 241          return aco_opcode::s_orn2_b32;
 242       case s_not:
 243          return aco_opcode::s_not_b32;
 244       case s_mov:
 245          return aco_opcode::s_mov_b32;
 246       case s_wqm:
 247          return aco_opcode::s_wqm_b32;
 248       case s_and_saveexec:
 249          return aco_opcode::s_and_saveexec_b32;
 250       case s_or_saveexec:
 251          return aco_opcode::s_or_saveexec_b32;
 252       case s_xnor:
 253          return aco_opcode::s_xnor_b32;
 254       case s_xor:
 255          return aco_opcode::s_xor_b32;
 256       case s_bcnt1_i32:
 257          return aco_opcode::s_bcnt1_i32_b32;
 258       case s_bitcmp1:
 259          return aco_opcode::s_bitcmp1_b32;
 260       case s_ff1_i32:
 261          return aco_opcode::s_ff1_i32_b32;
 262       default:
 263          unreachable("Unsupported wave specific opcode.");
 264       }
 265    }
 266
 267 % for fixed in ['m0', 'vcc', 'exec', 'scc']:
 268    Operand ${fixed}(Temp tmp) {
 269        % if fixed == 'vcc' or fixed == 'exec':
 270           assert(tmp.regClass() == lm);
 271        % endif
 272        Operand op(tmp);
 273        op.setFixed(aco::${fixed});
 274        return op;
 275    }
 276
 277    Definition ${fixed}(Definition def) {
 278        % if fixed == 'vcc' or fixed == 'exec':
 279           assert(def.regClass() == lm);
 280        % endif
 281        def.setFixed(aco::${fixed});
 282        return def;
 283    }
 284
 285    Definition hint_${fixed}(Definition def) {
 286        % if fixed == 'vcc' or fixed == 'exec':
 287           assert(def.regClass() == lm);
 288        % endif
 289        def.setHint(aco::${fixed});
 290        return def;
 291    }
 292
 293 % endfor
 294    /* hand-written helpers */
 295    Temp as_uniform(Op op)
 296    {
 297       assert(op.op.isTemp());
 298       if (op.op.getTemp().type() == RegType::vgpr)
 299          return pseudo(aco_opcode::p_as_uniform, def(RegType::sgpr, op.op.size()), op);
 300       else
 301          return op.op.getTemp();
 302    }
 303
 304    Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool bits24=false)
 305    {
 306       assert(tmp.type() == RegType::vgpr);
 307       if (imm == 0) {
 308          return vop1(aco_opcode::v_mov_b32, dst, Operand(0u));
 309       } else if (imm == 1) {
 310          return copy(dst, Operand(tmp));
 311       } else if (util_is_power_of_two_or_zero(imm)) {
 312          return vop2(aco_opcode::v_lshlrev_b32, dst, Operand((uint32_t)ffs(imm) - 1u), tmp);
 313       } else if (bits24) {
 314         return vop2(aco_opcode::v_mul_u32_u24, dst, Operand(imm), tmp);
 315       } else {
 316         Temp imm_tmp = copy(def(v1), Operand(imm));
 317         return vop3(aco_opcode::v_mul_lo_u32, dst, imm_tmp, tmp);
 318       }
 319    }
 320
 321    Result v_mul24_imm(Definition dst, Temp tmp, uint32_t imm)
 322    {
 323       return v_mul_imm(dst, tmp, imm, true);
 324    }
 325
 326    Result copy(Definition dst, Op op_) {
 327       Operand op = op_.op;
 328       if (dst.regClass() == s1 && op.size() == 1 && op.isLiteral()) {
 329          uint32_t imm = op.constantValue();
 330          if (imm == 0x3e22f983) {
 331             if (program->chip_class >= GFX8)
 332                op.setFixed(PhysReg{248}); /* it can be an inline constant on GFX8+ */
 333          } else if (imm >= 0xffff8000 || imm <= 0x7fff) {
 334             return sopk(aco_opcode::s_movk_i32, dst, imm & 0xFFFFu);
 335          } else if (util_bitreverse(imm) <= 64 || util_bitreverse(imm) >= 0xFFFFFFF0) {
 336             uint32_t rev = util_bitreverse(imm);
 337             return dst.regClass() == v1 ?
 338                    vop1(aco_opcode::v_bfrev_b32, dst, Operand(rev)) :
 339                    sop1(aco_opcode::s_brev_b32, dst, Operand(rev));
 340          } else if (imm != 0) {
 341             unsigned start = (ffs(imm) - 1) & 0x1f;
 342             unsigned size = util_bitcount(imm) & 0x1f;
 343             if ((((1u << size) - 1u) << start) == imm)
 344                 return sop2(aco_opcode::s_bfm_b32, dst, Operand(size), Operand(start));
 345          }
 346       }
 347
 348       if (dst.regClass() == s2) {
 349         return sop1(aco_opcode::s_mov_b64, dst, op);
 350       } else if (op.size() > 1) {
 351          return pseudo(aco_opcode::p_create_vector, dst, op);
 352       } else if (dst.regClass() == v1 || dst.regClass() == v1.as_linear()) {
 353         return vop1(aco_opcode::v_mov_b32, dst, op);
 354       } else {
 355         assert(dst.regClass() == s1);
 356         return sop1(aco_opcode::s_mov_b32, dst, op);
 357       }
 358    }
 359
 360    Result vadd32(Definition dst, Op a, Op b, bool carry_out=false, Op carry_in=Op(Operand(s2)), bool post_ra=false) {
 361       if (!b.op.isTemp() || b.op.regClass().type() != RegType::vgpr)
 362          std::swap(a, b);
 363       assert((post_ra || b.op.hasRegClass()) && b.op.regClass().type() == RegType::vgpr);
 364
 365       if (!carry_in.op.isUndefined())
 366          return vop2(aco_opcode::v_addc_co_u32, Definition(dst), hint_vcc(def(lm)), a, b, carry_in);
 367       else if (program->chip_class >= GFX10 && carry_out)
 368          return vop3(aco_opcode::v_add_co_u32_e64, Definition(dst), def(s2), a, b);
 369       else if (program->chip_class < GFX9 || carry_out)
 370          return vop2(aco_opcode::v_add_co_u32, Definition(dst), hint_vcc(def(lm)), a, b);
 371       else
 372          return vop2(aco_opcode::v_add_u32, Definition(dst), a, b);
 373    }
 374
 375    Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2)))
 376    {
 377       if (!borrow.op.isUndefined() || program->chip_class < GFX9)
 378          carry_out = true;
 379
 380       bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr;
 381       if (reverse)
 382          std::swap(a, b);
 383       assert(b.op.isTemp() && b.op.regClass().type() == RegType::vgpr);
 384
 385       aco_opcode op;
 386       Temp carry;
 387       if (carry_out) {
 388          carry = tmp(s2);
 389          if (borrow.op.isUndefined())
 390             op = reverse ? aco_opcode::v_subrev_co_u32 : aco_opcode::v_sub_co_u32;
 391          else
 392             op = reverse ? aco_opcode::v_subbrev_co_u32 : aco_opcode::v_subb_co_u32;
 393       } else {
 394          op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32;
 395       }
 396       bool vop3 = false;
 397       if (program->chip_class >= GFX10 && op == aco_opcode::v_subrev_co_u32) {
 398         vop3 = true;
 399         op = aco_opcode::v_subrev_co_u32_e64;
 400       } else if (program->chip_class >= GFX10 && op == aco_opcode::v_sub_co_u32) {
 401         vop3 = true;
 402         op = aco_opcode::v_sub_co_u32_e64;
 403       }
 404
 405       int num_ops = borrow.op.isUndefined() ? 2 : 3;
 406       int num_defs = carry_out ? 2 : 1;
 407       aco_ptr<Instruction> sub;
 408       if (vop3)
 409         sub.reset(create_instruction<VOP3A_instruction>(op, Format::VOP3B, num_ops, num_defs));
 410       else
 411         sub.reset(create_instruction<VOP2_instruction>(op, Format::VOP2, num_ops, num_defs));
 412       sub->operands[0] = a.op;
 413       sub->operands[1] = b.op;
 414       if (!borrow.op.isUndefined())
 415          sub->operands[2] = borrow.op;
 416       sub->definitions[0] = dst;
 417       if (carry_out) {
 418          sub->definitions[1] = Definition(carry);
 419          sub->definitions[1].setHint(aco::vcc);
 420       }
 421       return insert(std::move(sub));
 422    }
 423
 424    Result readlane(Definition dst, Op vsrc, Op lane)
 425    {
 426       if (program->chip_class >= GFX8)
 427          return vop3(aco_opcode::v_readlane_b32_e64, dst, vsrc, lane);
 428       else
 429          return vop2(aco_opcode::v_readlane_b32, dst, vsrc, lane);
 430    }
 431    Result writelane(Definition dst, Op val, Op lane, Op vsrc) {
 432       if (program->chip_class >= GFX8)
 433          return vop3(aco_opcode::v_writelane_b32_e64, dst, val, lane, vsrc);
 434       else
 435          return vop2(aco_opcode::v_writelane_b32, dst, val, lane, vsrc);
 436    }
 437 <%
 438 import itertools
 439 formats = [("pseudo", [Format.PSEUDO], 'Pseudo_instruction', list(itertools.product(range(5), range(5))) + [(8, 1), (1, 8)]),
 440            ("sop1", [Format.SOP1], 'SOP1_instruction', [(1, 1), (2, 1), (3, 2)]),
 441            ("sop2", [Format.SOP2], 'SOP2_instruction', itertools.product([1, 2], [2, 3])),
 442            ("sopk", [Format.SOPK], 'SOPK_instruction', itertools.product([0, 1, 2], [0, 1])),
 443            ("sopp", [Format.SOPP], 'SOPP_instruction', [(0, 0), (0, 1)]),
 444            ("sopc", [Format.SOPC], 'SOPC_instruction', [(1, 2)]),
 445            ("smem", [Format.SMEM], 'SMEM_instruction', [(0, 4), (0, 3), (1, 0), (1, 3), (1, 2), (0, 0)]),
 446            ("ds", [Format.DS], 'DS_instruction', [(1, 1), (1, 2), (0, 3), (0, 4)]),
 447            ("mubuf", [Format.MUBUF], 'MUBUF_instruction', [(0, 4), (1, 3)]),
 448            ("mimg", [Format.MIMG], 'MIMG_instruction', [(0, 4), (1, 3), (0, 3), (1, 2)]), #TODO(pendingchaos): less shapes?
 449            ("exp", [Format.EXP], 'Export_instruction', [(0, 4)]),
 450            ("branch", [Format.PSEUDO_BRANCH], 'Pseudo_branch_instruction', itertools.product([0], [0, 1])),
 451            ("barrier", [Format.PSEUDO_BARRIER], 'Pseudo_barrier_instruction', [(0, 0)]),
 452            ("reduction", [Format.PSEUDO_REDUCTION], 'Pseudo_reduction_instruction', [(3, 2), (3, 4)]),
 453            ("vop1", [Format.VOP1], 'VOP1_instruction', [(1, 1), (2, 2)]),
 454            ("vop2", [Format.VOP2], 'VOP2_instruction', itertools.product([1, 2], [2, 3])),
 455            ("vopc", [Format.VOPC], 'VOPC_instruction', itertools.product([1, 2], [2])),
 456            ("vop3", [Format.VOP3A], 'VOP3A_instruction', [(1, 3), (1, 2), (1, 1), (2, 2)]),
 457            ("vintrp", [Format.VINTRP], 'Interp_instruction', [(1, 2), (1, 3)]),
 458            ("vop1_dpp", [Format.VOP1, Format.DPP], 'DPP_instruction', [(1, 1)]),
 459            ("vop2_dpp", [Format.VOP2, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2, 3])),
 460            ("vopc_dpp", [Format.VOPC, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2])),
 461            ("vop1_e64", [Format.VOP1, Format.VOP3A], 'VOP3A_instruction', itertools.product([1], [1])),
 462            ("vop2_e64", [Format.VOP2, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2, 3])),
 463            ("vopc_e64", [Format.VOPC, Format.VOP3A], 'VOP3A_instruction', itertools.product([1, 2], [2])),
 464            ("flat", [Format.FLAT], 'FLAT_instruction', [(0, 3), (1, 2)]),
 465            ("global", [Format.GLOBAL], 'FLAT_instruction', [(0, 3), (1, 2)])]
 466 %>\\
 467 % for name, formats, struct, shapes in formats:
 468     % for num_definitions, num_operands in shapes:
 469         <%
 470         args = ['aco_opcode opcode']
 471         for i in range(num_definitions):
 472             args.append('Definition def%d' % i)
 473         for i in range(num_operands):
 474             args.append('Op op%d' % i)
 475         for f in formats:
 476             args += f.get_builder_field_decls()
 477         %>\\
 478
 479    Result ${name}(${', '.join(args)})
 480    {
 481       ${struct} *instr = create_instruction<${struct}>(opcode, (Format)(${'|'.join('(int)Format::%s' % f.name for f in formats)}), ${num_operands}, ${num_definitions});
 482         % for i in range(num_definitions):
 483             instr->definitions[${i}] = def${i};
 484         % endfor
 485         % for i in range(num_operands):
 486             instr->operands[${i}] = op${i}.op;
 487         % endfor
 488         % for f in formats:
 489             % for dest, field_name in zip(f.get_builder_field_dests(), f.get_builder_field_names()):
 490       instr->${dest} = ${field_name};
 491             % endfor
 492         % endfor
 493       return insert(instr);
 494    }
 495
 496     % if name == 'sop1' or name == 'sop2' or name == 'sopc':
 497         <%
 498         args[0] = 'WaveSpecificOpcode opcode'
 499         params = []
 500         for i in range(num_definitions):
 501             params.append('def%d' % i)
 502         for i in range(num_operands):
 503             params.append('op%d' % i)
 504         %>\\
 505
 506    inline Result ${name}(${', '.join(args)})
 507    {
 508        return ${name}(w64or32(opcode), ${', '.join(params)});
 509    }
 510
 511     % endif
 512     % endfor
 513 % endfor
 514 };
 515
 516 }
 517 #endif /* _ACO_BUILDER_ */"""
 518
 519 from aco_opcodes import opcodes, Format
 520 from mako.template import Template
 521
 522 print(Template(template).render(opcodes=opcodes, Format=Format))