2 * Copyright © 2018 Valve Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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30 #include "vulkan/radv_shader.h"
37 * The general idea of this pass is:
38 * The CFG is traversed in reverse postorder (forward) and loops are processed
39 * several times until no progress is made.
40 * Per BB two wait_ctx is maintained: an in-context and out-context.
41 * The in-context is the joined out-contexts of the predecessors.
42 * The context contains a map: gpr -> wait_entry
43 * consisting of the information about the cnt values to be waited for.
44 * Note: After merge-nodes, it might occur that for the same register
45 * multiple cnt values are to be waited for.
47 * The values are updated according to the encountered instructions:
48 * - additional events increment the counter of waits of the same type
49 * - or erase gprs with counters higher than to be waited for.
52 // TODO: do a more clever insertion of wait_cnt (lgkm_cnt) when there is a load followed by a use of a previous load
54 /* Instructions of the same event will finish in-order except for smem
55 * and maybe flat. Instructions of different events may not finish in-order. */
56 enum wait_event
: uint16_t {
61 event_vmem_store
= 1 << 4, /* GFX10+ */
63 event_exp_pos
= 1 << 6,
64 event_exp_param
= 1 << 7,
65 event_exp_mrt_null
= 1 << 8,
66 event_gds_gpr_lock
= 1 << 9,
67 event_vmem_gpr_lock
= 1 << 10,
70 enum counter_type
: uint8_t {
72 counter_lgkm
= 1 << 1,
77 static const uint16_t exp_events
= event_exp_pos
| event_exp_param
| event_exp_mrt_null
| event_gds_gpr_lock
| event_vmem_gpr_lock
;
78 static const uint16_t lgkm_events
= event_smem
| event_lds
| event_gds
| event_flat
;
79 static const uint16_t vm_events
= event_vmem
| event_flat
;
80 static const uint16_t vs_events
= event_vmem_store
;
82 uint8_t get_counters_for_event(wait_event ev
)
91 case event_vmem_store
:
94 return counter_vm
| counter_lgkm
;
97 case event_exp_mrt_null
:
98 case event_gds_gpr_lock
:
99 case event_vmem_gpr_lock
:
107 static const uint8_t unset_counter
= 0xff;
115 vm(unset_counter
), exp(unset_counter
), lgkm(unset_counter
), vs(unset_counter
) {}
116 wait_imm(uint16_t vm_
, uint16_t exp_
, uint16_t lgkm_
, uint16_t vs_
) :
117 vm(vm_
), exp(exp_
), lgkm(lgkm_
), vs(vs_
) {}
119 wait_imm(enum chip_class chip
, uint16_t packed
) : vs(unset_counter
)
123 vm
|= (packed
>> 10) & 0x30;
125 exp
= (packed
>> 4) & 0x7;
127 lgkm
= (packed
>> 8) & 0xf;
129 lgkm
|= (packed
>> 8) & 0x30;
132 uint16_t pack(enum chip_class chip
) const
135 assert(exp
== unset_counter
|| exp
<= 0x7);
138 assert(lgkm
== unset_counter
|| lgkm
<= 0x3f);
139 assert(vm
== unset_counter
|| vm
<= 0x3f);
140 imm
= ((vm
& 0x30) << 10) | ((lgkm
& 0x3f) << 8) | ((exp
& 0x7) << 4) | (vm
& 0xf);
143 assert(lgkm
== unset_counter
|| lgkm
<= 0xf);
144 assert(vm
== unset_counter
|| vm
<= 0x3f);
145 imm
= ((vm
& 0x30) << 10) | ((lgkm
& 0xf) << 8) | ((exp
& 0x7) << 4) | (vm
& 0xf);
148 assert(lgkm
== unset_counter
|| lgkm
<= 0xf);
149 assert(vm
== unset_counter
|| vm
<= 0xf);
150 imm
= ((lgkm
& 0xf) << 8) | ((exp
& 0x7) << 4) | (vm
& 0xf);
153 if (chip
< GFX9
&& vm
== wait_imm::unset_counter
)
154 imm
|= 0xc000; /* should have no effect on pre-GFX9 and now we won't have to worry about the architecture when interpreting the immediate */
155 if (chip
< GFX10
&& lgkm
== wait_imm::unset_counter
)
156 imm
|= 0x3000; /* should have no effect on pre-GFX10 and now we won't have to worry about the architecture when interpreting the immediate */
160 bool combine(const wait_imm
& other
)
162 bool changed
= other
.vm
< vm
|| other
.exp
< exp
|| other
.lgkm
< lgkm
|| other
.vs
< vs
;
163 vm
= std::min(vm
, other
.vm
);
164 exp
= std::min(exp
, other
.exp
);
165 lgkm
= std::min(lgkm
, other
.lgkm
);
166 vs
= std::min(vs
, other
.vs
);
172 return vm
== unset_counter
&& exp
== unset_counter
&&
173 lgkm
== unset_counter
&& vs
== unset_counter
;
179 uint16_t events
; /* use wait_event notion */
180 uint8_t counters
; /* use counter_type notion */
184 wait_entry(wait_event event
, wait_imm imm
, bool logical
, bool wait_on_read
)
185 : imm(imm
), events(event
), counters(get_counters_for_event(event
)),
186 wait_on_read(wait_on_read
), logical(logical
) {}
188 bool join(const wait_entry
& other
)
190 bool changed
= (other
.events
& ~events
) ||
191 (other
.counters
& ~counters
) ||
192 (other
.wait_on_read
&& !wait_on_read
);
193 events
|= other
.events
;
194 counters
|= other
.counters
;
195 changed
|= imm
.combine(other
.imm
);
196 wait_on_read
= wait_on_read
|| other
.wait_on_read
;
197 assert(logical
== other
.logical
);
201 void remove_counter(counter_type counter
)
203 counters
&= ~counter
;
205 if (counter
== counter_lgkm
) {
206 imm
.lgkm
= wait_imm::unset_counter
;
207 events
&= ~(event_smem
| event_lds
| event_gds
);
210 if (counter
== counter_vm
) {
211 imm
.vm
= wait_imm::unset_counter
;
212 events
&= ~event_vmem
;
215 if (counter
== counter_exp
) {
216 imm
.exp
= wait_imm::unset_counter
;
217 events
&= ~(event_exp_pos
| event_exp_param
| event_exp_mrt_null
| event_gds_gpr_lock
| event_vmem_gpr_lock
);
220 if (counter
== counter_vs
) {
221 imm
.vs
= wait_imm::unset_counter
;
222 events
&= ~event_vmem_store
;
225 if (!(counters
& counter_lgkm
) && !(counters
& counter_vm
))
226 events
&= ~event_flat
;
232 enum chip_class chip_class
;
234 uint16_t max_exp_cnt
;
235 uint16_t max_lgkm_cnt
;
237 uint16_t unordered_events
= event_smem
| event_flat
;
241 uint8_t lgkm_cnt
= 0;
243 bool pending_flat_lgkm
= false;
244 bool pending_flat_vm
= false;
245 bool pending_s_buffer_store
= false; /* GFX10 workaround */
247 wait_imm barrier_imm
[barrier_count
];
249 std::map
<PhysReg
,wait_entry
> gpr_map
;
252 wait_ctx(Program
*program_
)
254 chip_class(program_
->chip_class
),
255 max_vm_cnt(program_
->chip_class
>= GFX9
? 62 : 14),
257 max_lgkm_cnt(program_
->chip_class
>= GFX10
? 62 : 14),
258 max_vs_cnt(program_
->chip_class
>= GFX10
? 62 : 0),
259 unordered_events(event_smem
| (program_
->chip_class
< GFX10
? event_flat
: 0)) {}
261 bool join(const wait_ctx
* other
, bool logical
)
263 bool changed
= other
->exp_cnt
> exp_cnt
||
264 other
->vm_cnt
> vm_cnt
||
265 other
->lgkm_cnt
> lgkm_cnt
||
266 other
->vs_cnt
> vs_cnt
||
267 (other
->pending_flat_lgkm
&& !pending_flat_lgkm
) ||
268 (other
->pending_flat_vm
&& !pending_flat_vm
);
270 exp_cnt
= std::max(exp_cnt
, other
->exp_cnt
);
271 vm_cnt
= std::max(vm_cnt
, other
->vm_cnt
);
272 lgkm_cnt
= std::max(lgkm_cnt
, other
->lgkm_cnt
);
273 vs_cnt
= std::max(vs_cnt
, other
->vs_cnt
);
274 pending_flat_lgkm
|= other
->pending_flat_lgkm
;
275 pending_flat_vm
|= other
->pending_flat_vm
;
276 pending_s_buffer_store
|= other
->pending_s_buffer_store
;
278 for (std::pair
<PhysReg
,wait_entry
> entry
: other
->gpr_map
)
280 std::map
<PhysReg
,wait_entry
>::iterator it
= gpr_map
.find(entry
.first
);
281 if (entry
.second
.logical
!= logical
)
284 if (it
!= gpr_map
.end()) {
285 changed
|= it
->second
.join(entry
.second
);
287 gpr_map
.insert(entry
);
292 for (unsigned i
= 0; i
< barrier_count
; i
++)
293 changed
|= barrier_imm
[i
].combine(other
->barrier_imm
[i
]);
299 wait_imm
check_instr(Instruction
* instr
, wait_ctx
& ctx
)
303 for (const Operand op
: instr
->operands
) {
304 if (op
.isConstant() || op
.isUndefined())
307 /* check consecutively read gprs */
308 for (unsigned j
= 0; j
< op
.size(); j
++) {
309 PhysReg reg
{op
.physReg() + j
};
310 std::map
<PhysReg
,wait_entry
>::iterator it
= ctx
.gpr_map
.find(reg
);
311 if (it
== ctx
.gpr_map
.end() || !it
->second
.wait_on_read
)
314 wait
.combine(it
->second
.imm
);
318 for (const Definition
& def
: instr
->definitions
) {
319 /* check consecutively written gprs */
320 for (unsigned j
= 0; j
< def
.getTemp().size(); j
++)
322 PhysReg reg
{def
.physReg() + j
};
324 std::map
<PhysReg
,wait_entry
>::iterator it
= ctx
.gpr_map
.find(reg
);
325 if (it
== ctx
.gpr_map
.end())
328 /* Vector Memory reads and writes return in the order they were issued */
329 if (instr
->isVMEM() && ((it
->second
.events
& vm_events
) == event_vmem
)) {
330 it
->second
.remove_counter(counter_vm
);
331 if (!it
->second
.counters
)
332 it
= ctx
.gpr_map
.erase(it
);
336 /* LDS reads and writes return in the order they were issued. same for GDS */
337 if (instr
->format
== Format::DS
) {
338 bool gds
= static_cast<DS_instruction
*>(instr
)->gds
;
339 if ((it
->second
.events
& lgkm_events
) == (gds
? event_gds
: event_lds
)) {
340 it
->second
.remove_counter(counter_lgkm
);
341 if (!it
->second
.counters
)
342 it
= ctx
.gpr_map
.erase(it
);
347 wait
.combine(it
->second
.imm
);
354 wait_imm
parse_wait_instr(wait_ctx
& ctx
, Instruction
*instr
)
356 if (instr
->opcode
== aco_opcode::s_waitcnt_vscnt
&&
357 instr
->definitions
[0].physReg() == sgpr_null
) {
359 imm
.vs
= std::min
<uint8_t>(imm
.vs
, static_cast<SOPK_instruction
*>(instr
)->imm
);
361 } else if (instr
->opcode
== aco_opcode::s_waitcnt
) {
362 return wait_imm(ctx
.chip_class
, static_cast<SOPP_instruction
*>(instr
)->imm
);
367 wait_imm
kill(Instruction
* instr
, wait_ctx
& ctx
)
370 if (ctx
.exp_cnt
|| ctx
.vm_cnt
|| ctx
.lgkm_cnt
)
371 imm
.combine(check_instr(instr
, ctx
));
373 imm
.combine(parse_wait_instr(ctx
, instr
));
375 if (ctx
.chip_class
>= GFX10
) {
376 /* Seems to be required on GFX10 to achieve correct behaviour.
377 * It shouldn't cost anything anyways since we're about to do s_endpgm.
379 if (ctx
.lgkm_cnt
&& instr
->opcode
== aco_opcode::s_dcache_wb
)
382 /* GFX10: A store followed by a load at the same address causes a problem because
383 * the load doesn't load the correct values unless we wait for the store first.
384 * This is NOT mitigated by an s_nop.
386 * TODO: Refine this when we have proper alias analysis.
388 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
);
389 if (ctx
.pending_s_buffer_store
&&
390 !smem
->definitions
.empty() &&
391 !smem
->can_reorder
&& smem
->barrier
== barrier_buffer
) {
396 if (instr
->format
== Format::PSEUDO_BARRIER
) {
397 unsigned* bsize
= ctx
.program
->info
->cs
.block_size
;
398 unsigned workgroup_size
= bsize
[0] * bsize
[1] * bsize
[2];
399 switch (instr
->opcode
) {
400 case aco_opcode::p_memory_barrier_all
:
401 for (unsigned i
= 0; i
< barrier_count
; i
++) {
402 if ((1 << i
) == barrier_shared
&& workgroup_size
<= ctx
.program
->wave_size
)
404 imm
.combine(ctx
.barrier_imm
[i
]);
407 case aco_opcode::p_memory_barrier_atomic
:
408 imm
.combine(ctx
.barrier_imm
[ffs(barrier_atomic
) - 1]);
410 /* see comment in aco_scheduler.cpp's can_move_instr() on why these barriers are merged */
411 case aco_opcode::p_memory_barrier_buffer
:
412 case aco_opcode::p_memory_barrier_image
:
413 imm
.combine(ctx
.barrier_imm
[ffs(barrier_buffer
) - 1]);
414 imm
.combine(ctx
.barrier_imm
[ffs(barrier_image
) - 1]);
416 case aco_opcode::p_memory_barrier_shared
:
417 if (workgroup_size
> ctx
.program
->wave_size
)
418 imm
.combine(ctx
.barrier_imm
[ffs(barrier_shared
) - 1]);
427 if (ctx
.pending_flat_vm
&& imm
.vm
!= wait_imm::unset_counter
)
429 if (ctx
.pending_flat_lgkm
&& imm
.lgkm
!= wait_imm::unset_counter
)
433 ctx
.exp_cnt
= std::min(ctx
.exp_cnt
, imm
.exp
);
434 ctx
.vm_cnt
= std::min(ctx
.vm_cnt
, imm
.vm
);
435 ctx
.lgkm_cnt
= std::min(ctx
.lgkm_cnt
, imm
.lgkm
);
436 ctx
.vs_cnt
= std::min(ctx
.vs_cnt
, imm
.vs
);
438 /* update barrier wait imms */
439 for (unsigned i
= 0; i
< barrier_count
; i
++) {
440 wait_imm
& bar
= ctx
.barrier_imm
[i
];
441 if (bar
.exp
!= wait_imm::unset_counter
&& imm
.exp
<= bar
.exp
)
442 bar
.exp
= wait_imm::unset_counter
;
443 if (bar
.vm
!= wait_imm::unset_counter
&& imm
.vm
<= bar
.vm
)
444 bar
.vm
= wait_imm::unset_counter
;
445 if (bar
.lgkm
!= wait_imm::unset_counter
&& imm
.lgkm
<= bar
.lgkm
)
446 bar
.lgkm
= wait_imm::unset_counter
;
447 if (bar
.vs
!= wait_imm::unset_counter
&& imm
.vs
<= bar
.vs
)
448 bar
.vs
= wait_imm::unset_counter
;
451 /* remove all gprs with higher counter from map */
452 std::map
<PhysReg
,wait_entry
>::iterator it
= ctx
.gpr_map
.begin();
453 while (it
!= ctx
.gpr_map
.end())
455 if (imm
.exp
!= wait_imm::unset_counter
&& imm
.exp
<= it
->second
.imm
.exp
)
456 it
->second
.remove_counter(counter_exp
);
457 if (imm
.vm
!= wait_imm::unset_counter
&& imm
.vm
<= it
->second
.imm
.vm
)
458 it
->second
.remove_counter(counter_vm
);
459 if (imm
.lgkm
!= wait_imm::unset_counter
&& imm
.lgkm
<= it
->second
.imm
.lgkm
)
460 it
->second
.remove_counter(counter_lgkm
);
461 if (imm
.lgkm
!= wait_imm::unset_counter
&& imm
.vs
<= it
->second
.imm
.vs
)
462 it
->second
.remove_counter(counter_vs
);
463 if (!it
->second
.counters
)
464 it
= ctx
.gpr_map
.erase(it
);
471 ctx
.pending_flat_vm
= false;
473 ctx
.pending_flat_lgkm
= false;
474 ctx
.pending_s_buffer_store
= false;
480 void update_barrier_imm(wait_ctx
& ctx
, uint8_t counters
, barrier_interaction barrier
)
482 unsigned barrier_index
= ffs(barrier
) - 1;
483 for (unsigned i
= 0; i
< barrier_count
; i
++) {
484 wait_imm
& bar
= ctx
.barrier_imm
[i
];
485 if (i
== barrier_index
) {
486 if (counters
& counter_lgkm
)
488 if (counters
& counter_vm
)
490 if (counters
& counter_exp
)
492 if (counters
& counter_vs
)
495 if (counters
& counter_lgkm
&& bar
.lgkm
!= wait_imm::unset_counter
&& bar
.lgkm
< ctx
.max_lgkm_cnt
)
497 if (counters
& counter_vm
&& bar
.vm
!= wait_imm::unset_counter
&& bar
.vm
< ctx
.max_vm_cnt
)
499 if (counters
& counter_exp
&& bar
.exp
!= wait_imm::unset_counter
&& bar
.exp
< ctx
.max_exp_cnt
)
501 if (counters
& counter_vs
&& bar
.vs
!= wait_imm::unset_counter
&& bar
.vs
< ctx
.max_vs_cnt
)
507 void update_counters(wait_ctx
& ctx
, wait_event event
, barrier_interaction barrier
=barrier_none
)
509 uint8_t counters
= get_counters_for_event(event
);
511 if (counters
& counter_lgkm
&& ctx
.lgkm_cnt
<= ctx
.max_lgkm_cnt
)
513 if (counters
& counter_vm
&& ctx
.vm_cnt
<= ctx
.max_vm_cnt
)
515 if (counters
& counter_exp
&& ctx
.exp_cnt
<= ctx
.max_exp_cnt
)
517 if (counters
& counter_vs
&& ctx
.vs_cnt
<= ctx
.max_vs_cnt
)
520 update_barrier_imm(ctx
, counters
, barrier
);
522 if (ctx
.unordered_events
& event
)
525 if (ctx
.pending_flat_lgkm
)
526 counters
&= ~counter_lgkm
;
527 if (ctx
.pending_flat_vm
)
528 counters
&= ~counter_vm
;
530 for (std::pair
<const PhysReg
,wait_entry
>& e
: ctx
.gpr_map
) {
531 wait_entry
& entry
= e
.second
;
533 if (entry
.events
& ctx
.unordered_events
)
536 assert(entry
.events
);
538 if ((counters
& counter_exp
) && (entry
.events
& exp_events
) == event
&& entry
.imm
.exp
< ctx
.max_exp_cnt
)
540 if ((counters
& counter_lgkm
) && (entry
.events
& lgkm_events
) == event
&& entry
.imm
.lgkm
< ctx
.max_lgkm_cnt
)
542 if ((counters
& counter_vm
) && (entry
.events
& vm_events
) == event
&& entry
.imm
.vm
< ctx
.max_vm_cnt
)
544 if ((counters
& counter_vs
) && (entry
.events
& vs_events
) == event
&& entry
.imm
.vs
< ctx
.max_vs_cnt
)
549 void update_counters_for_flat_load(wait_ctx
& ctx
, barrier_interaction barrier
=barrier_none
)
551 assert(ctx
.chip_class
< GFX10
);
553 if (ctx
.lgkm_cnt
<= ctx
.max_lgkm_cnt
)
555 if (ctx
.vm_cnt
<= ctx
.max_vm_cnt
)
558 update_barrier_imm(ctx
, counter_vm
| counter_lgkm
, barrier
);
560 for (std::pair
<PhysReg
,wait_entry
> e
: ctx
.gpr_map
)
562 if (e
.second
.counters
& counter_vm
)
564 if (e
.second
.counters
& counter_lgkm
)
565 e
.second
.imm
.lgkm
= 0;
567 ctx
.pending_flat_lgkm
= true;
568 ctx
.pending_flat_vm
= true;
571 void insert_wait_entry(wait_ctx
& ctx
, PhysReg reg
, RegClass rc
, wait_event event
, bool wait_on_read
)
573 uint16_t counters
= get_counters_for_event(event
);
575 if (counters
& counter_lgkm
)
577 if (counters
& counter_vm
)
579 if (counters
& counter_exp
)
581 if (counters
& counter_vs
)
584 wait_entry
new_entry(event
, imm
, !rc
.is_linear(), wait_on_read
);
586 for (unsigned i
= 0; i
< rc
.size(); i
++) {
587 auto it
= ctx
.gpr_map
.emplace(PhysReg
{reg
.reg
+i
}, new_entry
);
589 it
.first
->second
.join(new_entry
);
593 void insert_wait_entry(wait_ctx
& ctx
, Operand op
, wait_event event
)
595 if (!op
.isConstant() && !op
.isUndefined())
596 insert_wait_entry(ctx
, op
.physReg(), op
.regClass(), event
, false);
599 void insert_wait_entry(wait_ctx
& ctx
, Definition def
, wait_event event
)
601 insert_wait_entry(ctx
, def
.physReg(), def
.regClass(), event
, true);
604 void gen(Instruction
* instr
, wait_ctx
& ctx
)
606 switch (instr
->format
) {
608 Export_instruction
* exp_instr
= static_cast<Export_instruction
*>(instr
);
611 if (exp_instr
->dest
<= 9)
612 ev
= event_exp_mrt_null
;
613 else if (exp_instr
->dest
<= 15)
616 ev
= event_exp_param
;
617 update_counters(ctx
, ev
);
619 /* insert new entries for exported vgprs */
620 for (unsigned i
= 0; i
< 4; i
++)
622 if (exp_instr
->enabled_mask
& (1 << i
)) {
623 unsigned idx
= exp_instr
->compressed
? i
>> 1 : i
;
624 assert(idx
< exp_instr
->operands
.size());
625 insert_wait_entry(ctx
, exp_instr
->operands
[idx
], ev
);
629 insert_wait_entry(ctx
, exec
, s2
, ev
, false);
633 if (ctx
.chip_class
< GFX10
&& !instr
->definitions
.empty())
634 update_counters_for_flat_load(ctx
, barrier_buffer
);
636 update_counters(ctx
, event_flat
, barrier_buffer
);
638 if (!instr
->definitions
.empty())
639 insert_wait_entry(ctx
, instr
->definitions
[0], event_flat
);
643 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
);
644 update_counters(ctx
, event_smem
, static_cast<SMEM_instruction
*>(instr
)->barrier
);
646 if (!instr
->definitions
.empty())
647 insert_wait_entry(ctx
, instr
->definitions
[0], event_smem
);
648 else if (ctx
.chip_class
>= GFX10
&&
649 !smem
->can_reorder
&&
650 smem
->barrier
== barrier_buffer
)
651 ctx
.pending_s_buffer_store
= true;
656 bool gds
= static_cast<DS_instruction
*>(instr
)->gds
;
657 update_counters(ctx
, gds
? event_gds
: event_lds
, gds
? barrier_none
: barrier_shared
);
659 update_counters(ctx
, event_gds_gpr_lock
);
661 if (!instr
->definitions
.empty())
662 insert_wait_entry(ctx
, instr
->definitions
[0], gds
? event_gds
: event_lds
);
665 for (const Operand
& op
: instr
->operands
)
666 insert_wait_entry(ctx
, op
, event_gds_gpr_lock
);
667 insert_wait_entry(ctx
, exec
, s2
, event_gds_gpr_lock
, false);
674 case Format::GLOBAL
: {
675 wait_event ev
= !instr
->definitions
.empty() || ctx
.chip_class
< GFX10
? event_vmem
: event_vmem_store
;
676 update_counters(ctx
, ev
, get_barrier_interaction(instr
));
678 if (!instr
->definitions
.empty())
679 insert_wait_entry(ctx
, instr
->definitions
[0], ev
);
681 if (instr
->operands
.size() == 4 && ctx
.chip_class
== GFX6
) {
683 update_counters(ctx
, event_vmem_gpr_lock
);
684 insert_wait_entry(ctx
, instr
->operands
[3], event_vmem_gpr_lock
);
693 void emit_waitcnt(wait_ctx
& ctx
, std::vector
<aco_ptr
<Instruction
>>& instructions
, wait_imm imm
)
695 if (imm
.vs
!= wait_imm::unset_counter
) {
696 assert(ctx
.chip_class
>= GFX10
);
697 SOPK_instruction
* waitcnt_vs
= create_instruction
<SOPK_instruction
>(aco_opcode::s_waitcnt_vscnt
, Format::SOPK
, 0, 1);
698 waitcnt_vs
->definitions
[0] = Definition(sgpr_null
, s1
);
699 waitcnt_vs
->imm
= imm
.vs
;
700 instructions
.emplace_back(waitcnt_vs
);
701 imm
.vs
= wait_imm::unset_counter
;
704 SOPP_instruction
* waitcnt
= create_instruction
<SOPP_instruction
>(aco_opcode::s_waitcnt
, Format::SOPP
, 0, 0);
705 waitcnt
->imm
= imm
.pack(ctx
.chip_class
);
707 instructions
.emplace_back(waitcnt
);
711 void handle_block(Program
*program
, Block
& block
, wait_ctx
& ctx
)
713 std::vector
<aco_ptr
<Instruction
>> new_instructions
;
716 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
717 bool is_wait
= !parse_wait_instr(ctx
, instr
.get()).empty();
719 queued_imm
.combine(kill(instr
.get(), ctx
));
721 gen(instr
.get(), ctx
);
723 if (instr
->format
!= Format::PSEUDO_BARRIER
&& !is_wait
) {
724 if (!queued_imm
.empty()) {
725 emit_waitcnt(ctx
, new_instructions
, queued_imm
);
726 queued_imm
= wait_imm();
728 new_instructions
.emplace_back(std::move(instr
));
732 if (!queued_imm
.empty())
733 emit_waitcnt(ctx
, new_instructions
, queued_imm
);
735 block
.instructions
.swap(new_instructions
);
738 } /* end namespace */
740 void insert_wait_states(Program
* program
)
743 std::vector
<bool> done(program
->blocks
.size());
744 wait_ctx in_ctx
[program
->blocks
.size()];
745 wait_ctx out_ctx
[program
->blocks
.size()];
746 for (unsigned i
= 0; i
< program
->blocks
.size(); i
++)
747 in_ctx
[i
] = wait_ctx(program
);
748 std::stack
<unsigned> loop_header_indices
;
749 unsigned loop_progress
= 0;
751 for (unsigned i
= 0; i
< program
->blocks
.size();) {
752 Block
& current
= program
->blocks
[i
++];
753 wait_ctx ctx
= in_ctx
[current
.index
];
755 if (current
.kind
& block_kind_loop_header
) {
756 loop_header_indices
.push(current
.index
);
757 } else if (current
.kind
& block_kind_loop_exit
) {
759 if (loop_progress
== loop_header_indices
.size()) {
760 i
= loop_header_indices
.top();
763 loop_header_indices
.pop();
764 loop_progress
= std::min
<unsigned>(loop_progress
, loop_header_indices
.size());
769 bool changed
= false;
770 for (unsigned b
: current
.linear_preds
)
771 changed
|= ctx
.join(&out_ctx
[b
], false);
772 for (unsigned b
: current
.logical_preds
)
773 changed
|= ctx
.join(&out_ctx
[b
], true);
775 in_ctx
[current
.index
] = ctx
;
777 if (done
[current
.index
] && !changed
)
780 if (current
.instructions
.empty()) {
781 out_ctx
[current
.index
] = ctx
;
785 loop_progress
= std::max
<unsigned>(loop_progress
, current
.loop_nest_depth
);
786 done
[current
.index
] = true;
788 handle_block(program
, current
, ctx
);
790 out_ctx
[current
.index
] = ctx
;