src/amd/compiler/aco_insert_waitcnt.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <algorithm>
  26 #include <map>
  27 #include <stack>
  28 #include <math.h>
  29
  30 #include "aco_ir.h"
  31 #include "vulkan/radv_shader.h"
  32
  33 namespace aco {
  34
  35 namespace {
  36
  37 /**
  38  * The general idea of this pass is:
  39  * The CFG is traversed in reverse postorder (forward) and loops are processed
  40  * several times until no progress is made.
  41  * Per BB two wait_ctx is maintained: an in-context and out-context.
  42  * The in-context is the joined out-contexts of the predecessors.
  43  * The context contains a map: gpr -> wait_entry
  44  * consisting of the information about the cnt values to be waited for.
  45  * Note: After merge-nodes, it might occur that for the same register
  46  *       multiple cnt values are to be waited for.
  47  *
  48  * The values are updated according to the encountered instructions:
  49  * - additional events increment the counter of waits of the same type
  50  * - or erase gprs with counters higher than to be waited for.
  51  */
  52
  53 // TODO: do a more clever insertion of wait_cnt (lgkm_cnt) when there is a load followed by a use of a previous load
  54
  55 /* Instructions of the same event will finish in-order except for smem
  56  * and maybe flat. Instructions of different events may not finish in-order. */
  57 enum wait_event : uint16_t {
  58    event_smem = 1 << 0,
  59    event_lds = 1 << 1,
  60    event_gds = 1 << 2,
  61    event_vmem = 1 << 3,
  62    event_vmem_store = 1 << 4, /* GFX10+ */
  63    event_flat = 1 << 5,
  64    event_exp_pos = 1 << 6,
  65    event_exp_param = 1 << 7,
  66    event_exp_mrt_null = 1 << 8,
  67    event_gds_gpr_lock = 1 << 9,
  68    event_vmem_gpr_lock = 1 << 10,
  69    event_sendmsg = 1 << 11,
  70    num_events = 12,
  71 };
  72
  73 enum counter_type : uint8_t {
  74    counter_exp = 1 << 0,
  75    counter_lgkm = 1 << 1,
  76    counter_vm = 1 << 2,
  77    counter_vs = 1 << 3,
  78    num_counters = 4,
  79 };
  80
  81 static const uint16_t exp_events = event_exp_pos | event_exp_param | event_exp_mrt_null | event_gds_gpr_lock | event_vmem_gpr_lock;
  82 static const uint16_t lgkm_events = event_smem | event_lds | event_gds | event_flat | event_sendmsg;
  83 static const uint16_t vm_events = event_vmem | event_flat;
  84 static const uint16_t vs_events = event_vmem_store;
  85
  86 uint8_t get_counters_for_event(wait_event ev)
  87 {
  88    switch (ev) {
  89    case event_smem:
  90    case event_lds:
  91    case event_gds:
  92    case event_sendmsg:
  93       return counter_lgkm;
  94    case event_vmem:
  95       return counter_vm;
  96    case event_vmem_store:
  97       return counter_vs;
  98    case event_flat:
  99       return counter_vm | counter_lgkm;
 100    case event_exp_pos:
 101    case event_exp_param:
 102    case event_exp_mrt_null:
 103    case event_gds_gpr_lock:
 104    case event_vmem_gpr_lock:
 105       return counter_exp;
 106    default:
 107       return 0;
 108    }
 109 }
 110
 111 uint16_t get_events_for_counter(counter_type ctr)
 112 {
 113    switch (ctr) {
 114    case counter_exp:
 115       return exp_events;
 116    case counter_lgkm:
 117       return lgkm_events;
 118    case counter_vm:
 119       return vm_events;
 120    case counter_vs:
 121       return vs_events;
 122    }
 123    return 0;
 124 }
 125
 126 struct wait_imm {
 127    static const uint8_t unset_counter = 0xff;
 128
 129    uint8_t vm;
 130    uint8_t exp;
 131    uint8_t lgkm;
 132    uint8_t vs;
 133
 134    wait_imm() :
 135       vm(unset_counter), exp(unset_counter), lgkm(unset_counter), vs(unset_counter) {}
 136    wait_imm(uint16_t vm_, uint16_t exp_, uint16_t lgkm_, uint16_t vs_) :
 137       vm(vm_), exp(exp_), lgkm(lgkm_), vs(vs_) {}
 138
 139    wait_imm(enum chip_class chip, uint16_t packed) : vs(unset_counter)
 140    {
 141       vm = packed & 0xf;
 142       if (chip >= GFX9)
 143          vm |= (packed >> 10) & 0x30;
 144
 145       exp = (packed >> 4) & 0x7;
 146
 147       lgkm = (packed >> 8) & 0xf;
 148       if (chip >= GFX10)
 149          lgkm |= (packed >> 8) & 0x30;
 150    }
 151
 152    uint16_t pack(enum chip_class chip) const
 153    {
 154       uint16_t imm = 0;
 155       assert(exp == unset_counter || exp <= 0x7);
 156       switch (chip) {
 157       case GFX10:
 158          assert(lgkm == unset_counter || lgkm <= 0x3f);
 159          assert(vm == unset_counter || vm <= 0x3f);
 160          imm = ((vm & 0x30) << 10) | ((lgkm & 0x3f) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
 161          break;
 162       case GFX9:
 163          assert(lgkm == unset_counter || lgkm <= 0xf);
 164          assert(vm == unset_counter || vm <= 0x3f);
 165          imm = ((vm & 0x30) << 10) | ((lgkm & 0xf) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
 166          break;
 167       default:
 168          assert(lgkm == unset_counter || lgkm <= 0xf);
 169          assert(vm == unset_counter || vm <= 0xf);
 170          imm = ((lgkm & 0xf) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
 171          break;
 172       }
 173       if (chip < GFX9 && vm == wait_imm::unset_counter)
 174          imm |= 0xc000; /* should have no effect on pre-GFX9 and now we won't have to worry about the architecture when interpreting the immediate */
 175       if (chip < GFX10 && lgkm == wait_imm::unset_counter)
 176          imm |= 0x3000; /* should have no effect on pre-GFX10 and now we won't have to worry about the architecture when interpreting the immediate */
 177       return imm;
 178    }
 179
 180    bool combine(const wait_imm& other)
 181    {
 182       bool changed = other.vm < vm || other.exp < exp || other.lgkm < lgkm || other.vs < vs;
 183       vm = std::min(vm, other.vm);
 184       exp = std::min(exp, other.exp);
 185       lgkm = std::min(lgkm, other.lgkm);
 186       vs = std::min(vs, other.vs);
 187       return changed;
 188    }
 189
 190    bool empty() const
 191    {
 192       return vm == unset_counter && exp == unset_counter &&
 193              lgkm == unset_counter && vs == unset_counter;
 194    }
 195 };
 196
 197 struct wait_entry {
 198    wait_imm imm;
 199    uint16_t events; /* use wait_event notion */
 200    uint8_t counters; /* use counter_type notion */
 201    bool wait_on_read:1;
 202    bool logical:1;
 203
 204    wait_entry(wait_event event, wait_imm imm, bool logical, bool wait_on_read)
 205            : imm(imm), events(event), counters(get_counters_for_event(event)),
 206              wait_on_read(wait_on_read), logical(logical) {}
 207
 208    bool join(const wait_entry& other)
 209    {
 210       bool changed = (other.events & ~events) ||
 211                      (other.counters & ~counters) ||
 212                      (other.wait_on_read && !wait_on_read);
 213       events |= other.events;
 214       counters |= other.counters;
 215       changed |= imm.combine(other.imm);
 216       wait_on_read = wait_on_read || other.wait_on_read;
 217       assert(logical == other.logical);
 218       return changed;
 219    }
 220
 221    void remove_counter(counter_type counter)
 222    {
 223       counters &= ~counter;
 224
 225       if (counter == counter_lgkm) {
 226          imm.lgkm = wait_imm::unset_counter;
 227          events &= ~(event_smem | event_lds | event_gds | event_sendmsg);
 228       }
 229
 230       if (counter == counter_vm) {
 231          imm.vm = wait_imm::unset_counter;
 232          events &= ~event_vmem;
 233       }
 234
 235       if (counter == counter_exp) {
 236          imm.exp = wait_imm::unset_counter;
 237          events &= ~(event_exp_pos | event_exp_param | event_exp_mrt_null | event_gds_gpr_lock | event_vmem_gpr_lock);
 238       }
 239
 240       if (counter == counter_vs) {
 241          imm.vs = wait_imm::unset_counter;
 242          events &= ~event_vmem_store;
 243       }
 244
 245       if (!(counters & counter_lgkm) && !(counters & counter_vm))
 246          events &= ~event_flat;
 247    }
 248 };
 249
 250 struct wait_ctx {
 251    Program *program;
 252    enum chip_class chip_class;
 253    uint16_t max_vm_cnt;
 254    uint16_t max_exp_cnt;
 255    uint16_t max_lgkm_cnt;
 256    uint16_t max_vs_cnt;
 257    uint16_t unordered_events = event_smem | event_flat;
 258
 259    uint8_t vm_cnt = 0;
 260    uint8_t exp_cnt = 0;
 261    uint8_t lgkm_cnt = 0;
 262    uint8_t vs_cnt = 0;
 263    bool pending_flat_lgkm = false;
 264    bool pending_flat_vm = false;
 265    bool pending_s_buffer_store = false; /* GFX10 workaround */
 266
 267    wait_imm barrier_imm[barrier_count];
 268    uint16_t barrier_events[barrier_count] = {}; /* use wait_event notion */
 269
 270    std::map<PhysReg,wait_entry> gpr_map;
 271
 272    /* used for vmem/smem scores */
 273    bool collect_statistics;
 274    Instruction *gen_instr;
 275    std::map<Instruction *, unsigned> unwaited_instrs[num_counters];
 276    std::map<PhysReg,std::set<Instruction *>> reg_instrs[num_counters];
 277    std::vector<unsigned> wait_distances[num_events];
 278
 279    wait_ctx() {}
 280    wait_ctx(Program *program_)
 281            : program(program_),
 282              chip_class(program_->chip_class),
 283              max_vm_cnt(program_->chip_class >= GFX9 ? 62 : 14),
 284              max_exp_cnt(6),
 285              max_lgkm_cnt(program_->chip_class >= GFX10 ? 62 : 14),
 286              max_vs_cnt(program_->chip_class >= GFX10 ? 62 : 0),
 287              unordered_events(event_smem | (program_->chip_class < GFX10 ? event_flat : 0)) {}
 288
 289    bool join(const wait_ctx* other, bool logical)
 290    {
 291       bool changed = other->exp_cnt > exp_cnt ||
 292                      other->vm_cnt > vm_cnt ||
 293                      other->lgkm_cnt > lgkm_cnt ||
 294                      other->vs_cnt > vs_cnt ||
 295                      (other->pending_flat_lgkm && !pending_flat_lgkm) ||
 296                      (other->pending_flat_vm && !pending_flat_vm);
 297
 298       exp_cnt = std::max(exp_cnt, other->exp_cnt);
 299       vm_cnt = std::max(vm_cnt, other->vm_cnt);
 300       lgkm_cnt = std::max(lgkm_cnt, other->lgkm_cnt);
 301       vs_cnt = std::max(vs_cnt, other->vs_cnt);
 302       pending_flat_lgkm |= other->pending_flat_lgkm;
 303       pending_flat_vm |= other->pending_flat_vm;
 304       pending_s_buffer_store |= other->pending_s_buffer_store;
 305
 306       for (std::pair<PhysReg,wait_entry> entry : other->gpr_map)
 307       {
 308          std::map<PhysReg,wait_entry>::iterator it = gpr_map.find(entry.first);
 309          if (entry.second.logical != logical)
 310             continue;
 311
 312          if (it != gpr_map.end()) {
 313             changed |= it->second.join(entry.second);
 314          } else {
 315             gpr_map.insert(entry);
 316             changed = true;
 317          }
 318       }
 319
 320       for (unsigned i = 0; i < barrier_count; i++) {
 321          changed |= barrier_imm[i].combine(other->barrier_imm[i]);
 322          changed |= other->barrier_events[i] & ~barrier_events[i];
 323          barrier_events[i] |= other->barrier_events[i];
 324       }
 325
 326       /* these are used for statistics, so don't update "changed" */
 327       for (unsigned i = 0; i < num_counters; i++) {
 328          for (std::pair<Instruction *, unsigned> instr : other->unwaited_instrs[i]) {
 329             auto pos = unwaited_instrs[i].find(instr.first);
 330             if (pos == unwaited_instrs[i].end())
 331                unwaited_instrs[i].insert(instr);
 332             else
 333                pos->second = std::min(pos->second, instr.second);
 334          }
 335          /* don't use a foreach loop to avoid copies */
 336          for (auto it = other->reg_instrs[i].begin(); it != other->reg_instrs[i].end(); ++it)
 337             reg_instrs[i][it->first].insert(it->second.begin(), it->second.end());
 338       }
 339
 340       return changed;
 341    }
 342
 343    void wait_and_remove_from_entry(PhysReg reg, wait_entry& entry, counter_type counter) {
 344       if (collect_statistics && (entry.counters & counter)) {
 345          unsigned counter_idx = ffs(counter) - 1;
 346          for (Instruction *instr : reg_instrs[counter_idx][reg]) {
 347             auto pos = unwaited_instrs[counter_idx].find(instr);
 348             if (pos == unwaited_instrs[counter_idx].end())
 349                continue;
 350
 351             unsigned distance = pos->second;
 352             unsigned events = entry.events & get_events_for_counter(counter);
 353             while (events) {
 354                unsigned event_idx = u_bit_scan(&events);
 355                wait_distances[event_idx].push_back(distance);
 356             }
 357
 358             unwaited_instrs[counter_idx].erase(instr);
 359          }
 360          reg_instrs[counter_idx][reg].clear();
 361       }
 362
 363       entry.remove_counter(counter);
 364    }
 365
 366    void advance_unwaited_instrs()
 367    {
 368       for (unsigned i = 0; i < num_counters; i++) {
 369          for (auto it = unwaited_instrs[i].begin(); it != unwaited_instrs[i].end(); ++it)
 370             it->second++;
 371       }
 372    }
 373 };
 374
 375 wait_imm check_instr(Instruction* instr, wait_ctx& ctx)
 376 {
 377    wait_imm wait;
 378
 379    for (const Operand op : instr->operands) {
 380       if (op.isConstant() || op.isUndefined())
 381          continue;
 382
 383       /* check consecutively read gprs */
 384       for (unsigned j = 0; j < op.size(); j++) {
 385          PhysReg reg{op.physReg() + j};
 386          std::map<PhysReg,wait_entry>::iterator it = ctx.gpr_map.find(reg);
 387          if (it == ctx.gpr_map.end() || !it->second.wait_on_read)
 388             continue;
 389
 390          wait.combine(it->second.imm);
 391       }
 392    }
 393
 394    for (const Definition& def : instr->definitions) {
 395       /* check consecutively written gprs */
 396       for (unsigned j = 0; j < def.getTemp().size(); j++)
 397       {
 398          PhysReg reg{def.physReg() + j};
 399
 400          std::map<PhysReg,wait_entry>::iterator it = ctx.gpr_map.find(reg);
 401          if (it == ctx.gpr_map.end())
 402             continue;
 403
 404          /* Vector Memory reads and writes return in the order they were issued */
 405          if (instr->isVMEM() && ((it->second.events & vm_events) == event_vmem))
 406             continue;
 407
 408          /* LDS reads and writes return in the order they were issued. same for GDS */
 409          if (instr->format == Format::DS) {
 410             bool gds = static_cast<DS_instruction*>(instr)->gds;
 411             if ((it->second.events & lgkm_events) == (gds ? event_gds : event_lds))
 412                continue;
 413          }
 414
 415          wait.combine(it->second.imm);
 416       }
 417    }
 418
 419    return wait;
 420 }
 421
 422 wait_imm parse_wait_instr(wait_ctx& ctx, Instruction *instr)
 423 {
 424    if (instr->opcode == aco_opcode::s_waitcnt_vscnt &&
 425        instr->definitions[0].physReg() == sgpr_null) {
 426       wait_imm imm;
 427       imm.vs = std::min<uint8_t>(imm.vs, static_cast<SOPK_instruction*>(instr)->imm);
 428       return imm;
 429    } else if (instr->opcode == aco_opcode::s_waitcnt) {
 430       return wait_imm(ctx.chip_class, static_cast<SOPP_instruction*>(instr)->imm);
 431    }
 432    return wait_imm();
 433 }
 434
 435 wait_imm kill(Instruction* instr, wait_ctx& ctx)
 436 {
 437    wait_imm imm;
 438    if (ctx.exp_cnt || ctx.vm_cnt || ctx.lgkm_cnt)
 439       imm.combine(check_instr(instr, ctx));
 440
 441    imm.combine(parse_wait_instr(ctx, instr));
 442
 443
 444    /* It's required to wait for scalar stores before "writing back" data.
 445     * It shouldn't cost anything anyways since we're about to do s_endpgm.
 446     */
 447    if (ctx.lgkm_cnt && instr->opcode == aco_opcode::s_dcache_wb) {
 448       assert(ctx.chip_class >= GFX8);
 449       imm.lgkm = 0;
 450    }
 451
 452    if (ctx.chip_class >= GFX10) {
 453       /* GFX10: A store followed by a load at the same address causes a problem because
 454        * the load doesn't load the correct values unless we wait for the store first.
 455        * This is NOT mitigated by an s_nop.
 456        *
 457        * TODO: Refine this when we have proper alias analysis.
 458        */
 459       SMEM_instruction *smem = static_cast<SMEM_instruction *>(instr);
 460       if (ctx.pending_s_buffer_store &&
 461           !smem->definitions.empty() &&
 462           !smem->can_reorder && smem->barrier == barrier_buffer) {
 463          imm.lgkm = 0;
 464       }
 465    }
 466
 467    if (instr->format == Format::PSEUDO_BARRIER) {
 468       switch (instr->opcode) {
 469       case aco_opcode::p_memory_barrier_common:
 470          imm.combine(ctx.barrier_imm[ffs(barrier_atomic) - 1]);
 471          imm.combine(ctx.barrier_imm[ffs(barrier_buffer) - 1]);
 472          imm.combine(ctx.barrier_imm[ffs(barrier_image) - 1]);
 473          if (ctx.program->workgroup_size > ctx.program->wave_size)
 474             imm.combine(ctx.barrier_imm[ffs(barrier_shared) - 1]);
 475          break;
 476       case aco_opcode::p_memory_barrier_atomic:
 477          imm.combine(ctx.barrier_imm[ffs(barrier_atomic) - 1]);
 478          break;
 479       /* see comment in aco_scheduler.cpp's can_move_instr() on why these barriers are merged */
 480       case aco_opcode::p_memory_barrier_buffer:
 481       case aco_opcode::p_memory_barrier_image:
 482          imm.combine(ctx.barrier_imm[ffs(barrier_buffer) - 1]);
 483          imm.combine(ctx.barrier_imm[ffs(barrier_image) - 1]);
 484          break;
 485       case aco_opcode::p_memory_barrier_shared:
 486          if (ctx.program->workgroup_size > ctx.program->wave_size)
 487             imm.combine(ctx.barrier_imm[ffs(barrier_shared) - 1]);
 488          break;
 489       case aco_opcode::p_memory_barrier_gs_data:
 490          imm.combine(ctx.barrier_imm[ffs(barrier_gs_data) - 1]);
 491          break;
 492       case aco_opcode::p_memory_barrier_gs_sendmsg:
 493          imm.combine(ctx.barrier_imm[ffs(barrier_gs_sendmsg) - 1]);
 494          break;
 495       default:
 496          assert(false);
 497          break;
 498       }
 499    }
 500
 501    if (!imm.empty()) {
 502       if (ctx.pending_flat_vm && imm.vm != wait_imm::unset_counter)
 503          imm.vm = 0;
 504       if (ctx.pending_flat_lgkm && imm.lgkm != wait_imm::unset_counter)
 505          imm.lgkm = 0;
 506
 507       /* reset counters */
 508       ctx.exp_cnt = std::min(ctx.exp_cnt, imm.exp);
 509       ctx.vm_cnt = std::min(ctx.vm_cnt, imm.vm);
 510       ctx.lgkm_cnt = std::min(ctx.lgkm_cnt, imm.lgkm);
 511       ctx.vs_cnt = std::min(ctx.vs_cnt, imm.vs);
 512
 513       /* update barrier wait imms */
 514       for (unsigned i = 0; i < barrier_count; i++) {
 515          wait_imm& bar = ctx.barrier_imm[i];
 516          uint16_t& bar_ev = ctx.barrier_events[i];
 517          if (bar.exp != wait_imm::unset_counter && imm.exp <= bar.exp) {
 518             bar.exp = wait_imm::unset_counter;
 519             bar_ev &= ~exp_events;
 520          }
 521          if (bar.vm != wait_imm::unset_counter && imm.vm <= bar.vm) {
 522             bar.vm = wait_imm::unset_counter;
 523             bar_ev &= ~(vm_events & ~event_flat);
 524          }
 525          if (bar.lgkm != wait_imm::unset_counter && imm.lgkm <= bar.lgkm) {
 526             bar.lgkm = wait_imm::unset_counter;
 527             bar_ev &= ~(lgkm_events & ~event_flat);
 528          }
 529          if (bar.vs != wait_imm::unset_counter && imm.vs <= bar.vs) {
 530             bar.vs = wait_imm::unset_counter;
 531             bar_ev &= ~vs_events;
 532          }
 533          if (bar.vm == wait_imm::unset_counter && bar.lgkm == wait_imm::unset_counter)
 534             bar_ev &= ~event_flat;
 535       }
 536
 537       /* remove all gprs with higher counter from map */
 538       std::map<PhysReg,wait_entry>::iterator it = ctx.gpr_map.begin();
 539       while (it != ctx.gpr_map.end())
 540       {
 541          if (imm.exp != wait_imm::unset_counter && imm.exp <= it->second.imm.exp)
 542             ctx.wait_and_remove_from_entry(it->first, it->second, counter_exp);
 543          if (imm.vm != wait_imm::unset_counter && imm.vm <= it->second.imm.vm)
 544             ctx.wait_and_remove_from_entry(it->first, it->second, counter_vm);
 545          if (imm.lgkm != wait_imm::unset_counter && imm.lgkm <= it->second.imm.lgkm)
 546             ctx.wait_and_remove_from_entry(it->first, it->second, counter_lgkm);
 547          if (imm.lgkm != wait_imm::unset_counter && imm.vs <= it->second.imm.vs)
 548             ctx.wait_and_remove_from_entry(it->first, it->second, counter_vs);
 549          if (!it->second.counters)
 550             it = ctx.gpr_map.erase(it);
 551          else
 552             it++;
 553       }
 554    }
 555
 556    if (imm.vm == 0)
 557       ctx.pending_flat_vm = false;
 558    if (imm.lgkm == 0) {
 559       ctx.pending_flat_lgkm = false;
 560       ctx.pending_s_buffer_store = false;
 561    }
 562
 563    return imm;
 564 }
 565
 566 void update_barrier_counter(uint8_t *ctr, unsigned max)
 567 {
 568    if (*ctr != wait_imm::unset_counter && *ctr < max)
 569       (*ctr)++;
 570 }
 571
 572 void update_barrier_imm(wait_ctx& ctx, uint8_t counters, wait_event event, barrier_interaction barrier)
 573 {
 574    for (unsigned i = 0; i < barrier_count; i++) {
 575       wait_imm& bar = ctx.barrier_imm[i];
 576       uint16_t& bar_ev = ctx.barrier_events[i];
 577       if (barrier & (1 << i)) {
 578          bar_ev |= event;
 579          if (counters & counter_lgkm)
 580             bar.lgkm = 0;
 581          if (counters & counter_vm)
 582             bar.vm = 0;
 583          if (counters & counter_exp)
 584             bar.exp = 0;
 585          if (counters & counter_vs)
 586             bar.vs = 0;
 587       } else if (!(bar_ev & ctx.unordered_events) && !(ctx.unordered_events & event)) {
 588          if (counters & counter_lgkm && (bar_ev & lgkm_events) == event)
 589             update_barrier_counter(&bar.lgkm, ctx.max_lgkm_cnt);
 590          if (counters & counter_vm && (bar_ev & vm_events) == event)
 591             update_barrier_counter(&bar.vm, ctx.max_vm_cnt);
 592          if (counters & counter_exp && (bar_ev & exp_events) == event)
 593             update_barrier_counter(&bar.exp, ctx.max_exp_cnt);
 594          if (counters & counter_vs && (bar_ev & vs_events) == event)
 595             update_barrier_counter(&bar.vs, ctx.max_vs_cnt);
 596       }
 597    }
 598 }
 599
 600 void update_counters(wait_ctx& ctx, wait_event event, barrier_interaction barrier=barrier_none)
 601 {
 602    uint8_t counters = get_counters_for_event(event);
 603
 604    if (counters & counter_lgkm && ctx.lgkm_cnt <= ctx.max_lgkm_cnt)
 605       ctx.lgkm_cnt++;
 606    if (counters & counter_vm && ctx.vm_cnt <= ctx.max_vm_cnt)
 607       ctx.vm_cnt++;
 608    if (counters & counter_exp && ctx.exp_cnt <= ctx.max_exp_cnt)
 609       ctx.exp_cnt++;
 610    if (counters & counter_vs && ctx.vs_cnt <= ctx.max_vs_cnt)
 611       ctx.vs_cnt++;
 612
 613    update_barrier_imm(ctx, counters, event, barrier);
 614
 615    if (ctx.unordered_events & event)
 616       return;
 617
 618    if (ctx.pending_flat_lgkm)
 619       counters &= ~counter_lgkm;
 620    if (ctx.pending_flat_vm)
 621       counters &= ~counter_vm;
 622
 623    for (std::pair<const PhysReg,wait_entry>& e : ctx.gpr_map) {
 624       wait_entry& entry = e.second;
 625
 626       if (entry.events & ctx.unordered_events)
 627          continue;
 628
 629       assert(entry.events);
 630
 631       if ((counters & counter_exp) && (entry.events & exp_events) == event && entry.imm.exp < ctx.max_exp_cnt)
 632          entry.imm.exp++;
 633       if ((counters & counter_lgkm) && (entry.events & lgkm_events) == event && entry.imm.lgkm < ctx.max_lgkm_cnt)
 634          entry.imm.lgkm++;
 635       if ((counters & counter_vm) && (entry.events & vm_events) == event && entry.imm.vm < ctx.max_vm_cnt)
 636          entry.imm.vm++;
 637       if ((counters & counter_vs) && (entry.events & vs_events) == event && entry.imm.vs < ctx.max_vs_cnt)
 638          entry.imm.vs++;
 639    }
 640 }
 641
 642 void update_counters_for_flat_load(wait_ctx& ctx, barrier_interaction barrier=barrier_none)
 643 {
 644    assert(ctx.chip_class < GFX10);
 645
 646    if (ctx.lgkm_cnt <= ctx.max_lgkm_cnt)
 647       ctx.lgkm_cnt++;
 648    if (ctx.vm_cnt <= ctx.max_vm_cnt)
 649       ctx.vm_cnt++;
 650
 651    update_barrier_imm(ctx, counter_vm | counter_lgkm, event_flat, barrier);
 652
 653    for (std::pair<PhysReg,wait_entry> e : ctx.gpr_map)
 654    {
 655       if (e.second.counters & counter_vm)
 656          e.second.imm.vm = 0;
 657       if (e.second.counters & counter_lgkm)
 658          e.second.imm.lgkm = 0;
 659    }
 660    ctx.pending_flat_lgkm = true;
 661    ctx.pending_flat_vm = true;
 662 }
 663
 664 void insert_wait_entry(wait_ctx& ctx, PhysReg reg, RegClass rc, wait_event event, bool wait_on_read)
 665 {
 666    uint16_t counters = get_counters_for_event(event);
 667    wait_imm imm;
 668    if (counters & counter_lgkm)
 669       imm.lgkm = 0;
 670    if (counters & counter_vm)
 671       imm.vm = 0;
 672    if (counters & counter_exp)
 673       imm.exp = 0;
 674    if (counters & counter_vs)
 675       imm.vs = 0;
 676
 677    wait_entry new_entry(event, imm, !rc.is_linear(), wait_on_read);
 678
 679    for (unsigned i = 0; i < rc.size(); i++) {
 680       auto it = ctx.gpr_map.emplace(PhysReg{reg.reg()+i}, new_entry);
 681       if (!it.second)
 682          it.first->second.join(new_entry);
 683    }
 684
 685    if (ctx.collect_statistics) {
 686       unsigned counters_todo = counters;
 687       while (counters_todo) {
 688          unsigned i = u_bit_scan(&counters_todo);
 689          ctx.unwaited_instrs[i].insert(std::make_pair(ctx.gen_instr, 0u));
 690          for (unsigned j = 0; j < rc.size(); j++)
 691             ctx.reg_instrs[i][PhysReg{reg.reg()+j}].insert(ctx.gen_instr);
 692       }
 693    }
 694 }
 695
 696 void insert_wait_entry(wait_ctx& ctx, Operand op, wait_event event)
 697 {
 698    if (!op.isConstant() && !op.isUndefined())
 699       insert_wait_entry(ctx, op.physReg(), op.regClass(), event, false);
 700 }
 701
 702 void insert_wait_entry(wait_ctx& ctx, Definition def, wait_event event)
 703 {
 704    insert_wait_entry(ctx, def.physReg(), def.regClass(), event, true);
 705 }
 706
 707 void gen(Instruction* instr, wait_ctx& ctx)
 708 {
 709    switch (instr->format) {
 710    case Format::EXP: {
 711       Export_instruction* exp_instr = static_cast<Export_instruction*>(instr);
 712
 713       wait_event ev;
 714       if (exp_instr->dest <= 9)
 715          ev = event_exp_mrt_null;
 716       else if (exp_instr->dest <= 15)
 717          ev = event_exp_pos;
 718       else
 719          ev = event_exp_param;
 720       update_counters(ctx, ev);
 721
 722       /* insert new entries for exported vgprs */
 723       for (unsigned i = 0; i < 4; i++)
 724       {
 725          if (exp_instr->enabled_mask & (1 << i)) {
 726             unsigned idx = exp_instr->compressed ? i >> 1 : i;
 727             assert(idx < exp_instr->operands.size());
 728             insert_wait_entry(ctx, exp_instr->operands[idx], ev);
 729
 730          }
 731       }
 732       insert_wait_entry(ctx, exec, s2, ev, false);
 733       break;
 734    }
 735    case Format::FLAT: {
 736       if (ctx.chip_class < GFX10 && !instr->definitions.empty())
 737          update_counters_for_flat_load(ctx, barrier_buffer);
 738       else
 739          update_counters(ctx, event_flat, barrier_buffer);
 740
 741       if (!instr->definitions.empty())
 742          insert_wait_entry(ctx, instr->definitions[0], event_flat);
 743       break;
 744    }
 745    case Format::SMEM: {
 746       SMEM_instruction *smem = static_cast<SMEM_instruction*>(instr);
 747       update_counters(ctx, event_smem, static_cast<SMEM_instruction*>(instr)->barrier);
 748
 749       if (!instr->definitions.empty())
 750          insert_wait_entry(ctx, instr->definitions[0], event_smem);
 751       else if (ctx.chip_class >= GFX10 &&
 752                !smem->can_reorder &&
 753                smem->barrier == barrier_buffer)
 754          ctx.pending_s_buffer_store = true;
 755
 756       break;
 757    }
 758    case Format::DS: {
 759       bool gds = static_cast<DS_instruction*>(instr)->gds;
 760       update_counters(ctx, gds ? event_gds : event_lds, gds ? barrier_none : barrier_shared);
 761       if (gds)
 762          update_counters(ctx, event_gds_gpr_lock);
 763
 764       if (!instr->definitions.empty())
 765          insert_wait_entry(ctx, instr->definitions[0], gds ? event_gds : event_lds);
 766
 767       if (gds) {
 768          for (const Operand& op : instr->operands)
 769             insert_wait_entry(ctx, op, event_gds_gpr_lock);
 770          insert_wait_entry(ctx, exec, s2, event_gds_gpr_lock, false);
 771       }
 772       break;
 773    }
 774    case Format::MUBUF:
 775    case Format::MTBUF:
 776    case Format::MIMG:
 777    case Format::GLOBAL: {
 778       wait_event ev = !instr->definitions.empty() || ctx.chip_class < GFX10 ? event_vmem : event_vmem_store;
 779       update_counters(ctx, ev, get_barrier_interaction(instr));
 780
 781       if (!instr->definitions.empty())
 782          insert_wait_entry(ctx, instr->definitions[0], ev);
 783
 784       if (ctx.chip_class == GFX6 &&
 785           instr->format != Format::MIMG &&
 786           instr->operands.size() == 4) {
 787          ctx.exp_cnt++;
 788          update_counters(ctx, event_vmem_gpr_lock);
 789          insert_wait_entry(ctx, instr->operands[3], event_vmem_gpr_lock);
 790       } else if (ctx.chip_class == GFX6 &&
 791                  instr->format == Format::MIMG &&
 792                  instr->operands[1].regClass().type() == RegType::vgpr) {
 793          ctx.exp_cnt++;
 794          update_counters(ctx, event_vmem_gpr_lock);
 795          insert_wait_entry(ctx, instr->operands[1], event_vmem_gpr_lock);
 796       }
 797
 798       break;
 799    }
 800    case Format::SOPP: {
 801       if (instr->opcode == aco_opcode::s_sendmsg ||
 802           instr->opcode == aco_opcode::s_sendmsghalt)
 803          update_counters(ctx, event_sendmsg, get_barrier_interaction(instr));
 804    }
 805    default:
 806       break;
 807    }
 808 }
 809
 810 void emit_waitcnt(wait_ctx& ctx, std::vector<aco_ptr<Instruction>>& instructions, wait_imm imm)
 811 {
 812    if (imm.vs != wait_imm::unset_counter) {
 813       assert(ctx.chip_class >= GFX10);
 814       SOPK_instruction* waitcnt_vs = create_instruction<SOPK_instruction>(aco_opcode::s_waitcnt_vscnt, Format::SOPK, 0, 1);
 815       waitcnt_vs->definitions[0] = Definition(sgpr_null, s1);
 816       waitcnt_vs->imm = imm.vs;
 817       instructions.emplace_back(waitcnt_vs);
 818       imm.vs = wait_imm::unset_counter;
 819    }
 820    if (!imm.empty()) {
 821       SOPP_instruction* waitcnt = create_instruction<SOPP_instruction>(aco_opcode::s_waitcnt, Format::SOPP, 0, 0);
 822       waitcnt->imm = imm.pack(ctx.chip_class);
 823       waitcnt->block = -1;
 824       instructions.emplace_back(waitcnt);
 825    }
 826 }
 827
 828 void handle_block(Program *program, Block& block, wait_ctx& ctx)
 829 {
 830    std::vector<aco_ptr<Instruction>> new_instructions;
 831
 832    wait_imm queued_imm;
 833
 834    ctx.collect_statistics = program->collect_statistics;
 835
 836    for (aco_ptr<Instruction>& instr : block.instructions) {
 837       bool is_wait = !parse_wait_instr(ctx, instr.get()).empty();
 838
 839       queued_imm.combine(kill(instr.get(), ctx));
 840
 841       ctx.gen_instr = instr.get();
 842       gen(instr.get(), ctx);
 843
 844       if (instr->format != Format::PSEUDO_BARRIER && !is_wait) {
 845          if (!queued_imm.empty()) {
 846             emit_waitcnt(ctx, new_instructions, queued_imm);
 847             queued_imm = wait_imm();
 848          }
 849          new_instructions.emplace_back(std::move(instr));
 850
 851          if (ctx.collect_statistics)
 852             ctx.advance_unwaited_instrs();
 853       }
 854    }
 855
 856    if (!queued_imm.empty())
 857       emit_waitcnt(ctx, new_instructions, queued_imm);
 858
 859    block.instructions.swap(new_instructions);
 860 }
 861
 862 } /* end namespace */
 863
 864 static uint32_t calculate_score(std::vector<wait_ctx> &ctx_vec, uint32_t event_mask)
 865 {
 866    double result = 0.0;
 867    unsigned num_waits = 0;
 868    while (event_mask) {
 869       unsigned event_index = u_bit_scan(&event_mask);
 870       for (const wait_ctx &ctx : ctx_vec) {
 871          for (unsigned dist : ctx.wait_distances[event_index]) {
 872             double score = dist;
 873             /* for many events, excessive distances provide little benefit, so
 874              * decrease the score in that case. */
 875             double threshold = INFINITY;
 876             double inv_strength = 0.000001;
 877             switch (1 << event_index) {
 878             case event_smem:
 879                threshold = 70.0;
 880                inv_strength = 75.0;
 881                break;
 882             case event_vmem:
 883             case event_vmem_store:
 884             case event_flat:
 885                threshold = 230.0;
 886                inv_strength = 150.0;
 887                break;
 888             case event_lds:
 889                threshold = 16.0;
 890                break;
 891             default:
 892                break;
 893             }
 894             if (score > threshold) {
 895                score -= threshold;
 896                score = threshold + score / (1.0 + score / inv_strength);
 897             }
 898
 899             /* we don't want increases in high scores to hide decreases in low scores,
 900              * so raise to the power of 0.1 before averaging. */
 901             result += pow(score, 0.1);
 902             num_waits++;
 903          }
 904       }
 905    }
 906    return round(pow(result / num_waits, 10.0) * 10.0);
 907 }
 908
 909 void insert_wait_states(Program* program)
 910 {
 911    /* per BB ctx */
 912    std::vector<bool> done(program->blocks.size());
 913    std::vector<wait_ctx> in_ctx(program->blocks.size(), wait_ctx(program));
 914    std::vector<wait_ctx> out_ctx(program->blocks.size(), wait_ctx(program));
 915
 916    std::stack<unsigned> loop_header_indices;
 917    unsigned loop_progress = 0;
 918
 919    for (unsigned i = 0; i < program->blocks.size();) {
 920       Block& current = program->blocks[i++];
 921       wait_ctx ctx = in_ctx[current.index];
 922
 923       if (current.kind & block_kind_loop_header) {
 924          loop_header_indices.push(current.index);
 925       } else if (current.kind & block_kind_loop_exit) {
 926          bool repeat = false;
 927          if (loop_progress == loop_header_indices.size()) {
 928             i = loop_header_indices.top();
 929             repeat = true;
 930          }
 931          loop_header_indices.pop();
 932          loop_progress = std::min<unsigned>(loop_progress, loop_header_indices.size());
 933          if (repeat)
 934             continue;
 935       }
 936
 937       bool changed = false;
 938       for (unsigned b : current.linear_preds)
 939          changed |= ctx.join(&out_ctx[b], false);
 940       for (unsigned b : current.logical_preds)
 941          changed |= ctx.join(&out_ctx[b], true);
 942
 943       if (done[current.index] && !changed) {
 944          in_ctx[current.index] = std::move(ctx);
 945          continue;
 946       } else {
 947          in_ctx[current.index] = ctx;
 948       }
 949
 950       if (current.instructions.empty()) {
 951          out_ctx[current.index] = std::move(ctx);
 952          continue;
 953       }
 954
 955       loop_progress = std::max<unsigned>(loop_progress, current.loop_nest_depth);
 956       done[current.index] = true;
 957
 958       handle_block(program, current, ctx);
 959
 960       out_ctx[current.index] = std::move(ctx);
 961    }
 962
 963    if (program->collect_statistics) {
 964       program->statistics[statistic_vmem_score] =
 965          calculate_score(out_ctx, event_vmem | event_flat | event_vmem_store);
 966       program->statistics[statistic_smem_score] =
 967          calculate_score(out_ctx, event_smem);
 968    }
 969 }
 970
 971 }
 972