src/amd/compiler/aco_insert_waitcnt.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <algorithm>
  26 #include <map>
  27 #include <stack>
  28
  29 #include "aco_ir.h"
  30 #include "vulkan/radv_shader.h"
  31
  32 namespace aco {
  33
  34 namespace {
  35
  36 /**
  37  * The general idea of this pass is:
  38  * The CFG is traversed in reverse postorder (forward) and loops are processed
  39  * several times until no progress is made.
  40  * Per BB two wait_ctx is maintained: an in-context and out-context.
  41  * The in-context is the joined out-contexts of the predecessors.
  42  * The context contains a map: gpr -> wait_entry
  43  * consisting of the information about the cnt values to be waited for.
  44  * Note: After merge-nodes, it might occur that for the same register
  45  *       multiple cnt values are to be waited for.
  46  *
  47  * The values are updated according to the encountered instructions:
  48  * - additional events increment the counter of waits of the same type
  49  * - or erase gprs with counters higher than to be waited for.
  50  */
  51
  52 // TODO: do a more clever insertion of wait_cnt (lgkm_cnt) when there is a load followed by a use of a previous load
  53
  54 /* Instructions of the same event will finish in-order except for smem
  55  * and maybe flat. Instructions of different events may not finish in-order. */
  56 enum wait_event : uint16_t {
  57    event_smem = 1 << 0,
  58    event_lds = 1 << 1,
  59    event_gds = 1 << 2,
  60    event_vmem = 1 << 3,
  61    event_vmem_store = 1 << 4, /* GFX10+ */
  62    event_flat = 1 << 5,
  63    event_exp_pos = 1 << 6,
  64    event_exp_param = 1 << 7,
  65    event_exp_mrt_null = 1 << 8,
  66    event_gds_gpr_lock = 1 << 9,
  67    event_vmem_gpr_lock = 1 << 10,
  68    event_sendmsg = 1 << 11,
  69 };
  70
  71 enum counter_type : uint8_t {
  72    counter_exp = 1 << 0,
  73    counter_lgkm = 1 << 1,
  74    counter_vm = 1 << 2,
  75    counter_vs = 1 << 3,
  76 };
  77
  78 static const uint16_t exp_events = event_exp_pos | event_exp_param | event_exp_mrt_null | event_gds_gpr_lock | event_vmem_gpr_lock;
  79 static const uint16_t lgkm_events = event_smem | event_lds | event_gds | event_flat | event_sendmsg;
  80 static const uint16_t vm_events = event_vmem | event_flat;
  81 static const uint16_t vs_events = event_vmem_store;
  82
  83 uint8_t get_counters_for_event(wait_event ev)
  84 {
  85    switch (ev) {
  86    case event_smem:
  87    case event_lds:
  88    case event_gds:
  89    case event_sendmsg:
  90       return counter_lgkm;
  91    case event_vmem:
  92       return counter_vm;
  93    case event_vmem_store:
  94       return counter_vs;
  95    case event_flat:
  96       return counter_vm | counter_lgkm;
  97    case event_exp_pos:
  98    case event_exp_param:
  99    case event_exp_mrt_null:
 100    case event_gds_gpr_lock:
 101    case event_vmem_gpr_lock:
 102       return counter_exp;
 103    default:
 104       return 0;
 105    }
 106 }
 107
 108 struct wait_imm {
 109    static const uint8_t unset_counter = 0xff;
 110
 111    uint8_t vm;
 112    uint8_t exp;
 113    uint8_t lgkm;
 114    uint8_t vs;
 115
 116    wait_imm() :
 117       vm(unset_counter), exp(unset_counter), lgkm(unset_counter), vs(unset_counter) {}
 118    wait_imm(uint16_t vm_, uint16_t exp_, uint16_t lgkm_, uint16_t vs_) :
 119       vm(vm_), exp(exp_), lgkm(lgkm_), vs(vs_) {}
 120
 121    wait_imm(enum chip_class chip, uint16_t packed) : vs(unset_counter)
 122    {
 123       vm = packed & 0xf;
 124       if (chip >= GFX9)
 125          vm |= (packed >> 10) & 0x30;
 126
 127       exp = (packed >> 4) & 0x7;
 128
 129       lgkm = (packed >> 8) & 0xf;
 130       if (chip >= GFX10)
 131          lgkm |= (packed >> 8) & 0x30;
 132    }
 133
 134    uint16_t pack(enum chip_class chip) const
 135    {
 136       uint16_t imm = 0;
 137       assert(exp == unset_counter || exp <= 0x7);
 138       switch (chip) {
 139       case GFX10:
 140          assert(lgkm == unset_counter || lgkm <= 0x3f);
 141          assert(vm == unset_counter || vm <= 0x3f);
 142          imm = ((vm & 0x30) << 10) | ((lgkm & 0x3f) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
 143          break;
 144       case GFX9:
 145          assert(lgkm == unset_counter || lgkm <= 0xf);
 146          assert(vm == unset_counter || vm <= 0x3f);
 147          imm = ((vm & 0x30) << 10) | ((lgkm & 0xf) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
 148          break;
 149       default:
 150          assert(lgkm == unset_counter || lgkm <= 0xf);
 151          assert(vm == unset_counter || vm <= 0xf);
 152          imm = ((lgkm & 0xf) << 8) | ((exp & 0x7) << 4) | (vm & 0xf);
 153          break;
 154       }
 155       if (chip < GFX9 && vm == wait_imm::unset_counter)
 156          imm |= 0xc000; /* should have no effect on pre-GFX9 and now we won't have to worry about the architecture when interpreting the immediate */
 157       if (chip < GFX10 && lgkm == wait_imm::unset_counter)
 158          imm |= 0x3000; /* should have no effect on pre-GFX10 and now we won't have to worry about the architecture when interpreting the immediate */
 159       return imm;
 160    }
 161
 162    bool combine(const wait_imm& other)
 163    {
 164       bool changed = other.vm < vm || other.exp < exp || other.lgkm < lgkm || other.vs < vs;
 165       vm = std::min(vm, other.vm);
 166       exp = std::min(exp, other.exp);
 167       lgkm = std::min(lgkm, other.lgkm);
 168       vs = std::min(vs, other.vs);
 169       return changed;
 170    }
 171
 172    bool empty() const
 173    {
 174       return vm == unset_counter && exp == unset_counter &&
 175              lgkm == unset_counter && vs == unset_counter;
 176    }
 177 };
 178
 179 struct wait_entry {
 180    wait_imm imm;
 181    uint16_t events; /* use wait_event notion */
 182    uint8_t counters; /* use counter_type notion */
 183    bool wait_on_read:1;
 184    bool logical:1;
 185
 186    wait_entry(wait_event event, wait_imm imm, bool logical, bool wait_on_read)
 187            : imm(imm), events(event), counters(get_counters_for_event(event)),
 188              wait_on_read(wait_on_read), logical(logical) {}
 189
 190    bool join(const wait_entry& other)
 191    {
 192       bool changed = (other.events & ~events) ||
 193                      (other.counters & ~counters) ||
 194                      (other.wait_on_read && !wait_on_read);
 195       events |= other.events;
 196       counters |= other.counters;
 197       changed |= imm.combine(other.imm);
 198       wait_on_read = wait_on_read || other.wait_on_read;
 199       assert(logical == other.logical);
 200       return changed;
 201    }
 202
 203    void remove_counter(counter_type counter)
 204    {
 205       counters &= ~counter;
 206
 207       if (counter == counter_lgkm) {
 208          imm.lgkm = wait_imm::unset_counter;
 209          events &= ~(event_smem | event_lds | event_gds | event_sendmsg);
 210       }
 211
 212       if (counter == counter_vm) {
 213          imm.vm = wait_imm::unset_counter;
 214          events &= ~event_vmem;
 215       }
 216
 217       if (counter == counter_exp) {
 218          imm.exp = wait_imm::unset_counter;
 219          events &= ~(event_exp_pos | event_exp_param | event_exp_mrt_null | event_gds_gpr_lock | event_vmem_gpr_lock);
 220       }
 221
 222       if (counter == counter_vs) {
 223          imm.vs = wait_imm::unset_counter;
 224          events &= ~event_vmem_store;
 225       }
 226
 227       if (!(counters & counter_lgkm) && !(counters & counter_vm))
 228          events &= ~event_flat;
 229    }
 230 };
 231
 232 struct wait_ctx {
 233    Program *program;
 234    enum chip_class chip_class;
 235    uint16_t max_vm_cnt;
 236    uint16_t max_exp_cnt;
 237    uint16_t max_lgkm_cnt;
 238    uint16_t max_vs_cnt;
 239    uint16_t unordered_events = event_smem | event_flat;
 240
 241    uint8_t vm_cnt = 0;
 242    uint8_t exp_cnt = 0;
 243    uint8_t lgkm_cnt = 0;
 244    uint8_t vs_cnt = 0;
 245    bool pending_flat_lgkm = false;
 246    bool pending_flat_vm = false;
 247    bool pending_s_buffer_store = false; /* GFX10 workaround */
 248
 249    wait_imm barrier_imm[barrier_count];
 250
 251    std::map<PhysReg,wait_entry> gpr_map;
 252
 253    wait_ctx() {}
 254    wait_ctx(Program *program_)
 255            : program(program_),
 256              chip_class(program_->chip_class),
 257              max_vm_cnt(program_->chip_class >= GFX9 ? 62 : 14),
 258              max_exp_cnt(6),
 259              max_lgkm_cnt(program_->chip_class >= GFX10 ? 62 : 14),
 260              max_vs_cnt(program_->chip_class >= GFX10 ? 62 : 0),
 261              unordered_events(event_smem | (program_->chip_class < GFX10 ? event_flat : 0)) {}
 262
 263    bool join(const wait_ctx* other, bool logical)
 264    {
 265       bool changed = other->exp_cnt > exp_cnt ||
 266                      other->vm_cnt > vm_cnt ||
 267                      other->lgkm_cnt > lgkm_cnt ||
 268                      other->vs_cnt > vs_cnt ||
 269                      (other->pending_flat_lgkm && !pending_flat_lgkm) ||
 270                      (other->pending_flat_vm && !pending_flat_vm);
 271
 272       exp_cnt = std::max(exp_cnt, other->exp_cnt);
 273       vm_cnt = std::max(vm_cnt, other->vm_cnt);
 274       lgkm_cnt = std::max(lgkm_cnt, other->lgkm_cnt);
 275       vs_cnt = std::max(vs_cnt, other->vs_cnt);
 276       pending_flat_lgkm |= other->pending_flat_lgkm;
 277       pending_flat_vm |= other->pending_flat_vm;
 278       pending_s_buffer_store |= other->pending_s_buffer_store;
 279
 280       for (std::pair<PhysReg,wait_entry> entry : other->gpr_map)
 281       {
 282          std::map<PhysReg,wait_entry>::iterator it = gpr_map.find(entry.first);
 283          if (entry.second.logical != logical)
 284             continue;
 285
 286          if (it != gpr_map.end()) {
 287             changed |= it->second.join(entry.second);
 288          } else {
 289             gpr_map.insert(entry);
 290             changed = true;
 291          }
 292       }
 293
 294       for (unsigned i = 0; i < barrier_count; i++)
 295          changed |= barrier_imm[i].combine(other->barrier_imm[i]);
 296
 297       return changed;
 298    }
 299 };
 300
 301 wait_imm check_instr(Instruction* instr, wait_ctx& ctx)
 302 {
 303    wait_imm wait;
 304
 305    for (const Operand op : instr->operands) {
 306       if (op.isConstant() || op.isUndefined())
 307          continue;
 308
 309       /* check consecutively read gprs */
 310       for (unsigned j = 0; j < op.size(); j++) {
 311          PhysReg reg{op.physReg() + j};
 312          std::map<PhysReg,wait_entry>::iterator it = ctx.gpr_map.find(reg);
 313          if (it == ctx.gpr_map.end() || !it->second.wait_on_read)
 314             continue;
 315
 316          wait.combine(it->second.imm);
 317       }
 318    }
 319
 320    for (const Definition& def : instr->definitions) {
 321       /* check consecutively written gprs */
 322       for (unsigned j = 0; j < def.getTemp().size(); j++)
 323       {
 324          PhysReg reg{def.physReg() + j};
 325
 326          std::map<PhysReg,wait_entry>::iterator it = ctx.gpr_map.find(reg);
 327          if (it == ctx.gpr_map.end())
 328             continue;
 329
 330          /* Vector Memory reads and writes return in the order they were issued */
 331          if (instr->isVMEM() && ((it->second.events & vm_events) == event_vmem)) {
 332             it->second.remove_counter(counter_vm);
 333             if (!it->second.counters)
 334                it = ctx.gpr_map.erase(it);
 335             continue;
 336          }
 337
 338          /* LDS reads and writes return in the order they were issued. same for GDS */
 339          if (instr->format == Format::DS) {
 340             bool gds = static_cast<DS_instruction*>(instr)->gds;
 341             if ((it->second.events & lgkm_events) == (gds ? event_gds : event_lds)) {
 342                it->second.remove_counter(counter_lgkm);
 343                if (!it->second.counters)
 344                   it = ctx.gpr_map.erase(it);
 345                continue;
 346             }
 347          }
 348
 349          wait.combine(it->second.imm);
 350       }
 351    }
 352
 353    return wait;
 354 }
 355
 356 wait_imm parse_wait_instr(wait_ctx& ctx, Instruction *instr)
 357 {
 358    if (instr->opcode == aco_opcode::s_waitcnt_vscnt &&
 359        instr->definitions[0].physReg() == sgpr_null) {
 360       wait_imm imm;
 361       imm.vs = std::min<uint8_t>(imm.vs, static_cast<SOPK_instruction*>(instr)->imm);
 362       return imm;
 363    } else if (instr->opcode == aco_opcode::s_waitcnt) {
 364       return wait_imm(ctx.chip_class, static_cast<SOPP_instruction*>(instr)->imm);
 365    }
 366    return wait_imm();
 367 }
 368
 369 wait_imm kill(Instruction* instr, wait_ctx& ctx)
 370 {
 371    wait_imm imm;
 372    if (ctx.exp_cnt || ctx.vm_cnt || ctx.lgkm_cnt)
 373       imm.combine(check_instr(instr, ctx));
 374
 375    imm.combine(parse_wait_instr(ctx, instr));
 376
 377
 378    /* It's required to wait for scalar stores before "writing back" data.
 379     * It shouldn't cost anything anyways since we're about to do s_endpgm.
 380     */
 381    if (ctx.lgkm_cnt && instr->opcode == aco_opcode::s_dcache_wb) {
 382       assert(ctx.chip_class >= GFX8);
 383       imm.lgkm = 0;
 384    }
 385
 386    if (ctx.chip_class >= GFX10) {
 387       /* GFX10: A store followed by a load at the same address causes a problem because
 388        * the load doesn't load the correct values unless we wait for the store first.
 389        * This is NOT mitigated by an s_nop.
 390        *
 391        * TODO: Refine this when we have proper alias analysis.
 392        */
 393       SMEM_instruction *smem = static_cast<SMEM_instruction *>(instr);
 394       if (ctx.pending_s_buffer_store &&
 395           !smem->definitions.empty() &&
 396           !smem->can_reorder && smem->barrier == barrier_buffer) {
 397          imm.lgkm = 0;
 398       }
 399    }
 400
 401    if (instr->format == Format::PSEUDO_BARRIER) {
 402       uint32_t workgroup_size = UINT32_MAX;
 403       if (ctx.program->stage & sw_cs) {
 404          unsigned* bsize = ctx.program->info->cs.block_size;
 405          workgroup_size = bsize[0] * bsize[1] * bsize[2];
 406       }
 407       switch (instr->opcode) {
 408       case aco_opcode::p_memory_barrier_common:
 409          imm.combine(ctx.barrier_imm[ffs(barrier_atomic) - 1]);
 410          imm.combine(ctx.barrier_imm[ffs(barrier_buffer) - 1]);
 411          imm.combine(ctx.barrier_imm[ffs(barrier_image) - 1]);
 412          if (workgroup_size > ctx.program->wave_size)
 413             imm.combine(ctx.barrier_imm[ffs(barrier_shared) - 1]);
 414          break;
 415       case aco_opcode::p_memory_barrier_atomic:
 416          imm.combine(ctx.barrier_imm[ffs(barrier_atomic) - 1]);
 417          break;
 418       /* see comment in aco_scheduler.cpp's can_move_instr() on why these barriers are merged */
 419       case aco_opcode::p_memory_barrier_buffer:
 420       case aco_opcode::p_memory_barrier_image:
 421          imm.combine(ctx.barrier_imm[ffs(barrier_buffer) - 1]);
 422          imm.combine(ctx.barrier_imm[ffs(barrier_image) - 1]);
 423          break;
 424       case aco_opcode::p_memory_barrier_shared:
 425          if (workgroup_size > ctx.program->wave_size)
 426             imm.combine(ctx.barrier_imm[ffs(barrier_shared) - 1]);
 427          break;
 428       case aco_opcode::p_memory_barrier_gs_data:
 429          imm.combine(ctx.barrier_imm[ffs(barrier_gs_data) - 1]);
 430          break;
 431       case aco_opcode::p_memory_barrier_gs_sendmsg:
 432          imm.combine(ctx.barrier_imm[ffs(barrier_gs_sendmsg) - 1]);
 433          break;
 434       default:
 435          assert(false);
 436          break;
 437       }
 438    }
 439
 440    if (!imm.empty()) {
 441       if (ctx.pending_flat_vm && imm.vm != wait_imm::unset_counter)
 442          imm.vm = 0;
 443       if (ctx.pending_flat_lgkm && imm.lgkm != wait_imm::unset_counter)
 444          imm.lgkm = 0;
 445
 446       /* reset counters */
 447       ctx.exp_cnt = std::min(ctx.exp_cnt, imm.exp);
 448       ctx.vm_cnt = std::min(ctx.vm_cnt, imm.vm);
 449       ctx.lgkm_cnt = std::min(ctx.lgkm_cnt, imm.lgkm);
 450       ctx.vs_cnt = std::min(ctx.vs_cnt, imm.vs);
 451
 452       /* update barrier wait imms */
 453       for (unsigned i = 0; i < barrier_count; i++) {
 454          wait_imm& bar = ctx.barrier_imm[i];
 455          if (bar.exp != wait_imm::unset_counter && imm.exp <= bar.exp)
 456             bar.exp = wait_imm::unset_counter;
 457          if (bar.vm != wait_imm::unset_counter && imm.vm <= bar.vm)
 458             bar.vm = wait_imm::unset_counter;
 459          if (bar.lgkm != wait_imm::unset_counter && imm.lgkm <= bar.lgkm)
 460             bar.lgkm = wait_imm::unset_counter;
 461          if (bar.vs != wait_imm::unset_counter && imm.vs <= bar.vs)
 462             bar.vs = wait_imm::unset_counter;
 463       }
 464
 465       /* remove all gprs with higher counter from map */
 466       std::map<PhysReg,wait_entry>::iterator it = ctx.gpr_map.begin();
 467       while (it != ctx.gpr_map.end())
 468       {
 469          if (imm.exp != wait_imm::unset_counter && imm.exp <= it->second.imm.exp)
 470             it->second.remove_counter(counter_exp);
 471          if (imm.vm != wait_imm::unset_counter && imm.vm <= it->second.imm.vm)
 472             it->second.remove_counter(counter_vm);
 473          if (imm.lgkm != wait_imm::unset_counter && imm.lgkm <= it->second.imm.lgkm)
 474             it->second.remove_counter(counter_lgkm);
 475          if (imm.lgkm != wait_imm::unset_counter && imm.vs <= it->second.imm.vs)
 476             it->second.remove_counter(counter_vs);
 477          if (!it->second.counters)
 478             it = ctx.gpr_map.erase(it);
 479          else
 480             it++;
 481       }
 482    }
 483
 484    if (imm.vm == 0)
 485       ctx.pending_flat_vm = false;
 486    if (imm.lgkm == 0) {
 487       ctx.pending_flat_lgkm = false;
 488       ctx.pending_s_buffer_store = false;
 489    }
 490
 491    return imm;
 492 }
 493
 494 void update_barrier_imm(wait_ctx& ctx, uint8_t counters, barrier_interaction barrier)
 495 {
 496    unsigned barrier_index = ffs(barrier) - 1;
 497    for (unsigned i = 0; i < barrier_count; i++) {
 498       wait_imm& bar = ctx.barrier_imm[i];
 499       if (i == barrier_index) {
 500          if (counters & counter_lgkm)
 501             bar.lgkm = 0;
 502          if (counters & counter_vm)
 503             bar.vm = 0;
 504          if (counters & counter_exp)
 505             bar.exp = 0;
 506          if (counters & counter_vs)
 507             bar.vs = 0;
 508       } else {
 509          if (counters & counter_lgkm && bar.lgkm != wait_imm::unset_counter && bar.lgkm < ctx.max_lgkm_cnt)
 510             bar.lgkm++;
 511          if (counters & counter_vm && bar.vm != wait_imm::unset_counter && bar.vm < ctx.max_vm_cnt)
 512             bar.vm++;
 513          if (counters & counter_exp && bar.exp != wait_imm::unset_counter && bar.exp < ctx.max_exp_cnt)
 514             bar.exp++;
 515          if (counters & counter_vs && bar.vs != wait_imm::unset_counter && bar.vs < ctx.max_vs_cnt)
 516             bar.vs++;
 517       }
 518    }
 519 }
 520
 521 void update_counters(wait_ctx& ctx, wait_event event, barrier_interaction barrier=barrier_none)
 522 {
 523    uint8_t counters = get_counters_for_event(event);
 524
 525    if (counters & counter_lgkm && ctx.lgkm_cnt <= ctx.max_lgkm_cnt)
 526       ctx.lgkm_cnt++;
 527    if (counters & counter_vm && ctx.vm_cnt <= ctx.max_vm_cnt)
 528       ctx.vm_cnt++;
 529    if (counters & counter_exp && ctx.exp_cnt <= ctx.max_exp_cnt)
 530       ctx.exp_cnt++;
 531    if (counters & counter_vs && ctx.vs_cnt <= ctx.max_vs_cnt)
 532       ctx.vs_cnt++;
 533
 534    update_barrier_imm(ctx, counters, barrier);
 535
 536    if (ctx.unordered_events & event)
 537       return;
 538
 539    if (ctx.pending_flat_lgkm)
 540       counters &= ~counter_lgkm;
 541    if (ctx.pending_flat_vm)
 542       counters &= ~counter_vm;
 543
 544    for (std::pair<const PhysReg,wait_entry>& e : ctx.gpr_map) {
 545       wait_entry& entry = e.second;
 546
 547       if (entry.events & ctx.unordered_events)
 548          continue;
 549
 550       assert(entry.events);
 551
 552       if ((counters & counter_exp) && (entry.events & exp_events) == event && entry.imm.exp < ctx.max_exp_cnt)
 553          entry.imm.exp++;
 554       if ((counters & counter_lgkm) && (entry.events & lgkm_events) == event && entry.imm.lgkm < ctx.max_lgkm_cnt)
 555          entry.imm.lgkm++;
 556       if ((counters & counter_vm) && (entry.events & vm_events) == event && entry.imm.vm < ctx.max_vm_cnt)
 557          entry.imm.vm++;
 558       if ((counters & counter_vs) && (entry.events & vs_events) == event && entry.imm.vs < ctx.max_vs_cnt)
 559          entry.imm.vs++;
 560    }
 561 }
 562
 563 void update_counters_for_flat_load(wait_ctx& ctx, barrier_interaction barrier=barrier_none)
 564 {
 565    assert(ctx.chip_class < GFX10);
 566
 567    if (ctx.lgkm_cnt <= ctx.max_lgkm_cnt)
 568       ctx.lgkm_cnt++;
 569    if (ctx.vm_cnt <= ctx.max_vm_cnt)
 570       ctx.vm_cnt++;
 571
 572    update_barrier_imm(ctx, counter_vm | counter_lgkm, barrier);
 573
 574    for (std::pair<PhysReg,wait_entry> e : ctx.gpr_map)
 575    {
 576       if (e.second.counters & counter_vm)
 577          e.second.imm.vm = 0;
 578       if (e.second.counters & counter_lgkm)
 579          e.second.imm.lgkm = 0;
 580    }
 581    ctx.pending_flat_lgkm = true;
 582    ctx.pending_flat_vm = true;
 583 }
 584
 585 void insert_wait_entry(wait_ctx& ctx, PhysReg reg, RegClass rc, wait_event event, bool wait_on_read)
 586 {
 587    uint16_t counters = get_counters_for_event(event);
 588    wait_imm imm;
 589    if (counters & counter_lgkm)
 590       imm.lgkm = 0;
 591    if (counters & counter_vm)
 592       imm.vm = 0;
 593    if (counters & counter_exp)
 594       imm.exp = 0;
 595    if (counters & counter_vs)
 596       imm.vs = 0;
 597
 598    wait_entry new_entry(event, imm, !rc.is_linear(), wait_on_read);
 599
 600    for (unsigned i = 0; i < rc.size(); i++) {
 601       auto it = ctx.gpr_map.emplace(PhysReg{reg.reg+i}, new_entry);
 602       if (!it.second)
 603          it.first->second.join(new_entry);
 604    }
 605 }
 606
 607 void insert_wait_entry(wait_ctx& ctx, Operand op, wait_event event)
 608 {
 609    if (!op.isConstant() && !op.isUndefined())
 610       insert_wait_entry(ctx, op.physReg(), op.regClass(), event, false);
 611 }
 612
 613 void insert_wait_entry(wait_ctx& ctx, Definition def, wait_event event)
 614 {
 615    insert_wait_entry(ctx, def.physReg(), def.regClass(), event, true);
 616 }
 617
 618 void gen(Instruction* instr, wait_ctx& ctx)
 619 {
 620    switch (instr->format) {
 621    case Format::EXP: {
 622       Export_instruction* exp_instr = static_cast<Export_instruction*>(instr);
 623
 624       wait_event ev;
 625       if (exp_instr->dest <= 9)
 626          ev = event_exp_mrt_null;
 627       else if (exp_instr->dest <= 15)
 628          ev = event_exp_pos;
 629       else
 630          ev = event_exp_param;
 631       update_counters(ctx, ev);
 632
 633       /* insert new entries for exported vgprs */
 634       for (unsigned i = 0; i < 4; i++)
 635       {
 636          if (exp_instr->enabled_mask & (1 << i)) {
 637             unsigned idx = exp_instr->compressed ? i >> 1 : i;
 638             assert(idx < exp_instr->operands.size());
 639             insert_wait_entry(ctx, exp_instr->operands[idx], ev);
 640
 641          }
 642       }
 643       insert_wait_entry(ctx, exec, s2, ev, false);
 644       break;
 645    }
 646    case Format::FLAT: {
 647       if (ctx.chip_class < GFX10 && !instr->definitions.empty())
 648          update_counters_for_flat_load(ctx, barrier_buffer);
 649       else
 650          update_counters(ctx, event_flat, barrier_buffer);
 651
 652       if (!instr->definitions.empty())
 653          insert_wait_entry(ctx, instr->definitions[0], event_flat);
 654       break;
 655    }
 656    case Format::SMEM: {
 657       SMEM_instruction *smem = static_cast<SMEM_instruction*>(instr);
 658       update_counters(ctx, event_smem, static_cast<SMEM_instruction*>(instr)->barrier);
 659
 660       if (!instr->definitions.empty())
 661          insert_wait_entry(ctx, instr->definitions[0], event_smem);
 662       else if (ctx.chip_class >= GFX10 &&
 663                !smem->can_reorder &&
 664                smem->barrier == barrier_buffer)
 665          ctx.pending_s_buffer_store = true;
 666
 667       break;
 668    }
 669    case Format::DS: {
 670       bool gds = static_cast<DS_instruction*>(instr)->gds;
 671       update_counters(ctx, gds ? event_gds : event_lds, gds ? barrier_none : barrier_shared);
 672       if (gds)
 673          update_counters(ctx, event_gds_gpr_lock);
 674
 675       if (!instr->definitions.empty())
 676          insert_wait_entry(ctx, instr->definitions[0], gds ? event_gds : event_lds);
 677
 678       if (gds) {
 679          for (const Operand& op : instr->operands)
 680             insert_wait_entry(ctx, op, event_gds_gpr_lock);
 681          insert_wait_entry(ctx, exec, s2, event_gds_gpr_lock, false);
 682       }
 683       break;
 684    }
 685    case Format::MUBUF:
 686    case Format::MTBUF:
 687    case Format::MIMG:
 688    case Format::GLOBAL: {
 689       wait_event ev = !instr->definitions.empty() || ctx.chip_class < GFX10 ? event_vmem : event_vmem_store;
 690       update_counters(ctx, ev, get_barrier_interaction(instr));
 691
 692       if (!instr->definitions.empty())
 693          insert_wait_entry(ctx, instr->definitions[0], ev);
 694
 695       if (ctx.chip_class == GFX6 &&
 696           instr->format != Format::MIMG &&
 697           instr->operands.size() == 4) {
 698          ctx.exp_cnt++;
 699          update_counters(ctx, event_vmem_gpr_lock);
 700          insert_wait_entry(ctx, instr->operands[3], event_vmem_gpr_lock);
 701       } else if (ctx.chip_class == GFX6 &&
 702                  instr->format == Format::MIMG &&
 703                  instr->operands[1].regClass().type() == RegType::vgpr) {
 704          ctx.exp_cnt++;
 705          update_counters(ctx, event_vmem_gpr_lock);
 706          insert_wait_entry(ctx, instr->operands[1], event_vmem_gpr_lock);
 707       }
 708
 709       break;
 710    }
 711    case Format::SOPP: {
 712       if (instr->opcode == aco_opcode::s_sendmsg ||
 713           instr->opcode == aco_opcode::s_sendmsghalt)
 714          update_counters(ctx, event_sendmsg, get_barrier_interaction(instr));
 715    }
 716    default:
 717       break;
 718    }
 719 }
 720
 721 void emit_waitcnt(wait_ctx& ctx, std::vector<aco_ptr<Instruction>>& instructions, wait_imm imm)
 722 {
 723    if (imm.vs != wait_imm::unset_counter) {
 724       assert(ctx.chip_class >= GFX10);
 725       SOPK_instruction* waitcnt_vs = create_instruction<SOPK_instruction>(aco_opcode::s_waitcnt_vscnt, Format::SOPK, 0, 1);
 726       waitcnt_vs->definitions[0] = Definition(sgpr_null, s1);
 727       waitcnt_vs->imm = imm.vs;
 728       instructions.emplace_back(waitcnt_vs);
 729       imm.vs = wait_imm::unset_counter;
 730    }
 731    if (!imm.empty()) {
 732       SOPP_instruction* waitcnt = create_instruction<SOPP_instruction>(aco_opcode::s_waitcnt, Format::SOPP, 0, 0);
 733       waitcnt->imm = imm.pack(ctx.chip_class);
 734       waitcnt->block = -1;
 735       instructions.emplace_back(waitcnt);
 736    }
 737 }
 738
 739 void handle_block(Program *program, Block& block, wait_ctx& ctx)
 740 {
 741    std::vector<aco_ptr<Instruction>> new_instructions;
 742
 743    wait_imm queued_imm;
 744    for (aco_ptr<Instruction>& instr : block.instructions) {
 745       bool is_wait = !parse_wait_instr(ctx, instr.get()).empty();
 746
 747       queued_imm.combine(kill(instr.get(), ctx));
 748
 749       gen(instr.get(), ctx);
 750
 751       if (instr->format != Format::PSEUDO_BARRIER && !is_wait) {
 752          if (!queued_imm.empty()) {
 753             emit_waitcnt(ctx, new_instructions, queued_imm);
 754             queued_imm = wait_imm();
 755          }
 756          new_instructions.emplace_back(std::move(instr));
 757       }
 758    }
 759
 760    if (!queued_imm.empty())
 761       emit_waitcnt(ctx, new_instructions, queued_imm);
 762
 763    block.instructions.swap(new_instructions);
 764 }
 765
 766 } /* end namespace */
 767
 768 void insert_wait_states(Program* program)
 769 {
 770    /* per BB ctx */
 771    std::vector<bool> done(program->blocks.size());
 772    wait_ctx in_ctx[program->blocks.size()];
 773    wait_ctx out_ctx[program->blocks.size()];
 774    for (unsigned i = 0; i < program->blocks.size(); i++)
 775       in_ctx[i] = wait_ctx(program);
 776    std::stack<unsigned> loop_header_indices;
 777    unsigned loop_progress = 0;
 778
 779    for (unsigned i = 0; i < program->blocks.size();) {
 780       Block& current = program->blocks[i++];
 781       wait_ctx ctx = in_ctx[current.index];
 782
 783       if (current.kind & block_kind_loop_header) {
 784          loop_header_indices.push(current.index);
 785       } else if (current.kind & block_kind_loop_exit) {
 786          bool repeat = false;
 787          if (loop_progress == loop_header_indices.size()) {
 788             i = loop_header_indices.top();
 789             repeat = true;
 790          }
 791          loop_header_indices.pop();
 792          loop_progress = std::min<unsigned>(loop_progress, loop_header_indices.size());
 793          if (repeat)
 794             continue;
 795       }
 796
 797       bool changed = false;
 798       for (unsigned b : current.linear_preds)
 799          changed |= ctx.join(&out_ctx[b], false);
 800       for (unsigned b : current.logical_preds)
 801          changed |= ctx.join(&out_ctx[b], true);
 802
 803       in_ctx[current.index] = ctx;
 804
 805       if (done[current.index] && !changed)
 806          continue;
 807
 808       if (current.instructions.empty()) {
 809          out_ctx[current.index] = ctx;
 810          continue;
 811       }
 812
 813       loop_progress = std::max<unsigned>(loop_progress, current.loop_nest_depth);
 814       done[current.index] = true;
 815
 816       handle_block(program, current, ctx);
 817
 818       out_ctx[current.index] = ctx;
 819    }
 820 }
 821
 822 }
 823