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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool then_branch_divergent
;
93 static bool visit_cf_list(struct isel_context
*ctx
,
94 struct exec_list
*list
);
96 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
98 succ
->logical_preds
.emplace_back(pred_idx
);
102 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
104 succ
->linear_preds
.emplace_back(pred_idx
);
107 static void add_edge(unsigned pred_idx
, Block
*succ
)
109 add_logical_edge(pred_idx
, succ
);
110 add_linear_edge(pred_idx
, succ
);
113 static void append_logical_start(Block
*b
)
115 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
118 static void append_logical_end(Block
*b
)
120 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
123 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
125 assert(ctx
->allocated
[def
->index
].id());
126 return ctx
->allocated
[def
->index
];
129 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
130 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
132 Builder
bld(ctx
->program
, ctx
->block
);
133 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
134 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
136 if (ctx
->program
->wave_size
== 32) {
139 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
144 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
146 Builder
bld(ctx
->program
, ctx
->block
);
149 dst
= bld
.tmp(src
.regClass());
151 assert(src
.size() == dst
.size());
153 if (ctx
->stage
!= fragment_fs
) {
157 bld
.copy(Definition(dst
), src
);
161 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
162 ctx
->program
->needs_wqm
|= program_needs_wqm
;
166 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
168 if (index
.regClass() == s1
)
169 return bld
.readlane(bld
.def(s1
), data
, index
);
171 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
173 /* Currently not implemented on GFX6-7 */
174 assert(ctx
->options
->chip_class
>= GFX8
);
176 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
177 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
180 /* GFX10, wave64 mode:
181 * The bpermute instruction is limited to half-wave operation, which means that it can't
182 * properly support subgroup shuffle like older generations (or wave32 mode), so we
185 if (!ctx
->has_gfx10_wave64_bpermute
) {
186 ctx
->has_gfx10_wave64_bpermute
= true;
187 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
188 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
191 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
192 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
193 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
194 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
196 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
197 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
200 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
202 if (val
.type() == RegType::sgpr
) {
203 Builder
bld(ctx
->program
, ctx
->block
);
204 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
206 assert(val
.type() == RegType::vgpr
);
210 //assumes a != 0xffffffff
211 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
214 Builder
bld(ctx
->program
, ctx
->block
);
216 if (util_is_power_of_two_or_zero(b
)) {
217 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
221 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
223 assert(info
.multiplier
<= 0xffffffff);
225 bool pre_shift
= info
.pre_shift
!= 0;
226 bool increment
= info
.increment
!= 0;
227 bool multiply
= true;
228 bool post_shift
= info
.post_shift
!= 0;
230 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
231 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
235 Temp pre_shift_dst
= a
;
237 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
238 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
241 Temp increment_dst
= pre_shift_dst
;
243 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
244 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
247 Temp multiply_dst
= increment_dst
;
249 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
250 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
251 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
255 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
259 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
261 Builder
bld(ctx
->program
, ctx
->block
);
262 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
266 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
268 /* no need to extract the whole vector */
269 if (src
.regClass() == dst_rc
) {
274 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
275 Builder
bld(ctx
->program
, ctx
->block
);
276 auto it
= ctx
->allocated_vec
.find(src
.id());
277 /* the size check needs to be early because elements other than 0 may be garbage */
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f32
:
630 op
= aco_opcode::v_cmp_gt_f32
;
632 case aco_opcode::v_cmp_ge_f32
:
633 op
= aco_opcode::v_cmp_le_f32
;
635 case aco_opcode::v_cmp_lt_i32
:
636 op
= aco_opcode::v_cmp_gt_i32
;
638 case aco_opcode::v_cmp_ge_i32
:
639 op
= aco_opcode::v_cmp_le_i32
;
641 case aco_opcode::v_cmp_lt_u32
:
642 op
= aco_opcode::v_cmp_gt_u32
;
644 case aco_opcode::v_cmp_ge_u32
:
645 op
= aco_opcode::v_cmp_le_u32
;
647 case aco_opcode::v_cmp_lt_f64
:
648 op
= aco_opcode::v_cmp_gt_f64
;
650 case aco_opcode::v_cmp_ge_f64
:
651 op
= aco_opcode::v_cmp_le_f64
;
653 case aco_opcode::v_cmp_lt_i64
:
654 op
= aco_opcode::v_cmp_gt_i64
;
656 case aco_opcode::v_cmp_ge_i64
:
657 op
= aco_opcode::v_cmp_le_i64
;
659 case aco_opcode::v_cmp_lt_u64
:
660 op
= aco_opcode::v_cmp_gt_u64
;
662 case aco_opcode::v_cmp_ge_u64
:
663 op
= aco_opcode::v_cmp_le_u64
;
665 default: /* eq and ne are commutative */
672 src1
= as_vgpr(ctx
, src1
);
676 Builder
bld(ctx
->program
, ctx
->block
);
677 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
680 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
682 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
683 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
684 Builder
bld(ctx
->program
, ctx
->block
);
686 assert(dst
.regClass() == bld
.lm
);
687 assert(src0
.type() == RegType::sgpr
);
688 assert(src1
.type() == RegType::sgpr
);
689 assert(src0
.regClass() == src1
.regClass());
691 /* Emit the SALU comparison instruction */
692 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
693 /* Turn the result into a per-lane bool */
694 bool_to_vector_condition(ctx
, cmp
, dst
);
697 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
698 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
700 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
701 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
702 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
703 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
705 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
706 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
707 aco_opcode op
= use_valu
? v_op
: s_op
;
708 assert(op
!= aco_opcode::num_opcodes
);
709 assert(dst
.regClass() == ctx
->program
->lane_mask
);
712 emit_vopc_instruction(ctx
, instr
, op
, dst
);
714 emit_sopc_instruction(ctx
, instr
, op
, dst
);
717 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
719 Builder
bld(ctx
->program
, ctx
->block
);
720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
721 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
723 assert(dst
.regClass() == bld
.lm
);
724 assert(src0
.regClass() == bld
.lm
);
725 assert(src1
.regClass() == bld
.lm
);
727 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
730 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
732 Builder
bld(ctx
->program
, ctx
->block
);
733 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
734 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
735 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
737 assert(cond
.regClass() == bld
.lm
);
739 if (dst
.type() == RegType::vgpr
) {
740 aco_ptr
<Instruction
> bcsel
;
741 if (dst
.size() == 1) {
742 then
= as_vgpr(ctx
, then
);
743 els
= as_vgpr(ctx
, els
);
745 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
746 } else if (dst
.size() == 2) {
747 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
748 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
749 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
750 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
752 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
753 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
755 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
758 nir_print_instr(&instr
->instr
, stderr
);
759 fprintf(stderr
, "\n");
764 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
765 assert(dst
.regClass() == bld
.lm
);
766 assert(then
.regClass() == bld
.lm
);
767 assert(els
.regClass() == bld
.lm
);
770 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
771 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
772 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
773 assert(dst
.size() == then
.size());
774 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
775 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
777 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
778 nir_print_instr(&instr
->instr
, stderr
);
779 fprintf(stderr
, "\n");
784 /* divergent boolean bcsel
785 * this implements bcsel on bools: dst = s0 ? s1 : s2
786 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
787 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
789 if (cond
.id() != then
.id())
790 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
792 if (cond
.id() == els
.id())
793 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
795 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
796 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
799 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
800 aco_opcode op
, uint32_t undo
)
802 /* multiply by 16777216 to handle denormals */
803 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
804 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
805 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
806 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
807 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
809 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
811 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
814 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
816 if (ctx
->block
->fp_mode
.denorm32
== 0) {
817 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
821 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
824 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
826 if (ctx
->block
->fp_mode
.denorm32
== 0) {
827 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
831 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
834 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
836 if (ctx
->block
->fp_mode
.denorm32
== 0) {
837 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
841 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
844 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
846 if (ctx
->block
->fp_mode
.denorm32
== 0) {
847 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
851 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
854 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
856 if (ctx
->options
->chip_class
>= GFX7
)
857 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
859 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
860 /* TODO: create more efficient code! */
861 if (val
.type() == RegType::sgpr
)
862 val
= as_vgpr(ctx
, val
);
864 /* Split the input value. */
865 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
868 /* Extract the exponent and compute the unbiased value. */
869 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
871 /* Extract the fractional part. */
872 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
873 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
875 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
876 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
878 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
879 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
880 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
881 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
882 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
884 /* Get the sign bit. */
885 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
887 /* Decide the operation to apply depending on the unbiased exponent. */
888 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
889 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
890 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
891 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
892 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
893 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
895 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
898 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
900 if (ctx
->options
->chip_class
>= GFX7
)
901 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
903 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
904 Temp src0
= as_vgpr(ctx
, val
);
906 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
907 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
909 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
910 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
911 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
913 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
914 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
915 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
916 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
918 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
919 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
921 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
923 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
924 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
926 return add
->definitions
[0].getTemp();
929 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
931 if (!instr
->dest
.dest
.is_ssa
) {
932 fprintf(stderr
, "nir alu dst not in ssa: ");
933 nir_print_instr(&instr
->instr
, stderr
);
934 fprintf(stderr
, "\n");
937 Builder
bld(ctx
->program
, ctx
->block
);
938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
943 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
944 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
945 for (unsigned i
= 0; i
< num
; ++i
)
946 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
948 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
949 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
950 for (unsigned i
= 0; i
< num
; ++i
)
951 vec
->operands
[i
] = Operand
{elems
[i
]};
952 vec
->definitions
[0] = Definition(dst
);
953 ctx
->block
->instructions
.emplace_back(std::move(vec
));
954 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
956 // TODO: that is a bit suboptimal..
957 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
958 for (unsigned i
= 0; i
< num
- 1; ++i
)
959 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
960 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
961 for (unsigned i
= 0; i
< num
; ++i
) {
962 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
964 elems
[bit
/ 32] = elems
[i
];
966 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
967 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
968 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
972 bld
.copy(Definition(dst
), elems
[0]);
974 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
979 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
980 aco_ptr
<Instruction
> mov
;
981 if (dst
.type() == RegType::sgpr
) {
982 if (src
.type() == RegType::vgpr
)
983 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
984 else if (src
.regClass() == s1
)
985 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
986 else if (src
.regClass() == s2
)
987 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
989 unreachable("wrong src register class for nir_op_imov");
990 } else if (dst
.regClass() == v1
) {
991 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
992 } else if (dst
.regClass() == v2
) {
993 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
995 nir_print_instr(&instr
->instr
, stderr
);
996 unreachable("Should have been lowered to scalar.");
1001 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1002 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1003 assert(src
.regClass() == bld
.lm
);
1004 assert(dst
.regClass() == bld
.lm
);
1005 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1006 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1007 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1008 } else if (dst
.regClass() == v1
) {
1009 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1010 } else if (dst
.type() == RegType::sgpr
) {
1011 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1012 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1014 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1015 nir_print_instr(&instr
->instr
, stderr
);
1016 fprintf(stderr
, "\n");
1021 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1022 if (dst
.regClass() == v1
) {
1023 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1024 } else if (dst
.regClass() == s1
) {
1025 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1026 } else if (dst
.size() == 2) {
1027 Temp src0
= bld
.tmp(dst
.type(), 1);
1028 Temp src1
= bld
.tmp(dst
.type(), 1);
1029 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1031 if (dst
.regClass() == s2
) {
1032 Temp carry
= bld
.tmp(s1
);
1033 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1034 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1035 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1037 Temp lower
= bld
.tmp(v1
);
1038 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1039 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1040 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1044 nir_print_instr(&instr
->instr
, stderr
);
1045 fprintf(stderr
, "\n");
1050 if (dst
.regClass() == s1
) {
1051 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1052 } else if (dst
.regClass() == v1
) {
1053 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1054 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1056 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1057 nir_print_instr(&instr
->instr
, stderr
);
1058 fprintf(stderr
, "\n");
1062 case nir_op_isign
: {
1063 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1064 if (dst
.regClass() == s1
) {
1065 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1066 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1067 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1068 } else if (dst
.regClass() == s2
) {
1069 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1071 if (ctx
->program
->chip_class
>= GFX8
)
1072 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1074 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1075 /* SCC gets zero-extended to 64 bit */
1076 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1077 } else if (dst
.regClass() == v1
) {
1078 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1079 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1080 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1081 } else if (dst
.regClass() == v2
) {
1082 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1083 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1084 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1085 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1086 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1087 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1089 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1090 nir_print_instr(&instr
->instr
, stderr
);
1091 fprintf(stderr
, "\n");
1096 if (dst
.regClass() == v1
) {
1097 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1098 } else if (dst
.regClass() == s1
) {
1099 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1101 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1102 nir_print_instr(&instr
->instr
, stderr
);
1103 fprintf(stderr
, "\n");
1108 if (dst
.regClass() == v1
) {
1109 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1110 } else if (dst
.regClass() == s1
) {
1111 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == v1
) {
1121 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1122 } else if (dst
.regClass() == s1
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1134 } else if (dst
.regClass() == s1
) {
1135 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1144 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1145 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1146 } else if (dst
.regClass() == v1
) {
1147 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1148 } else if (dst
.regClass() == s1
) {
1149 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1150 } else if (dst
.regClass() == s2
) {
1151 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1153 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1154 nir_print_instr(&instr
->instr
, stderr
);
1155 fprintf(stderr
, "\n");
1160 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1161 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1162 } else if (dst
.regClass() == v1
) {
1163 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1164 } else if (dst
.regClass() == s1
) {
1165 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1166 } else if (dst
.regClass() == s2
) {
1167 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1169 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1170 nir_print_instr(&instr
->instr
, stderr
);
1171 fprintf(stderr
, "\n");
1176 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1177 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1178 } else if (dst
.regClass() == v1
) {
1179 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1180 } else if (dst
.regClass() == s1
) {
1181 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1182 } else if (dst
.regClass() == s2
) {
1183 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1185 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1186 nir_print_instr(&instr
->instr
, stderr
);
1187 fprintf(stderr
, "\n");
1192 if (dst
.regClass() == v1
) {
1193 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1194 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1195 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1196 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1197 } else if (dst
.regClass() == v2
) {
1198 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1199 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1200 } else if (dst
.regClass() == s2
) {
1201 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1202 } else if (dst
.regClass() == s1
) {
1203 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1205 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1206 nir_print_instr(&instr
->instr
, stderr
);
1207 fprintf(stderr
, "\n");
1212 if (dst
.regClass() == v1
) {
1213 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1214 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1215 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1216 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1217 } else if (dst
.regClass() == v2
) {
1218 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1219 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1220 } else if (dst
.regClass() == s1
) {
1221 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1222 } else if (dst
.regClass() == s2
) {
1223 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1225 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1226 nir_print_instr(&instr
->instr
, stderr
);
1227 fprintf(stderr
, "\n");
1232 if (dst
.regClass() == v1
) {
1233 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1234 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1235 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1236 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1237 } else if (dst
.regClass() == v2
) {
1238 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1239 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1240 } else if (dst
.regClass() == s1
) {
1241 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1242 } else if (dst
.regClass() == s2
) {
1243 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1245 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1246 nir_print_instr(&instr
->instr
, stderr
);
1247 fprintf(stderr
, "\n");
1251 case nir_op_find_lsb
: {
1252 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1253 if (src
.regClass() == s1
) {
1254 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1255 } else if (src
.regClass() == v1
) {
1256 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1257 } else if (src
.regClass() == s2
) {
1258 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1260 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1261 nir_print_instr(&instr
->instr
, stderr
);
1262 fprintf(stderr
, "\n");
1266 case nir_op_ufind_msb
:
1267 case nir_op_ifind_msb
: {
1268 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1269 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1270 aco_opcode op
= src
.regClass() == s2
?
1271 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1272 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1273 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1275 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1276 Operand(src
.size() * 32u - 1u), msb_rev
);
1277 Temp msb
= sub
.def(0).getTemp();
1278 Temp carry
= sub
.def(1).getTemp();
1280 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1281 } else if (src
.regClass() == v1
) {
1282 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1283 Temp msb_rev
= bld
.tmp(v1
);
1284 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1285 Temp msb
= bld
.tmp(v1
);
1286 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1287 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1289 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1290 nir_print_instr(&instr
->instr
, stderr
);
1291 fprintf(stderr
, "\n");
1295 case nir_op_bitfield_reverse
: {
1296 if (dst
.regClass() == s1
) {
1297 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1298 } else if (dst
.regClass() == v1
) {
1299 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1301 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1302 nir_print_instr(&instr
->instr
, stderr
);
1303 fprintf(stderr
, "\n");
1308 if (dst
.regClass() == s1
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1313 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1314 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1315 if (dst
.regClass() == v1
) {
1316 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1320 assert(src0
.size() == 2 && src1
.size() == 2);
1321 Temp src00
= bld
.tmp(src0
.type(), 1);
1322 Temp src01
= bld
.tmp(dst
.type(), 1);
1323 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1324 Temp src10
= bld
.tmp(src1
.type(), 1);
1325 Temp src11
= bld
.tmp(dst
.type(), 1);
1326 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1328 if (dst
.regClass() == s2
) {
1329 Temp carry
= bld
.tmp(s1
);
1330 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1331 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1332 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1333 } else if (dst
.regClass() == v2
) {
1334 Temp dst0
= bld
.tmp(v1
);
1335 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1336 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1337 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1339 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1340 nir_print_instr(&instr
->instr
, stderr
);
1341 fprintf(stderr
, "\n");
1345 case nir_op_uadd_sat
: {
1346 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1347 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1348 if (dst
.regClass() == s1
) {
1349 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1350 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1352 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1353 } else if (dst
.regClass() == v1
) {
1354 if (ctx
->options
->chip_class
>= GFX9
) {
1355 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1356 add
->operands
[0] = Operand(src0
);
1357 add
->operands
[1] = Operand(src1
);
1358 add
->definitions
[0] = Definition(dst
);
1360 ctx
->block
->instructions
.emplace_back(std::move(add
));
1362 if (src1
.regClass() != v1
)
1363 std::swap(src0
, src1
);
1364 assert(src1
.regClass() == v1
);
1365 Temp tmp
= bld
.tmp(v1
);
1366 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1367 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1370 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1371 nir_print_instr(&instr
->instr
, stderr
);
1372 fprintf(stderr
, "\n");
1376 case nir_op_uadd_carry
: {
1377 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1378 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1379 if (dst
.regClass() == s1
) {
1380 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1383 if (dst
.regClass() == v1
) {
1384 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1385 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1389 Temp src00
= bld
.tmp(src0
.type(), 1);
1390 Temp src01
= bld
.tmp(dst
.type(), 1);
1391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1392 Temp src10
= bld
.tmp(src1
.type(), 1);
1393 Temp src11
= bld
.tmp(dst
.type(), 1);
1394 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1395 if (dst
.regClass() == s2
) {
1396 Temp carry
= bld
.tmp(s1
);
1397 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1398 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1399 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1400 } else if (dst
.regClass() == v2
) {
1401 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1402 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1403 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1406 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1407 nir_print_instr(&instr
->instr
, stderr
);
1408 fprintf(stderr
, "\n");
1413 if (dst
.regClass() == s1
) {
1414 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1418 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1419 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1420 if (dst
.regClass() == v1
) {
1421 bld
.vsub32(Definition(dst
), src0
, src1
);
1425 Temp src00
= bld
.tmp(src0
.type(), 1);
1426 Temp src01
= bld
.tmp(dst
.type(), 1);
1427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1428 Temp src10
= bld
.tmp(src1
.type(), 1);
1429 Temp src11
= bld
.tmp(dst
.type(), 1);
1430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1431 if (dst
.regClass() == s2
) {
1432 Temp carry
= bld
.tmp(s1
);
1433 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1434 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1435 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1436 } else if (dst
.regClass() == v2
) {
1437 Temp lower
= bld
.tmp(v1
);
1438 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1439 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1440 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1442 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1443 nir_print_instr(&instr
->instr
, stderr
);
1444 fprintf(stderr
, "\n");
1448 case nir_op_usub_borrow
: {
1449 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1450 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1451 if (dst
.regClass() == s1
) {
1452 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1454 } else if (dst
.regClass() == v1
) {
1455 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1456 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1460 Temp src00
= bld
.tmp(src0
.type(), 1);
1461 Temp src01
= bld
.tmp(dst
.type(), 1);
1462 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1463 Temp src10
= bld
.tmp(src1
.type(), 1);
1464 Temp src11
= bld
.tmp(dst
.type(), 1);
1465 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1466 if (dst
.regClass() == s2
) {
1467 Temp borrow
= bld
.tmp(s1
);
1468 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1469 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1470 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1471 } else if (dst
.regClass() == v2
) {
1472 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1473 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1474 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1475 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1477 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1478 nir_print_instr(&instr
->instr
, stderr
);
1479 fprintf(stderr
, "\n");
1484 if (dst
.regClass() == v1
) {
1485 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1486 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1487 } else if (dst
.regClass() == s1
) {
1488 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1491 nir_print_instr(&instr
->instr
, stderr
);
1492 fprintf(stderr
, "\n");
1496 case nir_op_umul_high
: {
1497 if (dst
.regClass() == v1
) {
1498 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1499 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1500 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1501 } else if (dst
.regClass() == s1
) {
1502 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1503 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1504 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1506 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1507 nir_print_instr(&instr
->instr
, stderr
);
1508 fprintf(stderr
, "\n");
1512 case nir_op_imul_high
: {
1513 if (dst
.regClass() == v1
) {
1514 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1515 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1516 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1517 } else if (dst
.regClass() == s1
) {
1518 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1519 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1520 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1522 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1523 nir_print_instr(&instr
->instr
, stderr
);
1524 fprintf(stderr
, "\n");
1529 if (dst
.size() == 1) {
1530 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1531 } else if (dst
.size() == 2) {
1532 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1533 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1535 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1536 nir_print_instr(&instr
->instr
, stderr
);
1537 fprintf(stderr
, "\n");
1542 if (dst
.size() == 1) {
1543 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1544 } else if (dst
.size() == 2) {
1545 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1546 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1548 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1549 nir_print_instr(&instr
->instr
, stderr
);
1550 fprintf(stderr
, "\n");
1555 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1556 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1557 if (dst
.size() == 1) {
1558 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1559 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1561 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1562 } else if (dst
.size() == 2) {
1563 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1564 get_alu_src(ctx
, instr
->src
[0]),
1565 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1566 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1569 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1570 nir_print_instr(&instr
->instr
, stderr
);
1571 fprintf(stderr
, "\n");
1576 if (dst
.size() == 1) {
1577 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1578 } else if (dst
.size() == 2) {
1579 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1580 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
),
1581 get_alu_src(ctx
, instr
->src
[0]),
1582 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1583 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1585 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
),
1586 get_alu_src(ctx
, instr
->src
[0]),
1587 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1590 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1591 nir_print_instr(&instr
->instr
, stderr
);
1592 fprintf(stderr
, "\n");
1597 if (dst
.size() == 1) {
1598 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1599 } else if (dst
.size() == 2) {
1600 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1601 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
),
1602 get_alu_src(ctx
, instr
->src
[0]),
1603 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1604 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1606 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
),
1607 get_alu_src(ctx
, instr
->src
[0]),
1608 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1611 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1612 nir_print_instr(&instr
->instr
, stderr
);
1613 fprintf(stderr
, "\n");
1617 case nir_op_fmax3
: {
1618 if (dst
.size() == 1) {
1619 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1621 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1622 nir_print_instr(&instr
->instr
, stderr
);
1623 fprintf(stderr
, "\n");
1627 case nir_op_fmin3
: {
1628 if (dst
.size() == 1) {
1629 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1632 nir_print_instr(&instr
->instr
, stderr
);
1633 fprintf(stderr
, "\n");
1637 case nir_op_fmed3
: {
1638 if (dst
.size() == 1) {
1639 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1641 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1642 nir_print_instr(&instr
->instr
, stderr
);
1643 fprintf(stderr
, "\n");
1647 case nir_op_umax3
: {
1648 if (dst
.size() == 1) {
1649 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1651 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1652 nir_print_instr(&instr
->instr
, stderr
);
1653 fprintf(stderr
, "\n");
1657 case nir_op_umin3
: {
1658 if (dst
.size() == 1) {
1659 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1661 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1662 nir_print_instr(&instr
->instr
, stderr
);
1663 fprintf(stderr
, "\n");
1667 case nir_op_umed3
: {
1668 if (dst
.size() == 1) {
1669 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1671 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1672 nir_print_instr(&instr
->instr
, stderr
);
1673 fprintf(stderr
, "\n");
1677 case nir_op_imax3
: {
1678 if (dst
.size() == 1) {
1679 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1681 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1682 nir_print_instr(&instr
->instr
, stderr
);
1683 fprintf(stderr
, "\n");
1687 case nir_op_imin3
: {
1688 if (dst
.size() == 1) {
1689 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1691 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1692 nir_print_instr(&instr
->instr
, stderr
);
1693 fprintf(stderr
, "\n");
1697 case nir_op_imed3
: {
1698 if (dst
.size() == 1) {
1699 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1701 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1702 nir_print_instr(&instr
->instr
, stderr
);
1703 fprintf(stderr
, "\n");
1707 case nir_op_cube_face_coord
: {
1708 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1709 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1710 emit_extract_vector(ctx
, in
, 1, v1
),
1711 emit_extract_vector(ctx
, in
, 2, v1
) };
1712 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1713 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1714 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1715 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1716 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1717 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1718 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1721 case nir_op_cube_face_index
: {
1722 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1723 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1724 emit_extract_vector(ctx
, in
, 1, v1
),
1725 emit_extract_vector(ctx
, in
, 2, v1
) };
1726 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1729 case nir_op_bcsel
: {
1730 emit_bcsel(ctx
, instr
, dst
);
1734 if (dst
.size() == 1) {
1735 emit_rsq(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1736 } else if (dst
.size() == 2) {
1737 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1739 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1740 nir_print_instr(&instr
->instr
, stderr
);
1741 fprintf(stderr
, "\n");
1746 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1747 if (dst
.size() == 1) {
1748 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1749 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1750 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1751 } else if (dst
.size() == 2) {
1752 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1753 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1754 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1755 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1756 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1757 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1759 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1760 nir_print_instr(&instr
->instr
, stderr
);
1761 fprintf(stderr
, "\n");
1766 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1767 if (dst
.size() == 1) {
1768 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1769 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1770 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1771 } else if (dst
.size() == 2) {
1772 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1773 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1774 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1775 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1776 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1777 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1779 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1780 nir_print_instr(&instr
->instr
, stderr
);
1781 fprintf(stderr
, "\n");
1786 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1787 if (dst
.size() == 1) {
1788 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1789 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1790 // TODO: confirm that this holds under any circumstances
1791 } else if (dst
.size() == 2) {
1792 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1793 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1796 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1797 nir_print_instr(&instr
->instr
, stderr
);
1798 fprintf(stderr
, "\n");
1802 case nir_op_flog2
: {
1803 if (dst
.size() == 1) {
1804 emit_log2(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1806 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1807 nir_print_instr(&instr
->instr
, stderr
);
1808 fprintf(stderr
, "\n");
1813 if (dst
.size() == 1) {
1814 emit_rcp(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1815 } else if (dst
.size() == 2) {
1816 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1818 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1819 nir_print_instr(&instr
->instr
, stderr
);
1820 fprintf(stderr
, "\n");
1824 case nir_op_fexp2
: {
1825 if (dst
.size() == 1) {
1826 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1828 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1829 nir_print_instr(&instr
->instr
, stderr
);
1830 fprintf(stderr
, "\n");
1834 case nir_op_fsqrt
: {
1835 if (dst
.size() == 1) {
1836 emit_sqrt(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1837 } else if (dst
.size() == 2) {
1838 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1840 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1841 nir_print_instr(&instr
->instr
, stderr
);
1842 fprintf(stderr
, "\n");
1846 case nir_op_ffract
: {
1847 if (dst
.size() == 1) {
1848 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1849 } else if (dst
.size() == 2) {
1850 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1852 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1853 nir_print_instr(&instr
->instr
, stderr
);
1854 fprintf(stderr
, "\n");
1858 case nir_op_ffloor
: {
1859 if (dst
.size() == 1) {
1860 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1861 } else if (dst
.size() == 2) {
1862 emit_floor_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1864 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1865 nir_print_instr(&instr
->instr
, stderr
);
1866 fprintf(stderr
, "\n");
1870 case nir_op_fceil
: {
1871 if (dst
.size() == 1) {
1872 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1873 } else if (dst
.size() == 2) {
1874 if (ctx
->options
->chip_class
>= GFX7
) {
1875 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1877 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1878 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1880 /* trunc = trunc(src0)
1881 * if (src0 > 0.0 && src0 != trunc)
1884 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1885 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1886 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1887 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1888 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1889 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1890 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1893 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1894 nir_print_instr(&instr
->instr
, stderr
);
1895 fprintf(stderr
, "\n");
1899 case nir_op_ftrunc
: {
1900 if (dst
.size() == 1) {
1901 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1902 } else if (dst
.size() == 2) {
1903 emit_trunc_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1906 nir_print_instr(&instr
->instr
, stderr
);
1907 fprintf(stderr
, "\n");
1911 case nir_op_fround_even
: {
1912 if (dst
.size() == 1) {
1913 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1914 } else if (dst
.size() == 2) {
1915 if (ctx
->options
->chip_class
>= GFX7
) {
1916 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1918 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1919 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1921 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
1922 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
1924 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
1925 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
1926 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1927 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1928 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
1929 tmp
= sub
->definitions
[0].getTemp();
1931 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
1932 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
1933 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
1934 Temp cond
= vop3
->definitions
[0].getTemp();
1936 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
1937 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
1938 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
1939 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
1941 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1944 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1945 nir_print_instr(&instr
->instr
, stderr
);
1946 fprintf(stderr
, "\n");
1952 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1953 aco_ptr
<Instruction
> norm
;
1954 if (dst
.size() == 1) {
1955 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
1956 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, as_vgpr(ctx
, src
));
1958 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1959 if (ctx
->options
->chip_class
< GFX9
)
1960 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
1962 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
1963 bld
.vop1(opcode
, Definition(dst
), tmp
);
1965 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1966 nir_print_instr(&instr
->instr
, stderr
);
1967 fprintf(stderr
, "\n");
1971 case nir_op_ldexp
: {
1972 if (dst
.size() == 1) {
1973 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
),
1974 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1975 get_alu_src(ctx
, instr
->src
[1]));
1976 } else if (dst
.size() == 2) {
1977 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
),
1978 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1979 get_alu_src(ctx
, instr
->src
[1]));
1981 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1982 nir_print_instr(&instr
->instr
, stderr
);
1983 fprintf(stderr
, "\n");
1987 case nir_op_frexp_sig
: {
1988 if (dst
.size() == 1) {
1989 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
),
1990 get_alu_src(ctx
, instr
->src
[0]));
1991 } else if (dst
.size() == 2) {
1992 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
),
1993 get_alu_src(ctx
, instr
->src
[0]));
1995 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1996 nir_print_instr(&instr
->instr
, stderr
);
1997 fprintf(stderr
, "\n");
2001 case nir_op_frexp_exp
: {
2002 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2003 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
),
2004 get_alu_src(ctx
, instr
->src
[0]));
2005 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2006 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
),
2007 get_alu_src(ctx
, instr
->src
[0]));
2009 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2010 nir_print_instr(&instr
->instr
, stderr
);
2011 fprintf(stderr
, "\n");
2015 case nir_op_fsign
: {
2016 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2017 if (dst
.size() == 1) {
2018 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2019 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2020 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2021 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2022 } else if (dst
.size() == 2) {
2023 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2024 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2025 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2027 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2028 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2029 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2031 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2033 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2034 nir_print_instr(&instr
->instr
, stderr
);
2035 fprintf(stderr
, "\n");
2040 case nir_op_f2f16_rtne
: {
2041 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2042 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2043 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2044 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2045 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2048 case nir_op_f2f16_rtz
: {
2049 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2050 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2051 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2052 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2053 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2056 case nir_op_f2f32
: {
2057 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2058 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2059 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2060 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2062 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2063 nir_print_instr(&instr
->instr
, stderr
);
2064 fprintf(stderr
, "\n");
2068 case nir_op_f2f64
: {
2069 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2070 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2071 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2072 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2075 case nir_op_i2f32
: {
2076 assert(dst
.size() == 1);
2077 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2080 case nir_op_i2f64
: {
2081 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2082 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2083 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2084 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2085 RegClass rc
= RegClass(src
.type(), 1);
2086 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2087 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2088 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2089 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2090 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2091 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2094 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2095 nir_print_instr(&instr
->instr
, stderr
);
2096 fprintf(stderr
, "\n");
2100 case nir_op_u2f32
: {
2101 assert(dst
.size() == 1);
2102 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2105 case nir_op_u2f64
: {
2106 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2107 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2108 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2109 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2110 RegClass rc
= RegClass(src
.type(), 1);
2111 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2112 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2113 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2114 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2115 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2116 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2118 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2119 nir_print_instr(&instr
->instr
, stderr
);
2120 fprintf(stderr
, "\n");
2124 case nir_op_f2i16
: {
2125 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2126 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2127 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2128 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2129 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2131 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2133 if (dst
.type() == RegType::vgpr
)
2134 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2136 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2139 case nir_op_f2u16
: {
2140 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2141 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2142 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2143 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2144 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2146 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2148 if (dst
.type() == RegType::vgpr
)
2149 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2151 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2154 case nir_op_f2i32
: {
2155 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2156 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2157 if (dst
.type() == RegType::vgpr
)
2158 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2160 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2161 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2163 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2164 if (dst
.type() == RegType::vgpr
)
2165 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2167 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2168 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2171 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2172 nir_print_instr(&instr
->instr
, stderr
);
2173 fprintf(stderr
, "\n");
2177 case nir_op_f2u32
: {
2178 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2179 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2180 if (dst
.type() == RegType::vgpr
)
2181 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2183 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2184 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2186 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2187 if (dst
.type() == RegType::vgpr
)
2188 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2190 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2191 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2194 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2195 nir_print_instr(&instr
->instr
, stderr
);
2196 fprintf(stderr
, "\n");
2200 case nir_op_f2i64
: {
2201 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2202 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2203 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2204 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2205 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2206 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2207 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2208 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2209 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2210 Temp new_exponent
= bld
.tmp(v1
);
2211 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2212 if (ctx
->program
->chip_class
>= GFX8
)
2213 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2215 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2216 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2217 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2218 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2219 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2220 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2221 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2222 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2223 Temp new_lower
= bld
.tmp(v1
);
2224 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2225 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2226 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2228 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2229 if (src
.type() == RegType::vgpr
)
2230 src
= bld
.as_uniform(src
);
2231 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2232 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2233 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2234 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2235 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2236 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2237 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2238 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2239 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2240 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2241 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2242 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2243 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2244 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2245 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2246 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2247 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2248 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2249 Temp borrow
= bld
.tmp(s1
);
2250 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2251 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2252 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2254 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2255 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2256 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2257 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2258 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2259 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2260 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2261 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2262 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2263 if (dst
.type() == RegType::sgpr
) {
2264 lower
= bld
.as_uniform(lower
);
2265 upper
= bld
.as_uniform(upper
);
2267 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2270 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2271 nir_print_instr(&instr
->instr
, stderr
);
2272 fprintf(stderr
, "\n");
2276 case nir_op_f2u64
: {
2277 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2278 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2279 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2280 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2281 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2282 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2283 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2284 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2285 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2286 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2287 Temp new_exponent
= bld
.tmp(v1
);
2288 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2289 if (ctx
->program
->chip_class
>= GFX8
)
2290 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2292 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2293 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2294 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2295 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2296 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2297 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2298 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2299 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2301 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2302 if (src
.type() == RegType::vgpr
)
2303 src
= bld
.as_uniform(src
);
2304 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2305 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2306 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2307 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2308 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2309 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2310 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2311 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2312 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2313 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2314 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2315 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2316 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2317 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2318 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2319 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2320 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2321 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2323 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2324 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2325 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2326 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2327 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2328 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2329 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2330 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2331 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2332 if (dst
.type() == RegType::sgpr
) {
2333 lower
= bld
.as_uniform(lower
);
2334 upper
= bld
.as_uniform(upper
);
2336 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2339 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2340 nir_print_instr(&instr
->instr
, stderr
);
2341 fprintf(stderr
, "\n");
2345 case nir_op_b2f32
: {
2346 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2347 assert(src
.regClass() == bld
.lm
);
2349 if (dst
.regClass() == s1
) {
2350 src
= bool_to_scalar_condition(ctx
, src
);
2351 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2352 } else if (dst
.regClass() == v1
) {
2353 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2355 unreachable("Wrong destination register class for nir_op_b2f32.");
2359 case nir_op_b2f64
: {
2360 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2361 assert(src
.regClass() == bld
.lm
);
2363 if (dst
.regClass() == s2
) {
2364 src
= bool_to_scalar_condition(ctx
, src
);
2365 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2366 } else if (dst
.regClass() == v2
) {
2367 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2368 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2369 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2371 unreachable("Wrong destination register class for nir_op_b2f64.");
2377 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2378 /* we can actually just say dst = src */
2379 if (src
.regClass() == s1
)
2380 bld
.copy(Definition(dst
), src
);
2382 emit_extract_vector(ctx
, src
, 0, dst
);
2385 case nir_op_i2i16
: {
2386 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2387 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2388 if (dst
.regClass() == s1
) {
2389 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2391 assert(src
.regClass() == v1b
);
2392 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2393 sdwa
->operands
[0] = Operand(src
);
2394 sdwa
->definitions
[0] = Definition(dst
);
2395 sdwa
->sel
[0] = sdwa_sbyte
;
2396 sdwa
->dst_sel
= sdwa_sword
;
2397 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2400 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2401 /* we can actually just say dst = src */
2402 if (src
.regClass() == s1
)
2403 bld
.copy(Definition(dst
), src
);
2405 emit_extract_vector(ctx
, src
, 0, dst
);
2409 case nir_op_u2u16
: {
2410 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2411 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2412 if (dst
.regClass() == s1
)
2413 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2415 assert(src
.regClass() == v1b
);
2416 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2417 sdwa
->operands
[0] = Operand(src
);
2418 sdwa
->definitions
[0] = Definition(dst
);
2419 sdwa
->sel
[0] = sdwa_ubyte
;
2420 sdwa
->dst_sel
= sdwa_uword
;
2421 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2424 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2425 /* we can actually just say dst = src */
2426 if (src
.regClass() == s1
)
2427 bld
.copy(Definition(dst
), src
);
2429 emit_extract_vector(ctx
, src
, 0, dst
);
2433 case nir_op_i2i32
: {
2434 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2435 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2436 if (dst
.regClass() == s1
) {
2437 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2439 assert(src
.regClass() == v1b
);
2440 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2441 sdwa
->operands
[0] = Operand(src
);
2442 sdwa
->definitions
[0] = Definition(dst
);
2443 sdwa
->sel
[0] = sdwa_sbyte
;
2444 sdwa
->dst_sel
= sdwa_sdword
;
2445 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2447 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2448 if (dst
.regClass() == s1
) {
2449 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2451 assert(src
.regClass() == v2b
);
2452 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2453 sdwa
->operands
[0] = Operand(src
);
2454 sdwa
->definitions
[0] = Definition(dst
);
2455 sdwa
->sel
[0] = sdwa_sword
;
2456 sdwa
->dst_sel
= sdwa_udword
;
2457 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2459 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2460 /* we can actually just say dst = src, as it would map the lower register */
2461 emit_extract_vector(ctx
, src
, 0, dst
);
2463 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2464 nir_print_instr(&instr
->instr
, stderr
);
2465 fprintf(stderr
, "\n");
2469 case nir_op_u2u32
: {
2470 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2471 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2472 if (dst
.regClass() == s1
)
2473 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2475 assert(src
.regClass() == v1b
);
2476 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2477 sdwa
->operands
[0] = Operand(src
);
2478 sdwa
->definitions
[0] = Definition(dst
);
2479 sdwa
->sel
[0] = sdwa_ubyte
;
2480 sdwa
->dst_sel
= sdwa_udword
;
2481 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2483 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2484 if (dst
.regClass() == s1
) {
2485 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2487 assert(src
.regClass() == v2b
);
2488 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2489 sdwa
->operands
[0] = Operand(src
);
2490 sdwa
->definitions
[0] = Definition(dst
);
2491 sdwa
->sel
[0] = sdwa_uword
;
2492 sdwa
->dst_sel
= sdwa_udword
;
2493 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2495 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2496 /* we can actually just say dst = src, as it would map the lower register */
2497 emit_extract_vector(ctx
, src
, 0, dst
);
2499 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2500 nir_print_instr(&instr
->instr
, stderr
);
2501 fprintf(stderr
, "\n");
2505 case nir_op_i2i64
: {
2506 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2507 if (src
.regClass() == s1
) {
2508 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2509 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2510 } else if (src
.regClass() == v1
) {
2511 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2512 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2514 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2515 nir_print_instr(&instr
->instr
, stderr
);
2516 fprintf(stderr
, "\n");
2520 case nir_op_u2u64
: {
2521 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2522 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2523 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2525 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2526 nir_print_instr(&instr
->instr
, stderr
);
2527 fprintf(stderr
, "\n");
2532 case nir_op_b2i32
: {
2533 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2534 assert(src
.regClass() == bld
.lm
);
2536 if (dst
.regClass() == s1
) {
2537 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2538 bool_to_scalar_condition(ctx
, src
, dst
);
2539 } else if (dst
.regClass() == v1
) {
2540 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2542 unreachable("Invalid register class for b2i32");
2548 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2549 assert(dst
.regClass() == bld
.lm
);
2551 if (src
.type() == RegType::vgpr
) {
2552 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2553 assert(dst
.regClass() == bld
.lm
);
2554 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2555 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2557 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2559 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2560 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2562 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2563 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2565 bool_to_vector_condition(ctx
, tmp
, dst
);
2569 case nir_op_pack_64_2x32_split
: {
2570 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2571 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2573 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2576 case nir_op_unpack_64_2x32_split_x
:
2577 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2579 case nir_op_unpack_64_2x32_split_y
:
2580 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2582 case nir_op_unpack_32_2x16_split_x
:
2583 if (dst
.type() == RegType::vgpr
) {
2584 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2586 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2589 case nir_op_unpack_32_2x16_split_y
:
2590 if (dst
.type() == RegType::vgpr
) {
2591 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2593 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2596 case nir_op_pack_32_2x16_split
: {
2597 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2598 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2599 if (dst
.regClass() == v1
) {
2600 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2602 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2603 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2604 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2608 case nir_op_pack_half_2x16
: {
2609 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2611 if (dst
.regClass() == v1
) {
2612 Temp src0
= bld
.tmp(v1
);
2613 Temp src1
= bld
.tmp(v1
);
2614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2615 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2616 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2618 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2619 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2620 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2622 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2623 nir_print_instr(&instr
->instr
, stderr
);
2624 fprintf(stderr
, "\n");
2628 case nir_op_unpack_half_2x16_split_x
: {
2629 if (dst
.regClass() == v1
) {
2630 Builder
bld(ctx
->program
, ctx
->block
);
2631 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2633 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2634 nir_print_instr(&instr
->instr
, stderr
);
2635 fprintf(stderr
, "\n");
2639 case nir_op_unpack_half_2x16_split_y
: {
2640 if (dst
.regClass() == v1
) {
2641 Builder
bld(ctx
->program
, ctx
->block
);
2642 /* TODO: use SDWA here */
2643 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2644 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2646 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2647 nir_print_instr(&instr
->instr
, stderr
);
2648 fprintf(stderr
, "\n");
2652 case nir_op_fquantize2f16
: {
2653 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2654 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2657 if (ctx
->program
->chip_class
>= GFX8
) {
2658 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2659 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2660 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2662 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2663 * so compare the result and flush to 0 if it's smaller.
2665 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2666 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2667 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2668 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2669 cmp_res
= vop3
->definitions
[0].getTemp();
2672 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2673 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2674 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2676 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2681 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2682 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2684 if (dst
.regClass() == s1
) {
2685 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2686 } else if (dst
.regClass() == v1
) {
2687 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2689 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2690 nir_print_instr(&instr
->instr
, stderr
);
2691 fprintf(stderr
, "\n");
2695 case nir_op_bitfield_select
: {
2696 /* (mask & insert) | (~mask & base) */
2697 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2698 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2699 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2701 /* dst = (insert & bitmask) | (base & ~bitmask) */
2702 if (dst
.regClass() == s1
) {
2703 aco_ptr
<Instruction
> sop2
;
2704 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2705 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2707 if (const_insert
&& const_bitmask
) {
2708 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2710 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2711 lhs
= Operand(insert
);
2715 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2716 if (const_base
&& const_bitmask
) {
2717 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2719 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2720 rhs
= Operand(base
);
2723 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2725 } else if (dst
.regClass() == v1
) {
2726 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2727 base
= as_vgpr(ctx
, base
);
2728 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2729 insert
= as_vgpr(ctx
, insert
);
2731 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2734 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2735 nir_print_instr(&instr
->instr
, stderr
);
2736 fprintf(stderr
, "\n");
2742 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2743 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2744 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2746 if (dst
.type() == RegType::sgpr
) {
2748 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2749 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2750 if (const_offset
&& const_bits
) {
2751 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2752 extract
= Operand(const_extract
);
2756 width
= Operand(const_bits
->u32
<< 16);
2758 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2760 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2764 if (dst
.regClass() == s1
) {
2765 if (instr
->op
== nir_op_ubfe
)
2766 opcode
= aco_opcode::s_bfe_u32
;
2768 opcode
= aco_opcode::s_bfe_i32
;
2769 } else if (dst
.regClass() == s2
) {
2770 if (instr
->op
== nir_op_ubfe
)
2771 opcode
= aco_opcode::s_bfe_u64
;
2773 opcode
= aco_opcode::s_bfe_i64
;
2775 unreachable("Unsupported BFE bit size");
2778 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2782 if (dst
.regClass() == v1
) {
2783 if (instr
->op
== nir_op_ubfe
)
2784 opcode
= aco_opcode::v_bfe_u32
;
2786 opcode
= aco_opcode::v_bfe_i32
;
2788 unreachable("Unsupported BFE bit size");
2791 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2795 case nir_op_bit_count
: {
2796 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2797 if (src
.regClass() == s1
) {
2798 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2799 } else if (src
.regClass() == v1
) {
2800 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2801 } else if (src
.regClass() == v2
) {
2802 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2803 emit_extract_vector(ctx
, src
, 1, v1
),
2804 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2805 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2806 } else if (src
.regClass() == s2
) {
2807 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2809 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2810 nir_print_instr(&instr
->instr
, stderr
);
2811 fprintf(stderr
, "\n");
2816 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2820 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2824 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2828 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2832 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2836 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2840 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2841 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2843 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2844 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2848 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2849 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2851 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2852 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2856 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2860 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2865 case nir_op_fddx_fine
:
2866 case nir_op_fddy_fine
:
2867 case nir_op_fddx_coarse
:
2868 case nir_op_fddy_coarse
: {
2869 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2870 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2871 if (instr
->op
== nir_op_fddx_fine
) {
2872 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2873 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2874 } else if (instr
->op
== nir_op_fddy_fine
) {
2875 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2876 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2878 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2879 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2880 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2882 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2886 if (ctx
->program
->chip_class
>= GFX8
) {
2887 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2888 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2890 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2891 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2892 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2894 emit_wqm(ctx
, tmp
, dst
, true);
2898 fprintf(stderr
, "Unknown NIR ALU instr: ");
2899 nir_print_instr(&instr
->instr
, stderr
);
2900 fprintf(stderr
, "\n");
2904 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2906 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2908 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2909 // which get truncated the lsb if double and msb if int
2910 // for now, we only use s_mov_b64 with 64bit inline constants
2911 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2912 assert(dst
.type() == RegType::sgpr
);
2914 Builder
bld(ctx
->program
, ctx
->block
);
2916 if (instr
->def
.bit_size
== 1) {
2917 assert(dst
.regClass() == bld
.lm
);
2918 int val
= instr
->value
[0].b
? -1 : 0;
2919 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2920 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2921 } else if (dst
.size() == 1) {
2922 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2924 assert(dst
.size() != 1);
2925 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2926 if (instr
->def
.bit_size
== 64)
2927 for (unsigned i
= 0; i
< dst
.size(); i
++)
2928 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2930 for (unsigned i
= 0; i
< dst
.size(); i
++)
2931 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2933 vec
->definitions
[0] = Definition(dst
);
2934 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2938 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2940 uint32_t new_mask
= 0;
2941 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2942 if (mask
& (1u << i
))
2943 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2947 Operand
load_lds_size_m0(isel_context
*ctx
)
2949 /* TODO: m0 does not need to be initialized on GFX9+ */
2950 Builder
bld(ctx
->program
, ctx
->block
);
2951 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
2954 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
2955 Temp address
, unsigned base_offset
, unsigned align
)
2957 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2959 Builder
bld(ctx
->program
, ctx
->block
);
2961 Operand m
= load_lds_size_m0(ctx
);
2963 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
2964 unsigned bytes_read
= 0;
2965 unsigned result_size
= 0;
2966 unsigned total_bytes
= num_components
* elem_size_bytes
;
2967 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
2968 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
2969 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
2971 while (bytes_read
< total_bytes
) {
2972 unsigned todo
= total_bytes
- bytes_read
;
2973 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
2974 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
2976 aco_opcode op
= aco_opcode::last_opcode
;
2978 if (todo
>= 16 && aligned16
&& large_ds_read
) {
2979 op
= aco_opcode::ds_read_b128
;
2981 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
2982 op
= aco_opcode::ds_read2_b64
;
2985 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
2986 op
= aco_opcode::ds_read_b96
;
2988 } else if (todo
>= 8 && aligned8
) {
2989 op
= aco_opcode::ds_read_b64
;
2991 } else if (todo
>= 8 && usable_read2
) {
2992 op
= aco_opcode::ds_read2_b32
;
2995 } else if (todo
>= 4) {
2996 op
= aco_opcode::ds_read_b32
;
3001 assert(todo
% elem_size_bytes
== 0);
3002 unsigned num_elements
= todo
/ elem_size_bytes
;
3003 unsigned offset
= base_offset
+ bytes_read
;
3004 unsigned max_offset
= read2
? 1019 : 65535;
3006 Temp address_offset
= address
;
3007 if (offset
> max_offset
) {
3008 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3009 offset
= bytes_read
;
3011 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3014 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3017 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3020 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3022 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3024 if (num_components
== 1) {
3025 assert(todo
== total_bytes
);
3026 if (dst
.type() == RegType::sgpr
)
3027 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3031 if (dst
.type() == RegType::sgpr
) {
3032 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3033 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3037 if (num_elements
== 1) {
3038 result
[result_size
++] = res
;
3040 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3041 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3042 split
->operands
[0] = Operand(res
);
3043 for (unsigned i
= 0; i
< num_elements
; i
++)
3044 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3045 ctx
->block
->instructions
.emplace_back(std::move(split
));
3051 assert(result_size
== num_components
&& result_size
> 1);
3052 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3053 for (unsigned i
= 0; i
< result_size
; i
++)
3054 vec
->operands
[i
] = Operand(result
[i
]);
3055 vec
->definitions
[0] = Definition(dst
);
3056 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3057 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3062 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3064 if (start
== 0 && size
== data
.size())
3065 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3067 unsigned size_hint
= 1;
3068 auto it
= ctx
->allocated_vec
.find(data
.id());
3069 if (it
!= ctx
->allocated_vec
.end())
3070 size_hint
= it
->second
[0].size();
3071 if (size
% size_hint
|| start
% size_hint
)
3078 for (unsigned i
= 0; i
< size
; i
++)
3079 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3082 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3084 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3085 for (unsigned i
= 0; i
< size
; i
++)
3086 vec
->operands
[i
] = Operand(elems
[i
]);
3087 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3088 vec
->definitions
[0] = Definition(res
);
3089 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3093 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3095 Builder
bld(ctx
->program
, ctx
->block
);
3096 unsigned bytes_written
= 0;
3097 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3098 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3100 while (bytes_written
< total_size
* 4) {
3101 unsigned todo
= total_size
* 4 - bytes_written
;
3102 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3103 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3105 aco_opcode op
= aco_opcode::last_opcode
;
3106 bool write2
= false;
3108 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3109 op
= aco_opcode::ds_write_b128
;
3111 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3112 op
= aco_opcode::ds_write2_b64
;
3115 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3116 op
= aco_opcode::ds_write_b96
;
3118 } else if (todo
>= 8 && aligned8
) {
3119 op
= aco_opcode::ds_write_b64
;
3121 } else if (todo
>= 8 && usable_write2
) {
3122 op
= aco_opcode::ds_write2_b32
;
3125 } else if (todo
>= 4) {
3126 op
= aco_opcode::ds_write_b32
;
3132 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3133 unsigned max_offset
= write2
? 1020 : 65535;
3134 Temp address_offset
= address
;
3135 if (offset
> max_offset
) {
3136 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3137 offset
= offset1
+ bytes_written
;
3139 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3142 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3143 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3144 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3146 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3147 bld
.ds(op
, address_offset
, val
, m
, offset
);
3150 bytes_written
+= size
* 4;
3154 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3155 Temp address
, unsigned base_offset
, unsigned align
)
3157 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3158 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3160 Operand m
= load_lds_size_m0(ctx
);
3162 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3163 assert(wrmask
<= 0x0f);
3164 int start
[2], count
[2];
3165 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3166 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3167 assert(wrmask
== 0);
3169 /* one combined store is sufficient */
3170 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3171 Builder
bld(ctx
->program
, ctx
->block
);
3173 Temp address_offset
= address
;
3174 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3175 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3179 assert(count
[0] == 1);
3180 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3182 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3183 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3184 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3185 base_offset
= base_offset
/ elem_size_bytes
;
3186 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3187 base_offset
+ start
[0], base_offset
+ start
[1]);
3191 for (unsigned i
= 0; i
< 2; i
++) {
3195 unsigned elem_size_words
= elem_size_bytes
/ 4;
3196 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3197 base_offset
, start
[i
] * elem_size_bytes
, align
);
3202 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3204 unsigned align
= 16;
3206 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3212 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3213 unsigned split_cnt
= 0u, Temp dst
= Temp())
3215 Builder
bld(ctx
->program
, ctx
->block
);
3216 unsigned dword_size
= elem_size_bytes
/ 4;
3219 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3221 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3222 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3223 instr
->definitions
[0] = Definition(dst
);
3225 for (unsigned i
= 0; i
< cnt
; ++i
) {
3227 assert(arr
[i
].size() == dword_size
);
3228 allocated_vec
[i
] = arr
[i
];
3229 instr
->operands
[i
] = Operand(arr
[i
]);
3231 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3232 allocated_vec
[i
] = zero
;
3233 instr
->operands
[i
] = Operand(zero
);
3237 bld
.insert(std::move(instr
));
3240 emit_split_vector(ctx
, dst
, split_cnt
);
3242 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3247 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3249 if (const_offset
>= 4096) {
3250 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3251 const_offset
%= 4096u;
3254 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3255 else if (unlikely(voffset
.regClass() == s1
))
3256 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3257 else if (likely(voffset
.regClass() == v1
))
3258 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3260 unreachable("Unsupported register class of voffset");
3263 return const_offset
;
3266 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3267 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3270 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3271 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3273 Builder
bld(ctx
->program
, ctx
->block
);
3274 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3275 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3277 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3278 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3279 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3280 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3281 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3283 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3286 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3287 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3288 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3290 Builder
bld(ctx
->program
, ctx
->block
);
3291 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3294 if (elem_size_bytes
== 8) {
3295 elem_size_bytes
= 4;
3296 write_mask
= widen_mask(write_mask
, 2);
3299 while (write_mask
) {
3302 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3307 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3308 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3310 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3311 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3314 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3315 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3325 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3326 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3328 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3329 assert(size_dwords
>= 1 && size_dwords
<= 4);
3331 Builder
bld(ctx
->program
, ctx
->block
);
3332 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3333 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3334 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3336 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3337 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3338 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3339 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3340 /* disable_wqm */ false, /* glc */ true,
3341 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3343 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3348 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3349 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3350 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3352 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3353 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3354 assert(!!stride
!= allow_combining
);
3356 Builder
bld(ctx
->program
, ctx
->block
);
3357 unsigned split_cnt
= num_components
;
3359 if (elem_size_bytes
== 8) {
3360 elem_size_bytes
= 4;
3361 num_components
*= 2;
3365 stride
= elem_size_bytes
;
3367 unsigned load_size
= 1;
3368 if (allow_combining
) {
3369 if ((num_components
% 4) == 0)
3371 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3373 else if ((num_components
% 2) == 0)
3377 unsigned num_loads
= num_components
/ load_size
;
3378 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3380 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3381 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3382 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3385 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3388 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3390 Builder
bld(ctx
->program
, ctx
->block
);
3391 Temp offset
= base_offset
.first
;
3392 unsigned const_offset
= base_offset
.second
;
3394 if (!nir_src_is_const(*off_src
)) {
3395 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3398 /* Calculate indirect offset with stride */
3399 if (likely(indirect_offset_arg
.regClass() == v1
))
3400 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3401 else if (indirect_offset_arg
.regClass() == s1
)
3402 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3404 unreachable("Unsupported register class of indirect offset");
3406 /* Add to the supplied base offset */
3407 if (offset
.id() == 0)
3408 offset
= with_stride
;
3409 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3410 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3411 else if (offset
.size() == 1 && with_stride
.size() == 1)
3412 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3414 unreachable("Unsupported register class of indirect offset");
3416 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3417 const_offset
+= const_offset_arg
* stride
;
3420 return std::make_pair(offset
, const_offset
);
3423 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3425 Builder
bld(ctx
->program
, ctx
->block
);
3428 if (off1
.first
.id() && off2
.first
.id()) {
3429 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3430 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3431 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3432 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3434 unreachable("Unsupported register class of indirect offset");
3436 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3439 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3442 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3444 Builder
bld(ctx
->program
, ctx
->block
);
3445 unsigned const_offset
= offs
.second
* multiplier
;
3447 if (!offs
.first
.id())
3448 return std::make_pair(offs
.first
, const_offset
);
3450 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3451 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3452 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3454 return std::make_pair(offset
, const_offset
);
3457 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3459 Builder
bld(ctx
->program
, ctx
->block
);
3461 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3462 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3463 /* component is in bytes */
3464 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3466 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3467 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3468 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3471 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3473 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3476 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3478 Builder
bld(ctx
->program
, ctx
->block
);
3480 switch (ctx
->shader
->info
.stage
) {
3481 case MESA_SHADER_TESS_CTRL
:
3482 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3483 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3484 case MESA_SHADER_TESS_EVAL
:
3485 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3487 unreachable("Unsupported stage in get_tess_rel_patch_id");
3491 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3493 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3494 Builder
bld(ctx
->program
, ctx
->block
);
3496 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3497 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3499 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3501 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3502 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3504 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3505 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3506 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3508 return offset_mul(ctx
, offs
, 4u);
3511 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3513 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3514 Builder
bld(ctx
->program
, ctx
->block
);
3516 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3517 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3518 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3519 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3520 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3521 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3523 std::pair
<Temp
, unsigned> offs
= instr
3524 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3525 : std::make_pair(Temp(), 0u);
3527 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3528 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3533 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3534 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3536 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3537 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3539 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3540 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3546 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3548 Builder
bld(ctx
->program
, ctx
->block
);
3550 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3551 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3553 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3555 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3556 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3557 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3559 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3560 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3565 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3567 Builder
bld(ctx
->program
, ctx
->block
);
3569 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3570 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3571 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3573 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3574 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3575 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3576 unsigned attr_stride
= ctx
->tcs_num_patches
;
3578 std::pair
<Temp
, unsigned> offs
= instr
3579 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3580 : std::make_pair(Temp(), 0u);
3582 if (const_base_offset
)
3583 offs
.second
+= const_base_offset
* attr_stride
;
3585 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3586 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3587 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3592 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3594 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3595 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3597 if (!nir_src_is_const(*off_src
)) {
3603 off
+= nir_src_as_uint(*off_src
) * 16u;
3606 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3607 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3614 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3616 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3617 unsigned component
= nir_intrinsic_component(instr
);
3618 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3620 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3621 if (off_instr
->type
!= nir_instr_type_load_const
)
3624 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3625 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3627 if (instr
->src
[0].ssa
->bit_size
== 64)
3628 write_mask
= widen_mask(write_mask
, 2);
3630 for (unsigned i
= 0; i
< 8; ++i
) {
3631 if (write_mask
& (1 << i
)) {
3632 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3633 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3641 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3643 /* Only TCS per-vertex inputs are supported by this function.
3644 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3646 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3649 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3650 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3651 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3652 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3653 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3654 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3659 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3660 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3661 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3662 assert(vec
.size() == dst
.size());
3664 Builder
bld(ctx
->program
, ctx
->block
);
3665 bld
.copy(Definition(dst
), vec
);
3669 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3671 Builder
bld(ctx
->program
, ctx
->block
);
3673 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3674 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3675 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3676 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3678 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3679 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3680 bool indirect_write
;
3681 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3682 if (temp_only_input
&& !indirect_write
)
3686 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3687 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3688 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3689 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3690 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3694 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3695 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3696 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3697 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3698 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3699 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3700 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3701 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3702 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3703 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3704 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3705 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3706 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3708 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3709 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3710 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3712 unreachable("Invalid LS or ES stage");
3715 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3716 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3717 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3721 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3723 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3724 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3725 off
!= ctx
->tcs_tess_lvl_in_loc
;
3728 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3730 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3731 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3734 uint64_t mask
= per_vertex
3735 ? ctx
->shader
->info
.outputs_read
3736 : ctx
->shader
->info
.patch_outputs_read
;
3737 bool indirect_write
;
3738 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3739 return indirect_write
|| output_read
;
3742 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3744 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3745 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3747 Builder
bld(ctx
->program
, ctx
->block
);
3749 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3750 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3751 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3753 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3754 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3755 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3756 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3758 if (write_to_vmem
) {
3759 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3760 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3761 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3763 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3764 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3765 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3769 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3770 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3771 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3775 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3777 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3778 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3780 Builder
bld(ctx
->program
, ctx
->block
);
3782 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3783 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3784 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3785 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3787 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3790 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3792 if (ctx
->stage
== vertex_vs
||
3793 ctx
->stage
== tess_eval_vs
||
3794 ctx
->stage
== fragment_fs
||
3795 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3796 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3797 if (!stored_to_temps
) {
3798 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3799 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3800 fprintf(stderr
, "\n");
3803 } else if (ctx
->stage
== vertex_es
||
3804 ctx
->stage
== vertex_ls
||
3805 ctx
->stage
== tess_eval_es
||
3806 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3807 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3808 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3809 visit_store_ls_or_es_output(ctx
, instr
);
3810 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3811 visit_store_tcs_output(ctx
, instr
, false);
3813 unreachable("Shader stage not implemented");
3817 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3819 visit_load_tcs_output(ctx
, instr
, false);
3822 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3824 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3825 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3827 Builder
bld(ctx
->program
, ctx
->block
);
3828 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3829 if (ctx
->program
->has_16bank_lds
)
3830 interp_p1
.instr
->operands
[0].setLateKill(true);
3831 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
3834 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3836 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3837 for (unsigned i
= 0; i
< num_components
; i
++)
3838 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3839 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3840 assert(num_components
== 4);
3841 Builder
bld(ctx
->program
, ctx
->block
);
3842 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3845 for (Operand
& op
: vec
->operands
)
3846 op
= op
.isUndefined() ? Operand(0u) : op
;
3848 vec
->definitions
[0] = Definition(dst
);
3849 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3850 emit_split_vector(ctx
, dst
, num_components
);
3854 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3856 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3857 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3858 unsigned idx
= nir_intrinsic_base(instr
);
3859 unsigned component
= nir_intrinsic_component(instr
);
3860 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3862 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3864 assert(offset
->u32
== 0);
3866 /* the lower 15bit of the prim_mask contain the offset into LDS
3867 * while the upper bits contain the number of prims */
3868 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3869 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3870 Builder
bld(ctx
->program
, ctx
->block
);
3871 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3872 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3873 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3874 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3875 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3878 if (instr
->dest
.ssa
.num_components
== 1) {
3879 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
3881 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
3882 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
3884 Temp tmp
= {ctx
->program
->allocateId(), v1
};
3885 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
3886 vec
->operands
[i
] = Operand(tmp
);
3888 vec
->definitions
[0] = Definition(dst
);
3889 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3893 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3894 unsigned offset
, unsigned stride
, unsigned channels
)
3896 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
3897 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
3899 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
3900 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
3903 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3904 unsigned offset
, unsigned stride
, unsigned *channels
)
3906 if (!vtx_info
->chan_byte_size
) {
3907 *channels
= vtx_info
->num_channels
;
3908 return vtx_info
->chan_format
;
3911 unsigned num_channels
= *channels
;
3912 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
3913 unsigned new_channels
= num_channels
+ 1;
3914 /* first, assume more loads is worse and try using a larger data format */
3915 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
3917 /* don't make the attribute potentially out-of-bounds */
3918 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
3922 if (new_channels
== 5) {
3923 /* then try decreasing load size (at the cost of more loads) */
3924 new_channels
= *channels
;
3925 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
3929 if (new_channels
< *channels
)
3930 *channels
= new_channels
;
3931 num_channels
= new_channels
;
3934 switch (vtx_info
->chan_format
) {
3935 case V_008F0C_BUF_DATA_FORMAT_8
:
3936 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
3937 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
3938 case V_008F0C_BUF_DATA_FORMAT_16
:
3939 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
3940 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
3941 case V_008F0C_BUF_DATA_FORMAT_32
:
3942 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
3943 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
3945 unreachable("shouldn't reach here");
3946 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
3949 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3950 * so we may need to fix it up. */
3951 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
3953 Builder
bld(ctx
->program
, ctx
->block
);
3955 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
3956 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
3958 /* For the integer-like cases, do a natural sign extension.
3960 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3961 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3964 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
3965 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
3967 /* Convert back to the right type. */
3968 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
3969 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3970 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
3971 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
3972 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
3973 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3979 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3981 Builder
bld(ctx
->program
, ctx
->block
);
3982 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3983 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
3985 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3986 if (off_instr
->type
!= nir_instr_type_load_const
) {
3987 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3988 nir_print_instr(off_instr
, stderr
);
3989 fprintf(stderr
, "\n");
3991 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
3993 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
3995 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
3996 unsigned component
= nir_intrinsic_component(instr
);
3997 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
3998 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
3999 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4000 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4002 unsigned dfmt
= attrib_format
& 0xf;
4003 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4004 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4006 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4007 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4008 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4009 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4011 num_channels
= MAX2(num_channels
, 3);
4013 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4014 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4017 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4018 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4019 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4021 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4023 Temp divided
= bld
.tmp(v1
);
4024 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4025 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4027 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4030 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4033 index
= bld
.vadd32(bld
.def(v1
),
4034 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4035 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4038 Temp channels
[num_channels
];
4039 unsigned channel_start
= 0;
4040 bool direct_fetch
= false;
4042 /* skip unused channels at the start */
4043 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4044 channel_start
= ffs(mask
) - 1;
4045 for (unsigned i
= 0; i
< channel_start
; i
++)
4046 channels
[i
] = Temp(0, s1
);
4047 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4048 num_channels
= 3 - (ffs(mask
) - 1);
4052 while (channel_start
< num_channels
) {
4053 unsigned fetch_size
= num_channels
- channel_start
;
4054 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4055 bool expanded
= false;
4057 /* use MUBUF when possible to avoid possible alignment issues */
4058 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4059 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4060 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4061 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4062 vtx_info
->chan_byte_size
== 4;
4063 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4065 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4067 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4068 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4074 Temp fetch_index
= index
;
4075 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4076 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4077 fetch_offset
= fetch_offset
% attrib_stride
;
4080 Operand
soffset(0u);
4081 if (fetch_offset
>= 4096) {
4082 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4083 fetch_offset
%= 4096;
4087 switch (fetch_size
) {
4089 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4092 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4095 assert(ctx
->options
->chip_class
>= GFX7
||
4096 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4097 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4100 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4103 unreachable("Unimplemented load_input vector size");
4107 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4108 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4109 num_channels
<= 3)) {
4110 direct_fetch
= true;
4113 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4117 Instruction
*mubuf
= bld
.mubuf(opcode
,
4118 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4119 fetch_offset
, false, true).instr
;
4120 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4122 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4123 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4124 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4125 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4128 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4130 if (fetch_size
== 1) {
4131 channels
[channel_start
] = fetch_dst
;
4133 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4134 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4137 channel_start
+= fetch_size
;
4140 if (!direct_fetch
) {
4141 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4142 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4144 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4145 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4146 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4148 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4149 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4150 unsigned num_temp
= 0;
4151 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4152 unsigned idx
= i
+ component
;
4153 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4154 Temp channel
= channels
[swizzle
[idx
]];
4155 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4156 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4157 vec
->operands
[i
] = Operand(channel
);
4161 } else if (is_float
&& idx
== 3) {
4162 vec
->operands
[i
] = Operand(0x3f800000u
);
4163 } else if (!is_float
&& idx
== 3) {
4164 vec
->operands
[i
] = Operand(1u);
4166 vec
->operands
[i
] = Operand(0u);
4169 vec
->definitions
[0] = Definition(dst
);
4170 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4171 emit_split_vector(ctx
, dst
, dst
.size());
4173 if (num_temp
== dst
.size())
4174 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4176 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4177 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4178 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4179 if (off_instr
->type
!= nir_instr_type_load_const
||
4180 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4181 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4182 nir_print_instr(off_instr
, stderr
);
4183 fprintf(stderr
, "\n");
4186 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4187 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4189 assert(offset
->u32
== 0);
4191 /* the lower 15bit of the prim_mask contain the offset into LDS
4192 * while the upper bits contain the number of prims */
4193 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4194 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4195 Builder
bld(ctx
->program
, ctx
->block
);
4196 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4197 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4198 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4199 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4200 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4203 unsigned idx
= nir_intrinsic_base(instr
);
4204 unsigned component
= nir_intrinsic_component(instr
);
4205 unsigned vertex_id
= 2; /* P0 */
4207 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4208 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4209 switch (src0
->u32
) {
4211 vertex_id
= 2; /* P0 */
4214 vertex_id
= 0; /* P10 */
4217 vertex_id
= 1; /* P20 */
4220 unreachable("invalid vertex index");
4224 if (dst
.size() == 1) {
4225 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4227 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4228 for (unsigned i
= 0; i
< dst
.size(); i
++)
4229 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4230 vec
->definitions
[0] = Definition(dst
);
4231 bld
.insert(std::move(vec
));
4234 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4235 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4236 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4237 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4238 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4240 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4242 unreachable("Shader stage not implemented");
4246 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4248 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4250 Builder
bld(ctx
->program
, ctx
->block
);
4251 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4254 if (!nir_src_is_const(*vertex_src
)) {
4255 /* better code could be created, but this case probably doesn't happen
4256 * much in practice */
4257 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4258 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4261 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4262 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4264 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4266 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4269 if (vertex_offset
.id()) {
4270 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4271 Operand(i
), indirect_vertex
);
4272 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4274 vertex_offset
= elem
;
4278 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4279 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4281 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4282 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4283 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4284 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4285 Operand((vertex
% 2u) * 16u), Operand(16u));
4287 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4290 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4291 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4292 return offset_mul(ctx
, offs
, 4u);
4295 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4297 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4299 Builder
bld(ctx
->program
, ctx
->block
);
4300 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4301 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4303 if (ctx
->stage
== geometry_gs
) {
4304 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4305 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4306 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4307 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4308 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4309 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4310 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4312 unreachable("Unsupported GS stage.");
4316 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4318 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4320 Builder
bld(ctx
->program
, ctx
->block
);
4321 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4323 if (load_input_from_temps(ctx
, instr
, dst
))
4326 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4327 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4328 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4330 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4333 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4335 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4337 Builder
bld(ctx
->program
, ctx
->block
);
4339 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4340 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4341 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4343 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4344 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4346 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4349 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4351 switch (ctx
->shader
->info
.stage
) {
4352 case MESA_SHADER_GEOMETRY
:
4353 visit_load_gs_per_vertex_input(ctx
, instr
);
4355 case MESA_SHADER_TESS_CTRL
:
4356 visit_load_tcs_per_vertex_input(ctx
, instr
);
4358 case MESA_SHADER_TESS_EVAL
:
4359 visit_load_tes_per_vertex_input(ctx
, instr
);
4362 unreachable("Unimplemented shader stage");
4366 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4368 visit_load_tcs_output(ctx
, instr
, true);
4371 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4373 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4374 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4376 visit_store_tcs_output(ctx
, instr
, true);
4379 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4381 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4383 Builder
bld(ctx
->program
, ctx
->block
);
4384 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4386 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4387 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4390 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4391 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4392 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4393 tes_w
= Operand(tmp
);
4396 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4397 emit_split_vector(ctx
, tess_coord
, 3);
4400 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4402 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4403 Builder
bld(ctx
->program
, ctx
->block
);
4404 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4405 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4406 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4409 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4413 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4415 Builder
bld(ctx
->program
, ctx
->block
);
4416 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4417 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4418 index
= bld
.as_uniform(index
);
4419 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4420 unsigned binding
= nir_intrinsic_binding(instr
);
4423 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4424 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4425 unsigned offset
= layout
->binding
[binding
].offset
;
4427 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4428 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4429 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4430 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4431 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4434 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4435 stride
= layout
->binding
[binding
].size
;
4438 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4439 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4441 if (nir_const_index
) {
4442 const_index
= const_index
* stride
;
4443 } else if (index
.type() == RegType::vgpr
) {
4444 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4445 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4447 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4451 if (nir_const_index
) {
4452 const_index
= const_index
+ offset
;
4453 } else if (index
.type() == RegType::vgpr
) {
4454 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4456 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4460 if (nir_const_index
&& const_index
== 0) {
4462 } else if (index
.type() == RegType::vgpr
) {
4463 index
= bld
.vadd32(bld
.def(v1
),
4464 nir_const_index
? Operand(const_index
) : Operand(index
),
4467 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4468 nir_const_index
? Operand(const_index
) : Operand(index
),
4472 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4475 void load_buffer(isel_context
*ctx
, unsigned num_components
, Temp dst
,
4476 Temp rsrc
, Temp offset
, bool glc
=false, bool readonly
=true)
4478 Builder
bld(ctx
->program
, ctx
->block
);
4480 unsigned num_bytes
= dst
.size() * 4;
4481 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4484 if (dst
.type() == RegType::vgpr
|| (ctx
->options
->chip_class
< GFX8
&& !readonly
)) {
4485 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4486 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4487 unsigned const_offset
= 0;
4489 Temp lower
= Temp();
4490 if (num_bytes
> 16) {
4491 assert(num_components
== 3 || num_components
== 4);
4492 op
= aco_opcode::buffer_load_dwordx4
;
4493 lower
= bld
.tmp(v4
);
4494 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4495 mubuf
->definitions
[0] = Definition(lower
);
4496 mubuf
->operands
[0] = Operand(rsrc
);
4497 mubuf
->operands
[1] = vaddr
;
4498 mubuf
->operands
[2] = soffset
;
4499 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4502 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4503 mubuf
->can_reorder
= readonly
;
4504 bld
.insert(std::move(mubuf
));
4505 emit_split_vector(ctx
, lower
, 2);
4508 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4509 /* GFX6 doesn't support loading vec3, expand to vec4. */
4513 switch (num_bytes
) {
4515 op
= aco_opcode::buffer_load_dword
;
4518 op
= aco_opcode::buffer_load_dwordx2
;
4521 assert(ctx
->options
->chip_class
> GFX6
);
4522 op
= aco_opcode::buffer_load_dwordx3
;
4525 op
= aco_opcode::buffer_load_dwordx4
;
4528 unreachable("Load SSBO not implemented for this size.");
4530 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4531 mubuf
->operands
[0] = Operand(rsrc
);
4532 mubuf
->operands
[1] = vaddr
;
4533 mubuf
->operands
[2] = soffset
;
4534 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4537 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4538 mubuf
->can_reorder
= readonly
;
4539 mubuf
->offset
= const_offset
;
4540 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4542 if (dst
.size() > 4) {
4543 assert(lower
!= Temp());
4544 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4545 instr
->definitions
[0] = Definition(upper
);
4546 bld
.insert(std::move(instr
));
4547 if (dst
.size() == 8)
4548 emit_split_vector(ctx
, upper
, 2);
4549 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4550 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4551 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4552 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4553 if (dst
.size() == 8)
4554 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4555 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4556 Temp vec
= bld
.tmp(v4
);
4557 instr
->definitions
[0] = Definition(vec
);
4558 bld
.insert(std::move(instr
));
4559 emit_split_vector(ctx
, vec
, 4);
4561 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4562 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4563 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4564 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4567 if (dst
.type() == RegType::sgpr
) {
4568 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4569 instr
->definitions
[0] = Definition(vec
);
4570 bld
.insert(std::move(instr
));
4571 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4573 instr
->definitions
[0] = Definition(dst
);
4574 bld
.insert(std::move(instr
));
4575 emit_split_vector(ctx
, dst
, num_components
);
4578 switch (num_bytes
) {
4580 op
= aco_opcode::s_buffer_load_dword
;
4583 op
= aco_opcode::s_buffer_load_dwordx2
;
4587 op
= aco_opcode::s_buffer_load_dwordx4
;
4591 op
= aco_opcode::s_buffer_load_dwordx8
;
4594 unreachable("Load SSBO not implemented for this size.");
4596 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4597 load
->operands
[0] = Operand(rsrc
);
4598 load
->operands
[1] = Operand(bld
.as_uniform(offset
));
4599 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4600 load
->definitions
[0] = Definition(dst
);
4603 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4604 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4605 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4608 if (dst
.size() == 3) {
4609 Temp vec
= bld
.tmp(s4
);
4610 load
->definitions
[0] = Definition(vec
);
4611 bld
.insert(std::move(load
));
4612 emit_split_vector(ctx
, vec
, 4);
4614 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4615 emit_extract_vector(ctx
, vec
, 0, s1
),
4616 emit_extract_vector(ctx
, vec
, 1, s1
),
4617 emit_extract_vector(ctx
, vec
, 2, s1
));
4618 } else if (dst
.size() == 6) {
4619 Temp vec
= bld
.tmp(s8
);
4620 load
->definitions
[0] = Definition(vec
);
4621 bld
.insert(std::move(load
));
4622 emit_split_vector(ctx
, vec
, 4);
4624 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4625 emit_extract_vector(ctx
, vec
, 0, s2
),
4626 emit_extract_vector(ctx
, vec
, 1, s2
),
4627 emit_extract_vector(ctx
, vec
, 2, s2
));
4629 bld
.insert(std::move(load
));
4631 emit_split_vector(ctx
, dst
, num_components
);
4635 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4637 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4638 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4640 Builder
bld(ctx
->program
, ctx
->block
);
4642 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4643 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4644 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4645 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4647 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4648 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4649 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4650 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4651 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4652 if (ctx
->options
->chip_class
>= GFX10
) {
4653 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4654 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4655 S_008F0C_RESOURCE_LEVEL(1);
4657 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4658 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4660 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4661 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4662 Operand(0xFFFFFFFFu
),
4663 Operand(desc_type
));
4664 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4665 rsrc
, upper_dwords
);
4667 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4668 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4671 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4674 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4676 Builder
bld(ctx
->program
, ctx
->block
);
4677 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4678 unsigned offset
= nir_intrinsic_base(instr
);
4679 unsigned count
= instr
->dest
.ssa
.num_components
;
4680 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4682 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4683 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4684 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4685 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4686 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4687 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4688 for (unsigned i
= 0; i
< count
; ++i
) {
4689 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4690 vec
->operands
[i
] = Operand
{elems
[i
]};
4692 vec
->definitions
[0] = Definition(dst
);
4693 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4694 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4699 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4700 if (offset
!= 0) // TODO check if index != 0 as well
4701 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4702 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4705 bool aligned
= true;
4707 if (instr
->dest
.ssa
.bit_size
== 8) {
4708 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4709 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4711 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4712 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4713 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4715 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4720 switch (vec
.size()) {
4722 op
= aco_opcode::s_load_dword
;
4725 op
= aco_opcode::s_load_dwordx2
;
4731 op
= aco_opcode::s_load_dwordx4
;
4737 op
= aco_opcode::s_load_dwordx8
;
4740 unreachable("unimplemented or forbidden load_push_constant.");
4743 bld
.smem(op
, Definition(vec
), ptr
, index
);
4746 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
4747 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4752 emit_split_vector(ctx
, vec
, 4);
4753 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
4754 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4755 emit_extract_vector(ctx
, vec
, 0, rc
),
4756 emit_extract_vector(ctx
, vec
, 1, rc
),
4757 emit_extract_vector(ctx
, vec
, 2, rc
));
4760 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4763 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4765 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4767 Builder
bld(ctx
->program
, ctx
->block
);
4769 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4770 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4771 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4772 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4773 if (ctx
->options
->chip_class
>= GFX10
) {
4774 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4775 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4776 S_008F0C_RESOURCE_LEVEL(1);
4778 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4779 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4782 unsigned base
= nir_intrinsic_base(instr
);
4783 unsigned range
= nir_intrinsic_range(instr
);
4785 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4786 if (base
&& offset
.type() == RegType::sgpr
)
4787 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
4788 else if (base
&& offset
.type() == RegType::vgpr
)
4789 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
4791 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4792 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
4793 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
4794 Operand(desc_type
));
4796 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, offset
);
4799 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4801 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4802 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4804 ctx
->program
->needs_exact
= true;
4806 // TODO: optimize uniform conditions
4807 Builder
bld(ctx
->program
, ctx
->block
);
4808 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4809 assert(src
.regClass() == bld
.lm
);
4810 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
4811 bld
.pseudo(aco_opcode::p_discard_if
, src
);
4812 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4816 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
4818 Builder
bld(ctx
->program
, ctx
->block
);
4820 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4821 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4823 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
4824 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
4826 if (ctx
->block
->loop_nest_depth
&&
4827 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
4828 /* we handle discards the same way as jump instructions */
4829 append_logical_end(ctx
->block
);
4831 /* in loops, discard behaves like break */
4832 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
4833 ctx
->block
->kind
|= block_kind_discard
;
4836 /* uniform discard - loop ends here */
4837 assert(nir_instr_is_last(&instr
->instr
));
4838 ctx
->block
->kind
|= block_kind_uniform
;
4839 ctx
->cf_info
.has_branch
= true;
4840 bld
.branch(aco_opcode::p_branch
);
4841 add_linear_edge(ctx
->block
->index
, linear_target
);
4845 /* we add a break right behind the discard() instructions */
4846 ctx
->block
->kind
|= block_kind_break
;
4847 unsigned idx
= ctx
->block
->index
;
4849 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
4850 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
4852 /* remove critical edges from linear CFG */
4853 bld
.branch(aco_opcode::p_branch
);
4854 Block
* break_block
= ctx
->program
->create_and_insert_block();
4855 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4856 break_block
->kind
|= block_kind_uniform
;
4857 add_linear_edge(idx
, break_block
);
4858 add_linear_edge(break_block
->index
, linear_target
);
4859 bld
.reset(break_block
);
4860 bld
.branch(aco_opcode::p_branch
);
4862 Block
* continue_block
= ctx
->program
->create_and_insert_block();
4863 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4864 add_linear_edge(idx
, continue_block
);
4865 append_logical_start(continue_block
);
4866 ctx
->block
= continue_block
;
4871 /* it can currently happen that NIR doesn't remove the unreachable code */
4872 if (!nir_instr_is_last(&instr
->instr
)) {
4873 ctx
->program
->needs_exact
= true;
4874 /* save exec somewhere temporarily so that it doesn't get
4875 * overwritten before the discard from outer exec masks */
4876 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
4877 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
4878 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4882 /* This condition is incorrect for uniformly branched discards in a loop
4883 * predicated by a divergent condition, but the above code catches that case
4884 * and the discard would end up turning into a discard_if.
4894 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
4895 /* program just ends here */
4896 ctx
->block
->kind
|= block_kind_uniform
;
4897 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
4898 0 /* enabled mask */, 9 /* dest */,
4899 false /* compressed */, true/* done */, true /* valid mask */);
4900 bld
.sopp(aco_opcode::s_endpgm
);
4901 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4903 ctx
->block
->kind
|= block_kind_discard
;
4904 /* branch and linear edge is added by visit_if() */
4908 enum aco_descriptor_type
{
4919 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
4920 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4922 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
4923 return dim
== ac_image_cube
||
4924 dim
== ac_image_1darray
||
4925 dim
== ac_image_2darray
||
4926 dim
== ac_image_2darraymsaa
;
4929 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
4930 enum aco_descriptor_type desc_type
,
4931 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
4933 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4934 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4935 if (it != ctx->tex_desc.end())
4938 Temp index
= Temp();
4939 bool index_set
= false;
4940 unsigned constant_index
= 0;
4941 unsigned descriptor_set
;
4942 unsigned base_index
;
4943 Builder
bld(ctx
->program
, ctx
->block
);
4946 assert(tex_instr
&& !image
);
4948 base_index
= tex_instr
->sampler_index
;
4950 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
4951 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
4955 assert(deref_instr
->deref_type
== nir_deref_type_array
);
4956 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
4958 constant_index
+= array_size
* const_value
->u32
;
4960 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
4961 if (indirect
.type() == RegType::vgpr
)
4962 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
4964 if (array_size
!= 1)
4965 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
4971 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
4975 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
4977 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
4978 base_index
= deref_instr
->var
->data
.binding
;
4981 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
4982 list
= convert_pointer_to_64_bit(ctx
, list
);
4984 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
4985 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
4986 unsigned offset
= binding
->offset
;
4987 unsigned stride
= binding
->size
;
4991 assert(base_index
< layout
->binding_count
);
4993 switch (desc_type
) {
4994 case ACO_DESC_IMAGE
:
4996 opcode
= aco_opcode::s_load_dwordx8
;
4998 case ACO_DESC_FMASK
:
5000 opcode
= aco_opcode::s_load_dwordx8
;
5003 case ACO_DESC_SAMPLER
:
5005 opcode
= aco_opcode::s_load_dwordx4
;
5006 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5007 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5009 case ACO_DESC_BUFFER
:
5011 opcode
= aco_opcode::s_load_dwordx4
;
5013 case ACO_DESC_PLANE_0
:
5014 case ACO_DESC_PLANE_1
:
5016 opcode
= aco_opcode::s_load_dwordx8
;
5017 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5019 case ACO_DESC_PLANE_2
:
5021 opcode
= aco_opcode::s_load_dwordx4
;
5025 unreachable("invalid desc_type\n");
5028 offset
+= constant_index
* stride
;
5030 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5031 (!index_set
|| binding
->immutable_samplers_equal
)) {
5032 if (binding
->immutable_samplers_equal
)
5035 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5036 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5037 Operand(samplers
[constant_index
* 4 + 0]),
5038 Operand(samplers
[constant_index
* 4 + 1]),
5039 Operand(samplers
[constant_index
* 4 + 2]),
5040 Operand(samplers
[constant_index
* 4 + 3]));
5045 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5047 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5048 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5051 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5053 if (desc_type
== ACO_DESC_PLANE_2
) {
5055 for (unsigned i
= 0; i
< 8; i
++)
5056 components
[i
] = bld
.tmp(s1
);
5057 bld
.pseudo(aco_opcode::p_split_vector
,
5058 Definition(components
[0]),
5059 Definition(components
[1]),
5060 Definition(components
[2]),
5061 Definition(components
[3]),
5064 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5065 bld
.pseudo(aco_opcode::p_split_vector
,
5066 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5067 Definition(components
[4]),
5068 Definition(components
[5]),
5069 Definition(components
[6]),
5070 Definition(components
[7]),
5073 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5074 components
[0], components
[1], components
[2], components
[3],
5075 components
[4], components
[5], components
[6], components
[7]);
5081 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5084 case GLSL_SAMPLER_DIM_BUF
:
5086 case GLSL_SAMPLER_DIM_1D
:
5087 return array
? 2 : 1;
5088 case GLSL_SAMPLER_DIM_2D
:
5089 return array
? 3 : 2;
5090 case GLSL_SAMPLER_DIM_MS
:
5091 return array
? 4 : 3;
5092 case GLSL_SAMPLER_DIM_3D
:
5093 case GLSL_SAMPLER_DIM_CUBE
:
5095 case GLSL_SAMPLER_DIM_RECT
:
5096 case GLSL_SAMPLER_DIM_SUBPASS
:
5098 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5107 /* Adjust the sample index according to FMASK.
5109 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5110 * which is the identity mapping. Each nibble says which physical sample
5111 * should be fetched to get that sample.
5113 * For example, 0x11111100 means there are only 2 samples stored and
5114 * the second sample covers 3/4 of the pixel. When reading samples 0
5115 * and 1, return physical sample 0 (determined by the first two 0s
5116 * in FMASK), otherwise return physical sample 1.
5118 * The sample index should be adjusted as follows:
5119 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5121 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5123 Builder
bld(ctx
->program
, ctx
->block
);
5124 Temp fmask
= bld
.tmp(v1
);
5125 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5126 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5129 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5130 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5131 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5132 load
->operands
[0] = Operand(fmask_desc_ptr
);
5133 load
->operands
[1] = Operand(s4
); /* no sampler */
5134 load
->operands
[2] = Operand(coord
);
5135 load
->definitions
[0] = Definition(fmask
);
5142 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5143 ctx
->block
->instructions
.emplace_back(std::move(load
));
5145 Operand sample_index4
;
5146 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5147 sample_index4
= Operand(sample_index
.constantValue() << 2);
5148 } else if (sample_index
.regClass() == s1
) {
5149 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5151 assert(sample_index
.regClass() == v1
);
5152 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5156 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5157 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5158 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5159 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5161 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5163 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5164 * resource descriptor is 0 (invalid),
5166 Temp compare
= bld
.tmp(bld
.lm
);
5167 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5168 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5170 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5172 /* Replace the MSAA sample index. */
5173 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5176 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5179 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5180 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5181 bool is_array
= glsl_sampler_type_is_array(type
);
5182 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5183 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5184 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5185 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5186 int count
= image_type_to_components_count(dim
, is_array
);
5187 std::vector
<Temp
> coords(count
);
5188 Builder
bld(ctx
->program
, ctx
->block
);
5192 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5193 /* get sample index */
5194 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5195 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5196 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5197 std::vector
<Temp
> fmask_load_address
;
5198 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5199 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5201 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5202 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5204 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5209 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5210 coords
.resize(coords
.size() + 1);
5211 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5213 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5215 for (int i
= 0; i
< count
; i
++)
5216 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5219 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5220 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5221 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5222 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5225 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5228 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5229 for (unsigned i
= 0; i
< coords
.size(); i
++)
5230 vec
->operands
[i
] = Operand(coords
[i
]);
5231 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5232 vec
->definitions
[0] = Definition(res
);
5233 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5238 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5240 Builder
bld(ctx
->program
, ctx
->block
);
5241 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5242 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5243 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5244 bool is_array
= glsl_sampler_type_is_array(type
);
5245 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5247 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5248 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5249 unsigned num_channels
= util_last_bit(mask
);
5250 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5251 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5254 switch (num_channels
) {
5256 opcode
= aco_opcode::buffer_load_format_x
;
5259 opcode
= aco_opcode::buffer_load_format_xy
;
5262 opcode
= aco_opcode::buffer_load_format_xyz
;
5265 opcode
= aco_opcode::buffer_load_format_xyzw
;
5268 unreachable(">4 channel buffer image load");
5270 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5271 load
->operands
[0] = Operand(rsrc
);
5272 load
->operands
[1] = Operand(vindex
);
5273 load
->operands
[2] = Operand((uint32_t) 0);
5275 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5278 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5279 load
->definitions
[0] = Definition(tmp
);
5281 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5282 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5283 load
->barrier
= barrier_image
;
5284 ctx
->block
->instructions
.emplace_back(std::move(load
));
5286 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5290 Temp coords
= get_image_coords(ctx
, instr
, type
);
5291 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5293 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5294 unsigned num_components
= util_bitcount(dmask
);
5296 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5299 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5301 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5302 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5304 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5305 load
->operands
[0] = Operand(resource
);
5306 load
->operands
[1] = Operand(s4
); /* no sampler */
5307 load
->operands
[2] = Operand(coords
);
5308 load
->definitions
[0] = Definition(tmp
);
5309 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5310 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5311 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5312 load
->dmask
= dmask
;
5314 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5315 load
->barrier
= barrier_image
;
5316 ctx
->block
->instructions
.emplace_back(std::move(load
));
5318 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5322 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5324 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5325 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5326 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5327 bool is_array
= glsl_sampler_type_is_array(type
);
5328 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5330 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5332 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5333 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5334 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5336 switch (data
.size()) {
5338 opcode
= aco_opcode::buffer_store_format_x
;
5341 opcode
= aco_opcode::buffer_store_format_xy
;
5344 opcode
= aco_opcode::buffer_store_format_xyz
;
5347 opcode
= aco_opcode::buffer_store_format_xyzw
;
5350 unreachable(">4 channel buffer image store");
5352 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5353 store
->operands
[0] = Operand(rsrc
);
5354 store
->operands
[1] = Operand(vindex
);
5355 store
->operands
[2] = Operand((uint32_t) 0);
5356 store
->operands
[3] = Operand(data
);
5357 store
->idxen
= true;
5360 store
->disable_wqm
= true;
5361 store
->barrier
= barrier_image
;
5362 ctx
->program
->needs_exact
= true;
5363 ctx
->block
->instructions
.emplace_back(std::move(store
));
5367 assert(data
.type() == RegType::vgpr
);
5368 Temp coords
= get_image_coords(ctx
, instr
, type
);
5369 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5371 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5372 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5374 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5375 store
->operands
[0] = Operand(resource
);
5376 store
->operands
[1] = Operand(data
);
5377 store
->operands
[2] = Operand(coords
);
5380 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5381 store
->dmask
= (1 << data
.size()) - 1;
5383 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5384 store
->disable_wqm
= true;
5385 store
->barrier
= barrier_image
;
5386 ctx
->program
->needs_exact
= true;
5387 ctx
->block
->instructions
.emplace_back(std::move(store
));
5391 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5393 /* return the previous value if dest is ever used */
5394 bool return_previous
= false;
5395 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5396 return_previous
= true;
5399 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5400 return_previous
= true;
5404 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5405 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5406 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5407 bool is_array
= glsl_sampler_type_is_array(type
);
5408 Builder
bld(ctx
->program
, ctx
->block
);
5410 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5411 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5413 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5414 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5416 aco_opcode buf_op
, image_op
;
5417 switch (instr
->intrinsic
) {
5418 case nir_intrinsic_image_deref_atomic_add
:
5419 buf_op
= aco_opcode::buffer_atomic_add
;
5420 image_op
= aco_opcode::image_atomic_add
;
5422 case nir_intrinsic_image_deref_atomic_umin
:
5423 buf_op
= aco_opcode::buffer_atomic_umin
;
5424 image_op
= aco_opcode::image_atomic_umin
;
5426 case nir_intrinsic_image_deref_atomic_imin
:
5427 buf_op
= aco_opcode::buffer_atomic_smin
;
5428 image_op
= aco_opcode::image_atomic_smin
;
5430 case nir_intrinsic_image_deref_atomic_umax
:
5431 buf_op
= aco_opcode::buffer_atomic_umax
;
5432 image_op
= aco_opcode::image_atomic_umax
;
5434 case nir_intrinsic_image_deref_atomic_imax
:
5435 buf_op
= aco_opcode::buffer_atomic_smax
;
5436 image_op
= aco_opcode::image_atomic_smax
;
5438 case nir_intrinsic_image_deref_atomic_and
:
5439 buf_op
= aco_opcode::buffer_atomic_and
;
5440 image_op
= aco_opcode::image_atomic_and
;
5442 case nir_intrinsic_image_deref_atomic_or
:
5443 buf_op
= aco_opcode::buffer_atomic_or
;
5444 image_op
= aco_opcode::image_atomic_or
;
5446 case nir_intrinsic_image_deref_atomic_xor
:
5447 buf_op
= aco_opcode::buffer_atomic_xor
;
5448 image_op
= aco_opcode::image_atomic_xor
;
5450 case nir_intrinsic_image_deref_atomic_exchange
:
5451 buf_op
= aco_opcode::buffer_atomic_swap
;
5452 image_op
= aco_opcode::image_atomic_swap
;
5454 case nir_intrinsic_image_deref_atomic_comp_swap
:
5455 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5456 image_op
= aco_opcode::image_atomic_cmpswap
;
5459 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5462 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5464 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5465 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5466 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5467 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5468 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5469 mubuf
->operands
[0] = Operand(resource
);
5470 mubuf
->operands
[1] = Operand(vindex
);
5471 mubuf
->operands
[2] = Operand((uint32_t)0);
5472 mubuf
->operands
[3] = Operand(data
);
5473 if (return_previous
)
5474 mubuf
->definitions
[0] = Definition(dst
);
5476 mubuf
->idxen
= true;
5477 mubuf
->glc
= return_previous
;
5478 mubuf
->dlc
= false; /* Not needed for atomics */
5479 mubuf
->disable_wqm
= true;
5480 mubuf
->barrier
= barrier_image
;
5481 ctx
->program
->needs_exact
= true;
5482 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5486 Temp coords
= get_image_coords(ctx
, instr
, type
);
5487 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5488 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5489 mimg
->operands
[0] = Operand(resource
);
5490 mimg
->operands
[1] = Operand(data
);
5491 mimg
->operands
[2] = Operand(coords
);
5492 if (return_previous
)
5493 mimg
->definitions
[0] = Definition(dst
);
5494 mimg
->glc
= return_previous
;
5495 mimg
->dlc
= false; /* Not needed for atomics */
5496 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5497 mimg
->dmask
= (1 << data
.size()) - 1;
5499 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5500 mimg
->disable_wqm
= true;
5501 mimg
->barrier
= barrier_image
;
5502 ctx
->program
->needs_exact
= true;
5503 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5507 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5509 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5510 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5511 Builder
bld(ctx
->program
, ctx
->block
);
5513 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5515 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5516 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5518 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5519 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5521 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5522 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5524 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5525 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5526 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5527 if (dst
.type() == RegType::vgpr
)
5528 bld
.copy(Definition(dst
), shr_dst
);
5530 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5532 emit_extract_vector(ctx
, desc
, 2, dst
);
5536 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5538 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5539 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5540 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5541 bool is_array
= glsl_sampler_type_is_array(type
);
5542 Builder
bld(ctx
->program
, ctx
->block
);
5544 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5545 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5546 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5550 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5553 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5555 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5557 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5558 mimg
->operands
[0] = Operand(resource
);
5559 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5560 mimg
->operands
[2] = Operand(lod
);
5561 uint8_t& dmask
= mimg
->dmask
;
5562 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5563 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5564 mimg
->da
= glsl_sampler_type_is_array(type
);
5565 mimg
->can_reorder
= true;
5566 Definition
& def
= mimg
->definitions
[0];
5567 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5569 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5570 glsl_sampler_type_is_array(type
)) {
5572 assert(instr
->dest
.ssa
.num_components
== 3);
5573 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5574 def
= Definition(tmp
);
5575 emit_split_vector(ctx
, tmp
, 3);
5577 /* divide 3rd value by 6 by multiplying with magic number */
5578 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5579 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5581 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5582 emit_extract_vector(ctx
, tmp
, 0, v1
),
5583 emit_extract_vector(ctx
, tmp
, 1, v1
),
5586 } else if (ctx
->options
->chip_class
== GFX9
&&
5587 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5588 glsl_sampler_type_is_array(type
)) {
5589 assert(instr
->dest
.ssa
.num_components
== 2);
5590 def
= Definition(dst
);
5593 def
= Definition(dst
);
5596 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5599 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5601 Builder
bld(ctx
->program
, ctx
->block
);
5602 unsigned num_components
= instr
->num_components
;
5604 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5605 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5606 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5608 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5609 load_buffer(ctx
, num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), glc
, false);
5612 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5614 Builder
bld(ctx
->program
, ctx
->block
);
5615 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5616 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5617 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5618 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5620 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5621 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5623 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5624 ctx
->options
->chip_class
>= GFX8
;
5626 offset
= bld
.as_uniform(offset
);
5627 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5631 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5632 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5633 /* GFX6 doesn't support storing vec3, split it. */
5634 writemask
|= 1u << (start
+ 2);
5637 int num_bytes
= count
* elem_size_bytes
;
5639 if (num_bytes
> 16) {
5640 assert(elem_size_bytes
== 8);
5641 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5646 // TODO: check alignment of sub-dword stores
5647 // TODO: split 3 bytes. there is no store instruction for that
5650 if (count
!= instr
->num_components
) {
5651 emit_split_vector(ctx
, data
, instr
->num_components
);
5652 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5653 for (int i
= 0; i
< count
; i
++) {
5654 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5655 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5657 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5658 vec
->definitions
[0] = Definition(write_data
);
5659 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5660 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5661 assert(num_bytes
% 4 == 0);
5662 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5663 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5664 assert(num_bytes
% 4 == 0);
5665 write_data
= bld
.as_uniform(data
);
5670 aco_opcode vmem_op
, smem_op
;
5671 switch (num_bytes
) {
5673 vmem_op
= aco_opcode::buffer_store_dword
;
5674 smem_op
= aco_opcode::s_buffer_store_dword
;
5677 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5678 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5681 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5682 smem_op
= aco_opcode::last_opcode
;
5683 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5686 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5687 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5690 unreachable("Store SSBO not implemented for this size.");
5692 if (ctx
->stage
== fragment_fs
)
5693 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5696 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5697 store
->operands
[0] = Operand(rsrc
);
5699 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5700 offset
, Operand(start
* elem_size_bytes
));
5701 store
->operands
[1] = Operand(off
);
5703 store
->operands
[1] = Operand(offset
);
5705 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5706 store
->operands
[1].setFixed(m0
);
5707 store
->operands
[2] = Operand(write_data
);
5708 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5710 store
->disable_wqm
= true;
5711 store
->barrier
= barrier_buffer
;
5712 ctx
->block
->instructions
.emplace_back(std::move(store
));
5713 ctx
->program
->wb_smem_l1_on_end
= true;
5714 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5715 ctx
->block
->kind
|= block_kind_needs_lowering
;
5716 ctx
->program
->needs_exact
= true;
5719 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
5720 store
->operands
[0] = Operand(rsrc
);
5721 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5722 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5723 store
->operands
[3] = Operand(write_data
);
5724 store
->offset
= start
* elem_size_bytes
;
5725 store
->offen
= (offset
.type() == RegType::vgpr
);
5726 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5728 store
->disable_wqm
= true;
5729 store
->barrier
= barrier_buffer
;
5730 ctx
->program
->needs_exact
= true;
5731 ctx
->block
->instructions
.emplace_back(std::move(store
));
5736 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5738 /* return the previous value if dest is ever used */
5739 bool return_previous
= false;
5740 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5741 return_previous
= true;
5744 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5745 return_previous
= true;
5749 Builder
bld(ctx
->program
, ctx
->block
);
5750 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5752 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
5753 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
5754 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
5756 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5757 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5758 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5760 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5762 aco_opcode op32
, op64
;
5763 switch (instr
->intrinsic
) {
5764 case nir_intrinsic_ssbo_atomic_add
:
5765 op32
= aco_opcode::buffer_atomic_add
;
5766 op64
= aco_opcode::buffer_atomic_add_x2
;
5768 case nir_intrinsic_ssbo_atomic_imin
:
5769 op32
= aco_opcode::buffer_atomic_smin
;
5770 op64
= aco_opcode::buffer_atomic_smin_x2
;
5772 case nir_intrinsic_ssbo_atomic_umin
:
5773 op32
= aco_opcode::buffer_atomic_umin
;
5774 op64
= aco_opcode::buffer_atomic_umin_x2
;
5776 case nir_intrinsic_ssbo_atomic_imax
:
5777 op32
= aco_opcode::buffer_atomic_smax
;
5778 op64
= aco_opcode::buffer_atomic_smax_x2
;
5780 case nir_intrinsic_ssbo_atomic_umax
:
5781 op32
= aco_opcode::buffer_atomic_umax
;
5782 op64
= aco_opcode::buffer_atomic_umax_x2
;
5784 case nir_intrinsic_ssbo_atomic_and
:
5785 op32
= aco_opcode::buffer_atomic_and
;
5786 op64
= aco_opcode::buffer_atomic_and_x2
;
5788 case nir_intrinsic_ssbo_atomic_or
:
5789 op32
= aco_opcode::buffer_atomic_or
;
5790 op64
= aco_opcode::buffer_atomic_or_x2
;
5792 case nir_intrinsic_ssbo_atomic_xor
:
5793 op32
= aco_opcode::buffer_atomic_xor
;
5794 op64
= aco_opcode::buffer_atomic_xor_x2
;
5796 case nir_intrinsic_ssbo_atomic_exchange
:
5797 op32
= aco_opcode::buffer_atomic_swap
;
5798 op64
= aco_opcode::buffer_atomic_swap_x2
;
5800 case nir_intrinsic_ssbo_atomic_comp_swap
:
5801 op32
= aco_opcode::buffer_atomic_cmpswap
;
5802 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
5805 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5807 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
5808 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5809 mubuf
->operands
[0] = Operand(rsrc
);
5810 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5811 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5812 mubuf
->operands
[3] = Operand(data
);
5813 if (return_previous
)
5814 mubuf
->definitions
[0] = Definition(dst
);
5816 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
5817 mubuf
->glc
= return_previous
;
5818 mubuf
->dlc
= false; /* Not needed for atomics */
5819 mubuf
->disable_wqm
= true;
5820 mubuf
->barrier
= barrier_buffer
;
5821 ctx
->program
->needs_exact
= true;
5822 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5825 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5827 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5828 Builder
bld(ctx
->program
, ctx
->block
);
5829 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
5830 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
5833 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
5835 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5836 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5838 if (addr
.type() == RegType::vgpr
)
5839 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
5840 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
5843 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5845 Builder
bld(ctx
->program
, ctx
->block
);
5846 unsigned num_components
= instr
->num_components
;
5847 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
5849 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5850 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5852 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5853 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
5855 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
5856 bool global
= ctx
->options
->chip_class
>= GFX9
;
5858 if (ctx
->options
->chip_class
>= GFX7
) {
5860 switch (num_bytes
) {
5862 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
5865 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
5868 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
5871 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
5874 unreachable("load_global not implemented for this size.");
5877 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
5878 flat
->operands
[0] = Operand(addr
);
5879 flat
->operands
[1] = Operand(s1
);
5882 flat
->barrier
= barrier_buffer
;
5884 if (dst
.type() == RegType::sgpr
) {
5885 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
5886 flat
->definitions
[0] = Definition(vec
);
5887 ctx
->block
->instructions
.emplace_back(std::move(flat
));
5888 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
5890 flat
->definitions
[0] = Definition(dst
);
5891 ctx
->block
->instructions
.emplace_back(std::move(flat
));
5893 emit_split_vector(ctx
, dst
, num_components
);
5895 assert(ctx
->options
->chip_class
== GFX6
);
5897 /* GFX6 doesn't support loading vec3, expand to vec4. */
5898 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
5901 switch (num_bytes
) {
5903 op
= aco_opcode::buffer_load_dword
;
5906 op
= aco_opcode::buffer_load_dwordx2
;
5909 op
= aco_opcode::buffer_load_dwordx4
;
5912 unreachable("load_global not implemented for this size.");
5915 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
5917 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
5918 mubuf
->operands
[0] = Operand(rsrc
);
5919 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
5920 mubuf
->operands
[2] = Operand(0u);
5924 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
5925 mubuf
->disable_wqm
= false;
5926 mubuf
->barrier
= barrier_buffer
;
5927 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
5930 if (dst
.size() == 3) {
5931 Temp vec
= bld
.tmp(v4
);
5932 instr
->definitions
[0] = Definition(vec
);
5933 bld
.insert(std::move(instr
));
5934 emit_split_vector(ctx
, vec
, 4);
5936 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
5937 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
5938 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
5939 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
5942 if (dst
.type() == RegType::sgpr
) {
5943 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
5944 instr
->definitions
[0] = Definition(vec
);
5945 bld
.insert(std::move(instr
));
5946 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
5947 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
5949 instr
->definitions
[0] = Definition(dst
);
5950 bld
.insert(std::move(instr
));
5951 emit_split_vector(ctx
, dst
, num_components
);
5955 switch (num_bytes
) {
5957 op
= aco_opcode::s_load_dword
;
5960 op
= aco_opcode::s_load_dwordx2
;
5964 op
= aco_opcode::s_load_dwordx4
;
5967 unreachable("load_global not implemented for this size.");
5969 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
5970 load
->operands
[0] = Operand(addr
);
5971 load
->operands
[1] = Operand(0u);
5972 load
->definitions
[0] = Definition(dst
);
5975 load
->barrier
= barrier_buffer
;
5976 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
5978 if (dst
.size() == 3) {
5980 Temp vec
= bld
.tmp(s4
);
5981 load
->definitions
[0] = Definition(vec
);
5982 ctx
->block
->instructions
.emplace_back(std::move(load
));
5983 emit_split_vector(ctx
, vec
, 4);
5985 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5986 emit_extract_vector(ctx
, vec
, 0, s1
),
5987 emit_extract_vector(ctx
, vec
, 1, s1
),
5988 emit_extract_vector(ctx
, vec
, 2, s1
));
5990 ctx
->block
->instructions
.emplace_back(std::move(load
));
5995 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5997 Builder
bld(ctx
->program
, ctx
->block
);
5998 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6000 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6001 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6003 if (ctx
->options
->chip_class
>= GFX7
)
6004 addr
= as_vgpr(ctx
, addr
);
6006 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6009 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6010 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6011 /* GFX6 doesn't support storing vec3, split it. */
6012 writemask
|= 1u << (start
+ 2);
6015 unsigned num_bytes
= count
* elem_size_bytes
;
6017 Temp write_data
= data
;
6018 if (count
!= instr
->num_components
) {
6019 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6020 for (int i
= 0; i
< count
; i
++)
6021 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6022 write_data
= bld
.tmp(RegType::vgpr
, count
);
6023 vec
->definitions
[0] = Definition(write_data
);
6024 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6027 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6028 unsigned offset
= start
* elem_size_bytes
;
6030 if (ctx
->options
->chip_class
>= GFX7
) {
6031 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6032 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6033 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6034 Temp carry
= bld
.tmp(bld
.lm
);
6035 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6037 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6038 Operand(offset
), addr0
);
6039 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6041 carry
).def(1).setHint(vcc
);
6043 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6048 bool global
= ctx
->options
->chip_class
>= GFX9
;
6050 switch (num_bytes
) {
6052 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6055 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6058 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6061 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6064 unreachable("store_global not implemented for this size.");
6067 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6068 flat
->operands
[0] = Operand(addr
);
6069 flat
->operands
[1] = Operand(s1
);
6070 flat
->operands
[2] = Operand(data
);
6073 flat
->offset
= offset
;
6074 flat
->disable_wqm
= true;
6075 flat
->barrier
= barrier_buffer
;
6076 ctx
->program
->needs_exact
= true;
6077 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6079 assert(ctx
->options
->chip_class
== GFX6
);
6082 switch (num_bytes
) {
6084 op
= aco_opcode::buffer_store_dword
;
6087 op
= aco_opcode::buffer_store_dwordx2
;
6090 op
= aco_opcode::buffer_store_dwordx4
;
6093 unreachable("store_global not implemented for this size.");
6096 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6098 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6099 mubuf
->operands
[0] = Operand(rsrc
);
6100 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6101 mubuf
->operands
[2] = Operand(0u);
6102 mubuf
->operands
[3] = Operand(write_data
);
6105 mubuf
->offset
= offset
;
6106 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6107 mubuf
->disable_wqm
= true;
6108 mubuf
->barrier
= barrier_buffer
;
6109 ctx
->program
->needs_exact
= true;
6110 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6115 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6117 /* return the previous value if dest is ever used */
6118 bool return_previous
= false;
6119 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6120 return_previous
= true;
6123 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6124 return_previous
= true;
6128 Builder
bld(ctx
->program
, ctx
->block
);
6129 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6130 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6132 if (ctx
->options
->chip_class
>= GFX7
)
6133 addr
= as_vgpr(ctx
, addr
);
6135 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6136 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6137 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6139 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6141 aco_opcode op32
, op64
;
6143 if (ctx
->options
->chip_class
>= GFX7
) {
6144 bool global
= ctx
->options
->chip_class
>= GFX9
;
6145 switch (instr
->intrinsic
) {
6146 case nir_intrinsic_global_atomic_add
:
6147 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6148 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6150 case nir_intrinsic_global_atomic_imin
:
6151 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6152 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6154 case nir_intrinsic_global_atomic_umin
:
6155 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6156 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6158 case nir_intrinsic_global_atomic_imax
:
6159 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6160 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6162 case nir_intrinsic_global_atomic_umax
:
6163 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6164 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6166 case nir_intrinsic_global_atomic_and
:
6167 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6168 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6170 case nir_intrinsic_global_atomic_or
:
6171 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6172 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6174 case nir_intrinsic_global_atomic_xor
:
6175 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6176 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6178 case nir_intrinsic_global_atomic_exchange
:
6179 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6180 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6182 case nir_intrinsic_global_atomic_comp_swap
:
6183 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6184 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6187 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6190 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6191 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6192 flat
->operands
[0] = Operand(addr
);
6193 flat
->operands
[1] = Operand(s1
);
6194 flat
->operands
[2] = Operand(data
);
6195 if (return_previous
)
6196 flat
->definitions
[0] = Definition(dst
);
6197 flat
->glc
= return_previous
;
6198 flat
->dlc
= false; /* Not needed for atomics */
6200 flat
->disable_wqm
= true;
6201 flat
->barrier
= barrier_buffer
;
6202 ctx
->program
->needs_exact
= true;
6203 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6205 assert(ctx
->options
->chip_class
== GFX6
);
6207 switch (instr
->intrinsic
) {
6208 case nir_intrinsic_global_atomic_add
:
6209 op32
= aco_opcode::buffer_atomic_add
;
6210 op64
= aco_opcode::buffer_atomic_add_x2
;
6212 case nir_intrinsic_global_atomic_imin
:
6213 op32
= aco_opcode::buffer_atomic_smin
;
6214 op64
= aco_opcode::buffer_atomic_smin_x2
;
6216 case nir_intrinsic_global_atomic_umin
:
6217 op32
= aco_opcode::buffer_atomic_umin
;
6218 op64
= aco_opcode::buffer_atomic_umin_x2
;
6220 case nir_intrinsic_global_atomic_imax
:
6221 op32
= aco_opcode::buffer_atomic_smax
;
6222 op64
= aco_opcode::buffer_atomic_smax_x2
;
6224 case nir_intrinsic_global_atomic_umax
:
6225 op32
= aco_opcode::buffer_atomic_umax
;
6226 op64
= aco_opcode::buffer_atomic_umax_x2
;
6228 case nir_intrinsic_global_atomic_and
:
6229 op32
= aco_opcode::buffer_atomic_and
;
6230 op64
= aco_opcode::buffer_atomic_and_x2
;
6232 case nir_intrinsic_global_atomic_or
:
6233 op32
= aco_opcode::buffer_atomic_or
;
6234 op64
= aco_opcode::buffer_atomic_or_x2
;
6236 case nir_intrinsic_global_atomic_xor
:
6237 op32
= aco_opcode::buffer_atomic_xor
;
6238 op64
= aco_opcode::buffer_atomic_xor_x2
;
6240 case nir_intrinsic_global_atomic_exchange
:
6241 op32
= aco_opcode::buffer_atomic_swap
;
6242 op64
= aco_opcode::buffer_atomic_swap_x2
;
6244 case nir_intrinsic_global_atomic_comp_swap
:
6245 op32
= aco_opcode::buffer_atomic_cmpswap
;
6246 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6249 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6252 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6254 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6256 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6257 mubuf
->operands
[0] = Operand(rsrc
);
6258 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6259 mubuf
->operands
[2] = Operand(0u);
6260 mubuf
->operands
[3] = Operand(data
);
6261 if (return_previous
)
6262 mubuf
->definitions
[0] = Definition(dst
);
6263 mubuf
->glc
= return_previous
;
6266 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6267 mubuf
->disable_wqm
= true;
6268 mubuf
->barrier
= barrier_buffer
;
6269 ctx
->program
->needs_exact
= true;
6270 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6274 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6275 Builder
bld(ctx
->program
, ctx
->block
);
6276 switch(instr
->intrinsic
) {
6277 case nir_intrinsic_group_memory_barrier
:
6278 case nir_intrinsic_memory_barrier
:
6279 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6281 case nir_intrinsic_memory_barrier_buffer
:
6282 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6284 case nir_intrinsic_memory_barrier_image
:
6285 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6287 case nir_intrinsic_memory_barrier_tcs_patch
:
6288 case nir_intrinsic_memory_barrier_shared
:
6289 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6292 unreachable("Unimplemented memory barrier intrinsic");
6297 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6299 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6300 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6301 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6302 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6303 Builder
bld(ctx
->program
, ctx
->block
);
6305 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6306 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6307 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6310 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6312 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6313 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6314 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6315 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6316 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6318 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6319 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6322 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6324 unsigned offset
= nir_intrinsic_base(instr
);
6325 Operand m
= load_lds_size_m0(ctx
);
6326 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6327 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6329 unsigned num_operands
= 3;
6330 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6331 switch(instr
->intrinsic
) {
6332 case nir_intrinsic_shared_atomic_add
:
6333 op32
= aco_opcode::ds_add_u32
;
6334 op64
= aco_opcode::ds_add_u64
;
6335 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6336 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6338 case nir_intrinsic_shared_atomic_imin
:
6339 op32
= aco_opcode::ds_min_i32
;
6340 op64
= aco_opcode::ds_min_i64
;
6341 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6342 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6344 case nir_intrinsic_shared_atomic_umin
:
6345 op32
= aco_opcode::ds_min_u32
;
6346 op64
= aco_opcode::ds_min_u64
;
6347 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6348 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6350 case nir_intrinsic_shared_atomic_imax
:
6351 op32
= aco_opcode::ds_max_i32
;
6352 op64
= aco_opcode::ds_max_i64
;
6353 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6354 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6356 case nir_intrinsic_shared_atomic_umax
:
6357 op32
= aco_opcode::ds_max_u32
;
6358 op64
= aco_opcode::ds_max_u64
;
6359 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6360 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6362 case nir_intrinsic_shared_atomic_and
:
6363 op32
= aco_opcode::ds_and_b32
;
6364 op64
= aco_opcode::ds_and_b64
;
6365 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6366 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6368 case nir_intrinsic_shared_atomic_or
:
6369 op32
= aco_opcode::ds_or_b32
;
6370 op64
= aco_opcode::ds_or_b64
;
6371 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6372 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6374 case nir_intrinsic_shared_atomic_xor
:
6375 op32
= aco_opcode::ds_xor_b32
;
6376 op64
= aco_opcode::ds_xor_b64
;
6377 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6378 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6380 case nir_intrinsic_shared_atomic_exchange
:
6381 op32
= aco_opcode::ds_write_b32
;
6382 op64
= aco_opcode::ds_write_b64
;
6383 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6384 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6386 case nir_intrinsic_shared_atomic_comp_swap
:
6387 op32
= aco_opcode::ds_cmpst_b32
;
6388 op64
= aco_opcode::ds_cmpst_b64
;
6389 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6390 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6394 unreachable("Unhandled shared atomic intrinsic");
6397 /* return the previous value if dest is ever used */
6398 bool return_previous
= false;
6399 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6400 return_previous
= true;
6403 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6404 return_previous
= true;
6409 if (data
.size() == 1) {
6410 assert(instr
->dest
.ssa
.bit_size
== 32);
6411 op
= return_previous
? op32_rtn
: op32
;
6413 assert(instr
->dest
.ssa
.bit_size
== 64);
6414 op
= return_previous
? op64_rtn
: op64
;
6417 if (offset
> 65535) {
6418 Builder
bld(ctx
->program
, ctx
->block
);
6419 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6423 aco_ptr
<DS_instruction
> ds
;
6424 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6425 ds
->operands
[0] = Operand(address
);
6426 ds
->operands
[1] = Operand(data
);
6427 if (num_operands
== 4)
6428 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6429 ds
->operands
[num_operands
- 1] = m
;
6430 ds
->offset0
= offset
;
6431 if (return_previous
)
6432 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6433 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6436 Temp
get_scratch_resource(isel_context
*ctx
)
6438 Builder
bld(ctx
->program
, ctx
->block
);
6439 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6440 if (ctx
->stage
!= compute_cs
)
6441 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6443 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6444 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6446 if (ctx
->program
->chip_class
>= GFX10
) {
6447 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6448 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6449 S_008F0C_RESOURCE_LEVEL(1);
6450 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6451 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6452 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6455 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6456 if (ctx
->program
->chip_class
<= GFX8
)
6457 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6459 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6462 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6463 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6464 Builder
bld(ctx
->program
, ctx
->block
);
6465 Temp rsrc
= get_scratch_resource(ctx
);
6466 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6467 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6470 switch (dst
.size()) {
6472 op
= aco_opcode::buffer_load_dword
;
6475 op
= aco_opcode::buffer_load_dwordx2
;
6478 op
= aco_opcode::buffer_load_dwordx3
;
6481 op
= aco_opcode::buffer_load_dwordx4
;
6485 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6486 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6487 bld
.def(v4
), rsrc
, offset
,
6488 ctx
->program
->scratch_offset
, 0, true);
6489 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6490 aco_opcode::buffer_load_dwordx4
,
6491 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6492 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6493 emit_split_vector(ctx
, lower
, 2);
6494 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6495 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6496 if (dst
.size() == 8) {
6497 emit_split_vector(ctx
, upper
, 2);
6498 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6499 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6504 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6505 Format::PSEUDO
, dst
.size() / 2, 1)};
6506 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6507 vec
->operands
[i
] = Operand(elems
[i
]);
6508 vec
->definitions
[0] = Definition(dst
);
6509 bld
.insert(std::move(vec
));
6510 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6514 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6517 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6518 emit_split_vector(ctx
, dst
, instr
->num_components
);
6521 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6522 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6523 Builder
bld(ctx
->program
, ctx
->block
);
6524 Temp rsrc
= get_scratch_resource(ctx
);
6525 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6526 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6528 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6529 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6533 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6534 int num_bytes
= count
* elem_size_bytes
;
6536 if (num_bytes
> 16) {
6537 assert(elem_size_bytes
== 8);
6538 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6543 // TODO: check alignment of sub-dword stores
6544 // TODO: split 3 bytes. there is no store instruction for that
6547 if (count
!= instr
->num_components
) {
6548 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6549 for (int i
= 0; i
< count
; i
++) {
6550 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6551 vec
->operands
[i
] = Operand(elem
);
6553 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6554 vec
->definitions
[0] = Definition(write_data
);
6555 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6561 switch (num_bytes
) {
6563 op
= aco_opcode::buffer_store_dword
;
6566 op
= aco_opcode::buffer_store_dwordx2
;
6569 op
= aco_opcode::buffer_store_dwordx3
;
6572 op
= aco_opcode::buffer_store_dwordx4
;
6575 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6578 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6582 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6583 uint8_t log2_ps_iter_samples
;
6584 if (ctx
->program
->info
->ps
.force_persample
) {
6585 log2_ps_iter_samples
=
6586 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6588 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6591 /* The bit pattern matches that used by fixed function fragment
6593 static const unsigned ps_iter_masks
[] = {
6594 0xffff, /* not used */
6600 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6602 Builder
bld(ctx
->program
, ctx
->block
);
6604 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6605 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6606 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6607 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6608 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6609 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6612 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6613 Builder
bld(ctx
->program
, ctx
->block
);
6615 unsigned stream
= nir_intrinsic_stream_id(instr
);
6616 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6617 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6618 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6621 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6623 unsigned num_components
=
6624 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6625 assert(num_components
);
6627 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6628 unsigned stream_offset
= 0;
6629 for (unsigned i
= 0; i
< stream
; i
++) {
6630 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6631 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6634 /* Limit on the stride field for <= GFX7. */
6635 assert(stride
< (1 << 14));
6637 Temp gsvs_dwords
[4];
6638 for (unsigned i
= 0; i
< 4; i
++)
6639 gsvs_dwords
[i
] = bld
.tmp(s1
);
6640 bld
.pseudo(aco_opcode::p_split_vector
,
6641 Definition(gsvs_dwords
[0]),
6642 Definition(gsvs_dwords
[1]),
6643 Definition(gsvs_dwords
[2]),
6644 Definition(gsvs_dwords
[3]),
6647 if (stream_offset
) {
6648 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6650 Temp carry
= bld
.tmp(s1
);
6651 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6652 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6655 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6656 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6658 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6659 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6661 unsigned offset
= 0;
6662 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6663 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6666 for (unsigned j
= 0; j
< 4; j
++) {
6667 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6670 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6671 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6672 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6673 if (const_offset
>= 4096u) {
6674 if (vaddr_offset
.isUndefined())
6675 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6677 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6678 const_offset
%= 4096u;
6681 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6682 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6683 mtbuf
->operands
[1] = vaddr_offset
;
6684 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6685 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6686 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6687 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6688 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6689 mtbuf
->offset
= const_offset
;
6692 mtbuf
->barrier
= barrier_gs_data
;
6693 mtbuf
->can_reorder
= true;
6694 bld
.insert(std::move(mtbuf
));
6697 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6700 /* outputs for the next vertex are undefined and keeping them around can
6701 * create invalid IR with control flow */
6702 ctx
->outputs
.mask
[i
] = 0;
6705 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6708 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6710 Builder
bld(ctx
->program
, ctx
->block
);
6712 if (cluster_size
== 1) {
6714 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6715 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6716 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6717 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6718 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6719 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6720 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6721 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6722 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6723 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6724 //subgroupAnd(val) -> (exec & ~val) == 0
6725 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6726 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6727 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6728 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6729 //subgroupOr(val) -> (val & exec) != 0
6730 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6731 return bool_to_vector_condition(ctx
, tmp
);
6732 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6733 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6734 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6735 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6736 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6737 return bool_to_vector_condition(ctx
, tmp
);
6739 //subgroupClustered{And,Or,Xor}(val, n) ->
6740 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6741 //cluster_offset = ~(n - 1) & lane_id
6742 //cluster_mask = ((1 << n) - 1)
6743 //subgroupClusteredAnd():
6744 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6745 //subgroupClusteredOr():
6746 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6747 //subgroupClusteredXor():
6748 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6749 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6750 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6753 if (op
== nir_op_iand
)
6754 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6756 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6758 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6760 if (ctx
->program
->chip_class
<= GFX7
)
6761 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6762 else if (ctx
->program
->wave_size
== 64)
6763 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6765 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6766 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6767 if (cluster_mask
!= 0xffffffff)
6768 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6770 Definition cmp_def
= Definition();
6771 if (op
== nir_op_iand
) {
6772 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6773 } else if (op
== nir_op_ior
) {
6774 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6775 } else if (op
== nir_op_ixor
) {
6776 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6777 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6778 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6780 cmp_def
.setHint(vcc
);
6781 return cmp_def
.getTemp();
6785 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6787 Builder
bld(ctx
->program
, ctx
->block
);
6789 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6790 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6791 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6793 if (op
== nir_op_iand
)
6794 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6796 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6798 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6799 Temp lo
= lohi
.def(0).getTemp();
6800 Temp hi
= lohi
.def(1).getTemp();
6801 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
6803 Definition cmp_def
= Definition();
6804 if (op
== nir_op_iand
)
6805 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6806 else if (op
== nir_op_ior
)
6807 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6808 else if (op
== nir_op_ixor
)
6809 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
6810 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
6811 cmp_def
.setHint(vcc
);
6812 return cmp_def
.getTemp();
6815 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6817 Builder
bld(ctx
->program
, ctx
->block
);
6819 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6820 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6821 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6822 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
6823 if (op
== nir_op_iand
)
6824 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6825 else if (op
== nir_op_ior
)
6826 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6827 else if (op
== nir_op_ixor
)
6828 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6834 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
6836 Builder
bld(ctx
->program
, ctx
->block
);
6837 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6838 if (src
.regClass().type() == RegType::vgpr
) {
6839 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
6840 } else if (src
.regClass() == s1
) {
6841 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
6842 } else if (src
.regClass() == s2
) {
6843 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
6845 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6846 nir_print_instr(&instr
->instr
, stderr
);
6847 fprintf(stderr
, "\n");
6851 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
6853 Builder
bld(ctx
->program
, ctx
->block
);
6854 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
6855 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
6856 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
6858 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
6859 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
6860 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
6861 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
6864 if (ctx
->program
->chip_class
>= GFX8
) {
6865 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
6866 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
6867 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
6868 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
6869 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
6870 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
6872 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
6873 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
6874 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
6875 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
6876 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
6877 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
6878 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
6879 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
6880 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
6881 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
6884 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6885 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
6886 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
6887 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
6888 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
6889 Temp wqm1
= bld
.tmp(v1
);
6890 emit_wqm(ctx
, tmp1
, wqm1
, true);
6891 Temp wqm2
= bld
.tmp(v1
);
6892 emit_wqm(ctx
, tmp2
, wqm2
, true);
6893 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
6897 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6899 Builder
bld(ctx
->program
, ctx
->block
);
6900 switch(instr
->intrinsic
) {
6901 case nir_intrinsic_load_barycentric_sample
:
6902 case nir_intrinsic_load_barycentric_pixel
:
6903 case nir_intrinsic_load_barycentric_centroid
: {
6904 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
6905 Temp bary
= Temp(0, s2
);
6907 case INTERP_MODE_SMOOTH
:
6908 case INTERP_MODE_NONE
:
6909 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
6910 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
6911 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
6912 bary
= ctx
->persp_centroid
;
6913 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
6914 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
6916 case INTERP_MODE_NOPERSPECTIVE
:
6917 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
6918 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
6919 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
6920 bary
= ctx
->linear_centroid
;
6921 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
6922 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
6927 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6928 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
6929 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
6930 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6931 Operand(p1
), Operand(p2
));
6932 emit_split_vector(ctx
, dst
, 2);
6935 case nir_intrinsic_load_barycentric_model
: {
6936 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
6938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6939 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
6940 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
6941 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
6942 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6943 Operand(p1
), Operand(p2
), Operand(p3
));
6944 emit_split_vector(ctx
, dst
, 3);
6947 case nir_intrinsic_load_barycentric_at_sample
: {
6948 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
6949 switch (ctx
->options
->key
.fs
.num_samples
) {
6950 case 2: sample_pos_offset
+= 1 << 3; break;
6951 case 4: sample_pos_offset
+= 3 << 3; break;
6952 case 8: sample_pos_offset
+= 7 << 3; break;
6956 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6957 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
6958 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
6959 if (addr
.type() == RegType::sgpr
) {
6962 sample_pos_offset
+= const_addr
->u32
<< 3;
6963 offset
= Operand(sample_pos_offset
);
6964 } else if (ctx
->options
->chip_class
>= GFX9
) {
6965 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
6967 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
6968 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
6971 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
6972 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
6974 } else if (ctx
->options
->chip_class
>= GFX9
) {
6975 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
6976 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
6977 } else if (ctx
->options
->chip_class
>= GFX7
) {
6978 /* addr += private_segment_buffer + sample_pos_offset */
6979 Temp tmp0
= bld
.tmp(s1
);
6980 Temp tmp1
= bld
.tmp(s1
);
6981 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
6982 Definition scc_tmp
= bld
.def(s1
, scc
);
6983 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
6984 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
6985 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
6986 Temp pck0
= bld
.tmp(v1
);
6987 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
6988 tmp1
= as_vgpr(ctx
, tmp1
);
6989 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
6990 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
6992 /* sample_pos = flat_load_dwordx2 addr */
6993 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
6995 assert(ctx
->options
->chip_class
== GFX6
);
6997 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6998 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6999 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7001 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7002 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7004 sample_pos
= bld
.tmp(v2
);
7006 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7007 load
->definitions
[0] = Definition(sample_pos
);
7008 load
->operands
[0] = Operand(rsrc
);
7009 load
->operands
[1] = Operand(addr
);
7010 load
->operands
[2] = Operand(0u);
7011 load
->offset
= sample_pos_offset
;
7013 load
->addr64
= true;
7016 load
->disable_wqm
= false;
7017 load
->barrier
= barrier_none
;
7018 load
->can_reorder
= true;
7019 ctx
->block
->instructions
.emplace_back(std::move(load
));
7022 /* sample_pos -= 0.5 */
7023 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7024 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7025 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7026 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7027 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7029 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7032 case nir_intrinsic_load_barycentric_at_offset
: {
7033 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7034 RegClass rc
= RegClass(offset
.type(), 1);
7035 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7036 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7037 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7040 case nir_intrinsic_load_front_face
: {
7041 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7042 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7045 case nir_intrinsic_load_view_index
: {
7046 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7047 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7048 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7054 case nir_intrinsic_load_layer_id
: {
7055 unsigned idx
= nir_intrinsic_base(instr
);
7056 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7057 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7060 case nir_intrinsic_load_frag_coord
: {
7061 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7064 case nir_intrinsic_load_sample_pos
: {
7065 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7066 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7067 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7068 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7069 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7072 case nir_intrinsic_load_tess_coord
:
7073 visit_load_tess_coord(ctx
, instr
);
7075 case nir_intrinsic_load_interpolated_input
:
7076 visit_load_interpolated_input(ctx
, instr
);
7078 case nir_intrinsic_store_output
:
7079 visit_store_output(ctx
, instr
);
7081 case nir_intrinsic_load_input
:
7082 case nir_intrinsic_load_input_vertex
:
7083 visit_load_input(ctx
, instr
);
7085 case nir_intrinsic_load_output
:
7086 visit_load_output(ctx
, instr
);
7088 case nir_intrinsic_load_per_vertex_input
:
7089 visit_load_per_vertex_input(ctx
, instr
);
7091 case nir_intrinsic_load_per_vertex_output
:
7092 visit_load_per_vertex_output(ctx
, instr
);
7094 case nir_intrinsic_store_per_vertex_output
:
7095 visit_store_per_vertex_output(ctx
, instr
);
7097 case nir_intrinsic_load_ubo
:
7098 visit_load_ubo(ctx
, instr
);
7100 case nir_intrinsic_load_push_constant
:
7101 visit_load_push_constant(ctx
, instr
);
7103 case nir_intrinsic_load_constant
:
7104 visit_load_constant(ctx
, instr
);
7106 case nir_intrinsic_vulkan_resource_index
:
7107 visit_load_resource(ctx
, instr
);
7109 case nir_intrinsic_discard
:
7110 visit_discard(ctx
, instr
);
7112 case nir_intrinsic_discard_if
:
7113 visit_discard_if(ctx
, instr
);
7115 case nir_intrinsic_load_shared
:
7116 visit_load_shared(ctx
, instr
);
7118 case nir_intrinsic_store_shared
:
7119 visit_store_shared(ctx
, instr
);
7121 case nir_intrinsic_shared_atomic_add
:
7122 case nir_intrinsic_shared_atomic_imin
:
7123 case nir_intrinsic_shared_atomic_umin
:
7124 case nir_intrinsic_shared_atomic_imax
:
7125 case nir_intrinsic_shared_atomic_umax
:
7126 case nir_intrinsic_shared_atomic_and
:
7127 case nir_intrinsic_shared_atomic_or
:
7128 case nir_intrinsic_shared_atomic_xor
:
7129 case nir_intrinsic_shared_atomic_exchange
:
7130 case nir_intrinsic_shared_atomic_comp_swap
:
7131 visit_shared_atomic(ctx
, instr
);
7133 case nir_intrinsic_image_deref_load
:
7134 visit_image_load(ctx
, instr
);
7136 case nir_intrinsic_image_deref_store
:
7137 visit_image_store(ctx
, instr
);
7139 case nir_intrinsic_image_deref_atomic_add
:
7140 case nir_intrinsic_image_deref_atomic_umin
:
7141 case nir_intrinsic_image_deref_atomic_imin
:
7142 case nir_intrinsic_image_deref_atomic_umax
:
7143 case nir_intrinsic_image_deref_atomic_imax
:
7144 case nir_intrinsic_image_deref_atomic_and
:
7145 case nir_intrinsic_image_deref_atomic_or
:
7146 case nir_intrinsic_image_deref_atomic_xor
:
7147 case nir_intrinsic_image_deref_atomic_exchange
:
7148 case nir_intrinsic_image_deref_atomic_comp_swap
:
7149 visit_image_atomic(ctx
, instr
);
7151 case nir_intrinsic_image_deref_size
:
7152 visit_image_size(ctx
, instr
);
7154 case nir_intrinsic_load_ssbo
:
7155 visit_load_ssbo(ctx
, instr
);
7157 case nir_intrinsic_store_ssbo
:
7158 visit_store_ssbo(ctx
, instr
);
7160 case nir_intrinsic_load_global
:
7161 visit_load_global(ctx
, instr
);
7163 case nir_intrinsic_store_global
:
7164 visit_store_global(ctx
, instr
);
7166 case nir_intrinsic_global_atomic_add
:
7167 case nir_intrinsic_global_atomic_imin
:
7168 case nir_intrinsic_global_atomic_umin
:
7169 case nir_intrinsic_global_atomic_imax
:
7170 case nir_intrinsic_global_atomic_umax
:
7171 case nir_intrinsic_global_atomic_and
:
7172 case nir_intrinsic_global_atomic_or
:
7173 case nir_intrinsic_global_atomic_xor
:
7174 case nir_intrinsic_global_atomic_exchange
:
7175 case nir_intrinsic_global_atomic_comp_swap
:
7176 visit_global_atomic(ctx
, instr
);
7178 case nir_intrinsic_ssbo_atomic_add
:
7179 case nir_intrinsic_ssbo_atomic_imin
:
7180 case nir_intrinsic_ssbo_atomic_umin
:
7181 case nir_intrinsic_ssbo_atomic_imax
:
7182 case nir_intrinsic_ssbo_atomic_umax
:
7183 case nir_intrinsic_ssbo_atomic_and
:
7184 case nir_intrinsic_ssbo_atomic_or
:
7185 case nir_intrinsic_ssbo_atomic_xor
:
7186 case nir_intrinsic_ssbo_atomic_exchange
:
7187 case nir_intrinsic_ssbo_atomic_comp_swap
:
7188 visit_atomic_ssbo(ctx
, instr
);
7190 case nir_intrinsic_load_scratch
:
7191 visit_load_scratch(ctx
, instr
);
7193 case nir_intrinsic_store_scratch
:
7194 visit_store_scratch(ctx
, instr
);
7196 case nir_intrinsic_get_buffer_size
:
7197 visit_get_buffer_size(ctx
, instr
);
7199 case nir_intrinsic_control_barrier
: {
7200 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7201 /* GFX6 only (thanks to a hw bug workaround):
7202 * The real barrier instruction isn’t needed, because an entire patch
7203 * always fits into a single wave.
7208 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7209 bld
.sopp(aco_opcode::s_barrier
);
7213 case nir_intrinsic_memory_barrier_tcs_patch
:
7214 case nir_intrinsic_group_memory_barrier
:
7215 case nir_intrinsic_memory_barrier
:
7216 case nir_intrinsic_memory_barrier_buffer
:
7217 case nir_intrinsic_memory_barrier_image
:
7218 case nir_intrinsic_memory_barrier_shared
:
7219 emit_memory_barrier(ctx
, instr
);
7221 case nir_intrinsic_load_num_work_groups
: {
7222 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7223 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7224 emit_split_vector(ctx
, dst
, 3);
7227 case nir_intrinsic_load_local_invocation_id
: {
7228 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7229 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7230 emit_split_vector(ctx
, dst
, 3);
7233 case nir_intrinsic_load_work_group_id
: {
7234 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7235 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7236 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7237 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7238 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7239 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7240 emit_split_vector(ctx
, dst
, 3);
7243 case nir_intrinsic_load_local_invocation_index
: {
7244 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7246 /* The tg_size bits [6:11] contain the subgroup id,
7247 * we need this multiplied by the wave size, and then OR the thread id to it.
7249 if (ctx
->program
->wave_size
== 64) {
7250 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7251 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7252 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7253 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7255 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7256 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7257 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7258 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7262 case nir_intrinsic_load_subgroup_id
: {
7263 if (ctx
->stage
== compute_cs
) {
7264 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7265 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7267 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7271 case nir_intrinsic_load_subgroup_invocation
: {
7272 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7275 case nir_intrinsic_load_num_subgroups
: {
7276 if (ctx
->stage
== compute_cs
)
7277 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7278 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7280 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7283 case nir_intrinsic_ballot
: {
7284 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7285 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7286 Definition tmp
= bld
.def(dst
.regClass());
7287 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7288 if (instr
->src
[0].ssa
->bit_size
== 1) {
7289 assert(src
.regClass() == bld
.lm
);
7290 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7291 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7292 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7293 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7294 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7296 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7297 nir_print_instr(&instr
->instr
, stderr
);
7298 fprintf(stderr
, "\n");
7300 if (dst
.size() != bld
.lm
.size()) {
7301 /* Wave32 with ballot size set to 64 */
7302 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7304 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7307 case nir_intrinsic_shuffle
:
7308 case nir_intrinsic_read_invocation
: {
7309 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7310 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7311 emit_uniform_subgroup(ctx
, instr
, src
);
7313 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7314 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7315 tid
= bld
.as_uniform(tid
);
7316 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7317 if (src
.regClass() == v1
) {
7318 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7319 } else if (src
.regClass() == v2
) {
7320 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7321 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7322 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7323 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7324 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7325 emit_split_vector(ctx
, dst
, 2);
7326 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7327 assert(src
.regClass() == bld
.lm
);
7328 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7329 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7330 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7331 assert(src
.regClass() == bld
.lm
);
7333 if (ctx
->program
->chip_class
<= GFX7
)
7334 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7335 else if (ctx
->program
->wave_size
== 64)
7336 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7338 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7339 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7340 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7341 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7343 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7344 nir_print_instr(&instr
->instr
, stderr
);
7345 fprintf(stderr
, "\n");
7350 case nir_intrinsic_load_sample_id
: {
7351 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7352 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7355 case nir_intrinsic_load_sample_mask_in
: {
7356 visit_load_sample_mask_in(ctx
, instr
);
7359 case nir_intrinsic_read_first_invocation
: {
7360 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7361 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7362 if (src
.regClass() == v1
) {
7364 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7366 } else if (src
.regClass() == v2
) {
7367 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7368 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7369 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7370 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7371 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7372 emit_split_vector(ctx
, dst
, 2);
7373 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7374 assert(src
.regClass() == bld
.lm
);
7375 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7376 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7377 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7378 } else if (src
.regClass() == s1
) {
7379 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7380 } else if (src
.regClass() == s2
) {
7381 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7383 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7384 nir_print_instr(&instr
->instr
, stderr
);
7385 fprintf(stderr
, "\n");
7389 case nir_intrinsic_vote_all
: {
7390 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7391 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7392 assert(src
.regClass() == bld
.lm
);
7393 assert(dst
.regClass() == bld
.lm
);
7395 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7396 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7397 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7400 case nir_intrinsic_vote_any
: {
7401 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7402 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7403 assert(src
.regClass() == bld
.lm
);
7404 assert(dst
.regClass() == bld
.lm
);
7406 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7407 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7410 case nir_intrinsic_reduce
:
7411 case nir_intrinsic_inclusive_scan
:
7412 case nir_intrinsic_exclusive_scan
: {
7413 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7414 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7415 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7416 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7417 nir_intrinsic_cluster_size(instr
) : 0;
7418 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7420 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7421 emit_uniform_subgroup(ctx
, instr
, src
);
7422 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7423 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7425 else if (op
== nir_op_iadd
)
7427 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7429 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7431 switch (instr
->intrinsic
) {
7432 case nir_intrinsic_reduce
:
7433 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7435 case nir_intrinsic_exclusive_scan
:
7436 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7438 case nir_intrinsic_inclusive_scan
:
7439 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7444 } else if (cluster_size
== 1) {
7445 bld
.copy(Definition(dst
), src
);
7447 src
= as_vgpr(ctx
, src
);
7451 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7466 unreachable("unknown reduction op");
7471 switch (instr
->intrinsic
) {
7472 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7473 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7474 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7476 unreachable("unknown reduce intrinsic");
7479 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7480 reduce
->operands
[0] = Operand(src
);
7481 // filled in by aco_reduce_assign.cpp, used internally as part of the
7483 assert(dst
.size() == 1 || dst
.size() == 2);
7484 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7485 reduce
->operands
[2] = Operand(v1
.as_linear());
7487 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7488 reduce
->definitions
[0] = Definition(tmp_dst
);
7489 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7490 reduce
->definitions
[2] = Definition();
7491 reduce
->definitions
[3] = Definition(scc
, s1
);
7492 reduce
->definitions
[4] = Definition();
7493 reduce
->reduce_op
= reduce_op
;
7494 reduce
->cluster_size
= cluster_size
;
7495 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7497 emit_wqm(ctx
, tmp_dst
, dst
);
7501 case nir_intrinsic_quad_broadcast
: {
7502 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7503 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7504 emit_uniform_subgroup(ctx
, instr
, src
);
7506 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7507 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7508 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7510 if (instr
->dest
.ssa
.bit_size
== 1) {
7511 assert(src
.regClass() == bld
.lm
);
7512 assert(dst
.regClass() == bld
.lm
);
7513 uint32_t half_mask
= 0x11111111u
<< lane
;
7514 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7515 Temp tmp
= bld
.tmp(bld
.lm
);
7516 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7517 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7518 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7519 emit_wqm(ctx
, tmp
, dst
);
7520 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7521 if (ctx
->program
->chip_class
>= GFX8
)
7522 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7524 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7525 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7526 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7527 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7528 if (ctx
->program
->chip_class
>= GFX8
) {
7529 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7530 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7532 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7533 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7535 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7536 emit_split_vector(ctx
, dst
, 2);
7538 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7539 nir_print_instr(&instr
->instr
, stderr
);
7540 fprintf(stderr
, "\n");
7545 case nir_intrinsic_quad_swap_horizontal
:
7546 case nir_intrinsic_quad_swap_vertical
:
7547 case nir_intrinsic_quad_swap_diagonal
:
7548 case nir_intrinsic_quad_swizzle_amd
: {
7549 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7550 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7551 emit_uniform_subgroup(ctx
, instr
, src
);
7554 uint16_t dpp_ctrl
= 0;
7555 switch (instr
->intrinsic
) {
7556 case nir_intrinsic_quad_swap_horizontal
:
7557 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7559 case nir_intrinsic_quad_swap_vertical
:
7560 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7562 case nir_intrinsic_quad_swap_diagonal
:
7563 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7565 case nir_intrinsic_quad_swizzle_amd
:
7566 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7571 if (ctx
->program
->chip_class
< GFX8
)
7572 dpp_ctrl
|= (1 << 15);
7574 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7575 if (instr
->dest
.ssa
.bit_size
== 1) {
7576 assert(src
.regClass() == bld
.lm
);
7577 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7578 if (ctx
->program
->chip_class
>= GFX8
)
7579 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7581 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7582 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7583 emit_wqm(ctx
, tmp
, dst
);
7584 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7586 if (ctx
->program
->chip_class
>= GFX8
)
7587 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7589 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7590 emit_wqm(ctx
, tmp
, dst
);
7591 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7592 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7593 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7594 if (ctx
->program
->chip_class
>= GFX8
) {
7595 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7596 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7598 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7599 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7601 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7602 emit_split_vector(ctx
, dst
, 2);
7604 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7605 nir_print_instr(&instr
->instr
, stderr
);
7606 fprintf(stderr
, "\n");
7610 case nir_intrinsic_masked_swizzle_amd
: {
7611 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7612 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7613 emit_uniform_subgroup(ctx
, instr
, src
);
7616 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7617 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7618 if (dst
.regClass() == v1
) {
7620 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7622 } else if (dst
.regClass() == v2
) {
7623 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7624 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7625 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7626 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7627 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7628 emit_split_vector(ctx
, dst
, 2);
7630 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7631 nir_print_instr(&instr
->instr
, stderr
);
7632 fprintf(stderr
, "\n");
7636 case nir_intrinsic_write_invocation_amd
: {
7637 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7638 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7639 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7640 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7641 if (dst
.regClass() == v1
) {
7642 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7643 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7644 } else if (dst
.regClass() == v2
) {
7645 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7646 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7647 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7648 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7649 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7650 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7651 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7652 emit_split_vector(ctx
, dst
, 2);
7654 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7655 nir_print_instr(&instr
->instr
, stderr
);
7656 fprintf(stderr
, "\n");
7660 case nir_intrinsic_mbcnt_amd
: {
7661 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7662 RegClass rc
= RegClass(src
.type(), 1);
7663 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7664 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7665 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7666 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7667 emit_wqm(ctx
, wqm_tmp
, dst
);
7670 case nir_intrinsic_load_helper_invocation
: {
7671 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7672 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7673 ctx
->block
->kind
|= block_kind_needs_lowering
;
7674 ctx
->program
->needs_exact
= true;
7677 case nir_intrinsic_is_helper_invocation
: {
7678 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7679 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7680 ctx
->block
->kind
|= block_kind_needs_lowering
;
7681 ctx
->program
->needs_exact
= true;
7684 case nir_intrinsic_demote
:
7685 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7687 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7688 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7689 ctx
->block
->kind
|= block_kind_uses_demote
;
7690 ctx
->program
->needs_exact
= true;
7692 case nir_intrinsic_demote_if
: {
7693 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7694 assert(src
.regClass() == bld
.lm
);
7695 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7696 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7698 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7699 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7700 ctx
->block
->kind
|= block_kind_uses_demote
;
7701 ctx
->program
->needs_exact
= true;
7704 case nir_intrinsic_first_invocation
: {
7705 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7706 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7709 case nir_intrinsic_shader_clock
:
7710 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7711 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7713 case nir_intrinsic_load_vertex_id_zero_base
: {
7714 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7715 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7718 case nir_intrinsic_load_first_vertex
: {
7719 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7720 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7723 case nir_intrinsic_load_base_instance
: {
7724 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7725 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7728 case nir_intrinsic_load_instance_id
: {
7729 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7730 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7733 case nir_intrinsic_load_draw_id
: {
7734 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7735 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7738 case nir_intrinsic_load_invocation_id
: {
7739 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7741 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7742 if (ctx
->options
->chip_class
>= GFX10
)
7743 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7745 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7746 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7747 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7748 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7750 unreachable("Unsupported stage for load_invocation_id");
7755 case nir_intrinsic_load_primitive_id
: {
7756 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7758 switch (ctx
->shader
->info
.stage
) {
7759 case MESA_SHADER_GEOMETRY
:
7760 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7762 case MESA_SHADER_TESS_CTRL
:
7763 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7765 case MESA_SHADER_TESS_EVAL
:
7766 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7769 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7774 case nir_intrinsic_load_patch_vertices_in
: {
7775 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7776 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7778 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7779 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
7782 case nir_intrinsic_emit_vertex_with_counter
: {
7783 visit_emit_vertex_with_counter(ctx
, instr
);
7786 case nir_intrinsic_end_primitive_with_counter
: {
7787 unsigned stream
= nir_intrinsic_stream_id(instr
);
7788 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
7791 case nir_intrinsic_set_vertex_count
: {
7792 /* unused, the HW keeps track of this for us */
7796 fprintf(stderr
, "Unimplemented intrinsic instr: ");
7797 nir_print_instr(&instr
->instr
, stderr
);
7798 fprintf(stderr
, "\n");
7806 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
7807 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
7808 enum glsl_base_type
*stype
)
7810 nir_deref_instr
*texture_deref_instr
= NULL
;
7811 nir_deref_instr
*sampler_deref_instr
= NULL
;
7814 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
7815 switch (instr
->src
[i
].src_type
) {
7816 case nir_tex_src_texture_deref
:
7817 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7819 case nir_tex_src_sampler_deref
:
7820 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7822 case nir_tex_src_plane
:
7823 plane
= nir_src_as_int(instr
->src
[i
].src
);
7830 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
7832 if (!sampler_deref_instr
)
7833 sampler_deref_instr
= texture_deref_instr
;
7836 assert(instr
->op
!= nir_texop_txf_ms
&&
7837 instr
->op
!= nir_texop_samples_identical
);
7838 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
7839 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
7840 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
7841 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
7842 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
7843 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7845 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
7848 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
7850 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
7851 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7852 Builder
bld(ctx
->program
, ctx
->block
);
7854 /* to avoid unnecessary moves, we split and recombine sampler and image */
7855 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
7856 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7857 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7858 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
7859 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
7860 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
7861 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
7862 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
7864 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
7865 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
7866 img
[0], img
[1], img
[2], img
[3],
7867 img
[4], img
[5], img
[6], img
[7]);
7868 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7869 samp
[0], samp
[1], samp
[2], samp
[3]);
7872 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
7873 instr
->op
== nir_texop_samples_identical
))
7874 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7877 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
7878 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
7880 Builder
bld(ctx
->program
, ctx
->block
);
7882 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
7883 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
7884 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
7886 Operand
neg_one(0xbf800000u
);
7887 Operand
one(0x3f800000u
);
7888 Operand
two(0x40000000u
);
7889 Operand
four(0x40800000u
);
7891 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
7892 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
7893 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
7895 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
7896 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
7897 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
7898 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
7901 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
7902 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7903 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
7905 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
7908 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
7909 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
7910 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
7913 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7914 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
7916 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
7917 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
7920 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
7922 Builder
bld(ctx
->program
, ctx
->block
);
7923 Temp ma
, tc
, sc
, id
;
7926 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
7928 // see comment in ac_prepare_cube_coords()
7929 if (ctx
->options
->chip_class
<= GFX8
)
7930 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
7933 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7935 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
7936 vop3a
->operands
[0] = Operand(ma
);
7937 vop3a
->abs
[0] = true;
7938 Temp invma
= bld
.tmp(v1
);
7939 vop3a
->definitions
[0] = Definition(invma
);
7940 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
7942 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7944 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
7946 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7948 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
7950 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
7953 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
7954 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
7956 for (unsigned i
= 0; i
< 2; i
++) {
7957 // see comment in ac_prepare_cube_coords()
7959 Temp deriv_sc
, deriv_tc
;
7960 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
7961 &deriv_ma
, &deriv_sc
, &deriv_tc
);
7963 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
7965 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
7966 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
7967 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
7968 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
7969 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
7970 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
7971 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
7974 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
7975 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
7979 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
7986 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
7988 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
7990 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
7991 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
7994 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
7995 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
7996 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8000 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8002 Builder
bld(ctx
->program
, ctx
->block
);
8003 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8004 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8005 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8006 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8007 std::vector
<Temp
> coords
;
8008 std::vector
<Temp
> derivs
;
8009 nir_const_value
*sample_index_cv
= NULL
;
8010 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8011 enum glsl_base_type stype
;
8012 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8014 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8015 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8016 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8017 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8019 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8020 switch (instr
->src
[i
].src_type
) {
8021 case nir_tex_src_coord
: {
8022 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8023 for (unsigned i
= 0; i
< coord
.size(); i
++)
8024 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8027 case nir_tex_src_bias
:
8028 if (instr
->op
== nir_texop_txb
) {
8029 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8033 case nir_tex_src_lod
: {
8034 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8036 if (val
&& val
->f32
<= 0.0) {
8039 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8044 case nir_tex_src_comparator
:
8045 if (instr
->is_shadow
) {
8046 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8050 case nir_tex_src_offset
:
8051 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8052 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8055 case nir_tex_src_ddx
:
8056 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8059 case nir_tex_src_ddy
:
8060 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8063 case nir_tex_src_ms_index
:
8064 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8065 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8066 has_sample_index
= true;
8068 case nir_tex_src_texture_offset
:
8069 case nir_tex_src_sampler_offset
:
8075 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8076 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8078 if (instr
->op
== nir_texop_texture_samples
) {
8079 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8081 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8082 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8083 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8084 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8086 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8087 samples
, Operand(1u), bld
.scc(is_msaa
));
8091 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8092 aco_ptr
<Instruction
> tmp_instr
;
8093 Temp acc
, pack
= Temp();
8095 uint32_t pack_const
= 0;
8096 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8097 if (!const_offset
[i
])
8099 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8102 if (offset
.type() == RegType::sgpr
) {
8103 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8104 if (const_offset
[i
])
8107 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8108 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8111 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8114 if (pack
== Temp()) {
8117 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8121 if (pack_const
&& pack
!= Temp())
8122 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8124 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8125 if (const_offset
[i
])
8128 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8129 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8132 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8135 if (pack
== Temp()) {
8138 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8142 if (pack_const
&& pack
!= Temp())
8143 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8145 if (pack_const
&& pack
== Temp())
8146 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8147 else if (pack
== Temp())
8153 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8154 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8156 /* pack derivatives */
8157 if (has_ddx
|| has_ddy
) {
8158 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8159 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8160 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8161 derivs
= {ddy
, zero
, ddy
, zero
};
8163 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8164 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8165 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8166 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8171 if (instr
->coord_components
> 1 &&
8172 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8174 instr
->op
!= nir_texop_txf
)
8175 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8177 if (instr
->coord_components
> 2 &&
8178 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8179 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8180 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8181 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8183 instr
->op
!= nir_texop_txf
&&
8184 instr
->op
!= nir_texop_txf_ms
&&
8185 instr
->op
!= nir_texop_fragment_fetch
&&
8186 instr
->op
!= nir_texop_fragment_mask_fetch
)
8187 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8189 if (ctx
->options
->chip_class
== GFX9
&&
8190 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8191 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8192 assert(coords
.size() > 0 && coords
.size() < 3);
8194 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8195 Operand((uint32_t) 0) :
8196 Operand((uint32_t) 0x3f000000)));
8199 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8201 if (instr
->op
== nir_texop_samples_identical
)
8202 resource
= fmask_ptr
;
8204 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8205 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8206 instr
->op
!= nir_texop_txs
&&
8207 instr
->op
!= nir_texop_fragment_fetch
&&
8208 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8209 assert(has_sample_index
);
8210 Operand
op(sample_index
);
8211 if (sample_index_cv
)
8212 op
= Operand(sample_index_cv
->u32
);
8213 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8216 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8217 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8218 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8219 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8224 /* Build tex instruction */
8225 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8226 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8227 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8229 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8232 /* gather4 selects the component by dmask and always returns vec4 */
8233 if (instr
->op
== nir_texop_tg4
) {
8234 assert(instr
->dest
.ssa
.num_components
== 4);
8235 if (instr
->is_shadow
)
8238 dmask
= 1 << instr
->component
;
8239 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8240 tmp_dst
= bld
.tmp(v4
);
8241 } else if (instr
->op
== nir_texop_samples_identical
) {
8242 tmp_dst
= bld
.tmp(v1
);
8243 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8244 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8247 aco_ptr
<MIMG_instruction
> tex
;
8248 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8250 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8252 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8253 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8256 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8257 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8259 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8260 tex
->operands
[0] = Operand(resource
);
8261 tex
->operands
[1] = Operand(s4
); /* no sampler */
8262 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8263 if (ctx
->options
->chip_class
== GFX9
&&
8264 instr
->op
== nir_texop_txs
&&
8265 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8267 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8268 } else if (instr
->op
== nir_texop_query_levels
) {
8269 tex
->dmask
= 1 << 3;
8274 tex
->definitions
[0] = Definition(tmp_dst
);
8276 tex
->can_reorder
= true;
8277 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8280 /* divide 3rd value by 6 by multiplying with magic number */
8281 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8282 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8283 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8284 assert(instr
->dest
.ssa
.num_components
== 3);
8285 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8286 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8287 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8288 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8293 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8297 Temp tg4_compare_cube_wa64
= Temp();
8299 if (tg4_integer_workarounds
) {
8300 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8301 tex
->operands
[0] = Operand(resource
);
8302 tex
->operands
[1] = Operand(s4
); /* no sampler */
8303 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8307 Temp size
= bld
.tmp(v2
);
8308 tex
->definitions
[0] = Definition(size
);
8309 tex
->can_reorder
= true;
8310 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8311 emit_split_vector(ctx
, size
, size
.size());
8314 for (unsigned i
= 0; i
< 2; i
++) {
8315 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8316 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8317 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8318 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8321 Temp new_coords
[2] = {
8322 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8323 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8326 if (tg4_integer_cube_workaround
) {
8327 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8328 Temp desc
[resource
.size()];
8329 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8330 Format::PSEUDO
, 1, resource
.size())};
8331 split
->operands
[0] = Operand(resource
);
8332 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8333 desc
[i
] = bld
.tmp(s1
);
8334 split
->definitions
[i
] = Definition(desc
[i
]);
8336 ctx
->block
->instructions
.emplace_back(std::move(split
));
8338 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8339 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8340 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8343 if (stype
== GLSL_TYPE_UINT
) {
8344 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8345 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8346 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8347 bld
.scc(compare_cube_wa
));
8349 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8350 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8351 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8352 bld
.scc(compare_cube_wa
));
8354 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8355 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8357 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8359 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8360 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8361 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8363 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8364 Format::PSEUDO
, resource
.size(), 1)};
8365 for (unsigned i
= 0; i
< resource
.size(); i
++)
8366 vec
->operands
[i
] = Operand(desc
[i
]);
8367 resource
= bld
.tmp(resource
.regClass());
8368 vec
->definitions
[0] = Definition(resource
);
8369 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8371 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8372 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8373 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8374 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8376 coords
[0] = new_coords
[0];
8377 coords
[1] = new_coords
[1];
8380 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8381 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8383 assert(coords
.size() == 1);
8384 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8388 op
= aco_opcode::buffer_load_format_x
; break;
8390 op
= aco_opcode::buffer_load_format_xy
; break;
8392 op
= aco_opcode::buffer_load_format_xyz
; break;
8394 op
= aco_opcode::buffer_load_format_xyzw
; break;
8396 unreachable("Tex instruction loads more than 4 components.");
8399 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8400 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8403 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8405 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8406 mubuf
->operands
[0] = Operand(resource
);
8407 mubuf
->operands
[1] = Operand(coords
[0]);
8408 mubuf
->operands
[2] = Operand((uint32_t) 0);
8409 mubuf
->definitions
[0] = Definition(tmp_dst
);
8410 mubuf
->idxen
= true;
8411 mubuf
->can_reorder
= true;
8412 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8414 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8418 /* gather MIMG address components */
8419 std::vector
<Temp
> args
;
8421 args
.emplace_back(offset
);
8423 args
.emplace_back(bias
);
8425 args
.emplace_back(compare
);
8427 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8429 args
.insert(args
.end(), coords
.begin(), coords
.end());
8430 if (has_sample_index
)
8431 args
.emplace_back(sample_index
);
8433 args
.emplace_back(lod
);
8435 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8436 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8437 vec
->definitions
[0] = Definition(arg
);
8438 for (unsigned i
= 0; i
< args
.size(); i
++)
8439 vec
->operands
[i
] = Operand(args
[i
]);
8440 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8443 if (instr
->op
== nir_texop_txf
||
8444 instr
->op
== nir_texop_txf_ms
||
8445 instr
->op
== nir_texop_samples_identical
||
8446 instr
->op
== nir_texop_fragment_fetch
||
8447 instr
->op
== nir_texop_fragment_mask_fetch
) {
8448 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8449 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8450 tex
->operands
[0] = Operand(resource
);
8451 tex
->operands
[1] = Operand(s4
); /* no sampler */
8452 tex
->operands
[2] = Operand(arg
);
8457 tex
->definitions
[0] = Definition(tmp_dst
);
8458 tex
->can_reorder
= true;
8459 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8461 if (instr
->op
== nir_texop_samples_identical
) {
8462 assert(dmask
== 1 && dst
.regClass() == v1
);
8463 assert(dst
.id() != tmp_dst
.id());
8465 Temp tmp
= bld
.tmp(bld
.lm
);
8466 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8467 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8470 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8475 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8476 aco_opcode opcode
= aco_opcode::image_sample
;
8477 if (has_offset
) { /* image_sample_*_o */
8479 opcode
= aco_opcode::image_sample_c_o
;
8481 opcode
= aco_opcode::image_sample_c_d_o
;
8483 opcode
= aco_opcode::image_sample_c_b_o
;
8485 opcode
= aco_opcode::image_sample_c_lz_o
;
8487 opcode
= aco_opcode::image_sample_c_l_o
;
8489 opcode
= aco_opcode::image_sample_o
;
8491 opcode
= aco_opcode::image_sample_d_o
;
8493 opcode
= aco_opcode::image_sample_b_o
;
8495 opcode
= aco_opcode::image_sample_lz_o
;
8497 opcode
= aco_opcode::image_sample_l_o
;
8499 } else { /* no offset */
8501 opcode
= aco_opcode::image_sample_c
;
8503 opcode
= aco_opcode::image_sample_c_d
;
8505 opcode
= aco_opcode::image_sample_c_b
;
8507 opcode
= aco_opcode::image_sample_c_lz
;
8509 opcode
= aco_opcode::image_sample_c_l
;
8511 opcode
= aco_opcode::image_sample
;
8513 opcode
= aco_opcode::image_sample_d
;
8515 opcode
= aco_opcode::image_sample_b
;
8517 opcode
= aco_opcode::image_sample_lz
;
8519 opcode
= aco_opcode::image_sample_l
;
8523 if (instr
->op
== nir_texop_tg4
) {
8525 opcode
= aco_opcode::image_gather4_lz_o
;
8527 opcode
= aco_opcode::image_gather4_c_lz_o
;
8529 opcode
= aco_opcode::image_gather4_lz
;
8531 opcode
= aco_opcode::image_gather4_c_lz
;
8533 } else if (instr
->op
== nir_texop_lod
) {
8534 opcode
= aco_opcode::image_get_lod
;
8537 /* we don't need the bias, sample index, compare value or offset to be
8538 * computed in WQM but if the p_create_vector copies the coordinates, then it
8539 * needs to be in WQM */
8540 if (ctx
->stage
== fragment_fs
&&
8541 !has_derivs
&& !has_lod
&& !level_zero
&&
8542 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8543 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8544 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8546 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8547 tex
->operands
[0] = Operand(resource
);
8548 tex
->operands
[1] = Operand(sampler
);
8549 tex
->operands
[2] = Operand(arg
);
8553 tex
->definitions
[0] = Definition(tmp_dst
);
8554 tex
->can_reorder
= true;
8555 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8557 if (tg4_integer_cube_workaround
) {
8558 assert(tmp_dst
.id() != dst
.id());
8559 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8561 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8563 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8564 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8566 if (stype
== GLSL_TYPE_UINT
)
8567 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8569 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8570 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8572 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8573 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8574 val
[0], val
[1], val
[2], val
[3]);
8576 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8577 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8582 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8584 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8585 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8586 return Operand(tmp
.regClass());
8588 return Operand(tmp
);
8591 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8593 aco_ptr
<Pseudo_instruction
> phi
;
8594 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8595 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8597 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8598 logical
|= ctx
->block
->kind
& block_kind_merge
;
8599 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8601 /* we want a sorted list of sources, since the predecessor list is also sorted */
8602 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8603 nir_foreach_phi_src(src
, instr
)
8604 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8606 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8607 unsigned num_operands
= 0;
8608 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8609 unsigned num_defined
= 0;
8610 unsigned cur_pred_idx
= 0;
8611 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8612 if (cur_pred_idx
< preds
.size()) {
8613 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8614 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8615 unsigned skipped
= 0;
8616 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8618 if (cur_pred_idx
+ skipped
< preds
.size()) {
8619 for (unsigned i
= 0; i
< skipped
; i
++)
8620 operands
[num_operands
++] = Operand(dst
.regClass());
8621 cur_pred_idx
+= skipped
;
8626 /* Handle missing predecessors at the end. This shouldn't happen with loop
8627 * headers and we can't ignore these sources for loop header phis. */
8628 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8631 Operand op
= get_phi_operand(ctx
, src
.second
);
8632 operands
[num_operands
++] = op
;
8633 num_defined
+= !op
.isUndefined();
8635 /* handle block_kind_continue_or_break at loop exit blocks */
8636 while (cur_pred_idx
++ < preds
.size())
8637 operands
[num_operands
++] = Operand(dst
.regClass());
8639 /* If the loop ends with a break, still add a linear continue edge in case
8640 * that break is divergent or continue_or_break is used. We'll either remove
8641 * this operand later in visit_loop() if it's not necessary or replace the
8642 * undef with something correct. */
8643 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8644 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8645 nir_block
*last
= nir_loop_last_block(loop
);
8646 if (last
->successors
[0] != instr
->instr
.block
)
8647 operands
[num_operands
++] = Operand(RegClass());
8650 if (num_defined
== 0) {
8651 Builder
bld(ctx
->program
, ctx
->block
);
8652 if (dst
.regClass() == s1
) {
8653 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8654 } else if (dst
.regClass() == v1
) {
8655 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8657 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8658 for (unsigned i
= 0; i
< dst
.size(); i
++)
8659 vec
->operands
[i
] = Operand(0u);
8660 vec
->definitions
[0] = Definition(dst
);
8661 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8666 /* we can use a linear phi in some cases if one src is undef */
8667 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8668 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8670 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8671 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8672 assert(invert
->kind
& block_kind_invert
);
8674 unsigned then_block
= invert
->linear_preds
[0];
8676 Block
* insert_block
= NULL
;
8677 for (unsigned i
= 0; i
< num_operands
; i
++) {
8678 Operand op
= operands
[i
];
8679 if (op
.isUndefined())
8681 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8682 phi
->operands
[0] = op
;
8685 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8686 phi
->operands
[1] = Operand(dst
.regClass());
8687 phi
->definitions
[0] = Definition(dst
);
8688 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8692 /* try to scalarize vector phis */
8693 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8694 // TODO: scalarize linear phis on divergent ifs
8695 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8696 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8697 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8698 Operand src
= operands
[i
];
8699 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8700 can_scalarize
= false;
8702 if (can_scalarize
) {
8703 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8704 assert(dst
.size() % num_components
== 0);
8705 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8707 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8708 for (unsigned k
= 0; k
< num_components
; k
++) {
8709 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8710 for (unsigned i
= 0; i
< num_operands
; i
++) {
8711 Operand src
= operands
[i
];
8712 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8714 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8715 phi
->definitions
[0] = Definition(phi_dst
);
8716 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8717 new_vec
[k
] = phi_dst
;
8718 vec
->operands
[k
] = Operand(phi_dst
);
8720 vec
->definitions
[0] = Definition(dst
);
8721 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8722 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8727 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8728 for (unsigned i
= 0; i
< num_operands
; i
++)
8729 phi
->operands
[i
] = operands
[i
];
8730 phi
->definitions
[0] = Definition(dst
);
8731 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8735 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8737 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8739 assert(dst
.type() == RegType::sgpr
);
8741 if (dst
.size() == 1) {
8742 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8744 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8745 for (unsigned i
= 0; i
< dst
.size(); i
++)
8746 vec
->operands
[i
] = Operand(0u);
8747 vec
->definitions
[0] = Definition(dst
);
8748 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8752 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8754 Builder
bld(ctx
->program
, ctx
->block
);
8755 Block
*logical_target
;
8756 append_logical_end(ctx
->block
);
8757 unsigned idx
= ctx
->block
->index
;
8759 switch (instr
->type
) {
8760 case nir_jump_break
:
8761 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8762 add_logical_edge(idx
, logical_target
);
8763 ctx
->block
->kind
|= block_kind_break
;
8765 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8766 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8767 /* uniform break - directly jump out of the loop */
8768 ctx
->block
->kind
|= block_kind_uniform
;
8769 ctx
->cf_info
.has_branch
= true;
8770 bld
.branch(aco_opcode::p_branch
);
8771 add_linear_edge(idx
, logical_target
);
8774 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8775 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8777 case nir_jump_continue
:
8778 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8779 add_logical_edge(idx
, logical_target
);
8780 ctx
->block
->kind
|= block_kind_continue
;
8782 if (ctx
->cf_info
.parent_if
.is_divergent
) {
8783 /* for potential uniform breaks after this continue,
8784 we must ensure that they are handled correctly */
8785 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
8786 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8787 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8789 /* uniform continue - directly jump to the loop header */
8790 ctx
->block
->kind
|= block_kind_uniform
;
8791 ctx
->cf_info
.has_branch
= true;
8792 bld
.branch(aco_opcode::p_branch
);
8793 add_linear_edge(idx
, logical_target
);
8798 fprintf(stderr
, "Unknown NIR jump instr: ");
8799 nir_print_instr(&instr
->instr
, stderr
);
8800 fprintf(stderr
, "\n");
8804 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
8805 ctx
->cf_info
.exec_potentially_empty_break
= true;
8806 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
8809 /* remove critical edges from linear CFG */
8810 bld
.branch(aco_opcode::p_branch
);
8811 Block
* break_block
= ctx
->program
->create_and_insert_block();
8812 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8813 break_block
->kind
|= block_kind_uniform
;
8814 add_linear_edge(idx
, break_block
);
8815 /* the loop_header pointer might be invalidated by this point */
8816 if (instr
->type
== nir_jump_continue
)
8817 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8818 add_linear_edge(break_block
->index
, logical_target
);
8819 bld
.reset(break_block
);
8820 bld
.branch(aco_opcode::p_branch
);
8822 Block
* continue_block
= ctx
->program
->create_and_insert_block();
8823 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8824 add_linear_edge(idx
, continue_block
);
8825 append_logical_start(continue_block
);
8826 ctx
->block
= continue_block
;
8830 void visit_block(isel_context
*ctx
, nir_block
*block
)
8832 nir_foreach_instr(instr
, block
) {
8833 switch (instr
->type
) {
8834 case nir_instr_type_alu
:
8835 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
8837 case nir_instr_type_load_const
:
8838 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
8840 case nir_instr_type_intrinsic
:
8841 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
8843 case nir_instr_type_tex
:
8844 visit_tex(ctx
, nir_instr_as_tex(instr
));
8846 case nir_instr_type_phi
:
8847 visit_phi(ctx
, nir_instr_as_phi(instr
));
8849 case nir_instr_type_ssa_undef
:
8850 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
8852 case nir_instr_type_deref
:
8854 case nir_instr_type_jump
:
8855 visit_jump(ctx
, nir_instr_as_jump(instr
));
8858 fprintf(stderr
, "Unknown NIR instr type: ");
8859 nir_print_instr(instr
, stderr
);
8860 fprintf(stderr
, "\n");
8865 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8866 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
8871 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
8872 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
8874 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
8875 RegClass rc
= vals
[0].regClass();
8877 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
8879 unsigned next_pred
= 1;
8881 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
8882 Block
& block
= ctx
->program
->blocks
[idx
];
8883 if (block
.loop_nest_depth
!= loop_nest_depth
) {
8884 vals
[idx
- first
] = vals
[idx
- 1 - first
];
8888 if (block
.kind
& block_kind_continue
) {
8889 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
8894 bool all_same
= true;
8895 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
8896 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
8900 val
= vals
[block
.linear_preds
[0] - first
];
8902 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
8903 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
8904 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
8905 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
8906 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
8907 phi
->definitions
[0] = Definition(val
.getTemp());
8908 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
8910 vals
[idx
- first
] = val
;
8913 return vals
[last
- first
];
8916 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
8918 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8919 append_logical_end(ctx
->block
);
8920 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
8921 Builder
bld(ctx
->program
, ctx
->block
);
8922 bld
.branch(aco_opcode::p_branch
);
8923 unsigned loop_preheader_idx
= ctx
->block
->index
;
8925 Block loop_exit
= Block();
8926 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8927 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
8929 Block
* loop_header
= ctx
->program
->create_and_insert_block();
8930 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
8931 loop_header
->kind
|= block_kind_loop_header
;
8932 add_edge(loop_preheader_idx
, loop_header
);
8933 ctx
->block
= loop_header
;
8935 /* emit loop body */
8936 unsigned loop_header_idx
= loop_header
->index
;
8937 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
8938 append_logical_start(ctx
->block
);
8939 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
8941 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8942 if (!ctx
->cf_info
.has_branch
) {
8943 append_logical_end(ctx
->block
);
8944 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
8945 /* Discards can result in code running with an empty exec mask.
8946 * This would result in divergent breaks not ever being taken. As a
8947 * workaround, break the loop when the loop mask is empty instead of
8948 * always continuing. */
8949 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
8950 unsigned block_idx
= ctx
->block
->index
;
8952 /* create helper blocks to avoid critical edges */
8953 Block
*break_block
= ctx
->program
->create_and_insert_block();
8954 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8955 break_block
->kind
= block_kind_uniform
;
8956 bld
.reset(break_block
);
8957 bld
.branch(aco_opcode::p_branch
);
8958 add_linear_edge(block_idx
, break_block
);
8959 add_linear_edge(break_block
->index
, &loop_exit
);
8961 Block
*continue_block
= ctx
->program
->create_and_insert_block();
8962 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8963 continue_block
->kind
= block_kind_uniform
;
8964 bld
.reset(continue_block
);
8965 bld
.branch(aco_opcode::p_branch
);
8966 add_linear_edge(block_idx
, continue_block
);
8967 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8969 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8970 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
8971 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
8973 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
8974 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8975 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8977 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
8980 bld
.reset(ctx
->block
);
8981 bld
.branch(aco_opcode::p_branch
);
8984 /* Fixup phis in loop header from unreachable blocks.
8985 * has_branch/has_divergent_branch also indicates if the loop ends with a
8986 * break/continue instruction, but we don't emit those if unreachable=true */
8988 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
8989 bool linear
= ctx
->cf_info
.has_branch
;
8990 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
8991 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
8992 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
8993 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
8994 /* the last operand should be the one that needs to be removed */
8995 instr
->operands
.pop_back();
8996 } else if (!is_phi(instr
)) {
9002 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9003 * and the previous one shouldn't both happen at once because a break in the
9004 * merge block would get CSE'd */
9005 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9006 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9007 Operand vals
[num_vals
];
9008 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9009 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9010 if (ctx
->cf_info
.has_branch
)
9011 instr
->operands
.pop_back();
9013 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9014 } else if (!is_phi(instr
)) {
9020 ctx
->cf_info
.has_branch
= false;
9022 // TODO: if the loop has not a single exit, we must add one °°
9023 /* emit loop successor block */
9024 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9025 append_logical_start(ctx
->block
);
9028 // TODO: check if it is beneficial to not branch on continues
9029 /* trim linear phis in loop header */
9030 for (auto&& instr
: loop_entry
->instructions
) {
9031 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9032 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9033 new_phi
->definitions
[0] = instr
->definitions
[0];
9034 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9035 new_phi
->operands
[i
] = instr
->operands
[i
];
9036 /* check that the remaining operands are all the same */
9037 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9038 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9039 instr
.swap(new_phi
);
9040 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9049 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9053 append_logical_end(ctx
->block
);
9054 ctx
->block
->kind
|= block_kind_branch
;
9056 /* branch to linear then block */
9057 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9058 aco_ptr
<Pseudo_branch_instruction
> branch
;
9059 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9060 branch
->operands
[0] = Operand(cond
);
9061 ctx
->block
->instructions
.push_back(std::move(branch
));
9063 ic
->BB_if_idx
= ctx
->block
->index
;
9064 ic
->BB_invert
= Block();
9065 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9066 /* Invert blocks are intentionally not marked as top level because they
9067 * are not part of the logical cfg. */
9068 ic
->BB_invert
.kind
|= block_kind_invert
;
9069 ic
->BB_endif
= Block();
9070 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9071 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9073 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9074 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9075 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9076 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9077 ctx
->cf_info
.parent_if
.is_divergent
= true;
9079 /* divergent branches use cbranch_execz */
9080 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9081 ctx
->cf_info
.exec_potentially_empty_break
= false;
9082 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9084 /** emit logical then block */
9085 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9086 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9087 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9088 ctx
->block
= BB_then_logical
;
9089 append_logical_start(BB_then_logical
);
9092 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9094 Block
*BB_then_logical
= ctx
->block
;
9095 append_logical_end(BB_then_logical
);
9096 /* branch from logical then block to invert block */
9097 aco_ptr
<Pseudo_branch_instruction
> branch
;
9098 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9099 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9100 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9101 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9102 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9103 BB_then_logical
->kind
|= block_kind_uniform
;
9104 assert(!ctx
->cf_info
.has_branch
);
9105 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9106 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9108 /** emit linear then block */
9109 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9110 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9111 BB_then_linear
->kind
|= block_kind_uniform
;
9112 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9113 /* branch from linear then block to invert block */
9114 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9115 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9116 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9118 /** emit invert merge block */
9119 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9120 ic
->invert_idx
= ctx
->block
->index
;
9122 /* branch to linear else block (skip else) */
9123 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9124 branch
->operands
[0] = Operand(ic
->cond
);
9125 ctx
->block
->instructions
.push_back(std::move(branch
));
9127 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9128 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9129 ic
->exec_potentially_empty_break_depth_old
=
9130 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9131 /* divergent branches use cbranch_execz */
9132 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9133 ctx
->cf_info
.exec_potentially_empty_break
= false;
9134 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9136 /** emit logical else block */
9137 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9138 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9139 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9140 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9141 ctx
->block
= BB_else_logical
;
9142 append_logical_start(BB_else_logical
);
9145 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9147 Block
*BB_else_logical
= ctx
->block
;
9148 append_logical_end(BB_else_logical
);
9150 /* branch from logical else block to endif block */
9151 aco_ptr
<Pseudo_branch_instruction
> branch
;
9152 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9153 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9154 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9155 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9156 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9157 BB_else_logical
->kind
|= block_kind_uniform
;
9159 assert(!ctx
->cf_info
.has_branch
);
9160 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9163 /** emit linear else block */
9164 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9165 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9166 BB_else_linear
->kind
|= block_kind_uniform
;
9167 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9169 /* branch from linear else block to endif block */
9170 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9171 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9172 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9175 /** emit endif merge block */
9176 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9177 append_logical_start(ctx
->block
);
9180 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9181 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9182 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9183 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9184 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9185 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9186 !ctx
->cf_info
.parent_if
.is_divergent
) {
9187 ctx
->cf_info
.exec_potentially_empty_break
= false;
9188 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9190 /* uniform control flow never has an empty exec-mask */
9191 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9192 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9193 ctx
->cf_info
.exec_potentially_empty_break
= false;
9194 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9198 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9200 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9201 Builder
bld(ctx
->program
, ctx
->block
);
9202 aco_ptr
<Pseudo_branch_instruction
> branch
;
9204 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9206 * Uniform conditionals are represented in the following way*) :
9208 * The linear and logical CFG:
9211 * BB_THEN (logical) BB_ELSE (logical)
9215 * *) Exceptions may be due to break and continue statements within loops
9216 * If a break/continue happens within uniform control flow, it branches
9217 * to the loop exit/entry block. Otherwise, it branches to the next
9220 append_logical_end(ctx
->block
);
9221 ctx
->block
->kind
|= block_kind_uniform
;
9224 assert(cond
.regClass() == bld
.lm
);
9225 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9226 cond
= bool_to_scalar_condition(ctx
, cond
);
9228 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9229 branch
->operands
[0] = Operand(cond
);
9230 branch
->operands
[0].setFixed(scc
);
9231 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9233 unsigned BB_if_idx
= ctx
->block
->index
;
9234 Block BB_endif
= Block();
9235 BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9236 BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9238 /** emit then block */
9239 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9240 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9241 add_edge(BB_if_idx
, BB_then
);
9242 append_logical_start(BB_then
);
9243 ctx
->block
= BB_then
;
9244 visit_cf_list(ctx
, &if_stmt
->then_list
);
9245 BB_then
= ctx
->block
;
9246 bool then_branch
= ctx
->cf_info
.has_branch
;
9247 bool then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9250 append_logical_end(BB_then
);
9251 /* branch from then block to endif block */
9252 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9253 BB_then
->instructions
.emplace_back(std::move(branch
));
9254 add_linear_edge(BB_then
->index
, &BB_endif
);
9255 if (!then_branch_divergent
)
9256 add_logical_edge(BB_then
->index
, &BB_endif
);
9257 BB_then
->kind
|= block_kind_uniform
;
9260 ctx
->cf_info
.has_branch
= false;
9261 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9263 /** emit else block */
9264 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9265 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9266 add_edge(BB_if_idx
, BB_else
);
9267 append_logical_start(BB_else
);
9268 ctx
->block
= BB_else
;
9269 visit_cf_list(ctx
, &if_stmt
->else_list
);
9270 BB_else
= ctx
->block
;
9272 if (!ctx
->cf_info
.has_branch
) {
9273 append_logical_end(BB_else
);
9274 /* branch from then block to endif block */
9275 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9276 BB_else
->instructions
.emplace_back(std::move(branch
));
9277 add_linear_edge(BB_else
->index
, &BB_endif
);
9278 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9279 add_logical_edge(BB_else
->index
, &BB_endif
);
9280 BB_else
->kind
|= block_kind_uniform
;
9283 ctx
->cf_info
.has_branch
&= then_branch
;
9284 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= then_branch_divergent
;
9286 /** emit endif merge block */
9287 if (!ctx
->cf_info
.has_branch
) {
9288 ctx
->block
= ctx
->program
->insert_block(std::move(BB_endif
));
9289 append_logical_start(ctx
->block
);
9291 return !ctx
->cf_info
.has_branch
;
9292 } else { /* non-uniform condition */
9294 * To maintain a logical and linear CFG without critical edges,
9295 * non-uniform conditionals are represented in the following way*) :
9300 * BB_THEN (logical) BB_THEN (linear)
9302 * BB_INVERT (linear)
9304 * BB_ELSE (logical) BB_ELSE (linear)
9311 * BB_THEN (logical) BB_ELSE (logical)
9315 * *) Exceptions may be due to break and continue statements within loops
9320 begin_divergent_if_then(ctx
, &ic
, cond
);
9321 visit_cf_list(ctx
, &if_stmt
->then_list
);
9323 begin_divergent_if_else(ctx
, &ic
);
9324 visit_cf_list(ctx
, &if_stmt
->else_list
);
9326 end_divergent_if(ctx
, &ic
);
9332 static bool visit_cf_list(isel_context
*ctx
,
9333 struct exec_list
*list
)
9335 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9336 switch (node
->type
) {
9337 case nir_cf_node_block
:
9338 visit_block(ctx
, nir_cf_node_as_block(node
));
9340 case nir_cf_node_if
:
9341 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9344 case nir_cf_node_loop
:
9345 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9348 unreachable("unimplemented cf list type");
9354 static void create_null_export(isel_context
*ctx
)
9356 /* Some shader stages always need to have exports.
9357 * So when there is none, we need to add a null export.
9360 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9361 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9362 Builder
bld(ctx
->program
, ctx
->block
);
9363 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9364 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9367 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9369 assert(ctx
->stage
== vertex_vs
||
9370 ctx
->stage
== tess_eval_vs
||
9371 ctx
->stage
== gs_copy_vs
);
9373 int offset
= ctx
->stage
== tess_eval_vs
9374 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9375 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9376 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9377 if (!is_pos
&& !mask
)
9379 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9381 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9382 exp
->enabled_mask
= mask
;
9383 for (unsigned i
= 0; i
< 4; ++i
) {
9384 if (mask
& (1 << i
))
9385 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9387 exp
->operands
[i
] = Operand(v1
);
9389 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9390 * Setting valid_mask=1 prevents it and has no other effect.
9392 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9394 exp
->compressed
= false;
9396 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9398 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9399 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9404 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9406 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9407 exp
->enabled_mask
= 0;
9408 for (unsigned i
= 0; i
< 4; ++i
)
9409 exp
->operands
[i
] = Operand(v1
);
9410 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9411 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9412 exp
->enabled_mask
|= 0x1;
9414 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9415 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9416 exp
->enabled_mask
|= 0x4;
9418 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9419 if (ctx
->options
->chip_class
< GFX9
) {
9420 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9421 exp
->enabled_mask
|= 0x8;
9423 Builder
bld(ctx
->program
, ctx
->block
);
9425 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9426 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9427 if (exp
->operands
[2].isTemp())
9428 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9430 exp
->operands
[2] = Operand(out
);
9431 exp
->enabled_mask
|= 0x4;
9434 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9436 exp
->compressed
= false;
9437 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9438 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9441 static void create_vs_exports(isel_context
*ctx
)
9443 assert(ctx
->stage
== vertex_vs
||
9444 ctx
->stage
== tess_eval_vs
||
9445 ctx
->stage
== gs_copy_vs
);
9447 radv_vs_output_info
*outinfo
= ctx
->stage
== tess_eval_vs
9448 ? &ctx
->program
->info
->tes
.outinfo
9449 : &ctx
->program
->info
->vs
.outinfo
;
9451 if (outinfo
->export_prim_id
) {
9452 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9453 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9456 if (ctx
->options
->key
.has_multiview_view_index
) {
9457 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9458 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9461 /* the order these position exports are created is important */
9463 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9464 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9465 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9466 exported_pos
= true;
9468 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9469 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9470 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9471 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9473 if (ctx
->export_clip_dists
) {
9474 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9475 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9476 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9477 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9480 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9481 if (i
< VARYING_SLOT_VAR0
&& i
!= VARYING_SLOT_LAYER
&&
9482 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9485 export_vs_varying(ctx
, i
, false, NULL
);
9489 create_null_export(ctx
);
9492 static bool export_fs_mrt_z(isel_context
*ctx
)
9494 Builder
bld(ctx
->program
, ctx
->block
);
9495 unsigned enabled_channels
= 0;
9499 for (unsigned i
= 0; i
< 4; ++i
) {
9500 values
[i
] = Operand(v1
);
9503 /* Both stencil and sample mask only need 16-bits. */
9504 if (!ctx
->program
->info
->ps
.writes_z
&&
9505 (ctx
->program
->info
->ps
.writes_stencil
||
9506 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9507 compr
= true; /* COMPR flag */
9509 if (ctx
->program
->info
->ps
.writes_stencil
) {
9510 /* Stencil should be in X[23:16]. */
9511 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9512 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9513 enabled_channels
|= 0x3;
9516 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9517 /* SampleMask should be in Y[15:0]. */
9518 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9519 enabled_channels
|= 0xc;
9522 if (ctx
->program
->info
->ps
.writes_z
) {
9523 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9524 enabled_channels
|= 0x1;
9527 if (ctx
->program
->info
->ps
.writes_stencil
) {
9528 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9529 enabled_channels
|= 0x2;
9532 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9533 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9534 enabled_channels
|= 0x4;
9538 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9539 * writemask component.
9541 if (ctx
->options
->chip_class
== GFX6
&&
9542 ctx
->options
->family
!= CHIP_OLAND
&&
9543 ctx
->options
->family
!= CHIP_HAINAN
) {
9544 enabled_channels
|= 0x1;
9547 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9548 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9553 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9555 Builder
bld(ctx
->program
, ctx
->block
);
9556 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9559 for (unsigned i
= 0; i
< 4; ++i
) {
9560 if (write_mask
& (1 << i
)) {
9561 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9563 values
[i
] = Operand(v1
);
9567 unsigned target
, col_format
;
9568 unsigned enabled_channels
= 0;
9569 aco_opcode compr_op
= (aco_opcode
)0;
9571 slot
-= FRAG_RESULT_DATA0
;
9572 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9573 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9575 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9576 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9580 case V_028714_SPI_SHADER_ZERO
:
9581 enabled_channels
= 0; /* writemask */
9582 target
= V_008DFC_SQ_EXP_NULL
;
9585 case V_028714_SPI_SHADER_32_R
:
9586 enabled_channels
= 1;
9589 case V_028714_SPI_SHADER_32_GR
:
9590 enabled_channels
= 0x3;
9593 case V_028714_SPI_SHADER_32_AR
:
9594 if (ctx
->options
->chip_class
>= GFX10
) {
9595 /* Special case: on GFX10, the outputs are different for 32_AR */
9596 enabled_channels
= 0x3;
9597 values
[1] = values
[3];
9598 values
[3] = Operand(v1
);
9600 enabled_channels
= 0x9;
9604 case V_028714_SPI_SHADER_FP16_ABGR
:
9605 enabled_channels
= 0x5;
9606 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9609 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9610 enabled_channels
= 0x5;
9611 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9614 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9615 enabled_channels
= 0x5;
9616 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9619 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9620 enabled_channels
= 0x5;
9621 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9622 if (is_int8
|| is_int10
) {
9624 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9625 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9627 for (unsigned i
= 0; i
< 4; i
++) {
9628 if ((write_mask
>> i
) & 1) {
9629 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9630 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9638 case V_028714_SPI_SHADER_SINT16_ABGR
:
9639 enabled_channels
= 0x5;
9640 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9641 if (is_int8
|| is_int10
) {
9643 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9644 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9645 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9646 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9648 for (unsigned i
= 0; i
< 4; i
++) {
9649 if ((write_mask
>> i
) & 1) {
9650 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9651 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9653 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9654 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9661 case V_028714_SPI_SHADER_32_ABGR
:
9662 enabled_channels
= 0xF;
9669 if (target
== V_008DFC_SQ_EXP_NULL
)
9672 if ((bool) compr_op
) {
9673 for (int i
= 0; i
< 2; i
++) {
9674 /* check if at least one of the values to be compressed is enabled */
9675 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9677 enabled_channels
|= enabled
<< (i
*2);
9678 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9679 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9680 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9682 values
[i
] = Operand(v1
);
9685 values
[2] = Operand(v1
);
9686 values
[3] = Operand(v1
);
9688 for (int i
= 0; i
< 4; i
++)
9689 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9692 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9693 enabled_channels
, target
, (bool) compr_op
);
9697 static void create_fs_exports(isel_context
*ctx
)
9699 bool exported
= false;
9701 /* Export depth, stencil and sample mask. */
9702 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9703 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9704 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9705 exported
|= export_fs_mrt_z(ctx
);
9707 /* Export all color render targets. */
9708 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9709 if (ctx
->outputs
.mask
[i
])
9710 exported
|= export_fs_mrt_color(ctx
, i
);
9713 create_null_export(ctx
);
9716 static void write_tcs_tess_factors(isel_context
*ctx
)
9718 unsigned outer_comps
;
9719 unsigned inner_comps
;
9721 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
9738 Builder
bld(ctx
->program
, ctx
->block
);
9740 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
9741 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
9742 bld
.sopp(aco_opcode::s_barrier
);
9744 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
9745 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
9747 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
9748 if_context ic_invocation_id_is_zero
;
9749 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
9750 bld
.reset(ctx
->block
);
9752 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
9754 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
9755 unsigned stride
= inner_comps
+ outer_comps
;
9756 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
9760 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
9762 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
9764 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9765 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
9766 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
9768 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9769 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
9771 for (unsigned i
= 0; i
< outer_comps
; ++i
)
9772 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
9773 for (unsigned i
= 0; i
< inner_comps
; ++i
)
9774 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
9777 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
9778 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
9779 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
9780 unsigned tf_const_offset
= 0;
9782 if (ctx
->program
->chip_class
<= GFX8
) {
9783 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
9784 if_context ic_rel_patch_id_is_zero
;
9785 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
9786 bld
.reset(ctx
->block
);
9788 /* Store the dynamic HS control word. */
9789 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
9790 bld
.mubuf(aco_opcode::buffer_store_dword
,
9791 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
9792 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9793 /* disable_wqm */ false, /* glc */ true);
9794 tf_const_offset
+= 4;
9796 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
9797 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
9798 bld
.reset(ctx
->block
);
9801 assert(stride
== 2 || stride
== 4 || stride
== 6);
9802 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
9803 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
9805 /* Store to offchip for TES to read - only if TES reads them */
9806 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
9807 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
9808 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
9810 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
9811 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
9813 if (likely(inner_comps
)) {
9814 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
9815 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
9819 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
9820 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
9823 static void emit_stream_output(isel_context
*ctx
,
9824 Temp
const *so_buffers
,
9825 Temp
const *so_write_offset
,
9826 const struct radv_stream_output
*output
)
9828 unsigned num_comps
= util_bitcount(output
->component_mask
);
9829 unsigned writemask
= (1 << num_comps
) - 1;
9830 unsigned loc
= output
->location
;
9831 unsigned buf
= output
->buffer
;
9833 assert(num_comps
&& num_comps
<= 4);
9834 if (!num_comps
|| num_comps
> 4)
9837 unsigned start
= ffs(output
->component_mask
) - 1;
9840 bool all_undef
= true;
9841 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
9842 for (unsigned i
= 0; i
< num_comps
; i
++) {
9843 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
9844 all_undef
= all_undef
&& !out
[i
].id();
9851 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
9852 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
9853 /* GFX6 doesn't support storing vec3, split it. */
9854 writemask
|= 1u << (start
+ 2);
9858 unsigned offset
= output
->offset
+ start
* 4;
9860 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
9861 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
9862 for (int i
= 0; i
< count
; ++i
)
9863 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
9864 vec
->definitions
[0] = Definition(write_data
);
9865 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9870 opcode
= aco_opcode::buffer_store_dword
;
9873 opcode
= aco_opcode::buffer_store_dwordx2
;
9876 opcode
= aco_opcode::buffer_store_dwordx3
;
9879 opcode
= aco_opcode::buffer_store_dwordx4
;
9882 unreachable("Unsupported dword count.");
9885 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
9886 store
->operands
[0] = Operand(so_buffers
[buf
]);
9887 store
->operands
[1] = Operand(so_write_offset
[buf
]);
9888 store
->operands
[2] = Operand((uint32_t) 0);
9889 store
->operands
[3] = Operand(write_data
);
9890 if (offset
> 4095) {
9891 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9892 Builder
bld(ctx
->program
, ctx
->block
);
9893 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
9895 store
->offset
= offset
;
9897 store
->offen
= true;
9901 store
->can_reorder
= true;
9902 ctx
->block
->instructions
.emplace_back(std::move(store
));
9906 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
9908 Builder
bld(ctx
->program
, ctx
->block
);
9911 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
9912 for (unsigned i
= 0; i
< 4; i
++) {
9913 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
9917 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
9918 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
9921 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
9922 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
9924 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
9926 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
9929 begin_divergent_if_then(ctx
, &ic
, can_emit
);
9931 bld
.reset(ctx
->block
);
9933 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
9935 Temp so_write_offset
[4];
9937 for (unsigned i
= 0; i
< 4; i
++) {
9938 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
9943 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
9944 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
9945 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
9946 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
9948 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
9950 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
9951 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
9952 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
9953 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
9957 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
9958 struct radv_stream_output
*output
=
9959 &ctx
->program
->info
->so
.outputs
[i
];
9960 if (stream
!= output
->stream
)
9963 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
9966 begin_divergent_if_else(ctx
, &ic
);
9967 end_divergent_if(ctx
, &ic
);
9970 } /* end namespace */
9972 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
9974 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
9975 Builder
bld(ctx
->program
, ctx
->block
);
9976 constexpr unsigned hs_idx
= 1u;
9977 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
9978 get_arg(ctx
, ctx
->args
->merged_wave_info
),
9979 Operand((8u << 16) | (hs_idx
* 8u)));
9980 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
9982 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
9984 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9985 get_arg(ctx
, ctx
->args
->rel_auto_id
),
9986 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
9987 ls_has_nonzero_hs_threads
);
9988 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9989 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
9990 get_arg(ctx
, ctx
->args
->rel_auto_id
),
9991 ls_has_nonzero_hs_threads
);
9992 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
9993 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
9994 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
9995 ls_has_nonzero_hs_threads
);
9997 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
9998 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
9999 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10002 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10004 /* Split all arguments except for the first (ring_offsets) and the last
10005 * (exec) so that the dead channels don't stay live throughout the program.
10007 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10008 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10009 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10010 startpgm
->definitions
[i
].regClass().size());
10015 void handle_bc_optimize(isel_context
*ctx
)
10017 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10018 Builder
bld(ctx
->program
, ctx
->block
);
10019 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10020 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10021 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10022 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10023 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10024 if (uses_center
&& uses_centroid
) {
10025 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10026 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10028 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10030 for (unsigned i
= 0; i
< 2; i
++) {
10031 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10032 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10033 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10034 persp_centroid
, persp_center
, sel
);
10036 ctx
->persp_centroid
= bld
.tmp(v2
);
10037 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10038 Operand(new_coord
[0]), Operand(new_coord
[1]));
10039 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10042 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10044 for (unsigned i
= 0; i
< 2; i
++) {
10045 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10046 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10047 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10048 linear_centroid
, linear_center
, sel
);
10050 ctx
->linear_centroid
= bld
.tmp(v2
);
10051 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10052 Operand(new_coord
[0]), Operand(new_coord
[1]));
10053 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10058 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10060 Program
*program
= ctx
->program
;
10062 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10064 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10065 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10066 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10067 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10068 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10070 program
->next_fp_mode
.must_flush_denorms32
=
10071 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10072 program
->next_fp_mode
.must_flush_denorms16_64
=
10073 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10074 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10076 program
->next_fp_mode
.care_about_round32
=
10077 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10079 program
->next_fp_mode
.care_about_round16_64
=
10080 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10081 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10083 /* default to preserving fp16 and fp64 denorms, since it's free */
10084 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10085 program
->next_fp_mode
.denorm16_64
= 0;
10087 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10089 /* preserving fp32 denorms is expensive, so only do it if asked */
10090 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10091 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10093 program
->next_fp_mode
.denorm32
= 0;
10095 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10096 program
->next_fp_mode
.round32
= fp_round_tz
;
10098 program
->next_fp_mode
.round32
= fp_round_ne
;
10100 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10101 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10103 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10105 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10108 void cleanup_cfg(Program
*program
)
10110 /* create linear_succs/logical_succs */
10111 for (Block
& BB
: program
->blocks
) {
10112 for (unsigned idx
: BB
.linear_preds
)
10113 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10114 for (unsigned idx
: BB
.logical_preds
)
10115 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10119 void select_program(Program
*program
,
10120 unsigned shader_count
,
10121 struct nir_shader
*const *shaders
,
10122 ac_shader_config
* config
,
10123 struct radv_shader_args
*args
)
10125 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10126 if_context ic_merged_wave_info
;
10128 for (unsigned i
= 0; i
< shader_count
; i
++) {
10129 nir_shader
*nir
= shaders
[i
];
10130 init_context(&ctx
, nir
);
10132 setup_fp_mode(&ctx
, nir
);
10135 /* needs to be after init_context() for FS */
10136 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10137 append_logical_start(ctx
.block
);
10139 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10140 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10142 split_arguments(&ctx
, startpgm
);
10145 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10146 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10147 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10148 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10149 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10150 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10151 ctx
.stage
== tess_eval_geometry_gs
));
10153 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : (shader_count
>= 2 && !empty_shader
);
10154 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10155 if (check_merged_wave_info
) {
10156 Builder
bld(ctx
.program
, ctx
.block
);
10158 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10159 Temp count
= i
== 0 ? get_arg(&ctx
, args
->merged_wave_info
)
10160 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10161 get_arg(&ctx
, args
->merged_wave_info
), Operand(i
* 8u));
10163 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10166 if (ctx
.program
->wave_size
== 64) {
10167 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10168 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10169 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10171 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10172 cond
= emit_extract_vector(&ctx
, mask
, 0, bld
.lm
);
10175 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10179 Builder
bld(ctx
.program
, ctx
.block
);
10181 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10182 bld
.sopp(aco_opcode::s_barrier
);
10184 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10185 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10187 } else if (ctx
.stage
== geometry_gs
)
10188 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10190 if (ctx
.stage
== fragment_fs
)
10191 handle_bc_optimize(&ctx
);
10193 visit_cf_list(&ctx
, &func
->body
);
10195 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
== vertex_vs
|| ctx
.stage
== tess_eval_vs
))
10196 emit_streamout(&ctx
, 0);
10198 if (ctx
.stage
== vertex_vs
|| ctx
.stage
== tess_eval_vs
) {
10199 create_vs_exports(&ctx
);
10200 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10201 Builder
bld(ctx
.program
, ctx
.block
);
10202 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10203 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10204 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10205 write_tcs_tess_factors(&ctx
);
10208 if (ctx
.stage
== fragment_fs
)
10209 create_fs_exports(&ctx
);
10211 if (endif_merged_wave_info
) {
10212 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10213 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10216 ralloc_free(ctx
.divergent_vals
);
10218 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10219 /* Outputs of the previous stage are inputs to the next stage */
10220 ctx
.inputs
= ctx
.outputs
;
10221 ctx
.outputs
= shader_io_state();
10225 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10227 append_logical_end(ctx
.block
);
10228 ctx
.block
->kind
|= block_kind_uniform
| block_kind_export_end
;
10229 Builder
bld(ctx
.program
, ctx
.block
);
10230 if (ctx
.program
->wb_smem_l1_on_end
)
10231 bld
.smem(aco_opcode::s_dcache_wb
, false);
10232 bld
.sopp(aco_opcode::s_endpgm
);
10234 cleanup_cfg(program
);
10237 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10238 ac_shader_config
* config
,
10239 struct radv_shader_args
*args
)
10241 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10243 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10244 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10245 program
->next_fp_mode
.must_flush_denorms32
= false;
10246 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10247 program
->next_fp_mode
.care_about_round32
= false;
10248 program
->next_fp_mode
.care_about_round16_64
= false;
10249 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10250 program
->next_fp_mode
.denorm32
= 0;
10251 program
->next_fp_mode
.round32
= fp_round_ne
;
10252 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10253 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10255 add_startpgm(&ctx
);
10256 append_logical_start(ctx
.block
);
10258 Builder
bld(ctx
.program
, ctx
.block
);
10260 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10262 Operand
stream_id(0u);
10263 if (args
->shader_info
->so
.num_outputs
)
10264 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10265 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10267 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10269 std::stack
<Block
> endif_blocks
;
10271 for (unsigned stream
= 0; stream
< 4; stream
++) {
10272 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10275 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10276 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10279 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10281 unsigned BB_if_idx
= ctx
.block
->index
;
10282 Block BB_endif
= Block();
10283 if (!stream_id
.isConstant()) {
10285 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10286 append_logical_end(ctx
.block
);
10287 ctx
.block
->kind
|= block_kind_uniform
;
10288 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10290 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10292 ctx
.block
= ctx
.program
->create_and_insert_block();
10293 add_edge(BB_if_idx
, ctx
.block
);
10294 bld
.reset(ctx
.block
);
10295 append_logical_start(ctx
.block
);
10298 unsigned offset
= 0;
10299 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10300 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10303 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10304 unsigned length
= util_last_bit(output_usage_mask
);
10305 for (unsigned j
= 0; j
< length
; ++j
) {
10306 if (!(output_usage_mask
& (1 << j
)))
10309 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10310 Temp voffset
= vtx_offset
;
10311 if (const_offset
>= 4096u) {
10312 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10313 const_offset
%= 4096u;
10316 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10317 mubuf
->definitions
[0] = bld
.def(v1
);
10318 mubuf
->operands
[0] = Operand(gsvs_ring
);
10319 mubuf
->operands
[1] = Operand(voffset
);
10320 mubuf
->operands
[2] = Operand(0u);
10321 mubuf
->offen
= true;
10322 mubuf
->offset
= const_offset
;
10325 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10326 mubuf
->barrier
= barrier_none
;
10327 mubuf
->can_reorder
= true;
10329 ctx
.outputs
.mask
[i
] |= 1 << j
;
10330 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10332 bld
.insert(std::move(mubuf
));
10338 if (args
->shader_info
->so
.num_outputs
) {
10339 emit_streamout(&ctx
, stream
);
10340 bld
.reset(ctx
.block
);
10344 create_vs_exports(&ctx
);
10345 ctx
.block
->kind
|= block_kind_export_end
;
10348 if (!stream_id
.isConstant()) {
10349 append_logical_end(ctx
.block
);
10351 /* branch from then block to endif block */
10352 bld
.branch(aco_opcode::p_branch
);
10353 add_edge(ctx
.block
->index
, &BB_endif
);
10354 ctx
.block
->kind
|= block_kind_uniform
;
10356 /* emit else block */
10357 ctx
.block
= ctx
.program
->create_and_insert_block();
10358 add_edge(BB_if_idx
, ctx
.block
);
10359 bld
.reset(ctx
.block
);
10360 append_logical_start(ctx
.block
);
10362 endif_blocks
.push(std::move(BB_endif
));
10366 while (!endif_blocks
.empty()) {
10367 Block BB_endif
= std::move(endif_blocks
.top());
10368 endif_blocks
.pop();
10370 Block
*BB_else
= ctx
.block
;
10372 append_logical_end(BB_else
);
10373 /* branch from else block to endif block */
10374 bld
.branch(aco_opcode::p_branch
);
10375 add_edge(BB_else
->index
, &BB_endif
);
10376 BB_else
->kind
|= block_kind_uniform
;
10378 /** emit endif merge block */
10379 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10380 bld
.reset(ctx
.block
);
10381 append_logical_start(ctx
.block
);
10384 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10386 append_logical_end(ctx
.block
);
10387 ctx
.block
->kind
|= block_kind_uniform
;
10388 bld
.sopp(aco_opcode::s_endpgm
);
10390 cleanup_cfg(program
);