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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f16
:
630 op
= aco_opcode::v_cmp_gt_f16
;
632 case aco_opcode::v_cmp_ge_f16
:
633 op
= aco_opcode::v_cmp_le_f16
;
635 case aco_opcode::v_cmp_lt_i16
:
636 op
= aco_opcode::v_cmp_gt_i16
;
638 case aco_opcode::v_cmp_ge_i16
:
639 op
= aco_opcode::v_cmp_le_i16
;
641 case aco_opcode::v_cmp_lt_u16
:
642 op
= aco_opcode::v_cmp_gt_u16
;
644 case aco_opcode::v_cmp_ge_u16
:
645 op
= aco_opcode::v_cmp_le_u16
;
647 case aco_opcode::v_cmp_lt_f32
:
648 op
= aco_opcode::v_cmp_gt_f32
;
650 case aco_opcode::v_cmp_ge_f32
:
651 op
= aco_opcode::v_cmp_le_f32
;
653 case aco_opcode::v_cmp_lt_i32
:
654 op
= aco_opcode::v_cmp_gt_i32
;
656 case aco_opcode::v_cmp_ge_i32
:
657 op
= aco_opcode::v_cmp_le_i32
;
659 case aco_opcode::v_cmp_lt_u32
:
660 op
= aco_opcode::v_cmp_gt_u32
;
662 case aco_opcode::v_cmp_ge_u32
:
663 op
= aco_opcode::v_cmp_le_u32
;
665 case aco_opcode::v_cmp_lt_f64
:
666 op
= aco_opcode::v_cmp_gt_f64
;
668 case aco_opcode::v_cmp_ge_f64
:
669 op
= aco_opcode::v_cmp_le_f64
;
671 case aco_opcode::v_cmp_lt_i64
:
672 op
= aco_opcode::v_cmp_gt_i64
;
674 case aco_opcode::v_cmp_ge_i64
:
675 op
= aco_opcode::v_cmp_le_i64
;
677 case aco_opcode::v_cmp_lt_u64
:
678 op
= aco_opcode::v_cmp_gt_u64
;
680 case aco_opcode::v_cmp_ge_u64
:
681 op
= aco_opcode::v_cmp_le_u64
;
683 default: /* eq and ne are commutative */
690 src1
= as_vgpr(ctx
, src1
);
694 Builder
bld(ctx
->program
, ctx
->block
);
695 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
698 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
700 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
701 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
702 Builder
bld(ctx
->program
, ctx
->block
);
704 assert(dst
.regClass() == bld
.lm
);
705 assert(src0
.type() == RegType::sgpr
);
706 assert(src1
.type() == RegType::sgpr
);
707 assert(src0
.regClass() == src1
.regClass());
709 /* Emit the SALU comparison instruction */
710 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
711 /* Turn the result into a per-lane bool */
712 bool_to_vector_condition(ctx
, cmp
, dst
);
715 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
716 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
718 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
719 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
720 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
721 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
723 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
724 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
725 aco_opcode op
= use_valu
? v_op
: s_op
;
726 assert(op
!= aco_opcode::num_opcodes
);
727 assert(dst
.regClass() == ctx
->program
->lane_mask
);
730 emit_vopc_instruction(ctx
, instr
, op
, dst
);
732 emit_sopc_instruction(ctx
, instr
, op
, dst
);
735 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
737 Builder
bld(ctx
->program
, ctx
->block
);
738 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
739 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
741 assert(dst
.regClass() == bld
.lm
);
742 assert(src0
.regClass() == bld
.lm
);
743 assert(src1
.regClass() == bld
.lm
);
745 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
748 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
750 Builder
bld(ctx
->program
, ctx
->block
);
751 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
752 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
753 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
755 assert(cond
.regClass() == bld
.lm
);
757 if (dst
.type() == RegType::vgpr
) {
758 aco_ptr
<Instruction
> bcsel
;
759 if (dst
.regClass() == v2b
) {
760 then
= as_vgpr(ctx
, then
);
761 els
= as_vgpr(ctx
, els
);
763 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
765 } else if (dst
.regClass() == v1
) {
766 then
= as_vgpr(ctx
, then
);
767 els
= as_vgpr(ctx
, els
);
769 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
770 } else if (dst
.regClass() == v2
) {
771 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
772 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
773 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
774 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
776 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
777 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
779 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
781 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
782 nir_print_instr(&instr
->instr
, stderr
);
783 fprintf(stderr
, "\n");
788 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
789 assert(dst
.regClass() == bld
.lm
);
790 assert(then
.regClass() == bld
.lm
);
791 assert(els
.regClass() == bld
.lm
);
794 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
795 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
796 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
797 assert(dst
.size() == then
.size());
798 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
799 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
801 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
802 nir_print_instr(&instr
->instr
, stderr
);
803 fprintf(stderr
, "\n");
808 /* divergent boolean bcsel
809 * this implements bcsel on bools: dst = s0 ? s1 : s2
810 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
811 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
813 if (cond
.id() != then
.id())
814 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
816 if (cond
.id() == els
.id())
817 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
819 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
820 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
823 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
824 aco_opcode op
, uint32_t undo
)
826 /* multiply by 16777216 to handle denormals */
827 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
828 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
829 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
830 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
831 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
833 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
835 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
838 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
840 if (ctx
->block
->fp_mode
.denorm32
== 0) {
841 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
845 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
848 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
850 if (ctx
->block
->fp_mode
.denorm32
== 0) {
851 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
855 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
858 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
860 if (ctx
->block
->fp_mode
.denorm32
== 0) {
861 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
865 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
868 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
870 if (ctx
->block
->fp_mode
.denorm32
== 0) {
871 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
875 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
878 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
880 if (ctx
->options
->chip_class
>= GFX7
)
881 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
883 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
884 /* TODO: create more efficient code! */
885 if (val
.type() == RegType::sgpr
)
886 val
= as_vgpr(ctx
, val
);
888 /* Split the input value. */
889 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
890 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
892 /* Extract the exponent and compute the unbiased value. */
893 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
895 /* Extract the fractional part. */
896 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
897 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
899 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
900 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
902 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
903 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
904 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
905 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
906 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
908 /* Get the sign bit. */
909 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
911 /* Decide the operation to apply depending on the unbiased exponent. */
912 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
913 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
914 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
915 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
916 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
917 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
919 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
922 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
924 if (ctx
->options
->chip_class
>= GFX7
)
925 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
927 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
928 Temp src0
= as_vgpr(ctx
, val
);
930 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
931 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
933 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
934 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
935 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
937 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
938 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
939 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
940 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
942 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
943 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
945 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
947 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
948 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
950 return add
->definitions
[0].getTemp();
953 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
955 if (!instr
->dest
.dest
.is_ssa
) {
956 fprintf(stderr
, "nir alu dst not in ssa: ");
957 nir_print_instr(&instr
->instr
, stderr
);
958 fprintf(stderr
, "\n");
961 Builder
bld(ctx
->program
, ctx
->block
);
962 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
967 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
968 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
969 for (unsigned i
= 0; i
< num
; ++i
)
970 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
972 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
973 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
974 for (unsigned i
= 0; i
< num
; ++i
)
975 vec
->operands
[i
] = Operand
{elems
[i
]};
976 vec
->definitions
[0] = Definition(dst
);
977 ctx
->block
->instructions
.emplace_back(std::move(vec
));
978 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
980 // TODO: that is a bit suboptimal..
981 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
982 for (unsigned i
= 0; i
< num
- 1; ++i
)
983 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
984 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
985 for (unsigned i
= 0; i
< num
; ++i
) {
986 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
988 elems
[bit
/ 32] = elems
[i
];
990 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
991 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
992 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
996 bld
.copy(Definition(dst
), elems
[0]);
998 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1003 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1004 aco_ptr
<Instruction
> mov
;
1005 if (dst
.type() == RegType::sgpr
) {
1006 if (src
.type() == RegType::vgpr
)
1007 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1008 else if (src
.regClass() == s1
)
1009 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1010 else if (src
.regClass() == s2
)
1011 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1013 unreachable("wrong src register class for nir_op_imov");
1014 } else if (dst
.regClass() == v1
) {
1015 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1016 } else if (dst
.regClass() == v2
) {
1017 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1019 nir_print_instr(&instr
->instr
, stderr
);
1020 unreachable("Should have been lowered to scalar.");
1025 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1026 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1027 assert(src
.regClass() == bld
.lm
);
1028 assert(dst
.regClass() == bld
.lm
);
1029 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1030 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1031 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1032 } else if (dst
.regClass() == v1
) {
1033 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1034 } else if (dst
.type() == RegType::sgpr
) {
1035 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1036 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1038 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1039 nir_print_instr(&instr
->instr
, stderr
);
1040 fprintf(stderr
, "\n");
1045 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1046 if (dst
.regClass() == v1
) {
1047 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1048 } else if (dst
.regClass() == s1
) {
1049 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1050 } else if (dst
.size() == 2) {
1051 Temp src0
= bld
.tmp(dst
.type(), 1);
1052 Temp src1
= bld
.tmp(dst
.type(), 1);
1053 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1055 if (dst
.regClass() == s2
) {
1056 Temp carry
= bld
.tmp(s1
);
1057 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1058 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1059 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1061 Temp lower
= bld
.tmp(v1
);
1062 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1063 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1064 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1067 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1068 nir_print_instr(&instr
->instr
, stderr
);
1069 fprintf(stderr
, "\n");
1074 if (dst
.regClass() == s1
) {
1075 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1076 } else if (dst
.regClass() == v1
) {
1077 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1078 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1080 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1081 nir_print_instr(&instr
->instr
, stderr
);
1082 fprintf(stderr
, "\n");
1086 case nir_op_isign
: {
1087 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1088 if (dst
.regClass() == s1
) {
1089 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1090 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1091 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1092 } else if (dst
.regClass() == s2
) {
1093 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1095 if (ctx
->program
->chip_class
>= GFX8
)
1096 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1098 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1099 /* SCC gets zero-extended to 64 bit */
1100 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1101 } else if (dst
.regClass() == v1
) {
1102 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1103 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1104 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1105 } else if (dst
.regClass() == v2
) {
1106 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1107 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1108 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1109 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1110 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1111 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == v1
) {
1121 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1122 } else if (dst
.regClass() == s1
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1134 } else if (dst
.regClass() == s1
) {
1135 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1144 if (dst
.regClass() == v1
) {
1145 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1146 } else if (dst
.regClass() == s1
) {
1147 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1149 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1150 nir_print_instr(&instr
->instr
, stderr
);
1151 fprintf(stderr
, "\n");
1156 if (dst
.regClass() == v1
) {
1157 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1158 } else if (dst
.regClass() == s1
) {
1159 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1161 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1162 nir_print_instr(&instr
->instr
, stderr
);
1163 fprintf(stderr
, "\n");
1168 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1169 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1170 } else if (dst
.regClass() == v1
) {
1171 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1172 } else if (dst
.regClass() == s1
) {
1173 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1174 } else if (dst
.regClass() == s2
) {
1175 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1177 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1178 nir_print_instr(&instr
->instr
, stderr
);
1179 fprintf(stderr
, "\n");
1184 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1185 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1186 } else if (dst
.regClass() == v1
) {
1187 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1188 } else if (dst
.regClass() == s1
) {
1189 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1190 } else if (dst
.regClass() == s2
) {
1191 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1193 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1194 nir_print_instr(&instr
->instr
, stderr
);
1195 fprintf(stderr
, "\n");
1200 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1201 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1202 } else if (dst
.regClass() == v1
) {
1203 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1204 } else if (dst
.regClass() == s1
) {
1205 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1206 } else if (dst
.regClass() == s2
) {
1207 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1209 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1210 nir_print_instr(&instr
->instr
, stderr
);
1211 fprintf(stderr
, "\n");
1216 if (dst
.regClass() == v1
) {
1217 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1218 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1219 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1220 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1221 } else if (dst
.regClass() == v2
) {
1222 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1223 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1224 } else if (dst
.regClass() == s2
) {
1225 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1226 } else if (dst
.regClass() == s1
) {
1227 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1229 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1230 nir_print_instr(&instr
->instr
, stderr
);
1231 fprintf(stderr
, "\n");
1236 if (dst
.regClass() == v1
) {
1237 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1238 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1239 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1240 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1241 } else if (dst
.regClass() == v2
) {
1242 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1243 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1244 } else if (dst
.regClass() == s1
) {
1245 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1246 } else if (dst
.regClass() == s2
) {
1247 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1249 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1250 nir_print_instr(&instr
->instr
, stderr
);
1251 fprintf(stderr
, "\n");
1256 if (dst
.regClass() == v1
) {
1257 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1258 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1259 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1260 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1261 } else if (dst
.regClass() == v2
) {
1262 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1263 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1264 } else if (dst
.regClass() == s1
) {
1265 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1266 } else if (dst
.regClass() == s2
) {
1267 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1269 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1270 nir_print_instr(&instr
->instr
, stderr
);
1271 fprintf(stderr
, "\n");
1275 case nir_op_find_lsb
: {
1276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1277 if (src
.regClass() == s1
) {
1278 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1279 } else if (src
.regClass() == v1
) {
1280 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1281 } else if (src
.regClass() == s2
) {
1282 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1284 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1285 nir_print_instr(&instr
->instr
, stderr
);
1286 fprintf(stderr
, "\n");
1290 case nir_op_ufind_msb
:
1291 case nir_op_ifind_msb
: {
1292 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1293 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1294 aco_opcode op
= src
.regClass() == s2
?
1295 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1296 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1297 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1299 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1300 Operand(src
.size() * 32u - 1u), msb_rev
);
1301 Temp msb
= sub
.def(0).getTemp();
1302 Temp carry
= sub
.def(1).getTemp();
1304 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1305 } else if (src
.regClass() == v1
) {
1306 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1307 Temp msb_rev
= bld
.tmp(v1
);
1308 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1309 Temp msb
= bld
.tmp(v1
);
1310 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1311 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1313 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1314 nir_print_instr(&instr
->instr
, stderr
);
1315 fprintf(stderr
, "\n");
1319 case nir_op_bitfield_reverse
: {
1320 if (dst
.regClass() == s1
) {
1321 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1322 } else if (dst
.regClass() == v1
) {
1323 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1325 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1326 nir_print_instr(&instr
->instr
, stderr
);
1327 fprintf(stderr
, "\n");
1332 if (dst
.regClass() == s1
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1337 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1338 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1339 if (dst
.regClass() == v1
) {
1340 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1344 assert(src0
.size() == 2 && src1
.size() == 2);
1345 Temp src00
= bld
.tmp(src0
.type(), 1);
1346 Temp src01
= bld
.tmp(dst
.type(), 1);
1347 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1348 Temp src10
= bld
.tmp(src1
.type(), 1);
1349 Temp src11
= bld
.tmp(dst
.type(), 1);
1350 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1352 if (dst
.regClass() == s2
) {
1353 Temp carry
= bld
.tmp(s1
);
1354 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1355 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1356 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1357 } else if (dst
.regClass() == v2
) {
1358 Temp dst0
= bld
.tmp(v1
);
1359 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1360 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1361 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1363 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1364 nir_print_instr(&instr
->instr
, stderr
);
1365 fprintf(stderr
, "\n");
1369 case nir_op_uadd_sat
: {
1370 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1371 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1372 if (dst
.regClass() == s1
) {
1373 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1374 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1376 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1377 } else if (dst
.regClass() == v1
) {
1378 if (ctx
->options
->chip_class
>= GFX9
) {
1379 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1380 add
->operands
[0] = Operand(src0
);
1381 add
->operands
[1] = Operand(src1
);
1382 add
->definitions
[0] = Definition(dst
);
1384 ctx
->block
->instructions
.emplace_back(std::move(add
));
1386 if (src1
.regClass() != v1
)
1387 std::swap(src0
, src1
);
1388 assert(src1
.regClass() == v1
);
1389 Temp tmp
= bld
.tmp(v1
);
1390 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1391 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1394 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1395 nir_print_instr(&instr
->instr
, stderr
);
1396 fprintf(stderr
, "\n");
1400 case nir_op_uadd_carry
: {
1401 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1402 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1403 if (dst
.regClass() == s1
) {
1404 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1407 if (dst
.regClass() == v1
) {
1408 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1409 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1413 Temp src00
= bld
.tmp(src0
.type(), 1);
1414 Temp src01
= bld
.tmp(dst
.type(), 1);
1415 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1416 Temp src10
= bld
.tmp(src1
.type(), 1);
1417 Temp src11
= bld
.tmp(dst
.type(), 1);
1418 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1419 if (dst
.regClass() == s2
) {
1420 Temp carry
= bld
.tmp(s1
);
1421 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1422 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1423 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1424 } else if (dst
.regClass() == v2
) {
1425 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1426 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1427 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1428 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1430 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1431 nir_print_instr(&instr
->instr
, stderr
);
1432 fprintf(stderr
, "\n");
1437 if (dst
.regClass() == s1
) {
1438 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1442 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1443 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1444 if (dst
.regClass() == v1
) {
1445 bld
.vsub32(Definition(dst
), src0
, src1
);
1449 Temp src00
= bld
.tmp(src0
.type(), 1);
1450 Temp src01
= bld
.tmp(dst
.type(), 1);
1451 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1452 Temp src10
= bld
.tmp(src1
.type(), 1);
1453 Temp src11
= bld
.tmp(dst
.type(), 1);
1454 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1455 if (dst
.regClass() == s2
) {
1456 Temp carry
= bld
.tmp(s1
);
1457 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1458 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1459 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1460 } else if (dst
.regClass() == v2
) {
1461 Temp lower
= bld
.tmp(v1
);
1462 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1463 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1466 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1467 nir_print_instr(&instr
->instr
, stderr
);
1468 fprintf(stderr
, "\n");
1472 case nir_op_usub_borrow
: {
1473 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1474 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1475 if (dst
.regClass() == s1
) {
1476 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1478 } else if (dst
.regClass() == v1
) {
1479 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1480 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1484 Temp src00
= bld
.tmp(src0
.type(), 1);
1485 Temp src01
= bld
.tmp(dst
.type(), 1);
1486 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1487 Temp src10
= bld
.tmp(src1
.type(), 1);
1488 Temp src11
= bld
.tmp(dst
.type(), 1);
1489 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1490 if (dst
.regClass() == s2
) {
1491 Temp borrow
= bld
.tmp(s1
);
1492 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1493 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1495 } else if (dst
.regClass() == v2
) {
1496 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1497 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1498 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1499 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1501 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1502 nir_print_instr(&instr
->instr
, stderr
);
1503 fprintf(stderr
, "\n");
1508 if (dst
.regClass() == v1
) {
1509 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1510 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1511 } else if (dst
.regClass() == s1
) {
1512 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1514 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1515 nir_print_instr(&instr
->instr
, stderr
);
1516 fprintf(stderr
, "\n");
1520 case nir_op_umul_high
: {
1521 if (dst
.regClass() == v1
) {
1522 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1523 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1524 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1525 } else if (dst
.regClass() == s1
) {
1526 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1527 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1528 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1530 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1531 nir_print_instr(&instr
->instr
, stderr
);
1532 fprintf(stderr
, "\n");
1536 case nir_op_imul_high
: {
1537 if (dst
.regClass() == v1
) {
1538 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1539 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1540 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1541 } else if (dst
.regClass() == s1
) {
1542 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1543 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1544 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1546 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1547 nir_print_instr(&instr
->instr
, stderr
);
1548 fprintf(stderr
, "\n");
1553 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1554 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1555 if (dst
.regClass() == v2b
) {
1556 Temp tmp
= bld
.tmp(v1
);
1557 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1558 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1559 } else if (dst
.regClass() == v1
) {
1560 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1561 } else if (dst
.regClass() == v2
) {
1562 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1564 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1565 nir_print_instr(&instr
->instr
, stderr
);
1566 fprintf(stderr
, "\n");
1571 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1572 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1573 if (dst
.regClass() == v2b
) {
1574 Temp tmp
= bld
.tmp(v1
);
1575 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1576 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1577 } else if (dst
.regClass() == v1
) {
1578 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1579 } else if (dst
.regClass() == v2
) {
1580 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1582 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1583 nir_print_instr(&instr
->instr
, stderr
);
1584 fprintf(stderr
, "\n");
1589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1590 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1591 if (dst
.regClass() == v2b
) {
1592 Temp tmp
= bld
.tmp(v1
);
1593 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1594 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1596 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1597 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1598 } else if (dst
.regClass() == v1
) {
1599 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1600 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1602 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1603 } else if (dst
.regClass() == v2
) {
1604 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1606 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1609 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1610 nir_print_instr(&instr
->instr
, stderr
);
1611 fprintf(stderr
, "\n");
1616 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1617 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1618 if (dst
.regClass() == v2b
) {
1619 // TODO: check fp_mode.must_flush_denorms16_64
1620 Temp tmp
= bld
.tmp(v1
);
1621 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1622 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1623 } else if (dst
.regClass() == v1
) {
1624 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1625 } else if (dst
.regClass() == v2
) {
1626 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1627 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1628 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1630 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1633 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1634 nir_print_instr(&instr
->instr
, stderr
);
1635 fprintf(stderr
, "\n");
1640 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1641 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1642 if (dst
.regClass() == v2b
) {
1643 // TODO: check fp_mode.must_flush_denorms16_64
1644 Temp tmp
= bld
.tmp(v1
);
1645 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1646 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1647 } else if (dst
.regClass() == v1
) {
1648 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1649 } else if (dst
.regClass() == v2
) {
1650 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1651 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1652 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1654 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1657 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1658 nir_print_instr(&instr
->instr
, stderr
);
1659 fprintf(stderr
, "\n");
1663 case nir_op_fmax3
: {
1664 if (dst
.regClass() == v2b
) {
1665 Temp tmp
= bld
.tmp(v1
);
1666 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1667 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1668 } else if (dst
.regClass() == v1
) {
1669 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1671 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1672 nir_print_instr(&instr
->instr
, stderr
);
1673 fprintf(stderr
, "\n");
1677 case nir_op_fmin3
: {
1678 if (dst
.regClass() == v2b
) {
1679 Temp tmp
= bld
.tmp(v1
);
1680 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1681 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1682 } else if (dst
.regClass() == v1
) {
1683 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1685 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1686 nir_print_instr(&instr
->instr
, stderr
);
1687 fprintf(stderr
, "\n");
1691 case nir_op_fmed3
: {
1692 if (dst
.regClass() == v2b
) {
1693 Temp tmp
= bld
.tmp(v1
);
1694 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1695 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1696 } else if (dst
.regClass() == v1
) {
1697 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1699 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1700 nir_print_instr(&instr
->instr
, stderr
);
1701 fprintf(stderr
, "\n");
1705 case nir_op_umax3
: {
1706 if (dst
.size() == 1) {
1707 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1709 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1710 nir_print_instr(&instr
->instr
, stderr
);
1711 fprintf(stderr
, "\n");
1715 case nir_op_umin3
: {
1716 if (dst
.size() == 1) {
1717 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1719 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1720 nir_print_instr(&instr
->instr
, stderr
);
1721 fprintf(stderr
, "\n");
1725 case nir_op_umed3
: {
1726 if (dst
.size() == 1) {
1727 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1729 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1730 nir_print_instr(&instr
->instr
, stderr
);
1731 fprintf(stderr
, "\n");
1735 case nir_op_imax3
: {
1736 if (dst
.size() == 1) {
1737 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1739 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1740 nir_print_instr(&instr
->instr
, stderr
);
1741 fprintf(stderr
, "\n");
1745 case nir_op_imin3
: {
1746 if (dst
.size() == 1) {
1747 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1749 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1750 nir_print_instr(&instr
->instr
, stderr
);
1751 fprintf(stderr
, "\n");
1755 case nir_op_imed3
: {
1756 if (dst
.size() == 1) {
1757 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1759 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1760 nir_print_instr(&instr
->instr
, stderr
);
1761 fprintf(stderr
, "\n");
1765 case nir_op_cube_face_coord
: {
1766 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1767 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1768 emit_extract_vector(ctx
, in
, 1, v1
),
1769 emit_extract_vector(ctx
, in
, 2, v1
) };
1770 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1771 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1772 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1773 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1774 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1775 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1776 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1779 case nir_op_cube_face_index
: {
1780 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1781 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1782 emit_extract_vector(ctx
, in
, 1, v1
),
1783 emit_extract_vector(ctx
, in
, 2, v1
) };
1784 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1787 case nir_op_bcsel
: {
1788 emit_bcsel(ctx
, instr
, dst
);
1792 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1793 if (dst
.regClass() == v2b
) {
1794 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1795 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1796 } else if (dst
.regClass() == v1
) {
1797 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1798 } else if (dst
.regClass() == v2
) {
1799 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1801 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1802 nir_print_instr(&instr
->instr
, stderr
);
1803 fprintf(stderr
, "\n");
1808 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1809 if (dst
.regClass() == v2b
) {
1810 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1811 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1812 } else if (dst
.regClass() == v1
) {
1813 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1814 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1815 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1816 } else if (dst
.regClass() == v2
) {
1817 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1818 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1819 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1820 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1821 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1822 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1825 nir_print_instr(&instr
->instr
, stderr
);
1826 fprintf(stderr
, "\n");
1831 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1832 if (dst
.regClass() == v2b
) {
1833 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1834 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1835 } else if (dst
.regClass() == v1
) {
1836 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1837 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1838 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1839 } else if (dst
.regClass() == v2
) {
1840 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1841 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1842 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1843 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1844 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1845 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1847 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1848 nir_print_instr(&instr
->instr
, stderr
);
1849 fprintf(stderr
, "\n");
1854 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1855 if (dst
.regClass() == v2b
) {
1856 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1857 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1858 } else if (dst
.regClass() == v1
) {
1859 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1860 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1861 // TODO: confirm that this holds under any circumstances
1862 } else if (dst
.regClass() == v2
) {
1863 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1864 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1867 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1868 nir_print_instr(&instr
->instr
, stderr
);
1869 fprintf(stderr
, "\n");
1873 case nir_op_flog2
: {
1874 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1875 if (dst
.regClass() == v2b
) {
1876 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1877 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1878 } else if (dst
.regClass() == v1
) {
1879 emit_log2(ctx
, bld
, Definition(dst
), src
);
1881 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1882 nir_print_instr(&instr
->instr
, stderr
);
1883 fprintf(stderr
, "\n");
1888 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1889 if (dst
.regClass() == v2b
) {
1890 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1891 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1892 } else if (dst
.regClass() == v1
) {
1893 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1894 } else if (dst
.regClass() == v2
) {
1895 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1897 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1898 nir_print_instr(&instr
->instr
, stderr
);
1899 fprintf(stderr
, "\n");
1903 case nir_op_fexp2
: {
1904 if (dst
.regClass() == v2b
) {
1905 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1906 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1907 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1908 } else if (dst
.regClass() == v1
) {
1909 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1911 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1912 nir_print_instr(&instr
->instr
, stderr
);
1913 fprintf(stderr
, "\n");
1917 case nir_op_fsqrt
: {
1918 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1919 if (dst
.regClass() == v2b
) {
1920 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1921 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1922 } else if (dst
.regClass() == v1
) {
1923 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1924 } else if (dst
.regClass() == v2
) {
1925 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1927 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1928 nir_print_instr(&instr
->instr
, stderr
);
1929 fprintf(stderr
, "\n");
1933 case nir_op_ffract
: {
1934 if (dst
.regClass() == v2b
) {
1935 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1936 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1937 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1938 } else if (dst
.regClass() == v1
) {
1939 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1940 } else if (dst
.regClass() == v2
) {
1941 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1943 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1944 nir_print_instr(&instr
->instr
, stderr
);
1945 fprintf(stderr
, "\n");
1949 case nir_op_ffloor
: {
1950 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1951 if (dst
.regClass() == v2b
) {
1952 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1953 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1954 } else if (dst
.regClass() == v1
) {
1955 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1956 } else if (dst
.regClass() == v2
) {
1957 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1959 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1960 nir_print_instr(&instr
->instr
, stderr
);
1961 fprintf(stderr
, "\n");
1965 case nir_op_fceil
: {
1966 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1967 if (dst
.regClass() == v2b
) {
1968 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
1969 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1970 } else if (dst
.regClass() == v1
) {
1971 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1972 } else if (dst
.regClass() == v2
) {
1973 if (ctx
->options
->chip_class
>= GFX7
) {
1974 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1976 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1977 /* trunc = trunc(src0)
1978 * if (src0 > 0.0 && src0 != trunc)
1981 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1982 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1983 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1984 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1985 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1986 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1987 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1990 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1991 nir_print_instr(&instr
->instr
, stderr
);
1992 fprintf(stderr
, "\n");
1996 case nir_op_ftrunc
: {
1997 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1998 if (dst
.regClass() == v2b
) {
1999 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2000 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2001 } else if (dst
.regClass() == v1
) {
2002 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2003 } else if (dst
.regClass() == v2
) {
2004 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2006 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2007 nir_print_instr(&instr
->instr
, stderr
);
2008 fprintf(stderr
, "\n");
2012 case nir_op_fround_even
: {
2013 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2014 if (dst
.regClass() == v2b
) {
2015 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2016 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2017 } else if (dst
.regClass() == v1
) {
2018 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2019 } else if (dst
.regClass() == v2
) {
2020 if (ctx
->options
->chip_class
>= GFX7
) {
2021 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2023 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2024 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2025 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2027 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2028 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2029 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2030 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2031 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2032 tmp
= sub
->definitions
[0].getTemp();
2034 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2035 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2036 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2037 Temp cond
= vop3
->definitions
[0].getTemp();
2039 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2040 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2041 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2042 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2044 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2055 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2056 aco_ptr
<Instruction
> norm
;
2057 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2058 if (dst
.regClass() == v2b
) {
2059 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2060 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2061 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2062 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2063 } else if (dst
.regClass() == v1
) {
2064 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2066 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2067 if (ctx
->options
->chip_class
< GFX9
)
2068 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2070 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2071 bld
.vop1(opcode
, Definition(dst
), tmp
);
2073 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2074 nir_print_instr(&instr
->instr
, stderr
);
2075 fprintf(stderr
, "\n");
2079 case nir_op_ldexp
: {
2080 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2081 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2082 if (dst
.regClass() == v2b
) {
2083 Temp tmp
= bld
.tmp(v1
);
2084 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2085 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2086 } else if (dst
.regClass() == v1
) {
2087 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2088 } else if (dst
.regClass() == v2
) {
2089 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2091 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2092 nir_print_instr(&instr
->instr
, stderr
);
2093 fprintf(stderr
, "\n");
2097 case nir_op_frexp_sig
: {
2098 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2099 if (dst
.regClass() == v2b
) {
2100 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2101 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2102 } else if (dst
.regClass() == v1
) {
2103 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2104 } else if (dst
.regClass() == v2
) {
2105 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2107 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2108 nir_print_instr(&instr
->instr
, stderr
);
2109 fprintf(stderr
, "\n");
2113 case nir_op_frexp_exp
: {
2114 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2115 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2116 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2117 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2118 sdwa
->operands
[0] = Operand(tmp
);
2119 sdwa
->definitions
[0] = Definition(dst
);
2120 sdwa
->sel
[0] = sdwa_sbyte
;
2121 sdwa
->dst_sel
= sdwa_sdword
;
2122 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2123 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2124 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2125 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2126 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2128 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2129 nir_print_instr(&instr
->instr
, stderr
);
2130 fprintf(stderr
, "\n");
2134 case nir_op_fsign
: {
2135 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2136 if (dst
.regClass() == v2b
) {
2137 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2138 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2139 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2140 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2141 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2142 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2143 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2144 } else if (dst
.regClass() == v1
) {
2145 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2146 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2147 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2148 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2149 } else if (dst
.regClass() == v2
) {
2150 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2151 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2152 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2154 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2155 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2156 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2158 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2160 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2161 nir_print_instr(&instr
->instr
, stderr
);
2162 fprintf(stderr
, "\n");
2167 case nir_op_f2f16_rtne
: {
2168 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2169 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2170 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2171 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2172 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2175 case nir_op_f2f16_rtz
: {
2176 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2177 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2178 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2179 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2180 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2183 case nir_op_f2f32
: {
2184 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2185 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2186 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2187 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2189 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2190 nir_print_instr(&instr
->instr
, stderr
);
2191 fprintf(stderr
, "\n");
2195 case nir_op_f2f64
: {
2196 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2197 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2198 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2199 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2202 case nir_op_i2f16
: {
2203 assert(dst
.regClass() == v2b
);
2204 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_i16
, bld
.def(v1
),
2205 get_alu_src(ctx
, instr
->src
[0]));
2206 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2209 case nir_op_i2f32
: {
2210 assert(dst
.size() == 1);
2211 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2214 case nir_op_i2f64
: {
2215 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2216 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2217 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2218 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2219 RegClass rc
= RegClass(src
.type(), 1);
2220 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2221 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2222 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2223 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2224 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2225 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2228 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2229 nir_print_instr(&instr
->instr
, stderr
);
2230 fprintf(stderr
, "\n");
2234 case nir_op_u2f16
: {
2235 assert(dst
.regClass() == v2b
);
2236 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_u16
, bld
.def(v1
),
2237 get_alu_src(ctx
, instr
->src
[0]));
2238 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2241 case nir_op_u2f32
: {
2242 assert(dst
.size() == 1);
2243 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2246 case nir_op_u2f64
: {
2247 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2248 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2249 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2250 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2251 RegClass rc
= RegClass(src
.type(), 1);
2252 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2253 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2254 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2255 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2256 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2257 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2259 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2260 nir_print_instr(&instr
->instr
, stderr
);
2261 fprintf(stderr
, "\n");
2266 case nir_op_f2i16
: {
2267 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2268 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2269 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2270 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2271 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2273 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2275 if (dst
.type() == RegType::vgpr
)
2276 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2278 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2282 case nir_op_f2u16
: {
2283 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2284 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2285 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2286 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2287 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2289 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2291 if (dst
.type() == RegType::vgpr
)
2292 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2294 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2297 case nir_op_f2i32
: {
2298 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2299 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2300 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2301 if (dst
.type() == RegType::vgpr
) {
2302 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2304 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2305 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2307 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2308 if (dst
.type() == RegType::vgpr
)
2309 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2311 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2312 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2314 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2315 if (dst
.type() == RegType::vgpr
)
2316 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2318 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2319 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2322 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2323 nir_print_instr(&instr
->instr
, stderr
);
2324 fprintf(stderr
, "\n");
2328 case nir_op_f2u32
: {
2329 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2330 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2331 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2332 if (dst
.type() == RegType::vgpr
) {
2333 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2335 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2336 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2338 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2339 if (dst
.type() == RegType::vgpr
)
2340 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2342 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2343 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2345 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2346 if (dst
.type() == RegType::vgpr
)
2347 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2349 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2350 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2353 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2354 nir_print_instr(&instr
->instr
, stderr
);
2355 fprintf(stderr
, "\n");
2359 case nir_op_f2i64
: {
2360 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2361 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2362 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2364 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2365 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2366 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2367 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2368 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2369 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2370 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2371 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2372 Temp new_exponent
= bld
.tmp(v1
);
2373 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2374 if (ctx
->program
->chip_class
>= GFX8
)
2375 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2377 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2378 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2379 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2380 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2381 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2382 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2383 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2384 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2385 Temp new_lower
= bld
.tmp(v1
);
2386 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2387 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2388 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2390 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2391 if (src
.type() == RegType::vgpr
)
2392 src
= bld
.as_uniform(src
);
2393 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2394 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2395 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2396 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2397 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2398 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2399 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2400 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2401 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2402 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2403 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2404 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2405 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2406 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2407 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2408 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2409 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2410 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2411 Temp borrow
= bld
.tmp(s1
);
2412 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2413 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2414 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2416 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2417 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2418 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2419 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2420 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2421 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2422 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2423 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2424 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2425 if (dst
.type() == RegType::sgpr
) {
2426 lower
= bld
.as_uniform(lower
);
2427 upper
= bld
.as_uniform(upper
);
2429 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2432 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2433 nir_print_instr(&instr
->instr
, stderr
);
2434 fprintf(stderr
, "\n");
2438 case nir_op_f2u64
: {
2439 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2440 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2441 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2443 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2444 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2445 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2446 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2447 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2448 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2449 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2450 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2451 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2452 Temp new_exponent
= bld
.tmp(v1
);
2453 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2454 if (ctx
->program
->chip_class
>= GFX8
)
2455 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2457 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2458 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2459 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2460 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2461 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2462 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2463 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2466 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2467 if (src
.type() == RegType::vgpr
)
2468 src
= bld
.as_uniform(src
);
2469 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2470 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2471 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2472 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2473 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2474 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2475 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2476 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2477 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2478 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2479 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2480 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2481 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2482 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2483 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2484 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2485 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2486 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2488 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2489 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2490 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2491 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2492 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2493 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2494 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2495 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2496 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2497 if (dst
.type() == RegType::sgpr
) {
2498 lower
= bld
.as_uniform(lower
);
2499 upper
= bld
.as_uniform(upper
);
2501 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2504 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2505 nir_print_instr(&instr
->instr
, stderr
);
2506 fprintf(stderr
, "\n");
2510 case nir_op_b2f16
: {
2511 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2512 assert(src
.regClass() == bld
.lm
);
2514 if (dst
.regClass() == s1
) {
2515 src
= bool_to_scalar_condition(ctx
, src
);
2516 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2517 } else if (dst
.regClass() == v2b
) {
2518 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2519 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2520 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2522 unreachable("Wrong destination register class for nir_op_b2f16.");
2526 case nir_op_b2f32
: {
2527 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2528 assert(src
.regClass() == bld
.lm
);
2530 if (dst
.regClass() == s1
) {
2531 src
= bool_to_scalar_condition(ctx
, src
);
2532 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2533 } else if (dst
.regClass() == v1
) {
2534 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2536 unreachable("Wrong destination register class for nir_op_b2f32.");
2540 case nir_op_b2f64
: {
2541 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2542 assert(src
.regClass() == bld
.lm
);
2544 if (dst
.regClass() == s2
) {
2545 src
= bool_to_scalar_condition(ctx
, src
);
2546 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2547 } else if (dst
.regClass() == v2
) {
2548 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2549 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2550 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2552 unreachable("Wrong destination register class for nir_op_b2f64.");
2558 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2559 /* we can actually just say dst = src */
2560 if (src
.regClass() == s1
)
2561 bld
.copy(Definition(dst
), src
);
2563 emit_extract_vector(ctx
, src
, 0, dst
);
2566 case nir_op_i2i16
: {
2567 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2568 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2569 if (dst
.regClass() == s1
) {
2570 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2572 assert(src
.regClass() == v1b
);
2573 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2574 sdwa
->operands
[0] = Operand(src
);
2575 sdwa
->definitions
[0] = Definition(dst
);
2576 sdwa
->sel
[0] = sdwa_sbyte
;
2577 sdwa
->dst_sel
= sdwa_sword
;
2578 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2581 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2582 /* we can actually just say dst = src */
2583 if (src
.regClass() == s1
)
2584 bld
.copy(Definition(dst
), src
);
2586 emit_extract_vector(ctx
, src
, 0, dst
);
2590 case nir_op_u2u16
: {
2591 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2592 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2593 if (dst
.regClass() == s1
)
2594 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2596 assert(src
.regClass() == v1b
);
2597 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2598 sdwa
->operands
[0] = Operand(src
);
2599 sdwa
->definitions
[0] = Definition(dst
);
2600 sdwa
->sel
[0] = sdwa_ubyte
;
2601 sdwa
->dst_sel
= sdwa_uword
;
2602 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2605 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2606 /* we can actually just say dst = src */
2607 if (src
.regClass() == s1
)
2608 bld
.copy(Definition(dst
), src
);
2610 emit_extract_vector(ctx
, src
, 0, dst
);
2614 case nir_op_i2i32
: {
2615 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2616 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2617 if (dst
.regClass() == s1
) {
2618 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2620 assert(src
.regClass() == v1b
);
2621 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2622 sdwa
->operands
[0] = Operand(src
);
2623 sdwa
->definitions
[0] = Definition(dst
);
2624 sdwa
->sel
[0] = sdwa_sbyte
;
2625 sdwa
->dst_sel
= sdwa_sdword
;
2626 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2628 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2629 if (dst
.regClass() == s1
) {
2630 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2632 assert(src
.regClass() == v2b
);
2633 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2634 sdwa
->operands
[0] = Operand(src
);
2635 sdwa
->definitions
[0] = Definition(dst
);
2636 sdwa
->sel
[0] = sdwa_sword
;
2637 sdwa
->dst_sel
= sdwa_udword
;
2638 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2640 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2641 /* we can actually just say dst = src, as it would map the lower register */
2642 emit_extract_vector(ctx
, src
, 0, dst
);
2644 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2645 nir_print_instr(&instr
->instr
, stderr
);
2646 fprintf(stderr
, "\n");
2650 case nir_op_u2u32
: {
2651 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2652 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2653 if (dst
.regClass() == s1
)
2654 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2656 assert(src
.regClass() == v1b
);
2657 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2658 sdwa
->operands
[0] = Operand(src
);
2659 sdwa
->definitions
[0] = Definition(dst
);
2660 sdwa
->sel
[0] = sdwa_ubyte
;
2661 sdwa
->dst_sel
= sdwa_udword
;
2662 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2664 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2665 if (dst
.regClass() == s1
) {
2666 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2668 assert(src
.regClass() == v2b
);
2669 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2670 sdwa
->operands
[0] = Operand(src
);
2671 sdwa
->definitions
[0] = Definition(dst
);
2672 sdwa
->sel
[0] = sdwa_uword
;
2673 sdwa
->dst_sel
= sdwa_udword
;
2674 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2676 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2677 /* we can actually just say dst = src, as it would map the lower register */
2678 emit_extract_vector(ctx
, src
, 0, dst
);
2680 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2681 nir_print_instr(&instr
->instr
, stderr
);
2682 fprintf(stderr
, "\n");
2686 case nir_op_i2i64
: {
2687 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2688 if (src
.regClass() == s1
) {
2689 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2690 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2691 } else if (src
.regClass() == v1
) {
2692 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2693 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2695 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2696 nir_print_instr(&instr
->instr
, stderr
);
2697 fprintf(stderr
, "\n");
2701 case nir_op_u2u64
: {
2702 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2703 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2704 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2706 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2707 nir_print_instr(&instr
->instr
, stderr
);
2708 fprintf(stderr
, "\n");
2713 case nir_op_b2i32
: {
2714 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2715 assert(src
.regClass() == bld
.lm
);
2717 if (dst
.regClass() == s1
) {
2718 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2719 bool_to_scalar_condition(ctx
, src
, dst
);
2720 } else if (dst
.regClass() == v1
) {
2721 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2723 unreachable("Invalid register class for b2i32");
2729 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2730 assert(dst
.regClass() == bld
.lm
);
2732 if (src
.type() == RegType::vgpr
) {
2733 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2734 assert(dst
.regClass() == bld
.lm
);
2735 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2736 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2738 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2740 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2741 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2743 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2744 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2746 bool_to_vector_condition(ctx
, tmp
, dst
);
2750 case nir_op_pack_64_2x32_split
: {
2751 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2752 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2754 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2757 case nir_op_unpack_64_2x32_split_x
:
2758 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2760 case nir_op_unpack_64_2x32_split_y
:
2761 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2763 case nir_op_unpack_32_2x16_split_x
:
2764 if (dst
.type() == RegType::vgpr
) {
2765 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2767 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2770 case nir_op_unpack_32_2x16_split_y
:
2771 if (dst
.type() == RegType::vgpr
) {
2772 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2774 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2777 case nir_op_pack_32_2x16_split
: {
2778 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2779 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2780 if (dst
.regClass() == v1
) {
2781 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2782 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2783 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2785 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2786 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2787 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2791 case nir_op_pack_half_2x16
: {
2792 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2794 if (dst
.regClass() == v1
) {
2795 Temp src0
= bld
.tmp(v1
);
2796 Temp src1
= bld
.tmp(v1
);
2797 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2798 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2799 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2801 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2802 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2803 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2805 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2806 nir_print_instr(&instr
->instr
, stderr
);
2807 fprintf(stderr
, "\n");
2811 case nir_op_unpack_half_2x16_split_x
: {
2812 if (dst
.regClass() == v1
) {
2813 Builder
bld(ctx
->program
, ctx
->block
);
2814 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2816 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2817 nir_print_instr(&instr
->instr
, stderr
);
2818 fprintf(stderr
, "\n");
2822 case nir_op_unpack_half_2x16_split_y
: {
2823 if (dst
.regClass() == v1
) {
2824 Builder
bld(ctx
->program
, ctx
->block
);
2825 /* TODO: use SDWA here */
2826 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2827 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2829 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2830 nir_print_instr(&instr
->instr
, stderr
);
2831 fprintf(stderr
, "\n");
2835 case nir_op_fquantize2f16
: {
2836 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2837 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2840 if (ctx
->program
->chip_class
>= GFX8
) {
2841 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2842 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2843 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2845 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2846 * so compare the result and flush to 0 if it's smaller.
2848 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2849 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2850 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2851 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2852 cmp_res
= vop3
->definitions
[0].getTemp();
2855 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2856 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2857 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2859 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2864 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2865 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2867 if (dst
.regClass() == s1
) {
2868 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2869 } else if (dst
.regClass() == v1
) {
2870 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2872 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2873 nir_print_instr(&instr
->instr
, stderr
);
2874 fprintf(stderr
, "\n");
2878 case nir_op_bitfield_select
: {
2879 /* (mask & insert) | (~mask & base) */
2880 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2881 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2882 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2884 /* dst = (insert & bitmask) | (base & ~bitmask) */
2885 if (dst
.regClass() == s1
) {
2886 aco_ptr
<Instruction
> sop2
;
2887 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2888 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2890 if (const_insert
&& const_bitmask
) {
2891 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2893 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2894 lhs
= Operand(insert
);
2898 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2899 if (const_base
&& const_bitmask
) {
2900 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2902 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2903 rhs
= Operand(base
);
2906 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2908 } else if (dst
.regClass() == v1
) {
2909 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2910 base
= as_vgpr(ctx
, base
);
2911 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2912 insert
= as_vgpr(ctx
, insert
);
2914 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2917 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2918 nir_print_instr(&instr
->instr
, stderr
);
2919 fprintf(stderr
, "\n");
2925 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2926 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2927 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2929 if (dst
.type() == RegType::sgpr
) {
2931 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2932 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2933 if (const_offset
&& const_bits
) {
2934 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2935 extract
= Operand(const_extract
);
2939 width
= Operand(const_bits
->u32
<< 16);
2941 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2943 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2947 if (dst
.regClass() == s1
) {
2948 if (instr
->op
== nir_op_ubfe
)
2949 opcode
= aco_opcode::s_bfe_u32
;
2951 opcode
= aco_opcode::s_bfe_i32
;
2952 } else if (dst
.regClass() == s2
) {
2953 if (instr
->op
== nir_op_ubfe
)
2954 opcode
= aco_opcode::s_bfe_u64
;
2956 opcode
= aco_opcode::s_bfe_i64
;
2958 unreachable("Unsupported BFE bit size");
2961 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2965 if (dst
.regClass() == v1
) {
2966 if (instr
->op
== nir_op_ubfe
)
2967 opcode
= aco_opcode::v_bfe_u32
;
2969 opcode
= aco_opcode::v_bfe_i32
;
2971 unreachable("Unsupported BFE bit size");
2974 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2978 case nir_op_bit_count
: {
2979 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2980 if (src
.regClass() == s1
) {
2981 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2982 } else if (src
.regClass() == v1
) {
2983 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2984 } else if (src
.regClass() == v2
) {
2985 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2986 emit_extract_vector(ctx
, src
, 1, v1
),
2987 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2988 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2989 } else if (src
.regClass() == s2
) {
2990 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2992 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2993 nir_print_instr(&instr
->instr
, stderr
);
2994 fprintf(stderr
, "\n");
2999 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
3003 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
3007 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
3011 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
3015 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
3019 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
3023 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3024 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
3026 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
3027 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
3031 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3032 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
3034 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
3035 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
3039 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
3043 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3048 case nir_op_fddx_fine
:
3049 case nir_op_fddy_fine
:
3050 case nir_op_fddx_coarse
:
3051 case nir_op_fddy_coarse
: {
3052 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3053 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3054 if (instr
->op
== nir_op_fddx_fine
) {
3055 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3056 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3057 } else if (instr
->op
== nir_op_fddy_fine
) {
3058 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3059 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3061 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3062 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3063 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3065 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3069 if (ctx
->program
->chip_class
>= GFX8
) {
3070 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3071 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3073 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3074 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3075 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3077 emit_wqm(ctx
, tmp
, dst
, true);
3081 fprintf(stderr
, "Unknown NIR ALU instr: ");
3082 nir_print_instr(&instr
->instr
, stderr
);
3083 fprintf(stderr
, "\n");
3087 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3089 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3091 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3092 // which get truncated the lsb if double and msb if int
3093 // for now, we only use s_mov_b64 with 64bit inline constants
3094 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3095 assert(dst
.type() == RegType::sgpr
);
3097 Builder
bld(ctx
->program
, ctx
->block
);
3099 if (instr
->def
.bit_size
== 1) {
3100 assert(dst
.regClass() == bld
.lm
);
3101 int val
= instr
->value
[0].b
? -1 : 0;
3102 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3103 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3104 } else if (instr
->def
.bit_size
== 8) {
3105 /* ensure that the value is correctly represented in the low byte of the register */
3106 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3107 } else if (instr
->def
.bit_size
== 16) {
3108 /* ensure that the value is correctly represented in the low half of the register */
3109 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3110 } else if (dst
.size() == 1) {
3111 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3113 assert(dst
.size() != 1);
3114 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3115 if (instr
->def
.bit_size
== 64)
3116 for (unsigned i
= 0; i
< dst
.size(); i
++)
3117 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3119 for (unsigned i
= 0; i
< dst
.size(); i
++)
3120 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3122 vec
->definitions
[0] = Definition(dst
);
3123 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3127 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3129 uint32_t new_mask
= 0;
3130 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3131 if (mask
& (1u << i
))
3132 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3136 Operand
load_lds_size_m0(isel_context
*ctx
)
3138 /* TODO: m0 does not need to be initialized on GFX9+ */
3139 Builder
bld(ctx
->program
, ctx
->block
);
3140 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3143 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3144 Temp address
, unsigned base_offset
, unsigned align
)
3146 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3148 Builder
bld(ctx
->program
, ctx
->block
);
3150 Operand m
= load_lds_size_m0(ctx
);
3152 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
3153 unsigned bytes_read
= 0;
3154 unsigned result_size
= 0;
3155 unsigned total_bytes
= num_components
* elem_size_bytes
;
3156 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
3157 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
3158 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
3160 while (bytes_read
< total_bytes
) {
3161 unsigned todo
= total_bytes
- bytes_read
;
3162 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
3163 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
3165 aco_opcode op
= aco_opcode::last_opcode
;
3167 if (todo
>= 16 && aligned16
&& large_ds_read
) {
3168 op
= aco_opcode::ds_read_b128
;
3170 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
3171 op
= aco_opcode::ds_read2_b64
;
3174 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
3175 op
= aco_opcode::ds_read_b96
;
3177 } else if (todo
>= 8 && aligned8
) {
3178 op
= aco_opcode::ds_read_b64
;
3180 } else if (todo
>= 8 && usable_read2
) {
3181 op
= aco_opcode::ds_read2_b32
;
3184 } else if (todo
>= 4) {
3185 op
= aco_opcode::ds_read_b32
;
3190 assert(todo
% elem_size_bytes
== 0);
3191 unsigned num_elements
= todo
/ elem_size_bytes
;
3192 unsigned offset
= base_offset
+ bytes_read
;
3193 unsigned max_offset
= read2
? 1019 : 65535;
3195 Temp address_offset
= address
;
3196 if (offset
> max_offset
) {
3197 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3198 offset
= bytes_read
;
3200 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3203 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3206 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3209 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3211 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3213 if (num_components
== 1) {
3214 assert(todo
== total_bytes
);
3215 if (dst
.type() == RegType::sgpr
)
3216 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3220 if (dst
.type() == RegType::sgpr
) {
3221 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3222 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3226 if (num_elements
== 1) {
3227 result
[result_size
++] = res
;
3229 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3230 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3231 split
->operands
[0] = Operand(res
);
3232 for (unsigned i
= 0; i
< num_elements
; i
++)
3233 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3234 ctx
->block
->instructions
.emplace_back(std::move(split
));
3240 assert(result_size
== num_components
&& result_size
> 1);
3241 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3242 for (unsigned i
= 0; i
< result_size
; i
++)
3243 vec
->operands
[i
] = Operand(result
[i
]);
3244 vec
->definitions
[0] = Definition(dst
);
3245 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3246 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3251 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3253 if (start
== 0 && size
== data
.size())
3254 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3256 unsigned size_hint
= 1;
3257 auto it
= ctx
->allocated_vec
.find(data
.id());
3258 if (it
!= ctx
->allocated_vec
.end())
3259 size_hint
= it
->second
[0].size();
3260 if (size
% size_hint
|| start
% size_hint
)
3267 for (unsigned i
= 0; i
< size
; i
++)
3268 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3271 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3273 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3274 for (unsigned i
= 0; i
< size
; i
++)
3275 vec
->operands
[i
] = Operand(elems
[i
]);
3276 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3277 vec
->definitions
[0] = Definition(res
);
3278 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3282 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3284 Builder
bld(ctx
->program
, ctx
->block
);
3285 unsigned bytes_written
= 0;
3286 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3287 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3289 while (bytes_written
< total_size
* 4) {
3290 unsigned todo
= total_size
* 4 - bytes_written
;
3291 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3292 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3294 aco_opcode op
= aco_opcode::last_opcode
;
3295 bool write2
= false;
3297 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3298 op
= aco_opcode::ds_write_b128
;
3300 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3301 op
= aco_opcode::ds_write2_b64
;
3304 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3305 op
= aco_opcode::ds_write_b96
;
3307 } else if (todo
>= 8 && aligned8
) {
3308 op
= aco_opcode::ds_write_b64
;
3310 } else if (todo
>= 8 && usable_write2
) {
3311 op
= aco_opcode::ds_write2_b32
;
3314 } else if (todo
>= 4) {
3315 op
= aco_opcode::ds_write_b32
;
3321 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3322 unsigned max_offset
= write2
? 1020 : 65535;
3323 Temp address_offset
= address
;
3324 if (offset
> max_offset
) {
3325 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3326 offset
= offset1
+ bytes_written
;
3328 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3331 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3332 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3333 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3335 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3336 bld
.ds(op
, address_offset
, val
, m
, offset
);
3339 bytes_written
+= size
* 4;
3343 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3344 Temp address
, unsigned base_offset
, unsigned align
)
3346 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3347 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3349 Operand m
= load_lds_size_m0(ctx
);
3351 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3352 assert(wrmask
<= 0x0f);
3353 int start
[2], count
[2];
3354 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3355 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3356 assert(wrmask
== 0);
3358 /* one combined store is sufficient */
3359 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3360 Builder
bld(ctx
->program
, ctx
->block
);
3362 Temp address_offset
= address
;
3363 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3364 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3368 assert(count
[0] == 1);
3369 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3371 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3372 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3373 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3374 base_offset
= base_offset
/ elem_size_bytes
;
3375 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3376 base_offset
+ start
[0], base_offset
+ start
[1]);
3380 for (unsigned i
= 0; i
< 2; i
++) {
3384 unsigned elem_size_words
= elem_size_bytes
/ 4;
3385 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3386 base_offset
, start
[i
] * elem_size_bytes
, align
);
3391 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3393 unsigned align
= 16;
3395 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3401 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3402 unsigned split_cnt
= 0u, Temp dst
= Temp())
3404 Builder
bld(ctx
->program
, ctx
->block
);
3405 unsigned dword_size
= elem_size_bytes
/ 4;
3408 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3410 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3411 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3412 instr
->definitions
[0] = Definition(dst
);
3414 for (unsigned i
= 0; i
< cnt
; ++i
) {
3416 assert(arr
[i
].size() == dword_size
);
3417 allocated_vec
[i
] = arr
[i
];
3418 instr
->operands
[i
] = Operand(arr
[i
]);
3420 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3421 allocated_vec
[i
] = zero
;
3422 instr
->operands
[i
] = Operand(zero
);
3426 bld
.insert(std::move(instr
));
3429 emit_split_vector(ctx
, dst
, split_cnt
);
3431 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3436 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3438 if (const_offset
>= 4096) {
3439 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3440 const_offset
%= 4096u;
3443 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3444 else if (unlikely(voffset
.regClass() == s1
))
3445 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3446 else if (likely(voffset
.regClass() == v1
))
3447 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3449 unreachable("Unsupported register class of voffset");
3452 return const_offset
;
3455 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3456 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3459 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3460 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3462 Builder
bld(ctx
->program
, ctx
->block
);
3463 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3464 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3466 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3467 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3468 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3469 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3470 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3472 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3475 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3476 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3477 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3479 Builder
bld(ctx
->program
, ctx
->block
);
3480 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3483 if (elem_size_bytes
== 8) {
3484 elem_size_bytes
= 4;
3485 write_mask
= widen_mask(write_mask
, 2);
3488 while (write_mask
) {
3491 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3496 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3497 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3499 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3500 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3503 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3504 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3514 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3515 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3517 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3518 assert(size_dwords
>= 1 && size_dwords
<= 4);
3520 Builder
bld(ctx
->program
, ctx
->block
);
3521 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3522 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3523 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3525 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3526 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3527 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3528 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3529 /* disable_wqm */ false, /* glc */ true,
3530 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3532 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3537 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3538 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3539 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3541 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3542 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3543 assert(!!stride
!= allow_combining
);
3545 Builder
bld(ctx
->program
, ctx
->block
);
3546 unsigned split_cnt
= num_components
;
3548 if (elem_size_bytes
== 8) {
3549 elem_size_bytes
= 4;
3550 num_components
*= 2;
3554 stride
= elem_size_bytes
;
3556 unsigned load_size
= 1;
3557 if (allow_combining
) {
3558 if ((num_components
% 4) == 0)
3560 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3562 else if ((num_components
% 2) == 0)
3566 unsigned num_loads
= num_components
/ load_size
;
3567 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3569 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3570 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3571 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3574 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3577 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3579 Builder
bld(ctx
->program
, ctx
->block
);
3580 Temp offset
= base_offset
.first
;
3581 unsigned const_offset
= base_offset
.second
;
3583 if (!nir_src_is_const(*off_src
)) {
3584 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3587 /* Calculate indirect offset with stride */
3588 if (likely(indirect_offset_arg
.regClass() == v1
))
3589 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3590 else if (indirect_offset_arg
.regClass() == s1
)
3591 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3593 unreachable("Unsupported register class of indirect offset");
3595 /* Add to the supplied base offset */
3596 if (offset
.id() == 0)
3597 offset
= with_stride
;
3598 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3599 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3600 else if (offset
.size() == 1 && with_stride
.size() == 1)
3601 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3603 unreachable("Unsupported register class of indirect offset");
3605 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3606 const_offset
+= const_offset_arg
* stride
;
3609 return std::make_pair(offset
, const_offset
);
3612 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3614 Builder
bld(ctx
->program
, ctx
->block
);
3617 if (off1
.first
.id() && off2
.first
.id()) {
3618 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3619 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3620 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3621 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3623 unreachable("Unsupported register class of indirect offset");
3625 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3628 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3631 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3633 Builder
bld(ctx
->program
, ctx
->block
);
3634 unsigned const_offset
= offs
.second
* multiplier
;
3636 if (!offs
.first
.id())
3637 return std::make_pair(offs
.first
, const_offset
);
3639 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3640 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3641 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3643 return std::make_pair(offset
, const_offset
);
3646 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3648 Builder
bld(ctx
->program
, ctx
->block
);
3650 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3651 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3652 /* component is in bytes */
3653 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3655 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3656 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3657 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3660 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3662 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3665 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3667 Builder
bld(ctx
->program
, ctx
->block
);
3669 switch (ctx
->shader
->info
.stage
) {
3670 case MESA_SHADER_TESS_CTRL
:
3671 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3672 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3673 case MESA_SHADER_TESS_EVAL
:
3674 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3676 unreachable("Unsupported stage in get_tess_rel_patch_id");
3680 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3682 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3683 Builder
bld(ctx
->program
, ctx
->block
);
3685 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3686 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3688 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3690 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3691 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3693 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3694 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3695 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3697 return offset_mul(ctx
, offs
, 4u);
3700 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3702 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3703 Builder
bld(ctx
->program
, ctx
->block
);
3705 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3706 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3707 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3708 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3709 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3710 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3712 std::pair
<Temp
, unsigned> offs
= instr
3713 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3714 : std::make_pair(Temp(), 0u);
3716 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3717 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3722 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3723 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3725 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3726 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3728 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3729 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3735 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3737 Builder
bld(ctx
->program
, ctx
->block
);
3739 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3740 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3742 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3744 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3745 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3746 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3748 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3749 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3754 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3756 Builder
bld(ctx
->program
, ctx
->block
);
3758 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3759 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3760 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3762 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3763 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3764 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3765 unsigned attr_stride
= ctx
->tcs_num_patches
;
3767 std::pair
<Temp
, unsigned> offs
= instr
3768 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3769 : std::make_pair(Temp(), 0u);
3771 if (const_base_offset
)
3772 offs
.second
+= const_base_offset
* attr_stride
;
3774 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3775 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3776 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3781 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3783 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3784 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3786 if (!nir_src_is_const(*off_src
)) {
3792 off
+= nir_src_as_uint(*off_src
) * 16u;
3795 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3796 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3803 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3805 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3806 unsigned component
= nir_intrinsic_component(instr
);
3807 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3809 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3810 if (off_instr
->type
!= nir_instr_type_load_const
)
3813 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3814 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3816 if (instr
->src
[0].ssa
->bit_size
== 64)
3817 write_mask
= widen_mask(write_mask
, 2);
3819 for (unsigned i
= 0; i
< 8; ++i
) {
3820 if (write_mask
& (1 << i
)) {
3821 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3822 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3830 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3832 /* Only TCS per-vertex inputs are supported by this function.
3833 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3835 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3838 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3839 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3840 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3841 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3842 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3843 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3848 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3849 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3850 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3851 assert(vec
.size() == dst
.size());
3853 Builder
bld(ctx
->program
, ctx
->block
);
3854 bld
.copy(Definition(dst
), vec
);
3858 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3860 Builder
bld(ctx
->program
, ctx
->block
);
3862 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3863 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3864 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3865 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3867 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3868 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3869 bool indirect_write
;
3870 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3871 if (temp_only_input
&& !indirect_write
)
3875 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3876 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3877 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3878 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3879 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3883 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3884 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3885 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3886 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3887 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3888 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3889 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3890 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3891 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3892 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3893 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3894 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3895 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3897 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3898 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3899 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3901 unreachable("Invalid LS or ES stage");
3904 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3905 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3906 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3910 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3912 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3913 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3914 off
!= ctx
->tcs_tess_lvl_in_loc
;
3917 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3919 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3920 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3923 uint64_t mask
= per_vertex
3924 ? ctx
->shader
->info
.outputs_read
3925 : ctx
->shader
->info
.patch_outputs_read
;
3926 bool indirect_write
;
3927 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3928 return indirect_write
|| output_read
;
3931 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3933 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3934 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3936 Builder
bld(ctx
->program
, ctx
->block
);
3938 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3939 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3940 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3942 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3943 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3944 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3945 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3947 if (write_to_vmem
) {
3948 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3949 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3950 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3952 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3953 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3954 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3958 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3959 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3960 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3964 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3966 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3967 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3969 Builder
bld(ctx
->program
, ctx
->block
);
3971 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3972 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3973 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3974 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3976 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3979 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3981 if (ctx
->stage
== vertex_vs
||
3982 ctx
->stage
== tess_eval_vs
||
3983 ctx
->stage
== fragment_fs
||
3984 ctx
->stage
== ngg_vertex_gs
||
3985 ctx
->stage
== ngg_tess_eval_gs
||
3986 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3987 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3988 if (!stored_to_temps
) {
3989 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3990 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3991 fprintf(stderr
, "\n");
3994 } else if (ctx
->stage
== vertex_es
||
3995 ctx
->stage
== vertex_ls
||
3996 ctx
->stage
== tess_eval_es
||
3997 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3998 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3999 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4000 visit_store_ls_or_es_output(ctx
, instr
);
4001 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4002 visit_store_tcs_output(ctx
, instr
, false);
4004 unreachable("Shader stage not implemented");
4008 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4010 visit_load_tcs_output(ctx
, instr
, false);
4013 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4015 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4016 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4018 Builder
bld(ctx
->program
, ctx
->block
);
4019 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
4020 if (ctx
->program
->has_16bank_lds
)
4021 interp_p1
.instr
->operands
[0].setLateKill(true);
4022 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4025 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4027 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4028 for (unsigned i
= 0; i
< num_components
; i
++)
4029 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4030 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4031 assert(num_components
== 4);
4032 Builder
bld(ctx
->program
, ctx
->block
);
4033 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4036 for (Operand
& op
: vec
->operands
)
4037 op
= op
.isUndefined() ? Operand(0u) : op
;
4039 vec
->definitions
[0] = Definition(dst
);
4040 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4041 emit_split_vector(ctx
, dst
, num_components
);
4045 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4047 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4048 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4049 unsigned idx
= nir_intrinsic_base(instr
);
4050 unsigned component
= nir_intrinsic_component(instr
);
4051 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4053 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4055 assert(offset
->u32
== 0);
4057 /* the lower 15bit of the prim_mask contain the offset into LDS
4058 * while the upper bits contain the number of prims */
4059 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4060 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4061 Builder
bld(ctx
->program
, ctx
->block
);
4062 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4063 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4064 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4065 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4066 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4069 if (instr
->dest
.ssa
.num_components
== 1) {
4070 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4072 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4073 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4075 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4076 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4077 vec
->operands
[i
] = Operand(tmp
);
4079 vec
->definitions
[0] = Definition(dst
);
4080 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4084 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4085 unsigned offset
, unsigned stride
, unsigned channels
)
4087 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4088 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4090 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4091 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4094 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4095 unsigned offset
, unsigned stride
, unsigned *channels
)
4097 if (!vtx_info
->chan_byte_size
) {
4098 *channels
= vtx_info
->num_channels
;
4099 return vtx_info
->chan_format
;
4102 unsigned num_channels
= *channels
;
4103 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4104 unsigned new_channels
= num_channels
+ 1;
4105 /* first, assume more loads is worse and try using a larger data format */
4106 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4108 /* don't make the attribute potentially out-of-bounds */
4109 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4113 if (new_channels
== 5) {
4114 /* then try decreasing load size (at the cost of more loads) */
4115 new_channels
= *channels
;
4116 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4120 if (new_channels
< *channels
)
4121 *channels
= new_channels
;
4122 num_channels
= new_channels
;
4125 switch (vtx_info
->chan_format
) {
4126 case V_008F0C_BUF_DATA_FORMAT_8
:
4127 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4128 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4129 case V_008F0C_BUF_DATA_FORMAT_16
:
4130 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4131 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4132 case V_008F0C_BUF_DATA_FORMAT_32
:
4133 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4134 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4136 unreachable("shouldn't reach here");
4137 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4140 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4141 * so we may need to fix it up. */
4142 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4144 Builder
bld(ctx
->program
, ctx
->block
);
4146 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4147 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4149 /* For the integer-like cases, do a natural sign extension.
4151 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4152 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4155 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4156 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4158 /* Convert back to the right type. */
4159 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4160 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4161 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4162 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4163 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4164 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4170 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4172 Builder
bld(ctx
->program
, ctx
->block
);
4173 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4174 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4176 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4177 if (off_instr
->type
!= nir_instr_type_load_const
) {
4178 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4179 nir_print_instr(off_instr
, stderr
);
4180 fprintf(stderr
, "\n");
4182 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4184 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4186 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4187 unsigned component
= nir_intrinsic_component(instr
);
4188 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4189 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4190 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4191 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4193 unsigned dfmt
= attrib_format
& 0xf;
4194 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4195 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4197 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4198 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4199 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4200 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4202 num_channels
= MAX2(num_channels
, 3);
4204 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4205 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4208 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4209 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4210 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4212 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4214 Temp divided
= bld
.tmp(v1
);
4215 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4216 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4218 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4221 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4224 index
= bld
.vadd32(bld
.def(v1
),
4225 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4226 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4229 Temp channels
[num_channels
];
4230 unsigned channel_start
= 0;
4231 bool direct_fetch
= false;
4233 /* skip unused channels at the start */
4234 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4235 channel_start
= ffs(mask
) - 1;
4236 for (unsigned i
= 0; i
< channel_start
; i
++)
4237 channels
[i
] = Temp(0, s1
);
4238 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4239 num_channels
= 3 - (ffs(mask
) - 1);
4243 while (channel_start
< num_channels
) {
4244 unsigned fetch_size
= num_channels
- channel_start
;
4245 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4246 bool expanded
= false;
4248 /* use MUBUF when possible to avoid possible alignment issues */
4249 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4250 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4251 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4252 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4253 vtx_info
->chan_byte_size
== 4;
4254 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4256 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4258 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4259 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4265 Temp fetch_index
= index
;
4266 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4267 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4268 fetch_offset
= fetch_offset
% attrib_stride
;
4271 Operand
soffset(0u);
4272 if (fetch_offset
>= 4096) {
4273 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4274 fetch_offset
%= 4096;
4278 switch (fetch_size
) {
4280 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4283 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4286 assert(ctx
->options
->chip_class
>= GFX7
||
4287 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4288 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4291 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4294 unreachable("Unimplemented load_input vector size");
4298 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4299 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4300 num_channels
<= 3)) {
4301 direct_fetch
= true;
4304 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4308 Instruction
*mubuf
= bld
.mubuf(opcode
,
4309 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4310 fetch_offset
, false, true).instr
;
4311 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4313 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4314 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4315 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4316 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4319 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4321 if (fetch_size
== 1) {
4322 channels
[channel_start
] = fetch_dst
;
4324 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4325 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4328 channel_start
+= fetch_size
;
4331 if (!direct_fetch
) {
4332 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4333 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4335 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4336 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4337 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4339 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4340 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4341 unsigned num_temp
= 0;
4342 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4343 unsigned idx
= i
+ component
;
4344 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4345 Temp channel
= channels
[swizzle
[idx
]];
4346 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4347 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4348 vec
->operands
[i
] = Operand(channel
);
4352 } else if (is_float
&& idx
== 3) {
4353 vec
->operands
[i
] = Operand(0x3f800000u
);
4354 } else if (!is_float
&& idx
== 3) {
4355 vec
->operands
[i
] = Operand(1u);
4357 vec
->operands
[i
] = Operand(0u);
4360 vec
->definitions
[0] = Definition(dst
);
4361 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4362 emit_split_vector(ctx
, dst
, dst
.size());
4364 if (num_temp
== dst
.size())
4365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4367 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4368 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4369 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4370 if (off_instr
->type
!= nir_instr_type_load_const
||
4371 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4372 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4373 nir_print_instr(off_instr
, stderr
);
4374 fprintf(stderr
, "\n");
4377 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4378 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4380 assert(offset
->u32
== 0);
4382 /* the lower 15bit of the prim_mask contain the offset into LDS
4383 * while the upper bits contain the number of prims */
4384 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4385 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4386 Builder
bld(ctx
->program
, ctx
->block
);
4387 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4388 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4389 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4390 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4391 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4394 unsigned idx
= nir_intrinsic_base(instr
);
4395 unsigned component
= nir_intrinsic_component(instr
);
4396 unsigned vertex_id
= 2; /* P0 */
4398 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4399 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4400 switch (src0
->u32
) {
4402 vertex_id
= 2; /* P0 */
4405 vertex_id
= 0; /* P10 */
4408 vertex_id
= 1; /* P20 */
4411 unreachable("invalid vertex index");
4415 if (dst
.size() == 1) {
4416 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4418 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4419 for (unsigned i
= 0; i
< dst
.size(); i
++)
4420 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4421 vec
->definitions
[0] = Definition(dst
);
4422 bld
.insert(std::move(vec
));
4425 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4426 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4427 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4428 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4429 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4431 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4433 unreachable("Shader stage not implemented");
4437 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4439 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4441 Builder
bld(ctx
->program
, ctx
->block
);
4442 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4445 if (!nir_src_is_const(*vertex_src
)) {
4446 /* better code could be created, but this case probably doesn't happen
4447 * much in practice */
4448 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4449 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4452 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4453 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4455 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4457 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4460 if (vertex_offset
.id()) {
4461 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4462 Operand(i
), indirect_vertex
);
4463 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4465 vertex_offset
= elem
;
4469 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4470 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4472 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4473 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4474 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4475 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4476 Operand((vertex
% 2u) * 16u), Operand(16u));
4478 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4481 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4482 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4483 return offset_mul(ctx
, offs
, 4u);
4486 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4488 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4490 Builder
bld(ctx
->program
, ctx
->block
);
4491 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4492 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4494 if (ctx
->stage
== geometry_gs
) {
4495 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4496 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4497 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4498 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4499 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4500 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4501 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4503 unreachable("Unsupported GS stage.");
4507 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4509 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4511 Builder
bld(ctx
->program
, ctx
->block
);
4512 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4514 if (load_input_from_temps(ctx
, instr
, dst
))
4517 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4518 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4519 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4521 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4524 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4526 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4528 Builder
bld(ctx
->program
, ctx
->block
);
4530 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4531 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4532 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4534 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4535 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4537 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4540 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4542 switch (ctx
->shader
->info
.stage
) {
4543 case MESA_SHADER_GEOMETRY
:
4544 visit_load_gs_per_vertex_input(ctx
, instr
);
4546 case MESA_SHADER_TESS_CTRL
:
4547 visit_load_tcs_per_vertex_input(ctx
, instr
);
4549 case MESA_SHADER_TESS_EVAL
:
4550 visit_load_tes_per_vertex_input(ctx
, instr
);
4553 unreachable("Unimplemented shader stage");
4557 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4559 visit_load_tcs_output(ctx
, instr
, true);
4562 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4564 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4565 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4567 visit_store_tcs_output(ctx
, instr
, true);
4570 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4572 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4574 Builder
bld(ctx
->program
, ctx
->block
);
4575 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4577 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4578 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4581 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4582 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4583 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4584 tes_w
= Operand(tmp
);
4587 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4588 emit_split_vector(ctx
, tess_coord
, 3);
4591 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4593 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4594 Builder
bld(ctx
->program
, ctx
->block
);
4595 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4596 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4597 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4600 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4604 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4606 Builder
bld(ctx
->program
, ctx
->block
);
4607 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4608 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4609 index
= bld
.as_uniform(index
);
4610 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4611 unsigned binding
= nir_intrinsic_binding(instr
);
4614 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4615 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4616 unsigned offset
= layout
->binding
[binding
].offset
;
4618 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4619 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4620 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4621 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4622 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4625 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4626 stride
= layout
->binding
[binding
].size
;
4629 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4630 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4632 if (nir_const_index
) {
4633 const_index
= const_index
* stride
;
4634 } else if (index
.type() == RegType::vgpr
) {
4635 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4636 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4638 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4642 if (nir_const_index
) {
4643 const_index
= const_index
+ offset
;
4644 } else if (index
.type() == RegType::vgpr
) {
4645 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4647 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4651 if (nir_const_index
&& const_index
== 0) {
4653 } else if (index
.type() == RegType::vgpr
) {
4654 index
= bld
.vadd32(bld
.def(v1
),
4655 nir_const_index
? Operand(const_index
) : Operand(index
),
4658 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4659 nir_const_index
? Operand(const_index
) : Operand(index
),
4663 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4666 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4667 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4668 bool glc
=false, bool readonly
=true)
4670 Builder
bld(ctx
->program
, ctx
->block
);
4671 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4672 unsigned num_bytes
= num_components
* component_size
;
4675 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4676 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4677 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4678 unsigned const_offset
= 0;
4680 /* for small bit sizes add buffer for unaligned loads */
4683 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4688 Temp lower
= Temp();
4689 if (num_bytes
> 16) {
4690 assert(num_components
== 3 || num_components
== 4);
4691 op
= aco_opcode::buffer_load_dwordx4
;
4692 lower
= bld
.tmp(v4
);
4693 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4694 mubuf
->definitions
[0] = Definition(lower
);
4695 mubuf
->operands
[0] = Operand(rsrc
);
4696 mubuf
->operands
[1] = vaddr
;
4697 mubuf
->operands
[2] = soffset
;
4698 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4701 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4702 mubuf
->can_reorder
= readonly
;
4703 bld
.insert(std::move(mubuf
));
4704 emit_split_vector(ctx
, lower
, 2);
4707 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4708 /* GFX6 doesn't support loading vec3, expand to vec4. */
4712 switch (num_bytes
) {
4714 op
= aco_opcode::buffer_load_ubyte
;
4717 op
= aco_opcode::buffer_load_ushort
;
4721 op
= aco_opcode::buffer_load_dword
;
4727 op
= aco_opcode::buffer_load_dwordx2
;
4731 assert(ctx
->options
->chip_class
> GFX6
);
4732 op
= aco_opcode::buffer_load_dwordx3
;
4735 op
= aco_opcode::buffer_load_dwordx4
;
4738 unreachable("Load SSBO not implemented for this size.");
4740 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4741 mubuf
->operands
[0] = Operand(rsrc
);
4742 mubuf
->operands
[1] = vaddr
;
4743 mubuf
->operands
[2] = soffset
;
4744 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4747 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4748 mubuf
->can_reorder
= readonly
;
4749 mubuf
->offset
= const_offset
;
4750 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4752 if (component_size
< 4) {
4753 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4754 instr
->definitions
[0] = Definition(vec
);
4755 bld
.insert(std::move(instr
));
4757 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4758 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4759 Temp tmp
[3] = {vec
, vec
, vec
};
4761 if (vec
.size() == 3) {
4762 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4763 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4764 } else if (vec
.size() == 2) {
4765 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4766 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4768 for (unsigned i
= 0; i
< dst
.size(); i
++)
4769 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4772 if (dst
.size() == 2)
4773 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4778 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4779 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4781 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4786 } else if (dst
.size() > 4) {
4787 assert(lower
!= Temp());
4788 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4789 instr
->definitions
[0] = Definition(upper
);
4790 bld
.insert(std::move(instr
));
4791 if (dst
.size() == 8)
4792 emit_split_vector(ctx
, upper
, 2);
4793 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4794 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4795 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4796 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4797 if (dst
.size() == 8)
4798 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4799 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4800 Temp vec
= bld
.tmp(v4
);
4801 instr
->definitions
[0] = Definition(vec
);
4802 bld
.insert(std::move(instr
));
4803 emit_split_vector(ctx
, vec
, 4);
4805 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4806 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4807 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4808 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4811 if (dst
.type() == RegType::sgpr
) {
4812 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4813 instr
->definitions
[0] = Definition(vec
);
4814 bld
.insert(std::move(instr
));
4815 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4817 instr
->definitions
[0] = Definition(dst
);
4818 bld
.insert(std::move(instr
));
4819 emit_split_vector(ctx
, dst
, num_components
);
4822 /* for small bit sizes add buffer for unaligned loads */
4824 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4826 switch (num_bytes
) {
4831 op
= aco_opcode::s_buffer_load_dword
;
4837 op
= aco_opcode::s_buffer_load_dwordx2
;
4842 op
= aco_opcode::s_buffer_load_dwordx4
;
4846 op
= aco_opcode::s_buffer_load_dwordx8
;
4849 unreachable("Load SSBO not implemented for this size.");
4851 offset
= bld
.as_uniform(offset
);
4852 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4853 load
->operands
[0] = Operand(rsrc
);
4854 load
->operands
[1] = Operand(offset
);
4855 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4856 load
->definitions
[0] = Definition(dst
);
4859 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4860 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4861 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4863 /* adjust misaligned small bit size loads */
4865 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
4866 load
->definitions
[0] = Definition(vec
);
4867 bld
.insert(std::move(load
));
4868 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
4869 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4872 } else if (dst
.size() == 3) {
4873 Temp vec
= bld
.tmp(s4
);
4874 load
->definitions
[0] = Definition(vec
);
4875 bld
.insert(std::move(load
));
4876 emit_split_vector(ctx
, vec
, 4);
4878 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4879 emit_extract_vector(ctx
, vec
, 0, s1
),
4880 emit_extract_vector(ctx
, vec
, 1, s1
),
4881 emit_extract_vector(ctx
, vec
, 2, s1
));
4882 } else if (dst
.size() == 6) {
4883 Temp vec
= bld
.tmp(s8
);
4884 load
->definitions
[0] = Definition(vec
);
4885 bld
.insert(std::move(load
));
4886 emit_split_vector(ctx
, vec
, 4);
4888 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4889 emit_extract_vector(ctx
, vec
, 0, s2
),
4890 emit_extract_vector(ctx
, vec
, 1, s2
),
4891 emit_extract_vector(ctx
, vec
, 2, s2
));
4893 bld
.insert(std::move(load
));
4895 emit_split_vector(ctx
, dst
, num_components
);
4899 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4901 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4902 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4904 Builder
bld(ctx
->program
, ctx
->block
);
4906 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4907 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4908 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4909 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4911 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4912 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4913 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4914 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4915 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4916 if (ctx
->options
->chip_class
>= GFX10
) {
4917 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4918 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4919 S_008F0C_RESOURCE_LEVEL(1);
4921 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4922 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4924 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4925 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4926 Operand(0xFFFFFFFFu
),
4927 Operand(desc_type
));
4928 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4929 rsrc
, upper_dwords
);
4931 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4932 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4934 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4937 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
4938 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
4939 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
4941 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
4944 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4946 Builder
bld(ctx
->program
, ctx
->block
);
4947 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4948 unsigned offset
= nir_intrinsic_base(instr
);
4949 unsigned count
= instr
->dest
.ssa
.num_components
;
4950 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4952 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4953 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4954 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4955 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4956 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4957 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4958 for (unsigned i
= 0; i
< count
; ++i
) {
4959 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4960 vec
->operands
[i
] = Operand
{elems
[i
]};
4962 vec
->definitions
[0] = Definition(dst
);
4963 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4964 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4969 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4970 if (offset
!= 0) // TODO check if index != 0 as well
4971 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4972 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4975 bool aligned
= true;
4977 if (instr
->dest
.ssa
.bit_size
== 8) {
4978 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4979 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4981 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4982 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4983 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4985 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4990 switch (vec
.size()) {
4992 op
= aco_opcode::s_load_dword
;
4995 op
= aco_opcode::s_load_dwordx2
;
5001 op
= aco_opcode::s_load_dwordx4
;
5007 op
= aco_opcode::s_load_dwordx8
;
5010 unreachable("unimplemented or forbidden load_push_constant.");
5013 bld
.smem(op
, Definition(vec
), ptr
, index
);
5016 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5017 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5022 emit_split_vector(ctx
, vec
, 4);
5023 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5024 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5025 emit_extract_vector(ctx
, vec
, 0, rc
),
5026 emit_extract_vector(ctx
, vec
, 1, rc
),
5027 emit_extract_vector(ctx
, vec
, 2, rc
));
5030 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5033 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5035 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5037 Builder
bld(ctx
->program
, ctx
->block
);
5039 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5040 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5041 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5042 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5043 if (ctx
->options
->chip_class
>= GFX10
) {
5044 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5045 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5046 S_008F0C_RESOURCE_LEVEL(1);
5048 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5049 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5052 unsigned base
= nir_intrinsic_base(instr
);
5053 unsigned range
= nir_intrinsic_range(instr
);
5055 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5056 if (base
&& offset
.type() == RegType::sgpr
)
5057 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5058 else if (base
&& offset
.type() == RegType::vgpr
)
5059 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5061 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5062 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5063 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5064 Operand(desc_type
));
5065 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5066 // TODO: get alignment information for subdword constants
5067 unsigned byte_align
= size
< 4 ? -1 : 0;
5068 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
5071 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5073 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5074 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5076 ctx
->program
->needs_exact
= true;
5078 // TODO: optimize uniform conditions
5079 Builder
bld(ctx
->program
, ctx
->block
);
5080 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5081 assert(src
.regClass() == bld
.lm
);
5082 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5083 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5084 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5088 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5090 Builder
bld(ctx
->program
, ctx
->block
);
5092 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5093 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5095 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5096 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5098 if (ctx
->block
->loop_nest_depth
&&
5099 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5100 /* we handle discards the same way as jump instructions */
5101 append_logical_end(ctx
->block
);
5103 /* in loops, discard behaves like break */
5104 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5105 ctx
->block
->kind
|= block_kind_discard
;
5108 /* uniform discard - loop ends here */
5109 assert(nir_instr_is_last(&instr
->instr
));
5110 ctx
->block
->kind
|= block_kind_uniform
;
5111 ctx
->cf_info
.has_branch
= true;
5112 bld
.branch(aco_opcode::p_branch
);
5113 add_linear_edge(ctx
->block
->index
, linear_target
);
5117 /* we add a break right behind the discard() instructions */
5118 ctx
->block
->kind
|= block_kind_break
;
5119 unsigned idx
= ctx
->block
->index
;
5121 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5122 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5124 /* remove critical edges from linear CFG */
5125 bld
.branch(aco_opcode::p_branch
);
5126 Block
* break_block
= ctx
->program
->create_and_insert_block();
5127 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5128 break_block
->kind
|= block_kind_uniform
;
5129 add_linear_edge(idx
, break_block
);
5130 add_linear_edge(break_block
->index
, linear_target
);
5131 bld
.reset(break_block
);
5132 bld
.branch(aco_opcode::p_branch
);
5134 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5135 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5136 add_linear_edge(idx
, continue_block
);
5137 append_logical_start(continue_block
);
5138 ctx
->block
= continue_block
;
5143 /* it can currently happen that NIR doesn't remove the unreachable code */
5144 if (!nir_instr_is_last(&instr
->instr
)) {
5145 ctx
->program
->needs_exact
= true;
5146 /* save exec somewhere temporarily so that it doesn't get
5147 * overwritten before the discard from outer exec masks */
5148 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5149 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5150 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5154 /* This condition is incorrect for uniformly branched discards in a loop
5155 * predicated by a divergent condition, but the above code catches that case
5156 * and the discard would end up turning into a discard_if.
5166 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5167 /* program just ends here */
5168 ctx
->block
->kind
|= block_kind_uniform
;
5169 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5170 0 /* enabled mask */, 9 /* dest */,
5171 false /* compressed */, true/* done */, true /* valid mask */);
5172 bld
.sopp(aco_opcode::s_endpgm
);
5173 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5175 ctx
->block
->kind
|= block_kind_discard
;
5176 /* branch and linear edge is added by visit_if() */
5180 enum aco_descriptor_type
{
5191 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5192 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5194 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5195 return dim
== ac_image_cube
||
5196 dim
== ac_image_1darray
||
5197 dim
== ac_image_2darray
||
5198 dim
== ac_image_2darraymsaa
;
5201 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5202 enum aco_descriptor_type desc_type
,
5203 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5205 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5206 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5207 if (it != ctx->tex_desc.end())
5210 Temp index
= Temp();
5211 bool index_set
= false;
5212 unsigned constant_index
= 0;
5213 unsigned descriptor_set
;
5214 unsigned base_index
;
5215 Builder
bld(ctx
->program
, ctx
->block
);
5218 assert(tex_instr
&& !image
);
5220 base_index
= tex_instr
->sampler_index
;
5222 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5223 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5227 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5228 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5230 constant_index
+= array_size
* const_value
->u32
;
5232 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5233 if (indirect
.type() == RegType::vgpr
)
5234 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5236 if (array_size
!= 1)
5237 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5243 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5247 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5249 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5250 base_index
= deref_instr
->var
->data
.binding
;
5253 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5254 list
= convert_pointer_to_64_bit(ctx
, list
);
5256 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5257 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5258 unsigned offset
= binding
->offset
;
5259 unsigned stride
= binding
->size
;
5263 assert(base_index
< layout
->binding_count
);
5265 switch (desc_type
) {
5266 case ACO_DESC_IMAGE
:
5268 opcode
= aco_opcode::s_load_dwordx8
;
5270 case ACO_DESC_FMASK
:
5272 opcode
= aco_opcode::s_load_dwordx8
;
5275 case ACO_DESC_SAMPLER
:
5277 opcode
= aco_opcode::s_load_dwordx4
;
5278 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5279 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5281 case ACO_DESC_BUFFER
:
5283 opcode
= aco_opcode::s_load_dwordx4
;
5285 case ACO_DESC_PLANE_0
:
5286 case ACO_DESC_PLANE_1
:
5288 opcode
= aco_opcode::s_load_dwordx8
;
5289 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5291 case ACO_DESC_PLANE_2
:
5293 opcode
= aco_opcode::s_load_dwordx4
;
5297 unreachable("invalid desc_type\n");
5300 offset
+= constant_index
* stride
;
5302 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5303 (!index_set
|| binding
->immutable_samplers_equal
)) {
5304 if (binding
->immutable_samplers_equal
)
5307 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5308 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5309 Operand(samplers
[constant_index
* 4 + 0]),
5310 Operand(samplers
[constant_index
* 4 + 1]),
5311 Operand(samplers
[constant_index
* 4 + 2]),
5312 Operand(samplers
[constant_index
* 4 + 3]));
5317 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5319 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5320 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5323 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5325 if (desc_type
== ACO_DESC_PLANE_2
) {
5327 for (unsigned i
= 0; i
< 8; i
++)
5328 components
[i
] = bld
.tmp(s1
);
5329 bld
.pseudo(aco_opcode::p_split_vector
,
5330 Definition(components
[0]),
5331 Definition(components
[1]),
5332 Definition(components
[2]),
5333 Definition(components
[3]),
5336 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5337 bld
.pseudo(aco_opcode::p_split_vector
,
5338 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5339 Definition(components
[4]),
5340 Definition(components
[5]),
5341 Definition(components
[6]),
5342 Definition(components
[7]),
5345 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5346 components
[0], components
[1], components
[2], components
[3],
5347 components
[4], components
[5], components
[6], components
[7]);
5353 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5356 case GLSL_SAMPLER_DIM_BUF
:
5358 case GLSL_SAMPLER_DIM_1D
:
5359 return array
? 2 : 1;
5360 case GLSL_SAMPLER_DIM_2D
:
5361 return array
? 3 : 2;
5362 case GLSL_SAMPLER_DIM_MS
:
5363 return array
? 4 : 3;
5364 case GLSL_SAMPLER_DIM_3D
:
5365 case GLSL_SAMPLER_DIM_CUBE
:
5367 case GLSL_SAMPLER_DIM_RECT
:
5368 case GLSL_SAMPLER_DIM_SUBPASS
:
5370 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5379 /* Adjust the sample index according to FMASK.
5381 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5382 * which is the identity mapping. Each nibble says which physical sample
5383 * should be fetched to get that sample.
5385 * For example, 0x11111100 means there are only 2 samples stored and
5386 * the second sample covers 3/4 of the pixel. When reading samples 0
5387 * and 1, return physical sample 0 (determined by the first two 0s
5388 * in FMASK), otherwise return physical sample 1.
5390 * The sample index should be adjusted as follows:
5391 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5393 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5395 Builder
bld(ctx
->program
, ctx
->block
);
5396 Temp fmask
= bld
.tmp(v1
);
5397 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5398 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5401 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5402 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5403 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5404 load
->operands
[0] = Operand(fmask_desc_ptr
);
5405 load
->operands
[1] = Operand(s4
); /* no sampler */
5406 load
->operands
[2] = Operand(coord
);
5407 load
->definitions
[0] = Definition(fmask
);
5414 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5415 ctx
->block
->instructions
.emplace_back(std::move(load
));
5417 Operand sample_index4
;
5418 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5419 sample_index4
= Operand(sample_index
.constantValue() << 2);
5420 } else if (sample_index
.regClass() == s1
) {
5421 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5423 assert(sample_index
.regClass() == v1
);
5424 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5428 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5429 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5430 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5431 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5433 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5435 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5436 * resource descriptor is 0 (invalid),
5438 Temp compare
= bld
.tmp(bld
.lm
);
5439 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5440 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5442 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5444 /* Replace the MSAA sample index. */
5445 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5448 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5451 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5452 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5453 bool is_array
= glsl_sampler_type_is_array(type
);
5454 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5455 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5456 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5457 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5458 int count
= image_type_to_components_count(dim
, is_array
);
5459 std::vector
<Temp
> coords(count
);
5460 Builder
bld(ctx
->program
, ctx
->block
);
5464 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5465 /* get sample index */
5466 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5467 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5468 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5469 std::vector
<Temp
> fmask_load_address
;
5470 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5471 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5473 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5474 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5476 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5481 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5482 coords
.resize(coords
.size() + 1);
5483 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5485 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5487 for (int i
= 0; i
< count
; i
++)
5488 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5491 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5492 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5493 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5494 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5497 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5500 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5501 for (unsigned i
= 0; i
< coords
.size(); i
++)
5502 vec
->operands
[i
] = Operand(coords
[i
]);
5503 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5504 vec
->definitions
[0] = Definition(res
);
5505 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5510 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5512 Builder
bld(ctx
->program
, ctx
->block
);
5513 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5514 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5515 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5516 bool is_array
= glsl_sampler_type_is_array(type
);
5517 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5519 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5520 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5521 unsigned num_channels
= util_last_bit(mask
);
5522 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5523 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5526 switch (num_channels
) {
5528 opcode
= aco_opcode::buffer_load_format_x
;
5531 opcode
= aco_opcode::buffer_load_format_xy
;
5534 opcode
= aco_opcode::buffer_load_format_xyz
;
5537 opcode
= aco_opcode::buffer_load_format_xyzw
;
5540 unreachable(">4 channel buffer image load");
5542 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5543 load
->operands
[0] = Operand(rsrc
);
5544 load
->operands
[1] = Operand(vindex
);
5545 load
->operands
[2] = Operand((uint32_t) 0);
5547 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5550 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5551 load
->definitions
[0] = Definition(tmp
);
5553 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5554 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5555 load
->barrier
= barrier_image
;
5556 ctx
->block
->instructions
.emplace_back(std::move(load
));
5558 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5562 Temp coords
= get_image_coords(ctx
, instr
, type
);
5563 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5565 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5566 unsigned num_components
= util_bitcount(dmask
);
5568 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5571 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5573 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5574 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5576 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5577 load
->operands
[0] = Operand(resource
);
5578 load
->operands
[1] = Operand(s4
); /* no sampler */
5579 load
->operands
[2] = Operand(coords
);
5580 load
->definitions
[0] = Definition(tmp
);
5581 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5582 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5583 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5584 load
->dmask
= dmask
;
5586 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5587 load
->barrier
= barrier_image
;
5588 ctx
->block
->instructions
.emplace_back(std::move(load
));
5590 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5594 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5596 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5597 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5598 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5599 bool is_array
= glsl_sampler_type_is_array(type
);
5600 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5602 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5604 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5605 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5606 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5608 switch (data
.size()) {
5610 opcode
= aco_opcode::buffer_store_format_x
;
5613 opcode
= aco_opcode::buffer_store_format_xy
;
5616 opcode
= aco_opcode::buffer_store_format_xyz
;
5619 opcode
= aco_opcode::buffer_store_format_xyzw
;
5622 unreachable(">4 channel buffer image store");
5624 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5625 store
->operands
[0] = Operand(rsrc
);
5626 store
->operands
[1] = Operand(vindex
);
5627 store
->operands
[2] = Operand((uint32_t) 0);
5628 store
->operands
[3] = Operand(data
);
5629 store
->idxen
= true;
5632 store
->disable_wqm
= true;
5633 store
->barrier
= barrier_image
;
5634 ctx
->program
->needs_exact
= true;
5635 ctx
->block
->instructions
.emplace_back(std::move(store
));
5639 assert(data
.type() == RegType::vgpr
);
5640 Temp coords
= get_image_coords(ctx
, instr
, type
);
5641 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5643 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5644 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5646 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5647 store
->operands
[0] = Operand(resource
);
5648 store
->operands
[1] = Operand(data
);
5649 store
->operands
[2] = Operand(coords
);
5652 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5653 store
->dmask
= (1 << data
.size()) - 1;
5655 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5656 store
->disable_wqm
= true;
5657 store
->barrier
= barrier_image
;
5658 ctx
->program
->needs_exact
= true;
5659 ctx
->block
->instructions
.emplace_back(std::move(store
));
5663 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5665 /* return the previous value if dest is ever used */
5666 bool return_previous
= false;
5667 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5668 return_previous
= true;
5671 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5672 return_previous
= true;
5676 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5677 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5678 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5679 bool is_array
= glsl_sampler_type_is_array(type
);
5680 Builder
bld(ctx
->program
, ctx
->block
);
5682 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5683 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5685 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5686 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5688 aco_opcode buf_op
, image_op
;
5689 switch (instr
->intrinsic
) {
5690 case nir_intrinsic_image_deref_atomic_add
:
5691 buf_op
= aco_opcode::buffer_atomic_add
;
5692 image_op
= aco_opcode::image_atomic_add
;
5694 case nir_intrinsic_image_deref_atomic_umin
:
5695 buf_op
= aco_opcode::buffer_atomic_umin
;
5696 image_op
= aco_opcode::image_atomic_umin
;
5698 case nir_intrinsic_image_deref_atomic_imin
:
5699 buf_op
= aco_opcode::buffer_atomic_smin
;
5700 image_op
= aco_opcode::image_atomic_smin
;
5702 case nir_intrinsic_image_deref_atomic_umax
:
5703 buf_op
= aco_opcode::buffer_atomic_umax
;
5704 image_op
= aco_opcode::image_atomic_umax
;
5706 case nir_intrinsic_image_deref_atomic_imax
:
5707 buf_op
= aco_opcode::buffer_atomic_smax
;
5708 image_op
= aco_opcode::image_atomic_smax
;
5710 case nir_intrinsic_image_deref_atomic_and
:
5711 buf_op
= aco_opcode::buffer_atomic_and
;
5712 image_op
= aco_opcode::image_atomic_and
;
5714 case nir_intrinsic_image_deref_atomic_or
:
5715 buf_op
= aco_opcode::buffer_atomic_or
;
5716 image_op
= aco_opcode::image_atomic_or
;
5718 case nir_intrinsic_image_deref_atomic_xor
:
5719 buf_op
= aco_opcode::buffer_atomic_xor
;
5720 image_op
= aco_opcode::image_atomic_xor
;
5722 case nir_intrinsic_image_deref_atomic_exchange
:
5723 buf_op
= aco_opcode::buffer_atomic_swap
;
5724 image_op
= aco_opcode::image_atomic_swap
;
5726 case nir_intrinsic_image_deref_atomic_comp_swap
:
5727 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5728 image_op
= aco_opcode::image_atomic_cmpswap
;
5731 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5734 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5736 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5737 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5738 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5739 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5740 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5741 mubuf
->operands
[0] = Operand(resource
);
5742 mubuf
->operands
[1] = Operand(vindex
);
5743 mubuf
->operands
[2] = Operand((uint32_t)0);
5744 mubuf
->operands
[3] = Operand(data
);
5745 if (return_previous
)
5746 mubuf
->definitions
[0] = Definition(dst
);
5748 mubuf
->idxen
= true;
5749 mubuf
->glc
= return_previous
;
5750 mubuf
->dlc
= false; /* Not needed for atomics */
5751 mubuf
->disable_wqm
= true;
5752 mubuf
->barrier
= barrier_image
;
5753 ctx
->program
->needs_exact
= true;
5754 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5758 Temp coords
= get_image_coords(ctx
, instr
, type
);
5759 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5760 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5761 mimg
->operands
[0] = Operand(resource
);
5762 mimg
->operands
[1] = Operand(data
);
5763 mimg
->operands
[2] = Operand(coords
);
5764 if (return_previous
)
5765 mimg
->definitions
[0] = Definition(dst
);
5766 mimg
->glc
= return_previous
;
5767 mimg
->dlc
= false; /* Not needed for atomics */
5768 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5769 mimg
->dmask
= (1 << data
.size()) - 1;
5771 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5772 mimg
->disable_wqm
= true;
5773 mimg
->barrier
= barrier_image
;
5774 ctx
->program
->needs_exact
= true;
5775 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5779 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5781 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5782 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5783 Builder
bld(ctx
->program
, ctx
->block
);
5785 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5787 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5788 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5790 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5791 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5793 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5794 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5796 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5797 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5798 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5799 if (dst
.type() == RegType::vgpr
)
5800 bld
.copy(Definition(dst
), shr_dst
);
5802 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5804 emit_extract_vector(ctx
, desc
, 2, dst
);
5808 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5810 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5811 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5812 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5813 bool is_array
= glsl_sampler_type_is_array(type
);
5814 Builder
bld(ctx
->program
, ctx
->block
);
5816 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5817 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5818 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5822 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5825 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5827 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5829 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5830 mimg
->operands
[0] = Operand(resource
);
5831 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5832 mimg
->operands
[2] = Operand(lod
);
5833 uint8_t& dmask
= mimg
->dmask
;
5834 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5835 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5836 mimg
->da
= glsl_sampler_type_is_array(type
);
5837 mimg
->can_reorder
= true;
5838 Definition
& def
= mimg
->definitions
[0];
5839 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5841 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5842 glsl_sampler_type_is_array(type
)) {
5844 assert(instr
->dest
.ssa
.num_components
== 3);
5845 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5846 def
= Definition(tmp
);
5847 emit_split_vector(ctx
, tmp
, 3);
5849 /* divide 3rd value by 6 by multiplying with magic number */
5850 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5851 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5853 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5854 emit_extract_vector(ctx
, tmp
, 0, v1
),
5855 emit_extract_vector(ctx
, tmp
, 1, v1
),
5858 } else if (ctx
->options
->chip_class
== GFX9
&&
5859 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5860 glsl_sampler_type_is_array(type
)) {
5861 assert(instr
->dest
.ssa
.num_components
== 2);
5862 def
= Definition(dst
);
5865 def
= Definition(dst
);
5868 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5871 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5873 Builder
bld(ctx
->program
, ctx
->block
);
5874 unsigned num_components
= instr
->num_components
;
5876 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5877 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5878 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5880 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5881 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5884 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5885 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5886 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5888 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
5891 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5893 Builder
bld(ctx
->program
, ctx
->block
);
5894 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5895 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5896 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5897 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5899 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5900 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5902 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5903 ctx
->options
->chip_class
>= GFX8
&&
5904 elem_size_bytes
>= 4;
5906 offset
= bld
.as_uniform(offset
);
5907 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5911 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5912 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5913 /* GFX6 doesn't support storing vec3, split it. */
5914 writemask
|= 1u << (start
+ 2);
5917 int num_bytes
= count
* elem_size_bytes
;
5919 /* dword or larger stores have to be dword-aligned */
5920 if (elem_size_bytes
< 4 && num_bytes
> 2) {
5921 // TODO: improve alignment check of sub-dword stores
5922 unsigned count_new
= 2 / elem_size_bytes
;
5923 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
5928 if (num_bytes
> 16) {
5929 assert(elem_size_bytes
== 8);
5930 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5936 if (elem_size_bytes
< 4) {
5937 if (data
.type() == RegType::sgpr
) {
5938 data
= as_vgpr(ctx
, data
);
5939 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
5941 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
5942 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5943 for (int i
= 0; i
< count
; i
++)
5944 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
5945 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
5946 vec
->definitions
[0] = Definition(write_data
);
5947 bld
.insert(std::move(vec
));
5948 } else if (count
!= instr
->num_components
) {
5949 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5950 for (int i
= 0; i
< count
; i
++) {
5951 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5952 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5954 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5955 vec
->definitions
[0] = Definition(write_data
);
5956 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5957 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5958 assert(num_bytes
% 4 == 0);
5959 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5960 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5961 assert(num_bytes
% 4 == 0);
5962 write_data
= bld
.as_uniform(data
);
5967 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
5968 switch (num_bytes
) {
5970 vmem_op
= aco_opcode::buffer_store_byte
;
5973 vmem_op
= aco_opcode::buffer_store_short
;
5976 vmem_op
= aco_opcode::buffer_store_dword
;
5977 smem_op
= aco_opcode::s_buffer_store_dword
;
5980 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5981 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5984 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5985 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5988 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5989 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5992 unreachable("Store SSBO not implemented for this size.");
5994 if (ctx
->stage
== fragment_fs
)
5995 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5998 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5999 store
->operands
[0] = Operand(rsrc
);
6001 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6002 offset
, Operand(start
* elem_size_bytes
));
6003 store
->operands
[1] = Operand(off
);
6005 store
->operands
[1] = Operand(offset
);
6007 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
6008 store
->operands
[1].setFixed(m0
);
6009 store
->operands
[2] = Operand(write_data
);
6010 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6012 store
->disable_wqm
= true;
6013 store
->barrier
= barrier_buffer
;
6014 ctx
->block
->instructions
.emplace_back(std::move(store
));
6015 ctx
->program
->wb_smem_l1_on_end
= true;
6016 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
6017 ctx
->block
->kind
|= block_kind_needs_lowering
;
6018 ctx
->program
->needs_exact
= true;
6021 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
6022 store
->operands
[0] = Operand(rsrc
);
6023 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6024 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6025 store
->operands
[3] = Operand(write_data
);
6026 store
->offset
= start
* elem_size_bytes
;
6027 store
->offen
= (offset
.type() == RegType::vgpr
);
6028 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6030 store
->disable_wqm
= true;
6031 store
->barrier
= barrier_buffer
;
6032 ctx
->program
->needs_exact
= true;
6033 ctx
->block
->instructions
.emplace_back(std::move(store
));
6038 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6040 /* return the previous value if dest is ever used */
6041 bool return_previous
= false;
6042 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6043 return_previous
= true;
6046 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6047 return_previous
= true;
6051 Builder
bld(ctx
->program
, ctx
->block
);
6052 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6054 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6055 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6056 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6058 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6059 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6060 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6062 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6064 aco_opcode op32
, op64
;
6065 switch (instr
->intrinsic
) {
6066 case nir_intrinsic_ssbo_atomic_add
:
6067 op32
= aco_opcode::buffer_atomic_add
;
6068 op64
= aco_opcode::buffer_atomic_add_x2
;
6070 case nir_intrinsic_ssbo_atomic_imin
:
6071 op32
= aco_opcode::buffer_atomic_smin
;
6072 op64
= aco_opcode::buffer_atomic_smin_x2
;
6074 case nir_intrinsic_ssbo_atomic_umin
:
6075 op32
= aco_opcode::buffer_atomic_umin
;
6076 op64
= aco_opcode::buffer_atomic_umin_x2
;
6078 case nir_intrinsic_ssbo_atomic_imax
:
6079 op32
= aco_opcode::buffer_atomic_smax
;
6080 op64
= aco_opcode::buffer_atomic_smax_x2
;
6082 case nir_intrinsic_ssbo_atomic_umax
:
6083 op32
= aco_opcode::buffer_atomic_umax
;
6084 op64
= aco_opcode::buffer_atomic_umax_x2
;
6086 case nir_intrinsic_ssbo_atomic_and
:
6087 op32
= aco_opcode::buffer_atomic_and
;
6088 op64
= aco_opcode::buffer_atomic_and_x2
;
6090 case nir_intrinsic_ssbo_atomic_or
:
6091 op32
= aco_opcode::buffer_atomic_or
;
6092 op64
= aco_opcode::buffer_atomic_or_x2
;
6094 case nir_intrinsic_ssbo_atomic_xor
:
6095 op32
= aco_opcode::buffer_atomic_xor
;
6096 op64
= aco_opcode::buffer_atomic_xor_x2
;
6098 case nir_intrinsic_ssbo_atomic_exchange
:
6099 op32
= aco_opcode::buffer_atomic_swap
;
6100 op64
= aco_opcode::buffer_atomic_swap_x2
;
6102 case nir_intrinsic_ssbo_atomic_comp_swap
:
6103 op32
= aco_opcode::buffer_atomic_cmpswap
;
6104 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6107 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6109 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6110 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6111 mubuf
->operands
[0] = Operand(rsrc
);
6112 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6113 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6114 mubuf
->operands
[3] = Operand(data
);
6115 if (return_previous
)
6116 mubuf
->definitions
[0] = Definition(dst
);
6118 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6119 mubuf
->glc
= return_previous
;
6120 mubuf
->dlc
= false; /* Not needed for atomics */
6121 mubuf
->disable_wqm
= true;
6122 mubuf
->barrier
= barrier_buffer
;
6123 ctx
->program
->needs_exact
= true;
6124 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6127 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6129 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6130 Builder
bld(ctx
->program
, ctx
->block
);
6131 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6132 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6135 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
6137 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6138 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6140 if (addr
.type() == RegType::vgpr
)
6141 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
6142 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
6145 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6147 Builder
bld(ctx
->program
, ctx
->block
);
6148 unsigned num_components
= instr
->num_components
;
6149 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
6151 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6152 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6154 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6155 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
6157 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
6158 bool global
= ctx
->options
->chip_class
>= GFX9
;
6160 if (ctx
->options
->chip_class
>= GFX7
) {
6162 switch (num_bytes
) {
6164 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
6167 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
6170 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
6173 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
6176 unreachable("load_global not implemented for this size.");
6179 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
6180 flat
->operands
[0] = Operand(addr
);
6181 flat
->operands
[1] = Operand(s1
);
6184 flat
->barrier
= barrier_buffer
;
6186 if (dst
.type() == RegType::sgpr
) {
6187 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6188 flat
->definitions
[0] = Definition(vec
);
6189 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6190 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6192 flat
->definitions
[0] = Definition(dst
);
6193 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6195 emit_split_vector(ctx
, dst
, num_components
);
6197 assert(ctx
->options
->chip_class
== GFX6
);
6199 /* GFX6 doesn't support loading vec3, expand to vec4. */
6200 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6203 switch (num_bytes
) {
6205 op
= aco_opcode::buffer_load_dword
;
6208 op
= aco_opcode::buffer_load_dwordx2
;
6211 op
= aco_opcode::buffer_load_dwordx4
;
6214 unreachable("load_global not implemented for this size.");
6217 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6219 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6220 mubuf
->operands
[0] = Operand(rsrc
);
6221 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6222 mubuf
->operands
[2] = Operand(0u);
6226 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6227 mubuf
->disable_wqm
= false;
6228 mubuf
->barrier
= barrier_buffer
;
6229 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6232 if (dst
.size() == 3) {
6233 Temp vec
= bld
.tmp(v4
);
6234 instr
->definitions
[0] = Definition(vec
);
6235 bld
.insert(std::move(instr
));
6236 emit_split_vector(ctx
, vec
, 4);
6238 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6239 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6240 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6241 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6244 if (dst
.type() == RegType::sgpr
) {
6245 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6246 instr
->definitions
[0] = Definition(vec
);
6247 bld
.insert(std::move(instr
));
6248 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6249 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6251 instr
->definitions
[0] = Definition(dst
);
6252 bld
.insert(std::move(instr
));
6253 emit_split_vector(ctx
, dst
, num_components
);
6257 switch (num_bytes
) {
6259 op
= aco_opcode::s_load_dword
;
6262 op
= aco_opcode::s_load_dwordx2
;
6266 op
= aco_opcode::s_load_dwordx4
;
6269 unreachable("load_global not implemented for this size.");
6271 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6272 load
->operands
[0] = Operand(addr
);
6273 load
->operands
[1] = Operand(0u);
6274 load
->definitions
[0] = Definition(dst
);
6277 load
->barrier
= barrier_buffer
;
6278 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6280 if (dst
.size() == 3) {
6282 Temp vec
= bld
.tmp(s4
);
6283 load
->definitions
[0] = Definition(vec
);
6284 ctx
->block
->instructions
.emplace_back(std::move(load
));
6285 emit_split_vector(ctx
, vec
, 4);
6287 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6288 emit_extract_vector(ctx
, vec
, 0, s1
),
6289 emit_extract_vector(ctx
, vec
, 1, s1
),
6290 emit_extract_vector(ctx
, vec
, 2, s1
));
6292 ctx
->block
->instructions
.emplace_back(std::move(load
));
6297 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6299 Builder
bld(ctx
->program
, ctx
->block
);
6300 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6302 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6303 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6305 if (ctx
->options
->chip_class
>= GFX7
)
6306 addr
= as_vgpr(ctx
, addr
);
6308 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6311 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6312 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6313 /* GFX6 doesn't support storing vec3, split it. */
6314 writemask
|= 1u << (start
+ 2);
6317 unsigned num_bytes
= count
* elem_size_bytes
;
6319 Temp write_data
= data
;
6320 if (count
!= instr
->num_components
) {
6321 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6322 for (int i
= 0; i
< count
; i
++)
6323 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6324 write_data
= bld
.tmp(RegType::vgpr
, count
);
6325 vec
->definitions
[0] = Definition(write_data
);
6326 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6329 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6330 unsigned offset
= start
* elem_size_bytes
;
6332 if (ctx
->options
->chip_class
>= GFX7
) {
6333 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6334 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6335 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6336 Temp carry
= bld
.tmp(bld
.lm
);
6337 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6339 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6340 Operand(offset
), addr0
);
6341 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6343 carry
).def(1).setHint(vcc
);
6345 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6350 bool global
= ctx
->options
->chip_class
>= GFX9
;
6352 switch (num_bytes
) {
6354 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6357 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6360 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6363 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6366 unreachable("store_global not implemented for this size.");
6369 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6370 flat
->operands
[0] = Operand(addr
);
6371 flat
->operands
[1] = Operand(s1
);
6372 flat
->operands
[2] = Operand(data
);
6375 flat
->offset
= offset
;
6376 flat
->disable_wqm
= true;
6377 flat
->barrier
= barrier_buffer
;
6378 ctx
->program
->needs_exact
= true;
6379 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6381 assert(ctx
->options
->chip_class
== GFX6
);
6384 switch (num_bytes
) {
6386 op
= aco_opcode::buffer_store_dword
;
6389 op
= aco_opcode::buffer_store_dwordx2
;
6392 op
= aco_opcode::buffer_store_dwordx4
;
6395 unreachable("store_global not implemented for this size.");
6398 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6400 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6401 mubuf
->operands
[0] = Operand(rsrc
);
6402 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6403 mubuf
->operands
[2] = Operand(0u);
6404 mubuf
->operands
[3] = Operand(write_data
);
6407 mubuf
->offset
= offset
;
6408 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6409 mubuf
->disable_wqm
= true;
6410 mubuf
->barrier
= barrier_buffer
;
6411 ctx
->program
->needs_exact
= true;
6412 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6417 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6419 /* return the previous value if dest is ever used */
6420 bool return_previous
= false;
6421 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6422 return_previous
= true;
6425 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6426 return_previous
= true;
6430 Builder
bld(ctx
->program
, ctx
->block
);
6431 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6432 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6434 if (ctx
->options
->chip_class
>= GFX7
)
6435 addr
= as_vgpr(ctx
, addr
);
6437 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6438 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6439 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6441 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6443 aco_opcode op32
, op64
;
6445 if (ctx
->options
->chip_class
>= GFX7
) {
6446 bool global
= ctx
->options
->chip_class
>= GFX9
;
6447 switch (instr
->intrinsic
) {
6448 case nir_intrinsic_global_atomic_add
:
6449 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6450 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6452 case nir_intrinsic_global_atomic_imin
:
6453 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6454 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6456 case nir_intrinsic_global_atomic_umin
:
6457 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6458 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6460 case nir_intrinsic_global_atomic_imax
:
6461 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6462 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6464 case nir_intrinsic_global_atomic_umax
:
6465 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6466 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6468 case nir_intrinsic_global_atomic_and
:
6469 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6470 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6472 case nir_intrinsic_global_atomic_or
:
6473 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6474 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6476 case nir_intrinsic_global_atomic_xor
:
6477 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6478 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6480 case nir_intrinsic_global_atomic_exchange
:
6481 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6482 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6484 case nir_intrinsic_global_atomic_comp_swap
:
6485 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6486 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6489 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6492 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6493 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6494 flat
->operands
[0] = Operand(addr
);
6495 flat
->operands
[1] = Operand(s1
);
6496 flat
->operands
[2] = Operand(data
);
6497 if (return_previous
)
6498 flat
->definitions
[0] = Definition(dst
);
6499 flat
->glc
= return_previous
;
6500 flat
->dlc
= false; /* Not needed for atomics */
6502 flat
->disable_wqm
= true;
6503 flat
->barrier
= barrier_buffer
;
6504 ctx
->program
->needs_exact
= true;
6505 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6507 assert(ctx
->options
->chip_class
== GFX6
);
6509 switch (instr
->intrinsic
) {
6510 case nir_intrinsic_global_atomic_add
:
6511 op32
= aco_opcode::buffer_atomic_add
;
6512 op64
= aco_opcode::buffer_atomic_add_x2
;
6514 case nir_intrinsic_global_atomic_imin
:
6515 op32
= aco_opcode::buffer_atomic_smin
;
6516 op64
= aco_opcode::buffer_atomic_smin_x2
;
6518 case nir_intrinsic_global_atomic_umin
:
6519 op32
= aco_opcode::buffer_atomic_umin
;
6520 op64
= aco_opcode::buffer_atomic_umin_x2
;
6522 case nir_intrinsic_global_atomic_imax
:
6523 op32
= aco_opcode::buffer_atomic_smax
;
6524 op64
= aco_opcode::buffer_atomic_smax_x2
;
6526 case nir_intrinsic_global_atomic_umax
:
6527 op32
= aco_opcode::buffer_atomic_umax
;
6528 op64
= aco_opcode::buffer_atomic_umax_x2
;
6530 case nir_intrinsic_global_atomic_and
:
6531 op32
= aco_opcode::buffer_atomic_and
;
6532 op64
= aco_opcode::buffer_atomic_and_x2
;
6534 case nir_intrinsic_global_atomic_or
:
6535 op32
= aco_opcode::buffer_atomic_or
;
6536 op64
= aco_opcode::buffer_atomic_or_x2
;
6538 case nir_intrinsic_global_atomic_xor
:
6539 op32
= aco_opcode::buffer_atomic_xor
;
6540 op64
= aco_opcode::buffer_atomic_xor_x2
;
6542 case nir_intrinsic_global_atomic_exchange
:
6543 op32
= aco_opcode::buffer_atomic_swap
;
6544 op64
= aco_opcode::buffer_atomic_swap_x2
;
6546 case nir_intrinsic_global_atomic_comp_swap
:
6547 op32
= aco_opcode::buffer_atomic_cmpswap
;
6548 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6551 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6554 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6556 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6558 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6559 mubuf
->operands
[0] = Operand(rsrc
);
6560 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6561 mubuf
->operands
[2] = Operand(0u);
6562 mubuf
->operands
[3] = Operand(data
);
6563 if (return_previous
)
6564 mubuf
->definitions
[0] = Definition(dst
);
6565 mubuf
->glc
= return_previous
;
6568 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6569 mubuf
->disable_wqm
= true;
6570 mubuf
->barrier
= barrier_buffer
;
6571 ctx
->program
->needs_exact
= true;
6572 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6576 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6577 Builder
bld(ctx
->program
, ctx
->block
);
6578 switch(instr
->intrinsic
) {
6579 case nir_intrinsic_group_memory_barrier
:
6580 case nir_intrinsic_memory_barrier
:
6581 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6583 case nir_intrinsic_memory_barrier_buffer
:
6584 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6586 case nir_intrinsic_memory_barrier_image
:
6587 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6589 case nir_intrinsic_memory_barrier_tcs_patch
:
6590 case nir_intrinsic_memory_barrier_shared
:
6591 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6594 unreachable("Unimplemented memory barrier intrinsic");
6599 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6601 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6602 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6603 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6604 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6605 Builder
bld(ctx
->program
, ctx
->block
);
6607 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6608 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6609 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6612 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6614 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6615 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6616 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6617 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6618 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6620 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6621 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6624 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6626 unsigned offset
= nir_intrinsic_base(instr
);
6627 Operand m
= load_lds_size_m0(ctx
);
6628 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6629 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6631 unsigned num_operands
= 3;
6632 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6633 switch(instr
->intrinsic
) {
6634 case nir_intrinsic_shared_atomic_add
:
6635 op32
= aco_opcode::ds_add_u32
;
6636 op64
= aco_opcode::ds_add_u64
;
6637 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6638 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6640 case nir_intrinsic_shared_atomic_imin
:
6641 op32
= aco_opcode::ds_min_i32
;
6642 op64
= aco_opcode::ds_min_i64
;
6643 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6644 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6646 case nir_intrinsic_shared_atomic_umin
:
6647 op32
= aco_opcode::ds_min_u32
;
6648 op64
= aco_opcode::ds_min_u64
;
6649 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6650 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6652 case nir_intrinsic_shared_atomic_imax
:
6653 op32
= aco_opcode::ds_max_i32
;
6654 op64
= aco_opcode::ds_max_i64
;
6655 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6656 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6658 case nir_intrinsic_shared_atomic_umax
:
6659 op32
= aco_opcode::ds_max_u32
;
6660 op64
= aco_opcode::ds_max_u64
;
6661 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6662 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6664 case nir_intrinsic_shared_atomic_and
:
6665 op32
= aco_opcode::ds_and_b32
;
6666 op64
= aco_opcode::ds_and_b64
;
6667 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6668 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6670 case nir_intrinsic_shared_atomic_or
:
6671 op32
= aco_opcode::ds_or_b32
;
6672 op64
= aco_opcode::ds_or_b64
;
6673 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6674 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6676 case nir_intrinsic_shared_atomic_xor
:
6677 op32
= aco_opcode::ds_xor_b32
;
6678 op64
= aco_opcode::ds_xor_b64
;
6679 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6680 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6682 case nir_intrinsic_shared_atomic_exchange
:
6683 op32
= aco_opcode::ds_write_b32
;
6684 op64
= aco_opcode::ds_write_b64
;
6685 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6686 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6688 case nir_intrinsic_shared_atomic_comp_swap
:
6689 op32
= aco_opcode::ds_cmpst_b32
;
6690 op64
= aco_opcode::ds_cmpst_b64
;
6691 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6692 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6696 unreachable("Unhandled shared atomic intrinsic");
6699 /* return the previous value if dest is ever used */
6700 bool return_previous
= false;
6701 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6702 return_previous
= true;
6705 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6706 return_previous
= true;
6711 if (data
.size() == 1) {
6712 assert(instr
->dest
.ssa
.bit_size
== 32);
6713 op
= return_previous
? op32_rtn
: op32
;
6715 assert(instr
->dest
.ssa
.bit_size
== 64);
6716 op
= return_previous
? op64_rtn
: op64
;
6719 if (offset
> 65535) {
6720 Builder
bld(ctx
->program
, ctx
->block
);
6721 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6725 aco_ptr
<DS_instruction
> ds
;
6726 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6727 ds
->operands
[0] = Operand(address
);
6728 ds
->operands
[1] = Operand(data
);
6729 if (num_operands
== 4)
6730 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6731 ds
->operands
[num_operands
- 1] = m
;
6732 ds
->offset0
= offset
;
6733 if (return_previous
)
6734 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6735 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6738 Temp
get_scratch_resource(isel_context
*ctx
)
6740 Builder
bld(ctx
->program
, ctx
->block
);
6741 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6742 if (ctx
->stage
!= compute_cs
)
6743 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6745 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6746 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6748 if (ctx
->program
->chip_class
>= GFX10
) {
6749 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6750 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6751 S_008F0C_RESOURCE_LEVEL(1);
6752 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6753 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6754 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6757 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6758 if (ctx
->program
->chip_class
<= GFX8
)
6759 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6761 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6764 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6765 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6766 Builder
bld(ctx
->program
, ctx
->block
);
6767 Temp rsrc
= get_scratch_resource(ctx
);
6768 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6769 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6772 switch (dst
.size()) {
6774 op
= aco_opcode::buffer_load_dword
;
6777 op
= aco_opcode::buffer_load_dwordx2
;
6780 op
= aco_opcode::buffer_load_dwordx3
;
6783 op
= aco_opcode::buffer_load_dwordx4
;
6787 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6788 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6789 bld
.def(v4
), rsrc
, offset
,
6790 ctx
->program
->scratch_offset
, 0, true);
6791 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6792 aco_opcode::buffer_load_dwordx4
,
6793 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6794 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6795 emit_split_vector(ctx
, lower
, 2);
6796 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6797 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6798 if (dst
.size() == 8) {
6799 emit_split_vector(ctx
, upper
, 2);
6800 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6801 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6806 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6807 Format::PSEUDO
, dst
.size() / 2, 1)};
6808 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6809 vec
->operands
[i
] = Operand(elems
[i
]);
6810 vec
->definitions
[0] = Definition(dst
);
6811 bld
.insert(std::move(vec
));
6812 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6816 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6819 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6820 emit_split_vector(ctx
, dst
, instr
->num_components
);
6823 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6824 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6825 Builder
bld(ctx
->program
, ctx
->block
);
6826 Temp rsrc
= get_scratch_resource(ctx
);
6827 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6828 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6830 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6831 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6835 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6836 int num_bytes
= count
* elem_size_bytes
;
6838 if (num_bytes
> 16) {
6839 assert(elem_size_bytes
== 8);
6840 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6845 // TODO: check alignment of sub-dword stores
6846 // TODO: split 3 bytes. there is no store instruction for that
6849 if (count
!= instr
->num_components
) {
6850 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6851 for (int i
= 0; i
< count
; i
++) {
6852 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6853 vec
->operands
[i
] = Operand(elem
);
6855 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6856 vec
->definitions
[0] = Definition(write_data
);
6857 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6863 switch (num_bytes
) {
6865 op
= aco_opcode::buffer_store_dword
;
6868 op
= aco_opcode::buffer_store_dwordx2
;
6871 op
= aco_opcode::buffer_store_dwordx3
;
6874 op
= aco_opcode::buffer_store_dwordx4
;
6877 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6880 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6884 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6885 uint8_t log2_ps_iter_samples
;
6886 if (ctx
->program
->info
->ps
.force_persample
) {
6887 log2_ps_iter_samples
=
6888 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6890 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6893 /* The bit pattern matches that used by fixed function fragment
6895 static const unsigned ps_iter_masks
[] = {
6896 0xffff, /* not used */
6902 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6904 Builder
bld(ctx
->program
, ctx
->block
);
6906 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6907 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6908 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6909 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6910 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6911 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6914 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6915 Builder
bld(ctx
->program
, ctx
->block
);
6917 unsigned stream
= nir_intrinsic_stream_id(instr
);
6918 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6919 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6920 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6923 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6925 unsigned num_components
=
6926 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6927 assert(num_components
);
6929 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6930 unsigned stream_offset
= 0;
6931 for (unsigned i
= 0; i
< stream
; i
++) {
6932 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6933 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6936 /* Limit on the stride field for <= GFX7. */
6937 assert(stride
< (1 << 14));
6939 Temp gsvs_dwords
[4];
6940 for (unsigned i
= 0; i
< 4; i
++)
6941 gsvs_dwords
[i
] = bld
.tmp(s1
);
6942 bld
.pseudo(aco_opcode::p_split_vector
,
6943 Definition(gsvs_dwords
[0]),
6944 Definition(gsvs_dwords
[1]),
6945 Definition(gsvs_dwords
[2]),
6946 Definition(gsvs_dwords
[3]),
6949 if (stream_offset
) {
6950 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6952 Temp carry
= bld
.tmp(s1
);
6953 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6954 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6957 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6958 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6960 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6961 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6963 unsigned offset
= 0;
6964 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6965 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6968 for (unsigned j
= 0; j
< 4; j
++) {
6969 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6972 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6973 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6974 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6975 if (const_offset
>= 4096u) {
6976 if (vaddr_offset
.isUndefined())
6977 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6979 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6980 const_offset
%= 4096u;
6983 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6984 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6985 mtbuf
->operands
[1] = vaddr_offset
;
6986 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6987 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6988 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6989 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6990 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6991 mtbuf
->offset
= const_offset
;
6994 mtbuf
->barrier
= barrier_gs_data
;
6995 mtbuf
->can_reorder
= true;
6996 bld
.insert(std::move(mtbuf
));
6999 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
7002 /* outputs for the next vertex are undefined and keeping them around can
7003 * create invalid IR with control flow */
7004 ctx
->outputs
.mask
[i
] = 0;
7007 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7010 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7012 Builder
bld(ctx
->program
, ctx
->block
);
7014 if (cluster_size
== 1) {
7016 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7017 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7018 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7019 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7020 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7021 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7022 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7023 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7024 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7025 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7026 //subgroupAnd(val) -> (exec & ~val) == 0
7027 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7028 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7029 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7030 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7031 //subgroupOr(val) -> (val & exec) != 0
7032 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7033 return bool_to_vector_condition(ctx
, tmp
);
7034 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7035 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7036 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7037 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7038 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7039 return bool_to_vector_condition(ctx
, tmp
);
7041 //subgroupClustered{And,Or,Xor}(val, n) ->
7042 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7043 //cluster_offset = ~(n - 1) & lane_id
7044 //cluster_mask = ((1 << n) - 1)
7045 //subgroupClusteredAnd():
7046 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7047 //subgroupClusteredOr():
7048 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7049 //subgroupClusteredXor():
7050 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7051 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7052 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7055 if (op
== nir_op_iand
)
7056 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7058 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7060 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7062 if (ctx
->program
->chip_class
<= GFX7
)
7063 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7064 else if (ctx
->program
->wave_size
== 64)
7065 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7067 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7068 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7069 if (cluster_mask
!= 0xffffffff)
7070 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7072 Definition cmp_def
= Definition();
7073 if (op
== nir_op_iand
) {
7074 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7075 } else if (op
== nir_op_ior
) {
7076 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7077 } else if (op
== nir_op_ixor
) {
7078 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7079 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7080 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7082 cmp_def
.setHint(vcc
);
7083 return cmp_def
.getTemp();
7087 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7089 Builder
bld(ctx
->program
, ctx
->block
);
7091 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7092 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7093 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7095 if (op
== nir_op_iand
)
7096 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7098 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7100 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7101 Temp lo
= lohi
.def(0).getTemp();
7102 Temp hi
= lohi
.def(1).getTemp();
7103 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7105 Definition cmp_def
= Definition();
7106 if (op
== nir_op_iand
)
7107 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7108 else if (op
== nir_op_ior
)
7109 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7110 else if (op
== nir_op_ixor
)
7111 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7112 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7113 cmp_def
.setHint(vcc
);
7114 return cmp_def
.getTemp();
7117 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7119 Builder
bld(ctx
->program
, ctx
->block
);
7121 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7122 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7123 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7124 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7125 if (op
== nir_op_iand
)
7126 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7127 else if (op
== nir_op_ior
)
7128 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7129 else if (op
== nir_op_ixor
)
7130 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7136 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7138 Builder
bld(ctx
->program
, ctx
->block
);
7139 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7140 if (src
.regClass().type() == RegType::vgpr
) {
7141 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7142 } else if (src
.regClass() == s1
) {
7143 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7144 } else if (src
.regClass() == s2
) {
7145 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7147 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7148 nir_print_instr(&instr
->instr
, stderr
);
7149 fprintf(stderr
, "\n");
7153 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7155 Builder
bld(ctx
->program
, ctx
->block
);
7156 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7157 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7158 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7160 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7161 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7162 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7163 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7166 if (ctx
->program
->chip_class
>= GFX8
) {
7167 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7168 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7169 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7170 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7171 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7172 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7174 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7175 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7176 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7177 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7178 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7179 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7180 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7181 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7182 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7183 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7186 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7187 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7188 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7189 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7190 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7191 Temp wqm1
= bld
.tmp(v1
);
7192 emit_wqm(ctx
, tmp1
, wqm1
, true);
7193 Temp wqm2
= bld
.tmp(v1
);
7194 emit_wqm(ctx
, tmp2
, wqm2
, true);
7195 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7199 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7201 Builder
bld(ctx
->program
, ctx
->block
);
7202 switch(instr
->intrinsic
) {
7203 case nir_intrinsic_load_barycentric_sample
:
7204 case nir_intrinsic_load_barycentric_pixel
:
7205 case nir_intrinsic_load_barycentric_centroid
: {
7206 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7207 Temp bary
= Temp(0, s2
);
7209 case INTERP_MODE_SMOOTH
:
7210 case INTERP_MODE_NONE
:
7211 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7212 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7213 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7214 bary
= ctx
->persp_centroid
;
7215 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7216 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7218 case INTERP_MODE_NOPERSPECTIVE
:
7219 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7220 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7221 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7222 bary
= ctx
->linear_centroid
;
7223 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7224 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7229 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7230 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7231 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7232 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7233 Operand(p1
), Operand(p2
));
7234 emit_split_vector(ctx
, dst
, 2);
7237 case nir_intrinsic_load_barycentric_model
: {
7238 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7240 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7241 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7242 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7243 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7244 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7245 Operand(p1
), Operand(p2
), Operand(p3
));
7246 emit_split_vector(ctx
, dst
, 3);
7249 case nir_intrinsic_load_barycentric_at_sample
: {
7250 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7251 switch (ctx
->options
->key
.fs
.num_samples
) {
7252 case 2: sample_pos_offset
+= 1 << 3; break;
7253 case 4: sample_pos_offset
+= 3 << 3; break;
7254 case 8: sample_pos_offset
+= 7 << 3; break;
7258 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7259 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7260 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7261 if (addr
.type() == RegType::sgpr
) {
7264 sample_pos_offset
+= const_addr
->u32
<< 3;
7265 offset
= Operand(sample_pos_offset
);
7266 } else if (ctx
->options
->chip_class
>= GFX9
) {
7267 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7269 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7270 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7273 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7274 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7276 } else if (ctx
->options
->chip_class
>= GFX9
) {
7277 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7278 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7279 } else if (ctx
->options
->chip_class
>= GFX7
) {
7280 /* addr += private_segment_buffer + sample_pos_offset */
7281 Temp tmp0
= bld
.tmp(s1
);
7282 Temp tmp1
= bld
.tmp(s1
);
7283 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7284 Definition scc_tmp
= bld
.def(s1
, scc
);
7285 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7286 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7287 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7288 Temp pck0
= bld
.tmp(v1
);
7289 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7290 tmp1
= as_vgpr(ctx
, tmp1
);
7291 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7292 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7294 /* sample_pos = flat_load_dwordx2 addr */
7295 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7297 assert(ctx
->options
->chip_class
== GFX6
);
7299 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7300 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7301 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7303 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7304 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7306 sample_pos
= bld
.tmp(v2
);
7308 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7309 load
->definitions
[0] = Definition(sample_pos
);
7310 load
->operands
[0] = Operand(rsrc
);
7311 load
->operands
[1] = Operand(addr
);
7312 load
->operands
[2] = Operand(0u);
7313 load
->offset
= sample_pos_offset
;
7315 load
->addr64
= true;
7318 load
->disable_wqm
= false;
7319 load
->barrier
= barrier_none
;
7320 load
->can_reorder
= true;
7321 ctx
->block
->instructions
.emplace_back(std::move(load
));
7324 /* sample_pos -= 0.5 */
7325 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7326 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7327 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7328 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7329 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7331 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7334 case nir_intrinsic_load_barycentric_at_offset
: {
7335 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7336 RegClass rc
= RegClass(offset
.type(), 1);
7337 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7338 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7339 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7342 case nir_intrinsic_load_front_face
: {
7343 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7344 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7347 case nir_intrinsic_load_view_index
: {
7348 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7349 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7350 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7356 case nir_intrinsic_load_layer_id
: {
7357 unsigned idx
= nir_intrinsic_base(instr
);
7358 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7359 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7362 case nir_intrinsic_load_frag_coord
: {
7363 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7366 case nir_intrinsic_load_sample_pos
: {
7367 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7368 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7369 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7370 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7371 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7374 case nir_intrinsic_load_tess_coord
:
7375 visit_load_tess_coord(ctx
, instr
);
7377 case nir_intrinsic_load_interpolated_input
:
7378 visit_load_interpolated_input(ctx
, instr
);
7380 case nir_intrinsic_store_output
:
7381 visit_store_output(ctx
, instr
);
7383 case nir_intrinsic_load_input
:
7384 case nir_intrinsic_load_input_vertex
:
7385 visit_load_input(ctx
, instr
);
7387 case nir_intrinsic_load_output
:
7388 visit_load_output(ctx
, instr
);
7390 case nir_intrinsic_load_per_vertex_input
:
7391 visit_load_per_vertex_input(ctx
, instr
);
7393 case nir_intrinsic_load_per_vertex_output
:
7394 visit_load_per_vertex_output(ctx
, instr
);
7396 case nir_intrinsic_store_per_vertex_output
:
7397 visit_store_per_vertex_output(ctx
, instr
);
7399 case nir_intrinsic_load_ubo
:
7400 visit_load_ubo(ctx
, instr
);
7402 case nir_intrinsic_load_push_constant
:
7403 visit_load_push_constant(ctx
, instr
);
7405 case nir_intrinsic_load_constant
:
7406 visit_load_constant(ctx
, instr
);
7408 case nir_intrinsic_vulkan_resource_index
:
7409 visit_load_resource(ctx
, instr
);
7411 case nir_intrinsic_discard
:
7412 visit_discard(ctx
, instr
);
7414 case nir_intrinsic_discard_if
:
7415 visit_discard_if(ctx
, instr
);
7417 case nir_intrinsic_load_shared
:
7418 visit_load_shared(ctx
, instr
);
7420 case nir_intrinsic_store_shared
:
7421 visit_store_shared(ctx
, instr
);
7423 case nir_intrinsic_shared_atomic_add
:
7424 case nir_intrinsic_shared_atomic_imin
:
7425 case nir_intrinsic_shared_atomic_umin
:
7426 case nir_intrinsic_shared_atomic_imax
:
7427 case nir_intrinsic_shared_atomic_umax
:
7428 case nir_intrinsic_shared_atomic_and
:
7429 case nir_intrinsic_shared_atomic_or
:
7430 case nir_intrinsic_shared_atomic_xor
:
7431 case nir_intrinsic_shared_atomic_exchange
:
7432 case nir_intrinsic_shared_atomic_comp_swap
:
7433 visit_shared_atomic(ctx
, instr
);
7435 case nir_intrinsic_image_deref_load
:
7436 visit_image_load(ctx
, instr
);
7438 case nir_intrinsic_image_deref_store
:
7439 visit_image_store(ctx
, instr
);
7441 case nir_intrinsic_image_deref_atomic_add
:
7442 case nir_intrinsic_image_deref_atomic_umin
:
7443 case nir_intrinsic_image_deref_atomic_imin
:
7444 case nir_intrinsic_image_deref_atomic_umax
:
7445 case nir_intrinsic_image_deref_atomic_imax
:
7446 case nir_intrinsic_image_deref_atomic_and
:
7447 case nir_intrinsic_image_deref_atomic_or
:
7448 case nir_intrinsic_image_deref_atomic_xor
:
7449 case nir_intrinsic_image_deref_atomic_exchange
:
7450 case nir_intrinsic_image_deref_atomic_comp_swap
:
7451 visit_image_atomic(ctx
, instr
);
7453 case nir_intrinsic_image_deref_size
:
7454 visit_image_size(ctx
, instr
);
7456 case nir_intrinsic_load_ssbo
:
7457 visit_load_ssbo(ctx
, instr
);
7459 case nir_intrinsic_store_ssbo
:
7460 visit_store_ssbo(ctx
, instr
);
7462 case nir_intrinsic_load_global
:
7463 visit_load_global(ctx
, instr
);
7465 case nir_intrinsic_store_global
:
7466 visit_store_global(ctx
, instr
);
7468 case nir_intrinsic_global_atomic_add
:
7469 case nir_intrinsic_global_atomic_imin
:
7470 case nir_intrinsic_global_atomic_umin
:
7471 case nir_intrinsic_global_atomic_imax
:
7472 case nir_intrinsic_global_atomic_umax
:
7473 case nir_intrinsic_global_atomic_and
:
7474 case nir_intrinsic_global_atomic_or
:
7475 case nir_intrinsic_global_atomic_xor
:
7476 case nir_intrinsic_global_atomic_exchange
:
7477 case nir_intrinsic_global_atomic_comp_swap
:
7478 visit_global_atomic(ctx
, instr
);
7480 case nir_intrinsic_ssbo_atomic_add
:
7481 case nir_intrinsic_ssbo_atomic_imin
:
7482 case nir_intrinsic_ssbo_atomic_umin
:
7483 case nir_intrinsic_ssbo_atomic_imax
:
7484 case nir_intrinsic_ssbo_atomic_umax
:
7485 case nir_intrinsic_ssbo_atomic_and
:
7486 case nir_intrinsic_ssbo_atomic_or
:
7487 case nir_intrinsic_ssbo_atomic_xor
:
7488 case nir_intrinsic_ssbo_atomic_exchange
:
7489 case nir_intrinsic_ssbo_atomic_comp_swap
:
7490 visit_atomic_ssbo(ctx
, instr
);
7492 case nir_intrinsic_load_scratch
:
7493 visit_load_scratch(ctx
, instr
);
7495 case nir_intrinsic_store_scratch
:
7496 visit_store_scratch(ctx
, instr
);
7498 case nir_intrinsic_get_buffer_size
:
7499 visit_get_buffer_size(ctx
, instr
);
7501 case nir_intrinsic_control_barrier
: {
7502 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7503 /* GFX6 only (thanks to a hw bug workaround):
7504 * The real barrier instruction isn’t needed, because an entire patch
7505 * always fits into a single wave.
7510 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7511 bld
.sopp(aco_opcode::s_barrier
);
7515 case nir_intrinsic_memory_barrier_tcs_patch
:
7516 case nir_intrinsic_group_memory_barrier
:
7517 case nir_intrinsic_memory_barrier
:
7518 case nir_intrinsic_memory_barrier_buffer
:
7519 case nir_intrinsic_memory_barrier_image
:
7520 case nir_intrinsic_memory_barrier_shared
:
7521 emit_memory_barrier(ctx
, instr
);
7523 case nir_intrinsic_load_num_work_groups
: {
7524 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7525 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7526 emit_split_vector(ctx
, dst
, 3);
7529 case nir_intrinsic_load_local_invocation_id
: {
7530 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7531 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7532 emit_split_vector(ctx
, dst
, 3);
7535 case nir_intrinsic_load_work_group_id
: {
7536 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7537 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7538 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7539 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7540 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7541 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7542 emit_split_vector(ctx
, dst
, 3);
7545 case nir_intrinsic_load_local_invocation_index
: {
7546 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7548 /* The tg_size bits [6:11] contain the subgroup id,
7549 * we need this multiplied by the wave size, and then OR the thread id to it.
7551 if (ctx
->program
->wave_size
== 64) {
7552 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7553 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7554 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7555 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7557 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7558 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7559 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7560 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7564 case nir_intrinsic_load_subgroup_id
: {
7565 if (ctx
->stage
== compute_cs
) {
7566 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7567 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7569 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7573 case nir_intrinsic_load_subgroup_invocation
: {
7574 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7577 case nir_intrinsic_load_num_subgroups
: {
7578 if (ctx
->stage
== compute_cs
)
7579 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7580 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7582 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7585 case nir_intrinsic_ballot
: {
7586 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7587 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7588 Definition tmp
= bld
.def(dst
.regClass());
7589 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7590 if (instr
->src
[0].ssa
->bit_size
== 1) {
7591 assert(src
.regClass() == bld
.lm
);
7592 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7593 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7594 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7595 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7596 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7598 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7599 nir_print_instr(&instr
->instr
, stderr
);
7600 fprintf(stderr
, "\n");
7602 if (dst
.size() != bld
.lm
.size()) {
7603 /* Wave32 with ballot size set to 64 */
7604 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7606 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7609 case nir_intrinsic_shuffle
:
7610 case nir_intrinsic_read_invocation
: {
7611 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7612 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7613 emit_uniform_subgroup(ctx
, instr
, src
);
7615 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7616 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7617 tid
= bld
.as_uniform(tid
);
7618 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7619 if (src
.regClass() == v1
) {
7620 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7621 } else if (src
.regClass() == v2
) {
7622 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7623 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7624 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7625 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7626 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7627 emit_split_vector(ctx
, dst
, 2);
7628 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7629 assert(src
.regClass() == bld
.lm
);
7630 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7631 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7632 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7633 assert(src
.regClass() == bld
.lm
);
7635 if (ctx
->program
->chip_class
<= GFX7
)
7636 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7637 else if (ctx
->program
->wave_size
== 64)
7638 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7640 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7641 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7642 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7643 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7645 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7646 nir_print_instr(&instr
->instr
, stderr
);
7647 fprintf(stderr
, "\n");
7652 case nir_intrinsic_load_sample_id
: {
7653 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7654 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7657 case nir_intrinsic_load_sample_mask_in
: {
7658 visit_load_sample_mask_in(ctx
, instr
);
7661 case nir_intrinsic_read_first_invocation
: {
7662 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7663 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7664 if (src
.regClass() == v1
) {
7666 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7668 } else if (src
.regClass() == v2
) {
7669 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7670 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7671 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7672 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7673 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7674 emit_split_vector(ctx
, dst
, 2);
7675 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7676 assert(src
.regClass() == bld
.lm
);
7677 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7678 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7679 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7680 } else if (src
.regClass() == s1
) {
7681 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7682 } else if (src
.regClass() == s2
) {
7683 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7685 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7686 nir_print_instr(&instr
->instr
, stderr
);
7687 fprintf(stderr
, "\n");
7691 case nir_intrinsic_vote_all
: {
7692 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7693 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7694 assert(src
.regClass() == bld
.lm
);
7695 assert(dst
.regClass() == bld
.lm
);
7697 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7698 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7699 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7702 case nir_intrinsic_vote_any
: {
7703 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7704 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7705 assert(src
.regClass() == bld
.lm
);
7706 assert(dst
.regClass() == bld
.lm
);
7708 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7709 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7712 case nir_intrinsic_reduce
:
7713 case nir_intrinsic_inclusive_scan
:
7714 case nir_intrinsic_exclusive_scan
: {
7715 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7716 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7717 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7718 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7719 nir_intrinsic_cluster_size(instr
) : 0;
7720 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7722 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7723 emit_uniform_subgroup(ctx
, instr
, src
);
7724 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7725 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7727 else if (op
== nir_op_iadd
)
7729 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7731 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7733 switch (instr
->intrinsic
) {
7734 case nir_intrinsic_reduce
:
7735 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7737 case nir_intrinsic_exclusive_scan
:
7738 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7740 case nir_intrinsic_inclusive_scan
:
7741 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7746 } else if (cluster_size
== 1) {
7747 bld
.copy(Definition(dst
), src
);
7749 src
= as_vgpr(ctx
, src
);
7753 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7768 unreachable("unknown reduction op");
7773 switch (instr
->intrinsic
) {
7774 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7775 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7776 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7778 unreachable("unknown reduce intrinsic");
7781 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7782 reduce
->operands
[0] = Operand(src
);
7783 // filled in by aco_reduce_assign.cpp, used internally as part of the
7785 assert(dst
.size() == 1 || dst
.size() == 2);
7786 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7787 reduce
->operands
[2] = Operand(v1
.as_linear());
7789 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7790 reduce
->definitions
[0] = Definition(tmp_dst
);
7791 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7792 reduce
->definitions
[2] = Definition();
7793 reduce
->definitions
[3] = Definition(scc
, s1
);
7794 reduce
->definitions
[4] = Definition();
7795 reduce
->reduce_op
= reduce_op
;
7796 reduce
->cluster_size
= cluster_size
;
7797 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7799 emit_wqm(ctx
, tmp_dst
, dst
);
7803 case nir_intrinsic_quad_broadcast
: {
7804 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7805 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7806 emit_uniform_subgroup(ctx
, instr
, src
);
7808 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7809 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7810 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7812 if (instr
->dest
.ssa
.bit_size
== 1) {
7813 assert(src
.regClass() == bld
.lm
);
7814 assert(dst
.regClass() == bld
.lm
);
7815 uint32_t half_mask
= 0x11111111u
<< lane
;
7816 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7817 Temp tmp
= bld
.tmp(bld
.lm
);
7818 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7819 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7820 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7821 emit_wqm(ctx
, tmp
, dst
);
7822 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7823 if (ctx
->program
->chip_class
>= GFX8
)
7824 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7826 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7827 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7828 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7829 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7830 if (ctx
->program
->chip_class
>= GFX8
) {
7831 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7832 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7834 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7835 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7837 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7838 emit_split_vector(ctx
, dst
, 2);
7840 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7841 nir_print_instr(&instr
->instr
, stderr
);
7842 fprintf(stderr
, "\n");
7847 case nir_intrinsic_quad_swap_horizontal
:
7848 case nir_intrinsic_quad_swap_vertical
:
7849 case nir_intrinsic_quad_swap_diagonal
:
7850 case nir_intrinsic_quad_swizzle_amd
: {
7851 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7852 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7853 emit_uniform_subgroup(ctx
, instr
, src
);
7856 uint16_t dpp_ctrl
= 0;
7857 switch (instr
->intrinsic
) {
7858 case nir_intrinsic_quad_swap_horizontal
:
7859 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7861 case nir_intrinsic_quad_swap_vertical
:
7862 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7864 case nir_intrinsic_quad_swap_diagonal
:
7865 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7867 case nir_intrinsic_quad_swizzle_amd
:
7868 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7873 if (ctx
->program
->chip_class
< GFX8
)
7874 dpp_ctrl
|= (1 << 15);
7876 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7877 if (instr
->dest
.ssa
.bit_size
== 1) {
7878 assert(src
.regClass() == bld
.lm
);
7879 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7880 if (ctx
->program
->chip_class
>= GFX8
)
7881 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7883 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7884 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7885 emit_wqm(ctx
, tmp
, dst
);
7886 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7888 if (ctx
->program
->chip_class
>= GFX8
)
7889 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7891 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7892 emit_wqm(ctx
, tmp
, dst
);
7893 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7894 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7895 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7896 if (ctx
->program
->chip_class
>= GFX8
) {
7897 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7898 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7900 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7901 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7903 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7904 emit_split_vector(ctx
, dst
, 2);
7906 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7907 nir_print_instr(&instr
->instr
, stderr
);
7908 fprintf(stderr
, "\n");
7912 case nir_intrinsic_masked_swizzle_amd
: {
7913 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7914 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7915 emit_uniform_subgroup(ctx
, instr
, src
);
7918 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7919 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7920 if (dst
.regClass() == v1
) {
7922 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7924 } else if (dst
.regClass() == v2
) {
7925 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7926 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7927 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7928 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7929 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7930 emit_split_vector(ctx
, dst
, 2);
7932 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7933 nir_print_instr(&instr
->instr
, stderr
);
7934 fprintf(stderr
, "\n");
7938 case nir_intrinsic_write_invocation_amd
: {
7939 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7940 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7941 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7942 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7943 if (dst
.regClass() == v1
) {
7944 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7945 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7946 } else if (dst
.regClass() == v2
) {
7947 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7948 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7949 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7950 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7951 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7952 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7953 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7954 emit_split_vector(ctx
, dst
, 2);
7956 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7957 nir_print_instr(&instr
->instr
, stderr
);
7958 fprintf(stderr
, "\n");
7962 case nir_intrinsic_mbcnt_amd
: {
7963 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7964 RegClass rc
= RegClass(src
.type(), 1);
7965 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7966 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7967 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7968 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7969 emit_wqm(ctx
, wqm_tmp
, dst
);
7972 case nir_intrinsic_load_helper_invocation
: {
7973 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7974 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7975 ctx
->block
->kind
|= block_kind_needs_lowering
;
7976 ctx
->program
->needs_exact
= true;
7979 case nir_intrinsic_is_helper_invocation
: {
7980 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7981 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7982 ctx
->block
->kind
|= block_kind_needs_lowering
;
7983 ctx
->program
->needs_exact
= true;
7986 case nir_intrinsic_demote
:
7987 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7989 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7990 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7991 ctx
->block
->kind
|= block_kind_uses_demote
;
7992 ctx
->program
->needs_exact
= true;
7994 case nir_intrinsic_demote_if
: {
7995 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7996 assert(src
.regClass() == bld
.lm
);
7997 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7998 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8000 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8001 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8002 ctx
->block
->kind
|= block_kind_uses_demote
;
8003 ctx
->program
->needs_exact
= true;
8006 case nir_intrinsic_first_invocation
: {
8007 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8008 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8011 case nir_intrinsic_shader_clock
:
8012 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
8013 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8015 case nir_intrinsic_load_vertex_id_zero_base
: {
8016 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8017 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8020 case nir_intrinsic_load_first_vertex
: {
8021 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8022 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8025 case nir_intrinsic_load_base_instance
: {
8026 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8027 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8030 case nir_intrinsic_load_instance_id
: {
8031 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8032 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8035 case nir_intrinsic_load_draw_id
: {
8036 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8037 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8040 case nir_intrinsic_load_invocation_id
: {
8041 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8043 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8044 if (ctx
->options
->chip_class
>= GFX10
)
8045 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8047 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8048 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8049 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8050 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8052 unreachable("Unsupported stage for load_invocation_id");
8057 case nir_intrinsic_load_primitive_id
: {
8058 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8060 switch (ctx
->shader
->info
.stage
) {
8061 case MESA_SHADER_GEOMETRY
:
8062 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8064 case MESA_SHADER_TESS_CTRL
:
8065 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8067 case MESA_SHADER_TESS_EVAL
:
8068 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8071 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8076 case nir_intrinsic_load_patch_vertices_in
: {
8077 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8078 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8080 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8081 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8084 case nir_intrinsic_emit_vertex_with_counter
: {
8085 visit_emit_vertex_with_counter(ctx
, instr
);
8088 case nir_intrinsic_end_primitive_with_counter
: {
8089 unsigned stream
= nir_intrinsic_stream_id(instr
);
8090 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8093 case nir_intrinsic_set_vertex_count
: {
8094 /* unused, the HW keeps track of this for us */
8098 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8099 nir_print_instr(&instr
->instr
, stderr
);
8100 fprintf(stderr
, "\n");
8108 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8109 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8110 enum glsl_base_type
*stype
)
8112 nir_deref_instr
*texture_deref_instr
= NULL
;
8113 nir_deref_instr
*sampler_deref_instr
= NULL
;
8116 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8117 switch (instr
->src
[i
].src_type
) {
8118 case nir_tex_src_texture_deref
:
8119 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8121 case nir_tex_src_sampler_deref
:
8122 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8124 case nir_tex_src_plane
:
8125 plane
= nir_src_as_int(instr
->src
[i
].src
);
8132 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8134 if (!sampler_deref_instr
)
8135 sampler_deref_instr
= texture_deref_instr
;
8138 assert(instr
->op
!= nir_texop_txf_ms
&&
8139 instr
->op
!= nir_texop_samples_identical
);
8140 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8141 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8142 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8143 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8144 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8145 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8147 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8150 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8152 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8153 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8154 Builder
bld(ctx
->program
, ctx
->block
);
8156 /* to avoid unnecessary moves, we split and recombine sampler and image */
8157 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8158 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8159 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8160 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8161 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8162 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8163 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8164 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8166 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8167 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8168 img
[0], img
[1], img
[2], img
[3],
8169 img
[4], img
[5], img
[6], img
[7]);
8170 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8171 samp
[0], samp
[1], samp
[2], samp
[3]);
8174 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8175 instr
->op
== nir_texop_samples_identical
))
8176 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8179 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8180 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8182 Builder
bld(ctx
->program
, ctx
->block
);
8184 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8185 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8186 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8188 Operand
neg_one(0xbf800000u
);
8189 Operand
one(0x3f800000u
);
8190 Operand
two(0x40000000u
);
8191 Operand
four(0x40800000u
);
8193 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8194 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8195 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8197 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8198 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8199 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8200 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8203 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8204 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8205 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8207 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8210 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8211 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8212 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8215 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8216 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8218 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8219 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8222 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8224 Builder
bld(ctx
->program
, ctx
->block
);
8225 Temp ma
, tc
, sc
, id
;
8228 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8230 // see comment in ac_prepare_cube_coords()
8231 if (ctx
->options
->chip_class
<= GFX8
)
8232 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8235 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8237 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8238 vop3a
->operands
[0] = Operand(ma
);
8239 vop3a
->abs
[0] = true;
8240 Temp invma
= bld
.tmp(v1
);
8241 vop3a
->definitions
[0] = Definition(invma
);
8242 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8244 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8246 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8248 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8250 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8252 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8255 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8256 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8258 for (unsigned i
= 0; i
< 2; i
++) {
8259 // see comment in ac_prepare_cube_coords()
8261 Temp deriv_sc
, deriv_tc
;
8262 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8263 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8265 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8267 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8268 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8269 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8270 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8271 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8272 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8273 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8276 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8277 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8281 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8288 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8290 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8292 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8293 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8296 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8297 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8298 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8302 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8304 Builder
bld(ctx
->program
, ctx
->block
);
8305 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8306 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8307 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8308 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8309 std::vector
<Temp
> coords
;
8310 std::vector
<Temp
> derivs
;
8311 nir_const_value
*sample_index_cv
= NULL
;
8312 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8313 enum glsl_base_type stype
;
8314 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8316 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8317 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8318 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8319 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8321 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8322 switch (instr
->src
[i
].src_type
) {
8323 case nir_tex_src_coord
: {
8324 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8325 for (unsigned i
= 0; i
< coord
.size(); i
++)
8326 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8329 case nir_tex_src_bias
:
8330 if (instr
->op
== nir_texop_txb
) {
8331 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8335 case nir_tex_src_lod
: {
8336 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8338 if (val
&& val
->f32
<= 0.0) {
8341 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8346 case nir_tex_src_comparator
:
8347 if (instr
->is_shadow
) {
8348 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8352 case nir_tex_src_offset
:
8353 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8354 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8357 case nir_tex_src_ddx
:
8358 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8361 case nir_tex_src_ddy
:
8362 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8365 case nir_tex_src_ms_index
:
8366 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8367 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8368 has_sample_index
= true;
8370 case nir_tex_src_texture_offset
:
8371 case nir_tex_src_sampler_offset
:
8377 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8378 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8380 if (instr
->op
== nir_texop_texture_samples
) {
8381 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8383 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8384 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8385 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8386 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8388 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8389 samples
, Operand(1u), bld
.scc(is_msaa
));
8393 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8394 aco_ptr
<Instruction
> tmp_instr
;
8395 Temp acc
, pack
= Temp();
8397 uint32_t pack_const
= 0;
8398 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8399 if (!const_offset
[i
])
8401 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8404 if (offset
.type() == RegType::sgpr
) {
8405 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8406 if (const_offset
[i
])
8409 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8410 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8413 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8416 if (pack
== Temp()) {
8419 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8423 if (pack_const
&& pack
!= Temp())
8424 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8426 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8427 if (const_offset
[i
])
8430 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8431 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8434 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8437 if (pack
== Temp()) {
8440 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8444 if (pack_const
&& pack
!= Temp())
8445 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8447 if (pack_const
&& pack
== Temp())
8448 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8449 else if (pack
== Temp())
8455 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8456 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8458 /* pack derivatives */
8459 if (has_ddx
|| has_ddy
) {
8460 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8461 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8462 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8463 derivs
= {ddx
, zero
, ddy
, zero
};
8465 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8466 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8467 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8468 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8473 if (instr
->coord_components
> 1 &&
8474 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8476 instr
->op
!= nir_texop_txf
)
8477 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8479 if (instr
->coord_components
> 2 &&
8480 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8481 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8482 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8483 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8485 instr
->op
!= nir_texop_txf
&&
8486 instr
->op
!= nir_texop_txf_ms
&&
8487 instr
->op
!= nir_texop_fragment_fetch
&&
8488 instr
->op
!= nir_texop_fragment_mask_fetch
)
8489 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8491 if (ctx
->options
->chip_class
== GFX9
&&
8492 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8493 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8494 assert(coords
.size() > 0 && coords
.size() < 3);
8496 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8497 Operand((uint32_t) 0) :
8498 Operand((uint32_t) 0x3f000000)));
8501 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8503 if (instr
->op
== nir_texop_samples_identical
)
8504 resource
= fmask_ptr
;
8506 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8507 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8508 instr
->op
!= nir_texop_txs
&&
8509 instr
->op
!= nir_texop_fragment_fetch
&&
8510 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8511 assert(has_sample_index
);
8512 Operand
op(sample_index
);
8513 if (sample_index_cv
)
8514 op
= Operand(sample_index_cv
->u32
);
8515 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8518 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8519 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8520 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8521 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8526 /* Build tex instruction */
8527 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8528 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8529 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8531 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8534 /* gather4 selects the component by dmask and always returns vec4 */
8535 if (instr
->op
== nir_texop_tg4
) {
8536 assert(instr
->dest
.ssa
.num_components
== 4);
8537 if (instr
->is_shadow
)
8540 dmask
= 1 << instr
->component
;
8541 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8542 tmp_dst
= bld
.tmp(v4
);
8543 } else if (instr
->op
== nir_texop_samples_identical
) {
8544 tmp_dst
= bld
.tmp(v1
);
8545 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8546 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8549 aco_ptr
<MIMG_instruction
> tex
;
8550 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8552 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8554 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8555 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8558 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8559 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8561 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8562 tex
->operands
[0] = Operand(resource
);
8563 tex
->operands
[1] = Operand(s4
); /* no sampler */
8564 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8565 if (ctx
->options
->chip_class
== GFX9
&&
8566 instr
->op
== nir_texop_txs
&&
8567 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8569 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8570 } else if (instr
->op
== nir_texop_query_levels
) {
8571 tex
->dmask
= 1 << 3;
8576 tex
->definitions
[0] = Definition(tmp_dst
);
8578 tex
->can_reorder
= true;
8579 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8582 /* divide 3rd value by 6 by multiplying with magic number */
8583 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8584 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8585 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8586 assert(instr
->dest
.ssa
.num_components
== 3);
8587 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8588 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8589 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8590 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8595 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8599 Temp tg4_compare_cube_wa64
= Temp();
8601 if (tg4_integer_workarounds
) {
8602 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8603 tex
->operands
[0] = Operand(resource
);
8604 tex
->operands
[1] = Operand(s4
); /* no sampler */
8605 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8609 Temp size
= bld
.tmp(v2
);
8610 tex
->definitions
[0] = Definition(size
);
8611 tex
->can_reorder
= true;
8612 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8613 emit_split_vector(ctx
, size
, size
.size());
8616 for (unsigned i
= 0; i
< 2; i
++) {
8617 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8618 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8619 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8620 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8623 Temp new_coords
[2] = {
8624 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8625 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8628 if (tg4_integer_cube_workaround
) {
8629 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8630 Temp desc
[resource
.size()];
8631 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8632 Format::PSEUDO
, 1, resource
.size())};
8633 split
->operands
[0] = Operand(resource
);
8634 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8635 desc
[i
] = bld
.tmp(s1
);
8636 split
->definitions
[i
] = Definition(desc
[i
]);
8638 ctx
->block
->instructions
.emplace_back(std::move(split
));
8640 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8641 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8642 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8645 if (stype
== GLSL_TYPE_UINT
) {
8646 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8647 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8648 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8649 bld
.scc(compare_cube_wa
));
8651 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8652 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8653 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8654 bld
.scc(compare_cube_wa
));
8656 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8657 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8659 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8661 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8662 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8663 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8665 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8666 Format::PSEUDO
, resource
.size(), 1)};
8667 for (unsigned i
= 0; i
< resource
.size(); i
++)
8668 vec
->operands
[i
] = Operand(desc
[i
]);
8669 resource
= bld
.tmp(resource
.regClass());
8670 vec
->definitions
[0] = Definition(resource
);
8671 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8673 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8674 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8675 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8676 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8678 coords
[0] = new_coords
[0];
8679 coords
[1] = new_coords
[1];
8682 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8683 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8685 assert(coords
.size() == 1);
8686 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8690 op
= aco_opcode::buffer_load_format_x
; break;
8692 op
= aco_opcode::buffer_load_format_xy
; break;
8694 op
= aco_opcode::buffer_load_format_xyz
; break;
8696 op
= aco_opcode::buffer_load_format_xyzw
; break;
8698 unreachable("Tex instruction loads more than 4 components.");
8701 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8702 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8705 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8707 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8708 mubuf
->operands
[0] = Operand(resource
);
8709 mubuf
->operands
[1] = Operand(coords
[0]);
8710 mubuf
->operands
[2] = Operand((uint32_t) 0);
8711 mubuf
->definitions
[0] = Definition(tmp_dst
);
8712 mubuf
->idxen
= true;
8713 mubuf
->can_reorder
= true;
8714 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8716 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8720 /* gather MIMG address components */
8721 std::vector
<Temp
> args
;
8723 args
.emplace_back(offset
);
8725 args
.emplace_back(bias
);
8727 args
.emplace_back(compare
);
8729 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8731 args
.insert(args
.end(), coords
.begin(), coords
.end());
8732 if (has_sample_index
)
8733 args
.emplace_back(sample_index
);
8735 args
.emplace_back(lod
);
8737 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8738 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8739 vec
->definitions
[0] = Definition(arg
);
8740 for (unsigned i
= 0; i
< args
.size(); i
++)
8741 vec
->operands
[i
] = Operand(args
[i
]);
8742 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8745 if (instr
->op
== nir_texop_txf
||
8746 instr
->op
== nir_texop_txf_ms
||
8747 instr
->op
== nir_texop_samples_identical
||
8748 instr
->op
== nir_texop_fragment_fetch
||
8749 instr
->op
== nir_texop_fragment_mask_fetch
) {
8750 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8751 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8752 tex
->operands
[0] = Operand(resource
);
8753 tex
->operands
[1] = Operand(s4
); /* no sampler */
8754 tex
->operands
[2] = Operand(arg
);
8759 tex
->definitions
[0] = Definition(tmp_dst
);
8760 tex
->can_reorder
= true;
8761 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8763 if (instr
->op
== nir_texop_samples_identical
) {
8764 assert(dmask
== 1 && dst
.regClass() == v1
);
8765 assert(dst
.id() != tmp_dst
.id());
8767 Temp tmp
= bld
.tmp(bld
.lm
);
8768 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8769 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8772 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8777 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8778 aco_opcode opcode
= aco_opcode::image_sample
;
8779 if (has_offset
) { /* image_sample_*_o */
8781 opcode
= aco_opcode::image_sample_c_o
;
8783 opcode
= aco_opcode::image_sample_c_d_o
;
8785 opcode
= aco_opcode::image_sample_c_b_o
;
8787 opcode
= aco_opcode::image_sample_c_lz_o
;
8789 opcode
= aco_opcode::image_sample_c_l_o
;
8791 opcode
= aco_opcode::image_sample_o
;
8793 opcode
= aco_opcode::image_sample_d_o
;
8795 opcode
= aco_opcode::image_sample_b_o
;
8797 opcode
= aco_opcode::image_sample_lz_o
;
8799 opcode
= aco_opcode::image_sample_l_o
;
8801 } else { /* no offset */
8803 opcode
= aco_opcode::image_sample_c
;
8805 opcode
= aco_opcode::image_sample_c_d
;
8807 opcode
= aco_opcode::image_sample_c_b
;
8809 opcode
= aco_opcode::image_sample_c_lz
;
8811 opcode
= aco_opcode::image_sample_c_l
;
8813 opcode
= aco_opcode::image_sample
;
8815 opcode
= aco_opcode::image_sample_d
;
8817 opcode
= aco_opcode::image_sample_b
;
8819 opcode
= aco_opcode::image_sample_lz
;
8821 opcode
= aco_opcode::image_sample_l
;
8825 if (instr
->op
== nir_texop_tg4
) {
8827 opcode
= aco_opcode::image_gather4_lz_o
;
8829 opcode
= aco_opcode::image_gather4_c_lz_o
;
8831 opcode
= aco_opcode::image_gather4_lz
;
8833 opcode
= aco_opcode::image_gather4_c_lz
;
8835 } else if (instr
->op
== nir_texop_lod
) {
8836 opcode
= aco_opcode::image_get_lod
;
8839 /* we don't need the bias, sample index, compare value or offset to be
8840 * computed in WQM but if the p_create_vector copies the coordinates, then it
8841 * needs to be in WQM */
8842 if (ctx
->stage
== fragment_fs
&&
8843 !has_derivs
&& !has_lod
&& !level_zero
&&
8844 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8845 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8846 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8848 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8849 tex
->operands
[0] = Operand(resource
);
8850 tex
->operands
[1] = Operand(sampler
);
8851 tex
->operands
[2] = Operand(arg
);
8855 tex
->definitions
[0] = Definition(tmp_dst
);
8856 tex
->can_reorder
= true;
8857 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8859 if (tg4_integer_cube_workaround
) {
8860 assert(tmp_dst
.id() != dst
.id());
8861 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8863 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8865 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8866 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8868 if (stype
== GLSL_TYPE_UINT
)
8869 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8871 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8872 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8874 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8875 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8876 val
[0], val
[1], val
[2], val
[3]);
8878 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8879 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8884 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8886 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8887 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8888 return Operand(tmp
.regClass());
8890 return Operand(tmp
);
8893 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8895 aco_ptr
<Pseudo_instruction
> phi
;
8896 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8897 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8899 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8900 logical
|= ctx
->block
->kind
& block_kind_merge
;
8901 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8903 /* we want a sorted list of sources, since the predecessor list is also sorted */
8904 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8905 nir_foreach_phi_src(src
, instr
)
8906 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8908 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8909 unsigned num_operands
= 0;
8910 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8911 unsigned num_defined
= 0;
8912 unsigned cur_pred_idx
= 0;
8913 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8914 if (cur_pred_idx
< preds
.size()) {
8915 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8916 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8917 unsigned skipped
= 0;
8918 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8920 if (cur_pred_idx
+ skipped
< preds
.size()) {
8921 for (unsigned i
= 0; i
< skipped
; i
++)
8922 operands
[num_operands
++] = Operand(dst
.regClass());
8923 cur_pred_idx
+= skipped
;
8928 /* Handle missing predecessors at the end. This shouldn't happen with loop
8929 * headers and we can't ignore these sources for loop header phis. */
8930 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8933 Operand op
= get_phi_operand(ctx
, src
.second
);
8934 operands
[num_operands
++] = op
;
8935 num_defined
+= !op
.isUndefined();
8937 /* handle block_kind_continue_or_break at loop exit blocks */
8938 while (cur_pred_idx
++ < preds
.size())
8939 operands
[num_operands
++] = Operand(dst
.regClass());
8941 /* If the loop ends with a break, still add a linear continue edge in case
8942 * that break is divergent or continue_or_break is used. We'll either remove
8943 * this operand later in visit_loop() if it's not necessary or replace the
8944 * undef with something correct. */
8945 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8946 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8947 nir_block
*last
= nir_loop_last_block(loop
);
8948 if (last
->successors
[0] != instr
->instr
.block
)
8949 operands
[num_operands
++] = Operand(RegClass());
8952 if (num_defined
== 0) {
8953 Builder
bld(ctx
->program
, ctx
->block
);
8954 if (dst
.regClass() == s1
) {
8955 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8956 } else if (dst
.regClass() == v1
) {
8957 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8959 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8960 for (unsigned i
= 0; i
< dst
.size(); i
++)
8961 vec
->operands
[i
] = Operand(0u);
8962 vec
->definitions
[0] = Definition(dst
);
8963 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8968 /* we can use a linear phi in some cases if one src is undef */
8969 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8970 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8972 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8973 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8974 assert(invert
->kind
& block_kind_invert
);
8976 unsigned then_block
= invert
->linear_preds
[0];
8978 Block
* insert_block
= NULL
;
8979 for (unsigned i
= 0; i
< num_operands
; i
++) {
8980 Operand op
= operands
[i
];
8981 if (op
.isUndefined())
8983 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8984 phi
->operands
[0] = op
;
8987 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8988 phi
->operands
[1] = Operand(dst
.regClass());
8989 phi
->definitions
[0] = Definition(dst
);
8990 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8994 /* try to scalarize vector phis */
8995 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8996 // TODO: scalarize linear phis on divergent ifs
8997 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8998 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8999 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9000 Operand src
= operands
[i
];
9001 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9002 can_scalarize
= false;
9004 if (can_scalarize
) {
9005 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9006 assert(dst
.size() % num_components
== 0);
9007 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9009 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9010 for (unsigned k
= 0; k
< num_components
; k
++) {
9011 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9012 for (unsigned i
= 0; i
< num_operands
; i
++) {
9013 Operand src
= operands
[i
];
9014 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9016 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9017 phi
->definitions
[0] = Definition(phi_dst
);
9018 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9019 new_vec
[k
] = phi_dst
;
9020 vec
->operands
[k
] = Operand(phi_dst
);
9022 vec
->definitions
[0] = Definition(dst
);
9023 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9024 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9029 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9030 for (unsigned i
= 0; i
< num_operands
; i
++)
9031 phi
->operands
[i
] = operands
[i
];
9032 phi
->definitions
[0] = Definition(dst
);
9033 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9037 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9039 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9041 assert(dst
.type() == RegType::sgpr
);
9043 if (dst
.size() == 1) {
9044 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9046 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9047 for (unsigned i
= 0; i
< dst
.size(); i
++)
9048 vec
->operands
[i
] = Operand(0u);
9049 vec
->definitions
[0] = Definition(dst
);
9050 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9054 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9056 Builder
bld(ctx
->program
, ctx
->block
);
9057 Block
*logical_target
;
9058 append_logical_end(ctx
->block
);
9059 unsigned idx
= ctx
->block
->index
;
9061 switch (instr
->type
) {
9062 case nir_jump_break
:
9063 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9064 add_logical_edge(idx
, logical_target
);
9065 ctx
->block
->kind
|= block_kind_break
;
9067 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9068 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9069 /* uniform break - directly jump out of the loop */
9070 ctx
->block
->kind
|= block_kind_uniform
;
9071 ctx
->cf_info
.has_branch
= true;
9072 bld
.branch(aco_opcode::p_branch
);
9073 add_linear_edge(idx
, logical_target
);
9076 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9077 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9079 case nir_jump_continue
:
9080 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9081 add_logical_edge(idx
, logical_target
);
9082 ctx
->block
->kind
|= block_kind_continue
;
9084 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9085 /* for potential uniform breaks after this continue,
9086 we must ensure that they are handled correctly */
9087 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9088 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9089 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9091 /* uniform continue - directly jump to the loop header */
9092 ctx
->block
->kind
|= block_kind_uniform
;
9093 ctx
->cf_info
.has_branch
= true;
9094 bld
.branch(aco_opcode::p_branch
);
9095 add_linear_edge(idx
, logical_target
);
9100 fprintf(stderr
, "Unknown NIR jump instr: ");
9101 nir_print_instr(&instr
->instr
, stderr
);
9102 fprintf(stderr
, "\n");
9106 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9107 ctx
->cf_info
.exec_potentially_empty_break
= true;
9108 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9111 /* remove critical edges from linear CFG */
9112 bld
.branch(aco_opcode::p_branch
);
9113 Block
* break_block
= ctx
->program
->create_and_insert_block();
9114 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9115 break_block
->kind
|= block_kind_uniform
;
9116 add_linear_edge(idx
, break_block
);
9117 /* the loop_header pointer might be invalidated by this point */
9118 if (instr
->type
== nir_jump_continue
)
9119 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9120 add_linear_edge(break_block
->index
, logical_target
);
9121 bld
.reset(break_block
);
9122 bld
.branch(aco_opcode::p_branch
);
9124 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9125 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9126 add_linear_edge(idx
, continue_block
);
9127 append_logical_start(continue_block
);
9128 ctx
->block
= continue_block
;
9132 void visit_block(isel_context
*ctx
, nir_block
*block
)
9134 nir_foreach_instr(instr
, block
) {
9135 switch (instr
->type
) {
9136 case nir_instr_type_alu
:
9137 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9139 case nir_instr_type_load_const
:
9140 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9142 case nir_instr_type_intrinsic
:
9143 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9145 case nir_instr_type_tex
:
9146 visit_tex(ctx
, nir_instr_as_tex(instr
));
9148 case nir_instr_type_phi
:
9149 visit_phi(ctx
, nir_instr_as_phi(instr
));
9151 case nir_instr_type_ssa_undef
:
9152 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9154 case nir_instr_type_deref
:
9156 case nir_instr_type_jump
:
9157 visit_jump(ctx
, nir_instr_as_jump(instr
));
9160 fprintf(stderr
, "Unknown NIR instr type: ");
9161 nir_print_instr(instr
, stderr
);
9162 fprintf(stderr
, "\n");
9167 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9168 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9173 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9174 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9176 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9177 RegClass rc
= vals
[0].regClass();
9179 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9181 unsigned next_pred
= 1;
9183 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9184 Block
& block
= ctx
->program
->blocks
[idx
];
9185 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9186 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9190 if (block
.kind
& block_kind_continue
) {
9191 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9196 bool all_same
= true;
9197 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9198 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9202 val
= vals
[block
.linear_preds
[0] - first
];
9204 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9205 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9206 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9207 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9208 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9209 phi
->definitions
[0] = Definition(val
.getTemp());
9210 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9212 vals
[idx
- first
] = val
;
9215 return vals
[last
- first
];
9218 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9220 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9221 append_logical_end(ctx
->block
);
9222 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9223 Builder
bld(ctx
->program
, ctx
->block
);
9224 bld
.branch(aco_opcode::p_branch
);
9225 unsigned loop_preheader_idx
= ctx
->block
->index
;
9227 Block loop_exit
= Block();
9228 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9229 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9231 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9232 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9233 loop_header
->kind
|= block_kind_loop_header
;
9234 add_edge(loop_preheader_idx
, loop_header
);
9235 ctx
->block
= loop_header
;
9237 /* emit loop body */
9238 unsigned loop_header_idx
= loop_header
->index
;
9239 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9240 append_logical_start(ctx
->block
);
9241 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9243 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9244 if (!ctx
->cf_info
.has_branch
) {
9245 append_logical_end(ctx
->block
);
9246 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9247 /* Discards can result in code running with an empty exec mask.
9248 * This would result in divergent breaks not ever being taken. As a
9249 * workaround, break the loop when the loop mask is empty instead of
9250 * always continuing. */
9251 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9252 unsigned block_idx
= ctx
->block
->index
;
9254 /* create helper blocks to avoid critical edges */
9255 Block
*break_block
= ctx
->program
->create_and_insert_block();
9256 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9257 break_block
->kind
= block_kind_uniform
;
9258 bld
.reset(break_block
);
9259 bld
.branch(aco_opcode::p_branch
);
9260 add_linear_edge(block_idx
, break_block
);
9261 add_linear_edge(break_block
->index
, &loop_exit
);
9263 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9264 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9265 continue_block
->kind
= block_kind_uniform
;
9266 bld
.reset(continue_block
);
9267 bld
.branch(aco_opcode::p_branch
);
9268 add_linear_edge(block_idx
, continue_block
);
9269 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9271 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9272 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9273 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9275 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9276 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9277 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9279 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9282 bld
.reset(ctx
->block
);
9283 bld
.branch(aco_opcode::p_branch
);
9286 /* Fixup phis in loop header from unreachable blocks.
9287 * has_branch/has_divergent_branch also indicates if the loop ends with a
9288 * break/continue instruction, but we don't emit those if unreachable=true */
9290 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9291 bool linear
= ctx
->cf_info
.has_branch
;
9292 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9293 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9294 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9295 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9296 /* the last operand should be the one that needs to be removed */
9297 instr
->operands
.pop_back();
9298 } else if (!is_phi(instr
)) {
9304 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9305 * and the previous one shouldn't both happen at once because a break in the
9306 * merge block would get CSE'd */
9307 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9308 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9309 Operand vals
[num_vals
];
9310 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9311 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9312 if (ctx
->cf_info
.has_branch
)
9313 instr
->operands
.pop_back();
9315 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9316 } else if (!is_phi(instr
)) {
9322 ctx
->cf_info
.has_branch
= false;
9324 // TODO: if the loop has not a single exit, we must add one °°
9325 /* emit loop successor block */
9326 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9327 append_logical_start(ctx
->block
);
9330 // TODO: check if it is beneficial to not branch on continues
9331 /* trim linear phis in loop header */
9332 for (auto&& instr
: loop_entry
->instructions
) {
9333 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9334 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9335 new_phi
->definitions
[0] = instr
->definitions
[0];
9336 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9337 new_phi
->operands
[i
] = instr
->operands
[i
];
9338 /* check that the remaining operands are all the same */
9339 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9340 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9341 instr
.swap(new_phi
);
9342 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9351 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9355 append_logical_end(ctx
->block
);
9356 ctx
->block
->kind
|= block_kind_branch
;
9358 /* branch to linear then block */
9359 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9360 aco_ptr
<Pseudo_branch_instruction
> branch
;
9361 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9362 branch
->operands
[0] = Operand(cond
);
9363 ctx
->block
->instructions
.push_back(std::move(branch
));
9365 ic
->BB_if_idx
= ctx
->block
->index
;
9366 ic
->BB_invert
= Block();
9367 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9368 /* Invert blocks are intentionally not marked as top level because they
9369 * are not part of the logical cfg. */
9370 ic
->BB_invert
.kind
|= block_kind_invert
;
9371 ic
->BB_endif
= Block();
9372 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9373 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9375 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9376 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9377 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9378 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9379 ctx
->cf_info
.parent_if
.is_divergent
= true;
9381 /* divergent branches use cbranch_execz */
9382 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9383 ctx
->cf_info
.exec_potentially_empty_break
= false;
9384 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9386 /** emit logical then block */
9387 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9388 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9389 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9390 ctx
->block
= BB_then_logical
;
9391 append_logical_start(BB_then_logical
);
9394 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9396 Block
*BB_then_logical
= ctx
->block
;
9397 append_logical_end(BB_then_logical
);
9398 /* branch from logical then block to invert block */
9399 aco_ptr
<Pseudo_branch_instruction
> branch
;
9400 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9401 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9402 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9403 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9404 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9405 BB_then_logical
->kind
|= block_kind_uniform
;
9406 assert(!ctx
->cf_info
.has_branch
);
9407 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9408 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9410 /** emit linear then block */
9411 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9412 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9413 BB_then_linear
->kind
|= block_kind_uniform
;
9414 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9415 /* branch from linear then block to invert block */
9416 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9417 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9418 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9420 /** emit invert merge block */
9421 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9422 ic
->invert_idx
= ctx
->block
->index
;
9424 /* branch to linear else block (skip else) */
9425 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9426 branch
->operands
[0] = Operand(ic
->cond
);
9427 ctx
->block
->instructions
.push_back(std::move(branch
));
9429 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9430 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9431 ic
->exec_potentially_empty_break_depth_old
=
9432 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9433 /* divergent branches use cbranch_execz */
9434 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9435 ctx
->cf_info
.exec_potentially_empty_break
= false;
9436 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9438 /** emit logical else block */
9439 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9440 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9441 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9442 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9443 ctx
->block
= BB_else_logical
;
9444 append_logical_start(BB_else_logical
);
9447 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9449 Block
*BB_else_logical
= ctx
->block
;
9450 append_logical_end(BB_else_logical
);
9452 /* branch from logical else block to endif block */
9453 aco_ptr
<Pseudo_branch_instruction
> branch
;
9454 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9455 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9456 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9457 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9458 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9459 BB_else_logical
->kind
|= block_kind_uniform
;
9461 assert(!ctx
->cf_info
.has_branch
);
9462 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9465 /** emit linear else block */
9466 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9467 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9468 BB_else_linear
->kind
|= block_kind_uniform
;
9469 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9471 /* branch from linear else block to endif block */
9472 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9473 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9474 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9477 /** emit endif merge block */
9478 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9479 append_logical_start(ctx
->block
);
9482 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9483 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9484 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9485 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9486 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9487 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9488 !ctx
->cf_info
.parent_if
.is_divergent
) {
9489 ctx
->cf_info
.exec_potentially_empty_break
= false;
9490 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9492 /* uniform control flow never has an empty exec-mask */
9493 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9494 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9495 ctx
->cf_info
.exec_potentially_empty_break
= false;
9496 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9500 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9502 assert(cond
.regClass() == s1
);
9504 append_logical_end(ctx
->block
);
9505 ctx
->block
->kind
|= block_kind_uniform
;
9507 aco_ptr
<Pseudo_branch_instruction
> branch
;
9508 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9509 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9510 branch
->operands
[0] = Operand(cond
);
9511 branch
->operands
[0].setFixed(scc
);
9512 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9514 ic
->BB_if_idx
= ctx
->block
->index
;
9515 ic
->BB_endif
= Block();
9516 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9517 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9519 ctx
->cf_info
.has_branch
= false;
9520 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9522 /** emit then block */
9523 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9524 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9525 add_edge(ic
->BB_if_idx
, BB_then
);
9526 append_logical_start(BB_then
);
9527 ctx
->block
= BB_then
;
9530 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9532 Block
*BB_then
= ctx
->block
;
9534 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9535 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9537 if (!ic
->uniform_has_then_branch
) {
9538 append_logical_end(BB_then
);
9539 /* branch from then block to endif block */
9540 aco_ptr
<Pseudo_branch_instruction
> branch
;
9541 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9542 BB_then
->instructions
.emplace_back(std::move(branch
));
9543 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9544 if (!ic
->then_branch_divergent
)
9545 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9546 BB_then
->kind
|= block_kind_uniform
;
9549 ctx
->cf_info
.has_branch
= false;
9550 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9552 /** emit else block */
9553 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9554 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9555 add_edge(ic
->BB_if_idx
, BB_else
);
9556 append_logical_start(BB_else
);
9557 ctx
->block
= BB_else
;
9560 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9562 Block
*BB_else
= ctx
->block
;
9564 if (!ctx
->cf_info
.has_branch
) {
9565 append_logical_end(BB_else
);
9566 /* branch from then block to endif block */
9567 aco_ptr
<Pseudo_branch_instruction
> branch
;
9568 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9569 BB_else
->instructions
.emplace_back(std::move(branch
));
9570 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9571 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9572 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9573 BB_else
->kind
|= block_kind_uniform
;
9576 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9577 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9579 /** emit endif merge block */
9580 if (!ctx
->cf_info
.has_branch
) {
9581 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9582 append_logical_start(ctx
->block
);
9586 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9588 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9589 Builder
bld(ctx
->program
, ctx
->block
);
9590 aco_ptr
<Pseudo_branch_instruction
> branch
;
9593 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9595 * Uniform conditionals are represented in the following way*) :
9597 * The linear and logical CFG:
9600 * BB_THEN (logical) BB_ELSE (logical)
9604 * *) Exceptions may be due to break and continue statements within loops
9605 * If a break/continue happens within uniform control flow, it branches
9606 * to the loop exit/entry block. Otherwise, it branches to the next
9610 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9611 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9612 cond
= bool_to_scalar_condition(ctx
, cond
);
9614 begin_uniform_if_then(ctx
, &ic
, cond
);
9615 visit_cf_list(ctx
, &if_stmt
->then_list
);
9617 begin_uniform_if_else(ctx
, &ic
);
9618 visit_cf_list(ctx
, &if_stmt
->else_list
);
9620 end_uniform_if(ctx
, &ic
);
9622 return !ctx
->cf_info
.has_branch
;
9623 } else { /* non-uniform condition */
9625 * To maintain a logical and linear CFG without critical edges,
9626 * non-uniform conditionals are represented in the following way*) :
9631 * BB_THEN (logical) BB_THEN (linear)
9633 * BB_INVERT (linear)
9635 * BB_ELSE (logical) BB_ELSE (linear)
9642 * BB_THEN (logical) BB_ELSE (logical)
9646 * *) Exceptions may be due to break and continue statements within loops
9649 begin_divergent_if_then(ctx
, &ic
, cond
);
9650 visit_cf_list(ctx
, &if_stmt
->then_list
);
9652 begin_divergent_if_else(ctx
, &ic
);
9653 visit_cf_list(ctx
, &if_stmt
->else_list
);
9655 end_divergent_if(ctx
, &ic
);
9661 static bool visit_cf_list(isel_context
*ctx
,
9662 struct exec_list
*list
)
9664 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9665 switch (node
->type
) {
9666 case nir_cf_node_block
:
9667 visit_block(ctx
, nir_cf_node_as_block(node
));
9669 case nir_cf_node_if
:
9670 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9673 case nir_cf_node_loop
:
9674 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9677 unreachable("unimplemented cf list type");
9683 static void create_null_export(isel_context
*ctx
)
9685 /* Some shader stages always need to have exports.
9686 * So when there is none, we need to add a null export.
9689 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9690 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9691 Builder
bld(ctx
->program
, ctx
->block
);
9692 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9693 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9696 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9698 assert(ctx
->stage
== vertex_vs
||
9699 ctx
->stage
== tess_eval_vs
||
9700 ctx
->stage
== gs_copy_vs
||
9701 ctx
->stage
== ngg_vertex_gs
||
9702 ctx
->stage
== ngg_tess_eval_gs
);
9704 int offset
= (ctx
->stage
& sw_tes
)
9705 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9706 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9707 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9708 if (!is_pos
&& !mask
)
9710 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9712 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9713 exp
->enabled_mask
= mask
;
9714 for (unsigned i
= 0; i
< 4; ++i
) {
9715 if (mask
& (1 << i
))
9716 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9718 exp
->operands
[i
] = Operand(v1
);
9720 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9721 * Setting valid_mask=1 prevents it and has no other effect.
9723 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9725 exp
->compressed
= false;
9727 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9729 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9730 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9735 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9737 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9738 exp
->enabled_mask
= 0;
9739 for (unsigned i
= 0; i
< 4; ++i
)
9740 exp
->operands
[i
] = Operand(v1
);
9741 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9742 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9743 exp
->enabled_mask
|= 0x1;
9745 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9746 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9747 exp
->enabled_mask
|= 0x4;
9749 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9750 if (ctx
->options
->chip_class
< GFX9
) {
9751 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9752 exp
->enabled_mask
|= 0x8;
9754 Builder
bld(ctx
->program
, ctx
->block
);
9756 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9757 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9758 if (exp
->operands
[2].isTemp())
9759 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9761 exp
->operands
[2] = Operand(out
);
9762 exp
->enabled_mask
|= 0x4;
9765 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9767 exp
->compressed
= false;
9768 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9769 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9772 static void create_export_phis(isel_context
*ctx
)
9774 /* Used when exports are needed, but the output temps are defined in a preceding block.
9775 * This function will set up phis in order to access the outputs in the next block.
9778 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9779 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9780 ctx
->block
->instructions
.pop_back();
9782 Builder
bld(ctx
->program
, ctx
->block
);
9784 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9785 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9786 for (unsigned i
= 0; i
< 4; ++i
) {
9787 if (!(mask
& (1 << i
)))
9790 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9791 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9792 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9796 bld
.insert(std::move(logical_start
));
9799 static void create_vs_exports(isel_context
*ctx
)
9801 assert(ctx
->stage
== vertex_vs
||
9802 ctx
->stage
== tess_eval_vs
||
9803 ctx
->stage
== gs_copy_vs
||
9804 ctx
->stage
== ngg_vertex_gs
||
9805 ctx
->stage
== ngg_tess_eval_gs
);
9807 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9808 ? &ctx
->program
->info
->tes
.outinfo
9809 : &ctx
->program
->info
->vs
.outinfo
;
9811 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9812 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9813 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9816 if (ctx
->options
->key
.has_multiview_view_index
) {
9817 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9818 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9821 /* the order these position exports are created is important */
9823 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9824 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9825 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9826 exported_pos
= true;
9828 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9829 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9830 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9831 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9833 if (ctx
->export_clip_dists
) {
9834 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9835 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9836 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9837 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9840 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9841 if (i
< VARYING_SLOT_VAR0
&&
9842 i
!= VARYING_SLOT_LAYER
&&
9843 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9846 export_vs_varying(ctx
, i
, false, NULL
);
9850 create_null_export(ctx
);
9853 static bool export_fs_mrt_z(isel_context
*ctx
)
9855 Builder
bld(ctx
->program
, ctx
->block
);
9856 unsigned enabled_channels
= 0;
9860 for (unsigned i
= 0; i
< 4; ++i
) {
9861 values
[i
] = Operand(v1
);
9864 /* Both stencil and sample mask only need 16-bits. */
9865 if (!ctx
->program
->info
->ps
.writes_z
&&
9866 (ctx
->program
->info
->ps
.writes_stencil
||
9867 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9868 compr
= true; /* COMPR flag */
9870 if (ctx
->program
->info
->ps
.writes_stencil
) {
9871 /* Stencil should be in X[23:16]. */
9872 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9873 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9874 enabled_channels
|= 0x3;
9877 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9878 /* SampleMask should be in Y[15:0]. */
9879 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9880 enabled_channels
|= 0xc;
9883 if (ctx
->program
->info
->ps
.writes_z
) {
9884 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9885 enabled_channels
|= 0x1;
9888 if (ctx
->program
->info
->ps
.writes_stencil
) {
9889 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9890 enabled_channels
|= 0x2;
9893 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9894 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9895 enabled_channels
|= 0x4;
9899 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9900 * writemask component.
9902 if (ctx
->options
->chip_class
== GFX6
&&
9903 ctx
->options
->family
!= CHIP_OLAND
&&
9904 ctx
->options
->family
!= CHIP_HAINAN
) {
9905 enabled_channels
|= 0x1;
9908 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9909 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9914 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9916 Builder
bld(ctx
->program
, ctx
->block
);
9917 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9920 for (unsigned i
= 0; i
< 4; ++i
) {
9921 if (write_mask
& (1 << i
)) {
9922 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9924 values
[i
] = Operand(v1
);
9928 unsigned target
, col_format
;
9929 unsigned enabled_channels
= 0;
9930 aco_opcode compr_op
= (aco_opcode
)0;
9932 slot
-= FRAG_RESULT_DATA0
;
9933 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9934 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9936 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9937 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9941 case V_028714_SPI_SHADER_ZERO
:
9942 enabled_channels
= 0; /* writemask */
9943 target
= V_008DFC_SQ_EXP_NULL
;
9946 case V_028714_SPI_SHADER_32_R
:
9947 enabled_channels
= 1;
9950 case V_028714_SPI_SHADER_32_GR
:
9951 enabled_channels
= 0x3;
9954 case V_028714_SPI_SHADER_32_AR
:
9955 if (ctx
->options
->chip_class
>= GFX10
) {
9956 /* Special case: on GFX10, the outputs are different for 32_AR */
9957 enabled_channels
= 0x3;
9958 values
[1] = values
[3];
9959 values
[3] = Operand(v1
);
9961 enabled_channels
= 0x9;
9965 case V_028714_SPI_SHADER_FP16_ABGR
:
9966 enabled_channels
= 0x5;
9967 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9970 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9971 enabled_channels
= 0x5;
9972 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9975 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9976 enabled_channels
= 0x5;
9977 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9980 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9981 enabled_channels
= 0x5;
9982 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9983 if (is_int8
|| is_int10
) {
9985 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9986 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9988 for (unsigned i
= 0; i
< 4; i
++) {
9989 if ((write_mask
>> i
) & 1) {
9990 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9991 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9999 case V_028714_SPI_SHADER_SINT16_ABGR
:
10000 enabled_channels
= 0x5;
10001 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10002 if (is_int8
|| is_int10
) {
10004 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10005 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10006 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10007 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10009 for (unsigned i
= 0; i
< 4; i
++) {
10010 if ((write_mask
>> i
) & 1) {
10011 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10012 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10014 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10015 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10022 case V_028714_SPI_SHADER_32_ABGR
:
10023 enabled_channels
= 0xF;
10030 if (target
== V_008DFC_SQ_EXP_NULL
)
10033 if ((bool) compr_op
) {
10034 for (int i
= 0; i
< 2; i
++) {
10035 /* check if at least one of the values to be compressed is enabled */
10036 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10038 enabled_channels
|= enabled
<< (i
*2);
10039 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10040 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10041 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10043 values
[i
] = Operand(v1
);
10046 values
[2] = Operand(v1
);
10047 values
[3] = Operand(v1
);
10049 for (int i
= 0; i
< 4; i
++)
10050 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10053 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10054 enabled_channels
, target
, (bool) compr_op
);
10058 static void create_fs_exports(isel_context
*ctx
)
10060 bool exported
= false;
10062 /* Export depth, stencil and sample mask. */
10063 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10064 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10065 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10066 exported
|= export_fs_mrt_z(ctx
);
10068 /* Export all color render targets. */
10069 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10070 if (ctx
->outputs
.mask
[i
])
10071 exported
|= export_fs_mrt_color(ctx
, i
);
10074 create_null_export(ctx
);
10077 static void write_tcs_tess_factors(isel_context
*ctx
)
10079 unsigned outer_comps
;
10080 unsigned inner_comps
;
10082 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10099 Builder
bld(ctx
->program
, ctx
->block
);
10101 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10102 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10103 bld
.sopp(aco_opcode::s_barrier
);
10105 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10106 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10108 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10109 if_context ic_invocation_id_is_zero
;
10110 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10111 bld
.reset(ctx
->block
);
10113 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10115 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10116 unsigned stride
= inner_comps
+ outer_comps
;
10117 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10121 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10123 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10125 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10126 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10127 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10129 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10130 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10132 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10133 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10134 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10135 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10138 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10139 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10140 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10141 unsigned tf_const_offset
= 0;
10143 if (ctx
->program
->chip_class
<= GFX8
) {
10144 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10145 if_context ic_rel_patch_id_is_zero
;
10146 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10147 bld
.reset(ctx
->block
);
10149 /* Store the dynamic HS control word. */
10150 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10151 bld
.mubuf(aco_opcode::buffer_store_dword
,
10152 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10153 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10154 /* disable_wqm */ false, /* glc */ true);
10155 tf_const_offset
+= 4;
10157 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10158 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10159 bld
.reset(ctx
->block
);
10162 assert(stride
== 2 || stride
== 4 || stride
== 6);
10163 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10164 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10166 /* Store to offchip for TES to read - only if TES reads them */
10167 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10168 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10169 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10171 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10172 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10174 if (likely(inner_comps
)) {
10175 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10176 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10180 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10181 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10184 static void emit_stream_output(isel_context
*ctx
,
10185 Temp
const *so_buffers
,
10186 Temp
const *so_write_offset
,
10187 const struct radv_stream_output
*output
)
10189 unsigned num_comps
= util_bitcount(output
->component_mask
);
10190 unsigned writemask
= (1 << num_comps
) - 1;
10191 unsigned loc
= output
->location
;
10192 unsigned buf
= output
->buffer
;
10194 assert(num_comps
&& num_comps
<= 4);
10195 if (!num_comps
|| num_comps
> 4)
10198 unsigned start
= ffs(output
->component_mask
) - 1;
10201 bool all_undef
= true;
10202 assert(ctx
->stage
& hw_vs
);
10203 for (unsigned i
= 0; i
< num_comps
; i
++) {
10204 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10205 all_undef
= all_undef
&& !out
[i
].id();
10210 while (writemask
) {
10212 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10213 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10214 /* GFX6 doesn't support storing vec3, split it. */
10215 writemask
|= 1u << (start
+ 2);
10219 unsigned offset
= output
->offset
+ start
* 4;
10221 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10222 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10223 for (int i
= 0; i
< count
; ++i
)
10224 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10225 vec
->definitions
[0] = Definition(write_data
);
10226 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10231 opcode
= aco_opcode::buffer_store_dword
;
10234 opcode
= aco_opcode::buffer_store_dwordx2
;
10237 opcode
= aco_opcode::buffer_store_dwordx3
;
10240 opcode
= aco_opcode::buffer_store_dwordx4
;
10243 unreachable("Unsupported dword count.");
10246 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10247 store
->operands
[0] = Operand(so_buffers
[buf
]);
10248 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10249 store
->operands
[2] = Operand((uint32_t) 0);
10250 store
->operands
[3] = Operand(write_data
);
10251 if (offset
> 4095) {
10252 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10253 Builder
bld(ctx
->program
, ctx
->block
);
10254 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10256 store
->offset
= offset
;
10258 store
->offen
= true;
10260 store
->dlc
= false;
10262 store
->can_reorder
= true;
10263 ctx
->block
->instructions
.emplace_back(std::move(store
));
10267 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10269 Builder
bld(ctx
->program
, ctx
->block
);
10271 Temp so_buffers
[4];
10272 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10273 for (unsigned i
= 0; i
< 4; i
++) {
10274 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10278 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10279 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10282 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10283 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10285 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10287 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10290 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10292 bld
.reset(ctx
->block
);
10294 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10296 Temp so_write_offset
[4];
10298 for (unsigned i
= 0; i
< 4; i
++) {
10299 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10304 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10305 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10306 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10307 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10309 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10311 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10312 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10313 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10314 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10318 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10319 struct radv_stream_output
*output
=
10320 &ctx
->program
->info
->so
.outputs
[i
];
10321 if (stream
!= output
->stream
)
10324 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10327 begin_divergent_if_else(ctx
, &ic
);
10328 end_divergent_if(ctx
, &ic
);
10331 } /* end namespace */
10333 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10335 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10336 Builder
bld(ctx
->program
, ctx
->block
);
10337 constexpr unsigned hs_idx
= 1u;
10338 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10339 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10340 Operand((8u << 16) | (hs_idx
* 8u)));
10341 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10343 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10345 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10346 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10347 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10348 ls_has_nonzero_hs_threads
);
10349 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10350 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10351 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10352 ls_has_nonzero_hs_threads
);
10353 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10354 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10355 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10356 ls_has_nonzero_hs_threads
);
10358 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10359 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10360 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10363 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10365 /* Split all arguments except for the first (ring_offsets) and the last
10366 * (exec) so that the dead channels don't stay live throughout the program.
10368 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10369 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10370 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10371 startpgm
->definitions
[i
].regClass().size());
10376 void handle_bc_optimize(isel_context
*ctx
)
10378 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10379 Builder
bld(ctx
->program
, ctx
->block
);
10380 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10381 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10382 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10383 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10384 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10385 if (uses_center
&& uses_centroid
) {
10386 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10387 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10389 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10391 for (unsigned i
= 0; i
< 2; i
++) {
10392 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10393 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10394 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10395 persp_centroid
, persp_center
, sel
);
10397 ctx
->persp_centroid
= bld
.tmp(v2
);
10398 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10399 Operand(new_coord
[0]), Operand(new_coord
[1]));
10400 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10403 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10405 for (unsigned i
= 0; i
< 2; i
++) {
10406 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10407 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10408 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10409 linear_centroid
, linear_center
, sel
);
10411 ctx
->linear_centroid
= bld
.tmp(v2
);
10412 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10413 Operand(new_coord
[0]), Operand(new_coord
[1]));
10414 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10419 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10421 Program
*program
= ctx
->program
;
10423 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10425 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10426 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10427 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10428 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10429 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10431 program
->next_fp_mode
.must_flush_denorms32
=
10432 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10433 program
->next_fp_mode
.must_flush_denorms16_64
=
10434 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10435 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10437 program
->next_fp_mode
.care_about_round32
=
10438 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10440 program
->next_fp_mode
.care_about_round16_64
=
10441 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10442 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10444 /* default to preserving fp16 and fp64 denorms, since it's free */
10445 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10446 program
->next_fp_mode
.denorm16_64
= 0;
10448 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10450 /* preserving fp32 denorms is expensive, so only do it if asked */
10451 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10452 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10454 program
->next_fp_mode
.denorm32
= 0;
10456 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10457 program
->next_fp_mode
.round32
= fp_round_tz
;
10459 program
->next_fp_mode
.round32
= fp_round_ne
;
10461 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10462 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10464 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10466 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10469 void cleanup_cfg(Program
*program
)
10471 /* create linear_succs/logical_succs */
10472 for (Block
& BB
: program
->blocks
) {
10473 for (unsigned idx
: BB
.linear_preds
)
10474 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10475 for (unsigned idx
: BB
.logical_preds
)
10476 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10480 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10482 Builder
bld(ctx
->program
, ctx
->block
);
10484 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10485 Temp count
= i
== 0
10486 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10487 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10488 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10490 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10493 if (ctx
->program
->wave_size
== 64) {
10494 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10495 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10496 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10498 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10499 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10505 bool ngg_early_prim_export(isel_context
*ctx
)
10507 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10511 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10513 Builder
bld(ctx
->program
, ctx
->block
);
10515 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10516 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10518 /* Get the id of the current wave within the threadgroup (workgroup) */
10519 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10520 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10522 /* Execute the following code only on the first wave (wave id 0),
10523 * use the SCC def to tell if the wave id is zero or not.
10525 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10527 begin_uniform_if_then(ctx
, &ic
, cond
);
10528 begin_uniform_if_else(ctx
, &ic
);
10529 bld
.reset(ctx
->block
);
10531 /* Number of vertices output by VS/TES */
10532 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10533 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10534 /* Number of primitives output by VS/TES */
10535 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10536 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10538 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10539 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10540 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10542 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10543 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10545 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10546 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10548 end_uniform_if(ctx
, &ic
);
10551 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10553 Builder
bld(ctx
->program
, ctx
->block
);
10555 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10556 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10559 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10562 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10563 assert(vtxindex
[i
].id());
10566 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10570 /* The initial edge flag is always false in tess eval shaders. */
10571 if (ctx
->stage
== ngg_vertex_gs
) {
10572 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10573 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10577 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10582 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10584 Builder
bld(ctx
->program
, ctx
->block
);
10585 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10587 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10588 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10589 false /* compressed */, true/* done */, false /* valid mask */);
10592 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10594 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10595 * These must always come before VS exports.
10597 * It is recommended to do these as early as possible. They can be at the beginning when
10598 * there is no SW GS and the shader doesn't write edge flags.
10602 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10603 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10605 Builder
bld(ctx
->program
, ctx
->block
);
10606 constexpr unsigned max_vertices_per_primitive
= 3;
10607 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10609 if (ctx
->stage
== ngg_vertex_gs
) {
10610 /* TODO: optimize for points & lines */
10611 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10612 if (ctx
->shader
->info
.tess
.point_mode
)
10613 num_vertices_per_primitive
= 1;
10614 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10615 num_vertices_per_primitive
= 2;
10617 unreachable("Unsupported NGG shader stage");
10620 Temp vtxindex
[max_vertices_per_primitive
];
10621 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10622 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10623 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10624 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10625 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10626 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10627 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10628 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10630 /* Export primitive data to the index buffer. */
10631 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10633 /* Export primitive ID. */
10634 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10635 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10636 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10637 Temp provoking_vtx_index
= vtxindex
[0];
10638 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10640 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10643 begin_divergent_if_else(ctx
, &ic
);
10644 end_divergent_if(ctx
, &ic
);
10647 void ngg_emit_nogs_output(isel_context
*ctx
)
10649 /* Emits NGG GS output, for stages that don't have SW GS. */
10652 Builder
bld(ctx
->program
, ctx
->block
);
10653 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10655 /* NGG streamout is currently disabled by default. */
10656 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10658 if (late_prim_export
) {
10659 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10660 create_export_phis(ctx
);
10661 /* Do what we need to do in the GS threads. */
10662 ngg_emit_nogs_gsthreads(ctx
);
10664 /* What comes next should be executed on ES threads. */
10665 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10666 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10667 bld
.reset(ctx
->block
);
10670 /* Export VS outputs */
10671 ctx
->block
->kind
|= block_kind_export_end
;
10672 create_vs_exports(ctx
);
10674 /* Export primitive ID */
10675 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10678 if (ctx
->stage
== ngg_vertex_gs
) {
10679 /* Wait for GS threads to store primitive ID in LDS. */
10680 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10681 bld
.sopp(aco_opcode::s_barrier
);
10683 /* Calculate LDS address where the GS threads stored the primitive ID. */
10684 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10685 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10686 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10687 Temp wave_id_mul
= bld
.v_mul_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10688 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10689 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10691 /* Load primitive ID from LDS. */
10692 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10693 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10694 /* TES: Just use the patch ID as the primitive ID. */
10695 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10697 unreachable("unsupported NGG shader stage.");
10700 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10701 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10703 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10706 if (late_prim_export
) {
10707 begin_divergent_if_else(ctx
, &ic
);
10708 end_divergent_if(ctx
, &ic
);
10709 bld
.reset(ctx
->block
);
10713 void select_program(Program
*program
,
10714 unsigned shader_count
,
10715 struct nir_shader
*const *shaders
,
10716 ac_shader_config
* config
,
10717 struct radv_shader_args
*args
)
10719 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10720 if_context ic_merged_wave_info
;
10721 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10723 for (unsigned i
= 0; i
< shader_count
; i
++) {
10724 nir_shader
*nir
= shaders
[i
];
10725 init_context(&ctx
, nir
);
10727 setup_fp_mode(&ctx
, nir
);
10730 /* needs to be after init_context() for FS */
10731 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10732 append_logical_start(ctx
.block
);
10734 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10735 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10737 split_arguments(&ctx
, startpgm
);
10741 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10743 if (ngg_early_prim_export(&ctx
))
10744 ngg_emit_nogs_gsthreads(&ctx
);
10747 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10748 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10749 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10750 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10751 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10752 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10753 ctx
.stage
== tess_eval_geometry_gs
));
10755 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10756 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10757 if (check_merged_wave_info
) {
10758 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10759 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10763 Builder
bld(ctx
.program
, ctx
.block
);
10765 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10766 bld
.sopp(aco_opcode::s_barrier
);
10768 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10769 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10771 } else if (ctx
.stage
== geometry_gs
)
10772 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10774 if (ctx
.stage
== fragment_fs
)
10775 handle_bc_optimize(&ctx
);
10777 visit_cf_list(&ctx
, &func
->body
);
10779 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10780 emit_streamout(&ctx
, 0);
10782 if (ctx
.stage
& hw_vs
) {
10783 create_vs_exports(&ctx
);
10784 ctx
.block
->kind
|= block_kind_export_end
;
10785 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10786 ngg_emit_nogs_output(&ctx
);
10787 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10788 Builder
bld(ctx
.program
, ctx
.block
);
10789 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10790 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10791 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10792 write_tcs_tess_factors(&ctx
);
10795 if (ctx
.stage
== fragment_fs
) {
10796 create_fs_exports(&ctx
);
10797 ctx
.block
->kind
|= block_kind_export_end
;
10800 if (endif_merged_wave_info
) {
10801 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10802 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10805 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10806 ngg_emit_nogs_output(&ctx
);
10808 ralloc_free(ctx
.divergent_vals
);
10810 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10811 /* Outputs of the previous stage are inputs to the next stage */
10812 ctx
.inputs
= ctx
.outputs
;
10813 ctx
.outputs
= shader_io_state();
10817 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10819 append_logical_end(ctx
.block
);
10820 ctx
.block
->kind
|= block_kind_uniform
;
10821 Builder
bld(ctx
.program
, ctx
.block
);
10822 if (ctx
.program
->wb_smem_l1_on_end
)
10823 bld
.smem(aco_opcode::s_dcache_wb
, false);
10824 bld
.sopp(aco_opcode::s_endpgm
);
10826 cleanup_cfg(program
);
10829 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10830 ac_shader_config
* config
,
10831 struct radv_shader_args
*args
)
10833 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10835 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10836 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10837 program
->next_fp_mode
.must_flush_denorms32
= false;
10838 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10839 program
->next_fp_mode
.care_about_round32
= false;
10840 program
->next_fp_mode
.care_about_round16_64
= false;
10841 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10842 program
->next_fp_mode
.denorm32
= 0;
10843 program
->next_fp_mode
.round32
= fp_round_ne
;
10844 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10845 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10847 add_startpgm(&ctx
);
10848 append_logical_start(ctx
.block
);
10850 Builder
bld(ctx
.program
, ctx
.block
);
10852 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10854 Operand
stream_id(0u);
10855 if (args
->shader_info
->so
.num_outputs
)
10856 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10857 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10859 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10861 std::stack
<Block
> endif_blocks
;
10863 for (unsigned stream
= 0; stream
< 4; stream
++) {
10864 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10867 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10868 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10871 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10873 unsigned BB_if_idx
= ctx
.block
->index
;
10874 Block BB_endif
= Block();
10875 if (!stream_id
.isConstant()) {
10877 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10878 append_logical_end(ctx
.block
);
10879 ctx
.block
->kind
|= block_kind_uniform
;
10880 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10882 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10884 ctx
.block
= ctx
.program
->create_and_insert_block();
10885 add_edge(BB_if_idx
, ctx
.block
);
10886 bld
.reset(ctx
.block
);
10887 append_logical_start(ctx
.block
);
10890 unsigned offset
= 0;
10891 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10892 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10895 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10896 unsigned length
= util_last_bit(output_usage_mask
);
10897 for (unsigned j
= 0; j
< length
; ++j
) {
10898 if (!(output_usage_mask
& (1 << j
)))
10901 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10902 Temp voffset
= vtx_offset
;
10903 if (const_offset
>= 4096u) {
10904 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10905 const_offset
%= 4096u;
10908 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10909 mubuf
->definitions
[0] = bld
.def(v1
);
10910 mubuf
->operands
[0] = Operand(gsvs_ring
);
10911 mubuf
->operands
[1] = Operand(voffset
);
10912 mubuf
->operands
[2] = Operand(0u);
10913 mubuf
->offen
= true;
10914 mubuf
->offset
= const_offset
;
10917 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10918 mubuf
->barrier
= barrier_none
;
10919 mubuf
->can_reorder
= true;
10921 ctx
.outputs
.mask
[i
] |= 1 << j
;
10922 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10924 bld
.insert(std::move(mubuf
));
10930 if (args
->shader_info
->so
.num_outputs
) {
10931 emit_streamout(&ctx
, stream
);
10932 bld
.reset(ctx
.block
);
10936 create_vs_exports(&ctx
);
10937 ctx
.block
->kind
|= block_kind_export_end
;
10940 if (!stream_id
.isConstant()) {
10941 append_logical_end(ctx
.block
);
10943 /* branch from then block to endif block */
10944 bld
.branch(aco_opcode::p_branch
);
10945 add_edge(ctx
.block
->index
, &BB_endif
);
10946 ctx
.block
->kind
|= block_kind_uniform
;
10948 /* emit else block */
10949 ctx
.block
= ctx
.program
->create_and_insert_block();
10950 add_edge(BB_if_idx
, ctx
.block
);
10951 bld
.reset(ctx
.block
);
10952 append_logical_start(ctx
.block
);
10954 endif_blocks
.push(std::move(BB_endif
));
10958 while (!endif_blocks
.empty()) {
10959 Block BB_endif
= std::move(endif_blocks
.top());
10960 endif_blocks
.pop();
10962 Block
*BB_else
= ctx
.block
;
10964 append_logical_end(BB_else
);
10965 /* branch from else block to endif block */
10966 bld
.branch(aco_opcode::p_branch
);
10967 add_edge(BB_else
->index
, &BB_endif
);
10968 BB_else
->kind
|= block_kind_uniform
;
10970 /** emit endif merge block */
10971 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10972 bld
.reset(ctx
.block
);
10973 append_logical_start(ctx
.block
);
10976 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10978 append_logical_end(ctx
.block
);
10979 ctx
.block
->kind
|= block_kind_uniform
;
10980 bld
.sopp(aco_opcode::s_endpgm
);
10982 cleanup_cfg(program
);