2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
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7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "ac_shader_util.h"
32 #include "aco_builder.h"
33 #include "aco_interface.h"
34 #include "aco_instruction_selection_setup.cpp"
35 #include "util/fast_idiv_by_const.h"
40 class loop_info_RAII
{
42 unsigned header_idx_old
;
44 bool divergent_cont_old
;
45 bool divergent_branch_old
;
46 bool divergent_if_old
;
49 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
51 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
52 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
53 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
54 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
56 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
57 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
58 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
59 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
60 ctx
->cf_info
.parent_if
.is_divergent
= false;
61 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
66 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
67 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
68 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
70 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
71 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
72 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
73 ctx
->cf_info
.exec_potentially_empty
= false;
81 bool exec_potentially_empty_old
;
85 bool then_branch_divergent
;
90 static void visit_cf_list(struct isel_context
*ctx
,
91 struct exec_list
*list
);
93 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
95 succ
->logical_preds
.emplace_back(pred_idx
);
99 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
101 succ
->linear_preds
.emplace_back(pred_idx
);
104 static void add_edge(unsigned pred_idx
, Block
*succ
)
106 add_logical_edge(pred_idx
, succ
);
107 add_linear_edge(pred_idx
, succ
);
110 static void append_logical_start(Block
*b
)
112 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
115 static void append_logical_end(Block
*b
)
117 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
120 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
122 assert(ctx
->allocated
[def
->index
].id());
123 return ctx
->allocated
[def
->index
];
126 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
127 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
129 Builder
bld(ctx
->program
, ctx
->block
);
130 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
131 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
133 if (ctx
->program
->wave_size
== 32) {
136 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
141 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
143 Builder
bld(ctx
->program
, ctx
->block
);
146 dst
= bld
.tmp(src
.regClass());
148 assert(src
.size() == dst
.size());
150 if (ctx
->stage
!= fragment_fs
) {
154 bld
.copy(Definition(dst
), src
);
158 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
159 ctx
->program
->needs_wqm
|= program_needs_wqm
;
163 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
165 if (index
.regClass() == s1
)
166 return bld
.readlane(bld
.def(s1
), data
, index
);
168 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
170 /* Currently not implemented on GFX6-7 */
171 assert(ctx
->options
->chip_class
>= GFX8
);
173 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
174 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
177 /* GFX10, wave64 mode:
178 * The bpermute instruction is limited to half-wave operation, which means that it can't
179 * properly support subgroup shuffle like older generations (or wave32 mode), so we
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
189 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
190 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
191 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
193 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
194 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
197 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
199 if (val
.type() == RegType::sgpr
) {
200 Builder
bld(ctx
->program
, ctx
->block
);
201 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
203 assert(val
.type() == RegType::vgpr
);
207 //assumes a != 0xffffffff
208 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
211 Builder
bld(ctx
->program
, ctx
->block
);
213 if (util_is_power_of_two_or_zero(b
)) {
214 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
218 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
220 assert(info
.multiplier
<= 0xffffffff);
222 bool pre_shift
= info
.pre_shift
!= 0;
223 bool increment
= info
.increment
!= 0;
224 bool multiply
= true;
225 bool post_shift
= info
.post_shift
!= 0;
227 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
228 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
232 Temp pre_shift_dst
= a
;
234 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
235 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
238 Temp increment_dst
= pre_shift_dst
;
240 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
241 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
244 Temp multiply_dst
= increment_dst
;
246 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
247 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
248 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
252 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
256 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
258 Builder
bld(ctx
->program
, ctx
->block
);
259 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
263 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
265 /* no need to extract the whole vector */
266 if (src
.regClass() == dst_rc
) {
270 assert(src
.size() > idx
);
271 Builder
bld(ctx
->program
, ctx
->block
);
272 auto it
= ctx
->allocated_vec
.find(src
.id());
273 /* the size check needs to be early because elements other than 0 may be garbage */
274 if (it
!= ctx
->allocated_vec
.end() && it
->second
[0].size() == dst_rc
.size()) {
275 if (it
->second
[idx
].regClass() == dst_rc
) {
276 return it
->second
[idx
];
278 assert(dst_rc
.size() == it
->second
[idx
].regClass().size());
279 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
280 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
284 if (src
.size() == dst_rc
.size()) {
286 return bld
.copy(bld
.def(dst_rc
), src
);
288 Temp dst
= bld
.tmp(dst_rc
);
289 emit_extract_vector(ctx
, src
, idx
, dst
);
294 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
296 if (num_components
== 1)
298 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
300 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
301 split
->operands
[0] = Operand(vec_src
);
302 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
303 for (unsigned i
= 0; i
< num_components
; i
++) {
304 elems
[i
] = {ctx
->program
->allocateId(), RegClass(vec_src
.type(), vec_src
.size() / num_components
)};
305 split
->definitions
[i
] = Definition(elems
[i
]);
307 ctx
->block
->instructions
.emplace_back(std::move(split
));
308 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
311 /* This vector expansion uses a mask to determine which elements in the new vector
312 * come from the original vector. The other elements are undefined. */
313 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
315 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
320 Builder
bld(ctx
->program
, ctx
->block
);
321 if (num_components
== 1) {
322 if (dst
.type() == RegType::sgpr
)
323 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
325 bld
.copy(Definition(dst
), vec_src
);
329 unsigned component_size
= dst
.size() / num_components
;
330 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
332 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
333 vec
->definitions
[0] = Definition(dst
);
335 for (unsigned i
= 0; i
< num_components
; i
++) {
336 if (mask
& (1 << i
)) {
337 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
338 if (dst
.type() == RegType::sgpr
)
339 src
= bld
.as_uniform(src
);
340 vec
->operands
[i
] = Operand(src
);
342 vec
->operands
[i
] = Operand(0u);
344 elems
[i
] = vec
->operands
[i
].getTemp();
346 ctx
->block
->instructions
.emplace_back(std::move(vec
));
347 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
350 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
352 Builder
bld(ctx
->program
, ctx
->block
);
354 dst
= bld
.tmp(bld
.lm
);
356 assert(val
.regClass() == s1
);
357 assert(dst
.regClass() == bld
.lm
);
359 return bld
.sop2(Builder::s_cselect
, bld
.hint_vcc(Definition(dst
)), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
362 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
364 Builder
bld(ctx
->program
, ctx
->block
);
368 assert(val
.regClass() == bld
.lm
);
369 assert(dst
.regClass() == s1
);
371 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
372 Temp tmp
= bld
.tmp(s1
);
373 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
374 return emit_wqm(ctx
, tmp
, dst
);
377 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
379 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
380 return get_ssa_temp(ctx
, src
.src
.ssa
);
382 if (src
.src
.ssa
->num_components
== size
) {
383 bool identity_swizzle
= true;
384 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
385 if (src
.swizzle
[i
] != i
)
386 identity_swizzle
= false;
388 if (identity_swizzle
)
389 return get_ssa_temp(ctx
, src
.src
.ssa
);
392 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
393 unsigned elem_size
= vec
.size() / src
.src
.ssa
->num_components
;
394 assert(elem_size
> 0); /* TODO: 8 and 16-bit vectors not supported */
395 assert(vec
.size() % elem_size
== 0);
397 RegClass elem_rc
= RegClass(vec
.type(), elem_size
);
399 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
402 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
403 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
404 for (unsigned i
= 0; i
< size
; ++i
) {
405 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
406 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
408 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
)};
409 vec_instr
->definitions
[0] = Definition(dst
);
410 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
411 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
416 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
420 Builder
bld(ctx
->program
, ctx
->block
);
421 if (ptr
.type() == RegType::vgpr
)
422 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
423 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
424 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
427 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
429 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
430 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
431 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
432 sop2
->definitions
[0] = Definition(dst
);
434 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
435 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
438 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
439 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
441 Builder
bld(ctx
->program
, ctx
->block
);
442 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
443 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
444 if (src1
.type() == RegType::sgpr
) {
445 if (commutative
&& src0
.type() == RegType::vgpr
) {
449 } else if (src0
.type() == RegType::vgpr
&&
450 op
!= aco_opcode::v_madmk_f32
&&
451 op
!= aco_opcode::v_madak_f32
&&
452 op
!= aco_opcode::v_madmk_f16
&&
453 op
!= aco_opcode::v_madak_f16
) {
454 /* If the instruction is not commutative, we emit a VOP3A instruction */
455 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
458 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
462 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
463 assert(dst
.size() == 1);
464 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
465 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
467 bld
.vop2(op
, Definition(dst
), src0
, src1
);
471 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
472 bool flush_denorms
= false)
474 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
475 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
476 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
478 /* ensure that the instruction has at most 1 sgpr operand
479 * The optimizer will inline constants for us */
480 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
481 src0
= as_vgpr(ctx
, src0
);
482 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
483 src1
= as_vgpr(ctx
, src1
);
484 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
485 src2
= as_vgpr(ctx
, src2
);
487 Builder
bld(ctx
->program
, ctx
->block
);
488 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
489 assert(dst
.size() == 1);
490 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
491 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
493 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
497 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
499 Builder
bld(ctx
->program
, ctx
->block
);
500 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
503 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
505 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
506 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
507 assert(src0
.size() == src1
.size());
509 aco_ptr
<Instruction
> vopc
;
510 if (src1
.type() == RegType::sgpr
) {
511 if (src0
.type() == RegType::vgpr
) {
512 /* to swap the operands, we might also have to change the opcode */
514 case aco_opcode::v_cmp_lt_f32
:
515 op
= aco_opcode::v_cmp_gt_f32
;
517 case aco_opcode::v_cmp_ge_f32
:
518 op
= aco_opcode::v_cmp_le_f32
;
520 case aco_opcode::v_cmp_lt_i32
:
521 op
= aco_opcode::v_cmp_gt_i32
;
523 case aco_opcode::v_cmp_ge_i32
:
524 op
= aco_opcode::v_cmp_le_i32
;
526 case aco_opcode::v_cmp_lt_u32
:
527 op
= aco_opcode::v_cmp_gt_u32
;
529 case aco_opcode::v_cmp_ge_u32
:
530 op
= aco_opcode::v_cmp_le_u32
;
532 case aco_opcode::v_cmp_lt_f64
:
533 op
= aco_opcode::v_cmp_gt_f64
;
535 case aco_opcode::v_cmp_ge_f64
:
536 op
= aco_opcode::v_cmp_le_f64
;
538 case aco_opcode::v_cmp_lt_i64
:
539 op
= aco_opcode::v_cmp_gt_i64
;
541 case aco_opcode::v_cmp_ge_i64
:
542 op
= aco_opcode::v_cmp_le_i64
;
544 case aco_opcode::v_cmp_lt_u64
:
545 op
= aco_opcode::v_cmp_gt_u64
;
547 case aco_opcode::v_cmp_ge_u64
:
548 op
= aco_opcode::v_cmp_le_u64
;
550 default: /* eq and ne are commutative */
557 src1
= as_vgpr(ctx
, src1
);
561 Builder
bld(ctx
->program
, ctx
->block
);
562 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
565 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
567 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
568 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
569 Builder
bld(ctx
->program
, ctx
->block
);
571 assert(dst
.regClass() == bld
.lm
);
572 assert(src0
.type() == RegType::sgpr
);
573 assert(src1
.type() == RegType::sgpr
);
574 assert(src0
.regClass() == src1
.regClass());
576 /* Emit the SALU comparison instruction */
577 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
578 /* Turn the result into a per-lane bool */
579 bool_to_vector_condition(ctx
, cmp
, dst
);
582 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
583 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
585 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
586 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
587 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
588 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
590 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
591 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
592 aco_opcode op
= use_valu
? v_op
: s_op
;
593 assert(op
!= aco_opcode::num_opcodes
);
594 assert(dst
.regClass() == ctx
->program
->lane_mask
);
597 emit_vopc_instruction(ctx
, instr
, op
, dst
);
599 emit_sopc_instruction(ctx
, instr
, op
, dst
);
602 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
604 Builder
bld(ctx
->program
, ctx
->block
);
605 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
606 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
608 assert(dst
.regClass() == bld
.lm
);
609 assert(src0
.regClass() == bld
.lm
);
610 assert(src1
.regClass() == bld
.lm
);
612 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
615 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
617 Builder
bld(ctx
->program
, ctx
->block
);
618 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
619 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
620 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
622 assert(cond
.regClass() == bld
.lm
);
624 if (dst
.type() == RegType::vgpr
) {
625 aco_ptr
<Instruction
> bcsel
;
626 if (dst
.size() == 1) {
627 then
= as_vgpr(ctx
, then
);
628 els
= as_vgpr(ctx
, els
);
630 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
631 } else if (dst
.size() == 2) {
632 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
633 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
634 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
635 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
637 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
638 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
640 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
642 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
643 nir_print_instr(&instr
->instr
, stderr
);
644 fprintf(stderr
, "\n");
649 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
650 assert(dst
.regClass() == bld
.lm
);
651 assert(then
.regClass() == bld
.lm
);
652 assert(els
.regClass() == bld
.lm
);
655 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
656 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
657 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
658 assert(dst
.size() == then
.size());
659 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
660 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
662 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
663 nir_print_instr(&instr
->instr
, stderr
);
664 fprintf(stderr
, "\n");
669 /* divergent boolean bcsel
670 * this implements bcsel on bools: dst = s0 ? s1 : s2
671 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
672 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
674 if (cond
.id() != then
.id())
675 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
677 if (cond
.id() == els
.id())
678 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
680 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
681 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
684 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
685 aco_opcode op
, uint32_t undo
)
687 /* multiply by 16777216 to handle denormals */
688 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
689 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
690 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
691 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
692 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
694 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
696 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
699 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
701 if (ctx
->block
->fp_mode
.denorm32
== 0) {
702 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
706 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
709 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
711 if (ctx
->block
->fp_mode
.denorm32
== 0) {
712 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
716 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
719 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
721 if (ctx
->block
->fp_mode
.denorm32
== 0) {
722 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
726 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
729 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
731 if (ctx
->block
->fp_mode
.denorm32
== 0) {
732 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
736 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
739 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
741 if (!instr
->dest
.dest
.is_ssa
) {
742 fprintf(stderr
, "nir alu dst not in ssa: ");
743 nir_print_instr(&instr
->instr
, stderr
);
744 fprintf(stderr
, "\n");
747 Builder
bld(ctx
->program
, ctx
->block
);
748 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
753 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
754 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
755 for (unsigned i
= 0; i
< instr
->dest
.dest
.ssa
.num_components
; ++i
) {
756 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
757 vec
->operands
[i
] = Operand
{elems
[i
]};
759 vec
->definitions
[0] = Definition(dst
);
760 ctx
->block
->instructions
.emplace_back(std::move(vec
));
761 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
765 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
766 aco_ptr
<Instruction
> mov
;
767 if (dst
.type() == RegType::sgpr
) {
768 if (src
.type() == RegType::vgpr
)
769 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
770 else if (src
.regClass() == s1
)
771 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
772 else if (src
.regClass() == s2
)
773 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
775 unreachable("wrong src register class for nir_op_imov");
776 } else if (dst
.regClass() == v1
) {
777 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
778 } else if (dst
.regClass() == v2
) {
779 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
781 nir_print_instr(&instr
->instr
, stderr
);
782 unreachable("Should have been lowered to scalar.");
787 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
788 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
789 assert(src
.regClass() == bld
.lm
);
790 assert(dst
.regClass() == bld
.lm
);
791 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
792 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
793 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
794 } else if (dst
.regClass() == v1
) {
795 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
796 } else if (dst
.type() == RegType::sgpr
) {
797 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
798 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
800 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
801 nir_print_instr(&instr
->instr
, stderr
);
802 fprintf(stderr
, "\n");
807 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
808 if (dst
.regClass() == v1
) {
809 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
810 } else if (dst
.regClass() == s1
) {
811 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
812 } else if (dst
.size() == 2) {
813 Temp src0
= bld
.tmp(dst
.type(), 1);
814 Temp src1
= bld
.tmp(dst
.type(), 1);
815 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
817 if (dst
.regClass() == s2
) {
818 Temp carry
= bld
.tmp(s1
);
819 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
820 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
821 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
823 Temp lower
= bld
.tmp(v1
);
824 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
825 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
826 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
829 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
830 nir_print_instr(&instr
->instr
, stderr
);
831 fprintf(stderr
, "\n");
836 if (dst
.regClass() == s1
) {
837 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
838 } else if (dst
.regClass() == v1
) {
839 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
840 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
842 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
843 nir_print_instr(&instr
->instr
, stderr
);
844 fprintf(stderr
, "\n");
849 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
850 if (dst
.regClass() == s1
) {
851 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
852 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
853 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
854 } else if (dst
.regClass() == s2
) {
855 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
857 if (ctx
->program
->chip_class
>= GFX8
)
858 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
860 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
861 /* SCC gets zero-extended to 64 bit */
862 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
863 } else if (dst
.regClass() == v1
) {
864 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
865 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
866 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
867 } else if (dst
.regClass() == v2
) {
868 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
869 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
870 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
871 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
872 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
873 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
875 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
876 nir_print_instr(&instr
->instr
, stderr
);
877 fprintf(stderr
, "\n");
882 if (dst
.regClass() == v1
) {
883 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
884 } else if (dst
.regClass() == s1
) {
885 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
887 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
888 nir_print_instr(&instr
->instr
, stderr
);
889 fprintf(stderr
, "\n");
894 if (dst
.regClass() == v1
) {
895 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
896 } else if (dst
.regClass() == s1
) {
897 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
899 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
900 nir_print_instr(&instr
->instr
, stderr
);
901 fprintf(stderr
, "\n");
906 if (dst
.regClass() == v1
) {
907 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
908 } else if (dst
.regClass() == s1
) {
909 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
911 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
912 nir_print_instr(&instr
->instr
, stderr
);
913 fprintf(stderr
, "\n");
918 if (dst
.regClass() == v1
) {
919 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
920 } else if (dst
.regClass() == s1
) {
921 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
923 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
924 nir_print_instr(&instr
->instr
, stderr
);
925 fprintf(stderr
, "\n");
930 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
931 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
932 } else if (dst
.regClass() == v1
) {
933 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
934 } else if (dst
.regClass() == s1
) {
935 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
936 } else if (dst
.regClass() == s2
) {
937 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
939 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
940 nir_print_instr(&instr
->instr
, stderr
);
941 fprintf(stderr
, "\n");
946 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
947 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
948 } else if (dst
.regClass() == v1
) {
949 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
950 } else if (dst
.regClass() == s1
) {
951 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
952 } else if (dst
.regClass() == s2
) {
953 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
955 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
956 nir_print_instr(&instr
->instr
, stderr
);
957 fprintf(stderr
, "\n");
962 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
963 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
964 } else if (dst
.regClass() == v1
) {
965 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
966 } else if (dst
.regClass() == s1
) {
967 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
968 } else if (dst
.regClass() == s2
) {
969 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
971 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
972 nir_print_instr(&instr
->instr
, stderr
);
973 fprintf(stderr
, "\n");
978 if (dst
.regClass() == v1
) {
979 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
980 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
981 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
982 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
983 } else if (dst
.regClass() == v2
) {
984 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
985 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
986 } else if (dst
.regClass() == s2
) {
987 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
988 } else if (dst
.regClass() == s1
) {
989 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
991 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
992 nir_print_instr(&instr
->instr
, stderr
);
993 fprintf(stderr
, "\n");
998 if (dst
.regClass() == v1
) {
999 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1000 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1001 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1002 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1003 } else if (dst
.regClass() == v2
) {
1004 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1005 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1006 } else if (dst
.regClass() == s1
) {
1007 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1008 } else if (dst
.regClass() == s2
) {
1009 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1011 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1012 nir_print_instr(&instr
->instr
, stderr
);
1013 fprintf(stderr
, "\n");
1018 if (dst
.regClass() == v1
) {
1019 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1020 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1021 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1022 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1023 } else if (dst
.regClass() == v2
) {
1024 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1025 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1026 } else if (dst
.regClass() == s1
) {
1027 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1028 } else if (dst
.regClass() == s2
) {
1029 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1031 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1032 nir_print_instr(&instr
->instr
, stderr
);
1033 fprintf(stderr
, "\n");
1037 case nir_op_find_lsb
: {
1038 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1039 if (src
.regClass() == s1
) {
1040 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1041 } else if (src
.regClass() == v1
) {
1042 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1043 } else if (src
.regClass() == s2
) {
1044 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1046 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1047 nir_print_instr(&instr
->instr
, stderr
);
1048 fprintf(stderr
, "\n");
1052 case nir_op_ufind_msb
:
1053 case nir_op_ifind_msb
: {
1054 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1055 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1056 aco_opcode op
= src
.regClass() == s2
?
1057 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1058 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1059 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1061 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1062 Operand(src
.size() * 32u - 1u), msb_rev
);
1063 Temp msb
= sub
.def(0).getTemp();
1064 Temp carry
= sub
.def(1).getTemp();
1066 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, carry
);
1067 } else if (src
.regClass() == v1
) {
1068 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1069 Temp msb_rev
= bld
.tmp(v1
);
1070 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1071 Temp msb
= bld
.tmp(v1
);
1072 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1073 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1075 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1076 nir_print_instr(&instr
->instr
, stderr
);
1077 fprintf(stderr
, "\n");
1081 case nir_op_bitfield_reverse
: {
1082 if (dst
.regClass() == s1
) {
1083 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1084 } else if (dst
.regClass() == v1
) {
1085 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1087 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1088 nir_print_instr(&instr
->instr
, stderr
);
1089 fprintf(stderr
, "\n");
1094 if (dst
.regClass() == s1
) {
1095 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1099 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1100 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1101 if (dst
.regClass() == v1
) {
1102 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1106 assert(src0
.size() == 2 && src1
.size() == 2);
1107 Temp src00
= bld
.tmp(src0
.type(), 1);
1108 Temp src01
= bld
.tmp(dst
.type(), 1);
1109 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1110 Temp src10
= bld
.tmp(src1
.type(), 1);
1111 Temp src11
= bld
.tmp(dst
.type(), 1);
1112 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1114 if (dst
.regClass() == s2
) {
1115 Temp carry
= bld
.tmp(s1
);
1116 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1117 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1118 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1119 } else if (dst
.regClass() == v2
) {
1120 Temp dst0
= bld
.tmp(v1
);
1121 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1122 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1123 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1131 case nir_op_uadd_sat
: {
1132 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1133 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1134 if (dst
.regClass() == s1
) {
1135 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1136 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1138 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1139 } else if (dst
.regClass() == v1
) {
1140 if (ctx
->options
->chip_class
>= GFX9
) {
1141 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1142 add
->operands
[0] = Operand(src0
);
1143 add
->operands
[1] = Operand(src1
);
1144 add
->definitions
[0] = Definition(dst
);
1146 ctx
->block
->instructions
.emplace_back(std::move(add
));
1148 if (src1
.regClass() != v1
)
1149 std::swap(src0
, src1
);
1150 assert(src1
.regClass() == v1
);
1151 Temp tmp
= bld
.tmp(v1
);
1152 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1153 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1156 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1157 nir_print_instr(&instr
->instr
, stderr
);
1158 fprintf(stderr
, "\n");
1162 case nir_op_uadd_carry
: {
1163 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1164 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1165 if (dst
.regClass() == s1
) {
1166 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1169 if (dst
.regClass() == v1
) {
1170 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1171 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1175 Temp src00
= bld
.tmp(src0
.type(), 1);
1176 Temp src01
= bld
.tmp(dst
.type(), 1);
1177 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1178 Temp src10
= bld
.tmp(src1
.type(), 1);
1179 Temp src11
= bld
.tmp(dst
.type(), 1);
1180 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1181 if (dst
.regClass() == s2
) {
1182 Temp carry
= bld
.tmp(s1
);
1183 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1184 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1185 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1186 } else if (dst
.regClass() == v2
) {
1187 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1188 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1189 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1190 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1192 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1193 nir_print_instr(&instr
->instr
, stderr
);
1194 fprintf(stderr
, "\n");
1199 if (dst
.regClass() == s1
) {
1200 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1204 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1205 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1206 if (dst
.regClass() == v1
) {
1207 bld
.vsub32(Definition(dst
), src0
, src1
);
1211 Temp src00
= bld
.tmp(src0
.type(), 1);
1212 Temp src01
= bld
.tmp(dst
.type(), 1);
1213 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1214 Temp src10
= bld
.tmp(src1
.type(), 1);
1215 Temp src11
= bld
.tmp(dst
.type(), 1);
1216 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1217 if (dst
.regClass() == s2
) {
1218 Temp carry
= bld
.tmp(s1
);
1219 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1220 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1221 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1222 } else if (dst
.regClass() == v2
) {
1223 Temp lower
= bld
.tmp(v1
);
1224 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1225 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1226 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1228 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1229 nir_print_instr(&instr
->instr
, stderr
);
1230 fprintf(stderr
, "\n");
1234 case nir_op_usub_borrow
: {
1235 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1236 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1237 if (dst
.regClass() == s1
) {
1238 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1240 } else if (dst
.regClass() == v1
) {
1241 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1242 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1246 Temp src00
= bld
.tmp(src0
.type(), 1);
1247 Temp src01
= bld
.tmp(dst
.type(), 1);
1248 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1249 Temp src10
= bld
.tmp(src1
.type(), 1);
1250 Temp src11
= bld
.tmp(dst
.type(), 1);
1251 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1252 if (dst
.regClass() == s2
) {
1253 Temp borrow
= bld
.tmp(s1
);
1254 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1255 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1256 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1257 } else if (dst
.regClass() == v2
) {
1258 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1259 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1260 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1261 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1263 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1264 nir_print_instr(&instr
->instr
, stderr
);
1265 fprintf(stderr
, "\n");
1270 if (dst
.regClass() == v1
) {
1271 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1272 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1273 } else if (dst
.regClass() == s1
) {
1274 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1276 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1277 nir_print_instr(&instr
->instr
, stderr
);
1278 fprintf(stderr
, "\n");
1282 case nir_op_umul_high
: {
1283 if (dst
.regClass() == v1
) {
1284 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1285 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1286 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1287 } else if (dst
.regClass() == s1
) {
1288 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1289 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1290 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1292 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1293 nir_print_instr(&instr
->instr
, stderr
);
1294 fprintf(stderr
, "\n");
1298 case nir_op_imul_high
: {
1299 if (dst
.regClass() == v1
) {
1300 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1301 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1302 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1303 } else if (dst
.regClass() == s1
) {
1304 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1305 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1306 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1308 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1309 nir_print_instr(&instr
->instr
, stderr
);
1310 fprintf(stderr
, "\n");
1315 if (dst
.size() == 1) {
1316 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1317 } else if (dst
.size() == 2) {
1318 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1319 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1321 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1322 nir_print_instr(&instr
->instr
, stderr
);
1323 fprintf(stderr
, "\n");
1328 if (dst
.size() == 1) {
1329 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1330 } else if (dst
.size() == 2) {
1331 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1332 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1334 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1335 nir_print_instr(&instr
->instr
, stderr
);
1336 fprintf(stderr
, "\n");
1341 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1342 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1343 if (dst
.size() == 1) {
1344 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1345 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1347 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1348 } else if (dst
.size() == 2) {
1349 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1350 get_alu_src(ctx
, instr
->src
[0]),
1351 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1352 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1355 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1356 nir_print_instr(&instr
->instr
, stderr
);
1357 fprintf(stderr
, "\n");
1362 if (dst
.size() == 1) {
1363 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1364 } else if (dst
.size() == 2) {
1365 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1366 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
),
1367 get_alu_src(ctx
, instr
->src
[0]),
1368 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1369 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1371 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
),
1372 get_alu_src(ctx
, instr
->src
[0]),
1373 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1376 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1377 nir_print_instr(&instr
->instr
, stderr
);
1378 fprintf(stderr
, "\n");
1383 if (dst
.size() == 1) {
1384 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1385 } else if (dst
.size() == 2) {
1386 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1387 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
),
1388 get_alu_src(ctx
, instr
->src
[0]),
1389 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1390 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1392 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
),
1393 get_alu_src(ctx
, instr
->src
[0]),
1394 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1397 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1398 nir_print_instr(&instr
->instr
, stderr
);
1399 fprintf(stderr
, "\n");
1403 case nir_op_fmax3
: {
1404 if (dst
.size() == 1) {
1405 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1407 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1408 nir_print_instr(&instr
->instr
, stderr
);
1409 fprintf(stderr
, "\n");
1413 case nir_op_fmin3
: {
1414 if (dst
.size() == 1) {
1415 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1417 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1418 nir_print_instr(&instr
->instr
, stderr
);
1419 fprintf(stderr
, "\n");
1423 case nir_op_fmed3
: {
1424 if (dst
.size() == 1) {
1425 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1427 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1428 nir_print_instr(&instr
->instr
, stderr
);
1429 fprintf(stderr
, "\n");
1433 case nir_op_umax3
: {
1434 if (dst
.size() == 1) {
1435 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1437 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1438 nir_print_instr(&instr
->instr
, stderr
);
1439 fprintf(stderr
, "\n");
1443 case nir_op_umin3
: {
1444 if (dst
.size() == 1) {
1445 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1447 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1448 nir_print_instr(&instr
->instr
, stderr
);
1449 fprintf(stderr
, "\n");
1453 case nir_op_umed3
: {
1454 if (dst
.size() == 1) {
1455 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1457 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1458 nir_print_instr(&instr
->instr
, stderr
);
1459 fprintf(stderr
, "\n");
1463 case nir_op_imax3
: {
1464 if (dst
.size() == 1) {
1465 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1467 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1468 nir_print_instr(&instr
->instr
, stderr
);
1469 fprintf(stderr
, "\n");
1473 case nir_op_imin3
: {
1474 if (dst
.size() == 1) {
1475 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1477 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1478 nir_print_instr(&instr
->instr
, stderr
);
1479 fprintf(stderr
, "\n");
1483 case nir_op_imed3
: {
1484 if (dst
.size() == 1) {
1485 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1487 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1488 nir_print_instr(&instr
->instr
, stderr
);
1489 fprintf(stderr
, "\n");
1493 case nir_op_cube_face_coord
: {
1494 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1495 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1496 emit_extract_vector(ctx
, in
, 1, v1
),
1497 emit_extract_vector(ctx
, in
, 2, v1
) };
1498 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1499 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1500 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1501 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1502 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1503 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1504 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1507 case nir_op_cube_face_index
: {
1508 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1509 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1510 emit_extract_vector(ctx
, in
, 1, v1
),
1511 emit_extract_vector(ctx
, in
, 2, v1
) };
1512 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1515 case nir_op_bcsel
: {
1516 emit_bcsel(ctx
, instr
, dst
);
1520 if (dst
.size() == 1) {
1521 emit_rsq(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1522 } else if (dst
.size() == 2) {
1523 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1525 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1526 nir_print_instr(&instr
->instr
, stderr
);
1527 fprintf(stderr
, "\n");
1532 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1533 if (dst
.size() == 1) {
1534 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1535 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1536 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1537 } else if (dst
.size() == 2) {
1538 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1539 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1540 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1541 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1542 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1543 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1545 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1546 nir_print_instr(&instr
->instr
, stderr
);
1547 fprintf(stderr
, "\n");
1552 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1553 if (dst
.size() == 1) {
1554 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1555 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1556 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1557 } else if (dst
.size() == 2) {
1558 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1559 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1560 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1561 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1562 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1563 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1565 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1566 nir_print_instr(&instr
->instr
, stderr
);
1567 fprintf(stderr
, "\n");
1572 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1573 if (dst
.size() == 1) {
1574 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1575 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1576 // TODO: confirm that this holds under any circumstances
1577 } else if (dst
.size() == 2) {
1578 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1579 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1582 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1583 nir_print_instr(&instr
->instr
, stderr
);
1584 fprintf(stderr
, "\n");
1588 case nir_op_flog2
: {
1589 if (dst
.size() == 1) {
1590 emit_log2(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1592 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1593 nir_print_instr(&instr
->instr
, stderr
);
1594 fprintf(stderr
, "\n");
1599 if (dst
.size() == 1) {
1600 emit_rcp(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1601 } else if (dst
.size() == 2) {
1602 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1604 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1605 nir_print_instr(&instr
->instr
, stderr
);
1606 fprintf(stderr
, "\n");
1610 case nir_op_fexp2
: {
1611 if (dst
.size() == 1) {
1612 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1614 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1615 nir_print_instr(&instr
->instr
, stderr
);
1616 fprintf(stderr
, "\n");
1620 case nir_op_fsqrt
: {
1621 if (dst
.size() == 1) {
1622 emit_sqrt(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1623 } else if (dst
.size() == 2) {
1624 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1626 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1627 nir_print_instr(&instr
->instr
, stderr
);
1628 fprintf(stderr
, "\n");
1632 case nir_op_ffract
: {
1633 if (dst
.size() == 1) {
1634 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1635 } else if (dst
.size() == 2) {
1636 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1638 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1639 nir_print_instr(&instr
->instr
, stderr
);
1640 fprintf(stderr
, "\n");
1644 case nir_op_ffloor
: {
1645 if (dst
.size() == 1) {
1646 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1647 } else if (dst
.size() == 2) {
1648 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f64
, dst
);
1650 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1651 nir_print_instr(&instr
->instr
, stderr
);
1652 fprintf(stderr
, "\n");
1656 case nir_op_fceil
: {
1657 if (dst
.size() == 1) {
1658 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1659 } else if (dst
.size() == 2) {
1660 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1662 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1663 nir_print_instr(&instr
->instr
, stderr
);
1664 fprintf(stderr
, "\n");
1668 case nir_op_ftrunc
: {
1669 if (dst
.size() == 1) {
1670 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1671 } else if (dst
.size() == 2) {
1672 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f64
, dst
);
1674 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1675 nir_print_instr(&instr
->instr
, stderr
);
1676 fprintf(stderr
, "\n");
1680 case nir_op_fround_even
: {
1681 if (dst
.size() == 1) {
1682 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1683 } else if (dst
.size() == 2) {
1684 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1686 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1687 nir_print_instr(&instr
->instr
, stderr
);
1688 fprintf(stderr
, "\n");
1694 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1695 aco_ptr
<Instruction
> norm
;
1696 if (dst
.size() == 1) {
1697 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
1698 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, as_vgpr(ctx
, src
));
1700 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1701 if (ctx
->options
->chip_class
< GFX9
)
1702 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
1704 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
1705 bld
.vop1(opcode
, Definition(dst
), tmp
);
1707 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1708 nir_print_instr(&instr
->instr
, stderr
);
1709 fprintf(stderr
, "\n");
1713 case nir_op_ldexp
: {
1714 if (dst
.size() == 1) {
1715 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
),
1716 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1717 get_alu_src(ctx
, instr
->src
[1]));
1718 } else if (dst
.size() == 2) {
1719 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
),
1720 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1721 get_alu_src(ctx
, instr
->src
[1]));
1723 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1724 nir_print_instr(&instr
->instr
, stderr
);
1725 fprintf(stderr
, "\n");
1729 case nir_op_frexp_sig
: {
1730 if (dst
.size() == 1) {
1731 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
),
1732 get_alu_src(ctx
, instr
->src
[0]));
1733 } else if (dst
.size() == 2) {
1734 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
),
1735 get_alu_src(ctx
, instr
->src
[0]));
1737 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1738 nir_print_instr(&instr
->instr
, stderr
);
1739 fprintf(stderr
, "\n");
1743 case nir_op_frexp_exp
: {
1744 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1745 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
),
1746 get_alu_src(ctx
, instr
->src
[0]));
1747 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1748 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
),
1749 get_alu_src(ctx
, instr
->src
[0]));
1751 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1752 nir_print_instr(&instr
->instr
, stderr
);
1753 fprintf(stderr
, "\n");
1757 case nir_op_fsign
: {
1758 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
1759 if (dst
.size() == 1) {
1760 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1761 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
1762 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1763 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
1764 } else if (dst
.size() == 2) {
1765 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1766 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
1767 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
1769 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1770 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
1771 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
1773 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
1775 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1776 nir_print_instr(&instr
->instr
, stderr
);
1777 fprintf(stderr
, "\n");
1781 case nir_op_f2f32
: {
1782 if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1783 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
1785 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1786 nir_print_instr(&instr
->instr
, stderr
);
1787 fprintf(stderr
, "\n");
1791 case nir_op_f2f64
: {
1792 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1793 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_f32
, dst
);
1795 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1796 nir_print_instr(&instr
->instr
, stderr
);
1797 fprintf(stderr
, "\n");
1801 case nir_op_i2f32
: {
1802 assert(dst
.size() == 1);
1803 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
1806 case nir_op_i2f64
: {
1807 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1808 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
1809 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1810 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1811 RegClass rc
= RegClass(src
.type(), 1);
1812 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
1813 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1814 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
1815 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
1816 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
1817 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
1820 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1821 nir_print_instr(&instr
->instr
, stderr
);
1822 fprintf(stderr
, "\n");
1826 case nir_op_u2f32
: {
1827 assert(dst
.size() == 1);
1828 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
1831 case nir_op_u2f64
: {
1832 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1833 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
1834 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1835 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1836 RegClass rc
= RegClass(src
.type(), 1);
1837 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
1838 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1839 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
1840 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
1841 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
1842 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
1844 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1845 nir_print_instr(&instr
->instr
, stderr
);
1846 fprintf(stderr
, "\n");
1850 case nir_op_f2i32
: {
1851 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1852 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1853 if (dst
.type() == RegType::vgpr
)
1854 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
1856 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
1857 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
1859 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1860 if (dst
.type() == RegType::vgpr
)
1861 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
1863 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
1864 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
1867 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1868 nir_print_instr(&instr
->instr
, stderr
);
1869 fprintf(stderr
, "\n");
1873 case nir_op_f2u32
: {
1874 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1875 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1876 if (dst
.type() == RegType::vgpr
)
1877 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
1879 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
1880 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
1882 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1883 if (dst
.type() == RegType::vgpr
)
1884 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
1886 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
1887 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
1890 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1891 nir_print_instr(&instr
->instr
, stderr
);
1892 fprintf(stderr
, "\n");
1896 case nir_op_f2i64
: {
1897 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1898 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
1899 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
1900 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
1901 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
1902 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1903 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
1904 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
1905 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
1906 Temp new_exponent
= bld
.tmp(v1
);
1907 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
1908 if (ctx
->program
->chip_class
>= GFX8
)
1909 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
1911 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
1912 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
1913 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
1914 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
1915 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
1916 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
1917 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
1918 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
1919 Temp new_lower
= bld
.tmp(v1
);
1920 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
1921 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
1922 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
1924 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
1925 if (src
.type() == RegType::vgpr
)
1926 src
= bld
.as_uniform(src
);
1927 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
1928 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
1929 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
1930 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
1931 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
1932 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1933 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
1934 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
1935 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
1936 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
1937 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
1938 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
1939 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
1940 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
1941 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
1942 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
1943 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
1944 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
1945 Temp borrow
= bld
.tmp(s1
);
1946 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
1947 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
1948 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1950 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1951 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
1952 Temp trunc
= bld
.vop1(aco_opcode::v_trunc_f64
, bld
.def(v2
), src
);
1953 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
1954 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
1955 Temp floor
= bld
.vop1(aco_opcode::v_floor_f64
, bld
.def(v2
), mul
);
1956 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
1957 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
1958 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
1959 if (dst
.type() == RegType::sgpr
) {
1960 lower
= bld
.as_uniform(lower
);
1961 upper
= bld
.as_uniform(upper
);
1963 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1966 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1967 nir_print_instr(&instr
->instr
, stderr
);
1968 fprintf(stderr
, "\n");
1972 case nir_op_f2u64
: {
1973 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1974 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
1975 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
1976 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
1977 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
1978 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
1979 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
1980 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
1981 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
1982 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
1983 Temp new_exponent
= bld
.tmp(v1
);
1984 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
1985 if (ctx
->program
->chip_class
>= GFX8
)
1986 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
1988 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
1989 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
1990 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
1991 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
1992 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
1993 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
1994 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
1995 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1997 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
1998 if (src
.type() == RegType::vgpr
)
1999 src
= bld
.as_uniform(src
);
2000 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2001 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2002 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2003 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2004 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2005 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2006 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2007 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2008 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2009 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2010 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2011 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2012 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2013 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2014 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2015 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2016 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2017 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2019 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2020 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2021 Temp trunc
= bld
.vop1(aco_opcode::v_trunc_f64
, bld
.def(v2
), src
);
2022 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2023 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2024 Temp floor
= bld
.vop1(aco_opcode::v_floor_f64
, bld
.def(v2
), mul
);
2025 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2026 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2027 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2028 if (dst
.type() == RegType::sgpr
) {
2029 lower
= bld
.as_uniform(lower
);
2030 upper
= bld
.as_uniform(upper
);
2032 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2035 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2036 nir_print_instr(&instr
->instr
, stderr
);
2037 fprintf(stderr
, "\n");
2041 case nir_op_b2f32
: {
2042 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2043 assert(src
.regClass() == bld
.lm
);
2045 if (dst
.regClass() == s1
) {
2046 src
= bool_to_scalar_condition(ctx
, src
);
2047 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2048 } else if (dst
.regClass() == v1
) {
2049 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2051 unreachable("Wrong destination register class for nir_op_b2f32.");
2055 case nir_op_b2f64
: {
2056 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2057 assert(src
.regClass() == bld
.lm
);
2059 if (dst
.regClass() == s2
) {
2060 src
= bool_to_scalar_condition(ctx
, src
);
2061 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2062 } else if (dst
.regClass() == v2
) {
2063 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2064 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2065 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2067 unreachable("Wrong destination register class for nir_op_b2f64.");
2071 case nir_op_i2i32
: {
2072 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2073 if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2074 /* we can actually just say dst = src, as it would map the lower register */
2075 emit_extract_vector(ctx
, src
, 0, dst
);
2077 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2078 nir_print_instr(&instr
->instr
, stderr
);
2079 fprintf(stderr
, "\n");
2083 case nir_op_u2u32
: {
2084 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2085 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2086 if (dst
.regClass() == s1
) {
2087 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2089 // TODO: do better with SDWA
2090 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0xFFFFu
), src
);
2092 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2093 /* we can actually just say dst = src, as it would map the lower register */
2094 emit_extract_vector(ctx
, src
, 0, dst
);
2096 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2097 nir_print_instr(&instr
->instr
, stderr
);
2098 fprintf(stderr
, "\n");
2102 case nir_op_i2i64
: {
2103 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2104 if (src
.regClass() == s1
) {
2105 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2106 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2107 } else if (src
.regClass() == v1
) {
2108 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2109 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2111 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2112 nir_print_instr(&instr
->instr
, stderr
);
2113 fprintf(stderr
, "\n");
2117 case nir_op_u2u64
: {
2118 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2119 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2120 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2122 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2123 nir_print_instr(&instr
->instr
, stderr
);
2124 fprintf(stderr
, "\n");
2128 case nir_op_b2i32
: {
2129 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2130 assert(src
.regClass() == bld
.lm
);
2132 if (dst
.regClass() == s1
) {
2133 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2134 bool_to_scalar_condition(ctx
, src
, dst
);
2135 } else if (dst
.regClass() == v1
) {
2136 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2138 unreachable("Invalid register class for b2i32");
2143 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2144 assert(dst
.regClass() == bld
.lm
);
2146 if (src
.type() == RegType::vgpr
) {
2147 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2148 assert(dst
.regClass() == bld
.lm
);
2149 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2150 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2152 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2154 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2155 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2157 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2158 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2160 bool_to_vector_condition(ctx
, tmp
, dst
);
2164 case nir_op_pack_64_2x32_split
: {
2165 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2166 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2168 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2171 case nir_op_unpack_64_2x32_split_x
:
2172 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2174 case nir_op_unpack_64_2x32_split_y
:
2175 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2177 case nir_op_pack_half_2x16
: {
2178 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2180 if (dst
.regClass() == v1
) {
2181 Temp src0
= bld
.tmp(v1
);
2182 Temp src1
= bld
.tmp(v1
);
2183 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2184 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2185 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2187 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2188 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2189 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2191 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2192 nir_print_instr(&instr
->instr
, stderr
);
2193 fprintf(stderr
, "\n");
2197 case nir_op_unpack_half_2x16_split_x
: {
2198 if (dst
.regClass() == v1
) {
2199 Builder
bld(ctx
->program
, ctx
->block
);
2200 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2202 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2203 nir_print_instr(&instr
->instr
, stderr
);
2204 fprintf(stderr
, "\n");
2208 case nir_op_unpack_half_2x16_split_y
: {
2209 if (dst
.regClass() == v1
) {
2210 Builder
bld(ctx
->program
, ctx
->block
);
2211 /* TODO: use SDWA here */
2212 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2213 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2215 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2216 nir_print_instr(&instr
->instr
, stderr
);
2217 fprintf(stderr
, "\n");
2221 case nir_op_fquantize2f16
: {
2222 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2223 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2226 if (ctx
->program
->chip_class
>= GFX8
) {
2227 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2228 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2229 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2231 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2232 * so compare the result and flush to 0 if it's smaller.
2234 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2235 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2236 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2237 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2238 cmp_res
= vop3
->definitions
[0].getTemp();
2241 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2242 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2243 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2245 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2250 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2251 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2253 if (dst
.regClass() == s1
) {
2254 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2255 } else if (dst
.regClass() == v1
) {
2256 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2258 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2259 nir_print_instr(&instr
->instr
, stderr
);
2260 fprintf(stderr
, "\n");
2264 case nir_op_bitfield_select
: {
2265 /* (mask & insert) | (~mask & base) */
2266 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2267 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2268 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2270 /* dst = (insert & bitmask) | (base & ~bitmask) */
2271 if (dst
.regClass() == s1
) {
2272 aco_ptr
<Instruction
> sop2
;
2273 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2274 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2276 if (const_insert
&& const_bitmask
) {
2277 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2279 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2280 lhs
= Operand(insert
);
2284 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2285 if (const_base
&& const_bitmask
) {
2286 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2288 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2289 rhs
= Operand(base
);
2292 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2294 } else if (dst
.regClass() == v1
) {
2295 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2296 base
= as_vgpr(ctx
, base
);
2297 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2298 insert
= as_vgpr(ctx
, insert
);
2300 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2303 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2304 nir_print_instr(&instr
->instr
, stderr
);
2305 fprintf(stderr
, "\n");
2311 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2312 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2313 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2315 if (dst
.type() == RegType::sgpr
) {
2317 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2318 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2319 if (const_offset
&& const_bits
) {
2320 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2321 extract
= Operand(const_extract
);
2325 width
= Operand(const_bits
->u32
<< 16);
2327 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2329 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2333 if (dst
.regClass() == s1
) {
2334 if (instr
->op
== nir_op_ubfe
)
2335 opcode
= aco_opcode::s_bfe_u32
;
2337 opcode
= aco_opcode::s_bfe_i32
;
2338 } else if (dst
.regClass() == s2
) {
2339 if (instr
->op
== nir_op_ubfe
)
2340 opcode
= aco_opcode::s_bfe_u64
;
2342 opcode
= aco_opcode::s_bfe_i64
;
2344 unreachable("Unsupported BFE bit size");
2347 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2351 if (dst
.regClass() == v1
) {
2352 if (instr
->op
== nir_op_ubfe
)
2353 opcode
= aco_opcode::v_bfe_u32
;
2355 opcode
= aco_opcode::v_bfe_i32
;
2357 unreachable("Unsupported BFE bit size");
2360 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2364 case nir_op_bit_count
: {
2365 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2366 if (src
.regClass() == s1
) {
2367 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2368 } else if (src
.regClass() == v1
) {
2369 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2370 } else if (src
.regClass() == v2
) {
2371 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2372 emit_extract_vector(ctx
, src
, 1, v1
),
2373 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2374 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2375 } else if (src
.regClass() == s2
) {
2376 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2378 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2379 nir_print_instr(&instr
->instr
, stderr
);
2380 fprintf(stderr
, "\n");
2385 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2389 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2393 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2397 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2401 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2405 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2409 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2410 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2412 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2413 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2417 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2418 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2420 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2421 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2425 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2429 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2434 case nir_op_fddx_fine
:
2435 case nir_op_fddy_fine
:
2436 case nir_op_fddx_coarse
:
2437 case nir_op_fddy_coarse
: {
2438 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2439 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2440 if (instr
->op
== nir_op_fddx_fine
) {
2441 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2442 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2443 } else if (instr
->op
== nir_op_fddy_fine
) {
2444 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2445 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2447 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2448 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2449 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2451 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2455 if (ctx
->program
->chip_class
>= GFX8
) {
2456 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2457 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2459 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2460 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2461 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2463 emit_wqm(ctx
, tmp
, dst
, true);
2467 fprintf(stderr
, "Unknown NIR ALU instr: ");
2468 nir_print_instr(&instr
->instr
, stderr
);
2469 fprintf(stderr
, "\n");
2473 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2475 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2477 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2478 // which get truncated the lsb if double and msb if int
2479 // for now, we only use s_mov_b64 with 64bit inline constants
2480 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2481 assert(dst
.type() == RegType::sgpr
);
2483 Builder
bld(ctx
->program
, ctx
->block
);
2485 if (instr
->def
.bit_size
== 1) {
2486 assert(dst
.regClass() == bld
.lm
);
2487 int val
= instr
->value
[0].b
? -1 : 0;
2488 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2489 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2490 } else if (dst
.size() == 1) {
2491 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2493 assert(dst
.size() != 1);
2494 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2495 if (instr
->def
.bit_size
== 64)
2496 for (unsigned i
= 0; i
< dst
.size(); i
++)
2497 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2499 for (unsigned i
= 0; i
< dst
.size(); i
++)
2500 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2502 vec
->definitions
[0] = Definition(dst
);
2503 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2507 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2509 uint32_t new_mask
= 0;
2510 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2511 if (mask
& (1u << i
))
2512 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2516 void visit_store_vs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
2518 /* This wouldn't work inside control flow or with indirect offsets but
2519 * that doesn't happen because of nir_lower_io_to_temporaries(). */
2521 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
2522 unsigned component
= nir_intrinsic_component(instr
);
2523 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
2524 unsigned idx
= nir_intrinsic_base(instr
) + component
;
2526 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
2527 if (off_instr
->type
!= nir_instr_type_load_const
) {
2528 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
2529 nir_print_instr(off_instr
, stderr
);
2530 fprintf(stderr
, "\n");
2532 idx
+= nir_instr_as_load_const(off_instr
)->value
[0].u32
* 4u;
2534 if (instr
->src
[0].ssa
->bit_size
== 64)
2535 write_mask
= widen_mask(write_mask
, 2);
2537 for (unsigned i
= 0; i
< 8; ++i
) {
2538 if (write_mask
& (1 << i
)) {
2539 ctx
->vs_output
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
2540 ctx
->vs_output
.outputs
[idx
/ 4u][idx
% 4u] = emit_extract_vector(ctx
, src
, i
, v1
);
2546 void visit_store_fs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
2548 Builder
bld(ctx
->program
, ctx
->block
);
2549 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
2551 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
2552 for (unsigned i
= 0; i
< 4; ++i
) {
2553 if (write_mask
& (1 << i
)) {
2554 Temp tmp
= emit_extract_vector(ctx
, src
, i
, v1
);
2555 values
[i
] = Operand(tmp
);
2557 values
[i
] = Operand(v1
);
2561 unsigned index
= nir_intrinsic_base(instr
) / 4;
2562 unsigned target
, col_format
;
2563 unsigned enabled_channels
= 0xF;
2564 aco_opcode compr_op
= (aco_opcode
)0;
2566 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
2567 assert(offset
&& "Non-const offsets on exports not yet supported");
2568 index
+= offset
->u32
;
2570 assert(index
!= FRAG_RESULT_COLOR
);
2572 /* Unlike vertex shader exports, it's fine to use multiple exports to
2573 * export separate channels of one target. So shaders which export both
2574 * FRAG_RESULT_SAMPLE_MASK and FRAG_RESULT_DEPTH should work fine.
2575 * TODO: combine the exports in those cases and create better code
2578 if (index
== FRAG_RESULT_SAMPLE_MASK
) {
2580 if (ctx
->program
->info
->ps
.writes_z
) {
2581 target
= V_008DFC_SQ_EXP_MRTZ
;
2582 enabled_channels
= 0x4;
2583 col_format
= (unsigned) -1;
2585 values
[2] = values
[0];
2586 values
[0] = Operand(v1
);
2588 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(values
[0]), Operand(v1
), Operand(v1
),
2589 0xc, V_008DFC_SQ_EXP_MRTZ
, true);
2593 } else if (index
== FRAG_RESULT_DEPTH
) {
2595 target
= V_008DFC_SQ_EXP_MRTZ
;
2596 enabled_channels
= 0x1;
2597 col_format
= (unsigned) -1;
2599 } else if (index
== FRAG_RESULT_STENCIL
) {
2601 if (ctx
->program
->info
->ps
.writes_z
) {
2602 target
= V_008DFC_SQ_EXP_MRTZ
;
2603 enabled_channels
= 0x2;
2604 col_format
= (unsigned) -1;
2606 values
[1] = values
[0];
2607 values
[0] = Operand(v1
);
2609 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
2610 bld
.exp(aco_opcode::exp
, values
[0], Operand(v1
), Operand(v1
), Operand(v1
),
2611 0x3, V_008DFC_SQ_EXP_MRTZ
, true);
2616 index
-= FRAG_RESULT_DATA0
;
2617 target
= V_008DFC_SQ_EXP_MRT
+ index
;
2618 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2620 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2621 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2625 case V_028714_SPI_SHADER_ZERO
:
2626 enabled_channels
= 0; /* writemask */
2627 target
= V_008DFC_SQ_EXP_NULL
;
2630 case V_028714_SPI_SHADER_32_R
:
2631 enabled_channels
= 1;
2634 case V_028714_SPI_SHADER_32_GR
:
2635 enabled_channels
= 0x3;
2638 case V_028714_SPI_SHADER_32_AR
:
2639 if (ctx
->options
->chip_class
>= GFX10
) {
2640 /* Special case: on GFX10, the outputs are different for 32_AR */
2641 enabled_channels
= 0x3;
2642 values
[1] = values
[3];
2643 values
[3] = Operand(v1
);
2645 enabled_channels
= 0x9;
2649 case V_028714_SPI_SHADER_FP16_ABGR
:
2650 enabled_channels
= 0x5;
2651 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
2654 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2655 enabled_channels
= 0x5;
2656 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
2659 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2660 enabled_channels
= 0x5;
2661 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
2664 case V_028714_SPI_SHADER_UINT16_ABGR
: {
2665 enabled_channels
= 0x5;
2666 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
2667 if (is_int8
|| is_int10
) {
2669 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
2670 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
2672 for (unsigned i
= 0; i
< 4; i
++) {
2673 if ((write_mask
>> i
) & 1) {
2674 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
2675 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
2683 case V_028714_SPI_SHADER_SINT16_ABGR
:
2684 enabled_channels
= 0x5;
2685 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
2686 if (is_int8
|| is_int10
) {
2688 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
2689 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
2690 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
2691 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
2693 for (unsigned i
= 0; i
< 4; i
++) {
2694 if ((write_mask
>> i
) & 1) {
2695 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
2696 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
2698 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
2699 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
2706 case V_028714_SPI_SHADER_32_ABGR
:
2707 enabled_channels
= 0xF;
2714 if (target
== V_008DFC_SQ_EXP_NULL
)
2717 if ((bool) compr_op
) {
2718 for (int i
= 0; i
< 2; i
++) {
2719 /* check if at least one of the values to be compressed is enabled */
2720 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
2722 enabled_channels
|= enabled
<< (i
*2);
2723 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
2724 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
2725 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
2727 values
[i
] = Operand(v1
);
2730 values
[2] = Operand(v1
);
2731 values
[3] = Operand(v1
);
2733 for (int i
= 0; i
< 4; i
++)
2734 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
2737 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
2738 enabled_channels
, target
, (bool) compr_op
);
2741 Operand
load_lds_size_m0(isel_context
*ctx
)
2743 /* TODO: m0 does not need to be initialized on GFX9+ */
2744 Builder
bld(ctx
->program
, ctx
->block
);
2745 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
2748 void load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
2749 Temp address
, unsigned base_offset
, unsigned align
)
2751 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2753 Builder
bld(ctx
->program
, ctx
->block
);
2755 Operand m
= load_lds_size_m0(ctx
);
2757 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
2758 unsigned bytes_read
= 0;
2759 unsigned result_size
= 0;
2760 unsigned total_bytes
= num_components
* elem_size_bytes
;
2761 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
2762 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
2764 while (bytes_read
< total_bytes
) {
2765 unsigned todo
= total_bytes
- bytes_read
;
2766 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
2767 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
2769 aco_opcode op
= aco_opcode::last_opcode
;
2771 if (todo
>= 16 && aligned16
&& large_ds_read
) {
2772 op
= aco_opcode::ds_read_b128
;
2774 } else if (todo
>= 16 && aligned8
) {
2775 op
= aco_opcode::ds_read2_b64
;
2778 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
2779 op
= aco_opcode::ds_read_b96
;
2781 } else if (todo
>= 8 && aligned8
) {
2782 op
= aco_opcode::ds_read_b64
;
2784 } else if (todo
>= 8) {
2785 op
= aco_opcode::ds_read2_b32
;
2788 } else if (todo
>= 4) {
2789 op
= aco_opcode::ds_read_b32
;
2794 assert(todo
% elem_size_bytes
== 0);
2795 unsigned num_elements
= todo
/ elem_size_bytes
;
2796 unsigned offset
= base_offset
+ bytes_read
;
2797 unsigned max_offset
= read2
? 1019 : 65535;
2799 Temp address_offset
= address
;
2800 if (offset
> max_offset
) {
2801 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
2802 offset
= bytes_read
;
2804 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
2807 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
2810 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
2813 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
>> 2, (offset
>> 2) + 1);
2815 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
2817 if (num_components
== 1) {
2818 assert(todo
== total_bytes
);
2819 if (dst
.type() == RegType::sgpr
)
2820 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
2824 if (dst
.type() == RegType::sgpr
) {
2825 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
2826 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
2830 if (num_elements
== 1) {
2831 result
[result_size
++] = res
;
2833 assert(res
!= dst
&& res
.size() % num_elements
== 0);
2834 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
2835 split
->operands
[0] = Operand(res
);
2836 for (unsigned i
= 0; i
< num_elements
; i
++)
2837 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
2838 ctx
->block
->instructions
.emplace_back(std::move(split
));
2844 assert(result_size
== num_components
&& result_size
> 1);
2845 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
2846 for (unsigned i
= 0; i
< result_size
; i
++)
2847 vec
->operands
[i
] = Operand(result
[i
]);
2848 vec
->definitions
[0] = Definition(dst
);
2849 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2850 ctx
->allocated_vec
.emplace(dst
.id(), result
);
2853 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
2855 if (start
== 0 && size
== data
.size())
2856 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
2858 unsigned size_hint
= 1;
2859 auto it
= ctx
->allocated_vec
.find(data
.id());
2860 if (it
!= ctx
->allocated_vec
.end())
2861 size_hint
= it
->second
[0].size();
2862 if (size
% size_hint
|| start
% size_hint
)
2869 for (unsigned i
= 0; i
< size
; i
++)
2870 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
2873 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
2875 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
2876 for (unsigned i
= 0; i
< size
; i
++)
2877 vec
->operands
[i
] = Operand(elems
[i
]);
2878 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
2879 vec
->definitions
[0] = Definition(res
);
2880 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2884 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
2886 Builder
bld(ctx
->program
, ctx
->block
);
2887 unsigned bytes_written
= 0;
2888 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
2890 while (bytes_written
< total_size
* 4) {
2891 unsigned todo
= total_size
* 4 - bytes_written
;
2892 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
2893 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
2895 aco_opcode op
= aco_opcode::last_opcode
;
2896 bool write2
= false;
2898 if (todo
>= 16 && aligned16
&& large_ds_write
) {
2899 op
= aco_opcode::ds_write_b128
;
2901 } else if (todo
>= 16 && aligned8
) {
2902 op
= aco_opcode::ds_write2_b64
;
2905 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
2906 op
= aco_opcode::ds_write_b96
;
2908 } else if (todo
>= 8 && aligned8
) {
2909 op
= aco_opcode::ds_write_b64
;
2911 } else if (todo
>= 8) {
2912 op
= aco_opcode::ds_write2_b32
;
2915 } else if (todo
>= 4) {
2916 op
= aco_opcode::ds_write_b32
;
2922 unsigned offset
= offset0
+ offset1
+ bytes_written
;
2923 unsigned max_offset
= write2
? 1020 : 65535;
2924 Temp address_offset
= address
;
2925 if (offset
> max_offset
) {
2926 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
2927 offset
= offset1
+ bytes_written
;
2929 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
2932 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
2933 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
2934 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
>> 2, (offset
>> 2) + 1);
2936 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
2937 bld
.ds(op
, address_offset
, val
, m
, offset
);
2940 bytes_written
+= size
* 4;
2944 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
2945 Temp address
, unsigned base_offset
, unsigned align
)
2947 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2949 Operand m
= load_lds_size_m0(ctx
);
2951 /* we need at most two stores for 32bit variables */
2952 int start
[2], count
[2];
2953 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
2954 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
2955 assert(wrmask
== 0);
2957 /* one combined store is sufficient */
2958 if (count
[0] == count
[1]) {
2959 Builder
bld(ctx
->program
, ctx
->block
);
2961 Temp address_offset
= address
;
2962 if ((base_offset
>> 2) + start
[1] > 255) {
2963 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
2967 assert(count
[0] == 1);
2968 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], v1
);
2969 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], v1
);
2970 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
2971 base_offset
= base_offset
/ elem_size_bytes
;
2972 bld
.ds(op
, address_offset
, val0
, val1
, m
,
2973 base_offset
+ start
[0], base_offset
+ start
[1]);
2977 for (unsigned i
= 0; i
< 2; i
++) {
2981 unsigned elem_size_words
= elem_size_bytes
/ 4;
2982 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
2983 base_offset
, start
[i
] * elem_size_bytes
, align
);
2988 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
2990 if (ctx
->stage
== vertex_vs
) {
2991 visit_store_vs_output(ctx
, instr
);
2992 } else if (ctx
->stage
== fragment_fs
) {
2993 visit_store_fs_output(ctx
, instr
);
2995 unreachable("Shader stage not implemented");
2999 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3001 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3002 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3004 Builder
bld(ctx
->program
, ctx
->block
);
3005 Temp tmp
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3006 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), tmp
, idx
, component
);
3009 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3011 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3012 for (unsigned i
= 0; i
< num_components
; i
++)
3013 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3014 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3015 assert(num_components
== 4);
3016 Builder
bld(ctx
->program
, ctx
->block
);
3017 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3020 for (Operand
& op
: vec
->operands
)
3021 op
= op
.isUndefined() ? Operand(0u) : op
;
3023 vec
->definitions
[0] = Definition(dst
);
3024 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3025 emit_split_vector(ctx
, dst
, num_components
);
3029 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3031 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3032 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3033 unsigned idx
= nir_intrinsic_base(instr
);
3034 unsigned component
= nir_intrinsic_component(instr
);
3035 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3037 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3039 assert(offset
->u32
== 0);
3041 /* the lower 15bit of the prim_mask contain the offset into LDS
3042 * while the upper bits contain the number of prims */
3043 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3044 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3045 Builder
bld(ctx
->program
, ctx
->block
);
3046 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3047 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3048 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3049 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3050 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3053 if (instr
->dest
.ssa
.num_components
== 1) {
3054 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
3056 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
3057 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
3059 Temp tmp
= {ctx
->program
->allocateId(), v1
};
3060 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
3061 vec
->operands
[i
] = Operand(tmp
);
3063 vec
->definitions
[0] = Definition(dst
);
3064 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3068 unsigned get_num_channels_from_data_format(unsigned data_format
)
3070 switch (data_format
) {
3071 case V_008F0C_BUF_DATA_FORMAT_8
:
3072 case V_008F0C_BUF_DATA_FORMAT_16
:
3073 case V_008F0C_BUF_DATA_FORMAT_32
:
3075 case V_008F0C_BUF_DATA_FORMAT_8_8
:
3076 case V_008F0C_BUF_DATA_FORMAT_16_16
:
3077 case V_008F0C_BUF_DATA_FORMAT_32_32
:
3079 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
3080 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
3081 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
3083 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
3084 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
3085 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
3086 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
3087 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
3096 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3097 * so we may need to fix it up. */
3098 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
3100 Builder
bld(ctx
->program
, ctx
->block
);
3102 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
3103 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
3105 /* For the integer-like cases, do a natural sign extension.
3107 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3108 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3111 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
3112 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
3114 /* Convert back to the right type. */
3115 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
3116 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3117 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
3118 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
3119 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
3120 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3126 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3128 Builder
bld(ctx
->program
, ctx
->block
);
3129 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3130 if (ctx
->stage
& sw_vs
) {
3132 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3133 if (off_instr
->type
!= nir_instr_type_load_const
) {
3134 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3135 nir_print_instr(off_instr
, stderr
);
3136 fprintf(stderr
, "\n");
3138 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
3140 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
3142 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
3143 unsigned component
= nir_intrinsic_component(instr
);
3144 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
3145 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
3146 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
3147 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
3149 unsigned dfmt
= attrib_format
& 0xf;
3151 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
3152 unsigned num_dfmt_channels
= get_num_channels_from_data_format(dfmt
);
3153 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
3154 unsigned num_channels
= MIN2(util_last_bit(mask
), num_dfmt_channels
);
3155 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
3156 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
3158 num_channels
= MAX2(num_channels
, 3);
3160 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, Operand(attrib_binding
* 16u));
3163 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
3164 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
3165 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
3167 ctx
->needs_instance_id
= true;
3168 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
3170 Temp divided
= bld
.tmp(v1
);
3171 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
3172 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
3174 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
3177 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
3180 index
= bld
.vadd32(bld
.def(v1
),
3181 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
3182 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
3185 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
3186 index
= bld
.vadd32(bld
.def(v1
), Operand(attrib_offset
/ attrib_stride
), index
);
3187 attrib_offset
= attrib_offset
% attrib_stride
;
3190 Operand
soffset(0u);
3191 if (attrib_offset
>= 4096) {
3192 soffset
= bld
.copy(bld
.def(s1
), Operand(attrib_offset
));
3197 switch (num_channels
) {
3199 opcode
= aco_opcode::tbuffer_load_format_x
;
3202 opcode
= aco_opcode::tbuffer_load_format_xy
;
3205 opcode
= aco_opcode::tbuffer_load_format_xyz
;
3208 opcode
= aco_opcode::tbuffer_load_format_xyzw
;
3211 unreachable("Unimplemented load_input vector size");
3214 Temp tmp
= post_shuffle
|| num_channels
!= dst
.size() || alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
|| component
? bld
.tmp(RegType::vgpr
, num_channels
) : dst
;
3216 aco_ptr
<MTBUF_instruction
> mubuf
{create_instruction
<MTBUF_instruction
>(opcode
, Format::MTBUF
, 3, 1)};
3217 mubuf
->operands
[0] = Operand(index
);
3218 mubuf
->operands
[1] = Operand(list
);
3219 mubuf
->operands
[2] = soffset
;
3220 mubuf
->definitions
[0] = Definition(tmp
);
3221 mubuf
->idxen
= true;
3222 mubuf
->can_reorder
= true;
3225 assert(attrib_offset
< 4096);
3226 mubuf
->offset
= attrib_offset
;
3227 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
3229 emit_split_vector(ctx
, tmp
, tmp
.size());
3231 if (tmp
.id() != dst
.id()) {
3232 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
3233 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
3235 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
3236 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
3237 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
3239 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3240 for (unsigned i
= 0; i
< dst
.size(); i
++) {
3241 unsigned idx
= i
+ component
;
3242 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
&& num_channels
>= 4) {
3243 Temp alpha
= emit_extract_vector(ctx
, tmp
, swizzle
[3], v1
);
3244 vec
->operands
[3] = Operand(adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, alpha
));
3245 } else if (idx
< num_channels
) {
3246 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, tmp
, swizzle
[idx
], v1
));
3247 } else if (is_float
&& idx
== 3) {
3248 vec
->operands
[i
] = Operand(0x3f800000u
);
3249 } else if (!is_float
&& idx
== 3) {
3250 vec
->operands
[i
] = Operand(1u);
3252 vec
->operands
[i
] = Operand(0u);
3255 vec
->definitions
[0] = Definition(dst
);
3256 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3257 emit_split_vector(ctx
, dst
, dst
.size());
3260 } else if (ctx
->stage
== fragment_fs
) {
3261 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3262 if (off_instr
->type
!= nir_instr_type_load_const
||
3263 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
3264 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3265 nir_print_instr(off_instr
, stderr
);
3266 fprintf(stderr
, "\n");
3269 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3270 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[0]);
3272 assert(offset
->u32
== 0);
3274 /* the lower 15bit of the prim_mask contain the offset into LDS
3275 * while the upper bits contain the number of prims */
3276 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3277 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3278 Builder
bld(ctx
->program
, ctx
->block
);
3279 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3280 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3281 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3282 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3283 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3286 unsigned idx
= nir_intrinsic_base(instr
);
3287 unsigned component
= nir_intrinsic_component(instr
);
3289 if (dst
.size() == 1) {
3290 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(2u), bld
.m0(prim_mask
), idx
, component
);
3292 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3293 for (unsigned i
= 0; i
< dst
.size(); i
++)
3294 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(2u), bld
.m0(prim_mask
), idx
, component
+ i
);
3295 vec
->definitions
[0] = Definition(dst
);
3296 bld
.insert(std::move(vec
));
3300 unreachable("Shader stage not implemented");
3304 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
3306 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
3307 Builder
bld(ctx
->program
, ctx
->block
);
3308 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
3309 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, Operand(desc_set
<< 2));//, false, false, false);
3312 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
3316 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3318 Builder
bld(ctx
->program
, ctx
->block
);
3319 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3320 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
3321 index
= bld
.as_uniform(index
);
3322 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
3323 unsigned binding
= nir_intrinsic_binding(instr
);
3326 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
3327 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
3328 unsigned offset
= layout
->binding
[binding
].offset
;
3330 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
3331 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
3332 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
3333 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
3334 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
3337 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
3338 stride
= layout
->binding
[binding
].size
;
3341 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
3342 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
3344 if (nir_const_index
) {
3345 const_index
= const_index
* stride
;
3346 } else if (index
.type() == RegType::vgpr
) {
3347 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
3348 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
3350 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
3354 if (nir_const_index
) {
3355 const_index
= const_index
+ offset
;
3356 } else if (index
.type() == RegType::vgpr
) {
3357 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
3359 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
3363 if (nir_const_index
&& const_index
== 0) {
3365 } else if (index
.type() == RegType::vgpr
) {
3366 index
= bld
.vadd32(bld
.def(v1
),
3367 nir_const_index
? Operand(const_index
) : Operand(index
),
3370 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3371 nir_const_index
? Operand(const_index
) : Operand(index
),
3375 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
3378 void load_buffer(isel_context
*ctx
, unsigned num_components
, Temp dst
,
3379 Temp rsrc
, Temp offset
, bool glc
=false, bool readonly
=true)
3381 Builder
bld(ctx
->program
, ctx
->block
);
3383 unsigned num_bytes
= dst
.size() * 4;
3384 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
3387 if (dst
.type() == RegType::vgpr
|| (ctx
->options
->chip_class
< GFX8
&& !readonly
)) {
3388 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3389 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3390 unsigned const_offset
= 0;
3392 Temp lower
= Temp();
3393 if (num_bytes
> 16) {
3394 assert(num_components
== 3 || num_components
== 4);
3395 op
= aco_opcode::buffer_load_dwordx4
;
3396 lower
= bld
.tmp(v4
);
3397 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3398 mubuf
->definitions
[0] = Definition(lower
);
3399 mubuf
->operands
[0] = vaddr
;
3400 mubuf
->operands
[1] = Operand(rsrc
);
3401 mubuf
->operands
[2] = soffset
;
3402 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3405 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
3406 mubuf
->can_reorder
= readonly
;
3407 bld
.insert(std::move(mubuf
));
3408 emit_split_vector(ctx
, lower
, 2);
3413 switch (num_bytes
) {
3415 op
= aco_opcode::buffer_load_dword
;
3418 op
= aco_opcode::buffer_load_dwordx2
;
3421 op
= aco_opcode::buffer_load_dwordx3
;
3424 op
= aco_opcode::buffer_load_dwordx4
;
3427 unreachable("Load SSBO not implemented for this size.");
3429 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3430 mubuf
->operands
[0] = vaddr
;
3431 mubuf
->operands
[1] = Operand(rsrc
);
3432 mubuf
->operands
[2] = soffset
;
3433 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3436 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
3437 mubuf
->can_reorder
= readonly
;
3438 mubuf
->offset
= const_offset
;
3439 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
3441 if (dst
.size() > 4) {
3442 assert(lower
!= Temp());
3443 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
3444 instr
->definitions
[0] = Definition(upper
);
3445 bld
.insert(std::move(instr
));
3446 if (dst
.size() == 8)
3447 emit_split_vector(ctx
, upper
, 2);
3448 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
3449 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
3450 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
3451 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
3452 if (dst
.size() == 8)
3453 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
3456 if (dst
.type() == RegType::sgpr
) {
3457 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
3458 instr
->definitions
[0] = Definition(vec
);
3459 bld
.insert(std::move(instr
));
3460 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
3462 instr
->definitions
[0] = Definition(dst
);
3463 bld
.insert(std::move(instr
));
3464 emit_split_vector(ctx
, dst
, num_components
);
3467 switch (num_bytes
) {
3469 op
= aco_opcode::s_buffer_load_dword
;
3472 op
= aco_opcode::s_buffer_load_dwordx2
;
3476 op
= aco_opcode::s_buffer_load_dwordx4
;
3480 op
= aco_opcode::s_buffer_load_dwordx8
;
3483 unreachable("Load SSBO not implemented for this size.");
3485 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3486 load
->operands
[0] = Operand(rsrc
);
3487 load
->operands
[1] = Operand(bld
.as_uniform(offset
));
3488 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
3489 load
->definitions
[0] = Definition(dst
);
3492 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
3493 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3494 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
3497 if (dst
.size() == 3) {
3498 Temp vec
= bld
.tmp(s4
);
3499 load
->definitions
[0] = Definition(vec
);
3500 bld
.insert(std::move(load
));
3501 emit_split_vector(ctx
, vec
, 4);
3503 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
3504 emit_extract_vector(ctx
, vec
, 0, s1
),
3505 emit_extract_vector(ctx
, vec
, 1, s1
),
3506 emit_extract_vector(ctx
, vec
, 2, s1
));
3507 } else if (dst
.size() == 6) {
3508 Temp vec
= bld
.tmp(s8
);
3509 load
->definitions
[0] = Definition(vec
);
3510 bld
.insert(std::move(load
));
3511 emit_split_vector(ctx
, vec
, 4);
3513 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
3514 emit_extract_vector(ctx
, vec
, 0, s2
),
3515 emit_extract_vector(ctx
, vec
, 1, s2
),
3516 emit_extract_vector(ctx
, vec
, 2, s2
));
3518 bld
.insert(std::move(load
));
3520 emit_split_vector(ctx
, dst
, num_components
);
3524 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3526 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3527 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3529 Builder
bld(ctx
->program
, ctx
->block
);
3531 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3532 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
3533 unsigned binding
= nir_intrinsic_binding(idx_instr
);
3534 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
3536 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
3537 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3538 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3539 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3540 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3541 if (ctx
->options
->chip_class
>= GFX10
) {
3542 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3543 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3544 S_008F0C_RESOURCE_LEVEL(1);
3546 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3547 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3549 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
3550 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
3551 Operand(0xFFFFFFFFu
),
3552 Operand(desc_type
));
3553 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
3554 rsrc
, upper_dwords
);
3556 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
3557 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
3560 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
3563 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3565 Builder
bld(ctx
->program
, ctx
->block
);
3566 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3568 unsigned offset
= nir_intrinsic_base(instr
);
3569 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
3570 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
3572 unsigned count
= instr
->dest
.ssa
.num_components
;
3573 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
3574 start
-= ctx
->args
->ac
.base_inline_push_consts
;
3575 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
3576 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
3577 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
3578 for (unsigned i
= 0; i
< count
; ++i
) {
3579 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
3580 vec
->operands
[i
] = Operand
{elems
[i
]};
3582 vec
->definitions
[0] = Definition(dst
);
3583 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3584 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
3589 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
3590 if (offset
!= 0) // TODO check if index != 0 as well
3591 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
3592 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
3597 switch (dst
.size()) {
3599 op
= aco_opcode::s_load_dword
;
3602 op
= aco_opcode::s_load_dwordx2
;
3608 op
= aco_opcode::s_load_dwordx4
;
3614 op
= aco_opcode::s_load_dwordx8
;
3617 unreachable("unimplemented or forbidden load_push_constant.");
3620 bld
.smem(op
, Definition(vec
), ptr
, index
);
3623 emit_split_vector(ctx
, vec
, 4);
3624 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
3625 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
3626 emit_extract_vector(ctx
, vec
, 0, rc
),
3627 emit_extract_vector(ctx
, vec
, 1, rc
),
3628 emit_extract_vector(ctx
, vec
, 2, rc
));
3631 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
3634 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3636 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3638 Builder
bld(ctx
->program
, ctx
->block
);
3640 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3641 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3642 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3643 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3644 if (ctx
->options
->chip_class
>= GFX10
) {
3645 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3646 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3647 S_008F0C_RESOURCE_LEVEL(1);
3649 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3650 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3653 unsigned base
= nir_intrinsic_base(instr
);
3654 unsigned range
= nir_intrinsic_range(instr
);
3656 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3657 if (base
&& offset
.type() == RegType::sgpr
)
3658 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
3659 else if (base
&& offset
.type() == RegType::vgpr
)
3660 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
3662 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
3663 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
3664 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
3665 Operand(desc_type
));
3667 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, offset
);
3670 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3672 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
3673 ctx
->cf_info
.exec_potentially_empty
= true;
3675 ctx
->program
->needs_exact
= true;
3677 // TODO: optimize uniform conditions
3678 Builder
bld(ctx
->program
, ctx
->block
);
3679 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3680 assert(src
.regClass() == bld
.lm
);
3681 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
3682 bld
.pseudo(aco_opcode::p_discard_if
, src
);
3683 ctx
->block
->kind
|= block_kind_uses_discard_if
;
3687 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
3689 Builder
bld(ctx
->program
, ctx
->block
);
3691 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
3692 ctx
->cf_info
.exec_potentially_empty
= true;
3694 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
3695 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
3697 if (ctx
->block
->loop_nest_depth
&&
3698 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
3699 /* we handle discards the same way as jump instructions */
3700 append_logical_end(ctx
->block
);
3702 /* in loops, discard behaves like break */
3703 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
3704 ctx
->block
->kind
|= block_kind_discard
;
3707 /* uniform discard - loop ends here */
3708 assert(nir_instr_is_last(&instr
->instr
));
3709 ctx
->block
->kind
|= block_kind_uniform
;
3710 ctx
->cf_info
.has_branch
= true;
3711 bld
.branch(aco_opcode::p_branch
);
3712 add_linear_edge(ctx
->block
->index
, linear_target
);
3716 /* we add a break right behind the discard() instructions */
3717 ctx
->block
->kind
|= block_kind_break
;
3718 unsigned idx
= ctx
->block
->index
;
3720 /* remove critical edges from linear CFG */
3721 bld
.branch(aco_opcode::p_branch
);
3722 Block
* break_block
= ctx
->program
->create_and_insert_block();
3723 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
3724 break_block
->kind
|= block_kind_uniform
;
3725 add_linear_edge(idx
, break_block
);
3726 add_linear_edge(break_block
->index
, linear_target
);
3727 bld
.reset(break_block
);
3728 bld
.branch(aco_opcode::p_branch
);
3730 Block
* continue_block
= ctx
->program
->create_and_insert_block();
3731 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
3732 add_linear_edge(idx
, continue_block
);
3733 append_logical_start(continue_block
);
3734 ctx
->block
= continue_block
;
3739 /* it can currently happen that NIR doesn't remove the unreachable code */
3740 if (!nir_instr_is_last(&instr
->instr
)) {
3741 ctx
->program
->needs_exact
= true;
3742 /* save exec somewhere temporarily so that it doesn't get
3743 * overwritten before the discard from outer exec masks */
3744 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
3745 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
3746 ctx
->block
->kind
|= block_kind_uses_discard_if
;
3750 /* This condition is incorrect for uniformly branched discards in a loop
3751 * predicated by a divergent condition, but the above code catches that case
3752 * and the discard would end up turning into a discard_if.
3762 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
3763 /* program just ends here */
3764 ctx
->block
->kind
|= block_kind_uniform
;
3765 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
3766 0 /* enabled mask */, 9 /* dest */,
3767 false /* compressed */, true/* done */, true /* valid mask */);
3768 bld
.sopp(aco_opcode::s_endpgm
);
3769 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
3771 ctx
->block
->kind
|= block_kind_discard
;
3772 /* branch and linear edge is added by visit_if() */
3776 enum aco_descriptor_type
{
3787 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
3788 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3790 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
3791 return dim
== ac_image_cube
||
3792 dim
== ac_image_1darray
||
3793 dim
== ac_image_2darray
||
3794 dim
== ac_image_2darraymsaa
;
3797 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
3798 enum aco_descriptor_type desc_type
,
3799 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
3801 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
3802 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
3803 if (it != ctx->tex_desc.end())
3806 Temp index
= Temp();
3807 bool index_set
= false;
3808 unsigned constant_index
= 0;
3809 unsigned descriptor_set
;
3810 unsigned base_index
;
3811 Builder
bld(ctx
->program
, ctx
->block
);
3814 assert(tex_instr
&& !image
);
3816 base_index
= tex_instr
->sampler_index
;
3818 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
3819 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
3823 assert(deref_instr
->deref_type
== nir_deref_type_array
);
3824 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
3826 constant_index
+= array_size
* const_value
->u32
;
3828 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
3829 if (indirect
.type() == RegType::vgpr
)
3830 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
3832 if (array_size
!= 1)
3833 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
3839 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
3843 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
3845 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
3846 base_index
= deref_instr
->var
->data
.binding
;
3849 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
3850 list
= convert_pointer_to_64_bit(ctx
, list
);
3852 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
3853 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
3854 unsigned offset
= binding
->offset
;
3855 unsigned stride
= binding
->size
;
3859 assert(base_index
< layout
->binding_count
);
3861 switch (desc_type
) {
3862 case ACO_DESC_IMAGE
:
3864 opcode
= aco_opcode::s_load_dwordx8
;
3866 case ACO_DESC_FMASK
:
3868 opcode
= aco_opcode::s_load_dwordx8
;
3871 case ACO_DESC_SAMPLER
:
3873 opcode
= aco_opcode::s_load_dwordx4
;
3874 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
3875 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
3877 case ACO_DESC_BUFFER
:
3879 opcode
= aco_opcode::s_load_dwordx4
;
3881 case ACO_DESC_PLANE_0
:
3882 case ACO_DESC_PLANE_1
:
3884 opcode
= aco_opcode::s_load_dwordx8
;
3885 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
3887 case ACO_DESC_PLANE_2
:
3889 opcode
= aco_opcode::s_load_dwordx4
;
3893 unreachable("invalid desc_type\n");
3896 offset
+= constant_index
* stride
;
3898 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
3899 (!index_set
|| binding
->immutable_samplers_equal
)) {
3900 if (binding
->immutable_samplers_equal
)
3903 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
3904 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
3905 Operand(samplers
[constant_index
* 4 + 0]),
3906 Operand(samplers
[constant_index
* 4 + 1]),
3907 Operand(samplers
[constant_index
* 4 + 2]),
3908 Operand(samplers
[constant_index
* 4 + 3]));
3913 off
= Operand(offset
);
3915 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
3916 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
3919 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
3921 if (desc_type
== ACO_DESC_PLANE_2
) {
3923 for (unsigned i
= 0; i
< 8; i
++)
3924 components
[i
] = bld
.tmp(s1
);
3925 bld
.pseudo(aco_opcode::p_split_vector
,
3926 Definition(components
[0]),
3927 Definition(components
[1]),
3928 Definition(components
[2]),
3929 Definition(components
[3]),
3932 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
3933 bld
.pseudo(aco_opcode::p_split_vector
,
3934 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
3935 Definition(components
[4]),
3936 Definition(components
[5]),
3937 Definition(components
[6]),
3938 Definition(components
[7]),
3941 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
3942 components
[0], components
[1], components
[2], components
[3],
3943 components
[4], components
[5], components
[6], components
[7]);
3949 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3952 case GLSL_SAMPLER_DIM_BUF
:
3954 case GLSL_SAMPLER_DIM_1D
:
3955 return array
? 2 : 1;
3956 case GLSL_SAMPLER_DIM_2D
:
3957 return array
? 3 : 2;
3958 case GLSL_SAMPLER_DIM_MS
:
3959 return array
? 4 : 3;
3960 case GLSL_SAMPLER_DIM_3D
:
3961 case GLSL_SAMPLER_DIM_CUBE
:
3963 case GLSL_SAMPLER_DIM_RECT
:
3964 case GLSL_SAMPLER_DIM_SUBPASS
:
3966 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3975 /* Adjust the sample index according to FMASK.
3977 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3978 * which is the identity mapping. Each nibble says which physical sample
3979 * should be fetched to get that sample.
3981 * For example, 0x11111100 means there are only 2 samples stored and
3982 * the second sample covers 3/4 of the pixel. When reading samples 0
3983 * and 1, return physical sample 0 (determined by the first two 0s
3984 * in FMASK), otherwise return physical sample 1.
3986 * The sample index should be adjusted as follows:
3987 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3989 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, Temp coords
, Operand sample_index
, Temp fmask_desc_ptr
)
3991 Builder
bld(ctx
->program
, ctx
->block
);
3992 Temp fmask
= bld
.tmp(v1
);
3993 unsigned dim
= ctx
->options
->chip_class
>= GFX10
3994 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
3997 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 2, 1)};
3998 load
->operands
[0] = Operand(coords
);
3999 load
->operands
[1] = Operand(fmask_desc_ptr
);
4000 load
->definitions
[0] = Definition(fmask
);
4007 load
->can_reorder
= true; /* fmask images shouldn't be modified */
4008 ctx
->block
->instructions
.emplace_back(std::move(load
));
4010 Operand sample_index4
;
4011 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
4012 sample_index4
= Operand(sample_index
.constantValue() << 2);
4013 } else if (sample_index
.regClass() == s1
) {
4014 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
4016 assert(sample_index
.regClass() == v1
);
4017 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
4021 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
4022 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
4023 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
4024 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
4026 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
4028 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4029 * resource descriptor is 0 (invalid),
4031 Temp compare
= bld
.tmp(bld
.lm
);
4032 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
4033 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
4035 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
4037 /* Replace the MSAA sample index. */
4038 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
4041 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
4044 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4045 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4046 bool is_array
= glsl_sampler_type_is_array(type
);
4047 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
4048 assert(!add_frag_pos
&& "Input attachments should be lowered.");
4049 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
4050 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
4051 int count
= image_type_to_components_count(dim
, is_array
);
4052 std::vector
<Operand
> coords(count
);
4055 Operand sample_index
;
4056 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
4058 sample_index
= Operand(sample_cv
->u32
);
4060 sample_index
= Operand(emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
), 0, v1
));
4062 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
4063 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, is_array
? 3 : 2, 1)};
4064 for (unsigned i
= 0; i
< vec
->operands
.size(); i
++)
4065 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, src0
, i
, v1
));
4066 Temp fmask_load_address
= {ctx
->program
->allocateId(), is_array
? v3
: v2
};
4067 vec
->definitions
[0] = Definition(fmask_load_address
);
4068 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4070 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
4071 sample_index
= Operand(adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
));
4074 coords
[count
] = sample_index
;
4077 if (count
== 1 && !gfx9_1d
)
4078 return emit_extract_vector(ctx
, src0
, 0, v1
);
4081 coords
[0] = Operand(emit_extract_vector(ctx
, src0
, 0, v1
));
4082 coords
.resize(coords
.size() + 1);
4083 coords
[1] = Operand((uint32_t) 0);
4085 coords
[2] = Operand(emit_extract_vector(ctx
, src0
, 1, v1
));
4087 for (int i
= 0; i
< count
; i
++)
4088 coords
[i
] = Operand(emit_extract_vector(ctx
, src0
, i
, v1
));
4091 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
4092 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
4093 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
4094 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
4097 coords
.emplace_back(Operand(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
)));
4100 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
4101 for (unsigned i
= 0; i
< coords
.size(); i
++)
4102 vec
->operands
[i
] = coords
[i
];
4103 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
4104 vec
->definitions
[0] = Definition(res
);
4105 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4110 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4112 Builder
bld(ctx
->program
, ctx
->block
);
4113 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4114 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4115 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4116 bool is_array
= glsl_sampler_type_is_array(type
);
4117 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4119 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
4120 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
4121 unsigned num_channels
= util_last_bit(mask
);
4122 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
4123 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
4126 switch (num_channels
) {
4128 opcode
= aco_opcode::buffer_load_format_x
;
4131 opcode
= aco_opcode::buffer_load_format_xy
;
4134 opcode
= aco_opcode::buffer_load_format_xyz
;
4137 opcode
= aco_opcode::buffer_load_format_xyzw
;
4140 unreachable(">4 channel buffer image load");
4142 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
4143 load
->operands
[0] = Operand(vindex
);
4144 load
->operands
[1] = Operand(rsrc
);
4145 load
->operands
[2] = Operand((uint32_t) 0);
4147 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
4150 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
4151 load
->definitions
[0] = Definition(tmp
);
4153 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
4154 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
4155 load
->barrier
= barrier_image
;
4156 ctx
->block
->instructions
.emplace_back(std::move(load
));
4158 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
4162 Temp coords
= get_image_coords(ctx
, instr
, type
);
4163 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
4165 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
4166 unsigned num_components
= util_bitcount(dmask
);
4168 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
4171 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
4173 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
4174 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
4176 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 2, 1)};
4177 load
->operands
[0] = Operand(coords
);
4178 load
->operands
[1] = Operand(resource
);
4179 load
->definitions
[0] = Definition(tmp
);
4180 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
4181 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
4182 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4183 load
->dmask
= dmask
;
4185 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
4186 load
->barrier
= barrier_image
;
4187 ctx
->block
->instructions
.emplace_back(std::move(load
));
4189 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
4193 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4195 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4196 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4197 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4198 bool is_array
= glsl_sampler_type_is_array(type
);
4199 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
4201 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
4203 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
4204 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
4205 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
4207 switch (data
.size()) {
4209 opcode
= aco_opcode::buffer_store_format_x
;
4212 opcode
= aco_opcode::buffer_store_format_xy
;
4215 opcode
= aco_opcode::buffer_store_format_xyz
;
4218 opcode
= aco_opcode::buffer_store_format_xyzw
;
4221 unreachable(">4 channel buffer image store");
4223 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
4224 store
->operands
[0] = Operand(vindex
);
4225 store
->operands
[1] = Operand(rsrc
);
4226 store
->operands
[2] = Operand((uint32_t) 0);
4227 store
->operands
[3] = Operand(data
);
4228 store
->idxen
= true;
4231 store
->disable_wqm
= true;
4232 store
->barrier
= barrier_image
;
4233 ctx
->program
->needs_exact
= true;
4234 ctx
->block
->instructions
.emplace_back(std::move(store
));
4238 assert(data
.type() == RegType::vgpr
);
4239 Temp coords
= get_image_coords(ctx
, instr
, type
);
4240 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
4242 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
4243 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
4245 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 4, 0)};
4246 store
->operands
[0] = Operand(coords
);
4247 store
->operands
[1] = Operand(resource
);
4248 store
->operands
[2] = Operand(s4
);
4249 store
->operands
[3] = Operand(data
);
4252 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4253 store
->dmask
= (1 << data
.size()) - 1;
4255 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
4256 store
->disable_wqm
= true;
4257 store
->barrier
= barrier_image
;
4258 ctx
->program
->needs_exact
= true;
4259 ctx
->block
->instructions
.emplace_back(std::move(store
));
4263 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4265 /* return the previous value if dest is ever used */
4266 bool return_previous
= false;
4267 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
4268 return_previous
= true;
4271 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
4272 return_previous
= true;
4276 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4277 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4278 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4279 bool is_array
= glsl_sampler_type_is_array(type
);
4280 Builder
bld(ctx
->program
, ctx
->block
);
4282 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
4283 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
4285 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
4286 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
4288 aco_opcode buf_op
, image_op
;
4289 switch (instr
->intrinsic
) {
4290 case nir_intrinsic_image_deref_atomic_add
:
4291 buf_op
= aco_opcode::buffer_atomic_add
;
4292 image_op
= aco_opcode::image_atomic_add
;
4294 case nir_intrinsic_image_deref_atomic_umin
:
4295 buf_op
= aco_opcode::buffer_atomic_umin
;
4296 image_op
= aco_opcode::image_atomic_umin
;
4298 case nir_intrinsic_image_deref_atomic_imin
:
4299 buf_op
= aco_opcode::buffer_atomic_smin
;
4300 image_op
= aco_opcode::image_atomic_smin
;
4302 case nir_intrinsic_image_deref_atomic_umax
:
4303 buf_op
= aco_opcode::buffer_atomic_umax
;
4304 image_op
= aco_opcode::image_atomic_umax
;
4306 case nir_intrinsic_image_deref_atomic_imax
:
4307 buf_op
= aco_opcode::buffer_atomic_smax
;
4308 image_op
= aco_opcode::image_atomic_smax
;
4310 case nir_intrinsic_image_deref_atomic_and
:
4311 buf_op
= aco_opcode::buffer_atomic_and
;
4312 image_op
= aco_opcode::image_atomic_and
;
4314 case nir_intrinsic_image_deref_atomic_or
:
4315 buf_op
= aco_opcode::buffer_atomic_or
;
4316 image_op
= aco_opcode::image_atomic_or
;
4318 case nir_intrinsic_image_deref_atomic_xor
:
4319 buf_op
= aco_opcode::buffer_atomic_xor
;
4320 image_op
= aco_opcode::image_atomic_xor
;
4322 case nir_intrinsic_image_deref_atomic_exchange
:
4323 buf_op
= aco_opcode::buffer_atomic_swap
;
4324 image_op
= aco_opcode::image_atomic_swap
;
4326 case nir_intrinsic_image_deref_atomic_comp_swap
:
4327 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
4328 image_op
= aco_opcode::image_atomic_cmpswap
;
4331 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
4334 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4336 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
4337 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
4338 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
4339 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
4340 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
4341 mubuf
->operands
[0] = Operand(vindex
);
4342 mubuf
->operands
[1] = Operand(resource
);
4343 mubuf
->operands
[2] = Operand((uint32_t)0);
4344 mubuf
->operands
[3] = Operand(data
);
4345 if (return_previous
)
4346 mubuf
->definitions
[0] = Definition(dst
);
4348 mubuf
->idxen
= true;
4349 mubuf
->glc
= return_previous
;
4350 mubuf
->dlc
= false; /* Not needed for atomics */
4351 mubuf
->disable_wqm
= true;
4352 mubuf
->barrier
= barrier_image
;
4353 ctx
->program
->needs_exact
= true;
4354 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
4358 Temp coords
= get_image_coords(ctx
, instr
, type
);
4359 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
4360 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 4, return_previous
? 1 : 0)};
4361 mimg
->operands
[0] = Operand(coords
);
4362 mimg
->operands
[1] = Operand(resource
);
4363 mimg
->operands
[2] = Operand(s4
); /* no sampler */
4364 mimg
->operands
[3] = Operand(data
);
4365 if (return_previous
)
4366 mimg
->definitions
[0] = Definition(dst
);
4367 mimg
->glc
= return_previous
;
4368 mimg
->dlc
= false; /* Not needed for atomics */
4369 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4370 mimg
->dmask
= (1 << data
.size()) - 1;
4372 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
4373 mimg
->disable_wqm
= true;
4374 mimg
->barrier
= barrier_image
;
4375 ctx
->program
->needs_exact
= true;
4376 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
4380 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
4382 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
4383 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
4384 Builder
bld(ctx
->program
, ctx
->block
);
4386 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
4388 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
4389 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
4391 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
4392 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
4394 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
4395 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
4397 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
4398 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
4399 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
4400 if (dst
.type() == RegType::vgpr
)
4401 bld
.copy(Definition(dst
), shr_dst
);
4403 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
4405 emit_extract_vector(ctx
, desc
, 2, dst
);
4409 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4411 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4412 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4413 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4414 bool is_array
= glsl_sampler_type_is_array(type
);
4415 Builder
bld(ctx
->program
, ctx
->block
);
4417 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
4418 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
4419 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
4423 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
4426 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
4428 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4430 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 2, 1)};
4431 mimg
->operands
[0] = Operand(lod
);
4432 mimg
->operands
[1] = Operand(resource
);
4433 uint8_t& dmask
= mimg
->dmask
;
4434 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4435 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
4436 mimg
->da
= glsl_sampler_type_is_array(type
);
4437 mimg
->can_reorder
= true;
4438 Definition
& def
= mimg
->definitions
[0];
4439 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
4441 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
4442 glsl_sampler_type_is_array(type
)) {
4444 assert(instr
->dest
.ssa
.num_components
== 3);
4445 Temp tmp
= {ctx
->program
->allocateId(), v3
};
4446 def
= Definition(tmp
);
4447 emit_split_vector(ctx
, tmp
, 3);
4449 /* divide 3rd value by 6 by multiplying with magic number */
4450 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
4451 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
4453 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4454 emit_extract_vector(ctx
, tmp
, 0, v1
),
4455 emit_extract_vector(ctx
, tmp
, 1, v1
),
4458 } else if (ctx
->options
->chip_class
== GFX9
&&
4459 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
4460 glsl_sampler_type_is_array(type
)) {
4461 assert(instr
->dest
.ssa
.num_components
== 2);
4462 def
= Definition(dst
);
4465 def
= Definition(dst
);
4468 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4471 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4473 Builder
bld(ctx
->program
, ctx
->block
);
4474 unsigned num_components
= instr
->num_components
;
4476 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4477 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4478 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4480 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
4481 load_buffer(ctx
, num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), glc
, false);
4484 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4486 Builder
bld(ctx
->program
, ctx
->block
);
4487 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4488 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4489 unsigned writemask
= nir_intrinsic_write_mask(instr
);
4490 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
4492 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4493 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4495 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
4496 ctx
->options
->chip_class
>= GFX8
;
4498 offset
= bld
.as_uniform(offset
);
4499 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
4503 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
4504 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
4505 /* GFX6 doesn't support storing vec3, split it. */
4506 writemask
|= 1u << (start
+ 2);
4509 int num_bytes
= count
* elem_size_bytes
;
4511 if (num_bytes
> 16) {
4512 assert(elem_size_bytes
== 8);
4513 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
4518 // TODO: check alignment of sub-dword stores
4519 // TODO: split 3 bytes. there is no store instruction for that
4522 if (count
!= instr
->num_components
) {
4523 emit_split_vector(ctx
, data
, instr
->num_components
);
4524 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4525 for (int i
= 0; i
< count
; i
++) {
4526 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
4527 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
4529 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
4530 vec
->definitions
[0] = Definition(write_data
);
4531 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4532 } else if (!smem
&& data
.type() != RegType::vgpr
) {
4533 assert(num_bytes
% 4 == 0);
4534 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
4535 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
4536 assert(num_bytes
% 4 == 0);
4537 write_data
= bld
.as_uniform(data
);
4542 aco_opcode vmem_op
, smem_op
;
4543 switch (num_bytes
) {
4545 vmem_op
= aco_opcode::buffer_store_dword
;
4546 smem_op
= aco_opcode::s_buffer_store_dword
;
4549 vmem_op
= aco_opcode::buffer_store_dwordx2
;
4550 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
4553 vmem_op
= aco_opcode::buffer_store_dwordx3
;
4554 smem_op
= aco_opcode::last_opcode
;
4555 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
4558 vmem_op
= aco_opcode::buffer_store_dwordx4
;
4559 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
4562 unreachable("Store SSBO not implemented for this size.");
4564 if (ctx
->stage
== fragment_fs
)
4565 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
4568 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
4569 store
->operands
[0] = Operand(rsrc
);
4571 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4572 offset
, Operand(start
* elem_size_bytes
));
4573 store
->operands
[1] = Operand(off
);
4575 store
->operands
[1] = Operand(offset
);
4577 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
4578 store
->operands
[1].setFixed(m0
);
4579 store
->operands
[2] = Operand(write_data
);
4580 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
4582 store
->disable_wqm
= true;
4583 store
->barrier
= barrier_buffer
;
4584 ctx
->block
->instructions
.emplace_back(std::move(store
));
4585 ctx
->program
->wb_smem_l1_on_end
= true;
4586 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
4587 ctx
->block
->kind
|= block_kind_needs_lowering
;
4588 ctx
->program
->needs_exact
= true;
4591 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
4592 store
->operands
[0] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4593 store
->operands
[1] = Operand(rsrc
);
4594 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4595 store
->operands
[3] = Operand(write_data
);
4596 store
->offset
= start
* elem_size_bytes
;
4597 store
->offen
= (offset
.type() == RegType::vgpr
);
4598 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
4600 store
->disable_wqm
= true;
4601 store
->barrier
= barrier_buffer
;
4602 ctx
->program
->needs_exact
= true;
4603 ctx
->block
->instructions
.emplace_back(std::move(store
));
4608 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4610 /* return the previous value if dest is ever used */
4611 bool return_previous
= false;
4612 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
4613 return_previous
= true;
4616 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
4617 return_previous
= true;
4621 Builder
bld(ctx
->program
, ctx
->block
);
4622 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
4624 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
4625 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
4626 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
4628 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4629 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4630 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4632 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4634 aco_opcode op32
, op64
;
4635 switch (instr
->intrinsic
) {
4636 case nir_intrinsic_ssbo_atomic_add
:
4637 op32
= aco_opcode::buffer_atomic_add
;
4638 op64
= aco_opcode::buffer_atomic_add_x2
;
4640 case nir_intrinsic_ssbo_atomic_imin
:
4641 op32
= aco_opcode::buffer_atomic_smin
;
4642 op64
= aco_opcode::buffer_atomic_smin_x2
;
4644 case nir_intrinsic_ssbo_atomic_umin
:
4645 op32
= aco_opcode::buffer_atomic_umin
;
4646 op64
= aco_opcode::buffer_atomic_umin_x2
;
4648 case nir_intrinsic_ssbo_atomic_imax
:
4649 op32
= aco_opcode::buffer_atomic_smax
;
4650 op64
= aco_opcode::buffer_atomic_smax_x2
;
4652 case nir_intrinsic_ssbo_atomic_umax
:
4653 op32
= aco_opcode::buffer_atomic_umax
;
4654 op64
= aco_opcode::buffer_atomic_umax_x2
;
4656 case nir_intrinsic_ssbo_atomic_and
:
4657 op32
= aco_opcode::buffer_atomic_and
;
4658 op64
= aco_opcode::buffer_atomic_and_x2
;
4660 case nir_intrinsic_ssbo_atomic_or
:
4661 op32
= aco_opcode::buffer_atomic_or
;
4662 op64
= aco_opcode::buffer_atomic_or_x2
;
4664 case nir_intrinsic_ssbo_atomic_xor
:
4665 op32
= aco_opcode::buffer_atomic_xor
;
4666 op64
= aco_opcode::buffer_atomic_xor_x2
;
4668 case nir_intrinsic_ssbo_atomic_exchange
:
4669 op32
= aco_opcode::buffer_atomic_swap
;
4670 op64
= aco_opcode::buffer_atomic_swap_x2
;
4672 case nir_intrinsic_ssbo_atomic_comp_swap
:
4673 op32
= aco_opcode::buffer_atomic_cmpswap
;
4674 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
4677 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
4679 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
4680 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
4681 mubuf
->operands
[0] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4682 mubuf
->operands
[1] = Operand(rsrc
);
4683 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4684 mubuf
->operands
[3] = Operand(data
);
4685 if (return_previous
)
4686 mubuf
->definitions
[0] = Definition(dst
);
4688 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4689 mubuf
->glc
= return_previous
;
4690 mubuf
->dlc
= false; /* Not needed for atomics */
4691 mubuf
->disable_wqm
= true;
4692 mubuf
->barrier
= barrier_buffer
;
4693 ctx
->program
->needs_exact
= true;
4694 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
4697 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
4699 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4700 Builder
bld(ctx
->program
, ctx
->block
);
4701 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
4702 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
4705 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4707 Builder
bld(ctx
->program
, ctx
->block
);
4708 unsigned num_components
= instr
->num_components
;
4709 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
4711 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4712 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4714 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
4715 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4717 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
4718 bool global
= ctx
->options
->chip_class
>= GFX9
;
4720 switch (num_bytes
) {
4722 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
4725 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
4728 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
4731 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
4734 unreachable("load_global not implemented for this size.");
4736 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
4737 flat
->operands
[0] = Operand(addr
);
4738 flat
->operands
[1] = Operand(s1
);
4741 flat
->barrier
= barrier_buffer
;
4743 if (dst
.type() == RegType::sgpr
) {
4744 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4745 flat
->definitions
[0] = Definition(vec
);
4746 ctx
->block
->instructions
.emplace_back(std::move(flat
));
4747 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
4749 flat
->definitions
[0] = Definition(dst
);
4750 ctx
->block
->instructions
.emplace_back(std::move(flat
));
4752 emit_split_vector(ctx
, dst
, num_components
);
4754 switch (num_bytes
) {
4756 op
= aco_opcode::s_load_dword
;
4759 op
= aco_opcode::s_load_dwordx2
;
4763 op
= aco_opcode::s_load_dwordx4
;
4766 unreachable("load_global not implemented for this size.");
4768 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4769 load
->operands
[0] = Operand(addr
);
4770 load
->operands
[1] = Operand(0u);
4771 load
->definitions
[0] = Definition(dst
);
4774 load
->barrier
= barrier_buffer
;
4775 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4777 if (dst
.size() == 3) {
4779 Temp vec
= bld
.tmp(s4
);
4780 load
->definitions
[0] = Definition(vec
);
4781 ctx
->block
->instructions
.emplace_back(std::move(load
));
4782 emit_split_vector(ctx
, vec
, 4);
4784 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4785 emit_extract_vector(ctx
, vec
, 0, s1
),
4786 emit_extract_vector(ctx
, vec
, 1, s1
),
4787 emit_extract_vector(ctx
, vec
, 2, s1
));
4789 ctx
->block
->instructions
.emplace_back(std::move(load
));
4794 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4796 Builder
bld(ctx
->program
, ctx
->block
);
4797 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4799 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4800 Temp addr
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4802 unsigned writemask
= nir_intrinsic_write_mask(instr
);
4805 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
4806 unsigned num_bytes
= count
* elem_size_bytes
;
4808 Temp write_data
= data
;
4809 if (count
!= instr
->num_components
) {
4810 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4811 for (int i
= 0; i
< count
; i
++)
4812 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
4813 write_data
= bld
.tmp(RegType::vgpr
, count
);
4814 vec
->definitions
[0] = Definition(write_data
);
4815 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4818 unsigned offset
= start
* elem_size_bytes
;
4819 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
4820 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
4821 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
4822 Temp carry
= bld
.tmp(bld
.lm
);
4823 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
4825 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
4826 Operand(offset
), addr0
);
4827 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
4829 carry
).def(1).setHint(vcc
);
4831 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
4836 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
4837 bool global
= ctx
->options
->chip_class
>= GFX9
;
4839 switch (num_bytes
) {
4841 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
4844 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
4847 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
4850 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
4853 unreachable("store_global not implemented for this size.");
4855 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
4856 flat
->operands
[0] = Operand(addr
);
4857 flat
->operands
[1] = Operand(s1
);
4858 flat
->operands
[2] = Operand(data
);
4861 flat
->offset
= offset
;
4862 flat
->disable_wqm
= true;
4863 flat
->barrier
= barrier_buffer
;
4864 ctx
->program
->needs_exact
= true;
4865 ctx
->block
->instructions
.emplace_back(std::move(flat
));
4869 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4871 /* return the previous value if dest is ever used */
4872 bool return_previous
= false;
4873 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
4874 return_previous
= true;
4877 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
4878 return_previous
= true;
4882 Builder
bld(ctx
->program
, ctx
->block
);
4883 Temp addr
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4884 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4886 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
4887 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
4888 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
4890 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4892 bool global
= ctx
->options
->chip_class
>= GFX9
;
4893 aco_opcode op32
, op64
;
4894 switch (instr
->intrinsic
) {
4895 case nir_intrinsic_global_atomic_add
:
4896 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
4897 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
4899 case nir_intrinsic_global_atomic_imin
:
4900 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
4901 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
4903 case nir_intrinsic_global_atomic_umin
:
4904 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
4905 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
4907 case nir_intrinsic_global_atomic_imax
:
4908 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
4909 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
4911 case nir_intrinsic_global_atomic_umax
:
4912 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
4913 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
4915 case nir_intrinsic_global_atomic_and
:
4916 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
4917 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
4919 case nir_intrinsic_global_atomic_or
:
4920 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
4921 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
4923 case nir_intrinsic_global_atomic_xor
:
4924 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
4925 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
4927 case nir_intrinsic_global_atomic_exchange
:
4928 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
4929 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
4931 case nir_intrinsic_global_atomic_comp_swap
:
4932 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
4933 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
4936 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
4938 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
4939 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
4940 flat
->operands
[0] = Operand(addr
);
4941 flat
->operands
[1] = Operand(s1
);
4942 flat
->operands
[2] = Operand(data
);
4943 if (return_previous
)
4944 flat
->definitions
[0] = Definition(dst
);
4945 flat
->glc
= return_previous
;
4946 flat
->dlc
= false; /* Not needed for atomics */
4948 flat
->disable_wqm
= true;
4949 flat
->barrier
= barrier_buffer
;
4950 ctx
->program
->needs_exact
= true;
4951 ctx
->block
->instructions
.emplace_back(std::move(flat
));
4954 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
4955 Builder
bld(ctx
->program
, ctx
->block
);
4956 switch(instr
->intrinsic
) {
4957 case nir_intrinsic_group_memory_barrier
:
4958 case nir_intrinsic_memory_barrier
:
4959 bld
.barrier(aco_opcode::p_memory_barrier_all
);
4961 case nir_intrinsic_memory_barrier_buffer
:
4962 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
4964 case nir_intrinsic_memory_barrier_image
:
4965 bld
.barrier(aco_opcode::p_memory_barrier_image
);
4967 case nir_intrinsic_memory_barrier_shared
:
4968 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
4971 unreachable("Unimplemented memory barrier intrinsic");
4976 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4978 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
4979 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4980 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
4981 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4982 Builder
bld(ctx
->program
, ctx
->block
);
4984 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4985 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
4986 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
4989 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4991 unsigned writemask
= nir_intrinsic_write_mask(instr
);
4992 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4993 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4994 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4995 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
4997 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
4998 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
5001 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5003 unsigned offset
= nir_intrinsic_base(instr
);
5004 Operand m
= load_lds_size_m0(ctx
);
5005 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5006 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5008 unsigned num_operands
= 3;
5009 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
5010 switch(instr
->intrinsic
) {
5011 case nir_intrinsic_shared_atomic_add
:
5012 op32
= aco_opcode::ds_add_u32
;
5013 op64
= aco_opcode::ds_add_u64
;
5014 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
5015 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
5017 case nir_intrinsic_shared_atomic_imin
:
5018 op32
= aco_opcode::ds_min_i32
;
5019 op64
= aco_opcode::ds_min_i64
;
5020 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
5021 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
5023 case nir_intrinsic_shared_atomic_umin
:
5024 op32
= aco_opcode::ds_min_u32
;
5025 op64
= aco_opcode::ds_min_u64
;
5026 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
5027 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
5029 case nir_intrinsic_shared_atomic_imax
:
5030 op32
= aco_opcode::ds_max_i32
;
5031 op64
= aco_opcode::ds_max_i64
;
5032 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
5033 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
5035 case nir_intrinsic_shared_atomic_umax
:
5036 op32
= aco_opcode::ds_max_u32
;
5037 op64
= aco_opcode::ds_max_u64
;
5038 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
5039 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
5041 case nir_intrinsic_shared_atomic_and
:
5042 op32
= aco_opcode::ds_and_b32
;
5043 op64
= aco_opcode::ds_and_b64
;
5044 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
5045 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
5047 case nir_intrinsic_shared_atomic_or
:
5048 op32
= aco_opcode::ds_or_b32
;
5049 op64
= aco_opcode::ds_or_b64
;
5050 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
5051 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
5053 case nir_intrinsic_shared_atomic_xor
:
5054 op32
= aco_opcode::ds_xor_b32
;
5055 op64
= aco_opcode::ds_xor_b64
;
5056 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
5057 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
5059 case nir_intrinsic_shared_atomic_exchange
:
5060 op32
= aco_opcode::ds_write_b32
;
5061 op64
= aco_opcode::ds_write_b64
;
5062 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
5063 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
5065 case nir_intrinsic_shared_atomic_comp_swap
:
5066 op32
= aco_opcode::ds_cmpst_b32
;
5067 op64
= aco_opcode::ds_cmpst_b64
;
5068 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
5069 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
5073 unreachable("Unhandled shared atomic intrinsic");
5076 /* return the previous value if dest is ever used */
5077 bool return_previous
= false;
5078 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5079 return_previous
= true;
5082 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5083 return_previous
= true;
5088 if (data
.size() == 1) {
5089 assert(instr
->dest
.ssa
.bit_size
== 32);
5090 op
= return_previous
? op32_rtn
: op32
;
5092 assert(instr
->dest
.ssa
.bit_size
== 64);
5093 op
= return_previous
? op64_rtn
: op64
;
5096 if (offset
> 65535) {
5097 Builder
bld(ctx
->program
, ctx
->block
);
5098 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
5102 aco_ptr
<DS_instruction
> ds
;
5103 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
5104 ds
->operands
[0] = Operand(address
);
5105 ds
->operands
[1] = Operand(data
);
5106 if (num_operands
== 4)
5107 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5108 ds
->operands
[num_operands
- 1] = m
;
5109 ds
->offset0
= offset
;
5110 if (return_previous
)
5111 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
5112 ctx
->block
->instructions
.emplace_back(std::move(ds
));
5115 Temp
get_scratch_resource(isel_context
*ctx
)
5117 Builder
bld(ctx
->program
, ctx
->block
);
5118 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
5119 if (ctx
->stage
!= compute_cs
)
5120 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
5122 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
5123 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
5125 if (ctx
->program
->chip_class
>= GFX10
) {
5126 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5127 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5128 S_008F0C_RESOURCE_LEVEL(1);
5129 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
5130 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5131 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5134 /* older generations need element size = 16 bytes. element size removed in GFX9 */
5135 if (ctx
->program
->chip_class
<= GFX8
)
5136 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
5138 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
5141 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5142 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
5143 Builder
bld(ctx
->program
, ctx
->block
);
5144 Temp rsrc
= get_scratch_resource(ctx
);
5145 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5146 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5149 switch (dst
.size()) {
5151 op
= aco_opcode::buffer_load_dword
;
5154 op
= aco_opcode::buffer_load_dwordx2
;
5157 op
= aco_opcode::buffer_load_dwordx3
;
5160 op
= aco_opcode::buffer_load_dwordx4
;
5164 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5165 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
5166 bld
.def(v4
), offset
, rsrc
,
5167 ctx
->program
->scratch_offset
, 0, true);
5168 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
5169 aco_opcode::buffer_load_dwordx4
,
5170 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
5171 offset
, rsrc
, ctx
->program
->scratch_offset
, 16, true);
5172 emit_split_vector(ctx
, lower
, 2);
5173 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
5174 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
5175 if (dst
.size() == 8) {
5176 emit_split_vector(ctx
, upper
, 2);
5177 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
5178 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
5183 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
5184 Format::PSEUDO
, dst
.size() / 2, 1)};
5185 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
5186 vec
->operands
[i
] = Operand(elems
[i
]);
5187 vec
->definitions
[0] = Definition(dst
);
5188 bld
.insert(std::move(vec
));
5189 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5193 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
5196 bld
.mubuf(op
, Definition(dst
), offset
, rsrc
, ctx
->program
->scratch_offset
, 0, true);
5197 emit_split_vector(ctx
, dst
, instr
->num_components
);
5200 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5201 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
5202 Builder
bld(ctx
->program
, ctx
->block
);
5203 Temp rsrc
= get_scratch_resource(ctx
);
5204 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5205 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5207 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5208 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5212 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5213 int num_bytes
= count
* elem_size_bytes
;
5215 if (num_bytes
> 16) {
5216 assert(elem_size_bytes
== 8);
5217 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5222 // TODO: check alignment of sub-dword stores
5223 // TODO: split 3 bytes. there is no store instruction for that
5226 if (count
!= instr
->num_components
) {
5227 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5228 for (int i
= 0; i
< count
; i
++) {
5229 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
5230 vec
->operands
[i
] = Operand(elem
);
5232 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
5233 vec
->definitions
[0] = Definition(write_data
);
5234 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5240 switch (num_bytes
) {
5242 op
= aco_opcode::buffer_store_dword
;
5245 op
= aco_opcode::buffer_store_dwordx2
;
5248 op
= aco_opcode::buffer_store_dwordx3
;
5251 op
= aco_opcode::buffer_store_dwordx4
;
5254 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
5257 bld
.mubuf(op
, offset
, rsrc
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
5261 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5262 uint8_t log2_ps_iter_samples
;
5263 if (ctx
->program
->info
->ps
.force_persample
) {
5264 log2_ps_iter_samples
=
5265 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
5267 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
5270 /* The bit pattern matches that used by fixed function fragment
5272 static const unsigned ps_iter_masks
[] = {
5273 0xffff, /* not used */
5279 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
5281 Builder
bld(ctx
->program
, ctx
->block
);
5283 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
5284 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
5285 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
5286 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
5287 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5288 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
5291 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
5293 Builder
bld(ctx
->program
, ctx
->block
);
5295 if (cluster_size
== 1) {
5297 } if (op
== nir_op_iand
&& cluster_size
== 4) {
5298 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
5299 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
5300 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
5301 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
5302 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
5303 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
5304 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
5305 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
5306 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
5307 //subgroupAnd(val) -> (exec & ~val) == 0
5308 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
5309 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
5310 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
5311 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
5312 //subgroupOr(val) -> (val & exec) != 0
5313 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
5314 return bool_to_vector_condition(ctx
, tmp
);
5315 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
5316 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
5317 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5318 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
5319 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
5320 return bool_to_vector_condition(ctx
, tmp
);
5322 //subgroupClustered{And,Or,Xor}(val, n) ->
5323 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
5324 //cluster_offset = ~(n - 1) & lane_id
5325 //cluster_mask = ((1 << n) - 1)
5326 //subgroupClusteredAnd():
5327 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
5328 //subgroupClusteredOr():
5329 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
5330 //subgroupClusteredXor():
5331 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
5332 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
5333 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
5336 if (op
== nir_op_iand
)
5337 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5339 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5341 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
5343 if (ctx
->program
->chip_class
<= GFX7
)
5344 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
5345 else if (ctx
->program
->wave_size
== 64)
5346 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
5348 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
5349 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
5350 if (cluster_mask
!= 0xffffffff)
5351 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
5353 Definition cmp_def
= Definition();
5354 if (op
== nir_op_iand
) {
5355 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
5356 } else if (op
== nir_op_ior
) {
5357 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
5358 } else if (op
== nir_op_ixor
) {
5359 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
5360 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
5361 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
5363 cmp_def
.setHint(vcc
);
5364 return cmp_def
.getTemp();
5368 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
5370 Builder
bld(ctx
->program
, ctx
->block
);
5372 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
5373 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
5374 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
5376 if (op
== nir_op_iand
)
5377 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
5379 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5381 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
5382 Temp lo
= lohi
.def(0).getTemp();
5383 Temp hi
= lohi
.def(1).getTemp();
5384 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
5386 Definition cmp_def
= Definition();
5387 if (op
== nir_op_iand
)
5388 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
5389 else if (op
== nir_op_ior
)
5390 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
5391 else if (op
== nir_op_ixor
)
5392 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
5393 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
5394 cmp_def
.setHint(vcc
);
5395 return cmp_def
.getTemp();
5398 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
5400 Builder
bld(ctx
->program
, ctx
->block
);
5402 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
5403 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
5404 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
5405 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
5406 if (op
== nir_op_iand
)
5407 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
5408 else if (op
== nir_op_ior
)
5409 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
5410 else if (op
== nir_op_ixor
)
5411 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
5417 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
5419 Builder
bld(ctx
->program
, ctx
->block
);
5420 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
5421 if (src
.regClass().type() == RegType::vgpr
) {
5422 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
5423 } else if (src
.regClass() == s1
) {
5424 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
5425 } else if (src
.regClass() == s2
) {
5426 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
5428 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
5429 nir_print_instr(&instr
->instr
, stderr
);
5430 fprintf(stderr
, "\n");
5434 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
5436 Builder
bld(ctx
->program
, ctx
->block
);
5437 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
5438 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
5439 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
5441 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
5442 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
5443 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
5444 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
5447 if (ctx
->program
->chip_class
>= GFX8
) {
5448 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
5449 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
5450 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
5451 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
5452 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
5453 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
5455 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
5456 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
5457 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
5458 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
5459 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
5460 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
5461 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
5462 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
5463 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
5464 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
5467 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
5468 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
5469 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
5470 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
5471 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
5472 Temp wqm1
= bld
.tmp(v1
);
5473 emit_wqm(ctx
, tmp1
, wqm1
, true);
5474 Temp wqm2
= bld
.tmp(v1
);
5475 emit_wqm(ctx
, tmp2
, wqm2
, true);
5476 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
5480 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5482 Builder
bld(ctx
->program
, ctx
->block
);
5483 switch(instr
->intrinsic
) {
5484 case nir_intrinsic_load_barycentric_sample
:
5485 case nir_intrinsic_load_barycentric_pixel
:
5486 case nir_intrinsic_load_barycentric_centroid
: {
5487 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
5488 Temp bary
= Temp(0, s2
);
5490 case INTERP_MODE_SMOOTH
:
5491 case INTERP_MODE_NONE
:
5492 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
5493 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
5494 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
5495 bary
= ctx
->persp_centroid
;
5496 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
5497 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
5499 case INTERP_MODE_NOPERSPECTIVE
:
5500 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
5501 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
5502 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
5503 bary
= ctx
->linear_centroid
;
5504 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
5505 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
5510 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5511 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
5512 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
5513 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5514 Operand(p1
), Operand(p2
));
5515 emit_split_vector(ctx
, dst
, 2);
5518 case nir_intrinsic_load_barycentric_at_sample
: {
5519 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
5520 switch (ctx
->options
->key
.fs
.num_samples
) {
5521 case 2: sample_pos_offset
+= 1 << 3; break;
5522 case 4: sample_pos_offset
+= 3 << 3; break;
5523 case 8: sample_pos_offset
+= 7 << 3; break;
5527 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5528 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
5529 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
5530 if (addr
.type() == RegType::sgpr
) {
5533 sample_pos_offset
+= const_addr
->u32
<< 3;
5534 offset
= Operand(sample_pos_offset
);
5535 } else if (ctx
->options
->chip_class
>= GFX9
) {
5536 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
5538 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
5539 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
5541 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, Operand(offset
));
5543 } else if (ctx
->options
->chip_class
>= GFX9
) {
5544 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
5545 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
5547 /* addr += private_segment_buffer + sample_pos_offset */
5548 Temp tmp0
= bld
.tmp(s1
);
5549 Temp tmp1
= bld
.tmp(s1
);
5550 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
5551 Definition scc_tmp
= bld
.def(s1
, scc
);
5552 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
5553 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
5554 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
5555 Temp pck0
= bld
.tmp(v1
);
5556 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
5557 tmp1
= as_vgpr(ctx
, tmp1
);
5558 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
5559 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
5561 /* sample_pos = flat_load_dwordx2 addr */
5562 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
5565 /* sample_pos -= 0.5 */
5566 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
5567 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
5568 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
5569 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
5570 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
5572 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
5575 case nir_intrinsic_load_barycentric_at_offset
: {
5576 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5577 RegClass rc
= RegClass(offset
.type(), 1);
5578 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
5579 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
5580 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
5583 case nir_intrinsic_load_front_face
: {
5584 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
5585 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
5588 case nir_intrinsic_load_view_index
:
5589 case nir_intrinsic_load_layer_id
: {
5590 if (instr
->intrinsic
== nir_intrinsic_load_view_index
&& (ctx
->stage
& sw_vs
)) {
5591 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5592 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
5596 unsigned idx
= nir_intrinsic_base(instr
);
5597 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
5598 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
5601 case nir_intrinsic_load_frag_coord
: {
5602 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
5605 case nir_intrinsic_load_sample_pos
: {
5606 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
5607 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
5608 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
5609 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
5610 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
5613 case nir_intrinsic_load_interpolated_input
:
5614 visit_load_interpolated_input(ctx
, instr
);
5616 case nir_intrinsic_store_output
:
5617 visit_store_output(ctx
, instr
);
5619 case nir_intrinsic_load_input
:
5620 visit_load_input(ctx
, instr
);
5622 case nir_intrinsic_load_ubo
:
5623 visit_load_ubo(ctx
, instr
);
5625 case nir_intrinsic_load_push_constant
:
5626 visit_load_push_constant(ctx
, instr
);
5628 case nir_intrinsic_load_constant
:
5629 visit_load_constant(ctx
, instr
);
5631 case nir_intrinsic_vulkan_resource_index
:
5632 visit_load_resource(ctx
, instr
);
5634 case nir_intrinsic_discard
:
5635 visit_discard(ctx
, instr
);
5637 case nir_intrinsic_discard_if
:
5638 visit_discard_if(ctx
, instr
);
5640 case nir_intrinsic_load_shared
:
5641 visit_load_shared(ctx
, instr
);
5643 case nir_intrinsic_store_shared
:
5644 visit_store_shared(ctx
, instr
);
5646 case nir_intrinsic_shared_atomic_add
:
5647 case nir_intrinsic_shared_atomic_imin
:
5648 case nir_intrinsic_shared_atomic_umin
:
5649 case nir_intrinsic_shared_atomic_imax
:
5650 case nir_intrinsic_shared_atomic_umax
:
5651 case nir_intrinsic_shared_atomic_and
:
5652 case nir_intrinsic_shared_atomic_or
:
5653 case nir_intrinsic_shared_atomic_xor
:
5654 case nir_intrinsic_shared_atomic_exchange
:
5655 case nir_intrinsic_shared_atomic_comp_swap
:
5656 visit_shared_atomic(ctx
, instr
);
5658 case nir_intrinsic_image_deref_load
:
5659 visit_image_load(ctx
, instr
);
5661 case nir_intrinsic_image_deref_store
:
5662 visit_image_store(ctx
, instr
);
5664 case nir_intrinsic_image_deref_atomic_add
:
5665 case nir_intrinsic_image_deref_atomic_umin
:
5666 case nir_intrinsic_image_deref_atomic_imin
:
5667 case nir_intrinsic_image_deref_atomic_umax
:
5668 case nir_intrinsic_image_deref_atomic_imax
:
5669 case nir_intrinsic_image_deref_atomic_and
:
5670 case nir_intrinsic_image_deref_atomic_or
:
5671 case nir_intrinsic_image_deref_atomic_xor
:
5672 case nir_intrinsic_image_deref_atomic_exchange
:
5673 case nir_intrinsic_image_deref_atomic_comp_swap
:
5674 visit_image_atomic(ctx
, instr
);
5676 case nir_intrinsic_image_deref_size
:
5677 visit_image_size(ctx
, instr
);
5679 case nir_intrinsic_load_ssbo
:
5680 visit_load_ssbo(ctx
, instr
);
5682 case nir_intrinsic_store_ssbo
:
5683 visit_store_ssbo(ctx
, instr
);
5685 case nir_intrinsic_load_global
:
5686 visit_load_global(ctx
, instr
);
5688 case nir_intrinsic_store_global
:
5689 visit_store_global(ctx
, instr
);
5691 case nir_intrinsic_global_atomic_add
:
5692 case nir_intrinsic_global_atomic_imin
:
5693 case nir_intrinsic_global_atomic_umin
:
5694 case nir_intrinsic_global_atomic_imax
:
5695 case nir_intrinsic_global_atomic_umax
:
5696 case nir_intrinsic_global_atomic_and
:
5697 case nir_intrinsic_global_atomic_or
:
5698 case nir_intrinsic_global_atomic_xor
:
5699 case nir_intrinsic_global_atomic_exchange
:
5700 case nir_intrinsic_global_atomic_comp_swap
:
5701 visit_global_atomic(ctx
, instr
);
5703 case nir_intrinsic_ssbo_atomic_add
:
5704 case nir_intrinsic_ssbo_atomic_imin
:
5705 case nir_intrinsic_ssbo_atomic_umin
:
5706 case nir_intrinsic_ssbo_atomic_imax
:
5707 case nir_intrinsic_ssbo_atomic_umax
:
5708 case nir_intrinsic_ssbo_atomic_and
:
5709 case nir_intrinsic_ssbo_atomic_or
:
5710 case nir_intrinsic_ssbo_atomic_xor
:
5711 case nir_intrinsic_ssbo_atomic_exchange
:
5712 case nir_intrinsic_ssbo_atomic_comp_swap
:
5713 visit_atomic_ssbo(ctx
, instr
);
5715 case nir_intrinsic_load_scratch
:
5716 visit_load_scratch(ctx
, instr
);
5718 case nir_intrinsic_store_scratch
:
5719 visit_store_scratch(ctx
, instr
);
5721 case nir_intrinsic_get_buffer_size
:
5722 visit_get_buffer_size(ctx
, instr
);
5724 case nir_intrinsic_control_barrier
: {
5725 unsigned* bsize
= ctx
->program
->info
->cs
.block_size
;
5726 unsigned workgroup_size
= bsize
[0] * bsize
[1] * bsize
[2];
5727 if (workgroup_size
> ctx
->program
->wave_size
)
5728 bld
.sopp(aco_opcode::s_barrier
);
5731 case nir_intrinsic_group_memory_barrier
:
5732 case nir_intrinsic_memory_barrier
:
5733 case nir_intrinsic_memory_barrier_buffer
:
5734 case nir_intrinsic_memory_barrier_image
:
5735 case nir_intrinsic_memory_barrier_shared
:
5736 emit_memory_barrier(ctx
, instr
);
5738 case nir_intrinsic_memory_barrier_tcs_patch
:
5740 case nir_intrinsic_load_num_work_groups
: {
5741 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5742 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
5743 emit_split_vector(ctx
, dst
, 3);
5746 case nir_intrinsic_load_local_invocation_id
: {
5747 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5748 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
5749 emit_split_vector(ctx
, dst
, 3);
5752 case nir_intrinsic_load_work_group_id
: {
5753 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5754 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
5755 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5756 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
5757 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
5758 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
5759 emit_split_vector(ctx
, dst
, 3);
5762 case nir_intrinsic_load_local_invocation_index
: {
5763 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
5765 /* The tg_size bits [6:11] contain the subgroup id,
5766 * we need this multiplied by the wave size, and then OR the thread id to it.
5768 if (ctx
->program
->wave_size
== 64) {
5769 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
5770 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
5771 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
5772 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
5774 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
5775 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
5776 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
5777 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
5781 case nir_intrinsic_load_subgroup_id
: {
5782 if (ctx
->stage
== compute_cs
) {
5783 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
5784 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
5786 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
5790 case nir_intrinsic_load_subgroup_invocation
: {
5791 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
5794 case nir_intrinsic_load_num_subgroups
: {
5795 if (ctx
->stage
== compute_cs
)
5796 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
5797 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
5799 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
5802 case nir_intrinsic_ballot
: {
5803 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5804 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5805 Definition tmp
= bld
.def(dst
.regClass());
5806 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
5807 if (instr
->src
[0].ssa
->bit_size
== 1) {
5808 assert(src
.regClass() == bld
.lm
);
5809 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
5810 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
5811 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
5812 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
5813 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
5815 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
5816 nir_print_instr(&instr
->instr
, stderr
);
5817 fprintf(stderr
, "\n");
5819 if (dst
.size() != bld
.lm
.size()) {
5820 /* Wave32 with ballot size set to 64 */
5821 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
5823 emit_wqm(ctx
, tmp
.getTemp(), dst
);
5826 case nir_intrinsic_shuffle
:
5827 case nir_intrinsic_read_invocation
: {
5828 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5829 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
5830 emit_uniform_subgroup(ctx
, instr
, src
);
5832 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5833 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
5834 tid
= bld
.as_uniform(tid
);
5835 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5836 if (src
.regClass() == v1
) {
5837 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
5838 } else if (src
.regClass() == v2
) {
5839 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
5840 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
5841 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
5842 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
5843 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
5844 emit_split_vector(ctx
, dst
, 2);
5845 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
5846 assert(src
.regClass() == bld
.lm
);
5847 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
5848 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
5849 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
5850 assert(src
.regClass() == bld
.lm
);
5852 if (ctx
->program
->chip_class
<= GFX7
)
5853 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
5854 else if (ctx
->program
->wave_size
== 64)
5855 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
5857 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
5858 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
5859 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
5860 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
5862 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
5863 nir_print_instr(&instr
->instr
, stderr
);
5864 fprintf(stderr
, "\n");
5869 case nir_intrinsic_load_sample_id
: {
5870 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
5871 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
5874 case nir_intrinsic_load_sample_mask_in
: {
5875 visit_load_sample_mask_in(ctx
, instr
);
5878 case nir_intrinsic_read_first_invocation
: {
5879 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5880 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5881 if (src
.regClass() == v1
) {
5883 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
5885 } else if (src
.regClass() == v2
) {
5886 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
5887 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
5888 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
5889 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
5890 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
5891 emit_split_vector(ctx
, dst
, 2);
5892 } else if (instr
->dest
.ssa
.bit_size
== 1) {
5893 assert(src
.regClass() == bld
.lm
);
5894 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
5895 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
5896 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
5897 } else if (src
.regClass() == s1
) {
5898 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
5899 } else if (src
.regClass() == s2
) {
5900 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
5902 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
5903 nir_print_instr(&instr
->instr
, stderr
);
5904 fprintf(stderr
, "\n");
5908 case nir_intrinsic_vote_all
: {
5909 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5910 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5911 assert(src
.regClass() == bld
.lm
);
5912 assert(dst
.regClass() == bld
.lm
);
5914 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
5915 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
5916 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
5919 case nir_intrinsic_vote_any
: {
5920 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5921 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5922 assert(src
.regClass() == bld
.lm
);
5923 assert(dst
.regClass() == bld
.lm
);
5925 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
5926 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
5929 case nir_intrinsic_reduce
:
5930 case nir_intrinsic_inclusive_scan
:
5931 case nir_intrinsic_exclusive_scan
: {
5932 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5933 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5934 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
5935 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
5936 nir_intrinsic_cluster_size(instr
) : 0;
5937 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
5939 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
5940 emit_uniform_subgroup(ctx
, instr
, src
);
5941 } else if (instr
->dest
.ssa
.bit_size
== 1) {
5942 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
5944 else if (op
== nir_op_iadd
)
5946 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
5948 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
5950 switch (instr
->intrinsic
) {
5951 case nir_intrinsic_reduce
:
5952 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
5954 case nir_intrinsic_exclusive_scan
:
5955 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
5957 case nir_intrinsic_inclusive_scan
:
5958 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
5963 } else if (cluster_size
== 1) {
5964 bld
.copy(Definition(dst
), src
);
5966 src
= as_vgpr(ctx
, src
);
5970 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
5985 unreachable("unknown reduction op");
5990 switch (instr
->intrinsic
) {
5991 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
5992 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
5993 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
5995 unreachable("unknown reduce intrinsic");
5998 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
5999 reduce
->operands
[0] = Operand(src
);
6000 // filled in by aco_reduce_assign.cpp, used internally as part of the
6002 assert(dst
.size() == 1 || dst
.size() == 2);
6003 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
6004 reduce
->operands
[2] = Operand(v1
.as_linear());
6006 Temp tmp_dst
= bld
.tmp(dst
.regClass());
6007 reduce
->definitions
[0] = Definition(tmp_dst
);
6008 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
6009 reduce
->definitions
[2] = Definition();
6010 reduce
->definitions
[3] = Definition(scc
, s1
);
6011 reduce
->definitions
[4] = Definition();
6012 reduce
->reduce_op
= reduce_op
;
6013 reduce
->cluster_size
= cluster_size
;
6014 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
6016 emit_wqm(ctx
, tmp_dst
, dst
);
6020 case nir_intrinsic_quad_broadcast
: {
6021 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6022 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
6023 emit_uniform_subgroup(ctx
, instr
, src
);
6025 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6026 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
6027 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
6029 if (instr
->dest
.ssa
.bit_size
== 1) {
6030 assert(src
.regClass() == bld
.lm
);
6031 assert(dst
.regClass() == bld
.lm
);
6032 uint32_t half_mask
= 0x11111111u
<< lane
;
6033 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
6034 Temp tmp
= bld
.tmp(bld
.lm
);
6035 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
6036 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
6037 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
6038 emit_wqm(ctx
, tmp
, dst
);
6039 } else if (instr
->dest
.ssa
.bit_size
== 32) {
6040 if (ctx
->program
->chip_class
>= GFX8
)
6041 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
6043 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
6044 } else if (instr
->dest
.ssa
.bit_size
== 64) {
6045 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
6046 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
6047 if (ctx
->program
->chip_class
>= GFX8
) {
6048 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
6049 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
6051 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
6052 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
6054 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6055 emit_split_vector(ctx
, dst
, 2);
6057 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6058 nir_print_instr(&instr
->instr
, stderr
);
6059 fprintf(stderr
, "\n");
6064 case nir_intrinsic_quad_swap_horizontal
:
6065 case nir_intrinsic_quad_swap_vertical
:
6066 case nir_intrinsic_quad_swap_diagonal
:
6067 case nir_intrinsic_quad_swizzle_amd
: {
6068 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6069 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
6070 emit_uniform_subgroup(ctx
, instr
, src
);
6073 uint16_t dpp_ctrl
= 0;
6074 switch (instr
->intrinsic
) {
6075 case nir_intrinsic_quad_swap_horizontal
:
6076 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
6078 case nir_intrinsic_quad_swap_vertical
:
6079 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
6081 case nir_intrinsic_quad_swap_diagonal
:
6082 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
6084 case nir_intrinsic_quad_swizzle_amd
:
6085 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
6090 if (ctx
->program
->chip_class
< GFX8
)
6091 dpp_ctrl
|= (1 << 15);
6093 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6094 if (instr
->dest
.ssa
.bit_size
== 1) {
6095 assert(src
.regClass() == bld
.lm
);
6096 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
6097 if (ctx
->program
->chip_class
>= GFX8
)
6098 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
6100 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
6101 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
6102 emit_wqm(ctx
, tmp
, dst
);
6103 } else if (instr
->dest
.ssa
.bit_size
== 32) {
6105 if (ctx
->program
->chip_class
>= GFX8
)
6106 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
6108 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
6109 emit_wqm(ctx
, tmp
, dst
);
6110 } else if (instr
->dest
.ssa
.bit_size
== 64) {
6111 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
6112 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
6113 if (ctx
->program
->chip_class
>= GFX8
) {
6114 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
6115 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
6117 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
6118 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
6120 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6121 emit_split_vector(ctx
, dst
, 2);
6123 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6124 nir_print_instr(&instr
->instr
, stderr
);
6125 fprintf(stderr
, "\n");
6129 case nir_intrinsic_masked_swizzle_amd
: {
6130 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6131 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
6132 emit_uniform_subgroup(ctx
, instr
, src
);
6135 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6136 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
6137 if (dst
.regClass() == v1
) {
6139 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
6141 } else if (dst
.regClass() == v2
) {
6142 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
6143 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
6144 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
6145 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
6146 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6147 emit_split_vector(ctx
, dst
, 2);
6149 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6150 nir_print_instr(&instr
->instr
, stderr
);
6151 fprintf(stderr
, "\n");
6155 case nir_intrinsic_write_invocation_amd
: {
6156 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6157 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6158 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6159 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6160 if (dst
.regClass() == v1
) {
6161 /* src2 is ignored for writelane. RA assigns the same reg for dst */
6162 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
6163 } else if (dst
.regClass() == v2
) {
6164 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
6165 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
6166 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
6167 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
6168 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
6169 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
6170 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6171 emit_split_vector(ctx
, dst
, 2);
6173 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6174 nir_print_instr(&instr
->instr
, stderr
);
6175 fprintf(stderr
, "\n");
6179 case nir_intrinsic_mbcnt_amd
: {
6180 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6181 RegClass rc
= RegClass(src
.type(), 1);
6182 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
6183 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
6184 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6185 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
6186 emit_wqm(ctx
, wqm_tmp
, dst
);
6189 case nir_intrinsic_load_helper_invocation
: {
6190 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6191 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
6192 ctx
->block
->kind
|= block_kind_needs_lowering
;
6193 ctx
->program
->needs_exact
= true;
6196 case nir_intrinsic_is_helper_invocation
: {
6197 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6198 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
6199 ctx
->block
->kind
|= block_kind_needs_lowering
;
6200 ctx
->program
->needs_exact
= true;
6203 case nir_intrinsic_demote
:
6204 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
6206 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
6207 ctx
->cf_info
.exec_potentially_empty
= true;
6208 ctx
->block
->kind
|= block_kind_uses_demote
;
6209 ctx
->program
->needs_exact
= true;
6211 case nir_intrinsic_demote_if
: {
6212 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6213 assert(src
.regClass() == bld
.lm
);
6214 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6215 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
6217 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
6218 ctx
->cf_info
.exec_potentially_empty
= true;
6219 ctx
->block
->kind
|= block_kind_uses_demote
;
6220 ctx
->program
->needs_exact
= true;
6223 case nir_intrinsic_first_invocation
: {
6224 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
6225 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6228 case nir_intrinsic_shader_clock
:
6229 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
6230 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
6232 case nir_intrinsic_load_vertex_id_zero_base
: {
6233 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6234 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
6237 case nir_intrinsic_load_first_vertex
: {
6238 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6239 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
6242 case nir_intrinsic_load_base_instance
: {
6243 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6244 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
6247 case nir_intrinsic_load_instance_id
: {
6248 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6249 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
6252 case nir_intrinsic_load_draw_id
: {
6253 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6254 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
6258 fprintf(stderr
, "Unimplemented intrinsic instr: ");
6259 nir_print_instr(&instr
->instr
, stderr
);
6260 fprintf(stderr
, "\n");
6268 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
6269 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
6270 enum glsl_base_type
*stype
)
6272 nir_deref_instr
*texture_deref_instr
= NULL
;
6273 nir_deref_instr
*sampler_deref_instr
= NULL
;
6276 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
6277 switch (instr
->src
[i
].src_type
) {
6278 case nir_tex_src_texture_deref
:
6279 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
6281 case nir_tex_src_sampler_deref
:
6282 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
6284 case nir_tex_src_plane
:
6285 plane
= nir_src_as_int(instr
->src
[i
].src
);
6292 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
6294 if (!sampler_deref_instr
)
6295 sampler_deref_instr
= texture_deref_instr
;
6298 assert(instr
->op
!= nir_texop_txf_ms
&&
6299 instr
->op
!= nir_texop_samples_identical
);
6300 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
6301 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
6302 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
6303 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
6305 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
6308 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
6310 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
6311 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
6312 Builder
bld(ctx
->program
, ctx
->block
);
6314 /* to avoid unnecessary moves, we split and recombine sampler and image */
6315 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
6316 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
6317 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
6318 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
6319 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
6320 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
6321 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
6322 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
6324 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
6325 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
6326 img
[0], img
[1], img
[2], img
[3],
6327 img
[4], img
[5], img
[6], img
[7]);
6328 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6329 samp
[0], samp
[1], samp
[2], samp
[3]);
6332 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
6333 instr
->op
== nir_texop_samples_identical
))
6334 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
6337 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
6338 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
6340 Builder
bld(ctx
->program
, ctx
->block
);
6342 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
6343 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
6344 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
6346 Operand
neg_one(0xbf800000u
);
6347 Operand
one(0x3f800000u
);
6348 Operand
two(0x40000000u
);
6349 Operand
four(0x40800000u
);
6351 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
6352 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
6353 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
6355 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
6356 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
6357 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
6358 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
6361 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
6362 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
6363 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
6365 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
6368 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
6369 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
6370 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
6373 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
6374 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
6376 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
6377 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
6380 void prepare_cube_coords(isel_context
*ctx
, Temp
* coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
6382 Builder
bld(ctx
->program
, ctx
->block
);
6383 Temp coord_args
[4], ma
, tc
, sc
, id
;
6384 for (unsigned i
= 0; i
< (is_array
? 4 : 3); i
++)
6385 coord_args
[i
] = emit_extract_vector(ctx
, *coords
, i
, v1
);
6388 coord_args
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coord_args
[3]);
6390 // see comment in ac_prepare_cube_coords()
6391 if (ctx
->options
->chip_class
<= GFX8
)
6392 coord_args
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coord_args
[3]);
6395 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6397 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
6398 vop3a
->operands
[0] = Operand(ma
);
6399 vop3a
->abs
[0] = true;
6400 Temp invma
= bld
.tmp(v1
);
6401 vop3a
->definitions
[0] = Definition(invma
);
6402 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
6404 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6406 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
6408 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6410 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
6412 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6415 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
6416 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
6418 for (unsigned i
= 0; i
< 2; i
++) {
6419 // see comment in ac_prepare_cube_coords()
6421 Temp deriv_sc
, deriv_tc
;
6422 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
6423 &deriv_ma
, &deriv_sc
, &deriv_tc
);
6425 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
6427 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
6428 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
6429 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
6430 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
6431 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
6432 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
6433 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
6436 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
6437 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
6441 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coord_args
[3], id
, Operand(0x41000000u
/*8.0*/));
6442 *coords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), sc
, tc
, id
);
6446 Temp
apply_round_slice(isel_context
*ctx
, Temp coords
, unsigned idx
)
6449 for (unsigned i
= 0; i
< coords
.size(); i
++)
6450 coord_vec
[i
] = emit_extract_vector(ctx
, coords
, i
, v1
);
6452 Builder
bld(ctx
->program
, ctx
->block
);
6453 coord_vec
[idx
] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coord_vec
[idx
]);
6455 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
6456 for (unsigned i
= 0; i
< coords
.size(); i
++)
6457 vec
->operands
[i
] = Operand(coord_vec
[i
]);
6458 Temp res
= bld
.tmp(RegType::vgpr
, coords
.size());
6459 vec
->definitions
[0] = Definition(res
);
6460 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6464 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
6466 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
6468 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
6469 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
6472 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
6473 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
6474 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
6478 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
6480 Builder
bld(ctx
->program
, ctx
->block
);
6481 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
6482 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
6483 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), coords
, compare
= Temp(), sample_index
= Temp(),
6484 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(), derivs
= Temp();
6485 nir_const_value
*sample_index_cv
= NULL
;
6486 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
6487 enum glsl_base_type stype
;
6488 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
6490 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
6491 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
6492 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
6493 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
6495 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
6496 switch (instr
->src
[i
].src_type
) {
6497 case nir_tex_src_coord
:
6498 coords
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
));
6500 case nir_tex_src_bias
:
6501 if (instr
->op
== nir_texop_txb
) {
6502 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6506 case nir_tex_src_lod
: {
6507 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
6509 if (val
&& val
->f32
<= 0.0) {
6512 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6517 case nir_tex_src_comparator
:
6518 if (instr
->is_shadow
) {
6519 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6523 case nir_tex_src_offset
:
6524 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6525 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
6528 case nir_tex_src_ddx
:
6529 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6532 case nir_tex_src_ddy
:
6533 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6536 case nir_tex_src_ms_index
:
6537 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6538 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
6539 has_sample_index
= true;
6541 case nir_tex_src_texture_offset
:
6542 case nir_tex_src_sampler_offset
:
6547 // TODO: all other cases: structure taken from ac_nir_to_llvm.c
6548 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
6549 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6551 if (instr
->op
== nir_texop_texture_samples
) {
6552 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
6554 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
6555 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
6556 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
6557 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
6559 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
6560 samples
, Operand(1u), bld
.scc(is_msaa
));
6564 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
6565 aco_ptr
<Instruction
> tmp_instr
;
6566 Temp acc
, pack
= Temp();
6568 uint32_t pack_const
= 0;
6569 for (unsigned i
= 0; i
< offset
.size(); i
++) {
6570 if (!const_offset
[i
])
6572 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
6575 if (offset
.type() == RegType::sgpr
) {
6576 for (unsigned i
= 0; i
< offset
.size(); i
++) {
6577 if (const_offset
[i
])
6580 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
6581 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
6584 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
6587 if (pack
== Temp()) {
6590 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
6594 if (pack_const
&& pack
!= Temp())
6595 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
6597 for (unsigned i
= 0; i
< offset
.size(); i
++) {
6598 if (const_offset
[i
])
6601 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
6602 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
6605 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
6608 if (pack
== Temp()) {
6611 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
6615 if (pack_const
&& pack
!= Temp())
6616 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
6618 if (pack_const
&& pack
== Temp())
6619 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
6620 else if (pack
== Temp())
6626 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
6627 prepare_cube_coords(ctx
, &coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
6629 /* pack derivatives */
6630 if (has_ddx
|| has_ddy
) {
6631 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
6632 derivs
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v4
),
6633 ddx
, Operand(0u), ddy
, Operand(0u));
6635 derivs
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, ddx
.size() + ddy
.size()), ddx
, ddy
);
6640 if (instr
->coord_components
> 1 &&
6641 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
6643 instr
->op
!= nir_texop_txf
)
6644 coords
= apply_round_slice(ctx
, coords
, 1);
6646 if (instr
->coord_components
> 2 &&
6647 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
6648 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
6649 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
6650 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
6652 instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
)
6653 coords
= apply_round_slice(ctx
, coords
, 2);
6655 if (ctx
->options
->chip_class
== GFX9
&&
6656 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
6657 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
6658 assert(coords
.size() > 0 && coords
.size() < 3);
6660 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size() + 1, 1)};
6661 vec
->operands
[0] = Operand(emit_extract_vector(ctx
, coords
, 0, v1
));
6662 vec
->operands
[1] = instr
->op
== nir_texop_txf
? Operand((uint32_t) 0) : Operand((uint32_t) 0x3f000000);
6663 if (coords
.size() > 1)
6664 vec
->operands
[2] = Operand(emit_extract_vector(ctx
, coords
, 1, v1
));
6665 coords
= bld
.tmp(RegType::vgpr
, coords
.size() + 1);
6666 vec
->definitions
[0] = Definition(coords
);
6667 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6670 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
6672 if (instr
->op
== nir_texop_samples_identical
)
6673 resource
= fmask_ptr
;
6675 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
6676 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
6677 instr
->op
!= nir_texop_txs
) {
6678 assert(has_sample_index
);
6679 Operand
op(sample_index
);
6680 if (sample_index_cv
)
6681 op
= Operand(sample_index_cv
->u32
);
6682 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
6685 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
6686 Temp split_coords
[coords
.size()];
6687 emit_split_vector(ctx
, coords
, coords
.size());
6688 for (unsigned i
= 0; i
< coords
.size(); i
++)
6689 split_coords
[i
] = emit_extract_vector(ctx
, coords
, i
, v1
);
6692 for (; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
6693 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
6694 split_coords
[i
] = bld
.vadd32(bld
.def(v1
), split_coords
[i
], off
);
6697 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
6698 for (unsigned i
= 0; i
< coords
.size(); i
++)
6699 vec
->operands
[i
] = Operand(split_coords
[i
]);
6700 coords
= bld
.tmp(coords
.regClass());
6701 vec
->definitions
[0] = Definition(coords
);
6702 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6707 /* Build tex instruction */
6708 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
6709 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
6710 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
6712 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6715 /* gather4 selects the component by dmask and always returns vec4 */
6716 if (instr
->op
== nir_texop_tg4
) {
6717 assert(instr
->dest
.ssa
.num_components
== 4);
6718 if (instr
->is_shadow
)
6721 dmask
= 1 << instr
->component
;
6722 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
6723 tmp_dst
= bld
.tmp(v4
);
6724 } else if (instr
->op
== nir_texop_samples_identical
) {
6725 tmp_dst
= bld
.tmp(v1
);
6726 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
6727 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
6730 aco_ptr
<MIMG_instruction
> tex
;
6731 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
6733 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6735 bool div_by_6
= instr
->op
== nir_texop_txs
&&
6736 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
6739 if (tmp_dst
.id() == dst
.id() && div_by_6
)
6740 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
6742 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 2, 1));
6743 tex
->operands
[0] = Operand(as_vgpr(ctx
,lod
));
6744 tex
->operands
[1] = Operand(resource
);
6745 if (ctx
->options
->chip_class
== GFX9
&&
6746 instr
->op
== nir_texop_txs
&&
6747 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
6749 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
6750 } else if (instr
->op
== nir_texop_query_levels
) {
6751 tex
->dmask
= 1 << 3;
6756 tex
->definitions
[0] = Definition(tmp_dst
);
6758 tex
->can_reorder
= true;
6759 ctx
->block
->instructions
.emplace_back(std::move(tex
));
6762 /* divide 3rd value by 6 by multiplying with magic number */
6763 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
6764 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6765 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
6766 assert(instr
->dest
.ssa
.num_components
== 3);
6767 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
6768 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
6769 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
6770 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
6775 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
6779 Temp tg4_compare_cube_wa64
= Temp();
6781 if (tg4_integer_workarounds
) {
6782 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 2, 1));
6783 tex
->operands
[0] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6784 tex
->operands
[1] = Operand(resource
);
6788 Temp size
= bld
.tmp(v2
);
6789 tex
->definitions
[0] = Definition(size
);
6790 tex
->can_reorder
= true;
6791 ctx
->block
->instructions
.emplace_back(std::move(tex
));
6792 emit_split_vector(ctx
, size
, size
.size());
6795 for (unsigned i
= 0; i
< 2; i
++) {
6796 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
6797 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
6798 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
6799 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
6802 Temp orig_coords
[2] = {
6803 emit_extract_vector(ctx
, coords
, 0, v1
),
6804 emit_extract_vector(ctx
, coords
, 1, v1
)};
6805 Temp new_coords
[2] = {
6806 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), orig_coords
[0], half_texel
[0]),
6807 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), orig_coords
[1], half_texel
[1])
6810 if (tg4_integer_cube_workaround
) {
6811 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
6812 Temp desc
[resource
.size()];
6813 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
6814 Format::PSEUDO
, 1, resource
.size())};
6815 split
->operands
[0] = Operand(resource
);
6816 for (unsigned i
= 0; i
< resource
.size(); i
++) {
6817 desc
[i
] = bld
.tmp(s1
);
6818 split
->definitions
[i
] = Definition(desc
[i
]);
6820 ctx
->block
->instructions
.emplace_back(std::move(split
));
6822 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
6823 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
6824 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
6827 if (stype
== GLSL_TYPE_UINT
) {
6828 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
6829 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
6830 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
6831 bld
.scc(compare_cube_wa
));
6833 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
6834 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
6835 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
6836 bld
.scc(compare_cube_wa
));
6838 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
6839 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
6841 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
6843 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
6844 Operand((uint32_t)C_008F14_NUM_FORMAT
));
6845 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
6847 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6848 Format::PSEUDO
, resource
.size(), 1)};
6849 for (unsigned i
= 0; i
< resource
.size(); i
++)
6850 vec
->operands
[i
] = Operand(desc
[i
]);
6851 resource
= bld
.tmp(resource
.regClass());
6852 vec
->definitions
[0] = Definition(resource
);
6853 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6855 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
6856 new_coords
[0], orig_coords
[0], tg4_compare_cube_wa64
);
6857 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
6858 new_coords
[1], orig_coords
[1], tg4_compare_cube_wa64
);
6861 if (coords
.size() == 3) {
6862 coords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
),
6863 new_coords
[0], new_coords
[1],
6864 emit_extract_vector(ctx
, coords
, 2, v1
));
6866 assert(coords
.size() == 2);
6867 coords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
),
6868 new_coords
[0], new_coords
[1]);
6872 std::vector
<Operand
> args
;
6874 args
.emplace_back(Operand(offset
));
6876 args
.emplace_back(Operand(bias
));
6878 args
.emplace_back(Operand(compare
));
6880 args
.emplace_back(Operand(derivs
));
6881 args
.emplace_back(Operand(coords
));
6882 if (has_sample_index
)
6883 args
.emplace_back(Operand(sample_index
));
6885 args
.emplace_back(lod
);
6888 if (args
.size() > 1) {
6889 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
6891 for (unsigned i
= 0; i
< args
.size(); i
++) {
6892 size
+= args
[i
].size();
6893 vec
->operands
[i
] = args
[i
];
6895 RegClass rc
= RegClass(RegType::vgpr
, size
);
6896 Temp tmp
= bld
.tmp(rc
);
6897 vec
->definitions
[0] = Definition(tmp
);
6898 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6901 assert(args
[0].isTemp());
6902 arg
= as_vgpr(ctx
, args
[0].getTemp());
6905 /* we don't need the bias, sample index, compare value or offset to be
6906 * computed in WQM but if the p_create_vector copies the coordinates, then it
6907 * needs to be in WQM */
6908 if (!(has_ddx
&& has_ddy
) && !has_lod
&& !level_zero
&&
6909 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
6910 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
6911 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
6913 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
6914 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
6916 assert(coords
.size() == 1);
6917 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
6921 op
= aco_opcode::buffer_load_format_x
; break;
6923 op
= aco_opcode::buffer_load_format_xy
; break;
6925 op
= aco_opcode::buffer_load_format_xyz
; break;
6927 op
= aco_opcode::buffer_load_format_xyzw
; break;
6929 unreachable("Tex instruction loads more than 4 components.");
6932 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
6933 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
6936 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
6938 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6939 mubuf
->operands
[0] = Operand(coords
);
6940 mubuf
->operands
[1] = Operand(resource
);
6941 mubuf
->operands
[2] = Operand((uint32_t) 0);
6942 mubuf
->definitions
[0] = Definition(tmp_dst
);
6943 mubuf
->idxen
= true;
6944 mubuf
->can_reorder
= true;
6945 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6947 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
6952 if (instr
->op
== nir_texop_txf
||
6953 instr
->op
== nir_texop_txf_ms
||
6954 instr
->op
== nir_texop_samples_identical
) {
6955 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
6956 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 2, 1));
6957 tex
->operands
[0] = Operand(arg
);
6958 tex
->operands
[1] = Operand(resource
);
6963 tex
->definitions
[0] = Definition(tmp_dst
);
6964 tex
->can_reorder
= true;
6965 ctx
->block
->instructions
.emplace_back(std::move(tex
));
6967 if (instr
->op
== nir_texop_samples_identical
) {
6968 assert(dmask
== 1 && dst
.regClass() == v1
);
6969 assert(dst
.id() != tmp_dst
.id());
6971 Temp tmp
= bld
.tmp(bld
.lm
);
6972 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
6973 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
6976 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
6981 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
6982 aco_opcode opcode
= aco_opcode::image_sample
;
6983 if (has_offset
) { /* image_sample_*_o */
6985 opcode
= aco_opcode::image_sample_c_o
;
6987 opcode
= aco_opcode::image_sample_c_d_o
;
6989 opcode
= aco_opcode::image_sample_c_b_o
;
6991 opcode
= aco_opcode::image_sample_c_lz_o
;
6993 opcode
= aco_opcode::image_sample_c_l_o
;
6995 opcode
= aco_opcode::image_sample_o
;
6997 opcode
= aco_opcode::image_sample_d_o
;
6999 opcode
= aco_opcode::image_sample_b_o
;
7001 opcode
= aco_opcode::image_sample_lz_o
;
7003 opcode
= aco_opcode::image_sample_l_o
;
7005 } else { /* no offset */
7007 opcode
= aco_opcode::image_sample_c
;
7009 opcode
= aco_opcode::image_sample_c_d
;
7011 opcode
= aco_opcode::image_sample_c_b
;
7013 opcode
= aco_opcode::image_sample_c_lz
;
7015 opcode
= aco_opcode::image_sample_c_l
;
7017 opcode
= aco_opcode::image_sample
;
7019 opcode
= aco_opcode::image_sample_d
;
7021 opcode
= aco_opcode::image_sample_b
;
7023 opcode
= aco_opcode::image_sample_lz
;
7025 opcode
= aco_opcode::image_sample_l
;
7029 if (instr
->op
== nir_texop_tg4
) {
7031 opcode
= aco_opcode::image_gather4_lz_o
;
7033 opcode
= aco_opcode::image_gather4_c_lz_o
;
7035 opcode
= aco_opcode::image_gather4_lz
;
7037 opcode
= aco_opcode::image_gather4_c_lz
;
7039 } else if (instr
->op
== nir_texop_lod
) {
7040 opcode
= aco_opcode::image_get_lod
;
7043 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
7044 tex
->operands
[0] = Operand(arg
);
7045 tex
->operands
[1] = Operand(resource
);
7046 tex
->operands
[2] = Operand(sampler
);
7050 tex
->definitions
[0] = Definition(tmp_dst
);
7051 tex
->can_reorder
= true;
7052 ctx
->block
->instructions
.emplace_back(std::move(tex
));
7054 if (tg4_integer_cube_workaround
) {
7055 assert(tmp_dst
.id() != dst
.id());
7056 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
7058 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
7060 for (unsigned i
= 0; i
< dst
.size(); i
++) {
7061 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
7063 if (stype
== GLSL_TYPE_UINT
)
7064 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
7066 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
7067 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
7069 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
7070 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
7071 val
[0], val
[1], val
[2], val
[3]);
7073 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
7074 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
7079 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
7081 Temp tmp
= get_ssa_temp(ctx
, ssa
);
7082 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
7083 return Operand(tmp
.regClass());
7085 return Operand(tmp
);
7088 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
7090 aco_ptr
<Pseudo_instruction
> phi
;
7091 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7092 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
7094 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
7095 logical
|= ctx
->block
->kind
& block_kind_merge
;
7096 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
7098 /* we want a sorted list of sources, since the predecessor list is also sorted */
7099 std::map
<unsigned, nir_ssa_def
*> phi_src
;
7100 nir_foreach_phi_src(src
, instr
)
7101 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
7103 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
7104 unsigned num_operands
= 0;
7105 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size())];
7106 unsigned num_defined
= 0;
7107 unsigned cur_pred_idx
= 0;
7108 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
7109 if (cur_pred_idx
< preds
.size()) {
7110 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
7111 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
7112 unsigned skipped
= 0;
7113 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
7115 if (cur_pred_idx
+ skipped
< preds
.size()) {
7116 for (unsigned i
= 0; i
< skipped
; i
++)
7117 operands
[num_operands
++] = Operand(dst
.regClass());
7118 cur_pred_idx
+= skipped
;
7124 Operand op
= get_phi_operand(ctx
, src
.second
);
7125 operands
[num_operands
++] = op
;
7126 num_defined
+= !op
.isUndefined();
7128 /* handle block_kind_continue_or_break at loop exit blocks */
7129 while (cur_pred_idx
++ < preds
.size())
7130 operands
[num_operands
++] = Operand(dst
.regClass());
7132 if (num_defined
== 0) {
7133 Builder
bld(ctx
->program
, ctx
->block
);
7134 if (dst
.regClass() == s1
) {
7135 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
7136 } else if (dst
.regClass() == v1
) {
7137 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
7139 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
7140 for (unsigned i
= 0; i
< dst
.size(); i
++)
7141 vec
->operands
[i
] = Operand(0u);
7142 vec
->definitions
[0] = Definition(dst
);
7143 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7148 /* we can use a linear phi in some cases if one src is undef */
7149 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
7150 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
7152 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
7153 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
7154 assert(invert
->kind
& block_kind_invert
);
7156 unsigned then_block
= invert
->linear_preds
[0];
7158 Block
* insert_block
= NULL
;
7159 for (unsigned i
= 0; i
< num_operands
; i
++) {
7160 Operand op
= operands
[i
];
7161 if (op
.isUndefined())
7163 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
7164 phi
->operands
[0] = op
;
7167 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
7168 phi
->operands
[1] = Operand(dst
.regClass());
7169 phi
->definitions
[0] = Definition(dst
);
7170 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
7174 /* try to scalarize vector phis */
7175 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
7176 // TODO: scalarize linear phis on divergent ifs
7177 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
7178 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
7179 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
7180 Operand src
= operands
[i
];
7181 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
7182 can_scalarize
= false;
7184 if (can_scalarize
) {
7185 unsigned num_components
= instr
->dest
.ssa
.num_components
;
7186 assert(dst
.size() % num_components
== 0);
7187 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
7189 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
7190 for (unsigned k
= 0; k
< num_components
; k
++) {
7191 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
7192 for (unsigned i
= 0; i
< num_operands
; i
++) {
7193 Operand src
= operands
[i
];
7194 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
7196 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
7197 phi
->definitions
[0] = Definition(phi_dst
);
7198 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
7199 new_vec
[k
] = phi_dst
;
7200 vec
->operands
[k
] = Operand(phi_dst
);
7202 vec
->definitions
[0] = Definition(dst
);
7203 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7204 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
7209 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
7210 for (unsigned i
= 0; i
< num_operands
; i
++)
7211 phi
->operands
[i
] = operands
[i
];
7212 phi
->definitions
[0] = Definition(dst
);
7213 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
7217 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
7219 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
7221 assert(dst
.type() == RegType::sgpr
);
7223 if (dst
.size() == 1) {
7224 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
7226 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
7227 for (unsigned i
= 0; i
< dst
.size(); i
++)
7228 vec
->operands
[i
] = Operand(0u);
7229 vec
->definitions
[0] = Definition(dst
);
7230 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7234 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
7236 Builder
bld(ctx
->program
, ctx
->block
);
7237 Block
*logical_target
;
7238 append_logical_end(ctx
->block
);
7239 unsigned idx
= ctx
->block
->index
;
7241 switch (instr
->type
) {
7242 case nir_jump_break
:
7243 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
7244 add_logical_edge(idx
, logical_target
);
7245 ctx
->block
->kind
|= block_kind_break
;
7247 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
7248 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
7249 /* uniform break - directly jump out of the loop */
7250 ctx
->block
->kind
|= block_kind_uniform
;
7251 ctx
->cf_info
.has_branch
= true;
7252 bld
.branch(aco_opcode::p_branch
);
7253 add_linear_edge(idx
, logical_target
);
7256 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
7257 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
7259 case nir_jump_continue
:
7260 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
7261 add_logical_edge(idx
, logical_target
);
7262 ctx
->block
->kind
|= block_kind_continue
;
7264 if (ctx
->cf_info
.parent_if
.is_divergent
) {
7265 /* for potential uniform breaks after this continue,
7266 we must ensure that they are handled correctly */
7267 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
7268 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
7269 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
7271 /* uniform continue - directly jump to the loop header */
7272 ctx
->block
->kind
|= block_kind_uniform
;
7273 ctx
->cf_info
.has_branch
= true;
7274 bld
.branch(aco_opcode::p_branch
);
7275 add_linear_edge(idx
, logical_target
);
7280 fprintf(stderr
, "Unknown NIR jump instr: ");
7281 nir_print_instr(&instr
->instr
, stderr
);
7282 fprintf(stderr
, "\n");
7286 /* remove critical edges from linear CFG */
7287 bld
.branch(aco_opcode::p_branch
);
7288 Block
* break_block
= ctx
->program
->create_and_insert_block();
7289 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7290 break_block
->kind
|= block_kind_uniform
;
7291 add_linear_edge(idx
, break_block
);
7292 /* the loop_header pointer might be invalidated by this point */
7293 if (instr
->type
== nir_jump_continue
)
7294 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
7295 add_linear_edge(break_block
->index
, logical_target
);
7296 bld
.reset(break_block
);
7297 bld
.branch(aco_opcode::p_branch
);
7299 Block
* continue_block
= ctx
->program
->create_and_insert_block();
7300 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7301 add_linear_edge(idx
, continue_block
);
7302 append_logical_start(continue_block
);
7303 ctx
->block
= continue_block
;
7307 void visit_block(isel_context
*ctx
, nir_block
*block
)
7309 nir_foreach_instr(instr
, block
) {
7310 switch (instr
->type
) {
7311 case nir_instr_type_alu
:
7312 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
7314 case nir_instr_type_load_const
:
7315 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
7317 case nir_instr_type_intrinsic
:
7318 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
7320 case nir_instr_type_tex
:
7321 visit_tex(ctx
, nir_instr_as_tex(instr
));
7323 case nir_instr_type_phi
:
7324 visit_phi(ctx
, nir_instr_as_phi(instr
));
7326 case nir_instr_type_ssa_undef
:
7327 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
7329 case nir_instr_type_deref
:
7331 case nir_instr_type_jump
:
7332 visit_jump(ctx
, nir_instr_as_jump(instr
));
7335 fprintf(stderr
, "Unknown NIR instr type: ");
7336 nir_print_instr(instr
, stderr
);
7337 fprintf(stderr
, "\n");
7342 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7343 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
7348 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
7350 append_logical_end(ctx
->block
);
7351 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
7352 Builder
bld(ctx
->program
, ctx
->block
);
7353 bld
.branch(aco_opcode::p_branch
);
7354 unsigned loop_preheader_idx
= ctx
->block
->index
;
7356 Block loop_exit
= Block();
7357 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7358 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
7360 Block
* loop_header
= ctx
->program
->create_and_insert_block();
7361 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
7362 loop_header
->kind
|= block_kind_loop_header
;
7363 add_edge(loop_preheader_idx
, loop_header
);
7364 ctx
->block
= loop_header
;
7366 /* emit loop body */
7367 unsigned loop_header_idx
= loop_header
->index
;
7368 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
7369 append_logical_start(ctx
->block
);
7370 visit_cf_list(ctx
, &loop
->body
);
7372 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
7373 if (!ctx
->cf_info
.has_branch
) {
7374 append_logical_end(ctx
->block
);
7375 if (ctx
->cf_info
.exec_potentially_empty
) {
7376 /* Discards can result in code running with an empty exec mask.
7377 * This would result in divergent breaks not ever being taken. As a
7378 * workaround, break the loop when the loop mask is empty instead of
7379 * always continuing. */
7380 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
7381 unsigned block_idx
= ctx
->block
->index
;
7383 /* create helper blocks to avoid critical edges */
7384 Block
*break_block
= ctx
->program
->create_and_insert_block();
7385 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7386 break_block
->kind
= block_kind_uniform
;
7387 bld
.reset(break_block
);
7388 bld
.branch(aco_opcode::p_branch
);
7389 add_linear_edge(block_idx
, break_block
);
7390 add_linear_edge(break_block
->index
, &loop_exit
);
7392 Block
*continue_block
= ctx
->program
->create_and_insert_block();
7393 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7394 continue_block
->kind
= block_kind_uniform
;
7395 bld
.reset(continue_block
);
7396 bld
.branch(aco_opcode::p_branch
);
7397 add_linear_edge(block_idx
, continue_block
);
7398 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
7400 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
7401 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
7403 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
7404 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7405 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
7407 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
7410 bld
.reset(ctx
->block
);
7411 bld
.branch(aco_opcode::p_branch
);
7414 /* fixup phis in loop header from unreachable blocks */
7415 if (ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
) {
7416 bool linear
= ctx
->cf_info
.has_branch
;
7417 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
7418 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
7419 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
7420 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
7421 /* the last operand should be the one that needs to be removed */
7422 instr
->operands
.pop_back();
7423 } else if (!is_phi(instr
)) {
7429 ctx
->cf_info
.has_branch
= false;
7431 // TODO: if the loop has not a single exit, we must add one °°
7432 /* emit loop successor block */
7433 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
7434 append_logical_start(ctx
->block
);
7437 // TODO: check if it is beneficial to not branch on continues
7438 /* trim linear phis in loop header */
7439 for (auto&& instr
: loop_entry
->instructions
) {
7440 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
7441 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
7442 new_phi
->definitions
[0] = instr
->definitions
[0];
7443 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
7444 new_phi
->operands
[i
] = instr
->operands
[i
];
7445 /* check that the remaining operands are all the same */
7446 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
7447 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
7448 instr
.swap(new_phi
);
7449 } else if (instr
->opcode
== aco_opcode::p_phi
) {
7458 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
7462 append_logical_end(ctx
->block
);
7463 ctx
->block
->kind
|= block_kind_branch
;
7465 /* branch to linear then block */
7466 assert(cond
.regClass() == ctx
->program
->lane_mask
);
7467 aco_ptr
<Pseudo_branch_instruction
> branch
;
7468 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
7469 branch
->operands
[0] = Operand(cond
);
7470 ctx
->block
->instructions
.push_back(std::move(branch
));
7472 ic
->BB_if_idx
= ctx
->block
->index
;
7473 ic
->BB_invert
= Block();
7474 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7475 /* Invert blocks are intentionally not marked as top level because they
7476 * are not part of the logical cfg. */
7477 ic
->BB_invert
.kind
|= block_kind_invert
;
7478 ic
->BB_endif
= Block();
7479 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7480 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
7482 ic
->exec_potentially_empty_old
= ctx
->cf_info
.exec_potentially_empty
;
7483 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
7484 ctx
->cf_info
.parent_if
.is_divergent
= true;
7485 ctx
->cf_info
.exec_potentially_empty
= false; /* divergent branches use cbranch_execz */
7487 /** emit logical then block */
7488 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
7489 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7490 add_edge(ic
->BB_if_idx
, BB_then_logical
);
7491 ctx
->block
= BB_then_logical
;
7492 append_logical_start(BB_then_logical
);
7495 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
7497 Block
*BB_then_logical
= ctx
->block
;
7498 append_logical_end(BB_then_logical
);
7499 /* branch from logical then block to invert block */
7500 aco_ptr
<Pseudo_branch_instruction
> branch
;
7501 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7502 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
7503 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
7504 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7505 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
7506 BB_then_logical
->kind
|= block_kind_uniform
;
7507 assert(!ctx
->cf_info
.has_branch
);
7508 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
7509 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
7511 /** emit linear then block */
7512 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
7513 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7514 BB_then_linear
->kind
|= block_kind_uniform
;
7515 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
7516 /* branch from linear then block to invert block */
7517 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7518 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
7519 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
7521 /** emit invert merge block */
7522 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
7523 ic
->invert_idx
= ctx
->block
->index
;
7525 /* branch to linear else block (skip else) */
7526 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
7527 branch
->operands
[0] = Operand(ic
->cond
);
7528 ctx
->block
->instructions
.push_back(std::move(branch
));
7530 ic
->exec_potentially_empty_old
|= ctx
->cf_info
.exec_potentially_empty
;
7531 ctx
->cf_info
.exec_potentially_empty
= false; /* divergent branches use cbranch_execz */
7533 /** emit logical else block */
7534 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
7535 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7536 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
7537 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
7538 ctx
->block
= BB_else_logical
;
7539 append_logical_start(BB_else_logical
);
7542 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
7544 Block
*BB_else_logical
= ctx
->block
;
7545 append_logical_end(BB_else_logical
);
7547 /* branch from logical else block to endif block */
7548 aco_ptr
<Pseudo_branch_instruction
> branch
;
7549 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7550 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
7551 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
7552 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7553 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
7554 BB_else_logical
->kind
|= block_kind_uniform
;
7556 assert(!ctx
->cf_info
.has_branch
);
7557 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
7560 /** emit linear else block */
7561 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
7562 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7563 BB_else_linear
->kind
|= block_kind_uniform
;
7564 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
7566 /* branch from linear else block to endif block */
7567 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7568 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
7569 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
7572 /** emit endif merge block */
7573 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
7574 append_logical_start(ctx
->block
);
7577 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
7578 ctx
->cf_info
.exec_potentially_empty
|= ic
->exec_potentially_empty_old
;
7579 /* uniform control flow never has an empty exec-mask */
7580 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
7581 ctx
->cf_info
.exec_potentially_empty
= false;
7584 static void visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
7586 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
7587 Builder
bld(ctx
->program
, ctx
->block
);
7588 aco_ptr
<Pseudo_branch_instruction
> branch
;
7590 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
7592 * Uniform conditionals are represented in the following way*) :
7594 * The linear and logical CFG:
7597 * BB_THEN (logical) BB_ELSE (logical)
7601 * *) Exceptions may be due to break and continue statements within loops
7602 * If a break/continue happens within uniform control flow, it branches
7603 * to the loop exit/entry block. Otherwise, it branches to the next
7606 append_logical_end(ctx
->block
);
7607 ctx
->block
->kind
|= block_kind_uniform
;
7610 assert(cond
.regClass() == bld
.lm
);
7611 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
7612 cond
= bool_to_scalar_condition(ctx
, cond
);
7614 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
7615 branch
->operands
[0] = Operand(cond
);
7616 branch
->operands
[0].setFixed(scc
);
7617 ctx
->block
->instructions
.emplace_back(std::move(branch
));
7619 unsigned BB_if_idx
= ctx
->block
->index
;
7620 Block BB_endif
= Block();
7621 BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7622 BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
7624 /** emit then block */
7625 Block
* BB_then
= ctx
->program
->create_and_insert_block();
7626 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7627 add_edge(BB_if_idx
, BB_then
);
7628 append_logical_start(BB_then
);
7629 ctx
->block
= BB_then
;
7630 visit_cf_list(ctx
, &if_stmt
->then_list
);
7631 BB_then
= ctx
->block
;
7632 bool then_branch
= ctx
->cf_info
.has_branch
;
7633 bool then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
7636 append_logical_end(BB_then
);
7637 /* branch from then block to endif block */
7638 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7639 BB_then
->instructions
.emplace_back(std::move(branch
));
7640 add_linear_edge(BB_then
->index
, &BB_endif
);
7641 if (!then_branch_divergent
)
7642 add_logical_edge(BB_then
->index
, &BB_endif
);
7643 BB_then
->kind
|= block_kind_uniform
;
7646 ctx
->cf_info
.has_branch
= false;
7647 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
7649 /** emit else block */
7650 Block
* BB_else
= ctx
->program
->create_and_insert_block();
7651 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7652 add_edge(BB_if_idx
, BB_else
);
7653 append_logical_start(BB_else
);
7654 ctx
->block
= BB_else
;
7655 visit_cf_list(ctx
, &if_stmt
->else_list
);
7656 BB_else
= ctx
->block
;
7658 if (!ctx
->cf_info
.has_branch
) {
7659 append_logical_end(BB_else
);
7660 /* branch from then block to endif block */
7661 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7662 BB_else
->instructions
.emplace_back(std::move(branch
));
7663 add_linear_edge(BB_else
->index
, &BB_endif
);
7664 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7665 add_logical_edge(BB_else
->index
, &BB_endif
);
7666 BB_else
->kind
|= block_kind_uniform
;
7669 ctx
->cf_info
.has_branch
&= then_branch
;
7670 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= then_branch_divergent
;
7672 /** emit endif merge block */
7673 if (!ctx
->cf_info
.has_branch
) {
7674 ctx
->block
= ctx
->program
->insert_block(std::move(BB_endif
));
7675 append_logical_start(ctx
->block
);
7677 } else { /* non-uniform condition */
7679 * To maintain a logical and linear CFG without critical edges,
7680 * non-uniform conditionals are represented in the following way*) :
7685 * BB_THEN (logical) BB_THEN (linear)
7687 * BB_INVERT (linear)
7689 * BB_ELSE (logical) BB_ELSE (linear)
7696 * BB_THEN (logical) BB_ELSE (logical)
7700 * *) Exceptions may be due to break and continue statements within loops
7705 begin_divergent_if_then(ctx
, &ic
, cond
);
7706 visit_cf_list(ctx
, &if_stmt
->then_list
);
7708 begin_divergent_if_else(ctx
, &ic
);
7709 visit_cf_list(ctx
, &if_stmt
->else_list
);
7711 end_divergent_if(ctx
, &ic
);
7715 static void visit_cf_list(isel_context
*ctx
,
7716 struct exec_list
*list
)
7718 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
7719 switch (node
->type
) {
7720 case nir_cf_node_block
:
7721 visit_block(ctx
, nir_cf_node_as_block(node
));
7723 case nir_cf_node_if
:
7724 visit_if(ctx
, nir_cf_node_as_if(node
));
7726 case nir_cf_node_loop
:
7727 visit_loop(ctx
, nir_cf_node_as_loop(node
));
7730 unreachable("unimplemented cf list type");
7735 static void export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
7737 int offset
= ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
7738 uint64_t mask
= ctx
->vs_output
.mask
[slot
];
7739 if (!is_pos
&& !mask
)
7741 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
7743 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
7744 exp
->enabled_mask
= mask
;
7745 for (unsigned i
= 0; i
< 4; ++i
) {
7746 if (mask
& (1 << i
))
7747 exp
->operands
[i
] = Operand(ctx
->vs_output
.outputs
[slot
][i
]);
7749 exp
->operands
[i
] = Operand(v1
);
7751 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
7752 * Setting valid_mask=1 prevents it and has no other effect.
7754 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
7756 exp
->compressed
= false;
7758 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
7760 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
7761 ctx
->block
->instructions
.emplace_back(std::move(exp
));
7764 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
7766 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
7767 exp
->enabled_mask
= 0;
7768 for (unsigned i
= 0; i
< 4; ++i
)
7769 exp
->operands
[i
] = Operand(v1
);
7770 if (ctx
->vs_output
.mask
[VARYING_SLOT_PSIZ
]) {
7771 exp
->operands
[0] = Operand(ctx
->vs_output
.outputs
[VARYING_SLOT_PSIZ
][0]);
7772 exp
->enabled_mask
|= 0x1;
7774 if (ctx
->vs_output
.mask
[VARYING_SLOT_LAYER
]) {
7775 exp
->operands
[2] = Operand(ctx
->vs_output
.outputs
[VARYING_SLOT_LAYER
][0]);
7776 exp
->enabled_mask
|= 0x4;
7778 if (ctx
->vs_output
.mask
[VARYING_SLOT_VIEWPORT
]) {
7779 if (ctx
->options
->chip_class
< GFX9
) {
7780 exp
->operands
[3] = Operand(ctx
->vs_output
.outputs
[VARYING_SLOT_VIEWPORT
][0]);
7781 exp
->enabled_mask
|= 0x8;
7783 Builder
bld(ctx
->program
, ctx
->block
);
7785 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
7786 Operand(ctx
->vs_output
.outputs
[VARYING_SLOT_VIEWPORT
][0]));
7787 if (exp
->operands
[2].isTemp())
7788 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
7790 exp
->operands
[2] = Operand(out
);
7791 exp
->enabled_mask
|= 0x4;
7794 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
7796 exp
->compressed
= false;
7797 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
7798 ctx
->block
->instructions
.emplace_back(std::move(exp
));
7801 static void create_vs_exports(isel_context
*ctx
)
7803 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->vs
.outinfo
;
7805 if (outinfo
->export_prim_id
) {
7806 ctx
->vs_output
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
7807 ctx
->vs_output
.outputs
[VARYING_SLOT_PRIMITIVE_ID
][0] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
7810 if (ctx
->options
->key
.has_multiview_view_index
) {
7811 ctx
->vs_output
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
7812 ctx
->vs_output
.outputs
[VARYING_SLOT_LAYER
][0] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
7815 /* the order these position exports are created is important */
7817 export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
7818 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
7819 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
7821 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
7822 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
7823 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
7824 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
7826 if (ctx
->options
->key
.vs_common_out
.export_clip_dists
) {
7827 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
7828 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
7829 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
7830 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
7833 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
7834 if (i
< VARYING_SLOT_VAR0
&& i
!= VARYING_SLOT_LAYER
&&
7835 i
!= VARYING_SLOT_PRIMITIVE_ID
)
7838 export_vs_varying(ctx
, i
, false, NULL
);
7842 static void emit_stream_output(isel_context
*ctx
,
7843 Temp
const *so_buffers
,
7844 Temp
const *so_write_offset
,
7845 const struct radv_stream_output
*output
)
7847 unsigned num_comps
= util_bitcount(output
->component_mask
);
7848 unsigned writemask
= (1 << num_comps
) - 1;
7849 unsigned loc
= output
->location
;
7850 unsigned buf
= output
->buffer
;
7852 assert(num_comps
&& num_comps
<= 4);
7853 if (!num_comps
|| num_comps
> 4)
7856 unsigned start
= ffs(output
->component_mask
) - 1;
7859 bool all_undef
= true;
7860 assert(ctx
->stage
== vertex_vs
);
7861 for (unsigned i
= 0; i
< num_comps
; i
++) {
7862 out
[i
] = ctx
->vs_output
.outputs
[loc
][start
+ i
];
7863 all_undef
= all_undef
&& !out
[i
].id();
7870 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
7871 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
7872 /* GFX6 doesn't support storing vec3, split it. */
7873 writemask
|= 1u << (start
+ 2);
7877 unsigned offset
= output
->offset
+ start
* 4;
7879 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
7880 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
7881 for (int i
= 0; i
< count
; ++i
)
7882 vec
->operands
[i
] = (ctx
->vs_output
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
7883 vec
->definitions
[0] = Definition(write_data
);
7884 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7889 opcode
= aco_opcode::buffer_store_dword
;
7892 opcode
= aco_opcode::buffer_store_dwordx2
;
7895 opcode
= aco_opcode::buffer_store_dwordx3
;
7898 opcode
= aco_opcode::buffer_store_dwordx4
;
7902 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
7903 store
->operands
[0] = Operand(so_write_offset
[buf
]);
7904 store
->operands
[1] = Operand(so_buffers
[buf
]);
7905 store
->operands
[2] = Operand((uint32_t) 0);
7906 store
->operands
[3] = Operand(write_data
);
7907 if (offset
> 4095) {
7908 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
7909 Builder
bld(ctx
->program
, ctx
->block
);
7910 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
7912 store
->offset
= offset
;
7914 store
->offen
= true;
7918 store
->can_reorder
= true;
7919 ctx
->block
->instructions
.emplace_back(std::move(store
));
7923 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
7925 Builder
bld(ctx
->program
, ctx
->block
);
7928 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
7929 for (unsigned i
= 0; i
< 4; i
++) {
7930 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
7934 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, Operand(i
* 16u));
7937 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7938 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
7940 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
7942 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
7945 begin_divergent_if_then(ctx
, &ic
, can_emit
);
7947 bld
.reset(ctx
->block
);
7949 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
7951 Temp so_write_offset
[4];
7953 for (unsigned i
= 0; i
< 4; i
++) {
7954 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
7959 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
7960 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
7961 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
7962 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
7964 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
7966 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
7967 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
7968 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
7969 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
7973 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
7974 struct radv_stream_output
*output
=
7975 &ctx
->program
->info
->so
.outputs
[i
];
7976 if (stream
!= output
->stream
)
7979 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
7982 begin_divergent_if_else(ctx
, &ic
);
7983 end_divergent_if(ctx
, &ic
);
7986 } /* end namespace */
7988 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
7990 /* Split all arguments except for the first (ring_offsets) and the last
7991 * (exec) so that the dead channels don't stay live throughout the program.
7993 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
7994 if (startpgm
->definitions
[i
].regClass().size() > 1) {
7995 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
7996 startpgm
->definitions
[i
].regClass().size());
8001 void handle_bc_optimize(isel_context
*ctx
)
8003 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
8004 Builder
bld(ctx
->program
, ctx
->block
);
8005 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
8006 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
8007 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
8008 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
8009 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
8010 if (uses_center
&& uses_centroid
) {
8011 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
8012 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
8014 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
8016 for (unsigned i
= 0; i
< 2; i
++) {
8017 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
8018 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
8019 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8020 persp_centroid
, persp_center
, sel
);
8022 ctx
->persp_centroid
= bld
.tmp(v2
);
8023 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
8024 Operand(new_coord
[0]), Operand(new_coord
[1]));
8025 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
8028 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
8030 for (unsigned i
= 0; i
< 2; i
++) {
8031 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
8032 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
8033 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8034 linear_centroid
, linear_center
, sel
);
8036 ctx
->linear_centroid
= bld
.tmp(v2
);
8037 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
8038 Operand(new_coord
[0]), Operand(new_coord
[1]));
8039 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
8044 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
8046 Program
*program
= ctx
->program
;
8048 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
8050 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
8051 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
8052 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
8053 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
8054 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
8056 program
->next_fp_mode
.must_flush_denorms32
=
8057 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
8058 program
->next_fp_mode
.must_flush_denorms16_64
=
8059 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
8060 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
8062 program
->next_fp_mode
.care_about_round32
=
8063 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
8065 program
->next_fp_mode
.care_about_round16_64
=
8066 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
8067 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
8069 /* default to preserving fp16 and fp64 denorms, since it's free */
8070 if (program
->next_fp_mode
.must_flush_denorms16_64
)
8071 program
->next_fp_mode
.denorm16_64
= 0;
8073 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
8075 /* preserving fp32 denorms is expensive, so only do it if asked */
8076 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
8077 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
8079 program
->next_fp_mode
.denorm32
= 0;
8081 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
8082 program
->next_fp_mode
.round32
= fp_round_tz
;
8084 program
->next_fp_mode
.round32
= fp_round_ne
;
8086 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
8087 program
->next_fp_mode
.round16_64
= fp_round_tz
;
8089 program
->next_fp_mode
.round16_64
= fp_round_ne
;
8091 ctx
->block
->fp_mode
= program
->next_fp_mode
;
8094 void select_program(Program
*program
,
8095 unsigned shader_count
,
8096 struct nir_shader
*const *shaders
,
8097 ac_shader_config
* config
,
8098 struct radv_shader_args
*args
)
8100 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
);
8102 for (unsigned i
= 0; i
< shader_count
; i
++) {
8103 nir_shader
*nir
= shaders
[i
];
8104 init_context(&ctx
, nir
);
8106 setup_fp_mode(&ctx
, nir
);
8109 /* needs to be after init_context() for FS */
8110 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
8111 append_logical_start(ctx
.block
);
8112 split_arguments(&ctx
, startpgm
);
8116 if (shader_count
>= 2) {
8117 Builder
bld(ctx
.program
, ctx
.block
);
8118 Temp count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), ctx
.merged_wave_info
, Operand((8u << 16) | (i
* 8u)));
8119 Temp thread_id
= emit_mbcnt(&ctx
, bld
.def(v1
));
8120 Temp cond
= bld
.vopc(aco_opcode::v_cmp_gt_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), count
, thread_id
);
8122 begin_divergent_if_then(&ctx
, &ic
, cond
);
8126 Builder
bld(ctx
.program
, ctx
.block
);
8127 bld
.barrier(aco_opcode::p_memory_barrier_shared
); //TODO: different barriers are needed for different stages
8128 bld
.sopp(aco_opcode::s_barrier
);
8131 if (ctx
.stage
== fragment_fs
)
8132 handle_bc_optimize(&ctx
);
8134 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
8135 visit_cf_list(&ctx
, &func
->body
);
8137 if (ctx
.program
->info
->so
.num_outputs
/*&& !ctx->is_gs_copy_shader */)
8138 emit_streamout(&ctx
, 0);
8140 if (ctx
.stage
== vertex_vs
)
8141 create_vs_exports(&ctx
);
8143 if (shader_count
>= 2) {
8144 begin_divergent_if_else(&ctx
, &ic
);
8145 end_divergent_if(&ctx
, &ic
);
8148 ralloc_free(ctx
.divergent_vals
);
8151 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
8153 append_logical_end(ctx
.block
);
8154 ctx
.block
->kind
|= block_kind_uniform
;
8155 Builder
bld(ctx
.program
, ctx
.block
);
8156 if (ctx
.program
->wb_smem_l1_on_end
)
8157 bld
.smem(aco_opcode::s_dcache_wb
, false);
8158 bld
.sopp(aco_opcode::s_endpgm
);
8161 for (Block
& BB
: program
->blocks
) {
8162 for (unsigned idx
: BB
.linear_preds
)
8163 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
8164 for (unsigned idx
: BB
.logical_preds
)
8165 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);