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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f16
:
630 op
= aco_opcode::v_cmp_gt_f16
;
632 case aco_opcode::v_cmp_ge_f16
:
633 op
= aco_opcode::v_cmp_le_f16
;
635 case aco_opcode::v_cmp_lt_i16
:
636 op
= aco_opcode::v_cmp_gt_i16
;
638 case aco_opcode::v_cmp_ge_i16
:
639 op
= aco_opcode::v_cmp_le_i16
;
641 case aco_opcode::v_cmp_lt_u16
:
642 op
= aco_opcode::v_cmp_gt_u16
;
644 case aco_opcode::v_cmp_ge_u16
:
645 op
= aco_opcode::v_cmp_le_u16
;
647 case aco_opcode::v_cmp_lt_f32
:
648 op
= aco_opcode::v_cmp_gt_f32
;
650 case aco_opcode::v_cmp_ge_f32
:
651 op
= aco_opcode::v_cmp_le_f32
;
653 case aco_opcode::v_cmp_lt_i32
:
654 op
= aco_opcode::v_cmp_gt_i32
;
656 case aco_opcode::v_cmp_ge_i32
:
657 op
= aco_opcode::v_cmp_le_i32
;
659 case aco_opcode::v_cmp_lt_u32
:
660 op
= aco_opcode::v_cmp_gt_u32
;
662 case aco_opcode::v_cmp_ge_u32
:
663 op
= aco_opcode::v_cmp_le_u32
;
665 case aco_opcode::v_cmp_lt_f64
:
666 op
= aco_opcode::v_cmp_gt_f64
;
668 case aco_opcode::v_cmp_ge_f64
:
669 op
= aco_opcode::v_cmp_le_f64
;
671 case aco_opcode::v_cmp_lt_i64
:
672 op
= aco_opcode::v_cmp_gt_i64
;
674 case aco_opcode::v_cmp_ge_i64
:
675 op
= aco_opcode::v_cmp_le_i64
;
677 case aco_opcode::v_cmp_lt_u64
:
678 op
= aco_opcode::v_cmp_gt_u64
;
680 case aco_opcode::v_cmp_ge_u64
:
681 op
= aco_opcode::v_cmp_le_u64
;
683 default: /* eq and ne are commutative */
690 src1
= as_vgpr(ctx
, src1
);
694 Builder
bld(ctx
->program
, ctx
->block
);
695 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
698 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
700 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
701 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
702 Builder
bld(ctx
->program
, ctx
->block
);
704 assert(dst
.regClass() == bld
.lm
);
705 assert(src0
.type() == RegType::sgpr
);
706 assert(src1
.type() == RegType::sgpr
);
707 assert(src0
.regClass() == src1
.regClass());
709 /* Emit the SALU comparison instruction */
710 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
711 /* Turn the result into a per-lane bool */
712 bool_to_vector_condition(ctx
, cmp
, dst
);
715 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
716 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
718 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
719 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
720 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
721 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
723 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
724 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
725 aco_opcode op
= use_valu
? v_op
: s_op
;
726 assert(op
!= aco_opcode::num_opcodes
);
727 assert(dst
.regClass() == ctx
->program
->lane_mask
);
730 emit_vopc_instruction(ctx
, instr
, op
, dst
);
732 emit_sopc_instruction(ctx
, instr
, op
, dst
);
735 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
737 Builder
bld(ctx
->program
, ctx
->block
);
738 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
739 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
741 assert(dst
.regClass() == bld
.lm
);
742 assert(src0
.regClass() == bld
.lm
);
743 assert(src1
.regClass() == bld
.lm
);
745 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
748 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
750 Builder
bld(ctx
->program
, ctx
->block
);
751 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
752 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
753 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
755 assert(cond
.regClass() == bld
.lm
);
757 if (dst
.type() == RegType::vgpr
) {
758 aco_ptr
<Instruction
> bcsel
;
759 if (dst
.regClass() == v2b
) {
760 then
= as_vgpr(ctx
, then
);
761 els
= as_vgpr(ctx
, els
);
763 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
765 } else if (dst
.regClass() == v1
) {
766 then
= as_vgpr(ctx
, then
);
767 els
= as_vgpr(ctx
, els
);
769 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
770 } else if (dst
.regClass() == v2
) {
771 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
772 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
773 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
774 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
776 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
777 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
779 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
781 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
782 nir_print_instr(&instr
->instr
, stderr
);
783 fprintf(stderr
, "\n");
788 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
789 assert(dst
.regClass() == bld
.lm
);
790 assert(then
.regClass() == bld
.lm
);
791 assert(els
.regClass() == bld
.lm
);
794 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
795 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
796 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
797 assert(dst
.size() == then
.size());
798 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
799 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
801 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
802 nir_print_instr(&instr
->instr
, stderr
);
803 fprintf(stderr
, "\n");
808 /* divergent boolean bcsel
809 * this implements bcsel on bools: dst = s0 ? s1 : s2
810 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
811 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
813 if (cond
.id() != then
.id())
814 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
816 if (cond
.id() == els
.id())
817 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
819 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
820 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
823 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
824 aco_opcode op
, uint32_t undo
)
826 /* multiply by 16777216 to handle denormals */
827 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
828 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
829 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
830 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
831 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
833 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
835 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
838 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
840 if (ctx
->block
->fp_mode
.denorm32
== 0) {
841 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
845 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
848 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
850 if (ctx
->block
->fp_mode
.denorm32
== 0) {
851 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
855 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
858 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
860 if (ctx
->block
->fp_mode
.denorm32
== 0) {
861 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
865 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
868 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
870 if (ctx
->block
->fp_mode
.denorm32
== 0) {
871 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
875 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
878 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
880 if (ctx
->options
->chip_class
>= GFX7
)
881 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
883 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
884 /* TODO: create more efficient code! */
885 if (val
.type() == RegType::sgpr
)
886 val
= as_vgpr(ctx
, val
);
888 /* Split the input value. */
889 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
890 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
892 /* Extract the exponent and compute the unbiased value. */
893 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
895 /* Extract the fractional part. */
896 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
897 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
899 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
900 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
902 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
903 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
904 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
905 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
906 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
908 /* Get the sign bit. */
909 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
911 /* Decide the operation to apply depending on the unbiased exponent. */
912 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
913 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
914 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
915 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
916 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
917 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
919 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
922 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
924 if (ctx
->options
->chip_class
>= GFX7
)
925 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
927 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
928 Temp src0
= as_vgpr(ctx
, val
);
930 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
931 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
933 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
934 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
935 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
937 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
938 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
939 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
940 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
942 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
943 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
945 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
947 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
948 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
950 return add
->definitions
[0].getTemp();
953 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
955 if (!instr
->dest
.dest
.is_ssa
) {
956 fprintf(stderr
, "nir alu dst not in ssa: ");
957 nir_print_instr(&instr
->instr
, stderr
);
958 fprintf(stderr
, "\n");
961 Builder
bld(ctx
->program
, ctx
->block
);
962 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
967 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
968 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
969 for (unsigned i
= 0; i
< num
; ++i
)
970 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
972 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
973 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
974 for (unsigned i
= 0; i
< num
; ++i
)
975 vec
->operands
[i
] = Operand
{elems
[i
]};
976 vec
->definitions
[0] = Definition(dst
);
977 ctx
->block
->instructions
.emplace_back(std::move(vec
));
978 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
980 // TODO: that is a bit suboptimal..
981 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
982 for (unsigned i
= 0; i
< num
- 1; ++i
)
983 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
984 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
985 for (unsigned i
= 0; i
< num
; ++i
) {
986 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
988 elems
[bit
/ 32] = elems
[i
];
990 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
991 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
992 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
996 bld
.copy(Definition(dst
), elems
[0]);
998 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1003 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1004 aco_ptr
<Instruction
> mov
;
1005 if (dst
.type() == RegType::sgpr
) {
1006 if (src
.type() == RegType::vgpr
)
1007 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1008 else if (src
.regClass() == s1
)
1009 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1010 else if (src
.regClass() == s2
)
1011 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1013 unreachable("wrong src register class for nir_op_imov");
1014 } else if (dst
.regClass() == v1
) {
1015 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1016 } else if (dst
.regClass() == v2
) {
1017 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1019 nir_print_instr(&instr
->instr
, stderr
);
1020 unreachable("Should have been lowered to scalar.");
1025 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1026 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1027 assert(src
.regClass() == bld
.lm
);
1028 assert(dst
.regClass() == bld
.lm
);
1029 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1030 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1031 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1032 } else if (dst
.regClass() == v1
) {
1033 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1034 } else if (dst
.type() == RegType::sgpr
) {
1035 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1036 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1038 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1039 nir_print_instr(&instr
->instr
, stderr
);
1040 fprintf(stderr
, "\n");
1045 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1046 if (dst
.regClass() == v1
) {
1047 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1048 } else if (dst
.regClass() == s1
) {
1049 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1050 } else if (dst
.size() == 2) {
1051 Temp src0
= bld
.tmp(dst
.type(), 1);
1052 Temp src1
= bld
.tmp(dst
.type(), 1);
1053 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1055 if (dst
.regClass() == s2
) {
1056 Temp carry
= bld
.tmp(s1
);
1057 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1058 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1059 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1061 Temp lower
= bld
.tmp(v1
);
1062 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1063 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1064 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1067 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1068 nir_print_instr(&instr
->instr
, stderr
);
1069 fprintf(stderr
, "\n");
1074 if (dst
.regClass() == s1
) {
1075 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1076 } else if (dst
.regClass() == v1
) {
1077 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1078 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1080 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1081 nir_print_instr(&instr
->instr
, stderr
);
1082 fprintf(stderr
, "\n");
1086 case nir_op_isign
: {
1087 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1088 if (dst
.regClass() == s1
) {
1089 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1090 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1091 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1092 } else if (dst
.regClass() == s2
) {
1093 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1095 if (ctx
->program
->chip_class
>= GFX8
)
1096 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1098 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1099 /* SCC gets zero-extended to 64 bit */
1100 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1101 } else if (dst
.regClass() == v1
) {
1102 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1103 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1104 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1105 } else if (dst
.regClass() == v2
) {
1106 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1107 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1108 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1109 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1110 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1111 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == v1
) {
1121 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1122 } else if (dst
.regClass() == s1
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1134 } else if (dst
.regClass() == s1
) {
1135 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1144 if (dst
.regClass() == v1
) {
1145 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1146 } else if (dst
.regClass() == s1
) {
1147 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1149 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1150 nir_print_instr(&instr
->instr
, stderr
);
1151 fprintf(stderr
, "\n");
1156 if (dst
.regClass() == v1
) {
1157 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1158 } else if (dst
.regClass() == s1
) {
1159 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1161 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1162 nir_print_instr(&instr
->instr
, stderr
);
1163 fprintf(stderr
, "\n");
1168 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1169 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1170 } else if (dst
.regClass() == v1
) {
1171 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1172 } else if (dst
.regClass() == s1
) {
1173 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1174 } else if (dst
.regClass() == s2
) {
1175 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1177 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1178 nir_print_instr(&instr
->instr
, stderr
);
1179 fprintf(stderr
, "\n");
1184 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1185 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1186 } else if (dst
.regClass() == v1
) {
1187 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1188 } else if (dst
.regClass() == s1
) {
1189 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1190 } else if (dst
.regClass() == s2
) {
1191 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1193 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1194 nir_print_instr(&instr
->instr
, stderr
);
1195 fprintf(stderr
, "\n");
1200 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1201 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1202 } else if (dst
.regClass() == v1
) {
1203 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1204 } else if (dst
.regClass() == s1
) {
1205 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1206 } else if (dst
.regClass() == s2
) {
1207 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1209 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1210 nir_print_instr(&instr
->instr
, stderr
);
1211 fprintf(stderr
, "\n");
1216 if (dst
.regClass() == v1
) {
1217 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1218 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1219 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1220 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1221 } else if (dst
.regClass() == v2
) {
1222 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1223 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1224 } else if (dst
.regClass() == s2
) {
1225 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1226 } else if (dst
.regClass() == s1
) {
1227 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1229 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1230 nir_print_instr(&instr
->instr
, stderr
);
1231 fprintf(stderr
, "\n");
1236 if (dst
.regClass() == v1
) {
1237 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1238 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1239 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1240 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1241 } else if (dst
.regClass() == v2
) {
1242 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1243 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1244 } else if (dst
.regClass() == s1
) {
1245 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1246 } else if (dst
.regClass() == s2
) {
1247 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1249 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1250 nir_print_instr(&instr
->instr
, stderr
);
1251 fprintf(stderr
, "\n");
1256 if (dst
.regClass() == v1
) {
1257 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1258 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1259 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1260 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1261 } else if (dst
.regClass() == v2
) {
1262 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1263 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1264 } else if (dst
.regClass() == s1
) {
1265 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1266 } else if (dst
.regClass() == s2
) {
1267 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1269 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1270 nir_print_instr(&instr
->instr
, stderr
);
1271 fprintf(stderr
, "\n");
1275 case nir_op_find_lsb
: {
1276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1277 if (src
.regClass() == s1
) {
1278 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1279 } else if (src
.regClass() == v1
) {
1280 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1281 } else if (src
.regClass() == s2
) {
1282 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1284 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1285 nir_print_instr(&instr
->instr
, stderr
);
1286 fprintf(stderr
, "\n");
1290 case nir_op_ufind_msb
:
1291 case nir_op_ifind_msb
: {
1292 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1293 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1294 aco_opcode op
= src
.regClass() == s2
?
1295 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1296 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1297 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1299 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1300 Operand(src
.size() * 32u - 1u), msb_rev
);
1301 Temp msb
= sub
.def(0).getTemp();
1302 Temp carry
= sub
.def(1).getTemp();
1304 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1305 } else if (src
.regClass() == v1
) {
1306 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1307 Temp msb_rev
= bld
.tmp(v1
);
1308 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1309 Temp msb
= bld
.tmp(v1
);
1310 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1311 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1313 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1314 nir_print_instr(&instr
->instr
, stderr
);
1315 fprintf(stderr
, "\n");
1319 case nir_op_bitfield_reverse
: {
1320 if (dst
.regClass() == s1
) {
1321 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1322 } else if (dst
.regClass() == v1
) {
1323 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1325 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1326 nir_print_instr(&instr
->instr
, stderr
);
1327 fprintf(stderr
, "\n");
1332 if (dst
.regClass() == s1
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1337 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1338 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1339 if (dst
.regClass() == v1
) {
1340 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1344 assert(src0
.size() == 2 && src1
.size() == 2);
1345 Temp src00
= bld
.tmp(src0
.type(), 1);
1346 Temp src01
= bld
.tmp(dst
.type(), 1);
1347 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1348 Temp src10
= bld
.tmp(src1
.type(), 1);
1349 Temp src11
= bld
.tmp(dst
.type(), 1);
1350 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1352 if (dst
.regClass() == s2
) {
1353 Temp carry
= bld
.tmp(s1
);
1354 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1355 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1356 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1357 } else if (dst
.regClass() == v2
) {
1358 Temp dst0
= bld
.tmp(v1
);
1359 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1360 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1361 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1363 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1364 nir_print_instr(&instr
->instr
, stderr
);
1365 fprintf(stderr
, "\n");
1369 case nir_op_uadd_sat
: {
1370 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1371 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1372 if (dst
.regClass() == s1
) {
1373 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1374 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1376 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1377 } else if (dst
.regClass() == v1
) {
1378 if (ctx
->options
->chip_class
>= GFX9
) {
1379 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1380 add
->operands
[0] = Operand(src0
);
1381 add
->operands
[1] = Operand(src1
);
1382 add
->definitions
[0] = Definition(dst
);
1384 ctx
->block
->instructions
.emplace_back(std::move(add
));
1386 if (src1
.regClass() != v1
)
1387 std::swap(src0
, src1
);
1388 assert(src1
.regClass() == v1
);
1389 Temp tmp
= bld
.tmp(v1
);
1390 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1391 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1394 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1395 nir_print_instr(&instr
->instr
, stderr
);
1396 fprintf(stderr
, "\n");
1400 case nir_op_uadd_carry
: {
1401 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1402 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1403 if (dst
.regClass() == s1
) {
1404 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1407 if (dst
.regClass() == v1
) {
1408 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1409 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1413 Temp src00
= bld
.tmp(src0
.type(), 1);
1414 Temp src01
= bld
.tmp(dst
.type(), 1);
1415 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1416 Temp src10
= bld
.tmp(src1
.type(), 1);
1417 Temp src11
= bld
.tmp(dst
.type(), 1);
1418 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1419 if (dst
.regClass() == s2
) {
1420 Temp carry
= bld
.tmp(s1
);
1421 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1422 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1423 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1424 } else if (dst
.regClass() == v2
) {
1425 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1426 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1427 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1428 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1430 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1431 nir_print_instr(&instr
->instr
, stderr
);
1432 fprintf(stderr
, "\n");
1437 if (dst
.regClass() == s1
) {
1438 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1442 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1443 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1444 if (dst
.regClass() == v1
) {
1445 bld
.vsub32(Definition(dst
), src0
, src1
);
1449 Temp src00
= bld
.tmp(src0
.type(), 1);
1450 Temp src01
= bld
.tmp(dst
.type(), 1);
1451 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1452 Temp src10
= bld
.tmp(src1
.type(), 1);
1453 Temp src11
= bld
.tmp(dst
.type(), 1);
1454 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1455 if (dst
.regClass() == s2
) {
1456 Temp carry
= bld
.tmp(s1
);
1457 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1458 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1459 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1460 } else if (dst
.regClass() == v2
) {
1461 Temp lower
= bld
.tmp(v1
);
1462 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1463 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1466 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1467 nir_print_instr(&instr
->instr
, stderr
);
1468 fprintf(stderr
, "\n");
1472 case nir_op_usub_borrow
: {
1473 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1474 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1475 if (dst
.regClass() == s1
) {
1476 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1478 } else if (dst
.regClass() == v1
) {
1479 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1480 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1484 Temp src00
= bld
.tmp(src0
.type(), 1);
1485 Temp src01
= bld
.tmp(dst
.type(), 1);
1486 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1487 Temp src10
= bld
.tmp(src1
.type(), 1);
1488 Temp src11
= bld
.tmp(dst
.type(), 1);
1489 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1490 if (dst
.regClass() == s2
) {
1491 Temp borrow
= bld
.tmp(s1
);
1492 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1493 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1495 } else if (dst
.regClass() == v2
) {
1496 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1497 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1498 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1499 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1501 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1502 nir_print_instr(&instr
->instr
, stderr
);
1503 fprintf(stderr
, "\n");
1508 if (dst
.regClass() == v1
) {
1509 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1510 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1511 } else if (dst
.regClass() == s1
) {
1512 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1514 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1515 nir_print_instr(&instr
->instr
, stderr
);
1516 fprintf(stderr
, "\n");
1520 case nir_op_umul_high
: {
1521 if (dst
.regClass() == v1
) {
1522 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1523 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1524 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1525 } else if (dst
.regClass() == s1
) {
1526 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1527 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1528 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1530 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1531 nir_print_instr(&instr
->instr
, stderr
);
1532 fprintf(stderr
, "\n");
1536 case nir_op_imul_high
: {
1537 if (dst
.regClass() == v1
) {
1538 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1539 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1540 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1541 } else if (dst
.regClass() == s1
) {
1542 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1543 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1544 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1546 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1547 nir_print_instr(&instr
->instr
, stderr
);
1548 fprintf(stderr
, "\n");
1553 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1554 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1555 if (dst
.regClass() == v2b
) {
1556 Temp tmp
= bld
.tmp(v1
);
1557 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1558 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1559 } else if (dst
.regClass() == v1
) {
1560 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1561 } else if (dst
.regClass() == v2
) {
1562 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1564 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1565 nir_print_instr(&instr
->instr
, stderr
);
1566 fprintf(stderr
, "\n");
1571 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1572 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1573 if (dst
.regClass() == v2b
) {
1574 Temp tmp
= bld
.tmp(v1
);
1575 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1576 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1577 } else if (dst
.regClass() == v1
) {
1578 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1579 } else if (dst
.regClass() == v2
) {
1580 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1582 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1583 nir_print_instr(&instr
->instr
, stderr
);
1584 fprintf(stderr
, "\n");
1589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1590 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1591 if (dst
.regClass() == v2b
) {
1592 Temp tmp
= bld
.tmp(v1
);
1593 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1594 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1596 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1597 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1598 } else if (dst
.regClass() == v1
) {
1599 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1600 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1602 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1603 } else if (dst
.regClass() == v2
) {
1604 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1606 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1609 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1610 nir_print_instr(&instr
->instr
, stderr
);
1611 fprintf(stderr
, "\n");
1616 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1617 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1618 if (dst
.regClass() == v2b
) {
1619 // TODO: check fp_mode.must_flush_denorms16_64
1620 Temp tmp
= bld
.tmp(v1
);
1621 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1622 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1623 } else if (dst
.regClass() == v1
) {
1624 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1625 } else if (dst
.regClass() == v2
) {
1626 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1627 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1628 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1630 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1633 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1634 nir_print_instr(&instr
->instr
, stderr
);
1635 fprintf(stderr
, "\n");
1640 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1641 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1642 if (dst
.regClass() == v2b
) {
1643 // TODO: check fp_mode.must_flush_denorms16_64
1644 Temp tmp
= bld
.tmp(v1
);
1645 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1646 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1647 } else if (dst
.regClass() == v1
) {
1648 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1649 } else if (dst
.regClass() == v2
) {
1650 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1651 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1652 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1654 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1657 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1658 nir_print_instr(&instr
->instr
, stderr
);
1659 fprintf(stderr
, "\n");
1663 case nir_op_fmax3
: {
1664 if (dst
.regClass() == v2b
) {
1665 Temp tmp
= bld
.tmp(v1
);
1666 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1667 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1668 } else if (dst
.regClass() == v1
) {
1669 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1671 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1672 nir_print_instr(&instr
->instr
, stderr
);
1673 fprintf(stderr
, "\n");
1677 case nir_op_fmin3
: {
1678 if (dst
.regClass() == v2b
) {
1679 Temp tmp
= bld
.tmp(v1
);
1680 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1681 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1682 } else if (dst
.regClass() == v1
) {
1683 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1685 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1686 nir_print_instr(&instr
->instr
, stderr
);
1687 fprintf(stderr
, "\n");
1691 case nir_op_fmed3
: {
1692 if (dst
.regClass() == v2b
) {
1693 Temp tmp
= bld
.tmp(v1
);
1694 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1695 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1696 } else if (dst
.regClass() == v1
) {
1697 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1699 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1700 nir_print_instr(&instr
->instr
, stderr
);
1701 fprintf(stderr
, "\n");
1705 case nir_op_umax3
: {
1706 if (dst
.size() == 1) {
1707 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1709 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1710 nir_print_instr(&instr
->instr
, stderr
);
1711 fprintf(stderr
, "\n");
1715 case nir_op_umin3
: {
1716 if (dst
.size() == 1) {
1717 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1719 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1720 nir_print_instr(&instr
->instr
, stderr
);
1721 fprintf(stderr
, "\n");
1725 case nir_op_umed3
: {
1726 if (dst
.size() == 1) {
1727 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1729 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1730 nir_print_instr(&instr
->instr
, stderr
);
1731 fprintf(stderr
, "\n");
1735 case nir_op_imax3
: {
1736 if (dst
.size() == 1) {
1737 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1739 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1740 nir_print_instr(&instr
->instr
, stderr
);
1741 fprintf(stderr
, "\n");
1745 case nir_op_imin3
: {
1746 if (dst
.size() == 1) {
1747 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1749 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1750 nir_print_instr(&instr
->instr
, stderr
);
1751 fprintf(stderr
, "\n");
1755 case nir_op_imed3
: {
1756 if (dst
.size() == 1) {
1757 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1759 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1760 nir_print_instr(&instr
->instr
, stderr
);
1761 fprintf(stderr
, "\n");
1765 case nir_op_cube_face_coord
: {
1766 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1767 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1768 emit_extract_vector(ctx
, in
, 1, v1
),
1769 emit_extract_vector(ctx
, in
, 2, v1
) };
1770 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1771 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1772 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1773 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1774 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1775 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1776 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1779 case nir_op_cube_face_index
: {
1780 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1781 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1782 emit_extract_vector(ctx
, in
, 1, v1
),
1783 emit_extract_vector(ctx
, in
, 2, v1
) };
1784 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1787 case nir_op_bcsel
: {
1788 emit_bcsel(ctx
, instr
, dst
);
1792 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1793 if (dst
.regClass() == v2b
) {
1794 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1795 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1796 } else if (dst
.regClass() == v1
) {
1797 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1798 } else if (dst
.regClass() == v2
) {
1799 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1801 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1802 nir_print_instr(&instr
->instr
, stderr
);
1803 fprintf(stderr
, "\n");
1808 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1809 if (dst
.regClass() == v2b
) {
1810 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1811 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1812 } else if (dst
.regClass() == v1
) {
1813 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1814 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1815 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1816 } else if (dst
.regClass() == v2
) {
1817 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1818 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1819 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1820 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1821 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1822 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1825 nir_print_instr(&instr
->instr
, stderr
);
1826 fprintf(stderr
, "\n");
1831 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1832 if (dst
.regClass() == v2b
) {
1833 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1834 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1835 } else if (dst
.regClass() == v1
) {
1836 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1837 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1838 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1839 } else if (dst
.regClass() == v2
) {
1840 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1841 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1842 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1843 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1844 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1845 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1847 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1848 nir_print_instr(&instr
->instr
, stderr
);
1849 fprintf(stderr
, "\n");
1854 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1855 if (dst
.regClass() == v2b
) {
1856 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1857 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1858 } else if (dst
.regClass() == v1
) {
1859 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1860 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1861 // TODO: confirm that this holds under any circumstances
1862 } else if (dst
.regClass() == v2
) {
1863 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1864 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1867 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1868 nir_print_instr(&instr
->instr
, stderr
);
1869 fprintf(stderr
, "\n");
1873 case nir_op_flog2
: {
1874 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1875 if (dst
.regClass() == v2b
) {
1876 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1877 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1878 } else if (dst
.regClass() == v1
) {
1879 emit_log2(ctx
, bld
, Definition(dst
), src
);
1881 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1882 nir_print_instr(&instr
->instr
, stderr
);
1883 fprintf(stderr
, "\n");
1888 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1889 if (dst
.regClass() == v2b
) {
1890 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1891 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1892 } else if (dst
.regClass() == v1
) {
1893 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1894 } else if (dst
.regClass() == v2
) {
1895 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1897 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1898 nir_print_instr(&instr
->instr
, stderr
);
1899 fprintf(stderr
, "\n");
1903 case nir_op_fexp2
: {
1904 if (dst
.regClass() == v2b
) {
1905 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1906 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1907 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1908 } else if (dst
.regClass() == v1
) {
1909 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1911 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1912 nir_print_instr(&instr
->instr
, stderr
);
1913 fprintf(stderr
, "\n");
1917 case nir_op_fsqrt
: {
1918 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1919 if (dst
.regClass() == v2b
) {
1920 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1921 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1922 } else if (dst
.regClass() == v1
) {
1923 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1924 } else if (dst
.regClass() == v2
) {
1925 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1927 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1928 nir_print_instr(&instr
->instr
, stderr
);
1929 fprintf(stderr
, "\n");
1933 case nir_op_ffract
: {
1934 if (dst
.regClass() == v2b
) {
1935 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1936 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1937 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1938 } else if (dst
.regClass() == v1
) {
1939 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1940 } else if (dst
.regClass() == v2
) {
1941 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1943 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1944 nir_print_instr(&instr
->instr
, stderr
);
1945 fprintf(stderr
, "\n");
1949 case nir_op_ffloor
: {
1950 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1951 if (dst
.regClass() == v2b
) {
1952 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1953 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1954 } else if (dst
.regClass() == v1
) {
1955 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1956 } else if (dst
.regClass() == v2
) {
1957 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1959 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1960 nir_print_instr(&instr
->instr
, stderr
);
1961 fprintf(stderr
, "\n");
1965 case nir_op_fceil
: {
1966 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1967 if (dst
.regClass() == v2b
) {
1968 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
1969 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1970 } else if (dst
.regClass() == v1
) {
1971 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1972 } else if (dst
.regClass() == v2
) {
1973 if (ctx
->options
->chip_class
>= GFX7
) {
1974 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1976 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1977 /* trunc = trunc(src0)
1978 * if (src0 > 0.0 && src0 != trunc)
1981 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1982 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1983 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1984 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1985 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1986 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1987 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1990 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1991 nir_print_instr(&instr
->instr
, stderr
);
1992 fprintf(stderr
, "\n");
1996 case nir_op_ftrunc
: {
1997 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1998 if (dst
.regClass() == v2b
) {
1999 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2000 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2001 } else if (dst
.regClass() == v1
) {
2002 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2003 } else if (dst
.regClass() == v2
) {
2004 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2006 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2007 nir_print_instr(&instr
->instr
, stderr
);
2008 fprintf(stderr
, "\n");
2012 case nir_op_fround_even
: {
2013 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2014 if (dst
.regClass() == v2b
) {
2015 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2016 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2017 } else if (dst
.regClass() == v1
) {
2018 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2019 } else if (dst
.regClass() == v2
) {
2020 if (ctx
->options
->chip_class
>= GFX7
) {
2021 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2023 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2024 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2025 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2027 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2028 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2029 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2030 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2031 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2032 tmp
= sub
->definitions
[0].getTemp();
2034 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2035 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2036 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2037 Temp cond
= vop3
->definitions
[0].getTemp();
2039 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2040 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2041 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2042 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2044 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2055 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2056 aco_ptr
<Instruction
> norm
;
2057 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2058 if (dst
.regClass() == v2b
) {
2059 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2060 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2061 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2062 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2063 } else if (dst
.regClass() == v1
) {
2064 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2066 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2067 if (ctx
->options
->chip_class
< GFX9
)
2068 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2070 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2071 bld
.vop1(opcode
, Definition(dst
), tmp
);
2073 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2074 nir_print_instr(&instr
->instr
, stderr
);
2075 fprintf(stderr
, "\n");
2079 case nir_op_ldexp
: {
2080 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2081 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2082 if (dst
.regClass() == v2b
) {
2083 Temp tmp
= bld
.tmp(v1
);
2084 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2085 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2086 } else if (dst
.regClass() == v1
) {
2087 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2088 } else if (dst
.regClass() == v2
) {
2089 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2091 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2092 nir_print_instr(&instr
->instr
, stderr
);
2093 fprintf(stderr
, "\n");
2097 case nir_op_frexp_sig
: {
2098 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2099 if (dst
.regClass() == v2b
) {
2100 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2101 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2102 } else if (dst
.regClass() == v1
) {
2103 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2104 } else if (dst
.regClass() == v2
) {
2105 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2107 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2108 nir_print_instr(&instr
->instr
, stderr
);
2109 fprintf(stderr
, "\n");
2113 case nir_op_frexp_exp
: {
2114 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2115 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2116 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2117 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), tmp
, Operand(0u));
2118 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2119 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2120 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2121 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2123 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2124 nir_print_instr(&instr
->instr
, stderr
);
2125 fprintf(stderr
, "\n");
2129 case nir_op_fsign
: {
2130 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2131 if (dst
.regClass() == v2b
) {
2132 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2133 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2134 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2135 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2136 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2137 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2138 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2139 } else if (dst
.regClass() == v1
) {
2140 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2141 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2142 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2143 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2144 } else if (dst
.regClass() == v2
) {
2145 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2146 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2147 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2149 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2150 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2151 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2153 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2155 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2156 nir_print_instr(&instr
->instr
, stderr
);
2157 fprintf(stderr
, "\n");
2162 case nir_op_f2f16_rtne
: {
2163 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2164 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2165 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2166 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2167 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2170 case nir_op_f2f16_rtz
: {
2171 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2172 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2173 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2174 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2175 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2178 case nir_op_f2f32
: {
2179 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2180 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2181 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2182 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2184 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2185 nir_print_instr(&instr
->instr
, stderr
);
2186 fprintf(stderr
, "\n");
2190 case nir_op_f2f64
: {
2191 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2192 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2193 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2194 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2197 case nir_op_i2f32
: {
2198 assert(dst
.size() == 1);
2199 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2202 case nir_op_i2f64
: {
2203 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2204 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2205 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2206 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2207 RegClass rc
= RegClass(src
.type(), 1);
2208 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2209 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2210 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2211 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2212 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2213 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2216 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2217 nir_print_instr(&instr
->instr
, stderr
);
2218 fprintf(stderr
, "\n");
2222 case nir_op_u2f32
: {
2223 assert(dst
.size() == 1);
2224 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2227 case nir_op_u2f64
: {
2228 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2229 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2230 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2231 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2232 RegClass rc
= RegClass(src
.type(), 1);
2233 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2234 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2235 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2236 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2237 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2238 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2240 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2241 nir_print_instr(&instr
->instr
, stderr
);
2242 fprintf(stderr
, "\n");
2246 case nir_op_f2i16
: {
2247 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2248 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2249 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2250 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2251 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2253 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2255 if (dst
.type() == RegType::vgpr
)
2256 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2258 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2261 case nir_op_f2u16
: {
2262 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2263 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2264 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2265 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2266 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2268 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2270 if (dst
.type() == RegType::vgpr
)
2271 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2273 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2276 case nir_op_f2i32
: {
2277 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2278 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2279 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2280 if (dst
.type() == RegType::vgpr
) {
2281 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2283 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2284 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2286 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2287 if (dst
.type() == RegType::vgpr
)
2288 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2290 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2291 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2293 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2294 if (dst
.type() == RegType::vgpr
)
2295 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2297 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2298 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2301 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2302 nir_print_instr(&instr
->instr
, stderr
);
2303 fprintf(stderr
, "\n");
2307 case nir_op_f2u32
: {
2308 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2309 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2310 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2311 if (dst
.type() == RegType::vgpr
) {
2312 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2314 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2315 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2317 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2318 if (dst
.type() == RegType::vgpr
)
2319 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2321 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2322 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2324 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2325 if (dst
.type() == RegType::vgpr
)
2326 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2328 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2329 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2332 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2333 nir_print_instr(&instr
->instr
, stderr
);
2334 fprintf(stderr
, "\n");
2338 case nir_op_f2i64
: {
2339 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2340 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2341 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2342 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2343 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2344 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2345 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2346 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2347 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2348 Temp new_exponent
= bld
.tmp(v1
);
2349 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2350 if (ctx
->program
->chip_class
>= GFX8
)
2351 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2353 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2354 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2355 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2356 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2357 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2358 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2359 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2360 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2361 Temp new_lower
= bld
.tmp(v1
);
2362 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2363 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2364 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2366 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2367 if (src
.type() == RegType::vgpr
)
2368 src
= bld
.as_uniform(src
);
2369 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2370 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2371 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2372 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2373 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2374 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2375 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2376 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2377 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2378 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2379 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2380 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2381 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2382 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2383 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2384 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2385 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2386 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2387 Temp borrow
= bld
.tmp(s1
);
2388 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2389 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2390 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2392 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2393 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2394 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2395 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2396 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2397 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2398 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2399 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2400 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2401 if (dst
.type() == RegType::sgpr
) {
2402 lower
= bld
.as_uniform(lower
);
2403 upper
= bld
.as_uniform(upper
);
2405 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2408 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2409 nir_print_instr(&instr
->instr
, stderr
);
2410 fprintf(stderr
, "\n");
2414 case nir_op_f2u64
: {
2415 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2416 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2417 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2418 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2419 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2420 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2421 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2422 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2423 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2424 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2425 Temp new_exponent
= bld
.tmp(v1
);
2426 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2427 if (ctx
->program
->chip_class
>= GFX8
)
2428 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2430 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2431 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2432 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2433 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2434 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2435 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2436 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2437 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2439 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2440 if (src
.type() == RegType::vgpr
)
2441 src
= bld
.as_uniform(src
);
2442 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2443 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2444 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2445 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2446 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2447 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2448 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2449 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2450 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2451 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2452 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2453 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2454 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2455 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2456 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2457 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2458 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2459 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2461 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2462 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2463 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2464 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2465 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2466 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2467 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2468 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2469 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2470 if (dst
.type() == RegType::sgpr
) {
2471 lower
= bld
.as_uniform(lower
);
2472 upper
= bld
.as_uniform(upper
);
2474 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2477 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2478 nir_print_instr(&instr
->instr
, stderr
);
2479 fprintf(stderr
, "\n");
2483 case nir_op_b2f32
: {
2484 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2485 assert(src
.regClass() == bld
.lm
);
2487 if (dst
.regClass() == s1
) {
2488 src
= bool_to_scalar_condition(ctx
, src
);
2489 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2490 } else if (dst
.regClass() == v1
) {
2491 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2493 unreachable("Wrong destination register class for nir_op_b2f32.");
2497 case nir_op_b2f64
: {
2498 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2499 assert(src
.regClass() == bld
.lm
);
2501 if (dst
.regClass() == s2
) {
2502 src
= bool_to_scalar_condition(ctx
, src
);
2503 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2504 } else if (dst
.regClass() == v2
) {
2505 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2506 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2507 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2509 unreachable("Wrong destination register class for nir_op_b2f64.");
2515 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2516 /* we can actually just say dst = src */
2517 if (src
.regClass() == s1
)
2518 bld
.copy(Definition(dst
), src
);
2520 emit_extract_vector(ctx
, src
, 0, dst
);
2523 case nir_op_i2i16
: {
2524 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2525 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2526 if (dst
.regClass() == s1
) {
2527 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2529 assert(src
.regClass() == v1b
);
2530 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2531 sdwa
->operands
[0] = Operand(src
);
2532 sdwa
->definitions
[0] = Definition(dst
);
2533 sdwa
->sel
[0] = sdwa_sbyte
;
2534 sdwa
->dst_sel
= sdwa_sword
;
2535 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2538 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2539 /* we can actually just say dst = src */
2540 if (src
.regClass() == s1
)
2541 bld
.copy(Definition(dst
), src
);
2543 emit_extract_vector(ctx
, src
, 0, dst
);
2547 case nir_op_u2u16
: {
2548 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2549 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2550 if (dst
.regClass() == s1
)
2551 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2553 assert(src
.regClass() == v1b
);
2554 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2555 sdwa
->operands
[0] = Operand(src
);
2556 sdwa
->definitions
[0] = Definition(dst
);
2557 sdwa
->sel
[0] = sdwa_ubyte
;
2558 sdwa
->dst_sel
= sdwa_uword
;
2559 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2562 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2563 /* we can actually just say dst = src */
2564 if (src
.regClass() == s1
)
2565 bld
.copy(Definition(dst
), src
);
2567 emit_extract_vector(ctx
, src
, 0, dst
);
2571 case nir_op_i2i32
: {
2572 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2573 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2574 if (dst
.regClass() == s1
) {
2575 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2577 assert(src
.regClass() == v1b
);
2578 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2579 sdwa
->operands
[0] = Operand(src
);
2580 sdwa
->definitions
[0] = Definition(dst
);
2581 sdwa
->sel
[0] = sdwa_sbyte
;
2582 sdwa
->dst_sel
= sdwa_sdword
;
2583 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2585 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2586 if (dst
.regClass() == s1
) {
2587 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2589 assert(src
.regClass() == v2b
);
2590 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2591 sdwa
->operands
[0] = Operand(src
);
2592 sdwa
->definitions
[0] = Definition(dst
);
2593 sdwa
->sel
[0] = sdwa_sword
;
2594 sdwa
->dst_sel
= sdwa_udword
;
2595 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2597 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2598 /* we can actually just say dst = src, as it would map the lower register */
2599 emit_extract_vector(ctx
, src
, 0, dst
);
2601 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2602 nir_print_instr(&instr
->instr
, stderr
);
2603 fprintf(stderr
, "\n");
2607 case nir_op_u2u32
: {
2608 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2609 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2610 if (dst
.regClass() == s1
)
2611 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2613 assert(src
.regClass() == v1b
);
2614 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2615 sdwa
->operands
[0] = Operand(src
);
2616 sdwa
->definitions
[0] = Definition(dst
);
2617 sdwa
->sel
[0] = sdwa_ubyte
;
2618 sdwa
->dst_sel
= sdwa_udword
;
2619 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2621 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2622 if (dst
.regClass() == s1
) {
2623 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2625 assert(src
.regClass() == v2b
);
2626 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2627 sdwa
->operands
[0] = Operand(src
);
2628 sdwa
->definitions
[0] = Definition(dst
);
2629 sdwa
->sel
[0] = sdwa_uword
;
2630 sdwa
->dst_sel
= sdwa_udword
;
2631 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2633 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2634 /* we can actually just say dst = src, as it would map the lower register */
2635 emit_extract_vector(ctx
, src
, 0, dst
);
2637 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2638 nir_print_instr(&instr
->instr
, stderr
);
2639 fprintf(stderr
, "\n");
2643 case nir_op_i2i64
: {
2644 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2645 if (src
.regClass() == s1
) {
2646 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2647 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2648 } else if (src
.regClass() == v1
) {
2649 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2650 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2652 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2653 nir_print_instr(&instr
->instr
, stderr
);
2654 fprintf(stderr
, "\n");
2658 case nir_op_u2u64
: {
2659 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2660 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2661 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2663 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2664 nir_print_instr(&instr
->instr
, stderr
);
2665 fprintf(stderr
, "\n");
2670 case nir_op_b2i32
: {
2671 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2672 assert(src
.regClass() == bld
.lm
);
2674 if (dst
.regClass() == s1
) {
2675 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2676 bool_to_scalar_condition(ctx
, src
, dst
);
2677 } else if (dst
.regClass() == v1
) {
2678 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2680 unreachable("Invalid register class for b2i32");
2686 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2687 assert(dst
.regClass() == bld
.lm
);
2689 if (src
.type() == RegType::vgpr
) {
2690 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2691 assert(dst
.regClass() == bld
.lm
);
2692 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2693 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2695 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2697 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2698 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2700 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2701 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2703 bool_to_vector_condition(ctx
, tmp
, dst
);
2707 case nir_op_pack_64_2x32_split
: {
2708 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2709 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2711 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2714 case nir_op_unpack_64_2x32_split_x
:
2715 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2717 case nir_op_unpack_64_2x32_split_y
:
2718 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2720 case nir_op_unpack_32_2x16_split_x
:
2721 if (dst
.type() == RegType::vgpr
) {
2722 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2724 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2727 case nir_op_unpack_32_2x16_split_y
:
2728 if (dst
.type() == RegType::vgpr
) {
2729 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2731 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2734 case nir_op_pack_32_2x16_split
: {
2735 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2736 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2737 if (dst
.regClass() == v1
) {
2738 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2740 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2741 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2742 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2746 case nir_op_pack_half_2x16
: {
2747 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2749 if (dst
.regClass() == v1
) {
2750 Temp src0
= bld
.tmp(v1
);
2751 Temp src1
= bld
.tmp(v1
);
2752 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2753 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2754 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2756 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2757 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2758 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2760 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2761 nir_print_instr(&instr
->instr
, stderr
);
2762 fprintf(stderr
, "\n");
2766 case nir_op_unpack_half_2x16_split_x
: {
2767 if (dst
.regClass() == v1
) {
2768 Builder
bld(ctx
->program
, ctx
->block
);
2769 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2771 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2772 nir_print_instr(&instr
->instr
, stderr
);
2773 fprintf(stderr
, "\n");
2777 case nir_op_unpack_half_2x16_split_y
: {
2778 if (dst
.regClass() == v1
) {
2779 Builder
bld(ctx
->program
, ctx
->block
);
2780 /* TODO: use SDWA here */
2781 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2782 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2784 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2785 nir_print_instr(&instr
->instr
, stderr
);
2786 fprintf(stderr
, "\n");
2790 case nir_op_fquantize2f16
: {
2791 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2792 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2795 if (ctx
->program
->chip_class
>= GFX8
) {
2796 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2797 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2798 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2800 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2801 * so compare the result and flush to 0 if it's smaller.
2803 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2804 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2805 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2806 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2807 cmp_res
= vop3
->definitions
[0].getTemp();
2810 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2811 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2812 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2814 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2819 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2820 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2822 if (dst
.regClass() == s1
) {
2823 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2824 } else if (dst
.regClass() == v1
) {
2825 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2827 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2828 nir_print_instr(&instr
->instr
, stderr
);
2829 fprintf(stderr
, "\n");
2833 case nir_op_bitfield_select
: {
2834 /* (mask & insert) | (~mask & base) */
2835 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2836 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2837 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2839 /* dst = (insert & bitmask) | (base & ~bitmask) */
2840 if (dst
.regClass() == s1
) {
2841 aco_ptr
<Instruction
> sop2
;
2842 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2843 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2845 if (const_insert
&& const_bitmask
) {
2846 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2848 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2849 lhs
= Operand(insert
);
2853 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2854 if (const_base
&& const_bitmask
) {
2855 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2857 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2858 rhs
= Operand(base
);
2861 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2863 } else if (dst
.regClass() == v1
) {
2864 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2865 base
= as_vgpr(ctx
, base
);
2866 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2867 insert
= as_vgpr(ctx
, insert
);
2869 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2872 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2873 nir_print_instr(&instr
->instr
, stderr
);
2874 fprintf(stderr
, "\n");
2880 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2881 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2882 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2884 if (dst
.type() == RegType::sgpr
) {
2886 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2887 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2888 if (const_offset
&& const_bits
) {
2889 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2890 extract
= Operand(const_extract
);
2894 width
= Operand(const_bits
->u32
<< 16);
2896 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2898 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2902 if (dst
.regClass() == s1
) {
2903 if (instr
->op
== nir_op_ubfe
)
2904 opcode
= aco_opcode::s_bfe_u32
;
2906 opcode
= aco_opcode::s_bfe_i32
;
2907 } else if (dst
.regClass() == s2
) {
2908 if (instr
->op
== nir_op_ubfe
)
2909 opcode
= aco_opcode::s_bfe_u64
;
2911 opcode
= aco_opcode::s_bfe_i64
;
2913 unreachable("Unsupported BFE bit size");
2916 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2920 if (dst
.regClass() == v1
) {
2921 if (instr
->op
== nir_op_ubfe
)
2922 opcode
= aco_opcode::v_bfe_u32
;
2924 opcode
= aco_opcode::v_bfe_i32
;
2926 unreachable("Unsupported BFE bit size");
2929 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2933 case nir_op_bit_count
: {
2934 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2935 if (src
.regClass() == s1
) {
2936 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2937 } else if (src
.regClass() == v1
) {
2938 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2939 } else if (src
.regClass() == v2
) {
2940 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2941 emit_extract_vector(ctx
, src
, 1, v1
),
2942 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2943 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2944 } else if (src
.regClass() == s2
) {
2945 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2947 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2948 nir_print_instr(&instr
->instr
, stderr
);
2949 fprintf(stderr
, "\n");
2954 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2958 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2962 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2966 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2970 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2974 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2978 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2979 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2981 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2982 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2986 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2987 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2989 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2990 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2994 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2998 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3003 case nir_op_fddx_fine
:
3004 case nir_op_fddy_fine
:
3005 case nir_op_fddx_coarse
:
3006 case nir_op_fddy_coarse
: {
3007 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3008 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3009 if (instr
->op
== nir_op_fddx_fine
) {
3010 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3011 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3012 } else if (instr
->op
== nir_op_fddy_fine
) {
3013 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3014 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3016 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3017 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3018 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3020 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3024 if (ctx
->program
->chip_class
>= GFX8
) {
3025 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3026 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3028 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3029 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3030 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3032 emit_wqm(ctx
, tmp
, dst
, true);
3036 fprintf(stderr
, "Unknown NIR ALU instr: ");
3037 nir_print_instr(&instr
->instr
, stderr
);
3038 fprintf(stderr
, "\n");
3042 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3044 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3046 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3047 // which get truncated the lsb if double and msb if int
3048 // for now, we only use s_mov_b64 with 64bit inline constants
3049 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3050 assert(dst
.type() == RegType::sgpr
);
3052 Builder
bld(ctx
->program
, ctx
->block
);
3054 if (instr
->def
.bit_size
== 1) {
3055 assert(dst
.regClass() == bld
.lm
);
3056 int val
= instr
->value
[0].b
? -1 : 0;
3057 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3058 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3059 } else if (dst
.size() == 1) {
3060 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3062 assert(dst
.size() != 1);
3063 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3064 if (instr
->def
.bit_size
== 64)
3065 for (unsigned i
= 0; i
< dst
.size(); i
++)
3066 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3068 for (unsigned i
= 0; i
< dst
.size(); i
++)
3069 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3071 vec
->definitions
[0] = Definition(dst
);
3072 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3076 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3078 uint32_t new_mask
= 0;
3079 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3080 if (mask
& (1u << i
))
3081 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3085 Operand
load_lds_size_m0(isel_context
*ctx
)
3087 /* TODO: m0 does not need to be initialized on GFX9+ */
3088 Builder
bld(ctx
->program
, ctx
->block
);
3089 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3092 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3093 Temp address
, unsigned base_offset
, unsigned align
)
3095 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3097 Builder
bld(ctx
->program
, ctx
->block
);
3099 Operand m
= load_lds_size_m0(ctx
);
3101 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
3102 unsigned bytes_read
= 0;
3103 unsigned result_size
= 0;
3104 unsigned total_bytes
= num_components
* elem_size_bytes
;
3105 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
3106 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
3107 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
3109 while (bytes_read
< total_bytes
) {
3110 unsigned todo
= total_bytes
- bytes_read
;
3111 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
3112 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
3114 aco_opcode op
= aco_opcode::last_opcode
;
3116 if (todo
>= 16 && aligned16
&& large_ds_read
) {
3117 op
= aco_opcode::ds_read_b128
;
3119 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
3120 op
= aco_opcode::ds_read2_b64
;
3123 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
3124 op
= aco_opcode::ds_read_b96
;
3126 } else if (todo
>= 8 && aligned8
) {
3127 op
= aco_opcode::ds_read_b64
;
3129 } else if (todo
>= 8 && usable_read2
) {
3130 op
= aco_opcode::ds_read2_b32
;
3133 } else if (todo
>= 4) {
3134 op
= aco_opcode::ds_read_b32
;
3139 assert(todo
% elem_size_bytes
== 0);
3140 unsigned num_elements
= todo
/ elem_size_bytes
;
3141 unsigned offset
= base_offset
+ bytes_read
;
3142 unsigned max_offset
= read2
? 1019 : 65535;
3144 Temp address_offset
= address
;
3145 if (offset
> max_offset
) {
3146 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3147 offset
= bytes_read
;
3149 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3152 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3155 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3158 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3160 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3162 if (num_components
== 1) {
3163 assert(todo
== total_bytes
);
3164 if (dst
.type() == RegType::sgpr
)
3165 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3169 if (dst
.type() == RegType::sgpr
) {
3170 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3171 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3175 if (num_elements
== 1) {
3176 result
[result_size
++] = res
;
3178 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3179 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3180 split
->operands
[0] = Operand(res
);
3181 for (unsigned i
= 0; i
< num_elements
; i
++)
3182 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3183 ctx
->block
->instructions
.emplace_back(std::move(split
));
3189 assert(result_size
== num_components
&& result_size
> 1);
3190 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3191 for (unsigned i
= 0; i
< result_size
; i
++)
3192 vec
->operands
[i
] = Operand(result
[i
]);
3193 vec
->definitions
[0] = Definition(dst
);
3194 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3195 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3200 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3202 if (start
== 0 && size
== data
.size())
3203 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3205 unsigned size_hint
= 1;
3206 auto it
= ctx
->allocated_vec
.find(data
.id());
3207 if (it
!= ctx
->allocated_vec
.end())
3208 size_hint
= it
->second
[0].size();
3209 if (size
% size_hint
|| start
% size_hint
)
3216 for (unsigned i
= 0; i
< size
; i
++)
3217 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3220 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3222 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3223 for (unsigned i
= 0; i
< size
; i
++)
3224 vec
->operands
[i
] = Operand(elems
[i
]);
3225 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3226 vec
->definitions
[0] = Definition(res
);
3227 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3231 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3233 Builder
bld(ctx
->program
, ctx
->block
);
3234 unsigned bytes_written
= 0;
3235 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3236 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3238 while (bytes_written
< total_size
* 4) {
3239 unsigned todo
= total_size
* 4 - bytes_written
;
3240 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3241 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3243 aco_opcode op
= aco_opcode::last_opcode
;
3244 bool write2
= false;
3246 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3247 op
= aco_opcode::ds_write_b128
;
3249 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3250 op
= aco_opcode::ds_write2_b64
;
3253 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3254 op
= aco_opcode::ds_write_b96
;
3256 } else if (todo
>= 8 && aligned8
) {
3257 op
= aco_opcode::ds_write_b64
;
3259 } else if (todo
>= 8 && usable_write2
) {
3260 op
= aco_opcode::ds_write2_b32
;
3263 } else if (todo
>= 4) {
3264 op
= aco_opcode::ds_write_b32
;
3270 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3271 unsigned max_offset
= write2
? 1020 : 65535;
3272 Temp address_offset
= address
;
3273 if (offset
> max_offset
) {
3274 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3275 offset
= offset1
+ bytes_written
;
3277 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3280 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3281 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3282 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3284 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3285 bld
.ds(op
, address_offset
, val
, m
, offset
);
3288 bytes_written
+= size
* 4;
3292 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3293 Temp address
, unsigned base_offset
, unsigned align
)
3295 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3296 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3298 Operand m
= load_lds_size_m0(ctx
);
3300 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3301 assert(wrmask
<= 0x0f);
3302 int start
[2], count
[2];
3303 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3304 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3305 assert(wrmask
== 0);
3307 /* one combined store is sufficient */
3308 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3309 Builder
bld(ctx
->program
, ctx
->block
);
3311 Temp address_offset
= address
;
3312 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3313 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3317 assert(count
[0] == 1);
3318 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3320 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3321 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3322 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3323 base_offset
= base_offset
/ elem_size_bytes
;
3324 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3325 base_offset
+ start
[0], base_offset
+ start
[1]);
3329 for (unsigned i
= 0; i
< 2; i
++) {
3333 unsigned elem_size_words
= elem_size_bytes
/ 4;
3334 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3335 base_offset
, start
[i
] * elem_size_bytes
, align
);
3340 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3342 unsigned align
= 16;
3344 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3350 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3351 unsigned split_cnt
= 0u, Temp dst
= Temp())
3353 Builder
bld(ctx
->program
, ctx
->block
);
3354 unsigned dword_size
= elem_size_bytes
/ 4;
3357 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3359 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3360 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3361 instr
->definitions
[0] = Definition(dst
);
3363 for (unsigned i
= 0; i
< cnt
; ++i
) {
3365 assert(arr
[i
].size() == dword_size
);
3366 allocated_vec
[i
] = arr
[i
];
3367 instr
->operands
[i
] = Operand(arr
[i
]);
3369 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3370 allocated_vec
[i
] = zero
;
3371 instr
->operands
[i
] = Operand(zero
);
3375 bld
.insert(std::move(instr
));
3378 emit_split_vector(ctx
, dst
, split_cnt
);
3380 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3385 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3387 if (const_offset
>= 4096) {
3388 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3389 const_offset
%= 4096u;
3392 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3393 else if (unlikely(voffset
.regClass() == s1
))
3394 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3395 else if (likely(voffset
.regClass() == v1
))
3396 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3398 unreachable("Unsupported register class of voffset");
3401 return const_offset
;
3404 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3405 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3408 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3409 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3411 Builder
bld(ctx
->program
, ctx
->block
);
3412 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3413 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3415 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3416 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3417 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3418 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3419 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3421 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3424 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3425 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3426 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3428 Builder
bld(ctx
->program
, ctx
->block
);
3429 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3432 if (elem_size_bytes
== 8) {
3433 elem_size_bytes
= 4;
3434 write_mask
= widen_mask(write_mask
, 2);
3437 while (write_mask
) {
3440 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3445 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3446 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3448 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3449 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3452 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3453 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3463 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3464 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3466 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3467 assert(size_dwords
>= 1 && size_dwords
<= 4);
3469 Builder
bld(ctx
->program
, ctx
->block
);
3470 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3471 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3472 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3474 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3475 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3476 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3477 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3478 /* disable_wqm */ false, /* glc */ true,
3479 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3481 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3486 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3487 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3488 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3490 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3491 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3492 assert(!!stride
!= allow_combining
);
3494 Builder
bld(ctx
->program
, ctx
->block
);
3495 unsigned split_cnt
= num_components
;
3497 if (elem_size_bytes
== 8) {
3498 elem_size_bytes
= 4;
3499 num_components
*= 2;
3503 stride
= elem_size_bytes
;
3505 unsigned load_size
= 1;
3506 if (allow_combining
) {
3507 if ((num_components
% 4) == 0)
3509 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3511 else if ((num_components
% 2) == 0)
3515 unsigned num_loads
= num_components
/ load_size
;
3516 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3518 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3519 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3520 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3523 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3526 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3528 Builder
bld(ctx
->program
, ctx
->block
);
3529 Temp offset
= base_offset
.first
;
3530 unsigned const_offset
= base_offset
.second
;
3532 if (!nir_src_is_const(*off_src
)) {
3533 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3536 /* Calculate indirect offset with stride */
3537 if (likely(indirect_offset_arg
.regClass() == v1
))
3538 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3539 else if (indirect_offset_arg
.regClass() == s1
)
3540 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3542 unreachable("Unsupported register class of indirect offset");
3544 /* Add to the supplied base offset */
3545 if (offset
.id() == 0)
3546 offset
= with_stride
;
3547 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3548 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3549 else if (offset
.size() == 1 && with_stride
.size() == 1)
3550 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3552 unreachable("Unsupported register class of indirect offset");
3554 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3555 const_offset
+= const_offset_arg
* stride
;
3558 return std::make_pair(offset
, const_offset
);
3561 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3563 Builder
bld(ctx
->program
, ctx
->block
);
3566 if (off1
.first
.id() && off2
.first
.id()) {
3567 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3568 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3569 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3570 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3572 unreachable("Unsupported register class of indirect offset");
3574 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3577 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3580 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3582 Builder
bld(ctx
->program
, ctx
->block
);
3583 unsigned const_offset
= offs
.second
* multiplier
;
3585 if (!offs
.first
.id())
3586 return std::make_pair(offs
.first
, const_offset
);
3588 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3589 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3590 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3592 return std::make_pair(offset
, const_offset
);
3595 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3597 Builder
bld(ctx
->program
, ctx
->block
);
3599 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3600 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3601 /* component is in bytes */
3602 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3604 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3605 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3606 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3609 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3611 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3614 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3616 Builder
bld(ctx
->program
, ctx
->block
);
3618 switch (ctx
->shader
->info
.stage
) {
3619 case MESA_SHADER_TESS_CTRL
:
3620 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3621 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3622 case MESA_SHADER_TESS_EVAL
:
3623 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3625 unreachable("Unsupported stage in get_tess_rel_patch_id");
3629 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3631 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3632 Builder
bld(ctx
->program
, ctx
->block
);
3634 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3635 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3637 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3639 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3640 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3642 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3643 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3644 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3646 return offset_mul(ctx
, offs
, 4u);
3649 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3651 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3652 Builder
bld(ctx
->program
, ctx
->block
);
3654 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3655 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3656 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3657 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3658 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3659 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3661 std::pair
<Temp
, unsigned> offs
= instr
3662 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3663 : std::make_pair(Temp(), 0u);
3665 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3666 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3671 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3672 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3674 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3675 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3677 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3678 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3684 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3686 Builder
bld(ctx
->program
, ctx
->block
);
3688 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3689 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3691 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3693 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3694 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3695 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3697 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3698 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3703 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3705 Builder
bld(ctx
->program
, ctx
->block
);
3707 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3708 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3709 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3711 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3712 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3713 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3714 unsigned attr_stride
= ctx
->tcs_num_patches
;
3716 std::pair
<Temp
, unsigned> offs
= instr
3717 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3718 : std::make_pair(Temp(), 0u);
3720 if (const_base_offset
)
3721 offs
.second
+= const_base_offset
* attr_stride
;
3723 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3724 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3725 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3730 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3732 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3733 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3735 if (!nir_src_is_const(*off_src
)) {
3741 off
+= nir_src_as_uint(*off_src
) * 16u;
3744 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3745 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3752 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3754 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3755 unsigned component
= nir_intrinsic_component(instr
);
3756 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3758 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3759 if (off_instr
->type
!= nir_instr_type_load_const
)
3762 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3763 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3765 if (instr
->src
[0].ssa
->bit_size
== 64)
3766 write_mask
= widen_mask(write_mask
, 2);
3768 for (unsigned i
= 0; i
< 8; ++i
) {
3769 if (write_mask
& (1 << i
)) {
3770 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3771 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3779 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3781 /* Only TCS per-vertex inputs are supported by this function.
3782 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3784 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3787 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3788 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3789 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3790 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3791 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3792 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3797 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3798 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3799 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3800 assert(vec
.size() == dst
.size());
3802 Builder
bld(ctx
->program
, ctx
->block
);
3803 bld
.copy(Definition(dst
), vec
);
3807 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3809 Builder
bld(ctx
->program
, ctx
->block
);
3811 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3812 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3813 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3814 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3816 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3817 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3818 bool indirect_write
;
3819 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3820 if (temp_only_input
&& !indirect_write
)
3824 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3825 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3826 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3827 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3828 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3832 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3833 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3834 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3835 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3836 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3837 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3838 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3839 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3840 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3841 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3842 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3843 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3844 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3846 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3847 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3848 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3850 unreachable("Invalid LS or ES stage");
3853 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3854 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3855 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3859 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3861 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3862 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3863 off
!= ctx
->tcs_tess_lvl_in_loc
;
3866 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3868 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3869 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3872 uint64_t mask
= per_vertex
3873 ? ctx
->shader
->info
.outputs_read
3874 : ctx
->shader
->info
.patch_outputs_read
;
3875 bool indirect_write
;
3876 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3877 return indirect_write
|| output_read
;
3880 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3882 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3883 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3885 Builder
bld(ctx
->program
, ctx
->block
);
3887 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3888 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3889 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3891 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3892 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3893 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3894 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3896 if (write_to_vmem
) {
3897 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3898 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3899 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3901 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3902 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3903 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3907 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3908 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3909 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3913 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3915 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3916 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3918 Builder
bld(ctx
->program
, ctx
->block
);
3920 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3921 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3922 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3923 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3925 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3928 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3930 if (ctx
->stage
== vertex_vs
||
3931 ctx
->stage
== tess_eval_vs
||
3932 ctx
->stage
== fragment_fs
||
3933 ctx
->stage
== ngg_vertex_gs
||
3934 ctx
->stage
== ngg_tess_eval_gs
||
3935 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3936 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3937 if (!stored_to_temps
) {
3938 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3939 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3940 fprintf(stderr
, "\n");
3943 } else if (ctx
->stage
== vertex_es
||
3944 ctx
->stage
== vertex_ls
||
3945 ctx
->stage
== tess_eval_es
||
3946 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3947 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3948 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3949 visit_store_ls_or_es_output(ctx
, instr
);
3950 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3951 visit_store_tcs_output(ctx
, instr
, false);
3953 unreachable("Shader stage not implemented");
3957 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3959 visit_load_tcs_output(ctx
, instr
, false);
3962 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3964 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3965 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3967 Builder
bld(ctx
->program
, ctx
->block
);
3968 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3969 if (ctx
->program
->has_16bank_lds
)
3970 interp_p1
.instr
->operands
[0].setLateKill(true);
3971 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
3974 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3976 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3977 for (unsigned i
= 0; i
< num_components
; i
++)
3978 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3979 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3980 assert(num_components
== 4);
3981 Builder
bld(ctx
->program
, ctx
->block
);
3982 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3985 for (Operand
& op
: vec
->operands
)
3986 op
= op
.isUndefined() ? Operand(0u) : op
;
3988 vec
->definitions
[0] = Definition(dst
);
3989 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3990 emit_split_vector(ctx
, dst
, num_components
);
3994 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3996 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3997 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3998 unsigned idx
= nir_intrinsic_base(instr
);
3999 unsigned component
= nir_intrinsic_component(instr
);
4000 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4002 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4004 assert(offset
->u32
== 0);
4006 /* the lower 15bit of the prim_mask contain the offset into LDS
4007 * while the upper bits contain the number of prims */
4008 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4009 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4010 Builder
bld(ctx
->program
, ctx
->block
);
4011 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4012 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4013 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4014 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4015 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4018 if (instr
->dest
.ssa
.num_components
== 1) {
4019 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4021 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4022 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4024 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4025 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4026 vec
->operands
[i
] = Operand(tmp
);
4028 vec
->definitions
[0] = Definition(dst
);
4029 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4033 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4034 unsigned offset
, unsigned stride
, unsigned channels
)
4036 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4037 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4039 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4040 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4043 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4044 unsigned offset
, unsigned stride
, unsigned *channels
)
4046 if (!vtx_info
->chan_byte_size
) {
4047 *channels
= vtx_info
->num_channels
;
4048 return vtx_info
->chan_format
;
4051 unsigned num_channels
= *channels
;
4052 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4053 unsigned new_channels
= num_channels
+ 1;
4054 /* first, assume more loads is worse and try using a larger data format */
4055 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4057 /* don't make the attribute potentially out-of-bounds */
4058 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4062 if (new_channels
== 5) {
4063 /* then try decreasing load size (at the cost of more loads) */
4064 new_channels
= *channels
;
4065 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4069 if (new_channels
< *channels
)
4070 *channels
= new_channels
;
4071 num_channels
= new_channels
;
4074 switch (vtx_info
->chan_format
) {
4075 case V_008F0C_BUF_DATA_FORMAT_8
:
4076 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4077 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4078 case V_008F0C_BUF_DATA_FORMAT_16
:
4079 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4080 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4081 case V_008F0C_BUF_DATA_FORMAT_32
:
4082 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4083 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4085 unreachable("shouldn't reach here");
4086 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4089 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4090 * so we may need to fix it up. */
4091 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4093 Builder
bld(ctx
->program
, ctx
->block
);
4095 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4096 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4098 /* For the integer-like cases, do a natural sign extension.
4100 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4101 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4104 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4105 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4107 /* Convert back to the right type. */
4108 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4109 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4110 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4111 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4112 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4113 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4119 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4121 Builder
bld(ctx
->program
, ctx
->block
);
4122 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4123 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4125 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4126 if (off_instr
->type
!= nir_instr_type_load_const
) {
4127 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4128 nir_print_instr(off_instr
, stderr
);
4129 fprintf(stderr
, "\n");
4131 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4133 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4135 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4136 unsigned component
= nir_intrinsic_component(instr
);
4137 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4138 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4139 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4140 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4142 unsigned dfmt
= attrib_format
& 0xf;
4143 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4144 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4146 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4147 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4148 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4149 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4151 num_channels
= MAX2(num_channels
, 3);
4153 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4154 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4157 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4158 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4159 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4161 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4163 Temp divided
= bld
.tmp(v1
);
4164 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4165 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4167 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4170 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4173 index
= bld
.vadd32(bld
.def(v1
),
4174 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4175 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4178 Temp channels
[num_channels
];
4179 unsigned channel_start
= 0;
4180 bool direct_fetch
= false;
4182 /* skip unused channels at the start */
4183 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4184 channel_start
= ffs(mask
) - 1;
4185 for (unsigned i
= 0; i
< channel_start
; i
++)
4186 channels
[i
] = Temp(0, s1
);
4187 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4188 num_channels
= 3 - (ffs(mask
) - 1);
4192 while (channel_start
< num_channels
) {
4193 unsigned fetch_size
= num_channels
- channel_start
;
4194 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4195 bool expanded
= false;
4197 /* use MUBUF when possible to avoid possible alignment issues */
4198 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4199 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4200 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4201 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4202 vtx_info
->chan_byte_size
== 4;
4203 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4205 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4207 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4208 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4214 Temp fetch_index
= index
;
4215 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4216 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4217 fetch_offset
= fetch_offset
% attrib_stride
;
4220 Operand
soffset(0u);
4221 if (fetch_offset
>= 4096) {
4222 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4223 fetch_offset
%= 4096;
4227 switch (fetch_size
) {
4229 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4232 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4235 assert(ctx
->options
->chip_class
>= GFX7
||
4236 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4237 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4240 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4243 unreachable("Unimplemented load_input vector size");
4247 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4248 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4249 num_channels
<= 3)) {
4250 direct_fetch
= true;
4253 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4257 Instruction
*mubuf
= bld
.mubuf(opcode
,
4258 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4259 fetch_offset
, false, true).instr
;
4260 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4262 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4263 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4264 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4265 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4268 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4270 if (fetch_size
== 1) {
4271 channels
[channel_start
] = fetch_dst
;
4273 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4274 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4277 channel_start
+= fetch_size
;
4280 if (!direct_fetch
) {
4281 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4282 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4284 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4285 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4286 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4288 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4289 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4290 unsigned num_temp
= 0;
4291 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4292 unsigned idx
= i
+ component
;
4293 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4294 Temp channel
= channels
[swizzle
[idx
]];
4295 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4296 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4297 vec
->operands
[i
] = Operand(channel
);
4301 } else if (is_float
&& idx
== 3) {
4302 vec
->operands
[i
] = Operand(0x3f800000u
);
4303 } else if (!is_float
&& idx
== 3) {
4304 vec
->operands
[i
] = Operand(1u);
4306 vec
->operands
[i
] = Operand(0u);
4309 vec
->definitions
[0] = Definition(dst
);
4310 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4311 emit_split_vector(ctx
, dst
, dst
.size());
4313 if (num_temp
== dst
.size())
4314 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4316 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4317 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4318 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4319 if (off_instr
->type
!= nir_instr_type_load_const
||
4320 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4321 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4322 nir_print_instr(off_instr
, stderr
);
4323 fprintf(stderr
, "\n");
4326 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4327 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4329 assert(offset
->u32
== 0);
4331 /* the lower 15bit of the prim_mask contain the offset into LDS
4332 * while the upper bits contain the number of prims */
4333 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4334 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4335 Builder
bld(ctx
->program
, ctx
->block
);
4336 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4337 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4338 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4339 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4340 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4343 unsigned idx
= nir_intrinsic_base(instr
);
4344 unsigned component
= nir_intrinsic_component(instr
);
4345 unsigned vertex_id
= 2; /* P0 */
4347 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4348 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4349 switch (src0
->u32
) {
4351 vertex_id
= 2; /* P0 */
4354 vertex_id
= 0; /* P10 */
4357 vertex_id
= 1; /* P20 */
4360 unreachable("invalid vertex index");
4364 if (dst
.size() == 1) {
4365 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4367 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4368 for (unsigned i
= 0; i
< dst
.size(); i
++)
4369 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4370 vec
->definitions
[0] = Definition(dst
);
4371 bld
.insert(std::move(vec
));
4374 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4375 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4376 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4377 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4378 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4380 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4382 unreachable("Shader stage not implemented");
4386 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4388 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4390 Builder
bld(ctx
->program
, ctx
->block
);
4391 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4394 if (!nir_src_is_const(*vertex_src
)) {
4395 /* better code could be created, but this case probably doesn't happen
4396 * much in practice */
4397 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4398 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4401 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4402 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4404 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4406 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4409 if (vertex_offset
.id()) {
4410 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4411 Operand(i
), indirect_vertex
);
4412 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4414 vertex_offset
= elem
;
4418 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4419 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4421 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4422 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4423 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4424 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4425 Operand((vertex
% 2u) * 16u), Operand(16u));
4427 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4430 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4431 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4432 return offset_mul(ctx
, offs
, 4u);
4435 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4437 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4439 Builder
bld(ctx
->program
, ctx
->block
);
4440 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4441 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4443 if (ctx
->stage
== geometry_gs
) {
4444 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4445 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4446 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4447 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4448 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4449 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4450 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4452 unreachable("Unsupported GS stage.");
4456 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4458 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4460 Builder
bld(ctx
->program
, ctx
->block
);
4461 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4463 if (load_input_from_temps(ctx
, instr
, dst
))
4466 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4467 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4468 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4470 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4473 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4475 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4477 Builder
bld(ctx
->program
, ctx
->block
);
4479 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4480 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4481 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4483 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4484 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4486 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4489 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4491 switch (ctx
->shader
->info
.stage
) {
4492 case MESA_SHADER_GEOMETRY
:
4493 visit_load_gs_per_vertex_input(ctx
, instr
);
4495 case MESA_SHADER_TESS_CTRL
:
4496 visit_load_tcs_per_vertex_input(ctx
, instr
);
4498 case MESA_SHADER_TESS_EVAL
:
4499 visit_load_tes_per_vertex_input(ctx
, instr
);
4502 unreachable("Unimplemented shader stage");
4506 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4508 visit_load_tcs_output(ctx
, instr
, true);
4511 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4513 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4514 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4516 visit_store_tcs_output(ctx
, instr
, true);
4519 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4521 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4523 Builder
bld(ctx
->program
, ctx
->block
);
4524 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4526 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4527 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4530 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4531 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4532 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4533 tes_w
= Operand(tmp
);
4536 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4537 emit_split_vector(ctx
, tess_coord
, 3);
4540 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4542 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4543 Builder
bld(ctx
->program
, ctx
->block
);
4544 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4545 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4546 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4549 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4553 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4555 Builder
bld(ctx
->program
, ctx
->block
);
4556 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4557 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4558 index
= bld
.as_uniform(index
);
4559 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4560 unsigned binding
= nir_intrinsic_binding(instr
);
4563 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4564 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4565 unsigned offset
= layout
->binding
[binding
].offset
;
4567 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4568 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4569 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4570 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4571 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4574 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4575 stride
= layout
->binding
[binding
].size
;
4578 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4579 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4581 if (nir_const_index
) {
4582 const_index
= const_index
* stride
;
4583 } else if (index
.type() == RegType::vgpr
) {
4584 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4585 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4587 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4591 if (nir_const_index
) {
4592 const_index
= const_index
+ offset
;
4593 } else if (index
.type() == RegType::vgpr
) {
4594 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4596 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4600 if (nir_const_index
&& const_index
== 0) {
4602 } else if (index
.type() == RegType::vgpr
) {
4603 index
= bld
.vadd32(bld
.def(v1
),
4604 nir_const_index
? Operand(const_index
) : Operand(index
),
4607 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4608 nir_const_index
? Operand(const_index
) : Operand(index
),
4612 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4615 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4616 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4617 bool glc
=false, bool readonly
=true)
4619 Builder
bld(ctx
->program
, ctx
->block
);
4620 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4621 unsigned num_bytes
= num_components
* component_size
;
4624 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4625 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4626 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4627 unsigned const_offset
= 0;
4629 /* for small bit sizes add buffer for unaligned loads */
4632 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4637 Temp lower
= Temp();
4638 if (num_bytes
> 16) {
4639 assert(num_components
== 3 || num_components
== 4);
4640 op
= aco_opcode::buffer_load_dwordx4
;
4641 lower
= bld
.tmp(v4
);
4642 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4643 mubuf
->definitions
[0] = Definition(lower
);
4644 mubuf
->operands
[0] = Operand(rsrc
);
4645 mubuf
->operands
[1] = vaddr
;
4646 mubuf
->operands
[2] = soffset
;
4647 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4650 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4651 mubuf
->can_reorder
= readonly
;
4652 bld
.insert(std::move(mubuf
));
4653 emit_split_vector(ctx
, lower
, 2);
4656 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4657 /* GFX6 doesn't support loading vec3, expand to vec4. */
4661 switch (num_bytes
) {
4663 op
= aco_opcode::buffer_load_ubyte
;
4666 op
= aco_opcode::buffer_load_ushort
;
4670 op
= aco_opcode::buffer_load_dword
;
4676 op
= aco_opcode::buffer_load_dwordx2
;
4680 assert(ctx
->options
->chip_class
> GFX6
);
4681 op
= aco_opcode::buffer_load_dwordx3
;
4684 op
= aco_opcode::buffer_load_dwordx4
;
4687 unreachable("Load SSBO not implemented for this size.");
4689 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4690 mubuf
->operands
[0] = Operand(rsrc
);
4691 mubuf
->operands
[1] = vaddr
;
4692 mubuf
->operands
[2] = soffset
;
4693 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4696 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4697 mubuf
->can_reorder
= readonly
;
4698 mubuf
->offset
= const_offset
;
4699 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4701 if (component_size
< 4) {
4702 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4703 instr
->definitions
[0] = Definition(vec
);
4704 bld
.insert(std::move(instr
));
4706 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4707 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4708 Temp tmp
[3] = {vec
, vec
, vec
};
4710 if (vec
.size() == 3) {
4711 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4712 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4713 } else if (vec
.size() == 2) {
4714 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4715 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4717 for (unsigned i
= 0; i
< dst
.size(); i
++)
4718 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4721 if (dst
.size() == 2)
4722 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4727 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4728 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4730 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4735 } else if (dst
.size() > 4) {
4736 assert(lower
!= Temp());
4737 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4738 instr
->definitions
[0] = Definition(upper
);
4739 bld
.insert(std::move(instr
));
4740 if (dst
.size() == 8)
4741 emit_split_vector(ctx
, upper
, 2);
4742 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4743 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4744 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4745 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4746 if (dst
.size() == 8)
4747 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4748 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4749 Temp vec
= bld
.tmp(v4
);
4750 instr
->definitions
[0] = Definition(vec
);
4751 bld
.insert(std::move(instr
));
4752 emit_split_vector(ctx
, vec
, 4);
4754 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4755 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4756 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4757 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4760 if (dst
.type() == RegType::sgpr
) {
4761 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4762 instr
->definitions
[0] = Definition(vec
);
4763 bld
.insert(std::move(instr
));
4764 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4766 instr
->definitions
[0] = Definition(dst
);
4767 bld
.insert(std::move(instr
));
4768 emit_split_vector(ctx
, dst
, num_components
);
4771 /* for small bit sizes add buffer for unaligned loads */
4773 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4775 switch (num_bytes
) {
4780 op
= aco_opcode::s_buffer_load_dword
;
4786 op
= aco_opcode::s_buffer_load_dwordx2
;
4791 op
= aco_opcode::s_buffer_load_dwordx4
;
4795 op
= aco_opcode::s_buffer_load_dwordx8
;
4798 unreachable("Load SSBO not implemented for this size.");
4800 offset
= bld
.as_uniform(offset
);
4801 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4802 load
->operands
[0] = Operand(rsrc
);
4803 load
->operands
[1] = Operand(offset
);
4804 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4805 load
->definitions
[0] = Definition(dst
);
4808 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4809 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4810 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4812 /* adjust misaligned small bit size loads */
4814 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
4815 load
->definitions
[0] = Definition(vec
);
4816 bld
.insert(std::move(load
));
4817 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
4818 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4821 } else if (dst
.size() == 3) {
4822 Temp vec
= bld
.tmp(s4
);
4823 load
->definitions
[0] = Definition(vec
);
4824 bld
.insert(std::move(load
));
4825 emit_split_vector(ctx
, vec
, 4);
4827 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4828 emit_extract_vector(ctx
, vec
, 0, s1
),
4829 emit_extract_vector(ctx
, vec
, 1, s1
),
4830 emit_extract_vector(ctx
, vec
, 2, s1
));
4831 } else if (dst
.size() == 6) {
4832 Temp vec
= bld
.tmp(s8
);
4833 load
->definitions
[0] = Definition(vec
);
4834 bld
.insert(std::move(load
));
4835 emit_split_vector(ctx
, vec
, 4);
4837 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4838 emit_extract_vector(ctx
, vec
, 0, s2
),
4839 emit_extract_vector(ctx
, vec
, 1, s2
),
4840 emit_extract_vector(ctx
, vec
, 2, s2
));
4842 bld
.insert(std::move(load
));
4844 emit_split_vector(ctx
, dst
, num_components
);
4848 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4850 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4851 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4853 Builder
bld(ctx
->program
, ctx
->block
);
4855 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4856 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4857 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4858 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4860 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4861 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4862 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4863 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4864 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4865 if (ctx
->options
->chip_class
>= GFX10
) {
4866 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4867 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4868 S_008F0C_RESOURCE_LEVEL(1);
4870 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4871 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4873 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4874 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4875 Operand(0xFFFFFFFFu
),
4876 Operand(desc_type
));
4877 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4878 rsrc
, upper_dwords
);
4880 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4881 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4883 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4886 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
4887 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
4888 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
4890 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
4893 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4895 Builder
bld(ctx
->program
, ctx
->block
);
4896 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4897 unsigned offset
= nir_intrinsic_base(instr
);
4898 unsigned count
= instr
->dest
.ssa
.num_components
;
4899 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4901 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4902 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4903 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4904 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4905 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4906 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4907 for (unsigned i
= 0; i
< count
; ++i
) {
4908 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4909 vec
->operands
[i
] = Operand
{elems
[i
]};
4911 vec
->definitions
[0] = Definition(dst
);
4912 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4913 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4918 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4919 if (offset
!= 0) // TODO check if index != 0 as well
4920 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4921 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4924 bool aligned
= true;
4926 if (instr
->dest
.ssa
.bit_size
== 8) {
4927 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4928 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4930 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4931 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4932 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4934 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4939 switch (vec
.size()) {
4941 op
= aco_opcode::s_load_dword
;
4944 op
= aco_opcode::s_load_dwordx2
;
4950 op
= aco_opcode::s_load_dwordx4
;
4956 op
= aco_opcode::s_load_dwordx8
;
4959 unreachable("unimplemented or forbidden load_push_constant.");
4962 bld
.smem(op
, Definition(vec
), ptr
, index
);
4965 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
4966 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4971 emit_split_vector(ctx
, vec
, 4);
4972 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
4973 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4974 emit_extract_vector(ctx
, vec
, 0, rc
),
4975 emit_extract_vector(ctx
, vec
, 1, rc
),
4976 emit_extract_vector(ctx
, vec
, 2, rc
));
4979 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4982 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4984 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4986 Builder
bld(ctx
->program
, ctx
->block
);
4988 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4989 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4990 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4991 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4992 if (ctx
->options
->chip_class
>= GFX10
) {
4993 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4994 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4995 S_008F0C_RESOURCE_LEVEL(1);
4997 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4998 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5001 unsigned base
= nir_intrinsic_base(instr
);
5002 unsigned range
= nir_intrinsic_range(instr
);
5004 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5005 if (base
&& offset
.type() == RegType::sgpr
)
5006 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5007 else if (base
&& offset
.type() == RegType::vgpr
)
5008 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5010 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5011 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5012 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5013 Operand(desc_type
));
5014 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5015 // TODO: get alignment information for subdword constants
5016 unsigned byte_align
= size
< 4 ? -1 : 0;
5017 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
5020 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5022 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5023 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5025 ctx
->program
->needs_exact
= true;
5027 // TODO: optimize uniform conditions
5028 Builder
bld(ctx
->program
, ctx
->block
);
5029 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5030 assert(src
.regClass() == bld
.lm
);
5031 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5032 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5033 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5037 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5039 Builder
bld(ctx
->program
, ctx
->block
);
5041 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5042 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5044 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5045 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5047 if (ctx
->block
->loop_nest_depth
&&
5048 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5049 /* we handle discards the same way as jump instructions */
5050 append_logical_end(ctx
->block
);
5052 /* in loops, discard behaves like break */
5053 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5054 ctx
->block
->kind
|= block_kind_discard
;
5057 /* uniform discard - loop ends here */
5058 assert(nir_instr_is_last(&instr
->instr
));
5059 ctx
->block
->kind
|= block_kind_uniform
;
5060 ctx
->cf_info
.has_branch
= true;
5061 bld
.branch(aco_opcode::p_branch
);
5062 add_linear_edge(ctx
->block
->index
, linear_target
);
5066 /* we add a break right behind the discard() instructions */
5067 ctx
->block
->kind
|= block_kind_break
;
5068 unsigned idx
= ctx
->block
->index
;
5070 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5071 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5073 /* remove critical edges from linear CFG */
5074 bld
.branch(aco_opcode::p_branch
);
5075 Block
* break_block
= ctx
->program
->create_and_insert_block();
5076 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5077 break_block
->kind
|= block_kind_uniform
;
5078 add_linear_edge(idx
, break_block
);
5079 add_linear_edge(break_block
->index
, linear_target
);
5080 bld
.reset(break_block
);
5081 bld
.branch(aco_opcode::p_branch
);
5083 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5084 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5085 add_linear_edge(idx
, continue_block
);
5086 append_logical_start(continue_block
);
5087 ctx
->block
= continue_block
;
5092 /* it can currently happen that NIR doesn't remove the unreachable code */
5093 if (!nir_instr_is_last(&instr
->instr
)) {
5094 ctx
->program
->needs_exact
= true;
5095 /* save exec somewhere temporarily so that it doesn't get
5096 * overwritten before the discard from outer exec masks */
5097 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5098 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5099 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5103 /* This condition is incorrect for uniformly branched discards in a loop
5104 * predicated by a divergent condition, but the above code catches that case
5105 * and the discard would end up turning into a discard_if.
5115 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5116 /* program just ends here */
5117 ctx
->block
->kind
|= block_kind_uniform
;
5118 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5119 0 /* enabled mask */, 9 /* dest */,
5120 false /* compressed */, true/* done */, true /* valid mask */);
5121 bld
.sopp(aco_opcode::s_endpgm
);
5122 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5124 ctx
->block
->kind
|= block_kind_discard
;
5125 /* branch and linear edge is added by visit_if() */
5129 enum aco_descriptor_type
{
5140 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5141 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5143 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5144 return dim
== ac_image_cube
||
5145 dim
== ac_image_1darray
||
5146 dim
== ac_image_2darray
||
5147 dim
== ac_image_2darraymsaa
;
5150 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5151 enum aco_descriptor_type desc_type
,
5152 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5154 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5155 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5156 if (it != ctx->tex_desc.end())
5159 Temp index
= Temp();
5160 bool index_set
= false;
5161 unsigned constant_index
= 0;
5162 unsigned descriptor_set
;
5163 unsigned base_index
;
5164 Builder
bld(ctx
->program
, ctx
->block
);
5167 assert(tex_instr
&& !image
);
5169 base_index
= tex_instr
->sampler_index
;
5171 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5172 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5176 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5177 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5179 constant_index
+= array_size
* const_value
->u32
;
5181 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5182 if (indirect
.type() == RegType::vgpr
)
5183 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5185 if (array_size
!= 1)
5186 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5192 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5196 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5198 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5199 base_index
= deref_instr
->var
->data
.binding
;
5202 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5203 list
= convert_pointer_to_64_bit(ctx
, list
);
5205 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5206 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5207 unsigned offset
= binding
->offset
;
5208 unsigned stride
= binding
->size
;
5212 assert(base_index
< layout
->binding_count
);
5214 switch (desc_type
) {
5215 case ACO_DESC_IMAGE
:
5217 opcode
= aco_opcode::s_load_dwordx8
;
5219 case ACO_DESC_FMASK
:
5221 opcode
= aco_opcode::s_load_dwordx8
;
5224 case ACO_DESC_SAMPLER
:
5226 opcode
= aco_opcode::s_load_dwordx4
;
5227 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5228 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5230 case ACO_DESC_BUFFER
:
5232 opcode
= aco_opcode::s_load_dwordx4
;
5234 case ACO_DESC_PLANE_0
:
5235 case ACO_DESC_PLANE_1
:
5237 opcode
= aco_opcode::s_load_dwordx8
;
5238 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5240 case ACO_DESC_PLANE_2
:
5242 opcode
= aco_opcode::s_load_dwordx4
;
5246 unreachable("invalid desc_type\n");
5249 offset
+= constant_index
* stride
;
5251 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5252 (!index_set
|| binding
->immutable_samplers_equal
)) {
5253 if (binding
->immutable_samplers_equal
)
5256 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5257 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5258 Operand(samplers
[constant_index
* 4 + 0]),
5259 Operand(samplers
[constant_index
* 4 + 1]),
5260 Operand(samplers
[constant_index
* 4 + 2]),
5261 Operand(samplers
[constant_index
* 4 + 3]));
5266 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5268 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5269 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5272 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5274 if (desc_type
== ACO_DESC_PLANE_2
) {
5276 for (unsigned i
= 0; i
< 8; i
++)
5277 components
[i
] = bld
.tmp(s1
);
5278 bld
.pseudo(aco_opcode::p_split_vector
,
5279 Definition(components
[0]),
5280 Definition(components
[1]),
5281 Definition(components
[2]),
5282 Definition(components
[3]),
5285 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5286 bld
.pseudo(aco_opcode::p_split_vector
,
5287 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5288 Definition(components
[4]),
5289 Definition(components
[5]),
5290 Definition(components
[6]),
5291 Definition(components
[7]),
5294 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5295 components
[0], components
[1], components
[2], components
[3],
5296 components
[4], components
[5], components
[6], components
[7]);
5302 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5305 case GLSL_SAMPLER_DIM_BUF
:
5307 case GLSL_SAMPLER_DIM_1D
:
5308 return array
? 2 : 1;
5309 case GLSL_SAMPLER_DIM_2D
:
5310 return array
? 3 : 2;
5311 case GLSL_SAMPLER_DIM_MS
:
5312 return array
? 4 : 3;
5313 case GLSL_SAMPLER_DIM_3D
:
5314 case GLSL_SAMPLER_DIM_CUBE
:
5316 case GLSL_SAMPLER_DIM_RECT
:
5317 case GLSL_SAMPLER_DIM_SUBPASS
:
5319 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5328 /* Adjust the sample index according to FMASK.
5330 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5331 * which is the identity mapping. Each nibble says which physical sample
5332 * should be fetched to get that sample.
5334 * For example, 0x11111100 means there are only 2 samples stored and
5335 * the second sample covers 3/4 of the pixel. When reading samples 0
5336 * and 1, return physical sample 0 (determined by the first two 0s
5337 * in FMASK), otherwise return physical sample 1.
5339 * The sample index should be adjusted as follows:
5340 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5342 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5344 Builder
bld(ctx
->program
, ctx
->block
);
5345 Temp fmask
= bld
.tmp(v1
);
5346 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5347 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5350 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5351 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5352 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5353 load
->operands
[0] = Operand(fmask_desc_ptr
);
5354 load
->operands
[1] = Operand(s4
); /* no sampler */
5355 load
->operands
[2] = Operand(coord
);
5356 load
->definitions
[0] = Definition(fmask
);
5363 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5364 ctx
->block
->instructions
.emplace_back(std::move(load
));
5366 Operand sample_index4
;
5367 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5368 sample_index4
= Operand(sample_index
.constantValue() << 2);
5369 } else if (sample_index
.regClass() == s1
) {
5370 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5372 assert(sample_index
.regClass() == v1
);
5373 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5377 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5378 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5379 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5380 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5382 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5384 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5385 * resource descriptor is 0 (invalid),
5387 Temp compare
= bld
.tmp(bld
.lm
);
5388 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5389 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5391 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5393 /* Replace the MSAA sample index. */
5394 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5397 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5400 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5401 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5402 bool is_array
= glsl_sampler_type_is_array(type
);
5403 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5404 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5405 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5406 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5407 int count
= image_type_to_components_count(dim
, is_array
);
5408 std::vector
<Temp
> coords(count
);
5409 Builder
bld(ctx
->program
, ctx
->block
);
5413 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5414 /* get sample index */
5415 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5416 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5417 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5418 std::vector
<Temp
> fmask_load_address
;
5419 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5420 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5422 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5423 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5425 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5430 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5431 coords
.resize(coords
.size() + 1);
5432 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5434 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5436 for (int i
= 0; i
< count
; i
++)
5437 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5440 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5441 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5442 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5443 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5446 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5449 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5450 for (unsigned i
= 0; i
< coords
.size(); i
++)
5451 vec
->operands
[i
] = Operand(coords
[i
]);
5452 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5453 vec
->definitions
[0] = Definition(res
);
5454 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5459 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5461 Builder
bld(ctx
->program
, ctx
->block
);
5462 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5463 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5464 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5465 bool is_array
= glsl_sampler_type_is_array(type
);
5466 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5468 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5469 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5470 unsigned num_channels
= util_last_bit(mask
);
5471 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5472 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5475 switch (num_channels
) {
5477 opcode
= aco_opcode::buffer_load_format_x
;
5480 opcode
= aco_opcode::buffer_load_format_xy
;
5483 opcode
= aco_opcode::buffer_load_format_xyz
;
5486 opcode
= aco_opcode::buffer_load_format_xyzw
;
5489 unreachable(">4 channel buffer image load");
5491 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5492 load
->operands
[0] = Operand(rsrc
);
5493 load
->operands
[1] = Operand(vindex
);
5494 load
->operands
[2] = Operand((uint32_t) 0);
5496 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5499 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5500 load
->definitions
[0] = Definition(tmp
);
5502 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5503 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5504 load
->barrier
= barrier_image
;
5505 ctx
->block
->instructions
.emplace_back(std::move(load
));
5507 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5511 Temp coords
= get_image_coords(ctx
, instr
, type
);
5512 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5514 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5515 unsigned num_components
= util_bitcount(dmask
);
5517 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5520 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5522 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5523 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5525 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5526 load
->operands
[0] = Operand(resource
);
5527 load
->operands
[1] = Operand(s4
); /* no sampler */
5528 load
->operands
[2] = Operand(coords
);
5529 load
->definitions
[0] = Definition(tmp
);
5530 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5531 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5532 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5533 load
->dmask
= dmask
;
5535 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5536 load
->barrier
= barrier_image
;
5537 ctx
->block
->instructions
.emplace_back(std::move(load
));
5539 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5543 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5545 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5546 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5547 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5548 bool is_array
= glsl_sampler_type_is_array(type
);
5549 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5551 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5553 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5554 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5555 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5557 switch (data
.size()) {
5559 opcode
= aco_opcode::buffer_store_format_x
;
5562 opcode
= aco_opcode::buffer_store_format_xy
;
5565 opcode
= aco_opcode::buffer_store_format_xyz
;
5568 opcode
= aco_opcode::buffer_store_format_xyzw
;
5571 unreachable(">4 channel buffer image store");
5573 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5574 store
->operands
[0] = Operand(rsrc
);
5575 store
->operands
[1] = Operand(vindex
);
5576 store
->operands
[2] = Operand((uint32_t) 0);
5577 store
->operands
[3] = Operand(data
);
5578 store
->idxen
= true;
5581 store
->disable_wqm
= true;
5582 store
->barrier
= barrier_image
;
5583 ctx
->program
->needs_exact
= true;
5584 ctx
->block
->instructions
.emplace_back(std::move(store
));
5588 assert(data
.type() == RegType::vgpr
);
5589 Temp coords
= get_image_coords(ctx
, instr
, type
);
5590 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5592 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5593 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5595 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5596 store
->operands
[0] = Operand(resource
);
5597 store
->operands
[1] = Operand(data
);
5598 store
->operands
[2] = Operand(coords
);
5601 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5602 store
->dmask
= (1 << data
.size()) - 1;
5604 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5605 store
->disable_wqm
= true;
5606 store
->barrier
= barrier_image
;
5607 ctx
->program
->needs_exact
= true;
5608 ctx
->block
->instructions
.emplace_back(std::move(store
));
5612 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5614 /* return the previous value if dest is ever used */
5615 bool return_previous
= false;
5616 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5617 return_previous
= true;
5620 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5621 return_previous
= true;
5625 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5626 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5627 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5628 bool is_array
= glsl_sampler_type_is_array(type
);
5629 Builder
bld(ctx
->program
, ctx
->block
);
5631 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5632 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5634 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5635 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5637 aco_opcode buf_op
, image_op
;
5638 switch (instr
->intrinsic
) {
5639 case nir_intrinsic_image_deref_atomic_add
:
5640 buf_op
= aco_opcode::buffer_atomic_add
;
5641 image_op
= aco_opcode::image_atomic_add
;
5643 case nir_intrinsic_image_deref_atomic_umin
:
5644 buf_op
= aco_opcode::buffer_atomic_umin
;
5645 image_op
= aco_opcode::image_atomic_umin
;
5647 case nir_intrinsic_image_deref_atomic_imin
:
5648 buf_op
= aco_opcode::buffer_atomic_smin
;
5649 image_op
= aco_opcode::image_atomic_smin
;
5651 case nir_intrinsic_image_deref_atomic_umax
:
5652 buf_op
= aco_opcode::buffer_atomic_umax
;
5653 image_op
= aco_opcode::image_atomic_umax
;
5655 case nir_intrinsic_image_deref_atomic_imax
:
5656 buf_op
= aco_opcode::buffer_atomic_smax
;
5657 image_op
= aco_opcode::image_atomic_smax
;
5659 case nir_intrinsic_image_deref_atomic_and
:
5660 buf_op
= aco_opcode::buffer_atomic_and
;
5661 image_op
= aco_opcode::image_atomic_and
;
5663 case nir_intrinsic_image_deref_atomic_or
:
5664 buf_op
= aco_opcode::buffer_atomic_or
;
5665 image_op
= aco_opcode::image_atomic_or
;
5667 case nir_intrinsic_image_deref_atomic_xor
:
5668 buf_op
= aco_opcode::buffer_atomic_xor
;
5669 image_op
= aco_opcode::image_atomic_xor
;
5671 case nir_intrinsic_image_deref_atomic_exchange
:
5672 buf_op
= aco_opcode::buffer_atomic_swap
;
5673 image_op
= aco_opcode::image_atomic_swap
;
5675 case nir_intrinsic_image_deref_atomic_comp_swap
:
5676 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5677 image_op
= aco_opcode::image_atomic_cmpswap
;
5680 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5683 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5685 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5686 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5687 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5688 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5689 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5690 mubuf
->operands
[0] = Operand(resource
);
5691 mubuf
->operands
[1] = Operand(vindex
);
5692 mubuf
->operands
[2] = Operand((uint32_t)0);
5693 mubuf
->operands
[3] = Operand(data
);
5694 if (return_previous
)
5695 mubuf
->definitions
[0] = Definition(dst
);
5697 mubuf
->idxen
= true;
5698 mubuf
->glc
= return_previous
;
5699 mubuf
->dlc
= false; /* Not needed for atomics */
5700 mubuf
->disable_wqm
= true;
5701 mubuf
->barrier
= barrier_image
;
5702 ctx
->program
->needs_exact
= true;
5703 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5707 Temp coords
= get_image_coords(ctx
, instr
, type
);
5708 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5709 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5710 mimg
->operands
[0] = Operand(resource
);
5711 mimg
->operands
[1] = Operand(data
);
5712 mimg
->operands
[2] = Operand(coords
);
5713 if (return_previous
)
5714 mimg
->definitions
[0] = Definition(dst
);
5715 mimg
->glc
= return_previous
;
5716 mimg
->dlc
= false; /* Not needed for atomics */
5717 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5718 mimg
->dmask
= (1 << data
.size()) - 1;
5720 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5721 mimg
->disable_wqm
= true;
5722 mimg
->barrier
= barrier_image
;
5723 ctx
->program
->needs_exact
= true;
5724 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5728 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5730 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5731 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5732 Builder
bld(ctx
->program
, ctx
->block
);
5734 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5736 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5737 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5739 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5740 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5742 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5743 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5745 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5746 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5747 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5748 if (dst
.type() == RegType::vgpr
)
5749 bld
.copy(Definition(dst
), shr_dst
);
5751 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5753 emit_extract_vector(ctx
, desc
, 2, dst
);
5757 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5759 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5760 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5761 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5762 bool is_array
= glsl_sampler_type_is_array(type
);
5763 Builder
bld(ctx
->program
, ctx
->block
);
5765 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5766 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5767 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5771 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5774 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5776 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5778 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5779 mimg
->operands
[0] = Operand(resource
);
5780 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5781 mimg
->operands
[2] = Operand(lod
);
5782 uint8_t& dmask
= mimg
->dmask
;
5783 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5784 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5785 mimg
->da
= glsl_sampler_type_is_array(type
);
5786 mimg
->can_reorder
= true;
5787 Definition
& def
= mimg
->definitions
[0];
5788 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5790 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5791 glsl_sampler_type_is_array(type
)) {
5793 assert(instr
->dest
.ssa
.num_components
== 3);
5794 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5795 def
= Definition(tmp
);
5796 emit_split_vector(ctx
, tmp
, 3);
5798 /* divide 3rd value by 6 by multiplying with magic number */
5799 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5800 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5802 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5803 emit_extract_vector(ctx
, tmp
, 0, v1
),
5804 emit_extract_vector(ctx
, tmp
, 1, v1
),
5807 } else if (ctx
->options
->chip_class
== GFX9
&&
5808 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5809 glsl_sampler_type_is_array(type
)) {
5810 assert(instr
->dest
.ssa
.num_components
== 2);
5811 def
= Definition(dst
);
5814 def
= Definition(dst
);
5817 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5820 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5822 Builder
bld(ctx
->program
, ctx
->block
);
5823 unsigned num_components
= instr
->num_components
;
5825 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5826 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5827 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5829 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5830 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5833 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5834 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5835 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5837 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
5840 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5842 Builder
bld(ctx
->program
, ctx
->block
);
5843 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5844 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5845 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5846 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5848 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5849 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5851 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5852 ctx
->options
->chip_class
>= GFX8
&&
5853 elem_size_bytes
>= 4;
5855 offset
= bld
.as_uniform(offset
);
5856 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5860 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5861 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5862 /* GFX6 doesn't support storing vec3, split it. */
5863 writemask
|= 1u << (start
+ 2);
5866 int num_bytes
= count
* elem_size_bytes
;
5868 /* dword or larger stores have to be dword-aligned */
5869 if (elem_size_bytes
< 4 && num_bytes
> 2) {
5870 // TODO: improve alignment check of sub-dword stores
5871 unsigned count_new
= 2 / elem_size_bytes
;
5872 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
5877 if (num_bytes
> 16) {
5878 assert(elem_size_bytes
== 8);
5879 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5885 if (elem_size_bytes
< 4) {
5886 if (data
.type() == RegType::sgpr
) {
5887 data
= as_vgpr(ctx
, data
);
5888 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
5890 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
5891 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5892 for (int i
= 0; i
< count
; i
++)
5893 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
5894 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
5895 vec
->definitions
[0] = Definition(write_data
);
5896 bld
.insert(std::move(vec
));
5897 } else if (count
!= instr
->num_components
) {
5898 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5899 for (int i
= 0; i
< count
; i
++) {
5900 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5901 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5903 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5904 vec
->definitions
[0] = Definition(write_data
);
5905 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5906 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5907 assert(num_bytes
% 4 == 0);
5908 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5909 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5910 assert(num_bytes
% 4 == 0);
5911 write_data
= bld
.as_uniform(data
);
5916 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
5917 switch (num_bytes
) {
5919 vmem_op
= aco_opcode::buffer_store_byte
;
5922 vmem_op
= aco_opcode::buffer_store_short
;
5925 vmem_op
= aco_opcode::buffer_store_dword
;
5926 smem_op
= aco_opcode::s_buffer_store_dword
;
5929 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5930 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5933 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5934 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5937 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5938 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5941 unreachable("Store SSBO not implemented for this size.");
5943 if (ctx
->stage
== fragment_fs
)
5944 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5947 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5948 store
->operands
[0] = Operand(rsrc
);
5950 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5951 offset
, Operand(start
* elem_size_bytes
));
5952 store
->operands
[1] = Operand(off
);
5954 store
->operands
[1] = Operand(offset
);
5956 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5957 store
->operands
[1].setFixed(m0
);
5958 store
->operands
[2] = Operand(write_data
);
5959 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5961 store
->disable_wqm
= true;
5962 store
->barrier
= barrier_buffer
;
5963 ctx
->block
->instructions
.emplace_back(std::move(store
));
5964 ctx
->program
->wb_smem_l1_on_end
= true;
5965 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5966 ctx
->block
->kind
|= block_kind_needs_lowering
;
5967 ctx
->program
->needs_exact
= true;
5970 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
5971 store
->operands
[0] = Operand(rsrc
);
5972 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5973 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5974 store
->operands
[3] = Operand(write_data
);
5975 store
->offset
= start
* elem_size_bytes
;
5976 store
->offen
= (offset
.type() == RegType::vgpr
);
5977 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5979 store
->disable_wqm
= true;
5980 store
->barrier
= barrier_buffer
;
5981 ctx
->program
->needs_exact
= true;
5982 ctx
->block
->instructions
.emplace_back(std::move(store
));
5987 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5989 /* return the previous value if dest is ever used */
5990 bool return_previous
= false;
5991 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5992 return_previous
= true;
5995 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5996 return_previous
= true;
6000 Builder
bld(ctx
->program
, ctx
->block
);
6001 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6003 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6004 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6005 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6007 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6008 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6009 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6011 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6013 aco_opcode op32
, op64
;
6014 switch (instr
->intrinsic
) {
6015 case nir_intrinsic_ssbo_atomic_add
:
6016 op32
= aco_opcode::buffer_atomic_add
;
6017 op64
= aco_opcode::buffer_atomic_add_x2
;
6019 case nir_intrinsic_ssbo_atomic_imin
:
6020 op32
= aco_opcode::buffer_atomic_smin
;
6021 op64
= aco_opcode::buffer_atomic_smin_x2
;
6023 case nir_intrinsic_ssbo_atomic_umin
:
6024 op32
= aco_opcode::buffer_atomic_umin
;
6025 op64
= aco_opcode::buffer_atomic_umin_x2
;
6027 case nir_intrinsic_ssbo_atomic_imax
:
6028 op32
= aco_opcode::buffer_atomic_smax
;
6029 op64
= aco_opcode::buffer_atomic_smax_x2
;
6031 case nir_intrinsic_ssbo_atomic_umax
:
6032 op32
= aco_opcode::buffer_atomic_umax
;
6033 op64
= aco_opcode::buffer_atomic_umax_x2
;
6035 case nir_intrinsic_ssbo_atomic_and
:
6036 op32
= aco_opcode::buffer_atomic_and
;
6037 op64
= aco_opcode::buffer_atomic_and_x2
;
6039 case nir_intrinsic_ssbo_atomic_or
:
6040 op32
= aco_opcode::buffer_atomic_or
;
6041 op64
= aco_opcode::buffer_atomic_or_x2
;
6043 case nir_intrinsic_ssbo_atomic_xor
:
6044 op32
= aco_opcode::buffer_atomic_xor
;
6045 op64
= aco_opcode::buffer_atomic_xor_x2
;
6047 case nir_intrinsic_ssbo_atomic_exchange
:
6048 op32
= aco_opcode::buffer_atomic_swap
;
6049 op64
= aco_opcode::buffer_atomic_swap_x2
;
6051 case nir_intrinsic_ssbo_atomic_comp_swap
:
6052 op32
= aco_opcode::buffer_atomic_cmpswap
;
6053 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6056 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6058 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6059 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6060 mubuf
->operands
[0] = Operand(rsrc
);
6061 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6062 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6063 mubuf
->operands
[3] = Operand(data
);
6064 if (return_previous
)
6065 mubuf
->definitions
[0] = Definition(dst
);
6067 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6068 mubuf
->glc
= return_previous
;
6069 mubuf
->dlc
= false; /* Not needed for atomics */
6070 mubuf
->disable_wqm
= true;
6071 mubuf
->barrier
= barrier_buffer
;
6072 ctx
->program
->needs_exact
= true;
6073 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6076 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6078 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6079 Builder
bld(ctx
->program
, ctx
->block
);
6080 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6081 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6084 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
6086 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6087 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6089 if (addr
.type() == RegType::vgpr
)
6090 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
6091 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
6094 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6096 Builder
bld(ctx
->program
, ctx
->block
);
6097 unsigned num_components
= instr
->num_components
;
6098 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
6100 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6101 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6103 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6104 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
6106 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
6107 bool global
= ctx
->options
->chip_class
>= GFX9
;
6109 if (ctx
->options
->chip_class
>= GFX7
) {
6111 switch (num_bytes
) {
6113 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
6116 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
6119 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
6122 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
6125 unreachable("load_global not implemented for this size.");
6128 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
6129 flat
->operands
[0] = Operand(addr
);
6130 flat
->operands
[1] = Operand(s1
);
6133 flat
->barrier
= barrier_buffer
;
6135 if (dst
.type() == RegType::sgpr
) {
6136 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6137 flat
->definitions
[0] = Definition(vec
);
6138 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6139 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6141 flat
->definitions
[0] = Definition(dst
);
6142 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6144 emit_split_vector(ctx
, dst
, num_components
);
6146 assert(ctx
->options
->chip_class
== GFX6
);
6148 /* GFX6 doesn't support loading vec3, expand to vec4. */
6149 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6152 switch (num_bytes
) {
6154 op
= aco_opcode::buffer_load_dword
;
6157 op
= aco_opcode::buffer_load_dwordx2
;
6160 op
= aco_opcode::buffer_load_dwordx4
;
6163 unreachable("load_global not implemented for this size.");
6166 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6168 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6169 mubuf
->operands
[0] = Operand(rsrc
);
6170 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6171 mubuf
->operands
[2] = Operand(0u);
6175 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6176 mubuf
->disable_wqm
= false;
6177 mubuf
->barrier
= barrier_buffer
;
6178 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6181 if (dst
.size() == 3) {
6182 Temp vec
= bld
.tmp(v4
);
6183 instr
->definitions
[0] = Definition(vec
);
6184 bld
.insert(std::move(instr
));
6185 emit_split_vector(ctx
, vec
, 4);
6187 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6188 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6189 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6190 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6193 if (dst
.type() == RegType::sgpr
) {
6194 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6195 instr
->definitions
[0] = Definition(vec
);
6196 bld
.insert(std::move(instr
));
6197 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6198 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6200 instr
->definitions
[0] = Definition(dst
);
6201 bld
.insert(std::move(instr
));
6202 emit_split_vector(ctx
, dst
, num_components
);
6206 switch (num_bytes
) {
6208 op
= aco_opcode::s_load_dword
;
6211 op
= aco_opcode::s_load_dwordx2
;
6215 op
= aco_opcode::s_load_dwordx4
;
6218 unreachable("load_global not implemented for this size.");
6220 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6221 load
->operands
[0] = Operand(addr
);
6222 load
->operands
[1] = Operand(0u);
6223 load
->definitions
[0] = Definition(dst
);
6226 load
->barrier
= barrier_buffer
;
6227 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6229 if (dst
.size() == 3) {
6231 Temp vec
= bld
.tmp(s4
);
6232 load
->definitions
[0] = Definition(vec
);
6233 ctx
->block
->instructions
.emplace_back(std::move(load
));
6234 emit_split_vector(ctx
, vec
, 4);
6236 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6237 emit_extract_vector(ctx
, vec
, 0, s1
),
6238 emit_extract_vector(ctx
, vec
, 1, s1
),
6239 emit_extract_vector(ctx
, vec
, 2, s1
));
6241 ctx
->block
->instructions
.emplace_back(std::move(load
));
6246 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6248 Builder
bld(ctx
->program
, ctx
->block
);
6249 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6251 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6252 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6254 if (ctx
->options
->chip_class
>= GFX7
)
6255 addr
= as_vgpr(ctx
, addr
);
6257 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6260 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6261 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6262 /* GFX6 doesn't support storing vec3, split it. */
6263 writemask
|= 1u << (start
+ 2);
6266 unsigned num_bytes
= count
* elem_size_bytes
;
6268 Temp write_data
= data
;
6269 if (count
!= instr
->num_components
) {
6270 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6271 for (int i
= 0; i
< count
; i
++)
6272 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6273 write_data
= bld
.tmp(RegType::vgpr
, count
);
6274 vec
->definitions
[0] = Definition(write_data
);
6275 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6278 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6279 unsigned offset
= start
* elem_size_bytes
;
6281 if (ctx
->options
->chip_class
>= GFX7
) {
6282 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6283 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6284 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6285 Temp carry
= bld
.tmp(bld
.lm
);
6286 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6288 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6289 Operand(offset
), addr0
);
6290 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6292 carry
).def(1).setHint(vcc
);
6294 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6299 bool global
= ctx
->options
->chip_class
>= GFX9
;
6301 switch (num_bytes
) {
6303 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6306 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6309 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6312 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6315 unreachable("store_global not implemented for this size.");
6318 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6319 flat
->operands
[0] = Operand(addr
);
6320 flat
->operands
[1] = Operand(s1
);
6321 flat
->operands
[2] = Operand(data
);
6324 flat
->offset
= offset
;
6325 flat
->disable_wqm
= true;
6326 flat
->barrier
= barrier_buffer
;
6327 ctx
->program
->needs_exact
= true;
6328 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6330 assert(ctx
->options
->chip_class
== GFX6
);
6333 switch (num_bytes
) {
6335 op
= aco_opcode::buffer_store_dword
;
6338 op
= aco_opcode::buffer_store_dwordx2
;
6341 op
= aco_opcode::buffer_store_dwordx4
;
6344 unreachable("store_global not implemented for this size.");
6347 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6349 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6350 mubuf
->operands
[0] = Operand(rsrc
);
6351 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6352 mubuf
->operands
[2] = Operand(0u);
6353 mubuf
->operands
[3] = Operand(write_data
);
6356 mubuf
->offset
= offset
;
6357 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6358 mubuf
->disable_wqm
= true;
6359 mubuf
->barrier
= barrier_buffer
;
6360 ctx
->program
->needs_exact
= true;
6361 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6366 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6368 /* return the previous value if dest is ever used */
6369 bool return_previous
= false;
6370 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6371 return_previous
= true;
6374 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6375 return_previous
= true;
6379 Builder
bld(ctx
->program
, ctx
->block
);
6380 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6381 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6383 if (ctx
->options
->chip_class
>= GFX7
)
6384 addr
= as_vgpr(ctx
, addr
);
6386 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6387 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6388 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6390 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6392 aco_opcode op32
, op64
;
6394 if (ctx
->options
->chip_class
>= GFX7
) {
6395 bool global
= ctx
->options
->chip_class
>= GFX9
;
6396 switch (instr
->intrinsic
) {
6397 case nir_intrinsic_global_atomic_add
:
6398 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6399 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6401 case nir_intrinsic_global_atomic_imin
:
6402 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6403 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6405 case nir_intrinsic_global_atomic_umin
:
6406 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6407 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6409 case nir_intrinsic_global_atomic_imax
:
6410 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6411 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6413 case nir_intrinsic_global_atomic_umax
:
6414 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6415 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6417 case nir_intrinsic_global_atomic_and
:
6418 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6419 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6421 case nir_intrinsic_global_atomic_or
:
6422 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6423 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6425 case nir_intrinsic_global_atomic_xor
:
6426 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6427 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6429 case nir_intrinsic_global_atomic_exchange
:
6430 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6431 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6433 case nir_intrinsic_global_atomic_comp_swap
:
6434 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6435 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6438 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6441 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6442 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6443 flat
->operands
[0] = Operand(addr
);
6444 flat
->operands
[1] = Operand(s1
);
6445 flat
->operands
[2] = Operand(data
);
6446 if (return_previous
)
6447 flat
->definitions
[0] = Definition(dst
);
6448 flat
->glc
= return_previous
;
6449 flat
->dlc
= false; /* Not needed for atomics */
6451 flat
->disable_wqm
= true;
6452 flat
->barrier
= barrier_buffer
;
6453 ctx
->program
->needs_exact
= true;
6454 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6456 assert(ctx
->options
->chip_class
== GFX6
);
6458 switch (instr
->intrinsic
) {
6459 case nir_intrinsic_global_atomic_add
:
6460 op32
= aco_opcode::buffer_atomic_add
;
6461 op64
= aco_opcode::buffer_atomic_add_x2
;
6463 case nir_intrinsic_global_atomic_imin
:
6464 op32
= aco_opcode::buffer_atomic_smin
;
6465 op64
= aco_opcode::buffer_atomic_smin_x2
;
6467 case nir_intrinsic_global_atomic_umin
:
6468 op32
= aco_opcode::buffer_atomic_umin
;
6469 op64
= aco_opcode::buffer_atomic_umin_x2
;
6471 case nir_intrinsic_global_atomic_imax
:
6472 op32
= aco_opcode::buffer_atomic_smax
;
6473 op64
= aco_opcode::buffer_atomic_smax_x2
;
6475 case nir_intrinsic_global_atomic_umax
:
6476 op32
= aco_opcode::buffer_atomic_umax
;
6477 op64
= aco_opcode::buffer_atomic_umax_x2
;
6479 case nir_intrinsic_global_atomic_and
:
6480 op32
= aco_opcode::buffer_atomic_and
;
6481 op64
= aco_opcode::buffer_atomic_and_x2
;
6483 case nir_intrinsic_global_atomic_or
:
6484 op32
= aco_opcode::buffer_atomic_or
;
6485 op64
= aco_opcode::buffer_atomic_or_x2
;
6487 case nir_intrinsic_global_atomic_xor
:
6488 op32
= aco_opcode::buffer_atomic_xor
;
6489 op64
= aco_opcode::buffer_atomic_xor_x2
;
6491 case nir_intrinsic_global_atomic_exchange
:
6492 op32
= aco_opcode::buffer_atomic_swap
;
6493 op64
= aco_opcode::buffer_atomic_swap_x2
;
6495 case nir_intrinsic_global_atomic_comp_swap
:
6496 op32
= aco_opcode::buffer_atomic_cmpswap
;
6497 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6500 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6503 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6505 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6507 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6508 mubuf
->operands
[0] = Operand(rsrc
);
6509 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6510 mubuf
->operands
[2] = Operand(0u);
6511 mubuf
->operands
[3] = Operand(data
);
6512 if (return_previous
)
6513 mubuf
->definitions
[0] = Definition(dst
);
6514 mubuf
->glc
= return_previous
;
6517 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6518 mubuf
->disable_wqm
= true;
6519 mubuf
->barrier
= barrier_buffer
;
6520 ctx
->program
->needs_exact
= true;
6521 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6525 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6526 Builder
bld(ctx
->program
, ctx
->block
);
6527 switch(instr
->intrinsic
) {
6528 case nir_intrinsic_group_memory_barrier
:
6529 case nir_intrinsic_memory_barrier
:
6530 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6532 case nir_intrinsic_memory_barrier_buffer
:
6533 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6535 case nir_intrinsic_memory_barrier_image
:
6536 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6538 case nir_intrinsic_memory_barrier_tcs_patch
:
6539 case nir_intrinsic_memory_barrier_shared
:
6540 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6543 unreachable("Unimplemented memory barrier intrinsic");
6548 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6550 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6551 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6552 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6553 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6554 Builder
bld(ctx
->program
, ctx
->block
);
6556 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6557 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6558 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6561 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6563 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6564 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6565 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6566 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6567 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6569 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6570 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6573 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6575 unsigned offset
= nir_intrinsic_base(instr
);
6576 Operand m
= load_lds_size_m0(ctx
);
6577 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6578 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6580 unsigned num_operands
= 3;
6581 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6582 switch(instr
->intrinsic
) {
6583 case nir_intrinsic_shared_atomic_add
:
6584 op32
= aco_opcode::ds_add_u32
;
6585 op64
= aco_opcode::ds_add_u64
;
6586 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6587 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6589 case nir_intrinsic_shared_atomic_imin
:
6590 op32
= aco_opcode::ds_min_i32
;
6591 op64
= aco_opcode::ds_min_i64
;
6592 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6593 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6595 case nir_intrinsic_shared_atomic_umin
:
6596 op32
= aco_opcode::ds_min_u32
;
6597 op64
= aco_opcode::ds_min_u64
;
6598 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6599 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6601 case nir_intrinsic_shared_atomic_imax
:
6602 op32
= aco_opcode::ds_max_i32
;
6603 op64
= aco_opcode::ds_max_i64
;
6604 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6605 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6607 case nir_intrinsic_shared_atomic_umax
:
6608 op32
= aco_opcode::ds_max_u32
;
6609 op64
= aco_opcode::ds_max_u64
;
6610 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6611 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6613 case nir_intrinsic_shared_atomic_and
:
6614 op32
= aco_opcode::ds_and_b32
;
6615 op64
= aco_opcode::ds_and_b64
;
6616 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6617 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6619 case nir_intrinsic_shared_atomic_or
:
6620 op32
= aco_opcode::ds_or_b32
;
6621 op64
= aco_opcode::ds_or_b64
;
6622 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6623 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6625 case nir_intrinsic_shared_atomic_xor
:
6626 op32
= aco_opcode::ds_xor_b32
;
6627 op64
= aco_opcode::ds_xor_b64
;
6628 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6629 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6631 case nir_intrinsic_shared_atomic_exchange
:
6632 op32
= aco_opcode::ds_write_b32
;
6633 op64
= aco_opcode::ds_write_b64
;
6634 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6635 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6637 case nir_intrinsic_shared_atomic_comp_swap
:
6638 op32
= aco_opcode::ds_cmpst_b32
;
6639 op64
= aco_opcode::ds_cmpst_b64
;
6640 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6641 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6645 unreachable("Unhandled shared atomic intrinsic");
6648 /* return the previous value if dest is ever used */
6649 bool return_previous
= false;
6650 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6651 return_previous
= true;
6654 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6655 return_previous
= true;
6660 if (data
.size() == 1) {
6661 assert(instr
->dest
.ssa
.bit_size
== 32);
6662 op
= return_previous
? op32_rtn
: op32
;
6664 assert(instr
->dest
.ssa
.bit_size
== 64);
6665 op
= return_previous
? op64_rtn
: op64
;
6668 if (offset
> 65535) {
6669 Builder
bld(ctx
->program
, ctx
->block
);
6670 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6674 aco_ptr
<DS_instruction
> ds
;
6675 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6676 ds
->operands
[0] = Operand(address
);
6677 ds
->operands
[1] = Operand(data
);
6678 if (num_operands
== 4)
6679 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6680 ds
->operands
[num_operands
- 1] = m
;
6681 ds
->offset0
= offset
;
6682 if (return_previous
)
6683 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6684 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6687 Temp
get_scratch_resource(isel_context
*ctx
)
6689 Builder
bld(ctx
->program
, ctx
->block
);
6690 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6691 if (ctx
->stage
!= compute_cs
)
6692 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6694 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6695 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6697 if (ctx
->program
->chip_class
>= GFX10
) {
6698 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6699 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6700 S_008F0C_RESOURCE_LEVEL(1);
6701 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6702 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6703 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6706 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6707 if (ctx
->program
->chip_class
<= GFX8
)
6708 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6710 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6713 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6714 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6715 Builder
bld(ctx
->program
, ctx
->block
);
6716 Temp rsrc
= get_scratch_resource(ctx
);
6717 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6718 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6721 switch (dst
.size()) {
6723 op
= aco_opcode::buffer_load_dword
;
6726 op
= aco_opcode::buffer_load_dwordx2
;
6729 op
= aco_opcode::buffer_load_dwordx3
;
6732 op
= aco_opcode::buffer_load_dwordx4
;
6736 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6737 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6738 bld
.def(v4
), rsrc
, offset
,
6739 ctx
->program
->scratch_offset
, 0, true);
6740 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6741 aco_opcode::buffer_load_dwordx4
,
6742 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6743 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6744 emit_split_vector(ctx
, lower
, 2);
6745 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6746 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6747 if (dst
.size() == 8) {
6748 emit_split_vector(ctx
, upper
, 2);
6749 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6750 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6755 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6756 Format::PSEUDO
, dst
.size() / 2, 1)};
6757 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6758 vec
->operands
[i
] = Operand(elems
[i
]);
6759 vec
->definitions
[0] = Definition(dst
);
6760 bld
.insert(std::move(vec
));
6761 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6765 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6768 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6769 emit_split_vector(ctx
, dst
, instr
->num_components
);
6772 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6773 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6774 Builder
bld(ctx
->program
, ctx
->block
);
6775 Temp rsrc
= get_scratch_resource(ctx
);
6776 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6777 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6779 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6780 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6784 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6785 int num_bytes
= count
* elem_size_bytes
;
6787 if (num_bytes
> 16) {
6788 assert(elem_size_bytes
== 8);
6789 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6794 // TODO: check alignment of sub-dword stores
6795 // TODO: split 3 bytes. there is no store instruction for that
6798 if (count
!= instr
->num_components
) {
6799 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6800 for (int i
= 0; i
< count
; i
++) {
6801 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6802 vec
->operands
[i
] = Operand(elem
);
6804 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6805 vec
->definitions
[0] = Definition(write_data
);
6806 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6812 switch (num_bytes
) {
6814 op
= aco_opcode::buffer_store_dword
;
6817 op
= aco_opcode::buffer_store_dwordx2
;
6820 op
= aco_opcode::buffer_store_dwordx3
;
6823 op
= aco_opcode::buffer_store_dwordx4
;
6826 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6829 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6833 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6834 uint8_t log2_ps_iter_samples
;
6835 if (ctx
->program
->info
->ps
.force_persample
) {
6836 log2_ps_iter_samples
=
6837 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6839 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6842 /* The bit pattern matches that used by fixed function fragment
6844 static const unsigned ps_iter_masks
[] = {
6845 0xffff, /* not used */
6851 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6853 Builder
bld(ctx
->program
, ctx
->block
);
6855 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6856 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6857 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6858 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6859 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6860 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6863 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6864 Builder
bld(ctx
->program
, ctx
->block
);
6866 unsigned stream
= nir_intrinsic_stream_id(instr
);
6867 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6868 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6869 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6872 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6874 unsigned num_components
=
6875 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6876 assert(num_components
);
6878 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6879 unsigned stream_offset
= 0;
6880 for (unsigned i
= 0; i
< stream
; i
++) {
6881 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6882 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6885 /* Limit on the stride field for <= GFX7. */
6886 assert(stride
< (1 << 14));
6888 Temp gsvs_dwords
[4];
6889 for (unsigned i
= 0; i
< 4; i
++)
6890 gsvs_dwords
[i
] = bld
.tmp(s1
);
6891 bld
.pseudo(aco_opcode::p_split_vector
,
6892 Definition(gsvs_dwords
[0]),
6893 Definition(gsvs_dwords
[1]),
6894 Definition(gsvs_dwords
[2]),
6895 Definition(gsvs_dwords
[3]),
6898 if (stream_offset
) {
6899 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6901 Temp carry
= bld
.tmp(s1
);
6902 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6903 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6906 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6907 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6909 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6910 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6912 unsigned offset
= 0;
6913 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6914 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6917 for (unsigned j
= 0; j
< 4; j
++) {
6918 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6921 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6922 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6923 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6924 if (const_offset
>= 4096u) {
6925 if (vaddr_offset
.isUndefined())
6926 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6928 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6929 const_offset
%= 4096u;
6932 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6933 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6934 mtbuf
->operands
[1] = vaddr_offset
;
6935 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6936 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6937 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6938 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6939 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6940 mtbuf
->offset
= const_offset
;
6943 mtbuf
->barrier
= barrier_gs_data
;
6944 mtbuf
->can_reorder
= true;
6945 bld
.insert(std::move(mtbuf
));
6948 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6951 /* outputs for the next vertex are undefined and keeping them around can
6952 * create invalid IR with control flow */
6953 ctx
->outputs
.mask
[i
] = 0;
6956 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6959 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6961 Builder
bld(ctx
->program
, ctx
->block
);
6963 if (cluster_size
== 1) {
6965 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6966 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6967 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6968 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6969 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6970 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6971 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6972 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6973 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6974 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6975 //subgroupAnd(val) -> (exec & ~val) == 0
6976 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6977 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6978 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6979 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6980 //subgroupOr(val) -> (val & exec) != 0
6981 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6982 return bool_to_vector_condition(ctx
, tmp
);
6983 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6984 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6985 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6986 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6987 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6988 return bool_to_vector_condition(ctx
, tmp
);
6990 //subgroupClustered{And,Or,Xor}(val, n) ->
6991 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6992 //cluster_offset = ~(n - 1) & lane_id
6993 //cluster_mask = ((1 << n) - 1)
6994 //subgroupClusteredAnd():
6995 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6996 //subgroupClusteredOr():
6997 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6998 //subgroupClusteredXor():
6999 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7000 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7001 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7004 if (op
== nir_op_iand
)
7005 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7007 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7009 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7011 if (ctx
->program
->chip_class
<= GFX7
)
7012 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7013 else if (ctx
->program
->wave_size
== 64)
7014 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7016 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7017 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7018 if (cluster_mask
!= 0xffffffff)
7019 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7021 Definition cmp_def
= Definition();
7022 if (op
== nir_op_iand
) {
7023 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7024 } else if (op
== nir_op_ior
) {
7025 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7026 } else if (op
== nir_op_ixor
) {
7027 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7028 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7029 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7031 cmp_def
.setHint(vcc
);
7032 return cmp_def
.getTemp();
7036 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7038 Builder
bld(ctx
->program
, ctx
->block
);
7040 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7041 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7042 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7044 if (op
== nir_op_iand
)
7045 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7047 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7049 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7050 Temp lo
= lohi
.def(0).getTemp();
7051 Temp hi
= lohi
.def(1).getTemp();
7052 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7054 Definition cmp_def
= Definition();
7055 if (op
== nir_op_iand
)
7056 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7057 else if (op
== nir_op_ior
)
7058 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7059 else if (op
== nir_op_ixor
)
7060 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7061 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7062 cmp_def
.setHint(vcc
);
7063 return cmp_def
.getTemp();
7066 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7068 Builder
bld(ctx
->program
, ctx
->block
);
7070 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7071 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7072 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7073 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7074 if (op
== nir_op_iand
)
7075 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7076 else if (op
== nir_op_ior
)
7077 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7078 else if (op
== nir_op_ixor
)
7079 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7085 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7087 Builder
bld(ctx
->program
, ctx
->block
);
7088 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7089 if (src
.regClass().type() == RegType::vgpr
) {
7090 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7091 } else if (src
.regClass() == s1
) {
7092 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7093 } else if (src
.regClass() == s2
) {
7094 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7096 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7097 nir_print_instr(&instr
->instr
, stderr
);
7098 fprintf(stderr
, "\n");
7102 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7104 Builder
bld(ctx
->program
, ctx
->block
);
7105 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7106 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7107 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7109 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7110 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7111 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7112 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7115 if (ctx
->program
->chip_class
>= GFX8
) {
7116 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7117 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7118 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7119 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7120 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7121 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7123 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7124 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7125 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7126 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7127 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7128 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7129 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7130 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7131 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7132 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7135 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7136 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7137 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7138 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7139 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7140 Temp wqm1
= bld
.tmp(v1
);
7141 emit_wqm(ctx
, tmp1
, wqm1
, true);
7142 Temp wqm2
= bld
.tmp(v1
);
7143 emit_wqm(ctx
, tmp2
, wqm2
, true);
7144 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7148 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7150 Builder
bld(ctx
->program
, ctx
->block
);
7151 switch(instr
->intrinsic
) {
7152 case nir_intrinsic_load_barycentric_sample
:
7153 case nir_intrinsic_load_barycentric_pixel
:
7154 case nir_intrinsic_load_barycentric_centroid
: {
7155 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7156 Temp bary
= Temp(0, s2
);
7158 case INTERP_MODE_SMOOTH
:
7159 case INTERP_MODE_NONE
:
7160 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7161 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7162 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7163 bary
= ctx
->persp_centroid
;
7164 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7165 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7167 case INTERP_MODE_NOPERSPECTIVE
:
7168 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7169 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7170 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7171 bary
= ctx
->linear_centroid
;
7172 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7173 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7178 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7179 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7180 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7181 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7182 Operand(p1
), Operand(p2
));
7183 emit_split_vector(ctx
, dst
, 2);
7186 case nir_intrinsic_load_barycentric_model
: {
7187 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7189 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7190 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7191 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7192 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7193 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7194 Operand(p1
), Operand(p2
), Operand(p3
));
7195 emit_split_vector(ctx
, dst
, 3);
7198 case nir_intrinsic_load_barycentric_at_sample
: {
7199 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7200 switch (ctx
->options
->key
.fs
.num_samples
) {
7201 case 2: sample_pos_offset
+= 1 << 3; break;
7202 case 4: sample_pos_offset
+= 3 << 3; break;
7203 case 8: sample_pos_offset
+= 7 << 3; break;
7207 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7208 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7209 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7210 if (addr
.type() == RegType::sgpr
) {
7213 sample_pos_offset
+= const_addr
->u32
<< 3;
7214 offset
= Operand(sample_pos_offset
);
7215 } else if (ctx
->options
->chip_class
>= GFX9
) {
7216 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7218 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7219 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7222 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7223 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7225 } else if (ctx
->options
->chip_class
>= GFX9
) {
7226 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7227 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7228 } else if (ctx
->options
->chip_class
>= GFX7
) {
7229 /* addr += private_segment_buffer + sample_pos_offset */
7230 Temp tmp0
= bld
.tmp(s1
);
7231 Temp tmp1
= bld
.tmp(s1
);
7232 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7233 Definition scc_tmp
= bld
.def(s1
, scc
);
7234 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7235 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7236 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7237 Temp pck0
= bld
.tmp(v1
);
7238 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7239 tmp1
= as_vgpr(ctx
, tmp1
);
7240 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7241 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7243 /* sample_pos = flat_load_dwordx2 addr */
7244 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7246 assert(ctx
->options
->chip_class
== GFX6
);
7248 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7249 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7250 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7252 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7253 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7255 sample_pos
= bld
.tmp(v2
);
7257 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7258 load
->definitions
[0] = Definition(sample_pos
);
7259 load
->operands
[0] = Operand(rsrc
);
7260 load
->operands
[1] = Operand(addr
);
7261 load
->operands
[2] = Operand(0u);
7262 load
->offset
= sample_pos_offset
;
7264 load
->addr64
= true;
7267 load
->disable_wqm
= false;
7268 load
->barrier
= barrier_none
;
7269 load
->can_reorder
= true;
7270 ctx
->block
->instructions
.emplace_back(std::move(load
));
7273 /* sample_pos -= 0.5 */
7274 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7275 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7276 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7277 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7278 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7280 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7283 case nir_intrinsic_load_barycentric_at_offset
: {
7284 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7285 RegClass rc
= RegClass(offset
.type(), 1);
7286 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7287 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7288 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7291 case nir_intrinsic_load_front_face
: {
7292 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7293 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7296 case nir_intrinsic_load_view_index
: {
7297 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7298 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7299 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7305 case nir_intrinsic_load_layer_id
: {
7306 unsigned idx
= nir_intrinsic_base(instr
);
7307 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7308 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7311 case nir_intrinsic_load_frag_coord
: {
7312 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7315 case nir_intrinsic_load_sample_pos
: {
7316 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7317 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7318 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7319 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7320 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7323 case nir_intrinsic_load_tess_coord
:
7324 visit_load_tess_coord(ctx
, instr
);
7326 case nir_intrinsic_load_interpolated_input
:
7327 visit_load_interpolated_input(ctx
, instr
);
7329 case nir_intrinsic_store_output
:
7330 visit_store_output(ctx
, instr
);
7332 case nir_intrinsic_load_input
:
7333 case nir_intrinsic_load_input_vertex
:
7334 visit_load_input(ctx
, instr
);
7336 case nir_intrinsic_load_output
:
7337 visit_load_output(ctx
, instr
);
7339 case nir_intrinsic_load_per_vertex_input
:
7340 visit_load_per_vertex_input(ctx
, instr
);
7342 case nir_intrinsic_load_per_vertex_output
:
7343 visit_load_per_vertex_output(ctx
, instr
);
7345 case nir_intrinsic_store_per_vertex_output
:
7346 visit_store_per_vertex_output(ctx
, instr
);
7348 case nir_intrinsic_load_ubo
:
7349 visit_load_ubo(ctx
, instr
);
7351 case nir_intrinsic_load_push_constant
:
7352 visit_load_push_constant(ctx
, instr
);
7354 case nir_intrinsic_load_constant
:
7355 visit_load_constant(ctx
, instr
);
7357 case nir_intrinsic_vulkan_resource_index
:
7358 visit_load_resource(ctx
, instr
);
7360 case nir_intrinsic_discard
:
7361 visit_discard(ctx
, instr
);
7363 case nir_intrinsic_discard_if
:
7364 visit_discard_if(ctx
, instr
);
7366 case nir_intrinsic_load_shared
:
7367 visit_load_shared(ctx
, instr
);
7369 case nir_intrinsic_store_shared
:
7370 visit_store_shared(ctx
, instr
);
7372 case nir_intrinsic_shared_atomic_add
:
7373 case nir_intrinsic_shared_atomic_imin
:
7374 case nir_intrinsic_shared_atomic_umin
:
7375 case nir_intrinsic_shared_atomic_imax
:
7376 case nir_intrinsic_shared_atomic_umax
:
7377 case nir_intrinsic_shared_atomic_and
:
7378 case nir_intrinsic_shared_atomic_or
:
7379 case nir_intrinsic_shared_atomic_xor
:
7380 case nir_intrinsic_shared_atomic_exchange
:
7381 case nir_intrinsic_shared_atomic_comp_swap
:
7382 visit_shared_atomic(ctx
, instr
);
7384 case nir_intrinsic_image_deref_load
:
7385 visit_image_load(ctx
, instr
);
7387 case nir_intrinsic_image_deref_store
:
7388 visit_image_store(ctx
, instr
);
7390 case nir_intrinsic_image_deref_atomic_add
:
7391 case nir_intrinsic_image_deref_atomic_umin
:
7392 case nir_intrinsic_image_deref_atomic_imin
:
7393 case nir_intrinsic_image_deref_atomic_umax
:
7394 case nir_intrinsic_image_deref_atomic_imax
:
7395 case nir_intrinsic_image_deref_atomic_and
:
7396 case nir_intrinsic_image_deref_atomic_or
:
7397 case nir_intrinsic_image_deref_atomic_xor
:
7398 case nir_intrinsic_image_deref_atomic_exchange
:
7399 case nir_intrinsic_image_deref_atomic_comp_swap
:
7400 visit_image_atomic(ctx
, instr
);
7402 case nir_intrinsic_image_deref_size
:
7403 visit_image_size(ctx
, instr
);
7405 case nir_intrinsic_load_ssbo
:
7406 visit_load_ssbo(ctx
, instr
);
7408 case nir_intrinsic_store_ssbo
:
7409 visit_store_ssbo(ctx
, instr
);
7411 case nir_intrinsic_load_global
:
7412 visit_load_global(ctx
, instr
);
7414 case nir_intrinsic_store_global
:
7415 visit_store_global(ctx
, instr
);
7417 case nir_intrinsic_global_atomic_add
:
7418 case nir_intrinsic_global_atomic_imin
:
7419 case nir_intrinsic_global_atomic_umin
:
7420 case nir_intrinsic_global_atomic_imax
:
7421 case nir_intrinsic_global_atomic_umax
:
7422 case nir_intrinsic_global_atomic_and
:
7423 case nir_intrinsic_global_atomic_or
:
7424 case nir_intrinsic_global_atomic_xor
:
7425 case nir_intrinsic_global_atomic_exchange
:
7426 case nir_intrinsic_global_atomic_comp_swap
:
7427 visit_global_atomic(ctx
, instr
);
7429 case nir_intrinsic_ssbo_atomic_add
:
7430 case nir_intrinsic_ssbo_atomic_imin
:
7431 case nir_intrinsic_ssbo_atomic_umin
:
7432 case nir_intrinsic_ssbo_atomic_imax
:
7433 case nir_intrinsic_ssbo_atomic_umax
:
7434 case nir_intrinsic_ssbo_atomic_and
:
7435 case nir_intrinsic_ssbo_atomic_or
:
7436 case nir_intrinsic_ssbo_atomic_xor
:
7437 case nir_intrinsic_ssbo_atomic_exchange
:
7438 case nir_intrinsic_ssbo_atomic_comp_swap
:
7439 visit_atomic_ssbo(ctx
, instr
);
7441 case nir_intrinsic_load_scratch
:
7442 visit_load_scratch(ctx
, instr
);
7444 case nir_intrinsic_store_scratch
:
7445 visit_store_scratch(ctx
, instr
);
7447 case nir_intrinsic_get_buffer_size
:
7448 visit_get_buffer_size(ctx
, instr
);
7450 case nir_intrinsic_control_barrier
: {
7451 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7452 /* GFX6 only (thanks to a hw bug workaround):
7453 * The real barrier instruction isn’t needed, because an entire patch
7454 * always fits into a single wave.
7459 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7460 bld
.sopp(aco_opcode::s_barrier
);
7464 case nir_intrinsic_memory_barrier_tcs_patch
:
7465 case nir_intrinsic_group_memory_barrier
:
7466 case nir_intrinsic_memory_barrier
:
7467 case nir_intrinsic_memory_barrier_buffer
:
7468 case nir_intrinsic_memory_barrier_image
:
7469 case nir_intrinsic_memory_barrier_shared
:
7470 emit_memory_barrier(ctx
, instr
);
7472 case nir_intrinsic_load_num_work_groups
: {
7473 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7474 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7475 emit_split_vector(ctx
, dst
, 3);
7478 case nir_intrinsic_load_local_invocation_id
: {
7479 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7480 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7481 emit_split_vector(ctx
, dst
, 3);
7484 case nir_intrinsic_load_work_group_id
: {
7485 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7486 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7487 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7488 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7489 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7490 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7491 emit_split_vector(ctx
, dst
, 3);
7494 case nir_intrinsic_load_local_invocation_index
: {
7495 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7497 /* The tg_size bits [6:11] contain the subgroup id,
7498 * we need this multiplied by the wave size, and then OR the thread id to it.
7500 if (ctx
->program
->wave_size
== 64) {
7501 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7502 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7503 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7504 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7506 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7507 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7508 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7509 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7513 case nir_intrinsic_load_subgroup_id
: {
7514 if (ctx
->stage
== compute_cs
) {
7515 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7516 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7518 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7522 case nir_intrinsic_load_subgroup_invocation
: {
7523 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7526 case nir_intrinsic_load_num_subgroups
: {
7527 if (ctx
->stage
== compute_cs
)
7528 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7529 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7531 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7534 case nir_intrinsic_ballot
: {
7535 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7536 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7537 Definition tmp
= bld
.def(dst
.regClass());
7538 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7539 if (instr
->src
[0].ssa
->bit_size
== 1) {
7540 assert(src
.regClass() == bld
.lm
);
7541 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7542 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7543 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7544 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7545 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7547 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7548 nir_print_instr(&instr
->instr
, stderr
);
7549 fprintf(stderr
, "\n");
7551 if (dst
.size() != bld
.lm
.size()) {
7552 /* Wave32 with ballot size set to 64 */
7553 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7555 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7558 case nir_intrinsic_shuffle
:
7559 case nir_intrinsic_read_invocation
: {
7560 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7561 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7562 emit_uniform_subgroup(ctx
, instr
, src
);
7564 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7565 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7566 tid
= bld
.as_uniform(tid
);
7567 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7568 if (src
.regClass() == v1
) {
7569 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7570 } else if (src
.regClass() == v2
) {
7571 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7572 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7573 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7574 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7575 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7576 emit_split_vector(ctx
, dst
, 2);
7577 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7578 assert(src
.regClass() == bld
.lm
);
7579 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7580 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7581 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7582 assert(src
.regClass() == bld
.lm
);
7584 if (ctx
->program
->chip_class
<= GFX7
)
7585 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7586 else if (ctx
->program
->wave_size
== 64)
7587 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7589 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7590 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7591 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7592 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7594 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7595 nir_print_instr(&instr
->instr
, stderr
);
7596 fprintf(stderr
, "\n");
7601 case nir_intrinsic_load_sample_id
: {
7602 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7603 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7606 case nir_intrinsic_load_sample_mask_in
: {
7607 visit_load_sample_mask_in(ctx
, instr
);
7610 case nir_intrinsic_read_first_invocation
: {
7611 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7612 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7613 if (src
.regClass() == v1
) {
7615 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7617 } else if (src
.regClass() == v2
) {
7618 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7619 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7620 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7621 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7622 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7623 emit_split_vector(ctx
, dst
, 2);
7624 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7625 assert(src
.regClass() == bld
.lm
);
7626 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7627 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7628 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7629 } else if (src
.regClass() == s1
) {
7630 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7631 } else if (src
.regClass() == s2
) {
7632 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7634 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7635 nir_print_instr(&instr
->instr
, stderr
);
7636 fprintf(stderr
, "\n");
7640 case nir_intrinsic_vote_all
: {
7641 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7642 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7643 assert(src
.regClass() == bld
.lm
);
7644 assert(dst
.regClass() == bld
.lm
);
7646 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7647 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7648 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7651 case nir_intrinsic_vote_any
: {
7652 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7653 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7654 assert(src
.regClass() == bld
.lm
);
7655 assert(dst
.regClass() == bld
.lm
);
7657 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7658 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7661 case nir_intrinsic_reduce
:
7662 case nir_intrinsic_inclusive_scan
:
7663 case nir_intrinsic_exclusive_scan
: {
7664 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7665 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7666 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7667 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7668 nir_intrinsic_cluster_size(instr
) : 0;
7669 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7671 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7672 emit_uniform_subgroup(ctx
, instr
, src
);
7673 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7674 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7676 else if (op
== nir_op_iadd
)
7678 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7680 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7682 switch (instr
->intrinsic
) {
7683 case nir_intrinsic_reduce
:
7684 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7686 case nir_intrinsic_exclusive_scan
:
7687 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7689 case nir_intrinsic_inclusive_scan
:
7690 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7695 } else if (cluster_size
== 1) {
7696 bld
.copy(Definition(dst
), src
);
7698 src
= as_vgpr(ctx
, src
);
7702 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7717 unreachable("unknown reduction op");
7722 switch (instr
->intrinsic
) {
7723 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7724 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7725 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7727 unreachable("unknown reduce intrinsic");
7730 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7731 reduce
->operands
[0] = Operand(src
);
7732 // filled in by aco_reduce_assign.cpp, used internally as part of the
7734 assert(dst
.size() == 1 || dst
.size() == 2);
7735 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7736 reduce
->operands
[2] = Operand(v1
.as_linear());
7738 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7739 reduce
->definitions
[0] = Definition(tmp_dst
);
7740 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7741 reduce
->definitions
[2] = Definition();
7742 reduce
->definitions
[3] = Definition(scc
, s1
);
7743 reduce
->definitions
[4] = Definition();
7744 reduce
->reduce_op
= reduce_op
;
7745 reduce
->cluster_size
= cluster_size
;
7746 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7748 emit_wqm(ctx
, tmp_dst
, dst
);
7752 case nir_intrinsic_quad_broadcast
: {
7753 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7754 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7755 emit_uniform_subgroup(ctx
, instr
, src
);
7757 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7758 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7759 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7761 if (instr
->dest
.ssa
.bit_size
== 1) {
7762 assert(src
.regClass() == bld
.lm
);
7763 assert(dst
.regClass() == bld
.lm
);
7764 uint32_t half_mask
= 0x11111111u
<< lane
;
7765 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7766 Temp tmp
= bld
.tmp(bld
.lm
);
7767 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7768 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7769 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7770 emit_wqm(ctx
, tmp
, dst
);
7771 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7772 if (ctx
->program
->chip_class
>= GFX8
)
7773 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7775 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7776 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7777 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7778 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7779 if (ctx
->program
->chip_class
>= GFX8
) {
7780 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7781 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7783 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7784 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7786 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7787 emit_split_vector(ctx
, dst
, 2);
7789 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7790 nir_print_instr(&instr
->instr
, stderr
);
7791 fprintf(stderr
, "\n");
7796 case nir_intrinsic_quad_swap_horizontal
:
7797 case nir_intrinsic_quad_swap_vertical
:
7798 case nir_intrinsic_quad_swap_diagonal
:
7799 case nir_intrinsic_quad_swizzle_amd
: {
7800 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7801 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7802 emit_uniform_subgroup(ctx
, instr
, src
);
7805 uint16_t dpp_ctrl
= 0;
7806 switch (instr
->intrinsic
) {
7807 case nir_intrinsic_quad_swap_horizontal
:
7808 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7810 case nir_intrinsic_quad_swap_vertical
:
7811 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7813 case nir_intrinsic_quad_swap_diagonal
:
7814 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7816 case nir_intrinsic_quad_swizzle_amd
:
7817 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7822 if (ctx
->program
->chip_class
< GFX8
)
7823 dpp_ctrl
|= (1 << 15);
7825 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7826 if (instr
->dest
.ssa
.bit_size
== 1) {
7827 assert(src
.regClass() == bld
.lm
);
7828 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7829 if (ctx
->program
->chip_class
>= GFX8
)
7830 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7832 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7833 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7834 emit_wqm(ctx
, tmp
, dst
);
7835 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7837 if (ctx
->program
->chip_class
>= GFX8
)
7838 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7840 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7841 emit_wqm(ctx
, tmp
, dst
);
7842 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7843 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7844 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7845 if (ctx
->program
->chip_class
>= GFX8
) {
7846 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7847 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7849 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7850 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7852 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7853 emit_split_vector(ctx
, dst
, 2);
7855 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7856 nir_print_instr(&instr
->instr
, stderr
);
7857 fprintf(stderr
, "\n");
7861 case nir_intrinsic_masked_swizzle_amd
: {
7862 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7863 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7864 emit_uniform_subgroup(ctx
, instr
, src
);
7867 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7868 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7869 if (dst
.regClass() == v1
) {
7871 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7873 } else if (dst
.regClass() == v2
) {
7874 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7875 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7876 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7877 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7878 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7879 emit_split_vector(ctx
, dst
, 2);
7881 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7882 nir_print_instr(&instr
->instr
, stderr
);
7883 fprintf(stderr
, "\n");
7887 case nir_intrinsic_write_invocation_amd
: {
7888 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7889 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7890 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7891 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7892 if (dst
.regClass() == v1
) {
7893 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7894 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7895 } else if (dst
.regClass() == v2
) {
7896 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7897 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7898 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7899 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7900 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7901 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7902 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7903 emit_split_vector(ctx
, dst
, 2);
7905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7906 nir_print_instr(&instr
->instr
, stderr
);
7907 fprintf(stderr
, "\n");
7911 case nir_intrinsic_mbcnt_amd
: {
7912 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7913 RegClass rc
= RegClass(src
.type(), 1);
7914 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7915 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7916 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7917 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7918 emit_wqm(ctx
, wqm_tmp
, dst
);
7921 case nir_intrinsic_load_helper_invocation
: {
7922 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7923 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7924 ctx
->block
->kind
|= block_kind_needs_lowering
;
7925 ctx
->program
->needs_exact
= true;
7928 case nir_intrinsic_is_helper_invocation
: {
7929 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7930 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7931 ctx
->block
->kind
|= block_kind_needs_lowering
;
7932 ctx
->program
->needs_exact
= true;
7935 case nir_intrinsic_demote
:
7936 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7938 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7939 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7940 ctx
->block
->kind
|= block_kind_uses_demote
;
7941 ctx
->program
->needs_exact
= true;
7943 case nir_intrinsic_demote_if
: {
7944 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7945 assert(src
.regClass() == bld
.lm
);
7946 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7947 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7949 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7950 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7951 ctx
->block
->kind
|= block_kind_uses_demote
;
7952 ctx
->program
->needs_exact
= true;
7955 case nir_intrinsic_first_invocation
: {
7956 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7957 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7960 case nir_intrinsic_shader_clock
:
7961 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7962 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7964 case nir_intrinsic_load_vertex_id_zero_base
: {
7965 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7966 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7969 case nir_intrinsic_load_first_vertex
: {
7970 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7971 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7974 case nir_intrinsic_load_base_instance
: {
7975 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7976 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7979 case nir_intrinsic_load_instance_id
: {
7980 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7981 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7984 case nir_intrinsic_load_draw_id
: {
7985 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7986 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7989 case nir_intrinsic_load_invocation_id
: {
7990 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7992 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7993 if (ctx
->options
->chip_class
>= GFX10
)
7994 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7996 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7997 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7998 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7999 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8001 unreachable("Unsupported stage for load_invocation_id");
8006 case nir_intrinsic_load_primitive_id
: {
8007 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8009 switch (ctx
->shader
->info
.stage
) {
8010 case MESA_SHADER_GEOMETRY
:
8011 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8013 case MESA_SHADER_TESS_CTRL
:
8014 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8016 case MESA_SHADER_TESS_EVAL
:
8017 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8020 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8025 case nir_intrinsic_load_patch_vertices_in
: {
8026 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8027 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8029 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8030 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8033 case nir_intrinsic_emit_vertex_with_counter
: {
8034 visit_emit_vertex_with_counter(ctx
, instr
);
8037 case nir_intrinsic_end_primitive_with_counter
: {
8038 unsigned stream
= nir_intrinsic_stream_id(instr
);
8039 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8042 case nir_intrinsic_set_vertex_count
: {
8043 /* unused, the HW keeps track of this for us */
8047 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8048 nir_print_instr(&instr
->instr
, stderr
);
8049 fprintf(stderr
, "\n");
8057 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8058 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8059 enum glsl_base_type
*stype
)
8061 nir_deref_instr
*texture_deref_instr
= NULL
;
8062 nir_deref_instr
*sampler_deref_instr
= NULL
;
8065 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8066 switch (instr
->src
[i
].src_type
) {
8067 case nir_tex_src_texture_deref
:
8068 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8070 case nir_tex_src_sampler_deref
:
8071 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8073 case nir_tex_src_plane
:
8074 plane
= nir_src_as_int(instr
->src
[i
].src
);
8081 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8083 if (!sampler_deref_instr
)
8084 sampler_deref_instr
= texture_deref_instr
;
8087 assert(instr
->op
!= nir_texop_txf_ms
&&
8088 instr
->op
!= nir_texop_samples_identical
);
8089 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8090 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8091 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8092 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8093 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8094 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8096 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8099 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8101 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8102 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8103 Builder
bld(ctx
->program
, ctx
->block
);
8105 /* to avoid unnecessary moves, we split and recombine sampler and image */
8106 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8107 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8108 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8109 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8110 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8111 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8112 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8113 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8115 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8116 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8117 img
[0], img
[1], img
[2], img
[3],
8118 img
[4], img
[5], img
[6], img
[7]);
8119 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8120 samp
[0], samp
[1], samp
[2], samp
[3]);
8123 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8124 instr
->op
== nir_texop_samples_identical
))
8125 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8128 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8129 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8131 Builder
bld(ctx
->program
, ctx
->block
);
8133 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8134 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8135 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8137 Operand
neg_one(0xbf800000u
);
8138 Operand
one(0x3f800000u
);
8139 Operand
two(0x40000000u
);
8140 Operand
four(0x40800000u
);
8142 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8143 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8144 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8146 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8147 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8148 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8149 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8152 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8153 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8154 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8156 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8159 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8160 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8161 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8164 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8165 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8167 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8168 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8171 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8173 Builder
bld(ctx
->program
, ctx
->block
);
8174 Temp ma
, tc
, sc
, id
;
8177 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8179 // see comment in ac_prepare_cube_coords()
8180 if (ctx
->options
->chip_class
<= GFX8
)
8181 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8184 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8186 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8187 vop3a
->operands
[0] = Operand(ma
);
8188 vop3a
->abs
[0] = true;
8189 Temp invma
= bld
.tmp(v1
);
8190 vop3a
->definitions
[0] = Definition(invma
);
8191 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8193 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8195 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8197 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8199 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8201 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8204 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8205 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8207 for (unsigned i
= 0; i
< 2; i
++) {
8208 // see comment in ac_prepare_cube_coords()
8210 Temp deriv_sc
, deriv_tc
;
8211 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8212 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8214 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8216 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8217 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8218 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8219 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8220 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8221 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8222 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8225 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8226 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8230 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8237 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8239 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8241 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8242 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8245 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8246 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8247 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8251 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8253 Builder
bld(ctx
->program
, ctx
->block
);
8254 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8255 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8256 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8257 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8258 std::vector
<Temp
> coords
;
8259 std::vector
<Temp
> derivs
;
8260 nir_const_value
*sample_index_cv
= NULL
;
8261 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8262 enum glsl_base_type stype
;
8263 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8265 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8266 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8267 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8268 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8270 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8271 switch (instr
->src
[i
].src_type
) {
8272 case nir_tex_src_coord
: {
8273 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8274 for (unsigned i
= 0; i
< coord
.size(); i
++)
8275 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8278 case nir_tex_src_bias
:
8279 if (instr
->op
== nir_texop_txb
) {
8280 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8284 case nir_tex_src_lod
: {
8285 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8287 if (val
&& val
->f32
<= 0.0) {
8290 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8295 case nir_tex_src_comparator
:
8296 if (instr
->is_shadow
) {
8297 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8301 case nir_tex_src_offset
:
8302 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8303 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8306 case nir_tex_src_ddx
:
8307 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8310 case nir_tex_src_ddy
:
8311 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8314 case nir_tex_src_ms_index
:
8315 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8316 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8317 has_sample_index
= true;
8319 case nir_tex_src_texture_offset
:
8320 case nir_tex_src_sampler_offset
:
8326 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8327 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8329 if (instr
->op
== nir_texop_texture_samples
) {
8330 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8332 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8333 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8334 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8335 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8337 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8338 samples
, Operand(1u), bld
.scc(is_msaa
));
8342 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8343 aco_ptr
<Instruction
> tmp_instr
;
8344 Temp acc
, pack
= Temp();
8346 uint32_t pack_const
= 0;
8347 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8348 if (!const_offset
[i
])
8350 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8353 if (offset
.type() == RegType::sgpr
) {
8354 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8355 if (const_offset
[i
])
8358 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8359 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8362 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8365 if (pack
== Temp()) {
8368 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8372 if (pack_const
&& pack
!= Temp())
8373 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8375 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8376 if (const_offset
[i
])
8379 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8380 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8383 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8386 if (pack
== Temp()) {
8389 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8393 if (pack_const
&& pack
!= Temp())
8394 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8396 if (pack_const
&& pack
== Temp())
8397 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8398 else if (pack
== Temp())
8404 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8405 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8407 /* pack derivatives */
8408 if (has_ddx
|| has_ddy
) {
8409 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8410 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8411 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8412 derivs
= {ddy
, zero
, ddy
, zero
};
8414 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8415 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8416 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8417 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8422 if (instr
->coord_components
> 1 &&
8423 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8425 instr
->op
!= nir_texop_txf
)
8426 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8428 if (instr
->coord_components
> 2 &&
8429 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8430 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8431 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8432 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8434 instr
->op
!= nir_texop_txf
&&
8435 instr
->op
!= nir_texop_txf_ms
&&
8436 instr
->op
!= nir_texop_fragment_fetch
&&
8437 instr
->op
!= nir_texop_fragment_mask_fetch
)
8438 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8440 if (ctx
->options
->chip_class
== GFX9
&&
8441 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8442 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8443 assert(coords
.size() > 0 && coords
.size() < 3);
8445 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8446 Operand((uint32_t) 0) :
8447 Operand((uint32_t) 0x3f000000)));
8450 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8452 if (instr
->op
== nir_texop_samples_identical
)
8453 resource
= fmask_ptr
;
8455 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8456 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8457 instr
->op
!= nir_texop_txs
&&
8458 instr
->op
!= nir_texop_fragment_fetch
&&
8459 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8460 assert(has_sample_index
);
8461 Operand
op(sample_index
);
8462 if (sample_index_cv
)
8463 op
= Operand(sample_index_cv
->u32
);
8464 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8467 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8468 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8469 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8470 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8475 /* Build tex instruction */
8476 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8477 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8478 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8480 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8483 /* gather4 selects the component by dmask and always returns vec4 */
8484 if (instr
->op
== nir_texop_tg4
) {
8485 assert(instr
->dest
.ssa
.num_components
== 4);
8486 if (instr
->is_shadow
)
8489 dmask
= 1 << instr
->component
;
8490 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8491 tmp_dst
= bld
.tmp(v4
);
8492 } else if (instr
->op
== nir_texop_samples_identical
) {
8493 tmp_dst
= bld
.tmp(v1
);
8494 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8495 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8498 aco_ptr
<MIMG_instruction
> tex
;
8499 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8501 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8503 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8504 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8507 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8508 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8510 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8511 tex
->operands
[0] = Operand(resource
);
8512 tex
->operands
[1] = Operand(s4
); /* no sampler */
8513 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8514 if (ctx
->options
->chip_class
== GFX9
&&
8515 instr
->op
== nir_texop_txs
&&
8516 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8518 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8519 } else if (instr
->op
== nir_texop_query_levels
) {
8520 tex
->dmask
= 1 << 3;
8525 tex
->definitions
[0] = Definition(tmp_dst
);
8527 tex
->can_reorder
= true;
8528 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8531 /* divide 3rd value by 6 by multiplying with magic number */
8532 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8533 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8534 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8535 assert(instr
->dest
.ssa
.num_components
== 3);
8536 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8537 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8538 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8539 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8544 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8548 Temp tg4_compare_cube_wa64
= Temp();
8550 if (tg4_integer_workarounds
) {
8551 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8552 tex
->operands
[0] = Operand(resource
);
8553 tex
->operands
[1] = Operand(s4
); /* no sampler */
8554 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8558 Temp size
= bld
.tmp(v2
);
8559 tex
->definitions
[0] = Definition(size
);
8560 tex
->can_reorder
= true;
8561 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8562 emit_split_vector(ctx
, size
, size
.size());
8565 for (unsigned i
= 0; i
< 2; i
++) {
8566 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8567 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8568 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8569 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8572 Temp new_coords
[2] = {
8573 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8574 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8577 if (tg4_integer_cube_workaround
) {
8578 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8579 Temp desc
[resource
.size()];
8580 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8581 Format::PSEUDO
, 1, resource
.size())};
8582 split
->operands
[0] = Operand(resource
);
8583 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8584 desc
[i
] = bld
.tmp(s1
);
8585 split
->definitions
[i
] = Definition(desc
[i
]);
8587 ctx
->block
->instructions
.emplace_back(std::move(split
));
8589 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8590 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8591 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8594 if (stype
== GLSL_TYPE_UINT
) {
8595 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8596 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8597 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8598 bld
.scc(compare_cube_wa
));
8600 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8601 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8602 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8603 bld
.scc(compare_cube_wa
));
8605 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8606 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8608 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8610 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8611 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8612 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8614 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8615 Format::PSEUDO
, resource
.size(), 1)};
8616 for (unsigned i
= 0; i
< resource
.size(); i
++)
8617 vec
->operands
[i
] = Operand(desc
[i
]);
8618 resource
= bld
.tmp(resource
.regClass());
8619 vec
->definitions
[0] = Definition(resource
);
8620 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8622 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8623 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8624 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8625 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8627 coords
[0] = new_coords
[0];
8628 coords
[1] = new_coords
[1];
8631 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8632 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8634 assert(coords
.size() == 1);
8635 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8639 op
= aco_opcode::buffer_load_format_x
; break;
8641 op
= aco_opcode::buffer_load_format_xy
; break;
8643 op
= aco_opcode::buffer_load_format_xyz
; break;
8645 op
= aco_opcode::buffer_load_format_xyzw
; break;
8647 unreachable("Tex instruction loads more than 4 components.");
8650 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8651 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8654 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8656 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8657 mubuf
->operands
[0] = Operand(resource
);
8658 mubuf
->operands
[1] = Operand(coords
[0]);
8659 mubuf
->operands
[2] = Operand((uint32_t) 0);
8660 mubuf
->definitions
[0] = Definition(tmp_dst
);
8661 mubuf
->idxen
= true;
8662 mubuf
->can_reorder
= true;
8663 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8665 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8669 /* gather MIMG address components */
8670 std::vector
<Temp
> args
;
8672 args
.emplace_back(offset
);
8674 args
.emplace_back(bias
);
8676 args
.emplace_back(compare
);
8678 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8680 args
.insert(args
.end(), coords
.begin(), coords
.end());
8681 if (has_sample_index
)
8682 args
.emplace_back(sample_index
);
8684 args
.emplace_back(lod
);
8686 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8687 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8688 vec
->definitions
[0] = Definition(arg
);
8689 for (unsigned i
= 0; i
< args
.size(); i
++)
8690 vec
->operands
[i
] = Operand(args
[i
]);
8691 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8694 if (instr
->op
== nir_texop_txf
||
8695 instr
->op
== nir_texop_txf_ms
||
8696 instr
->op
== nir_texop_samples_identical
||
8697 instr
->op
== nir_texop_fragment_fetch
||
8698 instr
->op
== nir_texop_fragment_mask_fetch
) {
8699 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8700 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8701 tex
->operands
[0] = Operand(resource
);
8702 tex
->operands
[1] = Operand(s4
); /* no sampler */
8703 tex
->operands
[2] = Operand(arg
);
8708 tex
->definitions
[0] = Definition(tmp_dst
);
8709 tex
->can_reorder
= true;
8710 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8712 if (instr
->op
== nir_texop_samples_identical
) {
8713 assert(dmask
== 1 && dst
.regClass() == v1
);
8714 assert(dst
.id() != tmp_dst
.id());
8716 Temp tmp
= bld
.tmp(bld
.lm
);
8717 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8718 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8721 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8726 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8727 aco_opcode opcode
= aco_opcode::image_sample
;
8728 if (has_offset
) { /* image_sample_*_o */
8730 opcode
= aco_opcode::image_sample_c_o
;
8732 opcode
= aco_opcode::image_sample_c_d_o
;
8734 opcode
= aco_opcode::image_sample_c_b_o
;
8736 opcode
= aco_opcode::image_sample_c_lz_o
;
8738 opcode
= aco_opcode::image_sample_c_l_o
;
8740 opcode
= aco_opcode::image_sample_o
;
8742 opcode
= aco_opcode::image_sample_d_o
;
8744 opcode
= aco_opcode::image_sample_b_o
;
8746 opcode
= aco_opcode::image_sample_lz_o
;
8748 opcode
= aco_opcode::image_sample_l_o
;
8750 } else { /* no offset */
8752 opcode
= aco_opcode::image_sample_c
;
8754 opcode
= aco_opcode::image_sample_c_d
;
8756 opcode
= aco_opcode::image_sample_c_b
;
8758 opcode
= aco_opcode::image_sample_c_lz
;
8760 opcode
= aco_opcode::image_sample_c_l
;
8762 opcode
= aco_opcode::image_sample
;
8764 opcode
= aco_opcode::image_sample_d
;
8766 opcode
= aco_opcode::image_sample_b
;
8768 opcode
= aco_opcode::image_sample_lz
;
8770 opcode
= aco_opcode::image_sample_l
;
8774 if (instr
->op
== nir_texop_tg4
) {
8776 opcode
= aco_opcode::image_gather4_lz_o
;
8778 opcode
= aco_opcode::image_gather4_c_lz_o
;
8780 opcode
= aco_opcode::image_gather4_lz
;
8782 opcode
= aco_opcode::image_gather4_c_lz
;
8784 } else if (instr
->op
== nir_texop_lod
) {
8785 opcode
= aco_opcode::image_get_lod
;
8788 /* we don't need the bias, sample index, compare value or offset to be
8789 * computed in WQM but if the p_create_vector copies the coordinates, then it
8790 * needs to be in WQM */
8791 if (ctx
->stage
== fragment_fs
&&
8792 !has_derivs
&& !has_lod
&& !level_zero
&&
8793 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8794 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8795 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8797 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8798 tex
->operands
[0] = Operand(resource
);
8799 tex
->operands
[1] = Operand(sampler
);
8800 tex
->operands
[2] = Operand(arg
);
8804 tex
->definitions
[0] = Definition(tmp_dst
);
8805 tex
->can_reorder
= true;
8806 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8808 if (tg4_integer_cube_workaround
) {
8809 assert(tmp_dst
.id() != dst
.id());
8810 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8812 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8814 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8815 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8817 if (stype
== GLSL_TYPE_UINT
)
8818 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8820 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8821 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8823 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8824 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8825 val
[0], val
[1], val
[2], val
[3]);
8827 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8828 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8833 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8835 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8836 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8837 return Operand(tmp
.regClass());
8839 return Operand(tmp
);
8842 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8844 aco_ptr
<Pseudo_instruction
> phi
;
8845 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8846 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8848 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8849 logical
|= ctx
->block
->kind
& block_kind_merge
;
8850 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8852 /* we want a sorted list of sources, since the predecessor list is also sorted */
8853 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8854 nir_foreach_phi_src(src
, instr
)
8855 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8857 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8858 unsigned num_operands
= 0;
8859 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8860 unsigned num_defined
= 0;
8861 unsigned cur_pred_idx
= 0;
8862 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8863 if (cur_pred_idx
< preds
.size()) {
8864 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8865 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8866 unsigned skipped
= 0;
8867 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8869 if (cur_pred_idx
+ skipped
< preds
.size()) {
8870 for (unsigned i
= 0; i
< skipped
; i
++)
8871 operands
[num_operands
++] = Operand(dst
.regClass());
8872 cur_pred_idx
+= skipped
;
8877 /* Handle missing predecessors at the end. This shouldn't happen with loop
8878 * headers and we can't ignore these sources for loop header phis. */
8879 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8882 Operand op
= get_phi_operand(ctx
, src
.second
);
8883 operands
[num_operands
++] = op
;
8884 num_defined
+= !op
.isUndefined();
8886 /* handle block_kind_continue_or_break at loop exit blocks */
8887 while (cur_pred_idx
++ < preds
.size())
8888 operands
[num_operands
++] = Operand(dst
.regClass());
8890 /* If the loop ends with a break, still add a linear continue edge in case
8891 * that break is divergent or continue_or_break is used. We'll either remove
8892 * this operand later in visit_loop() if it's not necessary or replace the
8893 * undef with something correct. */
8894 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8895 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8896 nir_block
*last
= nir_loop_last_block(loop
);
8897 if (last
->successors
[0] != instr
->instr
.block
)
8898 operands
[num_operands
++] = Operand(RegClass());
8901 if (num_defined
== 0) {
8902 Builder
bld(ctx
->program
, ctx
->block
);
8903 if (dst
.regClass() == s1
) {
8904 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8905 } else if (dst
.regClass() == v1
) {
8906 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8908 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8909 for (unsigned i
= 0; i
< dst
.size(); i
++)
8910 vec
->operands
[i
] = Operand(0u);
8911 vec
->definitions
[0] = Definition(dst
);
8912 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8917 /* we can use a linear phi in some cases if one src is undef */
8918 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8919 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8921 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8922 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8923 assert(invert
->kind
& block_kind_invert
);
8925 unsigned then_block
= invert
->linear_preds
[0];
8927 Block
* insert_block
= NULL
;
8928 for (unsigned i
= 0; i
< num_operands
; i
++) {
8929 Operand op
= operands
[i
];
8930 if (op
.isUndefined())
8932 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8933 phi
->operands
[0] = op
;
8936 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8937 phi
->operands
[1] = Operand(dst
.regClass());
8938 phi
->definitions
[0] = Definition(dst
);
8939 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8943 /* try to scalarize vector phis */
8944 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8945 // TODO: scalarize linear phis on divergent ifs
8946 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8947 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8948 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8949 Operand src
= operands
[i
];
8950 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8951 can_scalarize
= false;
8953 if (can_scalarize
) {
8954 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8955 assert(dst
.size() % num_components
== 0);
8956 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8958 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8959 for (unsigned k
= 0; k
< num_components
; k
++) {
8960 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8961 for (unsigned i
= 0; i
< num_operands
; i
++) {
8962 Operand src
= operands
[i
];
8963 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8965 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8966 phi
->definitions
[0] = Definition(phi_dst
);
8967 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8968 new_vec
[k
] = phi_dst
;
8969 vec
->operands
[k
] = Operand(phi_dst
);
8971 vec
->definitions
[0] = Definition(dst
);
8972 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8973 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8978 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8979 for (unsigned i
= 0; i
< num_operands
; i
++)
8980 phi
->operands
[i
] = operands
[i
];
8981 phi
->definitions
[0] = Definition(dst
);
8982 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8986 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8988 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8990 assert(dst
.type() == RegType::sgpr
);
8992 if (dst
.size() == 1) {
8993 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8995 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8996 for (unsigned i
= 0; i
< dst
.size(); i
++)
8997 vec
->operands
[i
] = Operand(0u);
8998 vec
->definitions
[0] = Definition(dst
);
8999 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9003 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9005 Builder
bld(ctx
->program
, ctx
->block
);
9006 Block
*logical_target
;
9007 append_logical_end(ctx
->block
);
9008 unsigned idx
= ctx
->block
->index
;
9010 switch (instr
->type
) {
9011 case nir_jump_break
:
9012 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9013 add_logical_edge(idx
, logical_target
);
9014 ctx
->block
->kind
|= block_kind_break
;
9016 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9017 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9018 /* uniform break - directly jump out of the loop */
9019 ctx
->block
->kind
|= block_kind_uniform
;
9020 ctx
->cf_info
.has_branch
= true;
9021 bld
.branch(aco_opcode::p_branch
);
9022 add_linear_edge(idx
, logical_target
);
9025 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9026 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9028 case nir_jump_continue
:
9029 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9030 add_logical_edge(idx
, logical_target
);
9031 ctx
->block
->kind
|= block_kind_continue
;
9033 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9034 /* for potential uniform breaks after this continue,
9035 we must ensure that they are handled correctly */
9036 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9037 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9038 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9040 /* uniform continue - directly jump to the loop header */
9041 ctx
->block
->kind
|= block_kind_uniform
;
9042 ctx
->cf_info
.has_branch
= true;
9043 bld
.branch(aco_opcode::p_branch
);
9044 add_linear_edge(idx
, logical_target
);
9049 fprintf(stderr
, "Unknown NIR jump instr: ");
9050 nir_print_instr(&instr
->instr
, stderr
);
9051 fprintf(stderr
, "\n");
9055 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9056 ctx
->cf_info
.exec_potentially_empty_break
= true;
9057 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9060 /* remove critical edges from linear CFG */
9061 bld
.branch(aco_opcode::p_branch
);
9062 Block
* break_block
= ctx
->program
->create_and_insert_block();
9063 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9064 break_block
->kind
|= block_kind_uniform
;
9065 add_linear_edge(idx
, break_block
);
9066 /* the loop_header pointer might be invalidated by this point */
9067 if (instr
->type
== nir_jump_continue
)
9068 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9069 add_linear_edge(break_block
->index
, logical_target
);
9070 bld
.reset(break_block
);
9071 bld
.branch(aco_opcode::p_branch
);
9073 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9074 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9075 add_linear_edge(idx
, continue_block
);
9076 append_logical_start(continue_block
);
9077 ctx
->block
= continue_block
;
9081 void visit_block(isel_context
*ctx
, nir_block
*block
)
9083 nir_foreach_instr(instr
, block
) {
9084 switch (instr
->type
) {
9085 case nir_instr_type_alu
:
9086 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9088 case nir_instr_type_load_const
:
9089 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9091 case nir_instr_type_intrinsic
:
9092 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9094 case nir_instr_type_tex
:
9095 visit_tex(ctx
, nir_instr_as_tex(instr
));
9097 case nir_instr_type_phi
:
9098 visit_phi(ctx
, nir_instr_as_phi(instr
));
9100 case nir_instr_type_ssa_undef
:
9101 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9103 case nir_instr_type_deref
:
9105 case nir_instr_type_jump
:
9106 visit_jump(ctx
, nir_instr_as_jump(instr
));
9109 fprintf(stderr
, "Unknown NIR instr type: ");
9110 nir_print_instr(instr
, stderr
);
9111 fprintf(stderr
, "\n");
9116 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9117 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9122 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9123 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9125 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9126 RegClass rc
= vals
[0].regClass();
9128 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9130 unsigned next_pred
= 1;
9132 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9133 Block
& block
= ctx
->program
->blocks
[idx
];
9134 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9135 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9139 if (block
.kind
& block_kind_continue
) {
9140 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9145 bool all_same
= true;
9146 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9147 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9151 val
= vals
[block
.linear_preds
[0] - first
];
9153 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9154 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9155 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9156 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9157 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9158 phi
->definitions
[0] = Definition(val
.getTemp());
9159 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9161 vals
[idx
- first
] = val
;
9164 return vals
[last
- first
];
9167 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9169 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9170 append_logical_end(ctx
->block
);
9171 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9172 Builder
bld(ctx
->program
, ctx
->block
);
9173 bld
.branch(aco_opcode::p_branch
);
9174 unsigned loop_preheader_idx
= ctx
->block
->index
;
9176 Block loop_exit
= Block();
9177 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9178 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9180 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9181 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9182 loop_header
->kind
|= block_kind_loop_header
;
9183 add_edge(loop_preheader_idx
, loop_header
);
9184 ctx
->block
= loop_header
;
9186 /* emit loop body */
9187 unsigned loop_header_idx
= loop_header
->index
;
9188 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9189 append_logical_start(ctx
->block
);
9190 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9192 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9193 if (!ctx
->cf_info
.has_branch
) {
9194 append_logical_end(ctx
->block
);
9195 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9196 /* Discards can result in code running with an empty exec mask.
9197 * This would result in divergent breaks not ever being taken. As a
9198 * workaround, break the loop when the loop mask is empty instead of
9199 * always continuing. */
9200 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9201 unsigned block_idx
= ctx
->block
->index
;
9203 /* create helper blocks to avoid critical edges */
9204 Block
*break_block
= ctx
->program
->create_and_insert_block();
9205 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9206 break_block
->kind
= block_kind_uniform
;
9207 bld
.reset(break_block
);
9208 bld
.branch(aco_opcode::p_branch
);
9209 add_linear_edge(block_idx
, break_block
);
9210 add_linear_edge(break_block
->index
, &loop_exit
);
9212 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9213 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9214 continue_block
->kind
= block_kind_uniform
;
9215 bld
.reset(continue_block
);
9216 bld
.branch(aco_opcode::p_branch
);
9217 add_linear_edge(block_idx
, continue_block
);
9218 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9220 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9221 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9222 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9224 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9225 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9226 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9228 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9231 bld
.reset(ctx
->block
);
9232 bld
.branch(aco_opcode::p_branch
);
9235 /* Fixup phis in loop header from unreachable blocks.
9236 * has_branch/has_divergent_branch also indicates if the loop ends with a
9237 * break/continue instruction, but we don't emit those if unreachable=true */
9239 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9240 bool linear
= ctx
->cf_info
.has_branch
;
9241 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9242 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9243 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9244 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9245 /* the last operand should be the one that needs to be removed */
9246 instr
->operands
.pop_back();
9247 } else if (!is_phi(instr
)) {
9253 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9254 * and the previous one shouldn't both happen at once because a break in the
9255 * merge block would get CSE'd */
9256 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9257 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9258 Operand vals
[num_vals
];
9259 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9260 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9261 if (ctx
->cf_info
.has_branch
)
9262 instr
->operands
.pop_back();
9264 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9265 } else if (!is_phi(instr
)) {
9271 ctx
->cf_info
.has_branch
= false;
9273 // TODO: if the loop has not a single exit, we must add one °°
9274 /* emit loop successor block */
9275 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9276 append_logical_start(ctx
->block
);
9279 // TODO: check if it is beneficial to not branch on continues
9280 /* trim linear phis in loop header */
9281 for (auto&& instr
: loop_entry
->instructions
) {
9282 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9283 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9284 new_phi
->definitions
[0] = instr
->definitions
[0];
9285 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9286 new_phi
->operands
[i
] = instr
->operands
[i
];
9287 /* check that the remaining operands are all the same */
9288 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9289 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9290 instr
.swap(new_phi
);
9291 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9300 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9304 append_logical_end(ctx
->block
);
9305 ctx
->block
->kind
|= block_kind_branch
;
9307 /* branch to linear then block */
9308 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9309 aco_ptr
<Pseudo_branch_instruction
> branch
;
9310 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9311 branch
->operands
[0] = Operand(cond
);
9312 ctx
->block
->instructions
.push_back(std::move(branch
));
9314 ic
->BB_if_idx
= ctx
->block
->index
;
9315 ic
->BB_invert
= Block();
9316 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9317 /* Invert blocks are intentionally not marked as top level because they
9318 * are not part of the logical cfg. */
9319 ic
->BB_invert
.kind
|= block_kind_invert
;
9320 ic
->BB_endif
= Block();
9321 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9322 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9324 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9325 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9326 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9327 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9328 ctx
->cf_info
.parent_if
.is_divergent
= true;
9330 /* divergent branches use cbranch_execz */
9331 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9332 ctx
->cf_info
.exec_potentially_empty_break
= false;
9333 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9335 /** emit logical then block */
9336 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9337 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9338 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9339 ctx
->block
= BB_then_logical
;
9340 append_logical_start(BB_then_logical
);
9343 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9345 Block
*BB_then_logical
= ctx
->block
;
9346 append_logical_end(BB_then_logical
);
9347 /* branch from logical then block to invert block */
9348 aco_ptr
<Pseudo_branch_instruction
> branch
;
9349 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9350 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9351 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9352 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9353 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9354 BB_then_logical
->kind
|= block_kind_uniform
;
9355 assert(!ctx
->cf_info
.has_branch
);
9356 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9357 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9359 /** emit linear then block */
9360 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9361 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9362 BB_then_linear
->kind
|= block_kind_uniform
;
9363 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9364 /* branch from linear then block to invert block */
9365 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9366 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9367 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9369 /** emit invert merge block */
9370 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9371 ic
->invert_idx
= ctx
->block
->index
;
9373 /* branch to linear else block (skip else) */
9374 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9375 branch
->operands
[0] = Operand(ic
->cond
);
9376 ctx
->block
->instructions
.push_back(std::move(branch
));
9378 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9379 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9380 ic
->exec_potentially_empty_break_depth_old
=
9381 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9382 /* divergent branches use cbranch_execz */
9383 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9384 ctx
->cf_info
.exec_potentially_empty_break
= false;
9385 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9387 /** emit logical else block */
9388 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9389 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9390 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9391 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9392 ctx
->block
= BB_else_logical
;
9393 append_logical_start(BB_else_logical
);
9396 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9398 Block
*BB_else_logical
= ctx
->block
;
9399 append_logical_end(BB_else_logical
);
9401 /* branch from logical else block to endif block */
9402 aco_ptr
<Pseudo_branch_instruction
> branch
;
9403 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9404 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9405 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9406 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9407 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9408 BB_else_logical
->kind
|= block_kind_uniform
;
9410 assert(!ctx
->cf_info
.has_branch
);
9411 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9414 /** emit linear else block */
9415 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9416 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9417 BB_else_linear
->kind
|= block_kind_uniform
;
9418 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9420 /* branch from linear else block to endif block */
9421 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9422 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9423 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9426 /** emit endif merge block */
9427 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9428 append_logical_start(ctx
->block
);
9431 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9432 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9433 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9434 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9435 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9436 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9437 !ctx
->cf_info
.parent_if
.is_divergent
) {
9438 ctx
->cf_info
.exec_potentially_empty_break
= false;
9439 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9441 /* uniform control flow never has an empty exec-mask */
9442 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9443 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9444 ctx
->cf_info
.exec_potentially_empty_break
= false;
9445 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9449 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9451 assert(cond
.regClass() == s1
);
9453 append_logical_end(ctx
->block
);
9454 ctx
->block
->kind
|= block_kind_uniform
;
9456 aco_ptr
<Pseudo_branch_instruction
> branch
;
9457 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9458 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9459 branch
->operands
[0] = Operand(cond
);
9460 branch
->operands
[0].setFixed(scc
);
9461 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9463 ic
->BB_if_idx
= ctx
->block
->index
;
9464 ic
->BB_endif
= Block();
9465 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9466 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9468 ctx
->cf_info
.has_branch
= false;
9469 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9471 /** emit then block */
9472 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9473 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9474 add_edge(ic
->BB_if_idx
, BB_then
);
9475 append_logical_start(BB_then
);
9476 ctx
->block
= BB_then
;
9479 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9481 Block
*BB_then
= ctx
->block
;
9483 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9484 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9486 if (!ic
->uniform_has_then_branch
) {
9487 append_logical_end(BB_then
);
9488 /* branch from then block to endif block */
9489 aco_ptr
<Pseudo_branch_instruction
> branch
;
9490 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9491 BB_then
->instructions
.emplace_back(std::move(branch
));
9492 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9493 if (!ic
->then_branch_divergent
)
9494 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9495 BB_then
->kind
|= block_kind_uniform
;
9498 ctx
->cf_info
.has_branch
= false;
9499 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9501 /** emit else block */
9502 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9503 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9504 add_edge(ic
->BB_if_idx
, BB_else
);
9505 append_logical_start(BB_else
);
9506 ctx
->block
= BB_else
;
9509 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9511 Block
*BB_else
= ctx
->block
;
9513 if (!ctx
->cf_info
.has_branch
) {
9514 append_logical_end(BB_else
);
9515 /* branch from then block to endif block */
9516 aco_ptr
<Pseudo_branch_instruction
> branch
;
9517 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9518 BB_else
->instructions
.emplace_back(std::move(branch
));
9519 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9520 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9521 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9522 BB_else
->kind
|= block_kind_uniform
;
9525 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9526 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9528 /** emit endif merge block */
9529 if (!ctx
->cf_info
.has_branch
) {
9530 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9531 append_logical_start(ctx
->block
);
9535 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9537 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9538 Builder
bld(ctx
->program
, ctx
->block
);
9539 aco_ptr
<Pseudo_branch_instruction
> branch
;
9542 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9544 * Uniform conditionals are represented in the following way*) :
9546 * The linear and logical CFG:
9549 * BB_THEN (logical) BB_ELSE (logical)
9553 * *) Exceptions may be due to break and continue statements within loops
9554 * If a break/continue happens within uniform control flow, it branches
9555 * to the loop exit/entry block. Otherwise, it branches to the next
9559 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9560 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9561 cond
= bool_to_scalar_condition(ctx
, cond
);
9563 begin_uniform_if_then(ctx
, &ic
, cond
);
9564 visit_cf_list(ctx
, &if_stmt
->then_list
);
9566 begin_uniform_if_else(ctx
, &ic
);
9567 visit_cf_list(ctx
, &if_stmt
->else_list
);
9569 end_uniform_if(ctx
, &ic
);
9571 return !ctx
->cf_info
.has_branch
;
9572 } else { /* non-uniform condition */
9574 * To maintain a logical and linear CFG without critical edges,
9575 * non-uniform conditionals are represented in the following way*) :
9580 * BB_THEN (logical) BB_THEN (linear)
9582 * BB_INVERT (linear)
9584 * BB_ELSE (logical) BB_ELSE (linear)
9591 * BB_THEN (logical) BB_ELSE (logical)
9595 * *) Exceptions may be due to break and continue statements within loops
9598 begin_divergent_if_then(ctx
, &ic
, cond
);
9599 visit_cf_list(ctx
, &if_stmt
->then_list
);
9601 begin_divergent_if_else(ctx
, &ic
);
9602 visit_cf_list(ctx
, &if_stmt
->else_list
);
9604 end_divergent_if(ctx
, &ic
);
9610 static bool visit_cf_list(isel_context
*ctx
,
9611 struct exec_list
*list
)
9613 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9614 switch (node
->type
) {
9615 case nir_cf_node_block
:
9616 visit_block(ctx
, nir_cf_node_as_block(node
));
9618 case nir_cf_node_if
:
9619 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9622 case nir_cf_node_loop
:
9623 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9626 unreachable("unimplemented cf list type");
9632 static void create_null_export(isel_context
*ctx
)
9634 /* Some shader stages always need to have exports.
9635 * So when there is none, we need to add a null export.
9638 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9639 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9640 Builder
bld(ctx
->program
, ctx
->block
);
9641 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9642 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9645 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9647 assert(ctx
->stage
== vertex_vs
||
9648 ctx
->stage
== tess_eval_vs
||
9649 ctx
->stage
== gs_copy_vs
||
9650 ctx
->stage
== ngg_vertex_gs
||
9651 ctx
->stage
== ngg_tess_eval_gs
);
9653 int offset
= (ctx
->stage
& sw_tes
)
9654 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9655 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9656 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9657 if (!is_pos
&& !mask
)
9659 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9661 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9662 exp
->enabled_mask
= mask
;
9663 for (unsigned i
= 0; i
< 4; ++i
) {
9664 if (mask
& (1 << i
))
9665 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9667 exp
->operands
[i
] = Operand(v1
);
9669 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9670 * Setting valid_mask=1 prevents it and has no other effect.
9672 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9674 exp
->compressed
= false;
9676 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9678 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9679 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9684 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9686 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9687 exp
->enabled_mask
= 0;
9688 for (unsigned i
= 0; i
< 4; ++i
)
9689 exp
->operands
[i
] = Operand(v1
);
9690 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9691 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9692 exp
->enabled_mask
|= 0x1;
9694 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9695 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9696 exp
->enabled_mask
|= 0x4;
9698 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9699 if (ctx
->options
->chip_class
< GFX9
) {
9700 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9701 exp
->enabled_mask
|= 0x8;
9703 Builder
bld(ctx
->program
, ctx
->block
);
9705 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9706 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9707 if (exp
->operands
[2].isTemp())
9708 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9710 exp
->operands
[2] = Operand(out
);
9711 exp
->enabled_mask
|= 0x4;
9714 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9716 exp
->compressed
= false;
9717 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9718 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9721 static void create_export_phis(isel_context
*ctx
)
9723 /* Used when exports are needed, but the output temps are defined in a preceding block.
9724 * This function will set up phis in order to access the outputs in the next block.
9727 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9728 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9729 ctx
->block
->instructions
.pop_back();
9731 Builder
bld(ctx
->program
, ctx
->block
);
9733 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9734 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9735 for (unsigned i
= 0; i
< 4; ++i
) {
9736 if (!(mask
& (1 << i
)))
9739 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9740 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9741 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9745 bld
.insert(std::move(logical_start
));
9748 static void create_vs_exports(isel_context
*ctx
)
9750 assert(ctx
->stage
== vertex_vs
||
9751 ctx
->stage
== tess_eval_vs
||
9752 ctx
->stage
== gs_copy_vs
||
9753 ctx
->stage
== ngg_vertex_gs
||
9754 ctx
->stage
== ngg_tess_eval_gs
);
9756 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9757 ? &ctx
->program
->info
->tes
.outinfo
9758 : &ctx
->program
->info
->vs
.outinfo
;
9760 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9761 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9762 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9765 if (ctx
->options
->key
.has_multiview_view_index
) {
9766 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9767 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9770 /* the order these position exports are created is important */
9772 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9773 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9774 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9775 exported_pos
= true;
9777 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9778 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9779 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9780 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9782 if (ctx
->export_clip_dists
) {
9783 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9784 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9785 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9786 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9789 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9790 if (i
< VARYING_SLOT_VAR0
&&
9791 i
!= VARYING_SLOT_LAYER
&&
9792 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9795 export_vs_varying(ctx
, i
, false, NULL
);
9799 create_null_export(ctx
);
9802 static bool export_fs_mrt_z(isel_context
*ctx
)
9804 Builder
bld(ctx
->program
, ctx
->block
);
9805 unsigned enabled_channels
= 0;
9809 for (unsigned i
= 0; i
< 4; ++i
) {
9810 values
[i
] = Operand(v1
);
9813 /* Both stencil and sample mask only need 16-bits. */
9814 if (!ctx
->program
->info
->ps
.writes_z
&&
9815 (ctx
->program
->info
->ps
.writes_stencil
||
9816 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9817 compr
= true; /* COMPR flag */
9819 if (ctx
->program
->info
->ps
.writes_stencil
) {
9820 /* Stencil should be in X[23:16]. */
9821 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9822 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9823 enabled_channels
|= 0x3;
9826 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9827 /* SampleMask should be in Y[15:0]. */
9828 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9829 enabled_channels
|= 0xc;
9832 if (ctx
->program
->info
->ps
.writes_z
) {
9833 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9834 enabled_channels
|= 0x1;
9837 if (ctx
->program
->info
->ps
.writes_stencil
) {
9838 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9839 enabled_channels
|= 0x2;
9842 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9843 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9844 enabled_channels
|= 0x4;
9848 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9849 * writemask component.
9851 if (ctx
->options
->chip_class
== GFX6
&&
9852 ctx
->options
->family
!= CHIP_OLAND
&&
9853 ctx
->options
->family
!= CHIP_HAINAN
) {
9854 enabled_channels
|= 0x1;
9857 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9858 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9863 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9865 Builder
bld(ctx
->program
, ctx
->block
);
9866 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9869 for (unsigned i
= 0; i
< 4; ++i
) {
9870 if (write_mask
& (1 << i
)) {
9871 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9873 values
[i
] = Operand(v1
);
9877 unsigned target
, col_format
;
9878 unsigned enabled_channels
= 0;
9879 aco_opcode compr_op
= (aco_opcode
)0;
9881 slot
-= FRAG_RESULT_DATA0
;
9882 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9883 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9885 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9886 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9890 case V_028714_SPI_SHADER_ZERO
:
9891 enabled_channels
= 0; /* writemask */
9892 target
= V_008DFC_SQ_EXP_NULL
;
9895 case V_028714_SPI_SHADER_32_R
:
9896 enabled_channels
= 1;
9899 case V_028714_SPI_SHADER_32_GR
:
9900 enabled_channels
= 0x3;
9903 case V_028714_SPI_SHADER_32_AR
:
9904 if (ctx
->options
->chip_class
>= GFX10
) {
9905 /* Special case: on GFX10, the outputs are different for 32_AR */
9906 enabled_channels
= 0x3;
9907 values
[1] = values
[3];
9908 values
[3] = Operand(v1
);
9910 enabled_channels
= 0x9;
9914 case V_028714_SPI_SHADER_FP16_ABGR
:
9915 enabled_channels
= 0x5;
9916 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9919 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9920 enabled_channels
= 0x5;
9921 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9924 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9925 enabled_channels
= 0x5;
9926 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9929 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9930 enabled_channels
= 0x5;
9931 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9932 if (is_int8
|| is_int10
) {
9934 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9935 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9937 for (unsigned i
= 0; i
< 4; i
++) {
9938 if ((write_mask
>> i
) & 1) {
9939 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9940 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9948 case V_028714_SPI_SHADER_SINT16_ABGR
:
9949 enabled_channels
= 0x5;
9950 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9951 if (is_int8
|| is_int10
) {
9953 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9954 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9955 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9956 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9958 for (unsigned i
= 0; i
< 4; i
++) {
9959 if ((write_mask
>> i
) & 1) {
9960 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9961 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9963 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9964 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9971 case V_028714_SPI_SHADER_32_ABGR
:
9972 enabled_channels
= 0xF;
9979 if (target
== V_008DFC_SQ_EXP_NULL
)
9982 if ((bool) compr_op
) {
9983 for (int i
= 0; i
< 2; i
++) {
9984 /* check if at least one of the values to be compressed is enabled */
9985 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9987 enabled_channels
|= enabled
<< (i
*2);
9988 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9989 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9990 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9992 values
[i
] = Operand(v1
);
9995 values
[2] = Operand(v1
);
9996 values
[3] = Operand(v1
);
9998 for (int i
= 0; i
< 4; i
++)
9999 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10002 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10003 enabled_channels
, target
, (bool) compr_op
);
10007 static void create_fs_exports(isel_context
*ctx
)
10009 bool exported
= false;
10011 /* Export depth, stencil and sample mask. */
10012 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10013 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10014 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10015 exported
|= export_fs_mrt_z(ctx
);
10017 /* Export all color render targets. */
10018 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10019 if (ctx
->outputs
.mask
[i
])
10020 exported
|= export_fs_mrt_color(ctx
, i
);
10023 create_null_export(ctx
);
10026 static void write_tcs_tess_factors(isel_context
*ctx
)
10028 unsigned outer_comps
;
10029 unsigned inner_comps
;
10031 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10048 Builder
bld(ctx
->program
, ctx
->block
);
10050 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10051 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10052 bld
.sopp(aco_opcode::s_barrier
);
10054 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10055 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10057 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10058 if_context ic_invocation_id_is_zero
;
10059 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10060 bld
.reset(ctx
->block
);
10062 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10064 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10065 unsigned stride
= inner_comps
+ outer_comps
;
10066 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10070 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10072 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10074 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10075 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10076 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10078 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10079 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10081 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10082 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10083 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10084 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10087 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10088 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10089 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10090 unsigned tf_const_offset
= 0;
10092 if (ctx
->program
->chip_class
<= GFX8
) {
10093 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10094 if_context ic_rel_patch_id_is_zero
;
10095 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10096 bld
.reset(ctx
->block
);
10098 /* Store the dynamic HS control word. */
10099 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10100 bld
.mubuf(aco_opcode::buffer_store_dword
,
10101 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10102 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10103 /* disable_wqm */ false, /* glc */ true);
10104 tf_const_offset
+= 4;
10106 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10107 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10108 bld
.reset(ctx
->block
);
10111 assert(stride
== 2 || stride
== 4 || stride
== 6);
10112 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10113 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10115 /* Store to offchip for TES to read - only if TES reads them */
10116 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10117 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10118 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10120 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10121 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10123 if (likely(inner_comps
)) {
10124 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10125 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10129 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10130 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10133 static void emit_stream_output(isel_context
*ctx
,
10134 Temp
const *so_buffers
,
10135 Temp
const *so_write_offset
,
10136 const struct radv_stream_output
*output
)
10138 unsigned num_comps
= util_bitcount(output
->component_mask
);
10139 unsigned writemask
= (1 << num_comps
) - 1;
10140 unsigned loc
= output
->location
;
10141 unsigned buf
= output
->buffer
;
10143 assert(num_comps
&& num_comps
<= 4);
10144 if (!num_comps
|| num_comps
> 4)
10147 unsigned start
= ffs(output
->component_mask
) - 1;
10150 bool all_undef
= true;
10151 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
10152 for (unsigned i
= 0; i
< num_comps
; i
++) {
10153 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10154 all_undef
= all_undef
&& !out
[i
].id();
10159 while (writemask
) {
10161 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10162 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10163 /* GFX6 doesn't support storing vec3, split it. */
10164 writemask
|= 1u << (start
+ 2);
10168 unsigned offset
= output
->offset
+ start
* 4;
10170 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10171 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10172 for (int i
= 0; i
< count
; ++i
)
10173 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10174 vec
->definitions
[0] = Definition(write_data
);
10175 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10180 opcode
= aco_opcode::buffer_store_dword
;
10183 opcode
= aco_opcode::buffer_store_dwordx2
;
10186 opcode
= aco_opcode::buffer_store_dwordx3
;
10189 opcode
= aco_opcode::buffer_store_dwordx4
;
10192 unreachable("Unsupported dword count.");
10195 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10196 store
->operands
[0] = Operand(so_buffers
[buf
]);
10197 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10198 store
->operands
[2] = Operand((uint32_t) 0);
10199 store
->operands
[3] = Operand(write_data
);
10200 if (offset
> 4095) {
10201 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10202 Builder
bld(ctx
->program
, ctx
->block
);
10203 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10205 store
->offset
= offset
;
10207 store
->offen
= true;
10209 store
->dlc
= false;
10211 store
->can_reorder
= true;
10212 ctx
->block
->instructions
.emplace_back(std::move(store
));
10216 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10218 Builder
bld(ctx
->program
, ctx
->block
);
10220 Temp so_buffers
[4];
10221 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10222 for (unsigned i
= 0; i
< 4; i
++) {
10223 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10227 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10228 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10231 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10232 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10234 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10236 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10239 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10241 bld
.reset(ctx
->block
);
10243 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10245 Temp so_write_offset
[4];
10247 for (unsigned i
= 0; i
< 4; i
++) {
10248 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10253 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10254 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10255 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10256 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10258 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10260 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10261 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10262 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10263 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10267 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10268 struct radv_stream_output
*output
=
10269 &ctx
->program
->info
->so
.outputs
[i
];
10270 if (stream
!= output
->stream
)
10273 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10276 begin_divergent_if_else(ctx
, &ic
);
10277 end_divergent_if(ctx
, &ic
);
10280 } /* end namespace */
10282 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10284 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10285 Builder
bld(ctx
->program
, ctx
->block
);
10286 constexpr unsigned hs_idx
= 1u;
10287 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10288 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10289 Operand((8u << 16) | (hs_idx
* 8u)));
10290 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10292 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10294 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10295 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10296 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10297 ls_has_nonzero_hs_threads
);
10298 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10299 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10300 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10301 ls_has_nonzero_hs_threads
);
10302 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10303 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10304 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10305 ls_has_nonzero_hs_threads
);
10307 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10308 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10309 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10312 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10314 /* Split all arguments except for the first (ring_offsets) and the last
10315 * (exec) so that the dead channels don't stay live throughout the program.
10317 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10318 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10319 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10320 startpgm
->definitions
[i
].regClass().size());
10325 void handle_bc_optimize(isel_context
*ctx
)
10327 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10328 Builder
bld(ctx
->program
, ctx
->block
);
10329 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10330 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10331 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10332 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10333 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10334 if (uses_center
&& uses_centroid
) {
10335 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10336 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10338 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10340 for (unsigned i
= 0; i
< 2; i
++) {
10341 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10342 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10343 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10344 persp_centroid
, persp_center
, sel
);
10346 ctx
->persp_centroid
= bld
.tmp(v2
);
10347 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10348 Operand(new_coord
[0]), Operand(new_coord
[1]));
10349 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10352 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10354 for (unsigned i
= 0; i
< 2; i
++) {
10355 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10356 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10357 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10358 linear_centroid
, linear_center
, sel
);
10360 ctx
->linear_centroid
= bld
.tmp(v2
);
10361 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10362 Operand(new_coord
[0]), Operand(new_coord
[1]));
10363 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10368 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10370 Program
*program
= ctx
->program
;
10372 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10374 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10375 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10376 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10377 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10378 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10380 program
->next_fp_mode
.must_flush_denorms32
=
10381 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10382 program
->next_fp_mode
.must_flush_denorms16_64
=
10383 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10384 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10386 program
->next_fp_mode
.care_about_round32
=
10387 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10389 program
->next_fp_mode
.care_about_round16_64
=
10390 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10391 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10393 /* default to preserving fp16 and fp64 denorms, since it's free */
10394 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10395 program
->next_fp_mode
.denorm16_64
= 0;
10397 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10399 /* preserving fp32 denorms is expensive, so only do it if asked */
10400 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10401 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10403 program
->next_fp_mode
.denorm32
= 0;
10405 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10406 program
->next_fp_mode
.round32
= fp_round_tz
;
10408 program
->next_fp_mode
.round32
= fp_round_ne
;
10410 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10411 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10413 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10415 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10418 void cleanup_cfg(Program
*program
)
10420 /* create linear_succs/logical_succs */
10421 for (Block
& BB
: program
->blocks
) {
10422 for (unsigned idx
: BB
.linear_preds
)
10423 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10424 for (unsigned idx
: BB
.logical_preds
)
10425 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10429 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10431 Builder
bld(ctx
->program
, ctx
->block
);
10433 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10434 Temp count
= i
== 0
10435 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10436 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10437 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10439 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10442 if (ctx
->program
->wave_size
== 64) {
10443 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10444 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10445 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10447 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10448 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10454 bool ngg_early_prim_export(isel_context
*ctx
)
10456 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10460 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10462 Builder
bld(ctx
->program
, ctx
->block
);
10464 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10465 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10467 /* Get the id of the current wave within the threadgroup (workgroup) */
10468 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10469 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10471 /* Execute the following code only on the first wave (wave id 0),
10472 * use the SCC def to tell if the wave id is zero or not.
10474 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10476 begin_uniform_if_then(ctx
, &ic
, cond
);
10477 begin_uniform_if_else(ctx
, &ic
);
10478 bld
.reset(ctx
->block
);
10480 /* Number of vertices output by VS/TES */
10481 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10482 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10483 /* Number of primitives output by VS/TES */
10484 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10485 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10487 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10488 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10489 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10491 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10492 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10494 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10495 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10497 end_uniform_if(ctx
, &ic
);
10500 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10502 Builder
bld(ctx
->program
, ctx
->block
);
10504 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10505 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10508 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10511 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10512 assert(vtxindex
[i
].id());
10515 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10519 /* The initial edge flag is always false in tess eval shaders. */
10520 if (ctx
->stage
== ngg_vertex_gs
) {
10521 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10522 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10526 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10531 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10533 Builder
bld(ctx
->program
, ctx
->block
);
10534 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10536 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10537 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10538 false /* compressed */, true/* done */, false /* valid mask */);
10541 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10543 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10544 * These must always come before VS exports.
10546 * It is recommended to do these as early as possible. They can be at the beginning when
10547 * there is no SW GS and the shader doesn't write edge flags.
10551 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10552 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10554 Builder
bld(ctx
->program
, ctx
->block
);
10555 constexpr unsigned max_vertices_per_primitive
= 3;
10556 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10558 if (ctx
->stage
== ngg_vertex_gs
) {
10559 /* TODO: optimize for points & lines */
10560 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10561 if (ctx
->shader
->info
.tess
.point_mode
)
10562 num_vertices_per_primitive
= 1;
10563 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10564 num_vertices_per_primitive
= 2;
10566 unreachable("Unsupported NGG shader stage");
10569 Temp vtxindex
[max_vertices_per_primitive
];
10570 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10571 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10572 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10573 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10574 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10575 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10576 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10577 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10579 /* Export primitive data to the index buffer. */
10580 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10582 /* Export primitive ID. */
10583 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10584 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10585 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10586 Temp provoking_vtx_index
= vtxindex
[0];
10587 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10589 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10592 begin_divergent_if_else(ctx
, &ic
);
10593 end_divergent_if(ctx
, &ic
);
10596 void ngg_emit_nogs_output(isel_context
*ctx
)
10598 /* Emits NGG GS output, for stages that don't have SW GS. */
10601 Builder
bld(ctx
->program
, ctx
->block
);
10602 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10604 /* NGG streamout is currently disabled by default. */
10605 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10607 if (late_prim_export
) {
10608 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10609 create_export_phis(ctx
);
10610 /* Do what we need to do in the GS threads. */
10611 ngg_emit_nogs_gsthreads(ctx
);
10613 /* What comes next should be executed on ES threads. */
10614 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10615 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10616 bld
.reset(ctx
->block
);
10619 /* Export VS outputs */
10620 ctx
->block
->kind
|= block_kind_export_end
;
10621 create_vs_exports(ctx
);
10623 /* Export primitive ID */
10624 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10627 if (ctx
->stage
== ngg_vertex_gs
) {
10628 /* Wait for GS threads to store primitive ID in LDS. */
10629 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10630 bld
.sopp(aco_opcode::s_barrier
);
10632 /* Calculate LDS address where the GS threads stored the primitive ID. */
10633 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10634 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10635 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10636 Temp wave_id_mul
= bld
.v_mul_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10637 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10638 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10640 /* Load primitive ID from LDS. */
10641 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10642 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10643 /* TES: Just use the patch ID as the primitive ID. */
10644 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10646 unreachable("unsupported NGG shader stage.");
10649 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10650 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10652 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10655 if (late_prim_export
) {
10656 begin_divergent_if_else(ctx
, &ic
);
10657 end_divergent_if(ctx
, &ic
);
10658 bld
.reset(ctx
->block
);
10662 void select_program(Program
*program
,
10663 unsigned shader_count
,
10664 struct nir_shader
*const *shaders
,
10665 ac_shader_config
* config
,
10666 struct radv_shader_args
*args
)
10668 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10669 if_context ic_merged_wave_info
;
10670 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10672 for (unsigned i
= 0; i
< shader_count
; i
++) {
10673 nir_shader
*nir
= shaders
[i
];
10674 init_context(&ctx
, nir
);
10676 setup_fp_mode(&ctx
, nir
);
10679 /* needs to be after init_context() for FS */
10680 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10681 append_logical_start(ctx
.block
);
10683 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10684 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10686 split_arguments(&ctx
, startpgm
);
10690 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10692 if (ngg_early_prim_export(&ctx
))
10693 ngg_emit_nogs_gsthreads(&ctx
);
10696 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10697 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10698 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10699 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10700 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10701 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10702 ctx
.stage
== tess_eval_geometry_gs
));
10704 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10705 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10706 if (check_merged_wave_info
) {
10707 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10708 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10712 Builder
bld(ctx
.program
, ctx
.block
);
10714 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10715 bld
.sopp(aco_opcode::s_barrier
);
10717 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10718 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10720 } else if (ctx
.stage
== geometry_gs
)
10721 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10723 if (ctx
.stage
== fragment_fs
)
10724 handle_bc_optimize(&ctx
);
10726 visit_cf_list(&ctx
, &func
->body
);
10728 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10729 emit_streamout(&ctx
, 0);
10731 if (ctx
.stage
& hw_vs
) {
10732 create_vs_exports(&ctx
);
10733 ctx
.block
->kind
|= block_kind_export_end
;
10734 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10735 ngg_emit_nogs_output(&ctx
);
10736 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10737 Builder
bld(ctx
.program
, ctx
.block
);
10738 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10739 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10740 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10741 write_tcs_tess_factors(&ctx
);
10744 if (ctx
.stage
== fragment_fs
) {
10745 create_fs_exports(&ctx
);
10746 ctx
.block
->kind
|= block_kind_export_end
;
10749 if (endif_merged_wave_info
) {
10750 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10751 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10754 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10755 ngg_emit_nogs_output(&ctx
);
10757 ralloc_free(ctx
.divergent_vals
);
10759 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10760 /* Outputs of the previous stage are inputs to the next stage */
10761 ctx
.inputs
= ctx
.outputs
;
10762 ctx
.outputs
= shader_io_state();
10766 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10768 append_logical_end(ctx
.block
);
10769 ctx
.block
->kind
|= block_kind_uniform
;
10770 Builder
bld(ctx
.program
, ctx
.block
);
10771 if (ctx
.program
->wb_smem_l1_on_end
)
10772 bld
.smem(aco_opcode::s_dcache_wb
, false);
10773 bld
.sopp(aco_opcode::s_endpgm
);
10775 cleanup_cfg(program
);
10778 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10779 ac_shader_config
* config
,
10780 struct radv_shader_args
*args
)
10782 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10784 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10785 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10786 program
->next_fp_mode
.must_flush_denorms32
= false;
10787 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10788 program
->next_fp_mode
.care_about_round32
= false;
10789 program
->next_fp_mode
.care_about_round16_64
= false;
10790 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10791 program
->next_fp_mode
.denorm32
= 0;
10792 program
->next_fp_mode
.round32
= fp_round_ne
;
10793 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10794 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10796 add_startpgm(&ctx
);
10797 append_logical_start(ctx
.block
);
10799 Builder
bld(ctx
.program
, ctx
.block
);
10801 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10803 Operand
stream_id(0u);
10804 if (args
->shader_info
->so
.num_outputs
)
10805 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10806 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10808 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10810 std::stack
<Block
> endif_blocks
;
10812 for (unsigned stream
= 0; stream
< 4; stream
++) {
10813 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10816 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10817 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10820 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10822 unsigned BB_if_idx
= ctx
.block
->index
;
10823 Block BB_endif
= Block();
10824 if (!stream_id
.isConstant()) {
10826 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10827 append_logical_end(ctx
.block
);
10828 ctx
.block
->kind
|= block_kind_uniform
;
10829 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10831 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10833 ctx
.block
= ctx
.program
->create_and_insert_block();
10834 add_edge(BB_if_idx
, ctx
.block
);
10835 bld
.reset(ctx
.block
);
10836 append_logical_start(ctx
.block
);
10839 unsigned offset
= 0;
10840 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10841 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10844 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10845 unsigned length
= util_last_bit(output_usage_mask
);
10846 for (unsigned j
= 0; j
< length
; ++j
) {
10847 if (!(output_usage_mask
& (1 << j
)))
10850 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10851 Temp voffset
= vtx_offset
;
10852 if (const_offset
>= 4096u) {
10853 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10854 const_offset
%= 4096u;
10857 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10858 mubuf
->definitions
[0] = bld
.def(v1
);
10859 mubuf
->operands
[0] = Operand(gsvs_ring
);
10860 mubuf
->operands
[1] = Operand(voffset
);
10861 mubuf
->operands
[2] = Operand(0u);
10862 mubuf
->offen
= true;
10863 mubuf
->offset
= const_offset
;
10866 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10867 mubuf
->barrier
= barrier_none
;
10868 mubuf
->can_reorder
= true;
10870 ctx
.outputs
.mask
[i
] |= 1 << j
;
10871 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10873 bld
.insert(std::move(mubuf
));
10879 if (args
->shader_info
->so
.num_outputs
) {
10880 emit_streamout(&ctx
, stream
);
10881 bld
.reset(ctx
.block
);
10885 create_vs_exports(&ctx
);
10886 ctx
.block
->kind
|= block_kind_export_end
;
10889 if (!stream_id
.isConstant()) {
10890 append_logical_end(ctx
.block
);
10892 /* branch from then block to endif block */
10893 bld
.branch(aco_opcode::p_branch
);
10894 add_edge(ctx
.block
->index
, &BB_endif
);
10895 ctx
.block
->kind
|= block_kind_uniform
;
10897 /* emit else block */
10898 ctx
.block
= ctx
.program
->create_and_insert_block();
10899 add_edge(BB_if_idx
, ctx
.block
);
10900 bld
.reset(ctx
.block
);
10901 append_logical_start(ctx
.block
);
10903 endif_blocks
.push(std::move(BB_endif
));
10907 while (!endif_blocks
.empty()) {
10908 Block BB_endif
= std::move(endif_blocks
.top());
10909 endif_blocks
.pop();
10911 Block
*BB_else
= ctx
.block
;
10913 append_logical_end(BB_else
);
10914 /* branch from else block to endif block */
10915 bld
.branch(aco_opcode::p_branch
);
10916 add_edge(BB_else
->index
, &BB_endif
);
10917 BB_else
->kind
|= block_kind_uniform
;
10919 /** emit endif merge block */
10920 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10921 bld
.reset(ctx
.block
);
10922 append_logical_start(ctx
.block
);
10925 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10927 append_logical_end(ctx
.block
);
10928 ctx
.block
->kind
|= block_kind_uniform
;
10929 bld
.sopp(aco_opcode::s_endpgm
);
10931 cleanup_cfg(program
);