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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
565 src1
= as_vgpr(ctx
, src1
);
569 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
570 assert(dst
.size() == 1);
571 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
572 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
574 bld
.vop2(op
, Definition(dst
), src0
, src1
);
578 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
579 bool flush_denorms
= false)
581 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
582 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
583 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
585 /* ensure that the instruction has at most 1 sgpr operand
586 * The optimizer will inline constants for us */
587 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
588 src0
= as_vgpr(ctx
, src0
);
589 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
590 src1
= as_vgpr(ctx
, src1
);
591 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
592 src2
= as_vgpr(ctx
, src2
);
594 Builder
bld(ctx
->program
, ctx
->block
);
595 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
596 assert(dst
.size() == 1);
597 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
598 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
600 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
604 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
606 Builder
bld(ctx
->program
, ctx
->block
);
607 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
610 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
612 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
613 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
614 assert(src0
.size() == src1
.size());
616 aco_ptr
<Instruction
> vopc
;
617 if (src1
.type() == RegType::sgpr
) {
618 if (src0
.type() == RegType::vgpr
) {
619 /* to swap the operands, we might also have to change the opcode */
621 case aco_opcode::v_cmp_lt_f16
:
622 op
= aco_opcode::v_cmp_gt_f16
;
624 case aco_opcode::v_cmp_ge_f16
:
625 op
= aco_opcode::v_cmp_le_f16
;
627 case aco_opcode::v_cmp_lt_i16
:
628 op
= aco_opcode::v_cmp_gt_i16
;
630 case aco_opcode::v_cmp_ge_i16
:
631 op
= aco_opcode::v_cmp_le_i16
;
633 case aco_opcode::v_cmp_lt_u16
:
634 op
= aco_opcode::v_cmp_gt_u16
;
636 case aco_opcode::v_cmp_ge_u16
:
637 op
= aco_opcode::v_cmp_le_u16
;
639 case aco_opcode::v_cmp_lt_f32
:
640 op
= aco_opcode::v_cmp_gt_f32
;
642 case aco_opcode::v_cmp_ge_f32
:
643 op
= aco_opcode::v_cmp_le_f32
;
645 case aco_opcode::v_cmp_lt_i32
:
646 op
= aco_opcode::v_cmp_gt_i32
;
648 case aco_opcode::v_cmp_ge_i32
:
649 op
= aco_opcode::v_cmp_le_i32
;
651 case aco_opcode::v_cmp_lt_u32
:
652 op
= aco_opcode::v_cmp_gt_u32
;
654 case aco_opcode::v_cmp_ge_u32
:
655 op
= aco_opcode::v_cmp_le_u32
;
657 case aco_opcode::v_cmp_lt_f64
:
658 op
= aco_opcode::v_cmp_gt_f64
;
660 case aco_opcode::v_cmp_ge_f64
:
661 op
= aco_opcode::v_cmp_le_f64
;
663 case aco_opcode::v_cmp_lt_i64
:
664 op
= aco_opcode::v_cmp_gt_i64
;
666 case aco_opcode::v_cmp_ge_i64
:
667 op
= aco_opcode::v_cmp_le_i64
;
669 case aco_opcode::v_cmp_lt_u64
:
670 op
= aco_opcode::v_cmp_gt_u64
;
672 case aco_opcode::v_cmp_ge_u64
:
673 op
= aco_opcode::v_cmp_le_u64
;
675 default: /* eq and ne are commutative */
682 src1
= as_vgpr(ctx
, src1
);
686 Builder
bld(ctx
->program
, ctx
->block
);
687 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
690 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
692 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
693 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
694 Builder
bld(ctx
->program
, ctx
->block
);
696 assert(dst
.regClass() == bld
.lm
);
697 assert(src0
.type() == RegType::sgpr
);
698 assert(src1
.type() == RegType::sgpr
);
699 assert(src0
.regClass() == src1
.regClass());
701 /* Emit the SALU comparison instruction */
702 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
703 /* Turn the result into a per-lane bool */
704 bool_to_vector_condition(ctx
, cmp
, dst
);
707 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
708 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
710 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
711 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
712 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
713 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
715 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
716 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
717 aco_opcode op
= use_valu
? v_op
: s_op
;
718 assert(op
!= aco_opcode::num_opcodes
);
719 assert(dst
.regClass() == ctx
->program
->lane_mask
);
722 emit_vopc_instruction(ctx
, instr
, op
, dst
);
724 emit_sopc_instruction(ctx
, instr
, op
, dst
);
727 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
729 Builder
bld(ctx
->program
, ctx
->block
);
730 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
731 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
733 assert(dst
.regClass() == bld
.lm
);
734 assert(src0
.regClass() == bld
.lm
);
735 assert(src1
.regClass() == bld
.lm
);
737 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
740 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
742 Builder
bld(ctx
->program
, ctx
->block
);
743 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
744 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
745 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
747 assert(cond
.regClass() == bld
.lm
);
749 if (dst
.type() == RegType::vgpr
) {
750 aco_ptr
<Instruction
> bcsel
;
751 if (dst
.regClass() == v2b
) {
752 then
= as_vgpr(ctx
, then
);
753 els
= as_vgpr(ctx
, els
);
755 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
756 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
757 } else if (dst
.regClass() == v1
) {
758 then
= as_vgpr(ctx
, then
);
759 els
= as_vgpr(ctx
, els
);
761 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
762 } else if (dst
.regClass() == v2
) {
763 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
765 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
766 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
768 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
769 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
771 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
773 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
774 nir_print_instr(&instr
->instr
, stderr
);
775 fprintf(stderr
, "\n");
780 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
781 assert(dst
.regClass() == bld
.lm
);
782 assert(then
.regClass() == bld
.lm
);
783 assert(els
.regClass() == bld
.lm
);
786 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
787 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
788 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
789 assert(dst
.size() == then
.size());
790 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
791 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
793 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
794 nir_print_instr(&instr
->instr
, stderr
);
795 fprintf(stderr
, "\n");
800 /* divergent boolean bcsel
801 * this implements bcsel on bools: dst = s0 ? s1 : s2
802 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
803 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
805 if (cond
.id() != then
.id())
806 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
808 if (cond
.id() == els
.id())
809 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
811 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
812 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
815 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
816 aco_opcode op
, uint32_t undo
)
818 /* multiply by 16777216 to handle denormals */
819 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
820 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
821 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
822 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
823 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
825 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
827 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
830 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
832 if (ctx
->block
->fp_mode
.denorm32
== 0) {
833 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
837 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
840 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
842 if (ctx
->block
->fp_mode
.denorm32
== 0) {
843 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
847 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
850 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
852 if (ctx
->block
->fp_mode
.denorm32
== 0) {
853 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
857 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
860 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
862 if (ctx
->block
->fp_mode
.denorm32
== 0) {
863 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
867 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
870 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
872 if (ctx
->options
->chip_class
>= GFX7
)
873 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
875 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
876 /* TODO: create more efficient code! */
877 if (val
.type() == RegType::sgpr
)
878 val
= as_vgpr(ctx
, val
);
880 /* Split the input value. */
881 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
882 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
884 /* Extract the exponent and compute the unbiased value. */
885 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
887 /* Extract the fractional part. */
888 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
889 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
891 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
892 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
894 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
895 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
896 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
897 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
898 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
900 /* Get the sign bit. */
901 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
903 /* Decide the operation to apply depending on the unbiased exponent. */
904 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
905 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
906 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
907 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
908 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
909 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
911 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
914 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
916 if (ctx
->options
->chip_class
>= GFX7
)
917 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
919 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
920 Temp src0
= as_vgpr(ctx
, val
);
922 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
923 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
925 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
926 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
927 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
929 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
930 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
931 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
934 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
935 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
937 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
939 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
940 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
942 return add
->definitions
[0].getTemp();
945 Temp
convert_int(Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
947 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
948 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
950 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
953 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
954 return bld
.copy(Definition(dst
), src
);
955 else if (dst
.bytes() < src
.bytes())
956 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
960 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
963 } else if (src
.regClass() == s1
) {
965 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
967 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
969 assert(src_bits
!= 8 || src
.regClass() == v1b
);
970 assert(src_bits
!= 16 || src
.regClass() == v2b
);
971 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
972 sdwa
->operands
[0] = Operand(src
);
973 sdwa
->definitions
[0] = Definition(tmp
);
975 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
977 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
978 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
979 bld
.insert(std::move(sdwa
));
982 if (dst_bits
== 64) {
983 if (is_signed
&& dst
.regClass() == s2
) {
984 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
985 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
986 } else if (is_signed
&& dst
.regClass() == v2
) {
987 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
988 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
990 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
997 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
999 if (!instr
->dest
.dest
.is_ssa
) {
1000 fprintf(stderr
, "nir alu dst not in ssa: ");
1001 nir_print_instr(&instr
->instr
, stderr
);
1002 fprintf(stderr
, "\n");
1005 Builder
bld(ctx
->program
, ctx
->block
);
1006 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1011 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1012 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1013 for (unsigned i
= 0; i
< num
; ++i
)
1014 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1016 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1017 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1018 for (unsigned i
= 0; i
< num
; ++i
)
1019 vec
->operands
[i
] = Operand
{elems
[i
]};
1020 vec
->definitions
[0] = Definition(dst
);
1021 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1022 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1024 // TODO: that is a bit suboptimal..
1025 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1026 for (unsigned i
= 0; i
< num
- 1; ++i
)
1027 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1028 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1029 for (unsigned i
= 0; i
< num
; ++i
) {
1030 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1031 if (bit
% 32 == 0) {
1032 elems
[bit
/ 32] = elems
[i
];
1034 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1035 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1036 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1039 if (dst
.size() == 1)
1040 bld
.copy(Definition(dst
), elems
[0]);
1042 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1047 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1048 aco_ptr
<Instruction
> mov
;
1049 if (dst
.type() == RegType::sgpr
) {
1050 if (src
.type() == RegType::vgpr
)
1051 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1052 else if (src
.regClass() == s1
)
1053 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1054 else if (src
.regClass() == s2
)
1055 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1057 unreachable("wrong src register class for nir_op_imov");
1058 } else if (dst
.regClass() == v1
) {
1059 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1060 } else if (dst
.regClass() == v2
) {
1061 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1063 nir_print_instr(&instr
->instr
, stderr
);
1064 unreachable("Should have been lowered to scalar.");
1069 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1070 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1071 assert(src
.regClass() == bld
.lm
);
1072 assert(dst
.regClass() == bld
.lm
);
1073 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1074 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1075 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1076 } else if (dst
.regClass() == v1
) {
1077 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1078 } else if (dst
.type() == RegType::sgpr
) {
1079 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1080 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1082 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1083 nir_print_instr(&instr
->instr
, stderr
);
1084 fprintf(stderr
, "\n");
1089 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1090 if (dst
.regClass() == v1
) {
1091 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1092 } else if (dst
.regClass() == s1
) {
1093 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1094 } else if (dst
.size() == 2) {
1095 Temp src0
= bld
.tmp(dst
.type(), 1);
1096 Temp src1
= bld
.tmp(dst
.type(), 1);
1097 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1099 if (dst
.regClass() == s2
) {
1100 Temp carry
= bld
.tmp(s1
);
1101 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1102 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1103 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1105 Temp lower
= bld
.tmp(v1
);
1106 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1107 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1108 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1111 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1112 nir_print_instr(&instr
->instr
, stderr
);
1113 fprintf(stderr
, "\n");
1118 if (dst
.regClass() == s1
) {
1119 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1120 } else if (dst
.regClass() == v1
) {
1121 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1122 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1124 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1125 nir_print_instr(&instr
->instr
, stderr
);
1126 fprintf(stderr
, "\n");
1130 case nir_op_isign
: {
1131 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1132 if (dst
.regClass() == s1
) {
1133 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1134 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1135 } else if (dst
.regClass() == s2
) {
1136 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1138 if (ctx
->program
->chip_class
>= GFX8
)
1139 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1141 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1142 /* SCC gets zero-extended to 64 bit */
1143 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1144 } else if (dst
.regClass() == v1
) {
1145 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1146 } else if (dst
.regClass() == v2
) {
1147 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1148 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1149 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1150 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1151 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1152 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1154 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1155 nir_print_instr(&instr
->instr
, stderr
);
1156 fprintf(stderr
, "\n");
1161 if (dst
.regClass() == v1
) {
1162 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1163 } else if (dst
.regClass() == s1
) {
1164 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1166 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1167 nir_print_instr(&instr
->instr
, stderr
);
1168 fprintf(stderr
, "\n");
1173 if (dst
.regClass() == v1
) {
1174 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1175 } else if (dst
.regClass() == s1
) {
1176 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1178 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1179 nir_print_instr(&instr
->instr
, stderr
);
1180 fprintf(stderr
, "\n");
1185 if (dst
.regClass() == v1
) {
1186 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1187 } else if (dst
.regClass() == s1
) {
1188 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1190 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1191 nir_print_instr(&instr
->instr
, stderr
);
1192 fprintf(stderr
, "\n");
1197 if (dst
.regClass() == v1
) {
1198 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1199 } else if (dst
.regClass() == s1
) {
1200 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1202 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1203 nir_print_instr(&instr
->instr
, stderr
);
1204 fprintf(stderr
, "\n");
1209 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1210 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1211 } else if (dst
.regClass() == v1
) {
1212 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1213 } else if (dst
.regClass() == s1
) {
1214 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1215 } else if (dst
.regClass() == s2
) {
1216 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1218 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1219 nir_print_instr(&instr
->instr
, stderr
);
1220 fprintf(stderr
, "\n");
1225 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1226 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1227 } else if (dst
.regClass() == v1
) {
1228 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1229 } else if (dst
.regClass() == s1
) {
1230 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1231 } else if (dst
.regClass() == s2
) {
1232 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1234 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1235 nir_print_instr(&instr
->instr
, stderr
);
1236 fprintf(stderr
, "\n");
1241 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1242 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1243 } else if (dst
.regClass() == v1
) {
1244 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1245 } else if (dst
.regClass() == s1
) {
1246 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1247 } else if (dst
.regClass() == s2
) {
1248 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1250 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1251 nir_print_instr(&instr
->instr
, stderr
);
1252 fprintf(stderr
, "\n");
1257 if (dst
.regClass() == v1
) {
1258 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1259 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1260 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1261 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1262 } else if (dst
.regClass() == v2
) {
1263 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1264 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1265 } else if (dst
.regClass() == s2
) {
1266 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1267 } else if (dst
.regClass() == s1
) {
1268 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1270 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1271 nir_print_instr(&instr
->instr
, stderr
);
1272 fprintf(stderr
, "\n");
1277 if (dst
.regClass() == v1
) {
1278 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1279 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1280 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1281 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1282 } else if (dst
.regClass() == v2
) {
1283 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1284 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1285 } else if (dst
.regClass() == s1
) {
1286 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1287 } else if (dst
.regClass() == s2
) {
1288 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1290 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1291 nir_print_instr(&instr
->instr
, stderr
);
1292 fprintf(stderr
, "\n");
1297 if (dst
.regClass() == v1
) {
1298 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1299 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1300 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1301 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1302 } else if (dst
.regClass() == v2
) {
1303 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1304 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1305 } else if (dst
.regClass() == s1
) {
1306 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1307 } else if (dst
.regClass() == s2
) {
1308 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1310 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1311 nir_print_instr(&instr
->instr
, stderr
);
1312 fprintf(stderr
, "\n");
1316 case nir_op_find_lsb
: {
1317 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1318 if (src
.regClass() == s1
) {
1319 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1320 } else if (src
.regClass() == v1
) {
1321 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1322 } else if (src
.regClass() == s2
) {
1323 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1325 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1326 nir_print_instr(&instr
->instr
, stderr
);
1327 fprintf(stderr
, "\n");
1331 case nir_op_ufind_msb
:
1332 case nir_op_ifind_msb
: {
1333 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1334 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1335 aco_opcode op
= src
.regClass() == s2
?
1336 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1337 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1338 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1340 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1341 Operand(src
.size() * 32u - 1u), msb_rev
);
1342 Temp msb
= sub
.def(0).getTemp();
1343 Temp carry
= sub
.def(1).getTemp();
1345 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1346 } else if (src
.regClass() == v1
) {
1347 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1348 Temp msb_rev
= bld
.tmp(v1
);
1349 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1350 Temp msb
= bld
.tmp(v1
);
1351 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1352 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1354 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1355 nir_print_instr(&instr
->instr
, stderr
);
1356 fprintf(stderr
, "\n");
1360 case nir_op_bitfield_reverse
: {
1361 if (dst
.regClass() == s1
) {
1362 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1363 } else if (dst
.regClass() == v1
) {
1364 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1366 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1367 nir_print_instr(&instr
->instr
, stderr
);
1368 fprintf(stderr
, "\n");
1373 if (dst
.regClass() == s1
) {
1374 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1378 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1379 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1380 if (dst
.regClass() == v1
) {
1381 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1385 assert(src0
.size() == 2 && src1
.size() == 2);
1386 Temp src00
= bld
.tmp(src0
.type(), 1);
1387 Temp src01
= bld
.tmp(dst
.type(), 1);
1388 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1389 Temp src10
= bld
.tmp(src1
.type(), 1);
1390 Temp src11
= bld
.tmp(dst
.type(), 1);
1391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1393 if (dst
.regClass() == s2
) {
1394 Temp carry
= bld
.tmp(s1
);
1395 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1396 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1397 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1398 } else if (dst
.regClass() == v2
) {
1399 Temp dst0
= bld
.tmp(v1
);
1400 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1401 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1402 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1404 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1405 nir_print_instr(&instr
->instr
, stderr
);
1406 fprintf(stderr
, "\n");
1410 case nir_op_uadd_sat
: {
1411 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1412 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1413 if (dst
.regClass() == s1
) {
1414 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1415 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1417 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1418 } else if (dst
.regClass() == v1
) {
1419 if (ctx
->options
->chip_class
>= GFX9
) {
1420 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1421 add
->operands
[0] = Operand(src0
);
1422 add
->operands
[1] = Operand(src1
);
1423 add
->definitions
[0] = Definition(dst
);
1425 ctx
->block
->instructions
.emplace_back(std::move(add
));
1427 if (src1
.regClass() != v1
)
1428 std::swap(src0
, src1
);
1429 assert(src1
.regClass() == v1
);
1430 Temp tmp
= bld
.tmp(v1
);
1431 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1432 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1435 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1436 nir_print_instr(&instr
->instr
, stderr
);
1437 fprintf(stderr
, "\n");
1441 case nir_op_uadd_carry
: {
1442 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1443 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1444 if (dst
.regClass() == s1
) {
1445 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1448 if (dst
.regClass() == v1
) {
1449 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1450 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1454 Temp src00
= bld
.tmp(src0
.type(), 1);
1455 Temp src01
= bld
.tmp(dst
.type(), 1);
1456 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1457 Temp src10
= bld
.tmp(src1
.type(), 1);
1458 Temp src11
= bld
.tmp(dst
.type(), 1);
1459 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1460 if (dst
.regClass() == s2
) {
1461 Temp carry
= bld
.tmp(s1
);
1462 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1463 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1465 } else if (dst
.regClass() == v2
) {
1466 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1467 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1468 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1469 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1471 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1472 nir_print_instr(&instr
->instr
, stderr
);
1473 fprintf(stderr
, "\n");
1478 if (dst
.regClass() == s1
) {
1479 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1483 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1484 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1485 if (dst
.regClass() == v1
) {
1486 bld
.vsub32(Definition(dst
), src0
, src1
);
1490 Temp src00
= bld
.tmp(src0
.type(), 1);
1491 Temp src01
= bld
.tmp(dst
.type(), 1);
1492 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1493 Temp src10
= bld
.tmp(src1
.type(), 1);
1494 Temp src11
= bld
.tmp(dst
.type(), 1);
1495 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1496 if (dst
.regClass() == s2
) {
1497 Temp carry
= bld
.tmp(s1
);
1498 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1499 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1500 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1501 } else if (dst
.regClass() == v2
) {
1502 Temp lower
= bld
.tmp(v1
);
1503 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1504 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1505 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1507 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1508 nir_print_instr(&instr
->instr
, stderr
);
1509 fprintf(stderr
, "\n");
1513 case nir_op_usub_borrow
: {
1514 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1515 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1516 if (dst
.regClass() == s1
) {
1517 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1519 } else if (dst
.regClass() == v1
) {
1520 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1521 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1525 Temp src00
= bld
.tmp(src0
.type(), 1);
1526 Temp src01
= bld
.tmp(dst
.type(), 1);
1527 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1528 Temp src10
= bld
.tmp(src1
.type(), 1);
1529 Temp src11
= bld
.tmp(dst
.type(), 1);
1530 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1531 if (dst
.regClass() == s2
) {
1532 Temp borrow
= bld
.tmp(s1
);
1533 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1534 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1535 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1536 } else if (dst
.regClass() == v2
) {
1537 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1538 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1539 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1540 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1542 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1543 nir_print_instr(&instr
->instr
, stderr
);
1544 fprintf(stderr
, "\n");
1549 if (dst
.regClass() == v1
) {
1550 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1551 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1552 } else if (dst
.regClass() == s1
) {
1553 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1555 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1556 nir_print_instr(&instr
->instr
, stderr
);
1557 fprintf(stderr
, "\n");
1561 case nir_op_umul_high
: {
1562 if (dst
.regClass() == v1
) {
1563 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1564 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1565 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1566 } else if (dst
.regClass() == s1
) {
1567 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1568 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1569 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1571 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1572 nir_print_instr(&instr
->instr
, stderr
);
1573 fprintf(stderr
, "\n");
1577 case nir_op_imul_high
: {
1578 if (dst
.regClass() == v1
) {
1579 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1580 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1581 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1582 } else if (dst
.regClass() == s1
) {
1583 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1584 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1585 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1587 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1588 nir_print_instr(&instr
->instr
, stderr
);
1589 fprintf(stderr
, "\n");
1594 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1595 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1596 if (dst
.regClass() == v2b
) {
1597 Temp tmp
= bld
.tmp(v1
);
1598 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1599 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1600 } else if (dst
.regClass() == v1
) {
1601 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1602 } else if (dst
.regClass() == v2
) {
1603 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1605 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1606 nir_print_instr(&instr
->instr
, stderr
);
1607 fprintf(stderr
, "\n");
1612 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1613 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1614 if (dst
.regClass() == v2b
) {
1615 Temp tmp
= bld
.tmp(v1
);
1616 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1618 } else if (dst
.regClass() == v1
) {
1619 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1620 } else if (dst
.regClass() == v2
) {
1621 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1623 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1624 nir_print_instr(&instr
->instr
, stderr
);
1625 fprintf(stderr
, "\n");
1630 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1631 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1632 if (dst
.regClass() == v2b
) {
1633 Temp tmp
= bld
.tmp(v1
);
1634 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1635 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1637 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1638 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1639 } else if (dst
.regClass() == v1
) {
1640 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1641 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1643 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1644 } else if (dst
.regClass() == v2
) {
1645 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1646 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1647 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1650 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1651 nir_print_instr(&instr
->instr
, stderr
);
1652 fprintf(stderr
, "\n");
1657 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1658 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1659 if (dst
.regClass() == v2b
) {
1660 // TODO: check fp_mode.must_flush_denorms16_64
1661 Temp tmp
= bld
.tmp(v1
);
1662 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1663 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1664 } else if (dst
.regClass() == v1
) {
1665 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1666 } else if (dst
.regClass() == v2
) {
1667 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1668 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1669 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1671 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1674 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1675 nir_print_instr(&instr
->instr
, stderr
);
1676 fprintf(stderr
, "\n");
1681 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1682 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1683 if (dst
.regClass() == v2b
) {
1684 // TODO: check fp_mode.must_flush_denorms16_64
1685 Temp tmp
= bld
.tmp(v1
);
1686 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1687 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1688 } else if (dst
.regClass() == v1
) {
1689 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1690 } else if (dst
.regClass() == v2
) {
1691 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1692 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1693 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1695 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1698 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1699 nir_print_instr(&instr
->instr
, stderr
);
1700 fprintf(stderr
, "\n");
1704 case nir_op_fmax3
: {
1705 if (dst
.regClass() == v2b
) {
1706 Temp tmp
= bld
.tmp(v1
);
1707 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1708 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1709 } else if (dst
.regClass() == v1
) {
1710 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1712 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1713 nir_print_instr(&instr
->instr
, stderr
);
1714 fprintf(stderr
, "\n");
1718 case nir_op_fmin3
: {
1719 if (dst
.regClass() == v2b
) {
1720 Temp tmp
= bld
.tmp(v1
);
1721 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1722 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1723 } else if (dst
.regClass() == v1
) {
1724 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1726 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1727 nir_print_instr(&instr
->instr
, stderr
);
1728 fprintf(stderr
, "\n");
1732 case nir_op_fmed3
: {
1733 if (dst
.regClass() == v2b
) {
1734 Temp tmp
= bld
.tmp(v1
);
1735 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1736 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1737 } else if (dst
.regClass() == v1
) {
1738 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1740 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1741 nir_print_instr(&instr
->instr
, stderr
);
1742 fprintf(stderr
, "\n");
1746 case nir_op_umax3
: {
1747 if (dst
.size() == 1) {
1748 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1750 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1751 nir_print_instr(&instr
->instr
, stderr
);
1752 fprintf(stderr
, "\n");
1756 case nir_op_umin3
: {
1757 if (dst
.size() == 1) {
1758 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1760 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1761 nir_print_instr(&instr
->instr
, stderr
);
1762 fprintf(stderr
, "\n");
1766 case nir_op_umed3
: {
1767 if (dst
.size() == 1) {
1768 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1770 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1771 nir_print_instr(&instr
->instr
, stderr
);
1772 fprintf(stderr
, "\n");
1776 case nir_op_imax3
: {
1777 if (dst
.size() == 1) {
1778 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1780 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1781 nir_print_instr(&instr
->instr
, stderr
);
1782 fprintf(stderr
, "\n");
1786 case nir_op_imin3
: {
1787 if (dst
.size() == 1) {
1788 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1791 nir_print_instr(&instr
->instr
, stderr
);
1792 fprintf(stderr
, "\n");
1796 case nir_op_imed3
: {
1797 if (dst
.size() == 1) {
1798 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1800 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1801 nir_print_instr(&instr
->instr
, stderr
);
1802 fprintf(stderr
, "\n");
1806 case nir_op_cube_face_coord
: {
1807 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1808 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1809 emit_extract_vector(ctx
, in
, 1, v1
),
1810 emit_extract_vector(ctx
, in
, 2, v1
) };
1811 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1812 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1813 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1814 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1815 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1816 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1817 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1820 case nir_op_cube_face_index
: {
1821 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1822 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1823 emit_extract_vector(ctx
, in
, 1, v1
),
1824 emit_extract_vector(ctx
, in
, 2, v1
) };
1825 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1828 case nir_op_bcsel
: {
1829 emit_bcsel(ctx
, instr
, dst
);
1833 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1834 if (dst
.regClass() == v2b
) {
1835 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1836 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1837 } else if (dst
.regClass() == v1
) {
1838 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1839 } else if (dst
.regClass() == v2
) {
1840 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1842 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1843 nir_print_instr(&instr
->instr
, stderr
);
1844 fprintf(stderr
, "\n");
1849 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1850 if (dst
.regClass() == v2b
) {
1851 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1852 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1853 } else if (dst
.regClass() == v1
) {
1854 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1855 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1856 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1857 } else if (dst
.regClass() == v2
) {
1858 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1859 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1860 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1861 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1862 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1863 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1865 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1866 nir_print_instr(&instr
->instr
, stderr
);
1867 fprintf(stderr
, "\n");
1872 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1873 if (dst
.regClass() == v2b
) {
1874 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1875 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1876 } else if (dst
.regClass() == v1
) {
1877 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1878 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1879 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1880 } else if (dst
.regClass() == v2
) {
1881 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1882 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1883 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1884 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1885 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1886 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1889 nir_print_instr(&instr
->instr
, stderr
);
1890 fprintf(stderr
, "\n");
1895 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1896 if (dst
.regClass() == v2b
) {
1897 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1898 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1899 } else if (dst
.regClass() == v1
) {
1900 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1901 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1902 // TODO: confirm that this holds under any circumstances
1903 } else if (dst
.regClass() == v2
) {
1904 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1905 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1909 nir_print_instr(&instr
->instr
, stderr
);
1910 fprintf(stderr
, "\n");
1914 case nir_op_flog2
: {
1915 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1916 if (dst
.regClass() == v2b
) {
1917 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1918 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1919 } else if (dst
.regClass() == v1
) {
1920 emit_log2(ctx
, bld
, Definition(dst
), src
);
1922 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1923 nir_print_instr(&instr
->instr
, stderr
);
1924 fprintf(stderr
, "\n");
1929 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1930 if (dst
.regClass() == v2b
) {
1931 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1933 } else if (dst
.regClass() == v1
) {
1934 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1935 } else if (dst
.regClass() == v2
) {
1936 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1938 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1939 nir_print_instr(&instr
->instr
, stderr
);
1940 fprintf(stderr
, "\n");
1944 case nir_op_fexp2
: {
1945 if (dst
.regClass() == v2b
) {
1946 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1947 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1948 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1949 } else if (dst
.regClass() == v1
) {
1950 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1952 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1953 nir_print_instr(&instr
->instr
, stderr
);
1954 fprintf(stderr
, "\n");
1958 case nir_op_fsqrt
: {
1959 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1960 if (dst
.regClass() == v2b
) {
1961 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1963 } else if (dst
.regClass() == v1
) {
1964 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1965 } else if (dst
.regClass() == v2
) {
1966 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1968 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1969 nir_print_instr(&instr
->instr
, stderr
);
1970 fprintf(stderr
, "\n");
1974 case nir_op_ffract
: {
1975 if (dst
.regClass() == v2b
) {
1976 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1977 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1978 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1979 } else if (dst
.regClass() == v1
) {
1980 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1981 } else if (dst
.regClass() == v2
) {
1982 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1984 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1985 nir_print_instr(&instr
->instr
, stderr
);
1986 fprintf(stderr
, "\n");
1990 case nir_op_ffloor
: {
1991 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1992 if (dst
.regClass() == v2b
) {
1993 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1994 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1995 } else if (dst
.regClass() == v1
) {
1996 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1997 } else if (dst
.regClass() == v2
) {
1998 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2000 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2001 nir_print_instr(&instr
->instr
, stderr
);
2002 fprintf(stderr
, "\n");
2006 case nir_op_fceil
: {
2007 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2008 if (dst
.regClass() == v2b
) {
2009 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
2010 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2011 } else if (dst
.regClass() == v1
) {
2012 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2013 } else if (dst
.regClass() == v2
) {
2014 if (ctx
->options
->chip_class
>= GFX7
) {
2015 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2017 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2018 /* trunc = trunc(src0)
2019 * if (src0 > 0.0 && src0 != trunc)
2022 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2023 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2024 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2025 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2026 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2027 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2028 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2031 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2032 nir_print_instr(&instr
->instr
, stderr
);
2033 fprintf(stderr
, "\n");
2037 case nir_op_ftrunc
: {
2038 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2039 if (dst
.regClass() == v2b
) {
2040 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2041 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2042 } else if (dst
.regClass() == v1
) {
2043 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2044 } else if (dst
.regClass() == v2
) {
2045 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2053 case nir_op_fround_even
: {
2054 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2055 if (dst
.regClass() == v2b
) {
2056 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2057 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2058 } else if (dst
.regClass() == v1
) {
2059 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2060 } else if (dst
.regClass() == v2
) {
2061 if (ctx
->options
->chip_class
>= GFX7
) {
2062 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2064 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2065 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2066 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2068 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2069 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2070 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2071 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2072 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2073 tmp
= sub
->definitions
[0].getTemp();
2075 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2076 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2077 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2078 Temp cond
= vop3
->definitions
[0].getTemp();
2080 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2081 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2082 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2083 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2085 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2088 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2089 nir_print_instr(&instr
->instr
, stderr
);
2090 fprintf(stderr
, "\n");
2096 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2097 aco_ptr
<Instruction
> norm
;
2098 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2099 if (dst
.regClass() == v2b
) {
2100 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2101 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2102 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2103 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2104 } else if (dst
.regClass() == v1
) {
2105 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2107 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2108 if (ctx
->options
->chip_class
< GFX9
)
2109 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2111 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2112 bld
.vop1(opcode
, Definition(dst
), tmp
);
2114 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2115 nir_print_instr(&instr
->instr
, stderr
);
2116 fprintf(stderr
, "\n");
2120 case nir_op_ldexp
: {
2121 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2122 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2123 if (dst
.regClass() == v2b
) {
2124 Temp tmp
= bld
.tmp(v1
);
2125 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2126 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2127 } else if (dst
.regClass() == v1
) {
2128 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2129 } else if (dst
.regClass() == v2
) {
2130 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2132 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2133 nir_print_instr(&instr
->instr
, stderr
);
2134 fprintf(stderr
, "\n");
2138 case nir_op_frexp_sig
: {
2139 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2140 if (dst
.regClass() == v2b
) {
2141 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2142 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2143 } else if (dst
.regClass() == v1
) {
2144 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2145 } else if (dst
.regClass() == v2
) {
2146 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2148 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2149 nir_print_instr(&instr
->instr
, stderr
);
2150 fprintf(stderr
, "\n");
2154 case nir_op_frexp_exp
: {
2155 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2156 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2157 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2158 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2159 convert_int(bld
, tmp
, 8, 32, true, dst
);
2160 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2161 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2162 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2163 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2165 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2166 nir_print_instr(&instr
->instr
, stderr
);
2167 fprintf(stderr
, "\n");
2171 case nir_op_fsign
: {
2172 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2173 if (dst
.regClass() == v2b
) {
2174 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2175 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2176 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2177 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2178 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2179 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2180 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2181 } else if (dst
.regClass() == v1
) {
2182 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2183 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2184 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2185 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2186 } else if (dst
.regClass() == v2
) {
2187 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2188 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2189 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2191 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2192 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2193 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2195 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2197 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2198 nir_print_instr(&instr
->instr
, stderr
);
2199 fprintf(stderr
, "\n");
2204 case nir_op_f2f16_rtne
: {
2205 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2206 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2207 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2208 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2209 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2212 case nir_op_f2f16_rtz
: {
2213 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2214 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2215 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2216 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2217 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2220 case nir_op_f2f32
: {
2221 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2222 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2223 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2224 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2226 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2227 nir_print_instr(&instr
->instr
, stderr
);
2228 fprintf(stderr
, "\n");
2232 case nir_op_f2f64
: {
2233 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2234 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2235 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2236 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2239 case nir_op_i2f16
: {
2240 assert(dst
.regClass() == v2b
);
2241 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2242 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2243 src
= convert_int(bld
, src
, 8, 16, true);
2244 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_i16
, bld
.def(v1
), src
);
2245 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2248 case nir_op_i2f32
: {
2249 assert(dst
.size() == 1);
2250 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2251 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2252 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2253 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2256 case nir_op_i2f64
: {
2257 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2258 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2259 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2260 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2261 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2262 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2263 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2264 RegClass rc
= RegClass(src
.type(), 1);
2265 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2266 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2267 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2268 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2269 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2270 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2273 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2274 nir_print_instr(&instr
->instr
, stderr
);
2275 fprintf(stderr
, "\n");
2279 case nir_op_u2f16
: {
2280 assert(dst
.regClass() == v2b
);
2281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2282 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2283 src
= convert_int(bld
, src
, 8, 16, false);
2284 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_u16
, bld
.def(v1
), src
);
2285 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2288 case nir_op_u2f32
: {
2289 assert(dst
.size() == 1);
2290 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2291 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2292 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2293 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2295 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2296 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2297 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2301 case nir_op_u2f64
: {
2302 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2303 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2304 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2305 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2306 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2307 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2308 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2309 RegClass rc
= RegClass(src
.type(), 1);
2310 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2311 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2312 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2313 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2314 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2315 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2317 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2318 nir_print_instr(&instr
->instr
, stderr
);
2319 fprintf(stderr
, "\n");
2324 case nir_op_f2i16
: {
2325 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2326 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2327 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2328 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2329 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2331 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2333 if (dst
.type() == RegType::vgpr
)
2334 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2336 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2340 case nir_op_f2u16
: {
2341 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2342 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2343 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2344 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2345 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2347 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2349 if (dst
.type() == RegType::vgpr
)
2350 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2352 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2355 case nir_op_f2i32
: {
2356 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2357 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2358 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2359 if (dst
.type() == RegType::vgpr
) {
2360 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2362 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2363 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2365 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2366 if (dst
.type() == RegType::vgpr
)
2367 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2369 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2370 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2372 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2373 if (dst
.type() == RegType::vgpr
)
2374 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2376 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2377 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2380 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2381 nir_print_instr(&instr
->instr
, stderr
);
2382 fprintf(stderr
, "\n");
2386 case nir_op_f2u32
: {
2387 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2388 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2389 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2390 if (dst
.type() == RegType::vgpr
) {
2391 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2393 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2394 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2396 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2397 if (dst
.type() == RegType::vgpr
)
2398 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2400 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2401 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2403 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2404 if (dst
.type() == RegType::vgpr
)
2405 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2407 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2408 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2411 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2412 nir_print_instr(&instr
->instr
, stderr
);
2413 fprintf(stderr
, "\n");
2417 case nir_op_f2i64
: {
2418 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2419 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2420 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2422 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2423 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2424 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2425 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2426 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2427 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2428 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2429 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2430 Temp new_exponent
= bld
.tmp(v1
);
2431 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2432 if (ctx
->program
->chip_class
>= GFX8
)
2433 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2435 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2436 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2437 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2438 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2439 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2440 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2441 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2442 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2443 Temp new_lower
= bld
.tmp(v1
);
2444 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2445 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2446 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2448 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2449 if (src
.type() == RegType::vgpr
)
2450 src
= bld
.as_uniform(src
);
2451 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2452 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2453 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2454 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2455 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2456 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2457 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2458 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2459 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2460 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2461 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2462 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2463 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2464 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2465 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2466 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2467 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2468 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2469 Temp borrow
= bld
.tmp(s1
);
2470 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2471 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2472 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2474 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2475 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2476 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2477 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2478 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2479 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2480 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2481 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2482 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2483 if (dst
.type() == RegType::sgpr
) {
2484 lower
= bld
.as_uniform(lower
);
2485 upper
= bld
.as_uniform(upper
);
2487 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2491 nir_print_instr(&instr
->instr
, stderr
);
2492 fprintf(stderr
, "\n");
2496 case nir_op_f2u64
: {
2497 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2498 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2499 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2501 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2502 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2503 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2504 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2505 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2506 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2507 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2508 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2509 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2510 Temp new_exponent
= bld
.tmp(v1
);
2511 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2512 if (ctx
->program
->chip_class
>= GFX8
)
2513 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2515 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2516 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2517 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2518 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2519 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2520 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2521 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2522 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2524 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2525 if (src
.type() == RegType::vgpr
)
2526 src
= bld
.as_uniform(src
);
2527 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2528 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2529 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2530 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2531 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2532 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2533 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2534 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2535 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2536 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2537 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2538 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2539 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2540 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2541 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2542 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2543 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2544 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2546 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2547 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2548 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2549 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2550 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2551 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2552 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2553 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2554 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2555 if (dst
.type() == RegType::sgpr
) {
2556 lower
= bld
.as_uniform(lower
);
2557 upper
= bld
.as_uniform(upper
);
2559 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2562 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2563 nir_print_instr(&instr
->instr
, stderr
);
2564 fprintf(stderr
, "\n");
2568 case nir_op_b2f16
: {
2569 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2570 assert(src
.regClass() == bld
.lm
);
2572 if (dst
.regClass() == s1
) {
2573 src
= bool_to_scalar_condition(ctx
, src
);
2574 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2575 } else if (dst
.regClass() == v2b
) {
2576 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2577 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2578 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2580 unreachable("Wrong destination register class for nir_op_b2f16.");
2584 case nir_op_b2f32
: {
2585 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2586 assert(src
.regClass() == bld
.lm
);
2588 if (dst
.regClass() == s1
) {
2589 src
= bool_to_scalar_condition(ctx
, src
);
2590 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2591 } else if (dst
.regClass() == v1
) {
2592 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2594 unreachable("Wrong destination register class for nir_op_b2f32.");
2598 case nir_op_b2f64
: {
2599 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2600 assert(src
.regClass() == bld
.lm
);
2602 if (dst
.regClass() == s2
) {
2603 src
= bool_to_scalar_condition(ctx
, src
);
2604 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2605 } else if (dst
.regClass() == v2
) {
2606 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2607 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2608 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2610 unreachable("Wrong destination register class for nir_op_b2f64.");
2617 case nir_op_i2i64
: {
2618 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2619 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2625 case nir_op_u2u64
: {
2626 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2627 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2631 case nir_op_b2i32
: {
2632 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2633 assert(src
.regClass() == bld
.lm
);
2635 if (dst
.regClass() == s1
) {
2636 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2637 bool_to_scalar_condition(ctx
, src
, dst
);
2638 } else if (dst
.regClass() == v1
) {
2639 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2641 unreachable("Invalid register class for b2i32");
2647 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2648 assert(dst
.regClass() == bld
.lm
);
2650 if (src
.type() == RegType::vgpr
) {
2651 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2652 assert(dst
.regClass() == bld
.lm
);
2653 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2654 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2656 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2658 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2659 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2661 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2662 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2664 bool_to_vector_condition(ctx
, tmp
, dst
);
2668 case nir_op_pack_64_2x32_split
: {
2669 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2670 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2672 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2675 case nir_op_unpack_64_2x32_split_x
:
2676 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2678 case nir_op_unpack_64_2x32_split_y
:
2679 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2681 case nir_op_unpack_32_2x16_split_x
:
2682 if (dst
.type() == RegType::vgpr
) {
2683 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2685 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2688 case nir_op_unpack_32_2x16_split_y
:
2689 if (dst
.type() == RegType::vgpr
) {
2690 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2692 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2695 case nir_op_pack_32_2x16_split
: {
2696 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2697 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2698 if (dst
.regClass() == v1
) {
2699 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2700 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2701 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2703 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2704 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2705 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2709 case nir_op_pack_half_2x16
: {
2710 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2712 if (dst
.regClass() == v1
) {
2713 Temp src0
= bld
.tmp(v1
);
2714 Temp src1
= bld
.tmp(v1
);
2715 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2716 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2717 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2719 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2720 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2721 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2723 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2724 nir_print_instr(&instr
->instr
, stderr
);
2725 fprintf(stderr
, "\n");
2729 case nir_op_unpack_half_2x16_split_x
: {
2730 if (dst
.regClass() == v1
) {
2731 Builder
bld(ctx
->program
, ctx
->block
);
2732 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2734 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2735 nir_print_instr(&instr
->instr
, stderr
);
2736 fprintf(stderr
, "\n");
2740 case nir_op_unpack_half_2x16_split_y
: {
2741 if (dst
.regClass() == v1
) {
2742 Builder
bld(ctx
->program
, ctx
->block
);
2743 /* TODO: use SDWA here */
2744 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2745 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2747 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2748 nir_print_instr(&instr
->instr
, stderr
);
2749 fprintf(stderr
, "\n");
2753 case nir_op_fquantize2f16
: {
2754 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2755 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2758 if (ctx
->program
->chip_class
>= GFX8
) {
2759 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2760 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2761 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2763 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2764 * so compare the result and flush to 0 if it's smaller.
2766 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2767 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2768 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2769 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2770 cmp_res
= vop3
->definitions
[0].getTemp();
2773 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2774 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2775 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2777 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2782 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2783 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2785 if (dst
.regClass() == s1
) {
2786 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2787 } else if (dst
.regClass() == v1
) {
2788 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2791 nir_print_instr(&instr
->instr
, stderr
);
2792 fprintf(stderr
, "\n");
2796 case nir_op_bitfield_select
: {
2797 /* (mask & insert) | (~mask & base) */
2798 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2799 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2800 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2802 /* dst = (insert & bitmask) | (base & ~bitmask) */
2803 if (dst
.regClass() == s1
) {
2804 aco_ptr
<Instruction
> sop2
;
2805 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2806 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2808 if (const_insert
&& const_bitmask
) {
2809 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2811 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2812 lhs
= Operand(insert
);
2816 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2817 if (const_base
&& const_bitmask
) {
2818 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2820 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2821 rhs
= Operand(base
);
2824 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2826 } else if (dst
.regClass() == v1
) {
2827 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2828 base
= as_vgpr(ctx
, base
);
2829 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2830 insert
= as_vgpr(ctx
, insert
);
2832 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2835 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2836 nir_print_instr(&instr
->instr
, stderr
);
2837 fprintf(stderr
, "\n");
2843 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2844 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2845 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2847 if (dst
.type() == RegType::sgpr
) {
2849 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2850 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2851 if (const_offset
&& const_bits
) {
2852 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2853 extract
= Operand(const_extract
);
2857 width
= Operand(const_bits
->u32
<< 16);
2859 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2861 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2865 if (dst
.regClass() == s1
) {
2866 if (instr
->op
== nir_op_ubfe
)
2867 opcode
= aco_opcode::s_bfe_u32
;
2869 opcode
= aco_opcode::s_bfe_i32
;
2870 } else if (dst
.regClass() == s2
) {
2871 if (instr
->op
== nir_op_ubfe
)
2872 opcode
= aco_opcode::s_bfe_u64
;
2874 opcode
= aco_opcode::s_bfe_i64
;
2876 unreachable("Unsupported BFE bit size");
2879 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2883 if (dst
.regClass() == v1
) {
2884 if (instr
->op
== nir_op_ubfe
)
2885 opcode
= aco_opcode::v_bfe_u32
;
2887 opcode
= aco_opcode::v_bfe_i32
;
2889 unreachable("Unsupported BFE bit size");
2892 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2896 case nir_op_bit_count
: {
2897 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2898 if (src
.regClass() == s1
) {
2899 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2900 } else if (src
.regClass() == v1
) {
2901 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2902 } else if (src
.regClass() == v2
) {
2903 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2904 emit_extract_vector(ctx
, src
, 1, v1
),
2905 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2906 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2907 } else if (src
.regClass() == s2
) {
2908 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2910 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2911 nir_print_instr(&instr
->instr
, stderr
);
2912 fprintf(stderr
, "\n");
2917 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2921 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2925 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2929 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2933 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2937 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2941 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2942 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2944 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2945 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2949 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2950 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2952 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2953 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2957 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2961 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2966 case nir_op_fddx_fine
:
2967 case nir_op_fddy_fine
:
2968 case nir_op_fddx_coarse
:
2969 case nir_op_fddy_coarse
: {
2970 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2971 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2972 if (instr
->op
== nir_op_fddx_fine
) {
2973 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2974 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2975 } else if (instr
->op
== nir_op_fddy_fine
) {
2976 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2977 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2979 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2980 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2981 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2983 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2987 if (ctx
->program
->chip_class
>= GFX8
) {
2988 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2989 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2991 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2992 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2993 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2995 emit_wqm(ctx
, tmp
, dst
, true);
2999 fprintf(stderr
, "Unknown NIR ALU instr: ");
3000 nir_print_instr(&instr
->instr
, stderr
);
3001 fprintf(stderr
, "\n");
3005 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3007 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3009 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3010 // which get truncated the lsb if double and msb if int
3011 // for now, we only use s_mov_b64 with 64bit inline constants
3012 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3013 assert(dst
.type() == RegType::sgpr
);
3015 Builder
bld(ctx
->program
, ctx
->block
);
3017 if (instr
->def
.bit_size
== 1) {
3018 assert(dst
.regClass() == bld
.lm
);
3019 int val
= instr
->value
[0].b
? -1 : 0;
3020 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3021 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3022 } else if (instr
->def
.bit_size
== 8) {
3023 /* ensure that the value is correctly represented in the low byte of the register */
3024 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3025 } else if (instr
->def
.bit_size
== 16) {
3026 /* ensure that the value is correctly represented in the low half of the register */
3027 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3028 } else if (dst
.size() == 1) {
3029 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3031 assert(dst
.size() != 1);
3032 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3033 if (instr
->def
.bit_size
== 64)
3034 for (unsigned i
= 0; i
< dst
.size(); i
++)
3035 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3037 for (unsigned i
= 0; i
< dst
.size(); i
++)
3038 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3040 vec
->definitions
[0] = Definition(dst
);
3041 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3045 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3047 uint32_t new_mask
= 0;
3048 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3049 if (mask
& (1u << i
))
3050 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3054 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3056 Builder
bld(ctx
->program
, ctx
->block
);
3057 if (offset
.isTemp()) {
3058 Temp tmp
[3] = {vec
, vec
, vec
};
3060 if (vec
.size() == 3) {
3061 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3062 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3063 } else if (vec
.size() == 2) {
3064 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3065 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3067 for (unsigned i
= 0; i
< dst
.size(); i
++)
3068 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3071 if (dst
.size() == 2)
3072 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3074 offset
= Operand(0u);
3077 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3078 bld
.copy(Definition(dst
), vec
);
3080 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3083 struct LoadEmitInfo
{
3086 unsigned num_components
;
3087 unsigned component_size
;
3088 Temp resource
= Temp(0, s1
);
3089 unsigned component_stride
= 0;
3090 unsigned const_offset
= 0;
3091 unsigned align_mul
= 0;
3092 unsigned align_offset
= 0;
3095 unsigned swizzle_component_size
= 0;
3096 barrier_interaction barrier
= barrier_none
;
3097 bool can_reorder
= true;
3098 Temp soffset
= Temp(0, s1
);
3101 using LoadCallback
= Temp(*)(
3102 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3103 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3105 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3106 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3108 unsigned load_size
= info
->num_components
* info
->component_size
;
3109 unsigned component_size
= info
->component_size
;
3111 unsigned num_vals
= 0;
3112 Temp vals
[info
->dst
.bytes()];
3114 unsigned const_offset
= info
->const_offset
;
3116 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3117 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3119 unsigned bytes_read
= 0;
3120 while (bytes_read
< load_size
) {
3121 unsigned bytes_needed
= load_size
- bytes_read
;
3123 /* add buffer for unaligned loads */
3124 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3127 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3128 if (info
->component_stride
) {
3129 assert(supports_8bit_16bit_loads
&& "unimplemented");
3133 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3134 bytes_needed
= align(bytes_needed
, 4);
3141 if (info
->swizzle_component_size
)
3142 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3143 if (info
->component_stride
)
3144 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3146 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3148 /* reduce constant offset */
3149 Operand offset
= info
->offset
;
3150 unsigned reduced_const_offset
= const_offset
;
3151 bool remove_const_offset_completely
= need_to_align_offset
;
3152 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3153 unsigned to_add
= const_offset
;
3154 if (remove_const_offset_completely
) {
3155 reduced_const_offset
= 0;
3157 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3158 reduced_const_offset
%= max_const_offset_plus_one
;
3160 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3161 if (offset
.isConstant()) {
3162 offset
= Operand(offset
.constantValue() + to_add
);
3163 } else if (offset_tmp
.regClass() == s1
) {
3164 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3165 offset_tmp
, Operand(to_add
));
3166 } else if (offset_tmp
.regClass() == v1
) {
3167 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3169 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3170 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3171 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3173 if (offset_tmp
.regClass() == s2
) {
3174 Temp carry
= bld
.tmp(s1
);
3175 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3176 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3177 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3179 Temp new_lo
= bld
.tmp(v1
);
3180 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3181 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3182 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3187 /* align offset down if needed */
3188 Operand aligned_offset
= offset
;
3189 if (need_to_align_offset
) {
3190 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3191 if (offset
.isConstant()) {
3192 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3193 } else if (offset_tmp
.regClass() == s1
) {
3194 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3195 } else if (offset_tmp
.regClass() == s2
) {
3196 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3197 } else if (offset_tmp
.regClass() == v1
) {
3198 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3199 } else if (offset_tmp
.regClass() == v2
) {
3200 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3201 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3202 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3203 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3206 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3207 bld
.copy(bld
.def(s1
), aligned_offset
);
3209 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3210 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3211 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3213 /* shift result right if needed */
3215 Operand
align((uint32_t)byte_align
);
3216 if (byte_align
== -1) {
3217 if (offset
.isConstant())
3218 align
= Operand(offset
.constantValue() % 4u);
3219 else if (offset
.size() == 2)
3220 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3225 if (align
.isTemp() || align
.constantValue()) {
3226 assert(val
.bytes() >= load_size
&& "unimplemented");
3227 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3228 if (val
.type() == RegType::sgpr
)
3229 byte_align_scalar(ctx
, val
, align
, new_val
);
3231 byte_align_vector(ctx
, val
, align
, new_val
);
3236 /* add result to list and advance */
3237 if (info
->component_stride
) {
3238 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3239 const_offset
+= info
->component_stride
;
3240 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3242 const_offset
+= val
.bytes();
3243 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3245 bytes_read
+= val
.bytes();
3246 vals
[num_vals
++] = val
;
3249 /* the callback wrote directly to dst */
3250 if (vals
[0] == info
->dst
) {
3251 assert(num_vals
== 1);
3252 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3256 /* create array of components */
3257 unsigned components_split
= 0;
3258 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3259 bool has_vgprs
= false;
3260 for (unsigned i
= 0; i
< num_vals
;) {
3262 unsigned num_tmps
= 0;
3263 unsigned tmp_size
= 0;
3264 RegType reg_type
= RegType::sgpr
;
3265 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3266 if (vals
[i
].type() == RegType::vgpr
)
3267 reg_type
= RegType::vgpr
;
3268 tmp_size
+= vals
[i
].bytes();
3269 tmp
[num_tmps
++] = vals
[i
++];
3272 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3273 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3274 for (unsigned i
= 0; i
< num_vals
; i
++)
3275 vec
->operands
[i
] = Operand(tmp
[i
]);
3276 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3277 vec
->definitions
[0] = Definition(tmp
[0]);
3278 bld
.insert(std::move(vec
));
3281 if (tmp
[0].bytes() % component_size
) {
3283 assert(i
== num_vals
);
3284 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3285 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3288 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3290 unsigned start
= components_split
;
3292 if (tmp_size
== elem_rc
.bytes()) {
3293 allocated_vec
[components_split
++] = tmp
[0];
3295 assert(tmp_size
% elem_rc
.bytes() == 0);
3296 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3297 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3298 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3299 Temp component
= bld
.tmp(elem_rc
);
3300 allocated_vec
[components_split
++] = component
;
3301 split
->definitions
[i
] = Definition(component
);
3303 split
->operands
[0] = Operand(tmp
[0]);
3304 bld
.insert(std::move(split
));
3307 /* try to p_as_uniform early so we can create more optimizable code and
3308 * also update allocated_vec */
3309 for (unsigned j
= start
; j
< components_split
; j
++) {
3310 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3311 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3312 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3316 /* concatenate components and p_as_uniform() result if needed */
3317 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3318 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3320 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3322 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3323 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3324 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3325 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3327 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3328 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3329 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3330 vec
->definitions
[0] = Definition(tmp
);
3331 bld
.insert(std::move(vec
));
3332 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3334 vec
->definitions
[0] = Definition(info
->dst
);
3335 bld
.insert(std::move(vec
));
3339 Operand
load_lds_size_m0(Builder
& bld
)
3341 /* TODO: m0 does not need to be initialized on GFX9+ */
3342 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3345 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3346 Temp offset
, unsigned bytes_needed
,
3347 unsigned align
, unsigned const_offset
,
3350 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3352 Operand m
= load_lds_size_m0(bld
);
3354 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3355 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3360 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3361 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3363 op
= aco_opcode::ds_read_b128
;
3364 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3367 op
= aco_opcode::ds_read2_b64
;
3368 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3370 op
= aco_opcode::ds_read_b96
;
3371 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3373 op
= aco_opcode::ds_read_b64
;
3374 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3377 op
= aco_opcode::ds_read2_b32
;
3378 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3380 op
= aco_opcode::ds_read_b32
;
3381 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3383 op
= aco_opcode::ds_read_u16
;
3386 op
= aco_opcode::ds_read_u8
;
3389 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3390 if (const_offset
>= max_offset_plus_one
) {
3391 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3392 const_offset
%= max_offset_plus_one
;
3396 const_offset
/= (size
/ 2u);
3398 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3399 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3401 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3403 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3406 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3411 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3413 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3414 Temp offset
, unsigned bytes_needed
,
3415 unsigned align
, unsigned const_offset
,
3420 if (bytes_needed
<= 4) {
3422 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3423 } else if (bytes_needed
<= 8) {
3425 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3426 } else if (bytes_needed
<= 16) {
3428 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3429 } else if (bytes_needed
<= 32) {
3431 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3434 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3436 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3437 if (info
->resource
.id()) {
3438 load
->operands
[0] = Operand(info
->resource
);
3439 load
->operands
[1] = Operand(offset
);
3441 load
->operands
[0] = Operand(offset
);
3442 load
->operands
[1] = Operand(0u);
3444 RegClass
rc(RegType::sgpr
, size
);
3445 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3446 load
->definitions
[0] = Definition(val
);
3447 load
->glc
= info
->glc
;
3448 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3449 load
->barrier
= info
->barrier
;
3450 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3451 bld
.insert(std::move(load
));
3455 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3457 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3458 Temp offset
, unsigned bytes_needed
,
3459 unsigned align_
, unsigned const_offset
,
3462 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3463 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3465 if (info
->soffset
.id()) {
3466 if (soffset
.isTemp())
3467 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3468 soffset
= Operand(info
->soffset
);
3471 unsigned bytes_size
= 0;
3473 if (bytes_needed
== 1) {
3475 op
= aco_opcode::buffer_load_ubyte
;
3476 } else if (bytes_needed
== 2) {
3478 op
= aco_opcode::buffer_load_ushort
;
3479 } else if (bytes_needed
<= 4) {
3481 op
= aco_opcode::buffer_load_dword
;
3482 } else if (bytes_needed
<= 8) {
3484 op
= aco_opcode::buffer_load_dwordx2
;
3485 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3487 op
= aco_opcode::buffer_load_dwordx3
;
3490 op
= aco_opcode::buffer_load_dwordx4
;
3492 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3493 mubuf
->operands
[0] = Operand(info
->resource
);
3494 mubuf
->operands
[1] = vaddr
;
3495 mubuf
->operands
[2] = soffset
;
3496 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3497 mubuf
->glc
= info
->glc
;
3498 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3499 mubuf
->barrier
= info
->barrier
;
3500 mubuf
->can_reorder
= info
->can_reorder
;
3501 mubuf
->offset
= const_offset
;
3502 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3503 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3504 mubuf
->definitions
[0] = Definition(val
);
3505 bld
.insert(std::move(mubuf
));
3508 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3513 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3515 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3517 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3518 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3520 if (addr
.type() == RegType::vgpr
)
3521 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3522 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3525 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3526 Temp offset
, unsigned bytes_needed
,
3527 unsigned align_
, unsigned const_offset
,
3530 unsigned bytes_size
= 0;
3531 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3532 bool global
= bld
.program
->chip_class
>= GFX9
;
3534 if (bytes_needed
== 1) {
3536 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3537 } else if (bytes_needed
== 2) {
3539 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3540 } else if (bytes_needed
<= 4) {
3542 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3543 } else if (bytes_needed
<= 8) {
3545 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3546 } else if (bytes_needed
<= 12 && !mubuf
) {
3548 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3551 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3553 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3554 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3556 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3557 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3558 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3559 mubuf
->operands
[2] = Operand(0u);
3560 mubuf
->glc
= info
->glc
;
3563 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3564 mubuf
->disable_wqm
= false;
3565 mubuf
->barrier
= info
->barrier
;
3566 mubuf
->definitions
[0] = Definition(val
);
3567 bld
.insert(std::move(mubuf
));
3569 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3571 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3572 flat
->operands
[0] = Operand(offset
);
3573 flat
->operands
[1] = Operand(s1
);
3574 flat
->glc
= info
->glc
;
3575 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3576 flat
->barrier
= info
->barrier
;
3578 flat
->definitions
[0] = Definition(val
);
3579 bld
.insert(std::move(flat
));
3583 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3588 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3590 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3591 Temp address
, unsigned base_offset
, unsigned align
)
3593 assert(util_is_power_of_two_nonzero(align
));
3595 Builder
bld(ctx
->program
, ctx
->block
);
3597 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3598 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3599 info
.align_mul
= align
;
3600 info
.align_offset
= 0;
3601 info
.barrier
= barrier_shared
;
3602 info
.can_reorder
= false;
3603 info
.const_offset
= base_offset
;
3604 emit_lds_load(ctx
, bld
, &info
);
3609 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3611 if (start
== 0 && size
== data
.size())
3612 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3614 unsigned size_hint
= 1;
3615 auto it
= ctx
->allocated_vec
.find(data
.id());
3616 if (it
!= ctx
->allocated_vec
.end())
3617 size_hint
= it
->second
[0].size();
3618 if (size
% size_hint
|| start
% size_hint
)
3625 for (unsigned i
= 0; i
< size
; i
++)
3626 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3629 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3631 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3632 for (unsigned i
= 0; i
< size
; i
++)
3633 vec
->operands
[i
] = Operand(elems
[i
]);
3634 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3635 vec
->definitions
[0] = Definition(res
);
3636 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3640 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3642 Builder
bld(ctx
->program
, ctx
->block
);
3643 unsigned bytes_written
= 0;
3644 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3645 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3647 while (bytes_written
< total_size
* 4) {
3648 unsigned todo
= total_size
* 4 - bytes_written
;
3649 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3650 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3652 aco_opcode op
= aco_opcode::last_opcode
;
3653 bool write2
= false;
3655 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3656 op
= aco_opcode::ds_write_b128
;
3658 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3659 op
= aco_opcode::ds_write2_b64
;
3662 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3663 op
= aco_opcode::ds_write_b96
;
3665 } else if (todo
>= 8 && aligned8
) {
3666 op
= aco_opcode::ds_write_b64
;
3668 } else if (todo
>= 8 && usable_write2
) {
3669 op
= aco_opcode::ds_write2_b32
;
3672 } else if (todo
>= 4) {
3673 op
= aco_opcode::ds_write_b32
;
3679 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3680 unsigned max_offset
= write2
? 1020 : 65535;
3681 Temp address_offset
= address
;
3682 if (offset
> max_offset
) {
3683 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3684 offset
= offset1
+ bytes_written
;
3686 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3689 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3690 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3691 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3693 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3694 bld
.ds(op
, address_offset
, val
, m
, offset
);
3697 bytes_written
+= size
* 4;
3701 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3706 Builder
bld(ctx
->program
, ctx
->block
);
3708 ASSERTED
bool is_subdword
= false;
3709 for (unsigned i
= 0; i
< count
; i
++)
3710 is_subdword
|= offsets
[i
] % 4;
3711 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3712 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3714 /* count == 1 fast path */
3716 if (dst_type
== RegType::sgpr
)
3717 dst
[0] = bld
.as_uniform(src
);
3719 dst
[0] = as_vgpr(ctx
, src
);
3723 for (unsigned i
= 0; i
< count
- 1; i
++)
3724 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3725 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3727 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3728 src
= as_vgpr(ctx
, src
);
3730 /* use allocated_vec if possible */
3731 auto it
= ctx
->allocated_vec
.find(src
.id());
3732 if (it
!= ctx
->allocated_vec
.end()) {
3733 unsigned total_size
= 0;
3734 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3735 total_size
+= it
->second
[i
].bytes();
3736 if (total_size
!= src
.bytes())
3739 unsigned elem_size
= it
->second
[0].bytes();
3741 for (unsigned i
= 0; i
< count
; i
++) {
3742 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3746 for (unsigned i
= 0; i
< count
; i
++) {
3747 unsigned start_idx
= offsets
[i
] / elem_size
;
3748 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3749 if (op_count
== 1) {
3750 if (dst_type
== RegType::sgpr
)
3751 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3753 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3757 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3758 for (unsigned j
= 0; j
< op_count
; j
++) {
3759 Temp tmp
= it
->second
[start_idx
+ j
];
3760 if (dst_type
== RegType::sgpr
)
3761 tmp
= bld
.as_uniform(tmp
);
3762 vec
->operands
[j
] = Operand(tmp
);
3764 vec
->definitions
[0] = Definition(dst
[i
]);
3765 bld
.insert(std::move(vec
));
3771 if (dst_type
== RegType::sgpr
)
3772 src
= bld
.as_uniform(src
);
3776 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3777 split
->operands
[0] = Operand(src
);
3778 for (unsigned i
= 0; i
< count
; i
++)
3779 split
->definitions
[i
] = Definition(dst
[i
]);
3780 bld
.insert(std::move(split
));
3783 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3784 int *start
, int *count
)
3786 unsigned start_elem
= ffs(todo_mask
) - 1;
3787 bool skip
= !(mask
& (1 << start_elem
));
3789 mask
= ~mask
& todo_mask
;
3793 u_bit_scan_consecutive_range(&mask
, start
, count
);
3798 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3800 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3803 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3804 Temp address
, unsigned base_offset
, unsigned align
)
3806 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3807 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3809 Builder
bld(ctx
->program
, ctx
->block
);
3810 Operand m
= load_lds_size_m0(bld
);
3812 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3813 assert(wrmask
<= 0x0f);
3814 int start
[2], count
[2];
3815 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3816 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3817 assert(wrmask
== 0);
3819 /* one combined store is sufficient */
3820 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3821 Temp address_offset
= address
;
3822 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3823 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3827 assert(count
[0] == 1);
3828 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3830 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3831 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3832 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3833 base_offset
= base_offset
/ elem_size_bytes
;
3834 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3835 base_offset
+ start
[0], base_offset
+ start
[1]);
3839 for (unsigned i
= 0; i
< 2; i
++) {
3843 unsigned elem_size_words
= elem_size_bytes
/ 4;
3844 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3845 base_offset
, start
[i
] * elem_size_bytes
, align
);
3850 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3852 unsigned align
= 16;
3854 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3860 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3861 Temp data
, unsigned writemask
, int swizzle_element_size
,
3862 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3864 unsigned write_count_with_skips
= 0;
3867 /* determine how to split the data */
3868 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3871 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3872 offsets
[write_count_with_skips
] = offset
;
3873 if (skips
[write_count_with_skips
]) {
3874 advance_write_mask(&todo
, offset
, bytes
);
3875 write_count_with_skips
++;
3879 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3880 * larger than swizzle_element_size */
3881 bytes
= MIN2(bytes
, swizzle_element_size
);
3883 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3885 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3886 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3889 /* dword or larger stores have to be dword-aligned */
3890 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3891 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3892 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3893 if (bytes
>= 4 && !dword_aligned
)
3894 bytes
= MIN2(bytes
, 2);
3896 advance_write_mask(&todo
, offset
, bytes
);
3897 write_count_with_skips
++;
3900 /* actually split data */
3901 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3904 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3907 write_datas
[*write_count
] = write_datas
[i
];
3908 offsets
[*write_count
] = offsets
[i
];
3913 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3914 unsigned split_cnt
= 0u, Temp dst
= Temp())
3916 Builder
bld(ctx
->program
, ctx
->block
);
3917 unsigned dword_size
= elem_size_bytes
/ 4;
3920 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3922 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3923 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3924 instr
->definitions
[0] = Definition(dst
);
3926 for (unsigned i
= 0; i
< cnt
; ++i
) {
3928 assert(arr
[i
].size() == dword_size
);
3929 allocated_vec
[i
] = arr
[i
];
3930 instr
->operands
[i
] = Operand(arr
[i
]);
3932 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3933 allocated_vec
[i
] = zero
;
3934 instr
->operands
[i
] = Operand(zero
);
3938 bld
.insert(std::move(instr
));
3941 emit_split_vector(ctx
, dst
, split_cnt
);
3943 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3948 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3950 if (const_offset
>= 4096) {
3951 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3952 const_offset
%= 4096u;
3955 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3956 else if (unlikely(voffset
.regClass() == s1
))
3957 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3958 else if (likely(voffset
.regClass() == v1
))
3959 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3961 unreachable("Unsupported register class of voffset");
3964 return const_offset
;
3967 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3968 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3971 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3972 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3974 Builder
bld(ctx
->program
, ctx
->block
);
3975 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3976 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3978 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3979 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3980 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3981 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3982 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3984 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3987 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3988 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3989 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3991 Builder
bld(ctx
->program
, ctx
->block
);
3992 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3995 if (elem_size_bytes
== 8) {
3996 elem_size_bytes
= 4;
3997 write_mask
= widen_mask(write_mask
, 2);
4000 while (write_mask
) {
4003 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
4008 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
4009 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
4011 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
4012 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
4015 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
4016 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
4026 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
4027 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
4028 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
4030 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
4031 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
4032 assert(!!stride
!= allow_combining
);
4034 Builder
bld(ctx
->program
, ctx
->block
);
4036 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
4037 info
.component_stride
= allow_combining
? 0 : stride
;
4039 info
.swizzle_component_size
= allow_combining
? 0 : 4;
4040 info
.align_mul
= MIN2(elem_size_bytes
, 4);
4041 info
.align_offset
= 0;
4042 info
.soffset
= soffset
;
4043 info
.const_offset
= base_const_offset
;
4044 emit_mubuf_load(ctx
, bld
, &info
);
4047 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4049 Builder
bld(ctx
->program
, ctx
->block
);
4050 Temp offset
= base_offset
.first
;
4051 unsigned const_offset
= base_offset
.second
;
4053 if (!nir_src_is_const(*off_src
)) {
4054 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4057 /* Calculate indirect offset with stride */
4058 if (likely(indirect_offset_arg
.regClass() == v1
))
4059 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4060 else if (indirect_offset_arg
.regClass() == s1
)
4061 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4063 unreachable("Unsupported register class of indirect offset");
4065 /* Add to the supplied base offset */
4066 if (offset
.id() == 0)
4067 offset
= with_stride
;
4068 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4069 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4070 else if (offset
.size() == 1 && with_stride
.size() == 1)
4071 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4073 unreachable("Unsupported register class of indirect offset");
4075 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4076 const_offset
+= const_offset_arg
* stride
;
4079 return std::make_pair(offset
, const_offset
);
4082 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4084 Builder
bld(ctx
->program
, ctx
->block
);
4087 if (off1
.first
.id() && off2
.first
.id()) {
4088 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4089 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4090 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4091 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4093 unreachable("Unsupported register class of indirect offset");
4095 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4098 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4101 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4103 Builder
bld(ctx
->program
, ctx
->block
);
4104 unsigned const_offset
= offs
.second
* multiplier
;
4106 if (!offs
.first
.id())
4107 return std::make_pair(offs
.first
, const_offset
);
4109 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4110 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4111 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4113 return std::make_pair(offset
, const_offset
);
4116 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4118 Builder
bld(ctx
->program
, ctx
->block
);
4120 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4121 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4122 /* component is in bytes */
4123 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4125 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4126 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4127 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4130 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4132 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4135 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4137 Builder
bld(ctx
->program
, ctx
->block
);
4139 switch (ctx
->shader
->info
.stage
) {
4140 case MESA_SHADER_TESS_CTRL
:
4141 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4142 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4143 case MESA_SHADER_TESS_EVAL
:
4144 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4146 unreachable("Unsupported stage in get_tess_rel_patch_id");
4150 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4152 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4153 Builder
bld(ctx
->program
, ctx
->block
);
4155 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4156 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4158 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4160 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4161 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4163 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4164 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4165 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4167 return offset_mul(ctx
, offs
, 4u);
4170 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4172 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4173 Builder
bld(ctx
->program
, ctx
->block
);
4175 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4176 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
4177 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
4178 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
4179 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4180 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
4182 std::pair
<Temp
, unsigned> offs
= instr
4183 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4184 : std::make_pair(Temp(), 0u);
4186 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4187 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4192 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4193 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4195 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4196 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4198 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4199 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4205 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4207 Builder
bld(ctx
->program
, ctx
->block
);
4209 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4210 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4212 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4214 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4215 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4216 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4218 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4219 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4224 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4226 Builder
bld(ctx
->program
, ctx
->block
);
4228 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
4229 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
4230 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
4232 unsigned output_vertex_size
= num_tcs_outputs
* 16;
4233 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4234 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4235 unsigned attr_stride
= ctx
->tcs_num_patches
;
4237 std::pair
<Temp
, unsigned> offs
= instr
4238 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4239 : std::make_pair(Temp(), 0u);
4241 if (const_base_offset
)
4242 offs
.second
+= const_base_offset
* attr_stride
;
4244 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4245 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4246 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4251 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4256 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4257 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4259 if (!nir_src_is_const(*off_src
)) {
4265 off
+= nir_src_as_uint(*off_src
) * 16u;
4268 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
4269 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
4276 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4278 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4279 unsigned component
= nir_intrinsic_component(instr
);
4280 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4282 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4283 if (off_instr
->type
!= nir_instr_type_load_const
)
4286 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4287 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4289 if (instr
->src
[0].ssa
->bit_size
== 64)
4290 write_mask
= widen_mask(write_mask
, 2);
4292 for (unsigned i
= 0; i
< 8; ++i
) {
4293 if (write_mask
& (1 << i
)) {
4294 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4295 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
4303 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4305 /* Only TCS per-vertex inputs are supported by this function.
4306 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4308 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4311 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4312 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4313 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4314 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4315 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4316 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4321 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4322 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4323 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4328 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4330 Builder
bld(ctx
->program
, ctx
->block
);
4332 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4333 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4334 bool indirect_write
;
4335 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4336 if (temp_only_input
&& !indirect_write
)
4340 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4341 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4342 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4343 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4345 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4346 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4347 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4348 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4349 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4353 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4354 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4355 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4356 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4357 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4358 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4359 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4360 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4361 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4362 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4363 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4364 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4365 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4367 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
4368 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4369 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
4371 unreachable("Invalid LS or ES stage");
4374 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4375 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4376 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4380 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4385 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4386 return off
== ctx
->tcs_tess_lvl_out_loc
||
4387 off
== ctx
->tcs_tess_lvl_in_loc
;
4391 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4393 uint64_t mask
= per_vertex
4394 ? ctx
->program
->info
->tcs
.tes_inputs_read
4395 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4397 bool indirect_write
= false;
4398 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4399 return indirect_write
|| output_read_by_tes
;
4402 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4404 uint64_t mask
= per_vertex
4405 ? ctx
->shader
->info
.outputs_read
4406 : ctx
->shader
->info
.patch_outputs_read
;
4408 bool indirect_write
= false;
4409 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4410 return indirect_write
|| output_read
;
4413 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4415 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4416 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4418 Builder
bld(ctx
->program
, ctx
->block
);
4420 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4421 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4422 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4424 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4425 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4426 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4428 if (write_to_vmem
) {
4429 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4430 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4431 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4433 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4434 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4435 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4439 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4440 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4441 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4445 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4447 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4448 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4450 Builder
bld(ctx
->program
, ctx
->block
);
4452 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4453 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4454 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4455 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4457 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4460 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4462 if (ctx
->stage
== vertex_vs
||
4463 ctx
->stage
== tess_eval_vs
||
4464 ctx
->stage
== fragment_fs
||
4465 ctx
->stage
== ngg_vertex_gs
||
4466 ctx
->stage
== ngg_tess_eval_gs
||
4467 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4468 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4469 if (!stored_to_temps
) {
4470 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4471 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4472 fprintf(stderr
, "\n");
4475 } else if (ctx
->stage
== vertex_es
||
4476 ctx
->stage
== vertex_ls
||
4477 ctx
->stage
== tess_eval_es
||
4478 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4479 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4480 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4481 visit_store_ls_or_es_output(ctx
, instr
);
4482 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4483 visit_store_tcs_output(ctx
, instr
, false);
4485 unreachable("Shader stage not implemented");
4489 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4491 visit_load_tcs_output(ctx
, instr
, false);
4494 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4496 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4497 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4499 Builder
bld(ctx
->program
, ctx
->block
);
4500 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
4501 if (ctx
->program
->has_16bank_lds
)
4502 interp_p1
.instr
->operands
[0].setLateKill(true);
4503 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4506 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4508 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4509 for (unsigned i
= 0; i
< num_components
; i
++)
4510 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4511 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4512 assert(num_components
== 4);
4513 Builder
bld(ctx
->program
, ctx
->block
);
4514 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4517 for (Operand
& op
: vec
->operands
)
4518 op
= op
.isUndefined() ? Operand(0u) : op
;
4520 vec
->definitions
[0] = Definition(dst
);
4521 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4522 emit_split_vector(ctx
, dst
, num_components
);
4526 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4528 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4529 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4530 unsigned idx
= nir_intrinsic_base(instr
);
4531 unsigned component
= nir_intrinsic_component(instr
);
4532 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4534 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4536 assert(offset
->u32
== 0);
4538 /* the lower 15bit of the prim_mask contain the offset into LDS
4539 * while the upper bits contain the number of prims */
4540 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4541 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4542 Builder
bld(ctx
->program
, ctx
->block
);
4543 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4544 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4545 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4546 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4547 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4550 if (instr
->dest
.ssa
.num_components
== 1) {
4551 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4553 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4554 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4556 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4557 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4558 vec
->operands
[i
] = Operand(tmp
);
4560 vec
->definitions
[0] = Definition(dst
);
4561 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4565 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4566 unsigned offset
, unsigned stride
, unsigned channels
)
4568 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4569 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4571 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4572 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4575 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4576 unsigned offset
, unsigned stride
, unsigned *channels
)
4578 if (!vtx_info
->chan_byte_size
) {
4579 *channels
= vtx_info
->num_channels
;
4580 return vtx_info
->chan_format
;
4583 unsigned num_channels
= *channels
;
4584 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4585 unsigned new_channels
= num_channels
+ 1;
4586 /* first, assume more loads is worse and try using a larger data format */
4587 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4589 /* don't make the attribute potentially out-of-bounds */
4590 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4594 if (new_channels
== 5) {
4595 /* then try decreasing load size (at the cost of more loads) */
4596 new_channels
= *channels
;
4597 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4601 if (new_channels
< *channels
)
4602 *channels
= new_channels
;
4603 num_channels
= new_channels
;
4606 switch (vtx_info
->chan_format
) {
4607 case V_008F0C_BUF_DATA_FORMAT_8
:
4608 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4609 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4610 case V_008F0C_BUF_DATA_FORMAT_16
:
4611 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4612 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4613 case V_008F0C_BUF_DATA_FORMAT_32
:
4614 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4615 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4617 unreachable("shouldn't reach here");
4618 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4621 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4622 * so we may need to fix it up. */
4623 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4625 Builder
bld(ctx
->program
, ctx
->block
);
4627 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4628 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4630 /* For the integer-like cases, do a natural sign extension.
4632 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4633 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4636 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4637 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4639 /* Convert back to the right type. */
4640 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4641 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4642 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4643 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4644 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4645 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4651 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4653 Builder
bld(ctx
->program
, ctx
->block
);
4654 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4655 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4657 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4658 if (off_instr
->type
!= nir_instr_type_load_const
) {
4659 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4660 nir_print_instr(off_instr
, stderr
);
4661 fprintf(stderr
, "\n");
4663 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4665 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4667 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4668 unsigned component
= nir_intrinsic_component(instr
);
4669 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4670 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4671 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4672 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4674 unsigned dfmt
= attrib_format
& 0xf;
4675 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4676 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4678 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4679 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4680 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4681 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4683 num_channels
= MAX2(num_channels
, 3);
4685 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4686 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4689 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4690 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4691 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4693 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4695 Temp divided
= bld
.tmp(v1
);
4696 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4697 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4699 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4702 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4705 index
= bld
.vadd32(bld
.def(v1
),
4706 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4707 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4710 Temp channels
[num_channels
];
4711 unsigned channel_start
= 0;
4712 bool direct_fetch
= false;
4714 /* skip unused channels at the start */
4715 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4716 channel_start
= ffs(mask
) - 1;
4717 for (unsigned i
= 0; i
< channel_start
; i
++)
4718 channels
[i
] = Temp(0, s1
);
4719 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4720 num_channels
= 3 - (ffs(mask
) - 1);
4724 while (channel_start
< num_channels
) {
4725 unsigned fetch_size
= num_channels
- channel_start
;
4726 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4727 bool expanded
= false;
4729 /* use MUBUF when possible to avoid possible alignment issues */
4730 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4731 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4732 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4733 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4734 vtx_info
->chan_byte_size
== 4;
4735 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4737 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4739 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4740 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4746 Temp fetch_index
= index
;
4747 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4748 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4749 fetch_offset
= fetch_offset
% attrib_stride
;
4752 Operand
soffset(0u);
4753 if (fetch_offset
>= 4096) {
4754 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4755 fetch_offset
%= 4096;
4759 switch (fetch_size
) {
4761 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4764 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4767 assert(ctx
->options
->chip_class
>= GFX7
||
4768 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4769 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4772 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4775 unreachable("Unimplemented load_input vector size");
4779 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4780 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4781 num_channels
<= 3)) {
4782 direct_fetch
= true;
4785 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4789 Instruction
*mubuf
= bld
.mubuf(opcode
,
4790 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4791 fetch_offset
, false, true).instr
;
4792 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4794 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4795 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4796 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4797 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4800 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4802 if (fetch_size
== 1) {
4803 channels
[channel_start
] = fetch_dst
;
4805 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4806 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4809 channel_start
+= fetch_size
;
4812 if (!direct_fetch
) {
4813 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4814 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4816 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4817 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4818 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4820 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4821 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4822 unsigned num_temp
= 0;
4823 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4824 unsigned idx
= i
+ component
;
4825 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4826 Temp channel
= channels
[swizzle
[idx
]];
4827 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4828 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4829 vec
->operands
[i
] = Operand(channel
);
4833 } else if (is_float
&& idx
== 3) {
4834 vec
->operands
[i
] = Operand(0x3f800000u
);
4835 } else if (!is_float
&& idx
== 3) {
4836 vec
->operands
[i
] = Operand(1u);
4838 vec
->operands
[i
] = Operand(0u);
4841 vec
->definitions
[0] = Definition(dst
);
4842 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4843 emit_split_vector(ctx
, dst
, dst
.size());
4845 if (num_temp
== dst
.size())
4846 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4848 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4849 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4850 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4851 if (off_instr
->type
!= nir_instr_type_load_const
||
4852 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4853 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4854 nir_print_instr(off_instr
, stderr
);
4855 fprintf(stderr
, "\n");
4858 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4859 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4861 assert(offset
->u32
== 0);
4863 /* the lower 15bit of the prim_mask contain the offset into LDS
4864 * while the upper bits contain the number of prims */
4865 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4866 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4867 Builder
bld(ctx
->program
, ctx
->block
);
4868 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4869 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4870 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4871 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4872 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4875 unsigned idx
= nir_intrinsic_base(instr
);
4876 unsigned component
= nir_intrinsic_component(instr
);
4877 unsigned vertex_id
= 2; /* P0 */
4879 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4880 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4881 switch (src0
->u32
) {
4883 vertex_id
= 2; /* P0 */
4886 vertex_id
= 0; /* P10 */
4889 vertex_id
= 1; /* P20 */
4892 unreachable("invalid vertex index");
4896 if (dst
.size() == 1) {
4897 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4899 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4900 for (unsigned i
= 0; i
< dst
.size(); i
++)
4901 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4902 vec
->definitions
[0] = Definition(dst
);
4903 bld
.insert(std::move(vec
));
4906 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4907 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4908 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4909 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4910 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4912 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4914 unreachable("Shader stage not implemented");
4918 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4920 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4922 Builder
bld(ctx
->program
, ctx
->block
);
4923 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4926 if (!nir_src_is_const(*vertex_src
)) {
4927 /* better code could be created, but this case probably doesn't happen
4928 * much in practice */
4929 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4930 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4933 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4934 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4936 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4938 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4941 if (vertex_offset
.id()) {
4942 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4943 Operand(i
), indirect_vertex
);
4944 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4946 vertex_offset
= elem
;
4950 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4951 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4953 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4954 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4955 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4956 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4957 Operand((vertex
% 2u) * 16u), Operand(16u));
4959 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4962 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4963 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4964 return offset_mul(ctx
, offs
, 4u);
4967 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4969 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4971 Builder
bld(ctx
->program
, ctx
->block
);
4972 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4973 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4975 if (ctx
->stage
== geometry_gs
) {
4976 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4977 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4978 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4979 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4980 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4981 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4982 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4984 unreachable("Unsupported GS stage.");
4988 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4990 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4992 Builder
bld(ctx
->program
, ctx
->block
);
4993 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4995 if (load_input_from_temps(ctx
, instr
, dst
))
4998 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4999 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5000 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5002 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5005 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5007 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5009 Builder
bld(ctx
->program
, ctx
->block
);
5011 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5012 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5013 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5015 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5016 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5018 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5021 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5023 switch (ctx
->shader
->info
.stage
) {
5024 case MESA_SHADER_GEOMETRY
:
5025 visit_load_gs_per_vertex_input(ctx
, instr
);
5027 case MESA_SHADER_TESS_CTRL
:
5028 visit_load_tcs_per_vertex_input(ctx
, instr
);
5030 case MESA_SHADER_TESS_EVAL
:
5031 visit_load_tes_per_vertex_input(ctx
, instr
);
5034 unreachable("Unimplemented shader stage");
5038 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5040 visit_load_tcs_output(ctx
, instr
, true);
5043 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5045 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5046 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5048 visit_store_tcs_output(ctx
, instr
, true);
5051 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5053 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5055 Builder
bld(ctx
->program
, ctx
->block
);
5056 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5058 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5059 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5062 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5063 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5064 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5065 tes_w
= Operand(tmp
);
5068 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5069 emit_split_vector(ctx
, tess_coord
, 3);
5072 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5074 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5075 Builder
bld(ctx
->program
, ctx
->block
);
5076 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5077 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5078 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5081 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5085 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5087 Builder
bld(ctx
->program
, ctx
->block
);
5088 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5089 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
5090 index
= bld
.as_uniform(index
);
5091 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5092 unsigned binding
= nir_intrinsic_binding(instr
);
5095 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5096 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5097 unsigned offset
= layout
->binding
[binding
].offset
;
5099 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5100 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5101 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5102 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5103 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5106 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5107 stride
= layout
->binding
[binding
].size
;
5110 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5111 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5113 if (nir_const_index
) {
5114 const_index
= const_index
* stride
;
5115 } else if (index
.type() == RegType::vgpr
) {
5116 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5117 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5119 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5123 if (nir_const_index
) {
5124 const_index
= const_index
+ offset
;
5125 } else if (index
.type() == RegType::vgpr
) {
5126 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5128 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5132 if (nir_const_index
&& const_index
== 0) {
5134 } else if (index
.type() == RegType::vgpr
) {
5135 index
= bld
.vadd32(bld
.def(v1
),
5136 nir_const_index
? Operand(const_index
) : Operand(index
),
5139 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5140 nir_const_index
? Operand(const_index
) : Operand(index
),
5144 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5147 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5148 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5149 bool glc
=false, bool readonly
=true)
5151 Builder
bld(ctx
->program
, ctx
->block
);
5153 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5155 offset
= bld
.as_uniform(offset
);
5157 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5159 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5160 info
.can_reorder
= readonly
;
5161 info
.align_mul
= align_mul
;
5162 info
.align_offset
= align_offset
;
5164 emit_smem_load(ctx
, bld
, &info
);
5166 emit_mubuf_load(ctx
, bld
, &info
);
5169 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5171 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5172 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5174 Builder
bld(ctx
->program
, ctx
->block
);
5176 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5177 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5178 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5179 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5181 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5182 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5183 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5184 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5185 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5186 if (ctx
->options
->chip_class
>= GFX10
) {
5187 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5188 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5189 S_008F0C_RESOURCE_LEVEL(1);
5191 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5192 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5194 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5195 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5196 Operand(0xFFFFFFFFu
),
5197 Operand(desc_type
));
5198 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5199 rsrc
, upper_dwords
);
5201 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5202 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5204 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5205 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5206 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5209 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5211 Builder
bld(ctx
->program
, ctx
->block
);
5212 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5213 unsigned offset
= nir_intrinsic_base(instr
);
5214 unsigned count
= instr
->dest
.ssa
.num_components
;
5215 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5217 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5218 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5219 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5220 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5221 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5222 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5223 for (unsigned i
= 0; i
< count
; ++i
) {
5224 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5225 vec
->operands
[i
] = Operand
{elems
[i
]};
5227 vec
->definitions
[0] = Definition(dst
);
5228 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5229 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5234 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5235 if (offset
!= 0) // TODO check if index != 0 as well
5236 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5237 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5240 bool aligned
= true;
5242 if (instr
->dest
.ssa
.bit_size
== 8) {
5243 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5244 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5246 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5247 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5248 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5250 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5255 switch (vec
.size()) {
5257 op
= aco_opcode::s_load_dword
;
5260 op
= aco_opcode::s_load_dwordx2
;
5266 op
= aco_opcode::s_load_dwordx4
;
5272 op
= aco_opcode::s_load_dwordx8
;
5275 unreachable("unimplemented or forbidden load_push_constant.");
5278 bld
.smem(op
, Definition(vec
), ptr
, index
);
5281 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5282 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5287 emit_split_vector(ctx
, vec
, 4);
5288 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5289 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5290 emit_extract_vector(ctx
, vec
, 0, rc
),
5291 emit_extract_vector(ctx
, vec
, 1, rc
),
5292 emit_extract_vector(ctx
, vec
, 2, rc
));
5295 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5298 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5300 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5302 Builder
bld(ctx
->program
, ctx
->block
);
5304 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5305 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5306 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5307 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5308 if (ctx
->options
->chip_class
>= GFX10
) {
5309 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5310 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5311 S_008F0C_RESOURCE_LEVEL(1);
5313 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5314 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5317 unsigned base
= nir_intrinsic_base(instr
);
5318 unsigned range
= nir_intrinsic_range(instr
);
5320 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5321 if (base
&& offset
.type() == RegType::sgpr
)
5322 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5323 else if (base
&& offset
.type() == RegType::vgpr
)
5324 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5326 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5327 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5328 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5329 Operand(desc_type
));
5330 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5331 // TODO: get alignment information for subdword constants
5332 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5335 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5337 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5338 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5340 ctx
->program
->needs_exact
= true;
5342 // TODO: optimize uniform conditions
5343 Builder
bld(ctx
->program
, ctx
->block
);
5344 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5345 assert(src
.regClass() == bld
.lm
);
5346 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5347 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5348 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5352 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5354 Builder
bld(ctx
->program
, ctx
->block
);
5356 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5357 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5359 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5360 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5362 if (ctx
->block
->loop_nest_depth
&&
5363 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5364 /* we handle discards the same way as jump instructions */
5365 append_logical_end(ctx
->block
);
5367 /* in loops, discard behaves like break */
5368 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5369 ctx
->block
->kind
|= block_kind_discard
;
5372 /* uniform discard - loop ends here */
5373 assert(nir_instr_is_last(&instr
->instr
));
5374 ctx
->block
->kind
|= block_kind_uniform
;
5375 ctx
->cf_info
.has_branch
= true;
5376 bld
.branch(aco_opcode::p_branch
);
5377 add_linear_edge(ctx
->block
->index
, linear_target
);
5381 /* we add a break right behind the discard() instructions */
5382 ctx
->block
->kind
|= block_kind_break
;
5383 unsigned idx
= ctx
->block
->index
;
5385 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5386 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5388 /* remove critical edges from linear CFG */
5389 bld
.branch(aco_opcode::p_branch
);
5390 Block
* break_block
= ctx
->program
->create_and_insert_block();
5391 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5392 break_block
->kind
|= block_kind_uniform
;
5393 add_linear_edge(idx
, break_block
);
5394 add_linear_edge(break_block
->index
, linear_target
);
5395 bld
.reset(break_block
);
5396 bld
.branch(aco_opcode::p_branch
);
5398 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5399 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5400 add_linear_edge(idx
, continue_block
);
5401 append_logical_start(continue_block
);
5402 ctx
->block
= continue_block
;
5407 /* it can currently happen that NIR doesn't remove the unreachable code */
5408 if (!nir_instr_is_last(&instr
->instr
)) {
5409 ctx
->program
->needs_exact
= true;
5410 /* save exec somewhere temporarily so that it doesn't get
5411 * overwritten before the discard from outer exec masks */
5412 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5413 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5414 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5418 /* This condition is incorrect for uniformly branched discards in a loop
5419 * predicated by a divergent condition, but the above code catches that case
5420 * and the discard would end up turning into a discard_if.
5430 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5431 /* program just ends here */
5432 ctx
->block
->kind
|= block_kind_uniform
;
5433 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5434 0 /* enabled mask */, 9 /* dest */,
5435 false /* compressed */, true/* done */, true /* valid mask */);
5436 bld
.sopp(aco_opcode::s_endpgm
);
5437 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5439 ctx
->block
->kind
|= block_kind_discard
;
5440 /* branch and linear edge is added by visit_if() */
5444 enum aco_descriptor_type
{
5455 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5456 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5458 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5459 return dim
== ac_image_cube
||
5460 dim
== ac_image_1darray
||
5461 dim
== ac_image_2darray
||
5462 dim
== ac_image_2darraymsaa
;
5465 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5466 enum aco_descriptor_type desc_type
,
5467 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5469 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5470 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5471 if (it != ctx->tex_desc.end())
5474 Temp index
= Temp();
5475 bool index_set
= false;
5476 unsigned constant_index
= 0;
5477 unsigned descriptor_set
;
5478 unsigned base_index
;
5479 Builder
bld(ctx
->program
, ctx
->block
);
5482 assert(tex_instr
&& !image
);
5484 base_index
= tex_instr
->sampler_index
;
5486 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5487 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5491 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5492 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5494 constant_index
+= array_size
* const_value
->u32
;
5496 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5497 if (indirect
.type() == RegType::vgpr
)
5498 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5500 if (array_size
!= 1)
5501 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5507 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5511 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5513 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5514 base_index
= deref_instr
->var
->data
.binding
;
5517 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5518 list
= convert_pointer_to_64_bit(ctx
, list
);
5520 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5521 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5522 unsigned offset
= binding
->offset
;
5523 unsigned stride
= binding
->size
;
5527 assert(base_index
< layout
->binding_count
);
5529 switch (desc_type
) {
5530 case ACO_DESC_IMAGE
:
5532 opcode
= aco_opcode::s_load_dwordx8
;
5534 case ACO_DESC_FMASK
:
5536 opcode
= aco_opcode::s_load_dwordx8
;
5539 case ACO_DESC_SAMPLER
:
5541 opcode
= aco_opcode::s_load_dwordx4
;
5542 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5543 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5545 case ACO_DESC_BUFFER
:
5547 opcode
= aco_opcode::s_load_dwordx4
;
5549 case ACO_DESC_PLANE_0
:
5550 case ACO_DESC_PLANE_1
:
5552 opcode
= aco_opcode::s_load_dwordx8
;
5553 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5555 case ACO_DESC_PLANE_2
:
5557 opcode
= aco_opcode::s_load_dwordx4
;
5561 unreachable("invalid desc_type\n");
5564 offset
+= constant_index
* stride
;
5566 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5567 (!index_set
|| binding
->immutable_samplers_equal
)) {
5568 if (binding
->immutable_samplers_equal
)
5571 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5572 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5573 Operand(samplers
[constant_index
* 4 + 0]),
5574 Operand(samplers
[constant_index
* 4 + 1]),
5575 Operand(samplers
[constant_index
* 4 + 2]),
5576 Operand(samplers
[constant_index
* 4 + 3]));
5581 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5583 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5584 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5587 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5589 if (desc_type
== ACO_DESC_PLANE_2
) {
5591 for (unsigned i
= 0; i
< 8; i
++)
5592 components
[i
] = bld
.tmp(s1
);
5593 bld
.pseudo(aco_opcode::p_split_vector
,
5594 Definition(components
[0]),
5595 Definition(components
[1]),
5596 Definition(components
[2]),
5597 Definition(components
[3]),
5600 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5601 bld
.pseudo(aco_opcode::p_split_vector
,
5602 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5603 Definition(components
[4]),
5604 Definition(components
[5]),
5605 Definition(components
[6]),
5606 Definition(components
[7]),
5609 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5610 components
[0], components
[1], components
[2], components
[3],
5611 components
[4], components
[5], components
[6], components
[7]);
5617 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5620 case GLSL_SAMPLER_DIM_BUF
:
5622 case GLSL_SAMPLER_DIM_1D
:
5623 return array
? 2 : 1;
5624 case GLSL_SAMPLER_DIM_2D
:
5625 return array
? 3 : 2;
5626 case GLSL_SAMPLER_DIM_MS
:
5627 return array
? 4 : 3;
5628 case GLSL_SAMPLER_DIM_3D
:
5629 case GLSL_SAMPLER_DIM_CUBE
:
5631 case GLSL_SAMPLER_DIM_RECT
:
5632 case GLSL_SAMPLER_DIM_SUBPASS
:
5634 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5643 /* Adjust the sample index according to FMASK.
5645 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5646 * which is the identity mapping. Each nibble says which physical sample
5647 * should be fetched to get that sample.
5649 * For example, 0x11111100 means there are only 2 samples stored and
5650 * the second sample covers 3/4 of the pixel. When reading samples 0
5651 * and 1, return physical sample 0 (determined by the first two 0s
5652 * in FMASK), otherwise return physical sample 1.
5654 * The sample index should be adjusted as follows:
5655 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5657 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5659 Builder
bld(ctx
->program
, ctx
->block
);
5660 Temp fmask
= bld
.tmp(v1
);
5661 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5662 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5665 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5666 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5667 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5668 load
->operands
[0] = Operand(fmask_desc_ptr
);
5669 load
->operands
[1] = Operand(s4
); /* no sampler */
5670 load
->operands
[2] = Operand(coord
);
5671 load
->definitions
[0] = Definition(fmask
);
5678 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5679 ctx
->block
->instructions
.emplace_back(std::move(load
));
5681 Operand sample_index4
;
5682 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5683 sample_index4
= Operand(sample_index
.constantValue() << 2);
5684 } else if (sample_index
.regClass() == s1
) {
5685 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5687 assert(sample_index
.regClass() == v1
);
5688 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5692 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5693 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5694 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5695 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5697 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5699 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5700 * resource descriptor is 0 (invalid),
5702 Temp compare
= bld
.tmp(bld
.lm
);
5703 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5704 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5706 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5708 /* Replace the MSAA sample index. */
5709 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5712 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5715 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5716 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5717 bool is_array
= glsl_sampler_type_is_array(type
);
5718 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5719 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5720 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5721 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5722 int count
= image_type_to_components_count(dim
, is_array
);
5723 std::vector
<Temp
> coords(count
);
5724 Builder
bld(ctx
->program
, ctx
->block
);
5728 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5729 /* get sample index */
5730 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5731 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5732 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5733 std::vector
<Temp
> fmask_load_address
;
5734 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5735 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5737 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5738 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5740 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5745 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5746 coords
.resize(coords
.size() + 1);
5747 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5749 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5751 for (int i
= 0; i
< count
; i
++)
5752 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5755 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5756 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5757 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5758 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5761 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5764 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5765 for (unsigned i
= 0; i
< coords
.size(); i
++)
5766 vec
->operands
[i
] = Operand(coords
[i
]);
5767 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5768 vec
->definitions
[0] = Definition(res
);
5769 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5774 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5776 Builder
bld(ctx
->program
, ctx
->block
);
5777 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5778 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5779 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5780 bool is_array
= glsl_sampler_type_is_array(type
);
5781 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5783 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5784 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5785 unsigned num_channels
= util_last_bit(mask
);
5786 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5787 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5790 switch (num_channels
) {
5792 opcode
= aco_opcode::buffer_load_format_x
;
5795 opcode
= aco_opcode::buffer_load_format_xy
;
5798 opcode
= aco_opcode::buffer_load_format_xyz
;
5801 opcode
= aco_opcode::buffer_load_format_xyzw
;
5804 unreachable(">4 channel buffer image load");
5806 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5807 load
->operands
[0] = Operand(rsrc
);
5808 load
->operands
[1] = Operand(vindex
);
5809 load
->operands
[2] = Operand((uint32_t) 0);
5811 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5814 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5815 load
->definitions
[0] = Definition(tmp
);
5817 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5818 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5819 load
->barrier
= barrier_image
;
5820 ctx
->block
->instructions
.emplace_back(std::move(load
));
5822 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5826 Temp coords
= get_image_coords(ctx
, instr
, type
);
5827 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5829 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5830 unsigned num_components
= util_bitcount(dmask
);
5832 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5835 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5837 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5838 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5840 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5841 load
->operands
[0] = Operand(resource
);
5842 load
->operands
[1] = Operand(s4
); /* no sampler */
5843 load
->operands
[2] = Operand(coords
);
5844 load
->definitions
[0] = Definition(tmp
);
5845 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5846 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5847 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5848 load
->dmask
= dmask
;
5850 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5851 load
->barrier
= barrier_image
;
5852 ctx
->block
->instructions
.emplace_back(std::move(load
));
5854 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5858 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5860 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5861 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5862 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5863 bool is_array
= glsl_sampler_type_is_array(type
);
5864 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5866 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5868 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5869 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5870 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5872 switch (data
.size()) {
5874 opcode
= aco_opcode::buffer_store_format_x
;
5877 opcode
= aco_opcode::buffer_store_format_xy
;
5880 opcode
= aco_opcode::buffer_store_format_xyz
;
5883 opcode
= aco_opcode::buffer_store_format_xyzw
;
5886 unreachable(">4 channel buffer image store");
5888 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5889 store
->operands
[0] = Operand(rsrc
);
5890 store
->operands
[1] = Operand(vindex
);
5891 store
->operands
[2] = Operand((uint32_t) 0);
5892 store
->operands
[3] = Operand(data
);
5893 store
->idxen
= true;
5896 store
->disable_wqm
= true;
5897 store
->barrier
= barrier_image
;
5898 ctx
->program
->needs_exact
= true;
5899 ctx
->block
->instructions
.emplace_back(std::move(store
));
5903 assert(data
.type() == RegType::vgpr
);
5904 Temp coords
= get_image_coords(ctx
, instr
, type
);
5905 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5907 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5908 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5910 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5911 store
->operands
[0] = Operand(resource
);
5912 store
->operands
[1] = Operand(data
);
5913 store
->operands
[2] = Operand(coords
);
5916 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5917 store
->dmask
= (1 << data
.size()) - 1;
5919 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5920 store
->disable_wqm
= true;
5921 store
->barrier
= barrier_image
;
5922 ctx
->program
->needs_exact
= true;
5923 ctx
->block
->instructions
.emplace_back(std::move(store
));
5927 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5929 /* return the previous value if dest is ever used */
5930 bool return_previous
= false;
5931 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5932 return_previous
= true;
5935 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5936 return_previous
= true;
5940 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5941 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5942 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5943 bool is_array
= glsl_sampler_type_is_array(type
);
5944 Builder
bld(ctx
->program
, ctx
->block
);
5946 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5947 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5949 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5950 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5952 aco_opcode buf_op
, image_op
;
5953 switch (instr
->intrinsic
) {
5954 case nir_intrinsic_image_deref_atomic_add
:
5955 buf_op
= aco_opcode::buffer_atomic_add
;
5956 image_op
= aco_opcode::image_atomic_add
;
5958 case nir_intrinsic_image_deref_atomic_umin
:
5959 buf_op
= aco_opcode::buffer_atomic_umin
;
5960 image_op
= aco_opcode::image_atomic_umin
;
5962 case nir_intrinsic_image_deref_atomic_imin
:
5963 buf_op
= aco_opcode::buffer_atomic_smin
;
5964 image_op
= aco_opcode::image_atomic_smin
;
5966 case nir_intrinsic_image_deref_atomic_umax
:
5967 buf_op
= aco_opcode::buffer_atomic_umax
;
5968 image_op
= aco_opcode::image_atomic_umax
;
5970 case nir_intrinsic_image_deref_atomic_imax
:
5971 buf_op
= aco_opcode::buffer_atomic_smax
;
5972 image_op
= aco_opcode::image_atomic_smax
;
5974 case nir_intrinsic_image_deref_atomic_and
:
5975 buf_op
= aco_opcode::buffer_atomic_and
;
5976 image_op
= aco_opcode::image_atomic_and
;
5978 case nir_intrinsic_image_deref_atomic_or
:
5979 buf_op
= aco_opcode::buffer_atomic_or
;
5980 image_op
= aco_opcode::image_atomic_or
;
5982 case nir_intrinsic_image_deref_atomic_xor
:
5983 buf_op
= aco_opcode::buffer_atomic_xor
;
5984 image_op
= aco_opcode::image_atomic_xor
;
5986 case nir_intrinsic_image_deref_atomic_exchange
:
5987 buf_op
= aco_opcode::buffer_atomic_swap
;
5988 image_op
= aco_opcode::image_atomic_swap
;
5990 case nir_intrinsic_image_deref_atomic_comp_swap
:
5991 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5992 image_op
= aco_opcode::image_atomic_cmpswap
;
5995 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5998 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6000 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
6001 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
6002 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6003 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6004 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6005 mubuf
->operands
[0] = Operand(resource
);
6006 mubuf
->operands
[1] = Operand(vindex
);
6007 mubuf
->operands
[2] = Operand((uint32_t)0);
6008 mubuf
->operands
[3] = Operand(data
);
6009 if (return_previous
)
6010 mubuf
->definitions
[0] = Definition(dst
);
6012 mubuf
->idxen
= true;
6013 mubuf
->glc
= return_previous
;
6014 mubuf
->dlc
= false; /* Not needed for atomics */
6015 mubuf
->disable_wqm
= true;
6016 mubuf
->barrier
= barrier_image
;
6017 ctx
->program
->needs_exact
= true;
6018 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6022 Temp coords
= get_image_coords(ctx
, instr
, type
);
6023 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6024 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6025 mimg
->operands
[0] = Operand(resource
);
6026 mimg
->operands
[1] = Operand(data
);
6027 mimg
->operands
[2] = Operand(coords
);
6028 if (return_previous
)
6029 mimg
->definitions
[0] = Definition(dst
);
6030 mimg
->glc
= return_previous
;
6031 mimg
->dlc
= false; /* Not needed for atomics */
6032 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6033 mimg
->dmask
= (1 << data
.size()) - 1;
6035 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6036 mimg
->disable_wqm
= true;
6037 mimg
->barrier
= barrier_image
;
6038 ctx
->program
->needs_exact
= true;
6039 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6043 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6045 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6046 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6047 Builder
bld(ctx
->program
, ctx
->block
);
6049 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6051 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6052 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6054 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6055 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6057 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6058 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6060 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6061 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6062 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6063 if (dst
.type() == RegType::vgpr
)
6064 bld
.copy(Definition(dst
), shr_dst
);
6066 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6068 emit_extract_vector(ctx
, desc
, 2, dst
);
6072 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6074 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6075 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6076 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6077 bool is_array
= glsl_sampler_type_is_array(type
);
6078 Builder
bld(ctx
->program
, ctx
->block
);
6080 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6081 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6082 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6086 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6089 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6091 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6093 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6094 mimg
->operands
[0] = Operand(resource
);
6095 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6096 mimg
->operands
[2] = Operand(lod
);
6097 uint8_t& dmask
= mimg
->dmask
;
6098 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6099 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6100 mimg
->da
= glsl_sampler_type_is_array(type
);
6101 mimg
->can_reorder
= true;
6102 Definition
& def
= mimg
->definitions
[0];
6103 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6105 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6106 glsl_sampler_type_is_array(type
)) {
6108 assert(instr
->dest
.ssa
.num_components
== 3);
6109 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6110 def
= Definition(tmp
);
6111 emit_split_vector(ctx
, tmp
, 3);
6113 /* divide 3rd value by 6 by multiplying with magic number */
6114 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6115 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6117 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6118 emit_extract_vector(ctx
, tmp
, 0, v1
),
6119 emit_extract_vector(ctx
, tmp
, 1, v1
),
6122 } else if (ctx
->options
->chip_class
== GFX9
&&
6123 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6124 glsl_sampler_type_is_array(type
)) {
6125 assert(instr
->dest
.ssa
.num_components
== 2);
6126 def
= Definition(dst
);
6129 def
= Definition(dst
);
6132 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6135 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6137 Builder
bld(ctx
->program
, ctx
->block
);
6138 unsigned num_components
= instr
->num_components
;
6140 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6141 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6142 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6144 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6145 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6146 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6147 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6150 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6152 Builder
bld(ctx
->program
, ctx
->block
);
6153 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6154 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6155 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6156 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6158 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6159 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6161 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
6162 ctx
->options
->chip_class
>= GFX8
&&
6163 elem_size_bytes
>= 4;
6165 offset
= bld
.as_uniform(offset
);
6166 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6170 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6171 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
6172 /* GFX6 doesn't support storing vec3, split it. */
6173 writemask
|= 1u << (start
+ 2);
6176 int num_bytes
= count
* elem_size_bytes
;
6178 /* dword or larger stores have to be dword-aligned */
6179 if (elem_size_bytes
< 4 && num_bytes
> 2) {
6180 // TODO: improve alignment check of sub-dword stores
6181 unsigned count_new
= 2 / elem_size_bytes
;
6182 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
6187 if (num_bytes
> 16) {
6188 assert(elem_size_bytes
== 8);
6189 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6195 if (elem_size_bytes
< 4) {
6196 if (data
.type() == RegType::sgpr
) {
6197 data
= as_vgpr(ctx
, data
);
6198 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
6200 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
6201 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6202 for (int i
= 0; i
< count
; i
++)
6203 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
6204 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
6205 vec
->definitions
[0] = Definition(write_data
);
6206 bld
.insert(std::move(vec
));
6207 } else if (count
!= instr
->num_components
) {
6208 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6209 for (int i
= 0; i
< count
; i
++) {
6210 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
6211 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
6213 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
6214 vec
->definitions
[0] = Definition(write_data
);
6215 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6216 } else if (!smem
&& data
.type() != RegType::vgpr
) {
6217 assert(num_bytes
% 4 == 0);
6218 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
6219 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
6220 assert(num_bytes
% 4 == 0);
6221 write_data
= bld
.as_uniform(data
);
6226 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
6227 switch (num_bytes
) {
6229 vmem_op
= aco_opcode::buffer_store_byte
;
6232 vmem_op
= aco_opcode::buffer_store_short
;
6235 vmem_op
= aco_opcode::buffer_store_dword
;
6236 smem_op
= aco_opcode::s_buffer_store_dword
;
6239 vmem_op
= aco_opcode::buffer_store_dwordx2
;
6240 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
6243 vmem_op
= aco_opcode::buffer_store_dwordx3
;
6244 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
6247 vmem_op
= aco_opcode::buffer_store_dwordx4
;
6248 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
6251 unreachable("Store SSBO not implemented for this size.");
6253 if (ctx
->stage
== fragment_fs
)
6254 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
6257 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
6258 store
->operands
[0] = Operand(rsrc
);
6260 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6261 offset
, Operand(start
* elem_size_bytes
));
6262 store
->operands
[1] = Operand(off
);
6264 store
->operands
[1] = Operand(offset
);
6266 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
6267 store
->operands
[1].setFixed(m0
);
6268 store
->operands
[2] = Operand(write_data
);
6269 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6271 store
->disable_wqm
= true;
6272 store
->barrier
= barrier_buffer
;
6273 ctx
->block
->instructions
.emplace_back(std::move(store
));
6274 ctx
->program
->wb_smem_l1_on_end
= true;
6275 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
6276 ctx
->block
->kind
|= block_kind_needs_lowering
;
6277 ctx
->program
->needs_exact
= true;
6280 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
6281 store
->operands
[0] = Operand(rsrc
);
6282 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6283 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6284 store
->operands
[3] = Operand(write_data
);
6285 store
->offset
= start
* elem_size_bytes
;
6286 store
->offen
= (offset
.type() == RegType::vgpr
);
6287 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6289 store
->disable_wqm
= true;
6290 store
->barrier
= barrier_buffer
;
6291 ctx
->program
->needs_exact
= true;
6292 ctx
->block
->instructions
.emplace_back(std::move(store
));
6297 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6299 /* return the previous value if dest is ever used */
6300 bool return_previous
= false;
6301 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6302 return_previous
= true;
6305 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6306 return_previous
= true;
6310 Builder
bld(ctx
->program
, ctx
->block
);
6311 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6313 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6314 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6315 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6317 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6318 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6319 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6321 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6323 aco_opcode op32
, op64
;
6324 switch (instr
->intrinsic
) {
6325 case nir_intrinsic_ssbo_atomic_add
:
6326 op32
= aco_opcode::buffer_atomic_add
;
6327 op64
= aco_opcode::buffer_atomic_add_x2
;
6329 case nir_intrinsic_ssbo_atomic_imin
:
6330 op32
= aco_opcode::buffer_atomic_smin
;
6331 op64
= aco_opcode::buffer_atomic_smin_x2
;
6333 case nir_intrinsic_ssbo_atomic_umin
:
6334 op32
= aco_opcode::buffer_atomic_umin
;
6335 op64
= aco_opcode::buffer_atomic_umin_x2
;
6337 case nir_intrinsic_ssbo_atomic_imax
:
6338 op32
= aco_opcode::buffer_atomic_smax
;
6339 op64
= aco_opcode::buffer_atomic_smax_x2
;
6341 case nir_intrinsic_ssbo_atomic_umax
:
6342 op32
= aco_opcode::buffer_atomic_umax
;
6343 op64
= aco_opcode::buffer_atomic_umax_x2
;
6345 case nir_intrinsic_ssbo_atomic_and
:
6346 op32
= aco_opcode::buffer_atomic_and
;
6347 op64
= aco_opcode::buffer_atomic_and_x2
;
6349 case nir_intrinsic_ssbo_atomic_or
:
6350 op32
= aco_opcode::buffer_atomic_or
;
6351 op64
= aco_opcode::buffer_atomic_or_x2
;
6353 case nir_intrinsic_ssbo_atomic_xor
:
6354 op32
= aco_opcode::buffer_atomic_xor
;
6355 op64
= aco_opcode::buffer_atomic_xor_x2
;
6357 case nir_intrinsic_ssbo_atomic_exchange
:
6358 op32
= aco_opcode::buffer_atomic_swap
;
6359 op64
= aco_opcode::buffer_atomic_swap_x2
;
6361 case nir_intrinsic_ssbo_atomic_comp_swap
:
6362 op32
= aco_opcode::buffer_atomic_cmpswap
;
6363 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6366 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6368 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6369 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6370 mubuf
->operands
[0] = Operand(rsrc
);
6371 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6372 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6373 mubuf
->operands
[3] = Operand(data
);
6374 if (return_previous
)
6375 mubuf
->definitions
[0] = Definition(dst
);
6377 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6378 mubuf
->glc
= return_previous
;
6379 mubuf
->dlc
= false; /* Not needed for atomics */
6380 mubuf
->disable_wqm
= true;
6381 mubuf
->barrier
= barrier_buffer
;
6382 ctx
->program
->needs_exact
= true;
6383 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6386 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6388 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6389 Builder
bld(ctx
->program
, ctx
->block
);
6390 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6391 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6394 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6396 Builder
bld(ctx
->program
, ctx
->block
);
6397 unsigned num_components
= instr
->num_components
;
6398 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6400 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6401 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6402 num_components
, component_size
};
6403 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6404 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6405 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6406 info
.barrier
= barrier_buffer
;
6407 info
.can_reorder
= false;
6408 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6409 * it's safe to use SMEM */
6410 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6411 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6412 emit_global_load(ctx
, bld
, &info
);
6414 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6415 emit_smem_load(ctx
, bld
, &info
);
6419 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6421 Builder
bld(ctx
->program
, ctx
->block
);
6422 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6424 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6425 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6427 if (ctx
->options
->chip_class
>= GFX7
)
6428 addr
= as_vgpr(ctx
, addr
);
6430 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6433 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6434 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6435 /* GFX6 doesn't support storing vec3, split it. */
6436 writemask
|= 1u << (start
+ 2);
6439 unsigned num_bytes
= count
* elem_size_bytes
;
6441 Temp write_data
= data
;
6442 if (count
!= instr
->num_components
) {
6443 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6444 for (int i
= 0; i
< count
; i
++)
6445 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6446 write_data
= bld
.tmp(RegType::vgpr
, count
);
6447 vec
->definitions
[0] = Definition(write_data
);
6448 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6451 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6452 unsigned offset
= start
* elem_size_bytes
;
6454 if (ctx
->options
->chip_class
>= GFX7
) {
6455 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6456 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6457 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6458 Temp carry
= bld
.tmp(bld
.lm
);
6459 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6461 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6462 Operand(offset
), addr0
);
6463 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6465 carry
).def(1).setHint(vcc
);
6467 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6472 bool global
= ctx
->options
->chip_class
>= GFX9
;
6474 switch (num_bytes
) {
6476 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6479 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6482 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6485 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6488 unreachable("store_global not implemented for this size.");
6491 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6492 flat
->operands
[0] = Operand(addr
);
6493 flat
->operands
[1] = Operand(s1
);
6494 flat
->operands
[2] = Operand(data
);
6497 flat
->offset
= offset
;
6498 flat
->disable_wqm
= true;
6499 flat
->barrier
= barrier_buffer
;
6500 ctx
->program
->needs_exact
= true;
6501 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6503 assert(ctx
->options
->chip_class
== GFX6
);
6506 switch (num_bytes
) {
6508 op
= aco_opcode::buffer_store_dword
;
6511 op
= aco_opcode::buffer_store_dwordx2
;
6514 op
= aco_opcode::buffer_store_dwordx4
;
6517 unreachable("store_global not implemented for this size.");
6520 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6522 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6523 mubuf
->operands
[0] = Operand(rsrc
);
6524 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6525 mubuf
->operands
[2] = Operand(0u);
6526 mubuf
->operands
[3] = Operand(write_data
);
6529 mubuf
->offset
= offset
;
6530 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6531 mubuf
->disable_wqm
= true;
6532 mubuf
->barrier
= barrier_buffer
;
6533 ctx
->program
->needs_exact
= true;
6534 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6539 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6541 /* return the previous value if dest is ever used */
6542 bool return_previous
= false;
6543 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6544 return_previous
= true;
6547 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6548 return_previous
= true;
6552 Builder
bld(ctx
->program
, ctx
->block
);
6553 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6554 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6556 if (ctx
->options
->chip_class
>= GFX7
)
6557 addr
= as_vgpr(ctx
, addr
);
6559 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6560 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6561 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6563 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6565 aco_opcode op32
, op64
;
6567 if (ctx
->options
->chip_class
>= GFX7
) {
6568 bool global
= ctx
->options
->chip_class
>= GFX9
;
6569 switch (instr
->intrinsic
) {
6570 case nir_intrinsic_global_atomic_add
:
6571 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6572 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6574 case nir_intrinsic_global_atomic_imin
:
6575 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6576 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6578 case nir_intrinsic_global_atomic_umin
:
6579 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6580 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6582 case nir_intrinsic_global_atomic_imax
:
6583 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6584 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6586 case nir_intrinsic_global_atomic_umax
:
6587 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6588 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6590 case nir_intrinsic_global_atomic_and
:
6591 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6592 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6594 case nir_intrinsic_global_atomic_or
:
6595 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6596 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6598 case nir_intrinsic_global_atomic_xor
:
6599 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6600 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6602 case nir_intrinsic_global_atomic_exchange
:
6603 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6604 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6606 case nir_intrinsic_global_atomic_comp_swap
:
6607 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6608 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6611 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6614 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6615 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6616 flat
->operands
[0] = Operand(addr
);
6617 flat
->operands
[1] = Operand(s1
);
6618 flat
->operands
[2] = Operand(data
);
6619 if (return_previous
)
6620 flat
->definitions
[0] = Definition(dst
);
6621 flat
->glc
= return_previous
;
6622 flat
->dlc
= false; /* Not needed for atomics */
6624 flat
->disable_wqm
= true;
6625 flat
->barrier
= barrier_buffer
;
6626 ctx
->program
->needs_exact
= true;
6627 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6629 assert(ctx
->options
->chip_class
== GFX6
);
6631 switch (instr
->intrinsic
) {
6632 case nir_intrinsic_global_atomic_add
:
6633 op32
= aco_opcode::buffer_atomic_add
;
6634 op64
= aco_opcode::buffer_atomic_add_x2
;
6636 case nir_intrinsic_global_atomic_imin
:
6637 op32
= aco_opcode::buffer_atomic_smin
;
6638 op64
= aco_opcode::buffer_atomic_smin_x2
;
6640 case nir_intrinsic_global_atomic_umin
:
6641 op32
= aco_opcode::buffer_atomic_umin
;
6642 op64
= aco_opcode::buffer_atomic_umin_x2
;
6644 case nir_intrinsic_global_atomic_imax
:
6645 op32
= aco_opcode::buffer_atomic_smax
;
6646 op64
= aco_opcode::buffer_atomic_smax_x2
;
6648 case nir_intrinsic_global_atomic_umax
:
6649 op32
= aco_opcode::buffer_atomic_umax
;
6650 op64
= aco_opcode::buffer_atomic_umax_x2
;
6652 case nir_intrinsic_global_atomic_and
:
6653 op32
= aco_opcode::buffer_atomic_and
;
6654 op64
= aco_opcode::buffer_atomic_and_x2
;
6656 case nir_intrinsic_global_atomic_or
:
6657 op32
= aco_opcode::buffer_atomic_or
;
6658 op64
= aco_opcode::buffer_atomic_or_x2
;
6660 case nir_intrinsic_global_atomic_xor
:
6661 op32
= aco_opcode::buffer_atomic_xor
;
6662 op64
= aco_opcode::buffer_atomic_xor_x2
;
6664 case nir_intrinsic_global_atomic_exchange
:
6665 op32
= aco_opcode::buffer_atomic_swap
;
6666 op64
= aco_opcode::buffer_atomic_swap_x2
;
6668 case nir_intrinsic_global_atomic_comp_swap
:
6669 op32
= aco_opcode::buffer_atomic_cmpswap
;
6670 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6673 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6676 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6678 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6680 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6681 mubuf
->operands
[0] = Operand(rsrc
);
6682 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6683 mubuf
->operands
[2] = Operand(0u);
6684 mubuf
->operands
[3] = Operand(data
);
6685 if (return_previous
)
6686 mubuf
->definitions
[0] = Definition(dst
);
6687 mubuf
->glc
= return_previous
;
6690 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6691 mubuf
->disable_wqm
= true;
6692 mubuf
->barrier
= barrier_buffer
;
6693 ctx
->program
->needs_exact
= true;
6694 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6698 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6699 Builder
bld(ctx
->program
, ctx
->block
);
6700 switch(instr
->intrinsic
) {
6701 case nir_intrinsic_group_memory_barrier
:
6702 case nir_intrinsic_memory_barrier
:
6703 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6705 case nir_intrinsic_memory_barrier_buffer
:
6706 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6708 case nir_intrinsic_memory_barrier_image
:
6709 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6711 case nir_intrinsic_memory_barrier_tcs_patch
:
6712 case nir_intrinsic_memory_barrier_shared
:
6713 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6716 unreachable("Unimplemented memory barrier intrinsic");
6721 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6723 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6724 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6725 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6726 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6727 Builder
bld(ctx
->program
, ctx
->block
);
6729 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6730 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6731 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6734 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6736 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6737 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6738 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6739 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6740 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6742 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6743 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6746 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6748 unsigned offset
= nir_intrinsic_base(instr
);
6749 Builder
bld(ctx
->program
, ctx
->block
);
6750 Operand m
= load_lds_size_m0(bld
);
6751 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6752 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6754 unsigned num_operands
= 3;
6755 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6756 switch(instr
->intrinsic
) {
6757 case nir_intrinsic_shared_atomic_add
:
6758 op32
= aco_opcode::ds_add_u32
;
6759 op64
= aco_opcode::ds_add_u64
;
6760 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6761 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6763 case nir_intrinsic_shared_atomic_imin
:
6764 op32
= aco_opcode::ds_min_i32
;
6765 op64
= aco_opcode::ds_min_i64
;
6766 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6767 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6769 case nir_intrinsic_shared_atomic_umin
:
6770 op32
= aco_opcode::ds_min_u32
;
6771 op64
= aco_opcode::ds_min_u64
;
6772 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6773 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6775 case nir_intrinsic_shared_atomic_imax
:
6776 op32
= aco_opcode::ds_max_i32
;
6777 op64
= aco_opcode::ds_max_i64
;
6778 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6779 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6781 case nir_intrinsic_shared_atomic_umax
:
6782 op32
= aco_opcode::ds_max_u32
;
6783 op64
= aco_opcode::ds_max_u64
;
6784 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6785 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6787 case nir_intrinsic_shared_atomic_and
:
6788 op32
= aco_opcode::ds_and_b32
;
6789 op64
= aco_opcode::ds_and_b64
;
6790 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6791 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6793 case nir_intrinsic_shared_atomic_or
:
6794 op32
= aco_opcode::ds_or_b32
;
6795 op64
= aco_opcode::ds_or_b64
;
6796 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6797 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6799 case nir_intrinsic_shared_atomic_xor
:
6800 op32
= aco_opcode::ds_xor_b32
;
6801 op64
= aco_opcode::ds_xor_b64
;
6802 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6803 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6805 case nir_intrinsic_shared_atomic_exchange
:
6806 op32
= aco_opcode::ds_write_b32
;
6807 op64
= aco_opcode::ds_write_b64
;
6808 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6809 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6811 case nir_intrinsic_shared_atomic_comp_swap
:
6812 op32
= aco_opcode::ds_cmpst_b32
;
6813 op64
= aco_opcode::ds_cmpst_b64
;
6814 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6815 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6819 unreachable("Unhandled shared atomic intrinsic");
6822 /* return the previous value if dest is ever used */
6823 bool return_previous
= false;
6824 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6825 return_previous
= true;
6828 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6829 return_previous
= true;
6834 if (data
.size() == 1) {
6835 assert(instr
->dest
.ssa
.bit_size
== 32);
6836 op
= return_previous
? op32_rtn
: op32
;
6838 assert(instr
->dest
.ssa
.bit_size
== 64);
6839 op
= return_previous
? op64_rtn
: op64
;
6842 if (offset
> 65535) {
6843 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6847 aco_ptr
<DS_instruction
> ds
;
6848 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6849 ds
->operands
[0] = Operand(address
);
6850 ds
->operands
[1] = Operand(data
);
6851 if (num_operands
== 4)
6852 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6853 ds
->operands
[num_operands
- 1] = m
;
6854 ds
->offset0
= offset
;
6855 if (return_previous
)
6856 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6857 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6860 Temp
get_scratch_resource(isel_context
*ctx
)
6862 Builder
bld(ctx
->program
, ctx
->block
);
6863 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6864 if (ctx
->stage
!= compute_cs
)
6865 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6867 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6868 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6870 if (ctx
->program
->chip_class
>= GFX10
) {
6871 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6872 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6873 S_008F0C_RESOURCE_LEVEL(1);
6874 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6875 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6876 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6879 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6880 if (ctx
->program
->chip_class
<= GFX8
)
6881 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6883 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6886 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6887 Builder
bld(ctx
->program
, ctx
->block
);
6888 Temp rsrc
= get_scratch_resource(ctx
);
6889 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6890 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6892 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6893 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6894 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6895 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6896 info
.swizzle_component_size
= 16;
6897 info
.can_reorder
= false;
6898 info
.soffset
= ctx
->program
->scratch_offset
;
6899 emit_mubuf_load(ctx
, bld
, &info
);
6902 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6903 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6904 Builder
bld(ctx
->program
, ctx
->block
);
6905 Temp rsrc
= get_scratch_resource(ctx
);
6906 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6907 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6909 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6910 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6914 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6915 int num_bytes
= count
* elem_size_bytes
;
6917 if (num_bytes
> 16) {
6918 assert(elem_size_bytes
== 8);
6919 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6924 // TODO: check alignment of sub-dword stores
6925 // TODO: split 3 bytes. there is no store instruction for that
6928 if (count
!= instr
->num_components
) {
6929 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6930 for (int i
= 0; i
< count
; i
++) {
6931 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6932 vec
->operands
[i
] = Operand(elem
);
6934 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6935 vec
->definitions
[0] = Definition(write_data
);
6936 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6942 switch (num_bytes
) {
6944 op
= aco_opcode::buffer_store_dword
;
6947 op
= aco_opcode::buffer_store_dwordx2
;
6950 op
= aco_opcode::buffer_store_dwordx3
;
6953 op
= aco_opcode::buffer_store_dwordx4
;
6956 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6959 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6963 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6964 uint8_t log2_ps_iter_samples
;
6965 if (ctx
->program
->info
->ps
.force_persample
) {
6966 log2_ps_iter_samples
=
6967 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6969 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6972 /* The bit pattern matches that used by fixed function fragment
6974 static const unsigned ps_iter_masks
[] = {
6975 0xffff, /* not used */
6981 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6983 Builder
bld(ctx
->program
, ctx
->block
);
6985 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6986 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6987 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6988 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6989 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6990 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6993 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6994 Builder
bld(ctx
->program
, ctx
->block
);
6996 unsigned stream
= nir_intrinsic_stream_id(instr
);
6997 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6998 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6999 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
7002 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
7004 unsigned num_components
=
7005 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
7006 assert(num_components
);
7008 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
7009 unsigned stream_offset
= 0;
7010 for (unsigned i
= 0; i
< stream
; i
++) {
7011 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
7012 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
7015 /* Limit on the stride field for <= GFX7. */
7016 assert(stride
< (1 << 14));
7018 Temp gsvs_dwords
[4];
7019 for (unsigned i
= 0; i
< 4; i
++)
7020 gsvs_dwords
[i
] = bld
.tmp(s1
);
7021 bld
.pseudo(aco_opcode::p_split_vector
,
7022 Definition(gsvs_dwords
[0]),
7023 Definition(gsvs_dwords
[1]),
7024 Definition(gsvs_dwords
[2]),
7025 Definition(gsvs_dwords
[3]),
7028 if (stream_offset
) {
7029 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
7031 Temp carry
= bld
.tmp(s1
);
7032 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
7033 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
7036 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
7037 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
7039 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7040 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
7042 unsigned offset
= 0;
7043 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
7044 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
7047 for (unsigned j
= 0; j
< 4; j
++) {
7048 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
7051 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
7052 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
7053 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
7054 if (const_offset
>= 4096u) {
7055 if (vaddr_offset
.isUndefined())
7056 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
7058 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
7059 const_offset
%= 4096u;
7062 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
7063 mtbuf
->operands
[0] = Operand(gsvs_ring
);
7064 mtbuf
->operands
[1] = vaddr_offset
;
7065 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
7066 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
7067 mtbuf
->offen
= !vaddr_offset
.isUndefined();
7068 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
7069 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
7070 mtbuf
->offset
= const_offset
;
7073 mtbuf
->barrier
= barrier_gs_data
;
7074 mtbuf
->can_reorder
= true;
7075 bld
.insert(std::move(mtbuf
));
7078 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
7081 /* outputs for the next vertex are undefined and keeping them around can
7082 * create invalid IR with control flow */
7083 ctx
->outputs
.mask
[i
] = 0;
7086 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7089 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7091 Builder
bld(ctx
->program
, ctx
->block
);
7093 if (cluster_size
== 1) {
7095 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7096 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7097 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7098 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7099 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7100 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7101 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7102 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7103 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7104 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7105 //subgroupAnd(val) -> (exec & ~val) == 0
7106 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7107 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7108 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7109 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7110 //subgroupOr(val) -> (val & exec) != 0
7111 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7112 return bool_to_vector_condition(ctx
, tmp
);
7113 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7114 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7115 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7116 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7117 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7118 return bool_to_vector_condition(ctx
, tmp
);
7120 //subgroupClustered{And,Or,Xor}(val, n) ->
7121 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7122 //cluster_offset = ~(n - 1) & lane_id
7123 //cluster_mask = ((1 << n) - 1)
7124 //subgroupClusteredAnd():
7125 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7126 //subgroupClusteredOr():
7127 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7128 //subgroupClusteredXor():
7129 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7130 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7131 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7134 if (op
== nir_op_iand
)
7135 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7137 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7139 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7141 if (ctx
->program
->chip_class
<= GFX7
)
7142 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7143 else if (ctx
->program
->wave_size
== 64)
7144 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7146 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7147 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7148 if (cluster_mask
!= 0xffffffff)
7149 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7151 Definition cmp_def
= Definition();
7152 if (op
== nir_op_iand
) {
7153 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7154 } else if (op
== nir_op_ior
) {
7155 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7156 } else if (op
== nir_op_ixor
) {
7157 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7158 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7159 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7161 cmp_def
.setHint(vcc
);
7162 return cmp_def
.getTemp();
7166 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7168 Builder
bld(ctx
->program
, ctx
->block
);
7170 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7171 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7172 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7174 if (op
== nir_op_iand
)
7175 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7177 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7179 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7180 Temp lo
= lohi
.def(0).getTemp();
7181 Temp hi
= lohi
.def(1).getTemp();
7182 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7184 Definition cmp_def
= Definition();
7185 if (op
== nir_op_iand
)
7186 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7187 else if (op
== nir_op_ior
)
7188 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7189 else if (op
== nir_op_ixor
)
7190 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7191 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7192 cmp_def
.setHint(vcc
);
7193 return cmp_def
.getTemp();
7196 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7198 Builder
bld(ctx
->program
, ctx
->block
);
7200 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7201 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7202 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7203 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7204 if (op
== nir_op_iand
)
7205 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7206 else if (op
== nir_op_ior
)
7207 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7208 else if (op
== nir_op_ixor
)
7209 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7215 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7217 Builder
bld(ctx
->program
, ctx
->block
);
7218 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7219 if (src
.regClass().type() == RegType::vgpr
) {
7220 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7221 } else if (src
.regClass() == s1
) {
7222 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7223 } else if (src
.regClass() == s2
) {
7224 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7226 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7227 nir_print_instr(&instr
->instr
, stderr
);
7228 fprintf(stderr
, "\n");
7232 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7234 Builder
bld(ctx
->program
, ctx
->block
);
7235 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7236 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7237 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7239 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7240 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7241 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7242 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7245 if (ctx
->program
->chip_class
>= GFX8
) {
7246 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7247 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7248 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7249 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7250 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7251 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7253 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7254 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7255 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7256 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7257 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7258 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7259 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7260 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7261 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7262 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7265 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7266 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7267 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7268 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7269 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7270 Temp wqm1
= bld
.tmp(v1
);
7271 emit_wqm(ctx
, tmp1
, wqm1
, true);
7272 Temp wqm2
= bld
.tmp(v1
);
7273 emit_wqm(ctx
, tmp2
, wqm2
, true);
7274 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7278 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7280 Builder
bld(ctx
->program
, ctx
->block
);
7281 switch(instr
->intrinsic
) {
7282 case nir_intrinsic_load_barycentric_sample
:
7283 case nir_intrinsic_load_barycentric_pixel
:
7284 case nir_intrinsic_load_barycentric_centroid
: {
7285 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7286 Temp bary
= Temp(0, s2
);
7288 case INTERP_MODE_SMOOTH
:
7289 case INTERP_MODE_NONE
:
7290 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7291 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7292 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7293 bary
= ctx
->persp_centroid
;
7294 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7295 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7297 case INTERP_MODE_NOPERSPECTIVE
:
7298 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7299 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7300 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7301 bary
= ctx
->linear_centroid
;
7302 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7303 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7308 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7309 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7310 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7311 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7312 Operand(p1
), Operand(p2
));
7313 emit_split_vector(ctx
, dst
, 2);
7316 case nir_intrinsic_load_barycentric_model
: {
7317 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7319 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7320 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7321 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7322 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7323 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7324 Operand(p1
), Operand(p2
), Operand(p3
));
7325 emit_split_vector(ctx
, dst
, 3);
7328 case nir_intrinsic_load_barycentric_at_sample
: {
7329 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7330 switch (ctx
->options
->key
.fs
.num_samples
) {
7331 case 2: sample_pos_offset
+= 1 << 3; break;
7332 case 4: sample_pos_offset
+= 3 << 3; break;
7333 case 8: sample_pos_offset
+= 7 << 3; break;
7337 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7338 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7339 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7340 if (addr
.type() == RegType::sgpr
) {
7343 sample_pos_offset
+= const_addr
->u32
<< 3;
7344 offset
= Operand(sample_pos_offset
);
7345 } else if (ctx
->options
->chip_class
>= GFX9
) {
7346 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7348 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7349 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7352 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7353 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7355 } else if (ctx
->options
->chip_class
>= GFX9
) {
7356 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7357 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7358 } else if (ctx
->options
->chip_class
>= GFX7
) {
7359 /* addr += private_segment_buffer + sample_pos_offset */
7360 Temp tmp0
= bld
.tmp(s1
);
7361 Temp tmp1
= bld
.tmp(s1
);
7362 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7363 Definition scc_tmp
= bld
.def(s1
, scc
);
7364 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7365 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7366 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7367 Temp pck0
= bld
.tmp(v1
);
7368 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7369 tmp1
= as_vgpr(ctx
, tmp1
);
7370 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7371 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7373 /* sample_pos = flat_load_dwordx2 addr */
7374 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7376 assert(ctx
->options
->chip_class
== GFX6
);
7378 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7379 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7380 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7382 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7383 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7385 sample_pos
= bld
.tmp(v2
);
7387 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7388 load
->definitions
[0] = Definition(sample_pos
);
7389 load
->operands
[0] = Operand(rsrc
);
7390 load
->operands
[1] = Operand(addr
);
7391 load
->operands
[2] = Operand(0u);
7392 load
->offset
= sample_pos_offset
;
7394 load
->addr64
= true;
7397 load
->disable_wqm
= false;
7398 load
->barrier
= barrier_none
;
7399 load
->can_reorder
= true;
7400 ctx
->block
->instructions
.emplace_back(std::move(load
));
7403 /* sample_pos -= 0.5 */
7404 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7405 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7406 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7407 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7408 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7410 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7413 case nir_intrinsic_load_barycentric_at_offset
: {
7414 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7415 RegClass rc
= RegClass(offset
.type(), 1);
7416 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7417 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7418 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7421 case nir_intrinsic_load_front_face
: {
7422 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7423 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7426 case nir_intrinsic_load_view_index
: {
7427 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7428 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7429 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7435 case nir_intrinsic_load_layer_id
: {
7436 unsigned idx
= nir_intrinsic_base(instr
);
7437 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7438 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7441 case nir_intrinsic_load_frag_coord
: {
7442 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7445 case nir_intrinsic_load_sample_pos
: {
7446 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7447 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7448 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7449 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7450 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7453 case nir_intrinsic_load_tess_coord
:
7454 visit_load_tess_coord(ctx
, instr
);
7456 case nir_intrinsic_load_interpolated_input
:
7457 visit_load_interpolated_input(ctx
, instr
);
7459 case nir_intrinsic_store_output
:
7460 visit_store_output(ctx
, instr
);
7462 case nir_intrinsic_load_input
:
7463 case nir_intrinsic_load_input_vertex
:
7464 visit_load_input(ctx
, instr
);
7466 case nir_intrinsic_load_output
:
7467 visit_load_output(ctx
, instr
);
7469 case nir_intrinsic_load_per_vertex_input
:
7470 visit_load_per_vertex_input(ctx
, instr
);
7472 case nir_intrinsic_load_per_vertex_output
:
7473 visit_load_per_vertex_output(ctx
, instr
);
7475 case nir_intrinsic_store_per_vertex_output
:
7476 visit_store_per_vertex_output(ctx
, instr
);
7478 case nir_intrinsic_load_ubo
:
7479 visit_load_ubo(ctx
, instr
);
7481 case nir_intrinsic_load_push_constant
:
7482 visit_load_push_constant(ctx
, instr
);
7484 case nir_intrinsic_load_constant
:
7485 visit_load_constant(ctx
, instr
);
7487 case nir_intrinsic_vulkan_resource_index
:
7488 visit_load_resource(ctx
, instr
);
7490 case nir_intrinsic_discard
:
7491 visit_discard(ctx
, instr
);
7493 case nir_intrinsic_discard_if
:
7494 visit_discard_if(ctx
, instr
);
7496 case nir_intrinsic_load_shared
:
7497 visit_load_shared(ctx
, instr
);
7499 case nir_intrinsic_store_shared
:
7500 visit_store_shared(ctx
, instr
);
7502 case nir_intrinsic_shared_atomic_add
:
7503 case nir_intrinsic_shared_atomic_imin
:
7504 case nir_intrinsic_shared_atomic_umin
:
7505 case nir_intrinsic_shared_atomic_imax
:
7506 case nir_intrinsic_shared_atomic_umax
:
7507 case nir_intrinsic_shared_atomic_and
:
7508 case nir_intrinsic_shared_atomic_or
:
7509 case nir_intrinsic_shared_atomic_xor
:
7510 case nir_intrinsic_shared_atomic_exchange
:
7511 case nir_intrinsic_shared_atomic_comp_swap
:
7512 visit_shared_atomic(ctx
, instr
);
7514 case nir_intrinsic_image_deref_load
:
7515 visit_image_load(ctx
, instr
);
7517 case nir_intrinsic_image_deref_store
:
7518 visit_image_store(ctx
, instr
);
7520 case nir_intrinsic_image_deref_atomic_add
:
7521 case nir_intrinsic_image_deref_atomic_umin
:
7522 case nir_intrinsic_image_deref_atomic_imin
:
7523 case nir_intrinsic_image_deref_atomic_umax
:
7524 case nir_intrinsic_image_deref_atomic_imax
:
7525 case nir_intrinsic_image_deref_atomic_and
:
7526 case nir_intrinsic_image_deref_atomic_or
:
7527 case nir_intrinsic_image_deref_atomic_xor
:
7528 case nir_intrinsic_image_deref_atomic_exchange
:
7529 case nir_intrinsic_image_deref_atomic_comp_swap
:
7530 visit_image_atomic(ctx
, instr
);
7532 case nir_intrinsic_image_deref_size
:
7533 visit_image_size(ctx
, instr
);
7535 case nir_intrinsic_load_ssbo
:
7536 visit_load_ssbo(ctx
, instr
);
7538 case nir_intrinsic_store_ssbo
:
7539 visit_store_ssbo(ctx
, instr
);
7541 case nir_intrinsic_load_global
:
7542 visit_load_global(ctx
, instr
);
7544 case nir_intrinsic_store_global
:
7545 visit_store_global(ctx
, instr
);
7547 case nir_intrinsic_global_atomic_add
:
7548 case nir_intrinsic_global_atomic_imin
:
7549 case nir_intrinsic_global_atomic_umin
:
7550 case nir_intrinsic_global_atomic_imax
:
7551 case nir_intrinsic_global_atomic_umax
:
7552 case nir_intrinsic_global_atomic_and
:
7553 case nir_intrinsic_global_atomic_or
:
7554 case nir_intrinsic_global_atomic_xor
:
7555 case nir_intrinsic_global_atomic_exchange
:
7556 case nir_intrinsic_global_atomic_comp_swap
:
7557 visit_global_atomic(ctx
, instr
);
7559 case nir_intrinsic_ssbo_atomic_add
:
7560 case nir_intrinsic_ssbo_atomic_imin
:
7561 case nir_intrinsic_ssbo_atomic_umin
:
7562 case nir_intrinsic_ssbo_atomic_imax
:
7563 case nir_intrinsic_ssbo_atomic_umax
:
7564 case nir_intrinsic_ssbo_atomic_and
:
7565 case nir_intrinsic_ssbo_atomic_or
:
7566 case nir_intrinsic_ssbo_atomic_xor
:
7567 case nir_intrinsic_ssbo_atomic_exchange
:
7568 case nir_intrinsic_ssbo_atomic_comp_swap
:
7569 visit_atomic_ssbo(ctx
, instr
);
7571 case nir_intrinsic_load_scratch
:
7572 visit_load_scratch(ctx
, instr
);
7574 case nir_intrinsic_store_scratch
:
7575 visit_store_scratch(ctx
, instr
);
7577 case nir_intrinsic_get_buffer_size
:
7578 visit_get_buffer_size(ctx
, instr
);
7580 case nir_intrinsic_control_barrier
: {
7581 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7582 /* GFX6 only (thanks to a hw bug workaround):
7583 * The real barrier instruction isn’t needed, because an entire patch
7584 * always fits into a single wave.
7589 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7590 bld
.sopp(aco_opcode::s_barrier
);
7594 case nir_intrinsic_memory_barrier_tcs_patch
:
7595 case nir_intrinsic_group_memory_barrier
:
7596 case nir_intrinsic_memory_barrier
:
7597 case nir_intrinsic_memory_barrier_buffer
:
7598 case nir_intrinsic_memory_barrier_image
:
7599 case nir_intrinsic_memory_barrier_shared
:
7600 emit_memory_barrier(ctx
, instr
);
7602 case nir_intrinsic_load_num_work_groups
: {
7603 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7604 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7605 emit_split_vector(ctx
, dst
, 3);
7608 case nir_intrinsic_load_local_invocation_id
: {
7609 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7610 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7611 emit_split_vector(ctx
, dst
, 3);
7614 case nir_intrinsic_load_work_group_id
: {
7615 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7616 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7617 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7618 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7619 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7620 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7621 emit_split_vector(ctx
, dst
, 3);
7624 case nir_intrinsic_load_local_invocation_index
: {
7625 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7627 /* The tg_size bits [6:11] contain the subgroup id,
7628 * we need this multiplied by the wave size, and then OR the thread id to it.
7630 if (ctx
->program
->wave_size
== 64) {
7631 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7632 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7633 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7634 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7636 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7637 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7638 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7639 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7643 case nir_intrinsic_load_subgroup_id
: {
7644 if (ctx
->stage
== compute_cs
) {
7645 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7646 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7648 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7652 case nir_intrinsic_load_subgroup_invocation
: {
7653 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7656 case nir_intrinsic_load_num_subgroups
: {
7657 if (ctx
->stage
== compute_cs
)
7658 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7659 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7661 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7664 case nir_intrinsic_ballot
: {
7665 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7666 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7667 Definition tmp
= bld
.def(dst
.regClass());
7668 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7669 if (instr
->src
[0].ssa
->bit_size
== 1) {
7670 assert(src
.regClass() == bld
.lm
);
7671 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7672 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7673 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7674 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7675 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7677 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7678 nir_print_instr(&instr
->instr
, stderr
);
7679 fprintf(stderr
, "\n");
7681 if (dst
.size() != bld
.lm
.size()) {
7682 /* Wave32 with ballot size set to 64 */
7683 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7685 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7688 case nir_intrinsic_shuffle
:
7689 case nir_intrinsic_read_invocation
: {
7690 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7691 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7692 emit_uniform_subgroup(ctx
, instr
, src
);
7694 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7695 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7696 tid
= bld
.as_uniform(tid
);
7697 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7698 if (src
.regClass() == v1
) {
7699 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7700 } else if (src
.regClass() == v2
) {
7701 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7702 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7703 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7704 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7705 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7706 emit_split_vector(ctx
, dst
, 2);
7707 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7708 assert(src
.regClass() == bld
.lm
);
7709 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7710 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7711 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7712 assert(src
.regClass() == bld
.lm
);
7714 if (ctx
->program
->chip_class
<= GFX7
)
7715 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7716 else if (ctx
->program
->wave_size
== 64)
7717 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7719 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7720 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7721 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7722 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7724 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7725 nir_print_instr(&instr
->instr
, stderr
);
7726 fprintf(stderr
, "\n");
7731 case nir_intrinsic_load_sample_id
: {
7732 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7733 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7736 case nir_intrinsic_load_sample_mask_in
: {
7737 visit_load_sample_mask_in(ctx
, instr
);
7740 case nir_intrinsic_read_first_invocation
: {
7741 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7742 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7743 if (src
.regClass() == v1
) {
7745 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7747 } else if (src
.regClass() == v2
) {
7748 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7749 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7750 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7751 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7752 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7753 emit_split_vector(ctx
, dst
, 2);
7754 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7755 assert(src
.regClass() == bld
.lm
);
7756 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7757 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7758 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7759 } else if (src
.regClass() == s1
) {
7760 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7761 } else if (src
.regClass() == s2
) {
7762 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7764 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7765 nir_print_instr(&instr
->instr
, stderr
);
7766 fprintf(stderr
, "\n");
7770 case nir_intrinsic_vote_all
: {
7771 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7772 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7773 assert(src
.regClass() == bld
.lm
);
7774 assert(dst
.regClass() == bld
.lm
);
7776 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7777 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7778 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7781 case nir_intrinsic_vote_any
: {
7782 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7783 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7784 assert(src
.regClass() == bld
.lm
);
7785 assert(dst
.regClass() == bld
.lm
);
7787 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7788 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7791 case nir_intrinsic_reduce
:
7792 case nir_intrinsic_inclusive_scan
:
7793 case nir_intrinsic_exclusive_scan
: {
7794 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7795 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7796 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7797 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7798 nir_intrinsic_cluster_size(instr
) : 0;
7799 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7801 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7802 emit_uniform_subgroup(ctx
, instr
, src
);
7803 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7804 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7806 else if (op
== nir_op_iadd
)
7808 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7810 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7812 switch (instr
->intrinsic
) {
7813 case nir_intrinsic_reduce
:
7814 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7816 case nir_intrinsic_exclusive_scan
:
7817 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7819 case nir_intrinsic_inclusive_scan
:
7820 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7825 } else if (cluster_size
== 1) {
7826 bld
.copy(Definition(dst
), src
);
7828 src
= as_vgpr(ctx
, src
);
7832 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7847 unreachable("unknown reduction op");
7852 switch (instr
->intrinsic
) {
7853 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7854 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7855 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7857 unreachable("unknown reduce intrinsic");
7860 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7861 reduce
->operands
[0] = Operand(src
);
7862 // filled in by aco_reduce_assign.cpp, used internally as part of the
7864 assert(dst
.size() == 1 || dst
.size() == 2);
7865 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7866 reduce
->operands
[2] = Operand(v1
.as_linear());
7868 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7869 reduce
->definitions
[0] = Definition(tmp_dst
);
7870 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7871 reduce
->definitions
[2] = Definition();
7872 reduce
->definitions
[3] = Definition(scc
, s1
);
7873 reduce
->definitions
[4] = Definition();
7874 reduce
->reduce_op
= reduce_op
;
7875 reduce
->cluster_size
= cluster_size
;
7876 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7878 emit_wqm(ctx
, tmp_dst
, dst
);
7882 case nir_intrinsic_quad_broadcast
: {
7883 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7884 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7885 emit_uniform_subgroup(ctx
, instr
, src
);
7887 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7888 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7889 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7891 if (instr
->dest
.ssa
.bit_size
== 1) {
7892 assert(src
.regClass() == bld
.lm
);
7893 assert(dst
.regClass() == bld
.lm
);
7894 uint32_t half_mask
= 0x11111111u
<< lane
;
7895 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7896 Temp tmp
= bld
.tmp(bld
.lm
);
7897 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7898 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7899 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7900 emit_wqm(ctx
, tmp
, dst
);
7901 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7902 if (ctx
->program
->chip_class
>= GFX8
)
7903 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7905 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7906 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7907 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7908 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7909 if (ctx
->program
->chip_class
>= GFX8
) {
7910 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7911 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7913 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7914 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7916 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7917 emit_split_vector(ctx
, dst
, 2);
7919 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7920 nir_print_instr(&instr
->instr
, stderr
);
7921 fprintf(stderr
, "\n");
7926 case nir_intrinsic_quad_swap_horizontal
:
7927 case nir_intrinsic_quad_swap_vertical
:
7928 case nir_intrinsic_quad_swap_diagonal
:
7929 case nir_intrinsic_quad_swizzle_amd
: {
7930 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7931 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7932 emit_uniform_subgroup(ctx
, instr
, src
);
7935 uint16_t dpp_ctrl
= 0;
7936 switch (instr
->intrinsic
) {
7937 case nir_intrinsic_quad_swap_horizontal
:
7938 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7940 case nir_intrinsic_quad_swap_vertical
:
7941 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7943 case nir_intrinsic_quad_swap_diagonal
:
7944 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7946 case nir_intrinsic_quad_swizzle_amd
:
7947 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7952 if (ctx
->program
->chip_class
< GFX8
)
7953 dpp_ctrl
|= (1 << 15);
7955 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7956 if (instr
->dest
.ssa
.bit_size
== 1) {
7957 assert(src
.regClass() == bld
.lm
);
7958 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7959 if (ctx
->program
->chip_class
>= GFX8
)
7960 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7962 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7963 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7964 emit_wqm(ctx
, tmp
, dst
);
7965 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7967 if (ctx
->program
->chip_class
>= GFX8
)
7968 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7970 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7971 emit_wqm(ctx
, tmp
, dst
);
7972 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7973 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7974 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7975 if (ctx
->program
->chip_class
>= GFX8
) {
7976 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7977 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7979 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7980 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7982 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7983 emit_split_vector(ctx
, dst
, 2);
7985 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7986 nir_print_instr(&instr
->instr
, stderr
);
7987 fprintf(stderr
, "\n");
7991 case nir_intrinsic_masked_swizzle_amd
: {
7992 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7993 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7994 emit_uniform_subgroup(ctx
, instr
, src
);
7997 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7998 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7999 if (dst
.regClass() == v1
) {
8001 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
8003 } else if (dst
.regClass() == v2
) {
8004 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8005 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8006 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
8007 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
8008 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8009 emit_split_vector(ctx
, dst
, 2);
8011 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8012 nir_print_instr(&instr
->instr
, stderr
);
8013 fprintf(stderr
, "\n");
8017 case nir_intrinsic_write_invocation_amd
: {
8018 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
8019 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
8020 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
8021 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8022 if (dst
.regClass() == v1
) {
8023 /* src2 is ignored for writelane. RA assigns the same reg for dst */
8024 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
8025 } else if (dst
.regClass() == v2
) {
8026 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
8027 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
8028 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
8029 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
8030 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
8031 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
8032 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8033 emit_split_vector(ctx
, dst
, 2);
8035 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8036 nir_print_instr(&instr
->instr
, stderr
);
8037 fprintf(stderr
, "\n");
8041 case nir_intrinsic_mbcnt_amd
: {
8042 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8043 RegClass rc
= RegClass(src
.type(), 1);
8044 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
8045 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
8046 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8047 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
8048 emit_wqm(ctx
, wqm_tmp
, dst
);
8051 case nir_intrinsic_load_helper_invocation
: {
8052 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8053 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
8054 ctx
->block
->kind
|= block_kind_needs_lowering
;
8055 ctx
->program
->needs_exact
= true;
8058 case nir_intrinsic_is_helper_invocation
: {
8059 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8060 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
8061 ctx
->block
->kind
|= block_kind_needs_lowering
;
8062 ctx
->program
->needs_exact
= true;
8065 case nir_intrinsic_demote
:
8066 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
8068 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8069 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8070 ctx
->block
->kind
|= block_kind_uses_demote
;
8071 ctx
->program
->needs_exact
= true;
8073 case nir_intrinsic_demote_if
: {
8074 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8075 assert(src
.regClass() == bld
.lm
);
8076 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
8077 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8079 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8080 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8081 ctx
->block
->kind
|= block_kind_uses_demote
;
8082 ctx
->program
->needs_exact
= true;
8085 case nir_intrinsic_first_invocation
: {
8086 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8087 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8090 case nir_intrinsic_shader_clock
:
8091 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
8092 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8094 case nir_intrinsic_load_vertex_id_zero_base
: {
8095 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8096 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8099 case nir_intrinsic_load_first_vertex
: {
8100 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8101 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8104 case nir_intrinsic_load_base_instance
: {
8105 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8106 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8109 case nir_intrinsic_load_instance_id
: {
8110 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8111 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8114 case nir_intrinsic_load_draw_id
: {
8115 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8116 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8119 case nir_intrinsic_load_invocation_id
: {
8120 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8122 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8123 if (ctx
->options
->chip_class
>= GFX10
)
8124 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8126 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8127 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8128 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8129 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8131 unreachable("Unsupported stage for load_invocation_id");
8136 case nir_intrinsic_load_primitive_id
: {
8137 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8139 switch (ctx
->shader
->info
.stage
) {
8140 case MESA_SHADER_GEOMETRY
:
8141 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8143 case MESA_SHADER_TESS_CTRL
:
8144 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8146 case MESA_SHADER_TESS_EVAL
:
8147 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8150 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8155 case nir_intrinsic_load_patch_vertices_in
: {
8156 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8157 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8159 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8160 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8163 case nir_intrinsic_emit_vertex_with_counter
: {
8164 visit_emit_vertex_with_counter(ctx
, instr
);
8167 case nir_intrinsic_end_primitive_with_counter
: {
8168 unsigned stream
= nir_intrinsic_stream_id(instr
);
8169 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8172 case nir_intrinsic_set_vertex_count
: {
8173 /* unused, the HW keeps track of this for us */
8177 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8178 nir_print_instr(&instr
->instr
, stderr
);
8179 fprintf(stderr
, "\n");
8187 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8188 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8189 enum glsl_base_type
*stype
)
8191 nir_deref_instr
*texture_deref_instr
= NULL
;
8192 nir_deref_instr
*sampler_deref_instr
= NULL
;
8195 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8196 switch (instr
->src
[i
].src_type
) {
8197 case nir_tex_src_texture_deref
:
8198 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8200 case nir_tex_src_sampler_deref
:
8201 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8203 case nir_tex_src_plane
:
8204 plane
= nir_src_as_int(instr
->src
[i
].src
);
8211 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8213 if (!sampler_deref_instr
)
8214 sampler_deref_instr
= texture_deref_instr
;
8217 assert(instr
->op
!= nir_texop_txf_ms
&&
8218 instr
->op
!= nir_texop_samples_identical
);
8219 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8220 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8221 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8222 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8223 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8224 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8226 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8229 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8231 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8232 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8233 Builder
bld(ctx
->program
, ctx
->block
);
8235 /* to avoid unnecessary moves, we split and recombine sampler and image */
8236 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8237 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8238 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8239 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8240 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8241 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8242 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8243 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8245 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8246 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8247 img
[0], img
[1], img
[2], img
[3],
8248 img
[4], img
[5], img
[6], img
[7]);
8249 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8250 samp
[0], samp
[1], samp
[2], samp
[3]);
8253 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8254 instr
->op
== nir_texop_samples_identical
))
8255 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8258 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8259 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8261 Builder
bld(ctx
->program
, ctx
->block
);
8263 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8264 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8265 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8267 Operand
neg_one(0xbf800000u
);
8268 Operand
one(0x3f800000u
);
8269 Operand
two(0x40000000u
);
8270 Operand
four(0x40800000u
);
8272 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8273 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8274 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8276 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8277 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8278 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8279 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8282 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8283 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8284 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8286 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8289 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8290 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8291 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8294 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8295 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8297 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8298 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8301 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8303 Builder
bld(ctx
->program
, ctx
->block
);
8304 Temp ma
, tc
, sc
, id
;
8307 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8309 // see comment in ac_prepare_cube_coords()
8310 if (ctx
->options
->chip_class
<= GFX8
)
8311 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8314 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8316 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8317 vop3a
->operands
[0] = Operand(ma
);
8318 vop3a
->abs
[0] = true;
8319 Temp invma
= bld
.tmp(v1
);
8320 vop3a
->definitions
[0] = Definition(invma
);
8321 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8323 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8325 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8327 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8329 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8331 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8334 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8335 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8337 for (unsigned i
= 0; i
< 2; i
++) {
8338 // see comment in ac_prepare_cube_coords()
8340 Temp deriv_sc
, deriv_tc
;
8341 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8342 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8344 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8346 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8347 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8348 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8349 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8350 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8351 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8352 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8355 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8356 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8360 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8367 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8369 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8371 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8372 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8375 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8376 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8377 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8381 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8383 Builder
bld(ctx
->program
, ctx
->block
);
8384 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8385 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8386 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8387 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8388 std::vector
<Temp
> coords
;
8389 std::vector
<Temp
> derivs
;
8390 nir_const_value
*sample_index_cv
= NULL
;
8391 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8392 enum glsl_base_type stype
;
8393 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8395 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8396 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8397 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8398 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8400 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8401 switch (instr
->src
[i
].src_type
) {
8402 case nir_tex_src_coord
: {
8403 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8404 for (unsigned i
= 0; i
< coord
.size(); i
++)
8405 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8408 case nir_tex_src_bias
:
8409 if (instr
->op
== nir_texop_txb
) {
8410 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8414 case nir_tex_src_lod
: {
8415 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8417 if (val
&& val
->f32
<= 0.0) {
8420 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8425 case nir_tex_src_comparator
:
8426 if (instr
->is_shadow
) {
8427 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8431 case nir_tex_src_offset
:
8432 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8433 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8436 case nir_tex_src_ddx
:
8437 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8440 case nir_tex_src_ddy
:
8441 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8444 case nir_tex_src_ms_index
:
8445 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8446 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8447 has_sample_index
= true;
8449 case nir_tex_src_texture_offset
:
8450 case nir_tex_src_sampler_offset
:
8456 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8457 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8459 if (instr
->op
== nir_texop_texture_samples
) {
8460 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8462 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8463 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8464 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8465 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8467 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8468 samples
, Operand(1u), bld
.scc(is_msaa
));
8472 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8473 aco_ptr
<Instruction
> tmp_instr
;
8474 Temp acc
, pack
= Temp();
8476 uint32_t pack_const
= 0;
8477 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8478 if (!const_offset
[i
])
8480 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8483 if (offset
.type() == RegType::sgpr
) {
8484 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8485 if (const_offset
[i
])
8488 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8489 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8492 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8495 if (pack
== Temp()) {
8498 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8502 if (pack_const
&& pack
!= Temp())
8503 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8505 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8506 if (const_offset
[i
])
8509 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8510 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8513 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8516 if (pack
== Temp()) {
8519 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8523 if (pack_const
&& pack
!= Temp())
8524 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8526 if (pack_const
&& pack
== Temp())
8527 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8528 else if (pack
== Temp())
8534 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8535 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8537 /* pack derivatives */
8538 if (has_ddx
|| has_ddy
) {
8539 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8540 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8541 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8542 derivs
= {ddx
, zero
, ddy
, zero
};
8544 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8545 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8546 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8547 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8552 if (instr
->coord_components
> 1 &&
8553 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8555 instr
->op
!= nir_texop_txf
)
8556 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8558 if (instr
->coord_components
> 2 &&
8559 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8560 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8561 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8562 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8564 instr
->op
!= nir_texop_txf
&&
8565 instr
->op
!= nir_texop_txf_ms
&&
8566 instr
->op
!= nir_texop_fragment_fetch
&&
8567 instr
->op
!= nir_texop_fragment_mask_fetch
)
8568 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8570 if (ctx
->options
->chip_class
== GFX9
&&
8571 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8572 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8573 assert(coords
.size() > 0 && coords
.size() < 3);
8575 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8576 Operand((uint32_t) 0) :
8577 Operand((uint32_t) 0x3f000000)));
8580 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8582 if (instr
->op
== nir_texop_samples_identical
)
8583 resource
= fmask_ptr
;
8585 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8586 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8587 instr
->op
!= nir_texop_txs
&&
8588 instr
->op
!= nir_texop_fragment_fetch
&&
8589 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8590 assert(has_sample_index
);
8591 Operand
op(sample_index
);
8592 if (sample_index_cv
)
8593 op
= Operand(sample_index_cv
->u32
);
8594 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8597 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8598 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8599 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8600 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8605 /* Build tex instruction */
8606 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8607 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8608 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8610 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8613 /* gather4 selects the component by dmask and always returns vec4 */
8614 if (instr
->op
== nir_texop_tg4
) {
8615 assert(instr
->dest
.ssa
.num_components
== 4);
8616 if (instr
->is_shadow
)
8619 dmask
= 1 << instr
->component
;
8620 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8621 tmp_dst
= bld
.tmp(v4
);
8622 } else if (instr
->op
== nir_texop_samples_identical
) {
8623 tmp_dst
= bld
.tmp(v1
);
8624 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8625 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8628 aco_ptr
<MIMG_instruction
> tex
;
8629 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8631 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8633 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8634 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8637 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8638 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8640 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8641 tex
->operands
[0] = Operand(resource
);
8642 tex
->operands
[1] = Operand(s4
); /* no sampler */
8643 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8644 if (ctx
->options
->chip_class
== GFX9
&&
8645 instr
->op
== nir_texop_txs
&&
8646 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8648 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8649 } else if (instr
->op
== nir_texop_query_levels
) {
8650 tex
->dmask
= 1 << 3;
8655 tex
->definitions
[0] = Definition(tmp_dst
);
8657 tex
->can_reorder
= true;
8658 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8661 /* divide 3rd value by 6 by multiplying with magic number */
8662 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8663 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8664 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8665 assert(instr
->dest
.ssa
.num_components
== 3);
8666 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8667 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8668 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8669 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8674 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8678 Temp tg4_compare_cube_wa64
= Temp();
8680 if (tg4_integer_workarounds
) {
8681 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8682 tex
->operands
[0] = Operand(resource
);
8683 tex
->operands
[1] = Operand(s4
); /* no sampler */
8684 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8688 Temp size
= bld
.tmp(v2
);
8689 tex
->definitions
[0] = Definition(size
);
8690 tex
->can_reorder
= true;
8691 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8692 emit_split_vector(ctx
, size
, size
.size());
8695 for (unsigned i
= 0; i
< 2; i
++) {
8696 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8697 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8698 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8699 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8702 Temp new_coords
[2] = {
8703 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8704 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8707 if (tg4_integer_cube_workaround
) {
8708 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8709 Temp desc
[resource
.size()];
8710 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8711 Format::PSEUDO
, 1, resource
.size())};
8712 split
->operands
[0] = Operand(resource
);
8713 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8714 desc
[i
] = bld
.tmp(s1
);
8715 split
->definitions
[i
] = Definition(desc
[i
]);
8717 ctx
->block
->instructions
.emplace_back(std::move(split
));
8719 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8720 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8721 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8724 if (stype
== GLSL_TYPE_UINT
) {
8725 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8726 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8727 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8728 bld
.scc(compare_cube_wa
));
8730 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8731 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8732 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8733 bld
.scc(compare_cube_wa
));
8735 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8736 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8738 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8740 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8741 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8742 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8744 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8745 Format::PSEUDO
, resource
.size(), 1)};
8746 for (unsigned i
= 0; i
< resource
.size(); i
++)
8747 vec
->operands
[i
] = Operand(desc
[i
]);
8748 resource
= bld
.tmp(resource
.regClass());
8749 vec
->definitions
[0] = Definition(resource
);
8750 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8752 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8753 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8754 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8755 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8757 coords
[0] = new_coords
[0];
8758 coords
[1] = new_coords
[1];
8761 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8762 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8764 assert(coords
.size() == 1);
8765 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8769 op
= aco_opcode::buffer_load_format_x
; break;
8771 op
= aco_opcode::buffer_load_format_xy
; break;
8773 op
= aco_opcode::buffer_load_format_xyz
; break;
8775 op
= aco_opcode::buffer_load_format_xyzw
; break;
8777 unreachable("Tex instruction loads more than 4 components.");
8780 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8781 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8784 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8786 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8787 mubuf
->operands
[0] = Operand(resource
);
8788 mubuf
->operands
[1] = Operand(coords
[0]);
8789 mubuf
->operands
[2] = Operand((uint32_t) 0);
8790 mubuf
->definitions
[0] = Definition(tmp_dst
);
8791 mubuf
->idxen
= true;
8792 mubuf
->can_reorder
= true;
8793 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8795 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8799 /* gather MIMG address components */
8800 std::vector
<Temp
> args
;
8802 args
.emplace_back(offset
);
8804 args
.emplace_back(bias
);
8806 args
.emplace_back(compare
);
8808 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8810 args
.insert(args
.end(), coords
.begin(), coords
.end());
8811 if (has_sample_index
)
8812 args
.emplace_back(sample_index
);
8814 args
.emplace_back(lod
);
8816 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8817 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8818 vec
->definitions
[0] = Definition(arg
);
8819 for (unsigned i
= 0; i
< args
.size(); i
++)
8820 vec
->operands
[i
] = Operand(args
[i
]);
8821 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8824 if (instr
->op
== nir_texop_txf
||
8825 instr
->op
== nir_texop_txf_ms
||
8826 instr
->op
== nir_texop_samples_identical
||
8827 instr
->op
== nir_texop_fragment_fetch
||
8828 instr
->op
== nir_texop_fragment_mask_fetch
) {
8829 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8830 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8831 tex
->operands
[0] = Operand(resource
);
8832 tex
->operands
[1] = Operand(s4
); /* no sampler */
8833 tex
->operands
[2] = Operand(arg
);
8838 tex
->definitions
[0] = Definition(tmp_dst
);
8839 tex
->can_reorder
= true;
8840 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8842 if (instr
->op
== nir_texop_samples_identical
) {
8843 assert(dmask
== 1 && dst
.regClass() == v1
);
8844 assert(dst
.id() != tmp_dst
.id());
8846 Temp tmp
= bld
.tmp(bld
.lm
);
8847 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8848 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8851 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8856 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8857 aco_opcode opcode
= aco_opcode::image_sample
;
8858 if (has_offset
) { /* image_sample_*_o */
8860 opcode
= aco_opcode::image_sample_c_o
;
8862 opcode
= aco_opcode::image_sample_c_d_o
;
8864 opcode
= aco_opcode::image_sample_c_b_o
;
8866 opcode
= aco_opcode::image_sample_c_lz_o
;
8868 opcode
= aco_opcode::image_sample_c_l_o
;
8870 opcode
= aco_opcode::image_sample_o
;
8872 opcode
= aco_opcode::image_sample_d_o
;
8874 opcode
= aco_opcode::image_sample_b_o
;
8876 opcode
= aco_opcode::image_sample_lz_o
;
8878 opcode
= aco_opcode::image_sample_l_o
;
8880 } else { /* no offset */
8882 opcode
= aco_opcode::image_sample_c
;
8884 opcode
= aco_opcode::image_sample_c_d
;
8886 opcode
= aco_opcode::image_sample_c_b
;
8888 opcode
= aco_opcode::image_sample_c_lz
;
8890 opcode
= aco_opcode::image_sample_c_l
;
8892 opcode
= aco_opcode::image_sample
;
8894 opcode
= aco_opcode::image_sample_d
;
8896 opcode
= aco_opcode::image_sample_b
;
8898 opcode
= aco_opcode::image_sample_lz
;
8900 opcode
= aco_opcode::image_sample_l
;
8904 if (instr
->op
== nir_texop_tg4
) {
8906 opcode
= aco_opcode::image_gather4_lz_o
;
8908 opcode
= aco_opcode::image_gather4_c_lz_o
;
8910 opcode
= aco_opcode::image_gather4_lz
;
8912 opcode
= aco_opcode::image_gather4_c_lz
;
8914 } else if (instr
->op
== nir_texop_lod
) {
8915 opcode
= aco_opcode::image_get_lod
;
8918 /* we don't need the bias, sample index, compare value or offset to be
8919 * computed in WQM but if the p_create_vector copies the coordinates, then it
8920 * needs to be in WQM */
8921 if (ctx
->stage
== fragment_fs
&&
8922 !has_derivs
&& !has_lod
&& !level_zero
&&
8923 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8924 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8925 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8927 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8928 tex
->operands
[0] = Operand(resource
);
8929 tex
->operands
[1] = Operand(sampler
);
8930 tex
->operands
[2] = Operand(arg
);
8934 tex
->definitions
[0] = Definition(tmp_dst
);
8935 tex
->can_reorder
= true;
8936 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8938 if (tg4_integer_cube_workaround
) {
8939 assert(tmp_dst
.id() != dst
.id());
8940 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8942 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8944 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8945 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8947 if (stype
== GLSL_TYPE_UINT
)
8948 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8950 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8951 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8953 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8954 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8955 val
[0], val
[1], val
[2], val
[3]);
8957 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8958 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8963 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8965 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8966 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8967 return Operand(tmp
.regClass());
8969 return Operand(tmp
);
8972 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8974 aco_ptr
<Pseudo_instruction
> phi
;
8975 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8976 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8978 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8979 logical
|= ctx
->block
->kind
& block_kind_merge
;
8980 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8982 /* we want a sorted list of sources, since the predecessor list is also sorted */
8983 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8984 nir_foreach_phi_src(src
, instr
)
8985 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8987 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8988 unsigned num_operands
= 0;
8989 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8990 unsigned num_defined
= 0;
8991 unsigned cur_pred_idx
= 0;
8992 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8993 if (cur_pred_idx
< preds
.size()) {
8994 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8995 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8996 unsigned skipped
= 0;
8997 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8999 if (cur_pred_idx
+ skipped
< preds
.size()) {
9000 for (unsigned i
= 0; i
< skipped
; i
++)
9001 operands
[num_operands
++] = Operand(dst
.regClass());
9002 cur_pred_idx
+= skipped
;
9007 /* Handle missing predecessors at the end. This shouldn't happen with loop
9008 * headers and we can't ignore these sources for loop header phis. */
9009 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9012 Operand op
= get_phi_operand(ctx
, src
.second
);
9013 operands
[num_operands
++] = op
;
9014 num_defined
+= !op
.isUndefined();
9016 /* handle block_kind_continue_or_break at loop exit blocks */
9017 while (cur_pred_idx
++ < preds
.size())
9018 operands
[num_operands
++] = Operand(dst
.regClass());
9020 /* If the loop ends with a break, still add a linear continue edge in case
9021 * that break is divergent or continue_or_break is used. We'll either remove
9022 * this operand later in visit_loop() if it's not necessary or replace the
9023 * undef with something correct. */
9024 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9025 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9026 nir_block
*last
= nir_loop_last_block(loop
);
9027 if (last
->successors
[0] != instr
->instr
.block
)
9028 operands
[num_operands
++] = Operand(RegClass());
9031 if (num_defined
== 0) {
9032 Builder
bld(ctx
->program
, ctx
->block
);
9033 if (dst
.regClass() == s1
) {
9034 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9035 } else if (dst
.regClass() == v1
) {
9036 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9038 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9039 for (unsigned i
= 0; i
< dst
.size(); i
++)
9040 vec
->operands
[i
] = Operand(0u);
9041 vec
->definitions
[0] = Definition(dst
);
9042 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9047 /* we can use a linear phi in some cases if one src is undef */
9048 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9049 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9051 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9052 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9053 assert(invert
->kind
& block_kind_invert
);
9055 unsigned then_block
= invert
->linear_preds
[0];
9057 Block
* insert_block
= NULL
;
9058 for (unsigned i
= 0; i
< num_operands
; i
++) {
9059 Operand op
= operands
[i
];
9060 if (op
.isUndefined())
9062 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9063 phi
->operands
[0] = op
;
9066 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9067 phi
->operands
[1] = Operand(dst
.regClass());
9068 phi
->definitions
[0] = Definition(dst
);
9069 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9073 /* try to scalarize vector phis */
9074 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9075 // TODO: scalarize linear phis on divergent ifs
9076 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9077 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9078 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9079 Operand src
= operands
[i
];
9080 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9081 can_scalarize
= false;
9083 if (can_scalarize
) {
9084 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9085 assert(dst
.size() % num_components
== 0);
9086 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9088 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9089 for (unsigned k
= 0; k
< num_components
; k
++) {
9090 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9091 for (unsigned i
= 0; i
< num_operands
; i
++) {
9092 Operand src
= operands
[i
];
9093 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9095 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9096 phi
->definitions
[0] = Definition(phi_dst
);
9097 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9098 new_vec
[k
] = phi_dst
;
9099 vec
->operands
[k
] = Operand(phi_dst
);
9101 vec
->definitions
[0] = Definition(dst
);
9102 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9103 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9108 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9109 for (unsigned i
= 0; i
< num_operands
; i
++)
9110 phi
->operands
[i
] = operands
[i
];
9111 phi
->definitions
[0] = Definition(dst
);
9112 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9116 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9118 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9120 assert(dst
.type() == RegType::sgpr
);
9122 if (dst
.size() == 1) {
9123 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9125 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9126 for (unsigned i
= 0; i
< dst
.size(); i
++)
9127 vec
->operands
[i
] = Operand(0u);
9128 vec
->definitions
[0] = Definition(dst
);
9129 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9133 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9135 Builder
bld(ctx
->program
, ctx
->block
);
9136 Block
*logical_target
;
9137 append_logical_end(ctx
->block
);
9138 unsigned idx
= ctx
->block
->index
;
9140 switch (instr
->type
) {
9141 case nir_jump_break
:
9142 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9143 add_logical_edge(idx
, logical_target
);
9144 ctx
->block
->kind
|= block_kind_break
;
9146 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9147 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9148 /* uniform break - directly jump out of the loop */
9149 ctx
->block
->kind
|= block_kind_uniform
;
9150 ctx
->cf_info
.has_branch
= true;
9151 bld
.branch(aco_opcode::p_branch
);
9152 add_linear_edge(idx
, logical_target
);
9155 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9156 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9158 case nir_jump_continue
:
9159 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9160 add_logical_edge(idx
, logical_target
);
9161 ctx
->block
->kind
|= block_kind_continue
;
9163 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9164 /* for potential uniform breaks after this continue,
9165 we must ensure that they are handled correctly */
9166 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9167 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9168 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9170 /* uniform continue - directly jump to the loop header */
9171 ctx
->block
->kind
|= block_kind_uniform
;
9172 ctx
->cf_info
.has_branch
= true;
9173 bld
.branch(aco_opcode::p_branch
);
9174 add_linear_edge(idx
, logical_target
);
9179 fprintf(stderr
, "Unknown NIR jump instr: ");
9180 nir_print_instr(&instr
->instr
, stderr
);
9181 fprintf(stderr
, "\n");
9185 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9186 ctx
->cf_info
.exec_potentially_empty_break
= true;
9187 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9190 /* remove critical edges from linear CFG */
9191 bld
.branch(aco_opcode::p_branch
);
9192 Block
* break_block
= ctx
->program
->create_and_insert_block();
9193 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9194 break_block
->kind
|= block_kind_uniform
;
9195 add_linear_edge(idx
, break_block
);
9196 /* the loop_header pointer might be invalidated by this point */
9197 if (instr
->type
== nir_jump_continue
)
9198 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9199 add_linear_edge(break_block
->index
, logical_target
);
9200 bld
.reset(break_block
);
9201 bld
.branch(aco_opcode::p_branch
);
9203 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9204 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9205 add_linear_edge(idx
, continue_block
);
9206 append_logical_start(continue_block
);
9207 ctx
->block
= continue_block
;
9211 void visit_block(isel_context
*ctx
, nir_block
*block
)
9213 nir_foreach_instr(instr
, block
) {
9214 switch (instr
->type
) {
9215 case nir_instr_type_alu
:
9216 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9218 case nir_instr_type_load_const
:
9219 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9221 case nir_instr_type_intrinsic
:
9222 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9224 case nir_instr_type_tex
:
9225 visit_tex(ctx
, nir_instr_as_tex(instr
));
9227 case nir_instr_type_phi
:
9228 visit_phi(ctx
, nir_instr_as_phi(instr
));
9230 case nir_instr_type_ssa_undef
:
9231 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9233 case nir_instr_type_deref
:
9235 case nir_instr_type_jump
:
9236 visit_jump(ctx
, nir_instr_as_jump(instr
));
9239 fprintf(stderr
, "Unknown NIR instr type: ");
9240 nir_print_instr(instr
, stderr
);
9241 fprintf(stderr
, "\n");
9246 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9247 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9252 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9253 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9255 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9256 RegClass rc
= vals
[0].regClass();
9258 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9260 unsigned next_pred
= 1;
9262 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9263 Block
& block
= ctx
->program
->blocks
[idx
];
9264 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9265 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9269 if (block
.kind
& block_kind_continue
) {
9270 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9275 bool all_same
= true;
9276 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9277 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9281 val
= vals
[block
.linear_preds
[0] - first
];
9283 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9284 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9285 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9286 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9287 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9288 phi
->definitions
[0] = Definition(val
.getTemp());
9289 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9291 vals
[idx
- first
] = val
;
9294 return vals
[last
- first
];
9297 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9299 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9300 append_logical_end(ctx
->block
);
9301 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9302 Builder
bld(ctx
->program
, ctx
->block
);
9303 bld
.branch(aco_opcode::p_branch
);
9304 unsigned loop_preheader_idx
= ctx
->block
->index
;
9306 Block loop_exit
= Block();
9307 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9308 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9310 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9311 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9312 loop_header
->kind
|= block_kind_loop_header
;
9313 add_edge(loop_preheader_idx
, loop_header
);
9314 ctx
->block
= loop_header
;
9316 /* emit loop body */
9317 unsigned loop_header_idx
= loop_header
->index
;
9318 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9319 append_logical_start(ctx
->block
);
9320 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9322 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9323 if (!ctx
->cf_info
.has_branch
) {
9324 append_logical_end(ctx
->block
);
9325 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9326 /* Discards can result in code running with an empty exec mask.
9327 * This would result in divergent breaks not ever being taken. As a
9328 * workaround, break the loop when the loop mask is empty instead of
9329 * always continuing. */
9330 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9331 unsigned block_idx
= ctx
->block
->index
;
9333 /* create helper blocks to avoid critical edges */
9334 Block
*break_block
= ctx
->program
->create_and_insert_block();
9335 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9336 break_block
->kind
= block_kind_uniform
;
9337 bld
.reset(break_block
);
9338 bld
.branch(aco_opcode::p_branch
);
9339 add_linear_edge(block_idx
, break_block
);
9340 add_linear_edge(break_block
->index
, &loop_exit
);
9342 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9343 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9344 continue_block
->kind
= block_kind_uniform
;
9345 bld
.reset(continue_block
);
9346 bld
.branch(aco_opcode::p_branch
);
9347 add_linear_edge(block_idx
, continue_block
);
9348 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9350 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9351 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9352 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9354 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9355 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9356 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9358 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9361 bld
.reset(ctx
->block
);
9362 bld
.branch(aco_opcode::p_branch
);
9365 /* Fixup phis in loop header from unreachable blocks.
9366 * has_branch/has_divergent_branch also indicates if the loop ends with a
9367 * break/continue instruction, but we don't emit those if unreachable=true */
9369 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9370 bool linear
= ctx
->cf_info
.has_branch
;
9371 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9372 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9373 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9374 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9375 /* the last operand should be the one that needs to be removed */
9376 instr
->operands
.pop_back();
9377 } else if (!is_phi(instr
)) {
9383 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9384 * and the previous one shouldn't both happen at once because a break in the
9385 * merge block would get CSE'd */
9386 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9387 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9388 Operand vals
[num_vals
];
9389 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9390 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9391 if (ctx
->cf_info
.has_branch
)
9392 instr
->operands
.pop_back();
9394 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9395 } else if (!is_phi(instr
)) {
9401 ctx
->cf_info
.has_branch
= false;
9403 // TODO: if the loop has not a single exit, we must add one °°
9404 /* emit loop successor block */
9405 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9406 append_logical_start(ctx
->block
);
9409 // TODO: check if it is beneficial to not branch on continues
9410 /* trim linear phis in loop header */
9411 for (auto&& instr
: loop_entry
->instructions
) {
9412 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9413 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9414 new_phi
->definitions
[0] = instr
->definitions
[0];
9415 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9416 new_phi
->operands
[i
] = instr
->operands
[i
];
9417 /* check that the remaining operands are all the same */
9418 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9419 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9420 instr
.swap(new_phi
);
9421 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9430 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9434 append_logical_end(ctx
->block
);
9435 ctx
->block
->kind
|= block_kind_branch
;
9437 /* branch to linear then block */
9438 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9439 aco_ptr
<Pseudo_branch_instruction
> branch
;
9440 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9441 branch
->operands
[0] = Operand(cond
);
9442 ctx
->block
->instructions
.push_back(std::move(branch
));
9444 ic
->BB_if_idx
= ctx
->block
->index
;
9445 ic
->BB_invert
= Block();
9446 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9447 /* Invert blocks are intentionally not marked as top level because they
9448 * are not part of the logical cfg. */
9449 ic
->BB_invert
.kind
|= block_kind_invert
;
9450 ic
->BB_endif
= Block();
9451 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9452 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9454 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9455 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9456 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9457 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9458 ctx
->cf_info
.parent_if
.is_divergent
= true;
9460 /* divergent branches use cbranch_execz */
9461 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9462 ctx
->cf_info
.exec_potentially_empty_break
= false;
9463 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9465 /** emit logical then block */
9466 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9467 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9468 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9469 ctx
->block
= BB_then_logical
;
9470 append_logical_start(BB_then_logical
);
9473 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9475 Block
*BB_then_logical
= ctx
->block
;
9476 append_logical_end(BB_then_logical
);
9477 /* branch from logical then block to invert block */
9478 aco_ptr
<Pseudo_branch_instruction
> branch
;
9479 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9480 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9481 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9482 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9483 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9484 BB_then_logical
->kind
|= block_kind_uniform
;
9485 assert(!ctx
->cf_info
.has_branch
);
9486 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9487 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9489 /** emit linear then block */
9490 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9491 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9492 BB_then_linear
->kind
|= block_kind_uniform
;
9493 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9494 /* branch from linear then block to invert block */
9495 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9496 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9497 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9499 /** emit invert merge block */
9500 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9501 ic
->invert_idx
= ctx
->block
->index
;
9503 /* branch to linear else block (skip else) */
9504 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9505 branch
->operands
[0] = Operand(ic
->cond
);
9506 ctx
->block
->instructions
.push_back(std::move(branch
));
9508 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9509 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9510 ic
->exec_potentially_empty_break_depth_old
=
9511 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9512 /* divergent branches use cbranch_execz */
9513 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9514 ctx
->cf_info
.exec_potentially_empty_break
= false;
9515 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9517 /** emit logical else block */
9518 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9519 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9520 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9521 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9522 ctx
->block
= BB_else_logical
;
9523 append_logical_start(BB_else_logical
);
9526 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9528 Block
*BB_else_logical
= ctx
->block
;
9529 append_logical_end(BB_else_logical
);
9531 /* branch from logical else block to endif block */
9532 aco_ptr
<Pseudo_branch_instruction
> branch
;
9533 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9534 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9535 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9536 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9537 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9538 BB_else_logical
->kind
|= block_kind_uniform
;
9540 assert(!ctx
->cf_info
.has_branch
);
9541 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9544 /** emit linear else block */
9545 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9546 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9547 BB_else_linear
->kind
|= block_kind_uniform
;
9548 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9550 /* branch from linear else block to endif block */
9551 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9552 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9553 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9556 /** emit endif merge block */
9557 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9558 append_logical_start(ctx
->block
);
9561 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9562 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9563 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9564 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9565 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9566 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9567 !ctx
->cf_info
.parent_if
.is_divergent
) {
9568 ctx
->cf_info
.exec_potentially_empty_break
= false;
9569 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9571 /* uniform control flow never has an empty exec-mask */
9572 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9573 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9574 ctx
->cf_info
.exec_potentially_empty_break
= false;
9575 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9579 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9581 assert(cond
.regClass() == s1
);
9583 append_logical_end(ctx
->block
);
9584 ctx
->block
->kind
|= block_kind_uniform
;
9586 aco_ptr
<Pseudo_branch_instruction
> branch
;
9587 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9588 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9589 branch
->operands
[0] = Operand(cond
);
9590 branch
->operands
[0].setFixed(scc
);
9591 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9593 ic
->BB_if_idx
= ctx
->block
->index
;
9594 ic
->BB_endif
= Block();
9595 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9596 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9598 ctx
->cf_info
.has_branch
= false;
9599 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9601 /** emit then block */
9602 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9603 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9604 add_edge(ic
->BB_if_idx
, BB_then
);
9605 append_logical_start(BB_then
);
9606 ctx
->block
= BB_then
;
9609 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9611 Block
*BB_then
= ctx
->block
;
9613 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9614 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9616 if (!ic
->uniform_has_then_branch
) {
9617 append_logical_end(BB_then
);
9618 /* branch from then block to endif block */
9619 aco_ptr
<Pseudo_branch_instruction
> branch
;
9620 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9621 BB_then
->instructions
.emplace_back(std::move(branch
));
9622 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9623 if (!ic
->then_branch_divergent
)
9624 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9625 BB_then
->kind
|= block_kind_uniform
;
9628 ctx
->cf_info
.has_branch
= false;
9629 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9631 /** emit else block */
9632 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9633 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9634 add_edge(ic
->BB_if_idx
, BB_else
);
9635 append_logical_start(BB_else
);
9636 ctx
->block
= BB_else
;
9639 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9641 Block
*BB_else
= ctx
->block
;
9643 if (!ctx
->cf_info
.has_branch
) {
9644 append_logical_end(BB_else
);
9645 /* branch from then block to endif block */
9646 aco_ptr
<Pseudo_branch_instruction
> branch
;
9647 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9648 BB_else
->instructions
.emplace_back(std::move(branch
));
9649 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9650 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9651 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9652 BB_else
->kind
|= block_kind_uniform
;
9655 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9656 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9658 /** emit endif merge block */
9659 if (!ctx
->cf_info
.has_branch
) {
9660 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9661 append_logical_start(ctx
->block
);
9665 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9667 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9668 Builder
bld(ctx
->program
, ctx
->block
);
9669 aco_ptr
<Pseudo_branch_instruction
> branch
;
9672 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9674 * Uniform conditionals are represented in the following way*) :
9676 * The linear and logical CFG:
9679 * BB_THEN (logical) BB_ELSE (logical)
9683 * *) Exceptions may be due to break and continue statements within loops
9684 * If a break/continue happens within uniform control flow, it branches
9685 * to the loop exit/entry block. Otherwise, it branches to the next
9689 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9690 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9691 cond
= bool_to_scalar_condition(ctx
, cond
);
9693 begin_uniform_if_then(ctx
, &ic
, cond
);
9694 visit_cf_list(ctx
, &if_stmt
->then_list
);
9696 begin_uniform_if_else(ctx
, &ic
);
9697 visit_cf_list(ctx
, &if_stmt
->else_list
);
9699 end_uniform_if(ctx
, &ic
);
9701 return !ctx
->cf_info
.has_branch
;
9702 } else { /* non-uniform condition */
9704 * To maintain a logical and linear CFG without critical edges,
9705 * non-uniform conditionals are represented in the following way*) :
9710 * BB_THEN (logical) BB_THEN (linear)
9712 * BB_INVERT (linear)
9714 * BB_ELSE (logical) BB_ELSE (linear)
9721 * BB_THEN (logical) BB_ELSE (logical)
9725 * *) Exceptions may be due to break and continue statements within loops
9728 begin_divergent_if_then(ctx
, &ic
, cond
);
9729 visit_cf_list(ctx
, &if_stmt
->then_list
);
9731 begin_divergent_if_else(ctx
, &ic
);
9732 visit_cf_list(ctx
, &if_stmt
->else_list
);
9734 end_divergent_if(ctx
, &ic
);
9740 static bool visit_cf_list(isel_context
*ctx
,
9741 struct exec_list
*list
)
9743 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9744 switch (node
->type
) {
9745 case nir_cf_node_block
:
9746 visit_block(ctx
, nir_cf_node_as_block(node
));
9748 case nir_cf_node_if
:
9749 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9752 case nir_cf_node_loop
:
9753 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9756 unreachable("unimplemented cf list type");
9762 static void create_null_export(isel_context
*ctx
)
9764 /* Some shader stages always need to have exports.
9765 * So when there is none, we need to add a null export.
9768 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9769 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9770 Builder
bld(ctx
->program
, ctx
->block
);
9771 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9772 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9775 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9777 assert(ctx
->stage
== vertex_vs
||
9778 ctx
->stage
== tess_eval_vs
||
9779 ctx
->stage
== gs_copy_vs
||
9780 ctx
->stage
== ngg_vertex_gs
||
9781 ctx
->stage
== ngg_tess_eval_gs
);
9783 int offset
= (ctx
->stage
& sw_tes
)
9784 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9785 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9786 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9787 if (!is_pos
&& !mask
)
9789 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9791 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9792 exp
->enabled_mask
= mask
;
9793 for (unsigned i
= 0; i
< 4; ++i
) {
9794 if (mask
& (1 << i
))
9795 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9797 exp
->operands
[i
] = Operand(v1
);
9799 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9800 * Setting valid_mask=1 prevents it and has no other effect.
9802 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9804 exp
->compressed
= false;
9806 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9808 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9809 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9814 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9816 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9817 exp
->enabled_mask
= 0;
9818 for (unsigned i
= 0; i
< 4; ++i
)
9819 exp
->operands
[i
] = Operand(v1
);
9820 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9821 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9822 exp
->enabled_mask
|= 0x1;
9824 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9825 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9826 exp
->enabled_mask
|= 0x4;
9828 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9829 if (ctx
->options
->chip_class
< GFX9
) {
9830 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9831 exp
->enabled_mask
|= 0x8;
9833 Builder
bld(ctx
->program
, ctx
->block
);
9835 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9836 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9837 if (exp
->operands
[2].isTemp())
9838 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9840 exp
->operands
[2] = Operand(out
);
9841 exp
->enabled_mask
|= 0x4;
9844 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9846 exp
->compressed
= false;
9847 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9848 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9851 static void create_export_phis(isel_context
*ctx
)
9853 /* Used when exports are needed, but the output temps are defined in a preceding block.
9854 * This function will set up phis in order to access the outputs in the next block.
9857 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9858 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9859 ctx
->block
->instructions
.pop_back();
9861 Builder
bld(ctx
->program
, ctx
->block
);
9863 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9864 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9865 for (unsigned i
= 0; i
< 4; ++i
) {
9866 if (!(mask
& (1 << i
)))
9869 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9870 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9871 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9875 bld
.insert(std::move(logical_start
));
9878 static void create_vs_exports(isel_context
*ctx
)
9880 assert(ctx
->stage
== vertex_vs
||
9881 ctx
->stage
== tess_eval_vs
||
9882 ctx
->stage
== gs_copy_vs
||
9883 ctx
->stage
== ngg_vertex_gs
||
9884 ctx
->stage
== ngg_tess_eval_gs
);
9886 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9887 ? &ctx
->program
->info
->tes
.outinfo
9888 : &ctx
->program
->info
->vs
.outinfo
;
9890 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9891 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9892 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9895 if (ctx
->options
->key
.has_multiview_view_index
) {
9896 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9897 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9900 /* the order these position exports are created is important */
9902 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9903 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9904 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9905 exported_pos
= true;
9907 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9908 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9909 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9910 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9912 if (ctx
->export_clip_dists
) {
9913 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9914 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9915 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9916 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9919 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9920 if (i
< VARYING_SLOT_VAR0
&&
9921 i
!= VARYING_SLOT_LAYER
&&
9922 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9923 i
!= VARYING_SLOT_VIEWPORT
)
9926 export_vs_varying(ctx
, i
, false, NULL
);
9930 create_null_export(ctx
);
9933 static bool export_fs_mrt_z(isel_context
*ctx
)
9935 Builder
bld(ctx
->program
, ctx
->block
);
9936 unsigned enabled_channels
= 0;
9940 for (unsigned i
= 0; i
< 4; ++i
) {
9941 values
[i
] = Operand(v1
);
9944 /* Both stencil and sample mask only need 16-bits. */
9945 if (!ctx
->program
->info
->ps
.writes_z
&&
9946 (ctx
->program
->info
->ps
.writes_stencil
||
9947 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9948 compr
= true; /* COMPR flag */
9950 if (ctx
->program
->info
->ps
.writes_stencil
) {
9951 /* Stencil should be in X[23:16]. */
9952 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9953 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9954 enabled_channels
|= 0x3;
9957 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9958 /* SampleMask should be in Y[15:0]. */
9959 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9960 enabled_channels
|= 0xc;
9963 if (ctx
->program
->info
->ps
.writes_z
) {
9964 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9965 enabled_channels
|= 0x1;
9968 if (ctx
->program
->info
->ps
.writes_stencil
) {
9969 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9970 enabled_channels
|= 0x2;
9973 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9974 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9975 enabled_channels
|= 0x4;
9979 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9980 * writemask component.
9982 if (ctx
->options
->chip_class
== GFX6
&&
9983 ctx
->options
->family
!= CHIP_OLAND
&&
9984 ctx
->options
->family
!= CHIP_HAINAN
) {
9985 enabled_channels
|= 0x1;
9988 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9989 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9994 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9996 Builder
bld(ctx
->program
, ctx
->block
);
9997 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
10000 for (unsigned i
= 0; i
< 4; ++i
) {
10001 if (write_mask
& (1 << i
)) {
10002 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
10004 values
[i
] = Operand(v1
);
10008 unsigned target
, col_format
;
10009 unsigned enabled_channels
= 0;
10010 aco_opcode compr_op
= (aco_opcode
)0;
10012 slot
-= FRAG_RESULT_DATA0
;
10013 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10014 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10016 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10017 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10019 switch (col_format
)
10021 case V_028714_SPI_SHADER_ZERO
:
10022 enabled_channels
= 0; /* writemask */
10023 target
= V_008DFC_SQ_EXP_NULL
;
10026 case V_028714_SPI_SHADER_32_R
:
10027 enabled_channels
= 1;
10030 case V_028714_SPI_SHADER_32_GR
:
10031 enabled_channels
= 0x3;
10034 case V_028714_SPI_SHADER_32_AR
:
10035 if (ctx
->options
->chip_class
>= GFX10
) {
10036 /* Special case: on GFX10, the outputs are different for 32_AR */
10037 enabled_channels
= 0x3;
10038 values
[1] = values
[3];
10039 values
[3] = Operand(v1
);
10041 enabled_channels
= 0x9;
10045 case V_028714_SPI_SHADER_FP16_ABGR
:
10046 enabled_channels
= 0x5;
10047 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10050 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10051 enabled_channels
= 0x5;
10052 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10055 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10056 enabled_channels
= 0x5;
10057 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10060 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10061 enabled_channels
= 0x5;
10062 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10063 if (is_int8
|| is_int10
) {
10065 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10066 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10068 for (unsigned i
= 0; i
< 4; i
++) {
10069 if ((write_mask
>> i
) & 1) {
10070 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10071 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10079 case V_028714_SPI_SHADER_SINT16_ABGR
:
10080 enabled_channels
= 0x5;
10081 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10082 if (is_int8
|| is_int10
) {
10084 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10085 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10086 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10087 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10089 for (unsigned i
= 0; i
< 4; i
++) {
10090 if ((write_mask
>> i
) & 1) {
10091 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10092 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10094 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10095 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10102 case V_028714_SPI_SHADER_32_ABGR
:
10103 enabled_channels
= 0xF;
10110 if (target
== V_008DFC_SQ_EXP_NULL
)
10113 if ((bool) compr_op
) {
10114 for (int i
= 0; i
< 2; i
++) {
10115 /* check if at least one of the values to be compressed is enabled */
10116 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10118 enabled_channels
|= enabled
<< (i
*2);
10119 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10120 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10121 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10123 values
[i
] = Operand(v1
);
10126 values
[2] = Operand(v1
);
10127 values
[3] = Operand(v1
);
10129 for (int i
= 0; i
< 4; i
++)
10130 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10133 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10134 enabled_channels
, target
, (bool) compr_op
);
10138 static void create_fs_exports(isel_context
*ctx
)
10140 bool exported
= false;
10142 /* Export depth, stencil and sample mask. */
10143 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10144 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10145 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10146 exported
|= export_fs_mrt_z(ctx
);
10148 /* Export all color render targets. */
10149 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10150 if (ctx
->outputs
.mask
[i
])
10151 exported
|= export_fs_mrt_color(ctx
, i
);
10154 create_null_export(ctx
);
10157 static void write_tcs_tess_factors(isel_context
*ctx
)
10159 unsigned outer_comps
;
10160 unsigned inner_comps
;
10162 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10179 Builder
bld(ctx
->program
, ctx
->block
);
10181 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10182 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10183 bld
.sopp(aco_opcode::s_barrier
);
10185 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10186 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10188 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10189 if_context ic_invocation_id_is_zero
;
10190 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10191 bld
.reset(ctx
->block
);
10193 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10195 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10196 unsigned stride
= inner_comps
+ outer_comps
;
10197 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10201 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10203 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10205 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10206 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10207 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10209 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10210 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10212 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10213 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10214 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10215 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10218 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10219 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10220 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10221 unsigned tf_const_offset
= 0;
10223 if (ctx
->program
->chip_class
<= GFX8
) {
10224 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10225 if_context ic_rel_patch_id_is_zero
;
10226 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10227 bld
.reset(ctx
->block
);
10229 /* Store the dynamic HS control word. */
10230 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10231 bld
.mubuf(aco_opcode::buffer_store_dword
,
10232 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10233 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10234 /* disable_wqm */ false, /* glc */ true);
10235 tf_const_offset
+= 4;
10237 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10238 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10239 bld
.reset(ctx
->block
);
10242 assert(stride
== 2 || stride
== 4 || stride
== 6);
10243 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10244 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10246 /* Store to offchip for TES to read - only if TES reads them */
10247 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10248 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10249 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10251 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10252 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10254 if (likely(inner_comps
)) {
10255 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10256 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10260 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10261 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10264 static void emit_stream_output(isel_context
*ctx
,
10265 Temp
const *so_buffers
,
10266 Temp
const *so_write_offset
,
10267 const struct radv_stream_output
*output
)
10269 unsigned num_comps
= util_bitcount(output
->component_mask
);
10270 unsigned writemask
= (1 << num_comps
) - 1;
10271 unsigned loc
= output
->location
;
10272 unsigned buf
= output
->buffer
;
10274 assert(num_comps
&& num_comps
<= 4);
10275 if (!num_comps
|| num_comps
> 4)
10278 unsigned start
= ffs(output
->component_mask
) - 1;
10281 bool all_undef
= true;
10282 assert(ctx
->stage
& hw_vs
);
10283 for (unsigned i
= 0; i
< num_comps
; i
++) {
10284 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10285 all_undef
= all_undef
&& !out
[i
].id();
10290 while (writemask
) {
10292 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10293 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10294 /* GFX6 doesn't support storing vec3, split it. */
10295 writemask
|= 1u << (start
+ 2);
10299 unsigned offset
= output
->offset
+ start
* 4;
10301 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10302 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10303 for (int i
= 0; i
< count
; ++i
)
10304 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10305 vec
->definitions
[0] = Definition(write_data
);
10306 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10311 opcode
= aco_opcode::buffer_store_dword
;
10314 opcode
= aco_opcode::buffer_store_dwordx2
;
10317 opcode
= aco_opcode::buffer_store_dwordx3
;
10320 opcode
= aco_opcode::buffer_store_dwordx4
;
10323 unreachable("Unsupported dword count.");
10326 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10327 store
->operands
[0] = Operand(so_buffers
[buf
]);
10328 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10329 store
->operands
[2] = Operand((uint32_t) 0);
10330 store
->operands
[3] = Operand(write_data
);
10331 if (offset
> 4095) {
10332 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10333 Builder
bld(ctx
->program
, ctx
->block
);
10334 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10336 store
->offset
= offset
;
10338 store
->offen
= true;
10340 store
->dlc
= false;
10342 store
->can_reorder
= true;
10343 ctx
->block
->instructions
.emplace_back(std::move(store
));
10347 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10349 Builder
bld(ctx
->program
, ctx
->block
);
10351 Temp so_buffers
[4];
10352 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10353 for (unsigned i
= 0; i
< 4; i
++) {
10354 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10358 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10359 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10362 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10363 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10365 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10367 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10370 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10372 bld
.reset(ctx
->block
);
10374 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10376 Temp so_write_offset
[4];
10378 for (unsigned i
= 0; i
< 4; i
++) {
10379 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10384 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10385 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10386 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10387 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10389 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10391 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10392 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10393 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10394 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10398 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10399 struct radv_stream_output
*output
=
10400 &ctx
->program
->info
->so
.outputs
[i
];
10401 if (stream
!= output
->stream
)
10404 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10407 begin_divergent_if_else(ctx
, &ic
);
10408 end_divergent_if(ctx
, &ic
);
10411 } /* end namespace */
10413 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10415 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10416 Builder
bld(ctx
->program
, ctx
->block
);
10417 constexpr unsigned hs_idx
= 1u;
10418 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10419 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10420 Operand((8u << 16) | (hs_idx
* 8u)));
10421 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10423 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10425 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10426 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10427 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10428 ls_has_nonzero_hs_threads
);
10429 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10430 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10431 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10432 ls_has_nonzero_hs_threads
);
10433 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10434 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10435 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10436 ls_has_nonzero_hs_threads
);
10438 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10439 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10440 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10443 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10445 /* Split all arguments except for the first (ring_offsets) and the last
10446 * (exec) so that the dead channels don't stay live throughout the program.
10448 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10449 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10450 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10451 startpgm
->definitions
[i
].regClass().size());
10456 void handle_bc_optimize(isel_context
*ctx
)
10458 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10459 Builder
bld(ctx
->program
, ctx
->block
);
10460 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10461 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10462 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10463 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10464 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10465 if (uses_center
&& uses_centroid
) {
10466 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10467 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10469 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10471 for (unsigned i
= 0; i
< 2; i
++) {
10472 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10473 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10474 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10475 persp_centroid
, persp_center
, sel
);
10477 ctx
->persp_centroid
= bld
.tmp(v2
);
10478 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10479 Operand(new_coord
[0]), Operand(new_coord
[1]));
10480 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10483 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10485 for (unsigned i
= 0; i
< 2; i
++) {
10486 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10487 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10488 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10489 linear_centroid
, linear_center
, sel
);
10491 ctx
->linear_centroid
= bld
.tmp(v2
);
10492 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10493 Operand(new_coord
[0]), Operand(new_coord
[1]));
10494 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10499 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10501 Program
*program
= ctx
->program
;
10503 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10505 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10506 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10507 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10508 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10509 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10511 program
->next_fp_mode
.must_flush_denorms32
=
10512 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10513 program
->next_fp_mode
.must_flush_denorms16_64
=
10514 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10515 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10517 program
->next_fp_mode
.care_about_round32
=
10518 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10520 program
->next_fp_mode
.care_about_round16_64
=
10521 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10522 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10524 /* default to preserving fp16 and fp64 denorms, since it's free */
10525 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10526 program
->next_fp_mode
.denorm16_64
= 0;
10528 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10530 /* preserving fp32 denorms is expensive, so only do it if asked */
10531 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10532 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10534 program
->next_fp_mode
.denorm32
= 0;
10536 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10537 program
->next_fp_mode
.round32
= fp_round_tz
;
10539 program
->next_fp_mode
.round32
= fp_round_ne
;
10541 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10542 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10544 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10546 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10549 void cleanup_cfg(Program
*program
)
10551 /* create linear_succs/logical_succs */
10552 for (Block
& BB
: program
->blocks
) {
10553 for (unsigned idx
: BB
.linear_preds
)
10554 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10555 for (unsigned idx
: BB
.logical_preds
)
10556 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10560 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10562 Builder
bld(ctx
->program
, ctx
->block
);
10564 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10565 Temp count
= i
== 0
10566 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10567 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10568 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10570 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10573 if (ctx
->program
->wave_size
== 64) {
10574 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10575 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10576 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10578 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10579 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10585 bool ngg_early_prim_export(isel_context
*ctx
)
10587 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10591 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10593 Builder
bld(ctx
->program
, ctx
->block
);
10595 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10596 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10598 /* Get the id of the current wave within the threadgroup (workgroup) */
10599 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10600 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10602 /* Execute the following code only on the first wave (wave id 0),
10603 * use the SCC def to tell if the wave id is zero or not.
10605 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10607 begin_uniform_if_then(ctx
, &ic
, cond
);
10608 begin_uniform_if_else(ctx
, &ic
);
10609 bld
.reset(ctx
->block
);
10611 /* Number of vertices output by VS/TES */
10612 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10613 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10614 /* Number of primitives output by VS/TES */
10615 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10616 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10618 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10619 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10620 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10622 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10623 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10625 end_uniform_if(ctx
, &ic
);
10627 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10628 bld
.reset(ctx
->block
);
10629 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10632 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10634 Builder
bld(ctx
->program
, ctx
->block
);
10636 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10637 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10640 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10643 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10644 assert(vtxindex
[i
].id());
10647 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10651 /* The initial edge flag is always false in tess eval shaders. */
10652 if (ctx
->stage
== ngg_vertex_gs
) {
10653 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10654 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10658 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10663 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10665 Builder
bld(ctx
->program
, ctx
->block
);
10666 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10668 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10669 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10670 false /* compressed */, true/* done */, false /* valid mask */);
10673 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10675 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10676 * These must always come before VS exports.
10678 * It is recommended to do these as early as possible. They can be at the beginning when
10679 * there is no SW GS and the shader doesn't write edge flags.
10683 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10684 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10686 Builder
bld(ctx
->program
, ctx
->block
);
10687 constexpr unsigned max_vertices_per_primitive
= 3;
10688 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10690 if (ctx
->stage
== ngg_vertex_gs
) {
10691 /* TODO: optimize for points & lines */
10692 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10693 if (ctx
->shader
->info
.tess
.point_mode
)
10694 num_vertices_per_primitive
= 1;
10695 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10696 num_vertices_per_primitive
= 2;
10698 unreachable("Unsupported NGG shader stage");
10701 Temp vtxindex
[max_vertices_per_primitive
];
10702 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10703 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10704 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10705 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10706 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10707 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10708 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10709 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10711 /* Export primitive data to the index buffer. */
10712 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10714 /* Export primitive ID. */
10715 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10716 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10717 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10718 Temp provoking_vtx_index
= vtxindex
[0];
10719 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10721 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10724 begin_divergent_if_else(ctx
, &ic
);
10725 end_divergent_if(ctx
, &ic
);
10728 void ngg_emit_nogs_output(isel_context
*ctx
)
10730 /* Emits NGG GS output, for stages that don't have SW GS. */
10733 Builder
bld(ctx
->program
, ctx
->block
);
10734 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10736 /* NGG streamout is currently disabled by default. */
10737 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10739 if (late_prim_export
) {
10740 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10741 create_export_phis(ctx
);
10742 /* Do what we need to do in the GS threads. */
10743 ngg_emit_nogs_gsthreads(ctx
);
10745 /* What comes next should be executed on ES threads. */
10746 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10747 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10748 bld
.reset(ctx
->block
);
10751 /* Export VS outputs */
10752 ctx
->block
->kind
|= block_kind_export_end
;
10753 create_vs_exports(ctx
);
10755 /* Export primitive ID */
10756 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10759 if (ctx
->stage
== ngg_vertex_gs
) {
10760 /* Wait for GS threads to store primitive ID in LDS. */
10761 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10762 bld
.sopp(aco_opcode::s_barrier
);
10764 /* Calculate LDS address where the GS threads stored the primitive ID. */
10765 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10766 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10767 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10768 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10769 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10770 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10772 /* Load primitive ID from LDS. */
10773 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10774 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10775 /* TES: Just use the patch ID as the primitive ID. */
10776 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10778 unreachable("unsupported NGG shader stage.");
10781 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10782 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10784 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10787 if (late_prim_export
) {
10788 begin_divergent_if_else(ctx
, &ic
);
10789 end_divergent_if(ctx
, &ic
);
10790 bld
.reset(ctx
->block
);
10794 void select_program(Program
*program
,
10795 unsigned shader_count
,
10796 struct nir_shader
*const *shaders
,
10797 ac_shader_config
* config
,
10798 struct radv_shader_args
*args
)
10800 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10801 if_context ic_merged_wave_info
;
10802 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10804 for (unsigned i
= 0; i
< shader_count
; i
++) {
10805 nir_shader
*nir
= shaders
[i
];
10806 init_context(&ctx
, nir
);
10808 setup_fp_mode(&ctx
, nir
);
10811 /* needs to be after init_context() for FS */
10812 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10813 append_logical_start(ctx
.block
);
10815 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10816 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10818 split_arguments(&ctx
, startpgm
);
10822 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10824 if (ngg_early_prim_export(&ctx
))
10825 ngg_emit_nogs_gsthreads(&ctx
);
10828 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10829 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10830 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10831 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10832 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10833 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10834 ctx
.stage
== tess_eval_geometry_gs
));
10836 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10837 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10838 if (check_merged_wave_info
) {
10839 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10840 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10844 Builder
bld(ctx
.program
, ctx
.block
);
10846 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10847 bld
.sopp(aco_opcode::s_barrier
);
10849 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10850 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10852 } else if (ctx
.stage
== geometry_gs
)
10853 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10855 if (ctx
.stage
== fragment_fs
)
10856 handle_bc_optimize(&ctx
);
10858 visit_cf_list(&ctx
, &func
->body
);
10860 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10861 emit_streamout(&ctx
, 0);
10863 if (ctx
.stage
& hw_vs
) {
10864 create_vs_exports(&ctx
);
10865 ctx
.block
->kind
|= block_kind_export_end
;
10866 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10867 ngg_emit_nogs_output(&ctx
);
10868 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10869 Builder
bld(ctx
.program
, ctx
.block
);
10870 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10871 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10872 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10873 write_tcs_tess_factors(&ctx
);
10876 if (ctx
.stage
== fragment_fs
) {
10877 create_fs_exports(&ctx
);
10878 ctx
.block
->kind
|= block_kind_export_end
;
10881 if (endif_merged_wave_info
) {
10882 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10883 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10886 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10887 ngg_emit_nogs_output(&ctx
);
10889 ralloc_free(ctx
.divergent_vals
);
10891 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10892 /* Outputs of the previous stage are inputs to the next stage */
10893 ctx
.inputs
= ctx
.outputs
;
10894 ctx
.outputs
= shader_io_state();
10898 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10900 append_logical_end(ctx
.block
);
10901 ctx
.block
->kind
|= block_kind_uniform
;
10902 Builder
bld(ctx
.program
, ctx
.block
);
10903 if (ctx
.program
->wb_smem_l1_on_end
)
10904 bld
.smem(aco_opcode::s_dcache_wb
, false);
10905 bld
.sopp(aco_opcode::s_endpgm
);
10907 cleanup_cfg(program
);
10910 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10911 ac_shader_config
* config
,
10912 struct radv_shader_args
*args
)
10914 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10916 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10917 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10918 program
->next_fp_mode
.must_flush_denorms32
= false;
10919 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10920 program
->next_fp_mode
.care_about_round32
= false;
10921 program
->next_fp_mode
.care_about_round16_64
= false;
10922 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10923 program
->next_fp_mode
.denorm32
= 0;
10924 program
->next_fp_mode
.round32
= fp_round_ne
;
10925 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10926 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10928 add_startpgm(&ctx
);
10929 append_logical_start(ctx
.block
);
10931 Builder
bld(ctx
.program
, ctx
.block
);
10933 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10935 Operand
stream_id(0u);
10936 if (args
->shader_info
->so
.num_outputs
)
10937 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10938 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10940 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10942 std::stack
<Block
> endif_blocks
;
10944 for (unsigned stream
= 0; stream
< 4; stream
++) {
10945 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10948 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10949 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10952 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10954 unsigned BB_if_idx
= ctx
.block
->index
;
10955 Block BB_endif
= Block();
10956 if (!stream_id
.isConstant()) {
10958 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10959 append_logical_end(ctx
.block
);
10960 ctx
.block
->kind
|= block_kind_uniform
;
10961 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10963 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10965 ctx
.block
= ctx
.program
->create_and_insert_block();
10966 add_edge(BB_if_idx
, ctx
.block
);
10967 bld
.reset(ctx
.block
);
10968 append_logical_start(ctx
.block
);
10971 unsigned offset
= 0;
10972 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10973 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10976 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10977 unsigned length
= util_last_bit(output_usage_mask
);
10978 for (unsigned j
= 0; j
< length
; ++j
) {
10979 if (!(output_usage_mask
& (1 << j
)))
10982 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10983 Temp voffset
= vtx_offset
;
10984 if (const_offset
>= 4096u) {
10985 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10986 const_offset
%= 4096u;
10989 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10990 mubuf
->definitions
[0] = bld
.def(v1
);
10991 mubuf
->operands
[0] = Operand(gsvs_ring
);
10992 mubuf
->operands
[1] = Operand(voffset
);
10993 mubuf
->operands
[2] = Operand(0u);
10994 mubuf
->offen
= true;
10995 mubuf
->offset
= const_offset
;
10998 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10999 mubuf
->barrier
= barrier_none
;
11000 mubuf
->can_reorder
= true;
11002 ctx
.outputs
.mask
[i
] |= 1 << j
;
11003 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11005 bld
.insert(std::move(mubuf
));
11011 if (args
->shader_info
->so
.num_outputs
) {
11012 emit_streamout(&ctx
, stream
);
11013 bld
.reset(ctx
.block
);
11017 create_vs_exports(&ctx
);
11018 ctx
.block
->kind
|= block_kind_export_end
;
11021 if (!stream_id
.isConstant()) {
11022 append_logical_end(ctx
.block
);
11024 /* branch from then block to endif block */
11025 bld
.branch(aco_opcode::p_branch
);
11026 add_edge(ctx
.block
->index
, &BB_endif
);
11027 ctx
.block
->kind
|= block_kind_uniform
;
11029 /* emit else block */
11030 ctx
.block
= ctx
.program
->create_and_insert_block();
11031 add_edge(BB_if_idx
, ctx
.block
);
11032 bld
.reset(ctx
.block
);
11033 append_logical_start(ctx
.block
);
11035 endif_blocks
.push(std::move(BB_endif
));
11039 while (!endif_blocks
.empty()) {
11040 Block BB_endif
= std::move(endif_blocks
.top());
11041 endif_blocks
.pop();
11043 Block
*BB_else
= ctx
.block
;
11045 append_logical_end(BB_else
);
11046 /* branch from else block to endif block */
11047 bld
.branch(aco_opcode::p_branch
);
11048 add_edge(BB_else
->index
, &BB_endif
);
11049 BB_else
->kind
|= block_kind_uniform
;
11051 /** emit endif merge block */
11052 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11053 bld
.reset(ctx
.block
);
11054 append_logical_start(ctx
.block
);
11057 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11059 append_logical_end(ctx
.block
);
11060 ctx
.block
->kind
|= block_kind_uniform
;
11061 bld
.sopp(aco_opcode::s_endpgm
);
11063 cleanup_cfg(program
);