2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
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7 * to deal in the Software without restriction, including without limitation
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty
= false;
82 bool exec_potentially_empty_old
;
86 bool then_branch_divergent
;
91 static void visit_cf_list(struct isel_context
*ctx
,
92 struct exec_list
*list
);
94 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
96 succ
->logical_preds
.emplace_back(pred_idx
);
100 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
102 succ
->linear_preds
.emplace_back(pred_idx
);
105 static void add_edge(unsigned pred_idx
, Block
*succ
)
107 add_logical_edge(pred_idx
, succ
);
108 add_linear_edge(pred_idx
, succ
);
111 static void append_logical_start(Block
*b
)
113 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
116 static void append_logical_end(Block
*b
)
118 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
121 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
123 assert(ctx
->allocated
[def
->index
].id());
124 return ctx
->allocated
[def
->index
];
127 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
128 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
130 Builder
bld(ctx
->program
, ctx
->block
);
131 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
132 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
134 if (ctx
->program
->wave_size
== 32) {
137 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
142 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
144 Builder
bld(ctx
->program
, ctx
->block
);
147 dst
= bld
.tmp(src
.regClass());
149 assert(src
.size() == dst
.size());
151 if (ctx
->stage
!= fragment_fs
) {
155 bld
.copy(Definition(dst
), src
);
159 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
160 ctx
->program
->needs_wqm
|= program_needs_wqm
;
164 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
166 if (index
.regClass() == s1
)
167 return bld
.readlane(bld
.def(s1
), data
, index
);
169 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
171 /* Currently not implemented on GFX6-7 */
172 assert(ctx
->options
->chip_class
>= GFX8
);
174 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
175 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
178 /* GFX10, wave64 mode:
179 * The bpermute instruction is limited to half-wave operation, which means that it can't
180 * properly support subgroup shuffle like older generations (or wave32 mode), so we
183 if (!ctx
->has_gfx10_wave64_bpermute
) {
184 ctx
->has_gfx10_wave64_bpermute
= true;
185 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
186 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
189 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
190 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
191 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
192 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
194 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
195 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
198 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
200 if (val
.type() == RegType::sgpr
) {
201 Builder
bld(ctx
->program
, ctx
->block
);
202 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
204 assert(val
.type() == RegType::vgpr
);
208 //assumes a != 0xffffffff
209 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
212 Builder
bld(ctx
->program
, ctx
->block
);
214 if (util_is_power_of_two_or_zero(b
)) {
215 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
219 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
221 assert(info
.multiplier
<= 0xffffffff);
223 bool pre_shift
= info
.pre_shift
!= 0;
224 bool increment
= info
.increment
!= 0;
225 bool multiply
= true;
226 bool post_shift
= info
.post_shift
!= 0;
228 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
229 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
233 Temp pre_shift_dst
= a
;
235 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
236 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
239 Temp increment_dst
= pre_shift_dst
;
241 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
242 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
245 Temp multiply_dst
= increment_dst
;
247 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
248 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
249 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
253 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
257 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
259 Builder
bld(ctx
->program
, ctx
->block
);
260 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
264 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
266 /* no need to extract the whole vector */
267 if (src
.regClass() == dst_rc
) {
271 assert(src
.size() > idx
);
272 Builder
bld(ctx
->program
, ctx
->block
);
273 auto it
= ctx
->allocated_vec
.find(src
.id());
274 /* the size check needs to be early because elements other than 0 may be garbage */
275 if (it
!= ctx
->allocated_vec
.end() && it
->second
[0].size() == dst_rc
.size()) {
276 if (it
->second
[idx
].regClass() == dst_rc
) {
277 return it
->second
[idx
];
279 assert(dst_rc
.size() == it
->second
[idx
].regClass().size());
280 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
281 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
285 if (src
.size() == dst_rc
.size()) {
287 return bld
.copy(bld
.def(dst_rc
), src
);
289 Temp dst
= bld
.tmp(dst_rc
);
290 emit_extract_vector(ctx
, src
, idx
, dst
);
295 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
297 if (num_components
== 1)
299 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
301 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
302 split
->operands
[0] = Operand(vec_src
);
303 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
304 for (unsigned i
= 0; i
< num_components
; i
++) {
305 elems
[i
] = {ctx
->program
->allocateId(), RegClass(vec_src
.type(), vec_src
.size() / num_components
)};
306 split
->definitions
[i
] = Definition(elems
[i
]);
308 ctx
->block
->instructions
.emplace_back(std::move(split
));
309 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
312 /* This vector expansion uses a mask to determine which elements in the new vector
313 * come from the original vector. The other elements are undefined. */
314 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
316 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
321 Builder
bld(ctx
->program
, ctx
->block
);
322 if (num_components
== 1) {
323 if (dst
.type() == RegType::sgpr
)
324 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
326 bld
.copy(Definition(dst
), vec_src
);
330 unsigned component_size
= dst
.size() / num_components
;
331 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
333 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
334 vec
->definitions
[0] = Definition(dst
);
336 for (unsigned i
= 0; i
< num_components
; i
++) {
337 if (mask
& (1 << i
)) {
338 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
339 if (dst
.type() == RegType::sgpr
)
340 src
= bld
.as_uniform(src
);
341 vec
->operands
[i
] = Operand(src
);
343 vec
->operands
[i
] = Operand(0u);
345 elems
[i
] = vec
->operands
[i
].getTemp();
347 ctx
->block
->instructions
.emplace_back(std::move(vec
));
348 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
351 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
353 Builder
bld(ctx
->program
, ctx
->block
);
355 dst
= bld
.tmp(bld
.lm
);
357 assert(val
.regClass() == s1
);
358 assert(dst
.regClass() == bld
.lm
);
360 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
363 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
365 Builder
bld(ctx
->program
, ctx
->block
);
369 assert(val
.regClass() == bld
.lm
);
370 assert(dst
.regClass() == s1
);
372 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
373 Temp tmp
= bld
.tmp(s1
);
374 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
375 return emit_wqm(ctx
, tmp
, dst
);
378 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
380 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
381 return get_ssa_temp(ctx
, src
.src
.ssa
);
383 if (src
.src
.ssa
->num_components
== size
) {
384 bool identity_swizzle
= true;
385 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
386 if (src
.swizzle
[i
] != i
)
387 identity_swizzle
= false;
389 if (identity_swizzle
)
390 return get_ssa_temp(ctx
, src
.src
.ssa
);
393 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
394 unsigned elem_size
= vec
.size() / src
.src
.ssa
->num_components
;
395 assert(elem_size
> 0); /* TODO: 8 and 16-bit vectors not supported */
396 assert(vec
.size() % elem_size
== 0);
398 RegClass elem_rc
= RegClass(vec
.type(), elem_size
);
400 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
403 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
404 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
405 for (unsigned i
= 0; i
< size
; ++i
) {
406 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
407 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
409 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
)};
410 vec_instr
->definitions
[0] = Definition(dst
);
411 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
412 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
417 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
421 Builder
bld(ctx
->program
, ctx
->block
);
422 if (ptr
.type() == RegType::vgpr
)
423 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
424 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
425 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
428 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
430 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
431 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
432 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
433 sop2
->definitions
[0] = Definition(dst
);
435 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
436 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
439 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
440 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
442 Builder
bld(ctx
->program
, ctx
->block
);
443 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
444 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
445 if (src1
.type() == RegType::sgpr
) {
446 if (commutative
&& src0
.type() == RegType::vgpr
) {
450 } else if (src0
.type() == RegType::vgpr
&&
451 op
!= aco_opcode::v_madmk_f32
&&
452 op
!= aco_opcode::v_madak_f32
&&
453 op
!= aco_opcode::v_madmk_f16
&&
454 op
!= aco_opcode::v_madak_f16
) {
455 /* If the instruction is not commutative, we emit a VOP3A instruction */
456 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
459 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
463 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
464 assert(dst
.size() == 1);
465 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
466 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
468 bld
.vop2(op
, Definition(dst
), src0
, src1
);
472 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
473 bool flush_denorms
= false)
475 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
476 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
477 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
479 /* ensure that the instruction has at most 1 sgpr operand
480 * The optimizer will inline constants for us */
481 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
482 src0
= as_vgpr(ctx
, src0
);
483 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
484 src1
= as_vgpr(ctx
, src1
);
485 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
486 src2
= as_vgpr(ctx
, src2
);
488 Builder
bld(ctx
->program
, ctx
->block
);
489 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
490 assert(dst
.size() == 1);
491 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
492 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
494 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
498 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
500 Builder
bld(ctx
->program
, ctx
->block
);
501 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
504 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
506 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
507 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
508 assert(src0
.size() == src1
.size());
510 aco_ptr
<Instruction
> vopc
;
511 if (src1
.type() == RegType::sgpr
) {
512 if (src0
.type() == RegType::vgpr
) {
513 /* to swap the operands, we might also have to change the opcode */
515 case aco_opcode::v_cmp_lt_f32
:
516 op
= aco_opcode::v_cmp_gt_f32
;
518 case aco_opcode::v_cmp_ge_f32
:
519 op
= aco_opcode::v_cmp_le_f32
;
521 case aco_opcode::v_cmp_lt_i32
:
522 op
= aco_opcode::v_cmp_gt_i32
;
524 case aco_opcode::v_cmp_ge_i32
:
525 op
= aco_opcode::v_cmp_le_i32
;
527 case aco_opcode::v_cmp_lt_u32
:
528 op
= aco_opcode::v_cmp_gt_u32
;
530 case aco_opcode::v_cmp_ge_u32
:
531 op
= aco_opcode::v_cmp_le_u32
;
533 case aco_opcode::v_cmp_lt_f64
:
534 op
= aco_opcode::v_cmp_gt_f64
;
536 case aco_opcode::v_cmp_ge_f64
:
537 op
= aco_opcode::v_cmp_le_f64
;
539 case aco_opcode::v_cmp_lt_i64
:
540 op
= aco_opcode::v_cmp_gt_i64
;
542 case aco_opcode::v_cmp_ge_i64
:
543 op
= aco_opcode::v_cmp_le_i64
;
545 case aco_opcode::v_cmp_lt_u64
:
546 op
= aco_opcode::v_cmp_gt_u64
;
548 case aco_opcode::v_cmp_ge_u64
:
549 op
= aco_opcode::v_cmp_le_u64
;
551 default: /* eq and ne are commutative */
558 src1
= as_vgpr(ctx
, src1
);
562 Builder
bld(ctx
->program
, ctx
->block
);
563 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
566 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
568 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
569 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
570 Builder
bld(ctx
->program
, ctx
->block
);
572 assert(dst
.regClass() == bld
.lm
);
573 assert(src0
.type() == RegType::sgpr
);
574 assert(src1
.type() == RegType::sgpr
);
575 assert(src0
.regClass() == src1
.regClass());
577 /* Emit the SALU comparison instruction */
578 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
579 /* Turn the result into a per-lane bool */
580 bool_to_vector_condition(ctx
, cmp
, dst
);
583 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
584 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
586 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
587 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
588 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
589 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
591 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
592 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
593 aco_opcode op
= use_valu
? v_op
: s_op
;
594 assert(op
!= aco_opcode::num_opcodes
);
595 assert(dst
.regClass() == ctx
->program
->lane_mask
);
598 emit_vopc_instruction(ctx
, instr
, op
, dst
);
600 emit_sopc_instruction(ctx
, instr
, op
, dst
);
603 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
605 Builder
bld(ctx
->program
, ctx
->block
);
606 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
607 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
609 assert(dst
.regClass() == bld
.lm
);
610 assert(src0
.regClass() == bld
.lm
);
611 assert(src1
.regClass() == bld
.lm
);
613 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
616 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
618 Builder
bld(ctx
->program
, ctx
->block
);
619 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
620 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
621 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
623 assert(cond
.regClass() == bld
.lm
);
625 if (dst
.type() == RegType::vgpr
) {
626 aco_ptr
<Instruction
> bcsel
;
627 if (dst
.size() == 1) {
628 then
= as_vgpr(ctx
, then
);
629 els
= as_vgpr(ctx
, els
);
631 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
632 } else if (dst
.size() == 2) {
633 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
634 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
635 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
636 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
638 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
639 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
641 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
643 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
644 nir_print_instr(&instr
->instr
, stderr
);
645 fprintf(stderr
, "\n");
650 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
651 assert(dst
.regClass() == bld
.lm
);
652 assert(then
.regClass() == bld
.lm
);
653 assert(els
.regClass() == bld
.lm
);
656 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
657 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
658 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
659 assert(dst
.size() == then
.size());
660 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
661 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
663 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
664 nir_print_instr(&instr
->instr
, stderr
);
665 fprintf(stderr
, "\n");
670 /* divergent boolean bcsel
671 * this implements bcsel on bools: dst = s0 ? s1 : s2
672 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
673 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
675 if (cond
.id() != then
.id())
676 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
678 if (cond
.id() == els
.id())
679 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
681 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
682 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
685 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
686 aco_opcode op
, uint32_t undo
)
688 /* multiply by 16777216 to handle denormals */
689 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
690 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
691 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
692 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
693 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
695 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
697 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
700 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
702 if (ctx
->block
->fp_mode
.denorm32
== 0) {
703 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
707 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
710 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
712 if (ctx
->block
->fp_mode
.denorm32
== 0) {
713 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
717 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
720 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
722 if (ctx
->block
->fp_mode
.denorm32
== 0) {
723 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
727 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
730 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
732 if (ctx
->block
->fp_mode
.denorm32
== 0) {
733 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
737 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
740 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
742 if (ctx
->options
->chip_class
>= GFX7
)
743 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
745 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
746 /* TODO: create more efficient code! */
747 if (val
.type() == RegType::sgpr
)
748 val
= as_vgpr(ctx
, val
);
750 /* Split the input value. */
751 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
752 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
754 /* Extract the exponent and compute the unbiased value. */
755 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
757 /* Extract the fractional part. */
758 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
759 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
761 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
762 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
764 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
765 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
766 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
767 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
768 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
770 /* Get the sign bit. */
771 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
773 /* Decide the operation to apply depending on the unbiased exponent. */
774 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
775 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
776 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
777 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
778 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
779 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
781 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
784 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
786 if (ctx
->options
->chip_class
>= GFX7
)
787 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
789 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
790 Temp src0
= as_vgpr(ctx
, val
);
792 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
793 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
795 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
796 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
797 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
799 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
800 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
801 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
802 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
804 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
805 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
807 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
809 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
810 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
812 return add
->definitions
[0].getTemp();
815 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
817 if (!instr
->dest
.dest
.is_ssa
) {
818 fprintf(stderr
, "nir alu dst not in ssa: ");
819 nir_print_instr(&instr
->instr
, stderr
);
820 fprintf(stderr
, "\n");
823 Builder
bld(ctx
->program
, ctx
->block
);
824 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
829 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
830 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
831 for (unsigned i
= 0; i
< instr
->dest
.dest
.ssa
.num_components
; ++i
) {
832 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
833 vec
->operands
[i
] = Operand
{elems
[i
]};
835 vec
->definitions
[0] = Definition(dst
);
836 ctx
->block
->instructions
.emplace_back(std::move(vec
));
837 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
841 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
842 aco_ptr
<Instruction
> mov
;
843 if (dst
.type() == RegType::sgpr
) {
844 if (src
.type() == RegType::vgpr
)
845 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
846 else if (src
.regClass() == s1
)
847 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
848 else if (src
.regClass() == s2
)
849 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
851 unreachable("wrong src register class for nir_op_imov");
852 } else if (dst
.regClass() == v1
) {
853 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
854 } else if (dst
.regClass() == v2
) {
855 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
857 nir_print_instr(&instr
->instr
, stderr
);
858 unreachable("Should have been lowered to scalar.");
863 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
864 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
865 assert(src
.regClass() == bld
.lm
);
866 assert(dst
.regClass() == bld
.lm
);
867 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
868 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
869 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
870 } else if (dst
.regClass() == v1
) {
871 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
872 } else if (dst
.type() == RegType::sgpr
) {
873 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
874 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
876 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
877 nir_print_instr(&instr
->instr
, stderr
);
878 fprintf(stderr
, "\n");
883 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
884 if (dst
.regClass() == v1
) {
885 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
886 } else if (dst
.regClass() == s1
) {
887 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
888 } else if (dst
.size() == 2) {
889 Temp src0
= bld
.tmp(dst
.type(), 1);
890 Temp src1
= bld
.tmp(dst
.type(), 1);
891 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
893 if (dst
.regClass() == s2
) {
894 Temp carry
= bld
.tmp(s1
);
895 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
896 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
897 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
899 Temp lower
= bld
.tmp(v1
);
900 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
901 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
902 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
906 nir_print_instr(&instr
->instr
, stderr
);
907 fprintf(stderr
, "\n");
912 if (dst
.regClass() == s1
) {
913 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
914 } else if (dst
.regClass() == v1
) {
915 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
916 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
918 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
919 nir_print_instr(&instr
->instr
, stderr
);
920 fprintf(stderr
, "\n");
925 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
926 if (dst
.regClass() == s1
) {
927 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
928 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
929 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
930 } else if (dst
.regClass() == s2
) {
931 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
933 if (ctx
->program
->chip_class
>= GFX8
)
934 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
936 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
937 /* SCC gets zero-extended to 64 bit */
938 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
939 } else if (dst
.regClass() == v1
) {
940 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
941 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
942 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
943 } else if (dst
.regClass() == v2
) {
944 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
945 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
946 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
947 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
948 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
949 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
951 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
952 nir_print_instr(&instr
->instr
, stderr
);
953 fprintf(stderr
, "\n");
958 if (dst
.regClass() == v1
) {
959 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
960 } else if (dst
.regClass() == s1
) {
961 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
963 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
964 nir_print_instr(&instr
->instr
, stderr
);
965 fprintf(stderr
, "\n");
970 if (dst
.regClass() == v1
) {
971 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
972 } else if (dst
.regClass() == s1
) {
973 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
975 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
976 nir_print_instr(&instr
->instr
, stderr
);
977 fprintf(stderr
, "\n");
982 if (dst
.regClass() == v1
) {
983 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
984 } else if (dst
.regClass() == s1
) {
985 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
987 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
988 nir_print_instr(&instr
->instr
, stderr
);
989 fprintf(stderr
, "\n");
994 if (dst
.regClass() == v1
) {
995 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
996 } else if (dst
.regClass() == s1
) {
997 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
999 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1000 nir_print_instr(&instr
->instr
, stderr
);
1001 fprintf(stderr
, "\n");
1006 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1007 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1008 } else if (dst
.regClass() == v1
) {
1009 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1010 } else if (dst
.regClass() == s1
) {
1011 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1012 } else if (dst
.regClass() == s2
) {
1013 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1015 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1016 nir_print_instr(&instr
->instr
, stderr
);
1017 fprintf(stderr
, "\n");
1022 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1023 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1024 } else if (dst
.regClass() == v1
) {
1025 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1026 } else if (dst
.regClass() == s1
) {
1027 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1028 } else if (dst
.regClass() == s2
) {
1029 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1031 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1032 nir_print_instr(&instr
->instr
, stderr
);
1033 fprintf(stderr
, "\n");
1038 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1039 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1040 } else if (dst
.regClass() == v1
) {
1041 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1042 } else if (dst
.regClass() == s1
) {
1043 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1044 } else if (dst
.regClass() == s2
) {
1045 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1048 nir_print_instr(&instr
->instr
, stderr
);
1049 fprintf(stderr
, "\n");
1054 if (dst
.regClass() == v1
) {
1055 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1056 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1057 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1058 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1059 } else if (dst
.regClass() == v2
) {
1060 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1061 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1062 } else if (dst
.regClass() == s2
) {
1063 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1064 } else if (dst
.regClass() == s1
) {
1065 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1067 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1068 nir_print_instr(&instr
->instr
, stderr
);
1069 fprintf(stderr
, "\n");
1074 if (dst
.regClass() == v1
) {
1075 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1076 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1077 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1078 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1079 } else if (dst
.regClass() == v2
) {
1080 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1081 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1082 } else if (dst
.regClass() == s1
) {
1083 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1084 } else if (dst
.regClass() == s2
) {
1085 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1087 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1088 nir_print_instr(&instr
->instr
, stderr
);
1089 fprintf(stderr
, "\n");
1094 if (dst
.regClass() == v1
) {
1095 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1096 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1097 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1098 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1099 } else if (dst
.regClass() == v2
) {
1100 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1101 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1102 } else if (dst
.regClass() == s1
) {
1103 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1104 } else if (dst
.regClass() == s2
) {
1105 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1107 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1108 nir_print_instr(&instr
->instr
, stderr
);
1109 fprintf(stderr
, "\n");
1113 case nir_op_find_lsb
: {
1114 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1115 if (src
.regClass() == s1
) {
1116 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1117 } else if (src
.regClass() == v1
) {
1118 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1119 } else if (src
.regClass() == s2
) {
1120 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1122 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1123 nir_print_instr(&instr
->instr
, stderr
);
1124 fprintf(stderr
, "\n");
1128 case nir_op_ufind_msb
:
1129 case nir_op_ifind_msb
: {
1130 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1131 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1132 aco_opcode op
= src
.regClass() == s2
?
1133 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1134 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1135 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1137 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1138 Operand(src
.size() * 32u - 1u), msb_rev
);
1139 Temp msb
= sub
.def(0).getTemp();
1140 Temp carry
= sub
.def(1).getTemp();
1142 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, carry
);
1143 } else if (src
.regClass() == v1
) {
1144 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1145 Temp msb_rev
= bld
.tmp(v1
);
1146 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1147 Temp msb
= bld
.tmp(v1
);
1148 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1149 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1151 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1152 nir_print_instr(&instr
->instr
, stderr
);
1153 fprintf(stderr
, "\n");
1157 case nir_op_bitfield_reverse
: {
1158 if (dst
.regClass() == s1
) {
1159 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1160 } else if (dst
.regClass() == v1
) {
1161 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1163 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1164 nir_print_instr(&instr
->instr
, stderr
);
1165 fprintf(stderr
, "\n");
1170 if (dst
.regClass() == s1
) {
1171 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1175 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1176 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1177 if (dst
.regClass() == v1
) {
1178 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1182 assert(src0
.size() == 2 && src1
.size() == 2);
1183 Temp src00
= bld
.tmp(src0
.type(), 1);
1184 Temp src01
= bld
.tmp(dst
.type(), 1);
1185 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1186 Temp src10
= bld
.tmp(src1
.type(), 1);
1187 Temp src11
= bld
.tmp(dst
.type(), 1);
1188 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1190 if (dst
.regClass() == s2
) {
1191 Temp carry
= bld
.tmp(s1
);
1192 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1193 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1194 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1195 } else if (dst
.regClass() == v2
) {
1196 Temp dst0
= bld
.tmp(v1
);
1197 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1198 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1199 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1201 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1202 nir_print_instr(&instr
->instr
, stderr
);
1203 fprintf(stderr
, "\n");
1207 case nir_op_uadd_sat
: {
1208 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1209 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1210 if (dst
.regClass() == s1
) {
1211 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1212 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1214 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1215 } else if (dst
.regClass() == v1
) {
1216 if (ctx
->options
->chip_class
>= GFX9
) {
1217 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1218 add
->operands
[0] = Operand(src0
);
1219 add
->operands
[1] = Operand(src1
);
1220 add
->definitions
[0] = Definition(dst
);
1222 ctx
->block
->instructions
.emplace_back(std::move(add
));
1224 if (src1
.regClass() != v1
)
1225 std::swap(src0
, src1
);
1226 assert(src1
.regClass() == v1
);
1227 Temp tmp
= bld
.tmp(v1
);
1228 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1229 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1232 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1233 nir_print_instr(&instr
->instr
, stderr
);
1234 fprintf(stderr
, "\n");
1238 case nir_op_uadd_carry
: {
1239 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1240 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1241 if (dst
.regClass() == s1
) {
1242 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1245 if (dst
.regClass() == v1
) {
1246 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1247 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1251 Temp src00
= bld
.tmp(src0
.type(), 1);
1252 Temp src01
= bld
.tmp(dst
.type(), 1);
1253 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1254 Temp src10
= bld
.tmp(src1
.type(), 1);
1255 Temp src11
= bld
.tmp(dst
.type(), 1);
1256 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1257 if (dst
.regClass() == s2
) {
1258 Temp carry
= bld
.tmp(s1
);
1259 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1260 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1261 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1262 } else if (dst
.regClass() == v2
) {
1263 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1264 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1265 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1266 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1268 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1269 nir_print_instr(&instr
->instr
, stderr
);
1270 fprintf(stderr
, "\n");
1275 if (dst
.regClass() == s1
) {
1276 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1280 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1281 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1282 if (dst
.regClass() == v1
) {
1283 bld
.vsub32(Definition(dst
), src0
, src1
);
1287 Temp src00
= bld
.tmp(src0
.type(), 1);
1288 Temp src01
= bld
.tmp(dst
.type(), 1);
1289 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1290 Temp src10
= bld
.tmp(src1
.type(), 1);
1291 Temp src11
= bld
.tmp(dst
.type(), 1);
1292 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1293 if (dst
.regClass() == s2
) {
1294 Temp carry
= bld
.tmp(s1
);
1295 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1296 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1297 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1298 } else if (dst
.regClass() == v2
) {
1299 Temp lower
= bld
.tmp(v1
);
1300 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1301 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1302 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1304 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1305 nir_print_instr(&instr
->instr
, stderr
);
1306 fprintf(stderr
, "\n");
1310 case nir_op_usub_borrow
: {
1311 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1312 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1313 if (dst
.regClass() == s1
) {
1314 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1316 } else if (dst
.regClass() == v1
) {
1317 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1318 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1322 Temp src00
= bld
.tmp(src0
.type(), 1);
1323 Temp src01
= bld
.tmp(dst
.type(), 1);
1324 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1325 Temp src10
= bld
.tmp(src1
.type(), 1);
1326 Temp src11
= bld
.tmp(dst
.type(), 1);
1327 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1328 if (dst
.regClass() == s2
) {
1329 Temp borrow
= bld
.tmp(s1
);
1330 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1331 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1332 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1333 } else if (dst
.regClass() == v2
) {
1334 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1335 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1336 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1337 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1339 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1340 nir_print_instr(&instr
->instr
, stderr
);
1341 fprintf(stderr
, "\n");
1346 if (dst
.regClass() == v1
) {
1347 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1348 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1349 } else if (dst
.regClass() == s1
) {
1350 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1352 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1353 nir_print_instr(&instr
->instr
, stderr
);
1354 fprintf(stderr
, "\n");
1358 case nir_op_umul_high
: {
1359 if (dst
.regClass() == v1
) {
1360 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1361 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1362 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1363 } else if (dst
.regClass() == s1
) {
1364 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1365 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1366 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1368 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1369 nir_print_instr(&instr
->instr
, stderr
);
1370 fprintf(stderr
, "\n");
1374 case nir_op_imul_high
: {
1375 if (dst
.regClass() == v1
) {
1376 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1377 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1378 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1379 } else if (dst
.regClass() == s1
) {
1380 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1381 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1382 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1384 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1385 nir_print_instr(&instr
->instr
, stderr
);
1386 fprintf(stderr
, "\n");
1391 if (dst
.size() == 1) {
1392 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1393 } else if (dst
.size() == 2) {
1394 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1395 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1397 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1398 nir_print_instr(&instr
->instr
, stderr
);
1399 fprintf(stderr
, "\n");
1404 if (dst
.size() == 1) {
1405 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1406 } else if (dst
.size() == 2) {
1407 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1408 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1410 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1411 nir_print_instr(&instr
->instr
, stderr
);
1412 fprintf(stderr
, "\n");
1417 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1418 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1419 if (dst
.size() == 1) {
1420 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1421 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1423 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1424 } else if (dst
.size() == 2) {
1425 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1426 get_alu_src(ctx
, instr
->src
[0]),
1427 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1428 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1431 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1432 nir_print_instr(&instr
->instr
, stderr
);
1433 fprintf(stderr
, "\n");
1438 if (dst
.size() == 1) {
1439 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1440 } else if (dst
.size() == 2) {
1441 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1442 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
),
1443 get_alu_src(ctx
, instr
->src
[0]),
1444 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1445 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1447 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
),
1448 get_alu_src(ctx
, instr
->src
[0]),
1449 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1452 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1453 nir_print_instr(&instr
->instr
, stderr
);
1454 fprintf(stderr
, "\n");
1459 if (dst
.size() == 1) {
1460 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1461 } else if (dst
.size() == 2) {
1462 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1463 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
),
1464 get_alu_src(ctx
, instr
->src
[0]),
1465 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1466 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1468 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
),
1469 get_alu_src(ctx
, instr
->src
[0]),
1470 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1473 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1474 nir_print_instr(&instr
->instr
, stderr
);
1475 fprintf(stderr
, "\n");
1479 case nir_op_fmax3
: {
1480 if (dst
.size() == 1) {
1481 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1483 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1484 nir_print_instr(&instr
->instr
, stderr
);
1485 fprintf(stderr
, "\n");
1489 case nir_op_fmin3
: {
1490 if (dst
.size() == 1) {
1491 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1493 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1494 nir_print_instr(&instr
->instr
, stderr
);
1495 fprintf(stderr
, "\n");
1499 case nir_op_fmed3
: {
1500 if (dst
.size() == 1) {
1501 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1503 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1504 nir_print_instr(&instr
->instr
, stderr
);
1505 fprintf(stderr
, "\n");
1509 case nir_op_umax3
: {
1510 if (dst
.size() == 1) {
1511 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1513 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1514 nir_print_instr(&instr
->instr
, stderr
);
1515 fprintf(stderr
, "\n");
1519 case nir_op_umin3
: {
1520 if (dst
.size() == 1) {
1521 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1523 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1524 nir_print_instr(&instr
->instr
, stderr
);
1525 fprintf(stderr
, "\n");
1529 case nir_op_umed3
: {
1530 if (dst
.size() == 1) {
1531 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1533 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1534 nir_print_instr(&instr
->instr
, stderr
);
1535 fprintf(stderr
, "\n");
1539 case nir_op_imax3
: {
1540 if (dst
.size() == 1) {
1541 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1543 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1544 nir_print_instr(&instr
->instr
, stderr
);
1545 fprintf(stderr
, "\n");
1549 case nir_op_imin3
: {
1550 if (dst
.size() == 1) {
1551 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1553 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1554 nir_print_instr(&instr
->instr
, stderr
);
1555 fprintf(stderr
, "\n");
1559 case nir_op_imed3
: {
1560 if (dst
.size() == 1) {
1561 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1563 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1564 nir_print_instr(&instr
->instr
, stderr
);
1565 fprintf(stderr
, "\n");
1569 case nir_op_cube_face_coord
: {
1570 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1571 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1572 emit_extract_vector(ctx
, in
, 1, v1
),
1573 emit_extract_vector(ctx
, in
, 2, v1
) };
1574 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1575 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1576 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1577 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1578 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1579 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1580 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1583 case nir_op_cube_face_index
: {
1584 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1585 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1586 emit_extract_vector(ctx
, in
, 1, v1
),
1587 emit_extract_vector(ctx
, in
, 2, v1
) };
1588 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1591 case nir_op_bcsel
: {
1592 emit_bcsel(ctx
, instr
, dst
);
1596 if (dst
.size() == 1) {
1597 emit_rsq(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1598 } else if (dst
.size() == 2) {
1599 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1601 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1602 nir_print_instr(&instr
->instr
, stderr
);
1603 fprintf(stderr
, "\n");
1608 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1609 if (dst
.size() == 1) {
1610 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1611 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1612 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1613 } else if (dst
.size() == 2) {
1614 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1615 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1616 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1618 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1619 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1621 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1622 nir_print_instr(&instr
->instr
, stderr
);
1623 fprintf(stderr
, "\n");
1628 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1629 if (dst
.size() == 1) {
1630 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1631 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1632 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1633 } else if (dst
.size() == 2) {
1634 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1635 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1636 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1637 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1638 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1639 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1641 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1642 nir_print_instr(&instr
->instr
, stderr
);
1643 fprintf(stderr
, "\n");
1648 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1649 if (dst
.size() == 1) {
1650 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1651 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1652 // TODO: confirm that this holds under any circumstances
1653 } else if (dst
.size() == 2) {
1654 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1655 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1658 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1659 nir_print_instr(&instr
->instr
, stderr
);
1660 fprintf(stderr
, "\n");
1664 case nir_op_flog2
: {
1665 if (dst
.size() == 1) {
1666 emit_log2(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1668 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1669 nir_print_instr(&instr
->instr
, stderr
);
1670 fprintf(stderr
, "\n");
1675 if (dst
.size() == 1) {
1676 emit_rcp(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1677 } else if (dst
.size() == 2) {
1678 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1680 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1681 nir_print_instr(&instr
->instr
, stderr
);
1682 fprintf(stderr
, "\n");
1686 case nir_op_fexp2
: {
1687 if (dst
.size() == 1) {
1688 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1690 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1691 nir_print_instr(&instr
->instr
, stderr
);
1692 fprintf(stderr
, "\n");
1696 case nir_op_fsqrt
: {
1697 if (dst
.size() == 1) {
1698 emit_sqrt(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1699 } else if (dst
.size() == 2) {
1700 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1702 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1703 nir_print_instr(&instr
->instr
, stderr
);
1704 fprintf(stderr
, "\n");
1708 case nir_op_ffract
: {
1709 if (dst
.size() == 1) {
1710 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1711 } else if (dst
.size() == 2) {
1712 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1714 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1715 nir_print_instr(&instr
->instr
, stderr
);
1716 fprintf(stderr
, "\n");
1720 case nir_op_ffloor
: {
1721 if (dst
.size() == 1) {
1722 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1723 } else if (dst
.size() == 2) {
1724 emit_floor_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1726 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1727 nir_print_instr(&instr
->instr
, stderr
);
1728 fprintf(stderr
, "\n");
1732 case nir_op_fceil
: {
1733 if (dst
.size() == 1) {
1734 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1735 } else if (dst
.size() == 2) {
1736 if (ctx
->options
->chip_class
>= GFX7
) {
1737 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1739 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1740 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1742 /* trunc = trunc(src0)
1743 * if (src0 > 0.0 && src0 != trunc)
1746 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1747 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1748 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1749 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1750 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1751 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1752 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1755 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1756 nir_print_instr(&instr
->instr
, stderr
);
1757 fprintf(stderr
, "\n");
1761 case nir_op_ftrunc
: {
1762 if (dst
.size() == 1) {
1763 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1764 } else if (dst
.size() == 2) {
1765 emit_trunc_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1767 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1768 nir_print_instr(&instr
->instr
, stderr
);
1769 fprintf(stderr
, "\n");
1773 case nir_op_fround_even
: {
1774 if (dst
.size() == 1) {
1775 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1776 } else if (dst
.size() == 2) {
1777 if (ctx
->options
->chip_class
>= GFX7
) {
1778 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1780 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1781 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1783 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
1784 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
1786 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
1787 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
1788 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1789 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1790 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
1791 tmp
= sub
->definitions
[0].getTemp();
1793 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
1794 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
1795 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
1796 Temp cond
= vop3
->definitions
[0].getTemp();
1798 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
1799 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
1800 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
1801 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
1803 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1806 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1807 nir_print_instr(&instr
->instr
, stderr
);
1808 fprintf(stderr
, "\n");
1814 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1815 aco_ptr
<Instruction
> norm
;
1816 if (dst
.size() == 1) {
1817 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
1818 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, as_vgpr(ctx
, src
));
1820 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1821 if (ctx
->options
->chip_class
< GFX9
)
1822 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
1824 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
1825 bld
.vop1(opcode
, Definition(dst
), tmp
);
1827 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1828 nir_print_instr(&instr
->instr
, stderr
);
1829 fprintf(stderr
, "\n");
1833 case nir_op_ldexp
: {
1834 if (dst
.size() == 1) {
1835 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
),
1836 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1837 get_alu_src(ctx
, instr
->src
[1]));
1838 } else if (dst
.size() == 2) {
1839 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
),
1840 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1841 get_alu_src(ctx
, instr
->src
[1]));
1843 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1844 nir_print_instr(&instr
->instr
, stderr
);
1845 fprintf(stderr
, "\n");
1849 case nir_op_frexp_sig
: {
1850 if (dst
.size() == 1) {
1851 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
),
1852 get_alu_src(ctx
, instr
->src
[0]));
1853 } else if (dst
.size() == 2) {
1854 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
),
1855 get_alu_src(ctx
, instr
->src
[0]));
1857 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1858 nir_print_instr(&instr
->instr
, stderr
);
1859 fprintf(stderr
, "\n");
1863 case nir_op_frexp_exp
: {
1864 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1865 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
),
1866 get_alu_src(ctx
, instr
->src
[0]));
1867 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1868 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
),
1869 get_alu_src(ctx
, instr
->src
[0]));
1871 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1872 nir_print_instr(&instr
->instr
, stderr
);
1873 fprintf(stderr
, "\n");
1877 case nir_op_fsign
: {
1878 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
1879 if (dst
.size() == 1) {
1880 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1881 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
1882 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1883 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
1884 } else if (dst
.size() == 2) {
1885 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1886 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
1887 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
1889 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1890 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
1891 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
1893 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
1895 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1896 nir_print_instr(&instr
->instr
, stderr
);
1897 fprintf(stderr
, "\n");
1901 case nir_op_f2f32
: {
1902 if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1903 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
1905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1906 nir_print_instr(&instr
->instr
, stderr
);
1907 fprintf(stderr
, "\n");
1911 case nir_op_f2f64
: {
1912 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1913 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_f32
, dst
);
1915 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1916 nir_print_instr(&instr
->instr
, stderr
);
1917 fprintf(stderr
, "\n");
1921 case nir_op_i2f32
: {
1922 assert(dst
.size() == 1);
1923 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
1926 case nir_op_i2f64
: {
1927 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1928 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
1929 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1930 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1931 RegClass rc
= RegClass(src
.type(), 1);
1932 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
1933 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1934 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
1935 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
1936 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
1937 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
1940 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1941 nir_print_instr(&instr
->instr
, stderr
);
1942 fprintf(stderr
, "\n");
1946 case nir_op_u2f32
: {
1947 assert(dst
.size() == 1);
1948 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
1951 case nir_op_u2f64
: {
1952 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1953 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
1954 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1955 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1956 RegClass rc
= RegClass(src
.type(), 1);
1957 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
1958 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1959 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
1960 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
1961 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
1962 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
1964 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1965 nir_print_instr(&instr
->instr
, stderr
);
1966 fprintf(stderr
, "\n");
1970 case nir_op_f2i32
: {
1971 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1972 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1973 if (dst
.type() == RegType::vgpr
)
1974 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
1976 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
1977 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
1979 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1980 if (dst
.type() == RegType::vgpr
)
1981 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
1983 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
1984 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
1987 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1988 nir_print_instr(&instr
->instr
, stderr
);
1989 fprintf(stderr
, "\n");
1993 case nir_op_f2u32
: {
1994 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1995 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1996 if (dst
.type() == RegType::vgpr
)
1997 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
1999 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2000 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2002 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2003 if (dst
.type() == RegType::vgpr
)
2004 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2006 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2007 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2010 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2011 nir_print_instr(&instr
->instr
, stderr
);
2012 fprintf(stderr
, "\n");
2016 case nir_op_f2i64
: {
2017 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2018 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2019 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2020 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2021 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2022 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2023 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2024 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2025 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2026 Temp new_exponent
= bld
.tmp(v1
);
2027 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2028 if (ctx
->program
->chip_class
>= GFX8
)
2029 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2031 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2032 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2033 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2034 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2035 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2036 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2037 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2038 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2039 Temp new_lower
= bld
.tmp(v1
);
2040 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2041 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2042 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2044 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2045 if (src
.type() == RegType::vgpr
)
2046 src
= bld
.as_uniform(src
);
2047 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2048 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2049 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2050 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2051 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2052 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2053 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2054 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2055 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2056 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2057 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2058 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2059 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2060 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2061 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2062 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2063 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2064 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2065 Temp borrow
= bld
.tmp(s1
);
2066 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2067 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2068 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2070 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2071 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2072 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2073 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2074 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2075 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2076 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2077 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2078 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2079 if (dst
.type() == RegType::sgpr
) {
2080 lower
= bld
.as_uniform(lower
);
2081 upper
= bld
.as_uniform(upper
);
2083 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2086 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2087 nir_print_instr(&instr
->instr
, stderr
);
2088 fprintf(stderr
, "\n");
2092 case nir_op_f2u64
: {
2093 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2094 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2095 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2096 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2097 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2098 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2099 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2100 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2101 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2102 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2103 Temp new_exponent
= bld
.tmp(v1
);
2104 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2105 if (ctx
->program
->chip_class
>= GFX8
)
2106 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2108 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2109 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2110 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2111 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2112 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2113 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2114 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2115 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2117 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2118 if (src
.type() == RegType::vgpr
)
2119 src
= bld
.as_uniform(src
);
2120 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2121 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2122 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2123 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2124 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2125 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2126 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2127 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2128 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2129 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2130 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2131 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2132 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2133 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2134 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2135 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2136 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2137 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2139 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2140 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2141 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2142 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2143 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2144 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2145 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2146 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2147 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2148 if (dst
.type() == RegType::sgpr
) {
2149 lower
= bld
.as_uniform(lower
);
2150 upper
= bld
.as_uniform(upper
);
2152 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2155 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2156 nir_print_instr(&instr
->instr
, stderr
);
2157 fprintf(stderr
, "\n");
2161 case nir_op_b2f32
: {
2162 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2163 assert(src
.regClass() == bld
.lm
);
2165 if (dst
.regClass() == s1
) {
2166 src
= bool_to_scalar_condition(ctx
, src
);
2167 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2168 } else if (dst
.regClass() == v1
) {
2169 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2171 unreachable("Wrong destination register class for nir_op_b2f32.");
2175 case nir_op_b2f64
: {
2176 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2177 assert(src
.regClass() == bld
.lm
);
2179 if (dst
.regClass() == s2
) {
2180 src
= bool_to_scalar_condition(ctx
, src
);
2181 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2182 } else if (dst
.regClass() == v2
) {
2183 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2184 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2185 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2187 unreachable("Wrong destination register class for nir_op_b2f64.");
2191 case nir_op_i2i32
: {
2192 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2193 if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2194 /* we can actually just say dst = src, as it would map the lower register */
2195 emit_extract_vector(ctx
, src
, 0, dst
);
2197 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2198 nir_print_instr(&instr
->instr
, stderr
);
2199 fprintf(stderr
, "\n");
2203 case nir_op_u2u32
: {
2204 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2205 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2206 if (dst
.regClass() == s1
) {
2207 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2209 // TODO: do better with SDWA
2210 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0xFFFFu
), src
);
2212 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2213 /* we can actually just say dst = src, as it would map the lower register */
2214 emit_extract_vector(ctx
, src
, 0, dst
);
2216 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2217 nir_print_instr(&instr
->instr
, stderr
);
2218 fprintf(stderr
, "\n");
2222 case nir_op_i2i64
: {
2223 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2224 if (src
.regClass() == s1
) {
2225 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2226 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2227 } else if (src
.regClass() == v1
) {
2228 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2229 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2231 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2232 nir_print_instr(&instr
->instr
, stderr
);
2233 fprintf(stderr
, "\n");
2237 case nir_op_u2u64
: {
2238 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2239 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2240 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2242 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2243 nir_print_instr(&instr
->instr
, stderr
);
2244 fprintf(stderr
, "\n");
2248 case nir_op_b2i32
: {
2249 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2250 assert(src
.regClass() == bld
.lm
);
2252 if (dst
.regClass() == s1
) {
2253 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2254 bool_to_scalar_condition(ctx
, src
, dst
);
2255 } else if (dst
.regClass() == v1
) {
2256 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2258 unreachable("Invalid register class for b2i32");
2263 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2264 assert(dst
.regClass() == bld
.lm
);
2266 if (src
.type() == RegType::vgpr
) {
2267 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2268 assert(dst
.regClass() == bld
.lm
);
2269 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2270 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2272 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2274 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2275 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2277 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2278 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2280 bool_to_vector_condition(ctx
, tmp
, dst
);
2284 case nir_op_pack_64_2x32_split
: {
2285 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2286 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2288 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2291 case nir_op_unpack_64_2x32_split_x
:
2292 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2294 case nir_op_unpack_64_2x32_split_y
:
2295 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2297 case nir_op_pack_half_2x16
: {
2298 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2300 if (dst
.regClass() == v1
) {
2301 Temp src0
= bld
.tmp(v1
);
2302 Temp src1
= bld
.tmp(v1
);
2303 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2304 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2305 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2307 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2308 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2309 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2311 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2312 nir_print_instr(&instr
->instr
, stderr
);
2313 fprintf(stderr
, "\n");
2317 case nir_op_unpack_half_2x16_split_x
: {
2318 if (dst
.regClass() == v1
) {
2319 Builder
bld(ctx
->program
, ctx
->block
);
2320 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2322 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2323 nir_print_instr(&instr
->instr
, stderr
);
2324 fprintf(stderr
, "\n");
2328 case nir_op_unpack_half_2x16_split_y
: {
2329 if (dst
.regClass() == v1
) {
2330 Builder
bld(ctx
->program
, ctx
->block
);
2331 /* TODO: use SDWA here */
2332 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2333 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2335 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2336 nir_print_instr(&instr
->instr
, stderr
);
2337 fprintf(stderr
, "\n");
2341 case nir_op_fquantize2f16
: {
2342 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2343 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2346 if (ctx
->program
->chip_class
>= GFX8
) {
2347 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2348 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2349 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2351 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2352 * so compare the result and flush to 0 if it's smaller.
2354 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2355 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2356 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2357 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2358 cmp_res
= vop3
->definitions
[0].getTemp();
2361 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2362 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2363 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2365 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2370 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2371 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2373 if (dst
.regClass() == s1
) {
2374 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2375 } else if (dst
.regClass() == v1
) {
2376 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2378 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2379 nir_print_instr(&instr
->instr
, stderr
);
2380 fprintf(stderr
, "\n");
2384 case nir_op_bitfield_select
: {
2385 /* (mask & insert) | (~mask & base) */
2386 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2387 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2388 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2390 /* dst = (insert & bitmask) | (base & ~bitmask) */
2391 if (dst
.regClass() == s1
) {
2392 aco_ptr
<Instruction
> sop2
;
2393 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2394 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2396 if (const_insert
&& const_bitmask
) {
2397 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2399 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2400 lhs
= Operand(insert
);
2404 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2405 if (const_base
&& const_bitmask
) {
2406 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2408 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2409 rhs
= Operand(base
);
2412 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2414 } else if (dst
.regClass() == v1
) {
2415 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2416 base
= as_vgpr(ctx
, base
);
2417 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2418 insert
= as_vgpr(ctx
, insert
);
2420 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2423 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2424 nir_print_instr(&instr
->instr
, stderr
);
2425 fprintf(stderr
, "\n");
2431 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2432 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2433 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2435 if (dst
.type() == RegType::sgpr
) {
2437 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2438 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2439 if (const_offset
&& const_bits
) {
2440 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2441 extract
= Operand(const_extract
);
2445 width
= Operand(const_bits
->u32
<< 16);
2447 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2449 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2453 if (dst
.regClass() == s1
) {
2454 if (instr
->op
== nir_op_ubfe
)
2455 opcode
= aco_opcode::s_bfe_u32
;
2457 opcode
= aco_opcode::s_bfe_i32
;
2458 } else if (dst
.regClass() == s2
) {
2459 if (instr
->op
== nir_op_ubfe
)
2460 opcode
= aco_opcode::s_bfe_u64
;
2462 opcode
= aco_opcode::s_bfe_i64
;
2464 unreachable("Unsupported BFE bit size");
2467 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2471 if (dst
.regClass() == v1
) {
2472 if (instr
->op
== nir_op_ubfe
)
2473 opcode
= aco_opcode::v_bfe_u32
;
2475 opcode
= aco_opcode::v_bfe_i32
;
2477 unreachable("Unsupported BFE bit size");
2480 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2484 case nir_op_bit_count
: {
2485 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2486 if (src
.regClass() == s1
) {
2487 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2488 } else if (src
.regClass() == v1
) {
2489 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2490 } else if (src
.regClass() == v2
) {
2491 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2492 emit_extract_vector(ctx
, src
, 1, v1
),
2493 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2494 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2495 } else if (src
.regClass() == s2
) {
2496 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2498 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2499 nir_print_instr(&instr
->instr
, stderr
);
2500 fprintf(stderr
, "\n");
2505 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2509 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2513 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2517 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2521 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2525 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2529 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2530 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2532 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2533 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2537 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2538 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2540 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2541 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2545 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2549 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2554 case nir_op_fddx_fine
:
2555 case nir_op_fddy_fine
:
2556 case nir_op_fddx_coarse
:
2557 case nir_op_fddy_coarse
: {
2558 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2559 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2560 if (instr
->op
== nir_op_fddx_fine
) {
2561 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2562 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2563 } else if (instr
->op
== nir_op_fddy_fine
) {
2564 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2565 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2567 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2568 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2569 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2571 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2575 if (ctx
->program
->chip_class
>= GFX8
) {
2576 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2577 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2579 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2580 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2581 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2583 emit_wqm(ctx
, tmp
, dst
, true);
2587 fprintf(stderr
, "Unknown NIR ALU instr: ");
2588 nir_print_instr(&instr
->instr
, stderr
);
2589 fprintf(stderr
, "\n");
2593 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2595 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2597 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2598 // which get truncated the lsb if double and msb if int
2599 // for now, we only use s_mov_b64 with 64bit inline constants
2600 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2601 assert(dst
.type() == RegType::sgpr
);
2603 Builder
bld(ctx
->program
, ctx
->block
);
2605 if (instr
->def
.bit_size
== 1) {
2606 assert(dst
.regClass() == bld
.lm
);
2607 int val
= instr
->value
[0].b
? -1 : 0;
2608 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2609 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2610 } else if (dst
.size() == 1) {
2611 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2613 assert(dst
.size() != 1);
2614 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2615 if (instr
->def
.bit_size
== 64)
2616 for (unsigned i
= 0; i
< dst
.size(); i
++)
2617 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2619 for (unsigned i
= 0; i
< dst
.size(); i
++)
2620 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2622 vec
->definitions
[0] = Definition(dst
);
2623 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2627 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2629 uint32_t new_mask
= 0;
2630 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2631 if (mask
& (1u << i
))
2632 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2636 Operand
load_lds_size_m0(isel_context
*ctx
)
2638 /* TODO: m0 does not need to be initialized on GFX9+ */
2639 Builder
bld(ctx
->program
, ctx
->block
);
2640 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
2643 void load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
2644 Temp address
, unsigned base_offset
, unsigned align
)
2646 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2648 Builder
bld(ctx
->program
, ctx
->block
);
2650 Operand m
= load_lds_size_m0(ctx
);
2652 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
2653 unsigned bytes_read
= 0;
2654 unsigned result_size
= 0;
2655 unsigned total_bytes
= num_components
* elem_size_bytes
;
2656 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
2657 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
2659 while (bytes_read
< total_bytes
) {
2660 unsigned todo
= total_bytes
- bytes_read
;
2661 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
2662 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
2664 aco_opcode op
= aco_opcode::last_opcode
;
2666 if (todo
>= 16 && aligned16
&& large_ds_read
) {
2667 op
= aco_opcode::ds_read_b128
;
2669 } else if (todo
>= 16 && aligned8
) {
2670 op
= aco_opcode::ds_read2_b64
;
2673 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
2674 op
= aco_opcode::ds_read_b96
;
2676 } else if (todo
>= 8 && aligned8
) {
2677 op
= aco_opcode::ds_read_b64
;
2679 } else if (todo
>= 8) {
2680 op
= aco_opcode::ds_read2_b32
;
2683 } else if (todo
>= 4) {
2684 op
= aco_opcode::ds_read_b32
;
2689 assert(todo
% elem_size_bytes
== 0);
2690 unsigned num_elements
= todo
/ elem_size_bytes
;
2691 unsigned offset
= base_offset
+ bytes_read
;
2692 unsigned max_offset
= read2
? 1019 : 65535;
2694 Temp address_offset
= address
;
2695 if (offset
> max_offset
) {
2696 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
2697 offset
= bytes_read
;
2699 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
2702 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
2705 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
2708 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
>> 2, (offset
>> 2) + 1);
2710 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
2712 if (num_components
== 1) {
2713 assert(todo
== total_bytes
);
2714 if (dst
.type() == RegType::sgpr
)
2715 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
2719 if (dst
.type() == RegType::sgpr
) {
2720 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
2721 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
2725 if (num_elements
== 1) {
2726 result
[result_size
++] = res
;
2728 assert(res
!= dst
&& res
.size() % num_elements
== 0);
2729 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
2730 split
->operands
[0] = Operand(res
);
2731 for (unsigned i
= 0; i
< num_elements
; i
++)
2732 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
2733 ctx
->block
->instructions
.emplace_back(std::move(split
));
2739 assert(result_size
== num_components
&& result_size
> 1);
2740 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
2741 for (unsigned i
= 0; i
< result_size
; i
++)
2742 vec
->operands
[i
] = Operand(result
[i
]);
2743 vec
->definitions
[0] = Definition(dst
);
2744 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2745 ctx
->allocated_vec
.emplace(dst
.id(), result
);
2748 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
2750 if (start
== 0 && size
== data
.size())
2751 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
2753 unsigned size_hint
= 1;
2754 auto it
= ctx
->allocated_vec
.find(data
.id());
2755 if (it
!= ctx
->allocated_vec
.end())
2756 size_hint
= it
->second
[0].size();
2757 if (size
% size_hint
|| start
% size_hint
)
2764 for (unsigned i
= 0; i
< size
; i
++)
2765 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
2768 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
2770 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
2771 for (unsigned i
= 0; i
< size
; i
++)
2772 vec
->operands
[i
] = Operand(elems
[i
]);
2773 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
2774 vec
->definitions
[0] = Definition(res
);
2775 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2779 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
2781 Builder
bld(ctx
->program
, ctx
->block
);
2782 unsigned bytes_written
= 0;
2783 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
2785 while (bytes_written
< total_size
* 4) {
2786 unsigned todo
= total_size
* 4 - bytes_written
;
2787 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
2788 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
2790 aco_opcode op
= aco_opcode::last_opcode
;
2791 bool write2
= false;
2793 if (todo
>= 16 && aligned16
&& large_ds_write
) {
2794 op
= aco_opcode::ds_write_b128
;
2796 } else if (todo
>= 16 && aligned8
) {
2797 op
= aco_opcode::ds_write2_b64
;
2800 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
2801 op
= aco_opcode::ds_write_b96
;
2803 } else if (todo
>= 8 && aligned8
) {
2804 op
= aco_opcode::ds_write_b64
;
2806 } else if (todo
>= 8) {
2807 op
= aco_opcode::ds_write2_b32
;
2810 } else if (todo
>= 4) {
2811 op
= aco_opcode::ds_write_b32
;
2817 unsigned offset
= offset0
+ offset1
+ bytes_written
;
2818 unsigned max_offset
= write2
? 1020 : 65535;
2819 Temp address_offset
= address
;
2820 if (offset
> max_offset
) {
2821 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
2822 offset
= offset1
+ bytes_written
;
2824 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
2827 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
2828 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
2829 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
>> 2, (offset
>> 2) + 1);
2831 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
2832 bld
.ds(op
, address_offset
, val
, m
, offset
);
2835 bytes_written
+= size
* 4;
2839 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
2840 Temp address
, unsigned base_offset
, unsigned align
)
2842 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2844 Operand m
= load_lds_size_m0(ctx
);
2846 /* we need at most two stores for 32bit variables */
2847 int start
[2], count
[2];
2848 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
2849 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
2850 assert(wrmask
== 0);
2852 /* one combined store is sufficient */
2853 if (count
[0] == count
[1]) {
2854 Builder
bld(ctx
->program
, ctx
->block
);
2856 Temp address_offset
= address
;
2857 if ((base_offset
>> 2) + start
[1] > 255) {
2858 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
2862 assert(count
[0] == 1);
2863 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], v1
);
2864 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], v1
);
2865 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
2866 base_offset
= base_offset
/ elem_size_bytes
;
2867 bld
.ds(op
, address_offset
, val0
, val1
, m
,
2868 base_offset
+ start
[0], base_offset
+ start
[1]);
2872 for (unsigned i
= 0; i
< 2; i
++) {
2876 unsigned elem_size_words
= elem_size_bytes
/ 4;
2877 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
2878 base_offset
, start
[i
] * elem_size_bytes
, align
);
2883 void visit_store_vsgs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
2885 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
2886 unsigned component
= nir_intrinsic_component(instr
);
2887 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
2888 unsigned idx
= (nir_intrinsic_base(instr
) + component
) * 4u;
2890 Builder
bld(ctx
->program
, ctx
->block
);
2892 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
2893 if (off_instr
->type
!= nir_instr_type_load_const
)
2894 offset
= bld
.v_mul24_imm(bld
.def(v1
), get_ssa_temp(ctx
, instr
->src
[1].ssa
), 16u);
2896 idx
+= nir_instr_as_load_const(off_instr
)->value
[0].u32
* 16u;
2898 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
2899 if (ctx
->stage
== vertex_es
) {
2900 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
2902 Temp elems
[NIR_MAX_VEC_COMPONENTS
* 2];
2903 if (elem_size_bytes
== 8) {
2904 for (unsigned i
= 0; i
< src
.size() / 2; i
++) {
2905 Temp elem
= emit_extract_vector(ctx
, src
, i
, v2
);
2906 elems
[i
*2] = bld
.tmp(v1
);
2907 elems
[i
*2+1] = bld
.tmp(v1
);
2908 bld
.pseudo(aco_opcode::p_split_vector
, Definition(elems
[i
*2]), Definition(elems
[i
*2+1]), elem
);
2910 write_mask
= widen_mask(write_mask
, 2);
2911 elem_size_bytes
/= 2u;
2913 for (unsigned i
= 0; i
< src
.size(); i
++)
2914 elems
[i
] = emit_extract_vector(ctx
, src
, i
, v1
);
2917 while (write_mask
) {
2918 unsigned index
= u_bit_scan(&write_mask
);
2919 unsigned offset
= index
* elem_size_bytes
;
2920 Temp elem
= emit_extract_vector(ctx
, src
, index
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
2922 Operand
vaddr_offset(v1
);
2923 unsigned const_offset
= idx
+ offset
;
2924 if (const_offset
>= 4096u) {
2925 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
2926 const_offset
%= 4096u;
2929 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
2930 mtbuf
->operands
[0] = vaddr_offset
;
2931 mtbuf
->operands
[1] = Operand(esgs_ring
);
2932 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->es2gs_offset
));
2933 mtbuf
->operands
[3] = Operand(elem
);
2934 mtbuf
->offen
= !vaddr_offset
.isUndefined();
2935 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
2936 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
2937 mtbuf
->offset
= const_offset
;
2940 mtbuf
->barrier
= barrier_none
;
2941 mtbuf
->can_reorder
= true;
2942 bld
.insert(std::move(mtbuf
));
2945 unsigned itemsize
= ctx
->program
->info
->vs
.es_info
.esgs_itemsize
;
2947 Temp vertex_idx
= emit_mbcnt(ctx
, bld
.def(v1
));
2948 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
2949 vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), vertex_idx
,
2950 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
2952 Temp lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
2953 if (!offset
.isUndefined())
2954 lds_base
= bld
.vadd32(bld
.def(v1
), offset
, lds_base
);
2956 unsigned align
= 1 << (ffs(itemsize
) - 1);
2958 align
= std::min(align
, 1u << (ffs(idx
) - 1));
2960 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, lds_base
, idx
, align
);
2964 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
2966 if (ctx
->stage
== vertex_vs
||
2967 ctx
->stage
== fragment_fs
||
2968 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
2969 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
2970 unsigned component
= nir_intrinsic_component(instr
);
2971 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
2972 unsigned idx
= nir_intrinsic_base(instr
) + component
;
2974 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
2975 if (off_instr
->type
!= nir_instr_type_load_const
) {
2976 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
2977 nir_print_instr(off_instr
, stderr
);
2978 fprintf(stderr
, "\n");
2980 idx
+= nir_instr_as_load_const(off_instr
)->value
[0].u32
* 4u;
2982 if (instr
->src
[0].ssa
->bit_size
== 64)
2983 write_mask
= widen_mask(write_mask
, 2);
2985 for (unsigned i
= 0; i
< 8; ++i
) {
2986 if (write_mask
& (1 << i
)) {
2987 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
2988 ctx
->outputs
.outputs
[idx
/ 4u][idx
% 4u] = emit_extract_vector(ctx
, src
, i
, v1
);
2992 } else if (ctx
->stage
== vertex_es
||
2993 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
)) {
2994 visit_store_vsgs_output(ctx
, instr
);
2996 unreachable("Shader stage not implemented");
3000 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3002 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3003 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3005 Builder
bld(ctx
->program
, ctx
->block
);
3006 Temp tmp
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3007 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), tmp
, idx
, component
);
3010 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3012 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3013 for (unsigned i
= 0; i
< num_components
; i
++)
3014 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3015 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3016 assert(num_components
== 4);
3017 Builder
bld(ctx
->program
, ctx
->block
);
3018 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3021 for (Operand
& op
: vec
->operands
)
3022 op
= op
.isUndefined() ? Operand(0u) : op
;
3024 vec
->definitions
[0] = Definition(dst
);
3025 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3026 emit_split_vector(ctx
, dst
, num_components
);
3030 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3032 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3033 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3034 unsigned idx
= nir_intrinsic_base(instr
);
3035 unsigned component
= nir_intrinsic_component(instr
);
3036 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3038 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3040 assert(offset
->u32
== 0);
3042 /* the lower 15bit of the prim_mask contain the offset into LDS
3043 * while the upper bits contain the number of prims */
3044 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3045 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3046 Builder
bld(ctx
->program
, ctx
->block
);
3047 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3048 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3049 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3050 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3051 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3054 if (instr
->dest
.ssa
.num_components
== 1) {
3055 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
3057 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
3058 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
3060 Temp tmp
= {ctx
->program
->allocateId(), v1
};
3061 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
3062 vec
->operands
[i
] = Operand(tmp
);
3064 vec
->definitions
[0] = Definition(dst
);
3065 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3069 unsigned get_num_channels_from_data_format(unsigned data_format
)
3071 switch (data_format
) {
3072 case V_008F0C_BUF_DATA_FORMAT_8
:
3073 case V_008F0C_BUF_DATA_FORMAT_16
:
3074 case V_008F0C_BUF_DATA_FORMAT_32
:
3076 case V_008F0C_BUF_DATA_FORMAT_8_8
:
3077 case V_008F0C_BUF_DATA_FORMAT_16_16
:
3078 case V_008F0C_BUF_DATA_FORMAT_32_32
:
3080 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
3081 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
3082 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
3084 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
3085 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
3086 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
3087 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
3088 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
3097 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3098 * so we may need to fix it up. */
3099 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
3101 Builder
bld(ctx
->program
, ctx
->block
);
3103 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
3104 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
3106 /* For the integer-like cases, do a natural sign extension.
3108 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3109 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3112 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
3113 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
3115 /* Convert back to the right type. */
3116 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
3117 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3118 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
3119 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
3120 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
3121 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3127 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3129 Builder
bld(ctx
->program
, ctx
->block
);
3130 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3131 if (ctx
->stage
& sw_vs
) {
3133 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3134 if (off_instr
->type
!= nir_instr_type_load_const
) {
3135 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3136 nir_print_instr(off_instr
, stderr
);
3137 fprintf(stderr
, "\n");
3139 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
3141 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
3143 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
3144 unsigned component
= nir_intrinsic_component(instr
);
3145 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
3146 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
3147 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
3148 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
3150 unsigned dfmt
= attrib_format
& 0xf;
3152 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
3153 unsigned num_dfmt_channels
= get_num_channels_from_data_format(dfmt
);
3154 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
3155 unsigned num_channels
= MIN2(util_last_bit(mask
), num_dfmt_channels
);
3156 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
3157 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
3159 num_channels
= MAX2(num_channels
, 3);
3161 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, Operand(attrib_binding
* 16u));
3164 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
3165 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
3166 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
3168 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
3170 Temp divided
= bld
.tmp(v1
);
3171 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
3172 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
3174 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
3177 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
3180 index
= bld
.vadd32(bld
.def(v1
),
3181 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
3182 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
3185 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
3186 index
= bld
.vadd32(bld
.def(v1
), Operand(attrib_offset
/ attrib_stride
), index
);
3187 attrib_offset
= attrib_offset
% attrib_stride
;
3190 Operand
soffset(0u);
3191 if (attrib_offset
>= 4096) {
3192 soffset
= bld
.copy(bld
.def(s1
), Operand(attrib_offset
));
3197 switch (num_channels
) {
3199 opcode
= aco_opcode::tbuffer_load_format_x
;
3202 opcode
= aco_opcode::tbuffer_load_format_xy
;
3205 opcode
= aco_opcode::tbuffer_load_format_xyz
;
3208 opcode
= aco_opcode::tbuffer_load_format_xyzw
;
3211 unreachable("Unimplemented load_input vector size");
3214 Temp tmp
= post_shuffle
|| num_channels
!= dst
.size() || alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
|| component
? bld
.tmp(RegType::vgpr
, num_channels
) : dst
;
3216 aco_ptr
<MTBUF_instruction
> mubuf
{create_instruction
<MTBUF_instruction
>(opcode
, Format::MTBUF
, 3, 1)};
3217 mubuf
->operands
[0] = Operand(index
);
3218 mubuf
->operands
[1] = Operand(list
);
3219 mubuf
->operands
[2] = soffset
;
3220 mubuf
->definitions
[0] = Definition(tmp
);
3221 mubuf
->idxen
= true;
3222 mubuf
->can_reorder
= true;
3225 assert(attrib_offset
< 4096);
3226 mubuf
->offset
= attrib_offset
;
3227 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
3229 emit_split_vector(ctx
, tmp
, tmp
.size());
3231 if (tmp
.id() != dst
.id()) {
3232 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
3233 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
3235 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
3236 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
3237 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
3239 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3240 for (unsigned i
= 0; i
< dst
.size(); i
++) {
3241 unsigned idx
= i
+ component
;
3242 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
&& num_channels
>= 4) {
3243 Temp alpha
= emit_extract_vector(ctx
, tmp
, swizzle
[3], v1
);
3244 vec
->operands
[3] = Operand(adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, alpha
));
3245 } else if (idx
< num_channels
) {
3246 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, tmp
, swizzle
[idx
], v1
));
3247 } else if (is_float
&& idx
== 3) {
3248 vec
->operands
[i
] = Operand(0x3f800000u
);
3249 } else if (!is_float
&& idx
== 3) {
3250 vec
->operands
[i
] = Operand(1u);
3252 vec
->operands
[i
] = Operand(0u);
3255 vec
->definitions
[0] = Definition(dst
);
3256 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3257 emit_split_vector(ctx
, dst
, dst
.size());
3260 } else if (ctx
->stage
== fragment_fs
) {
3261 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3262 if (off_instr
->type
!= nir_instr_type_load_const
||
3263 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
3264 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3265 nir_print_instr(off_instr
, stderr
);
3266 fprintf(stderr
, "\n");
3269 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3270 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[0]);
3272 assert(offset
->u32
== 0);
3274 /* the lower 15bit of the prim_mask contain the offset into LDS
3275 * while the upper bits contain the number of prims */
3276 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3277 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3278 Builder
bld(ctx
->program
, ctx
->block
);
3279 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3280 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3281 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3282 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3283 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3286 unsigned idx
= nir_intrinsic_base(instr
);
3287 unsigned component
= nir_intrinsic_component(instr
);
3289 if (dst
.size() == 1) {
3290 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(2u), bld
.m0(prim_mask
), idx
, component
);
3292 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3293 for (unsigned i
= 0; i
< dst
.size(); i
++)
3294 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(2u), bld
.m0(prim_mask
), idx
, component
+ i
);
3295 vec
->definitions
[0] = Definition(dst
);
3296 bld
.insert(std::move(vec
));
3300 unreachable("Shader stage not implemented");
3304 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3306 assert(ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== geometry_gs
);
3307 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
3309 Builder
bld(ctx
->program
, ctx
->block
);
3310 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3312 Temp offset
= Temp();
3313 if (instr
->src
[0].ssa
->parent_instr
->type
!= nir_instr_type_load_const
) {
3314 /* better code could be created, but this case probably doesn't happen
3315 * much in practice */
3316 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
3317 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
3319 if (ctx
->stage
== vertex_geometry_gs
) {
3320 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
3322 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
3324 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
3327 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(s2
)),
3328 Operand(i
), indirect_vertex
);
3329 offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), offset
, elem
, cond
);
3334 if (ctx
->stage
== vertex_geometry_gs
)
3335 offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), offset
);
3337 unsigned vertex
= nir_src_as_uint(instr
->src
[0]);
3338 if (ctx
->stage
== vertex_geometry_gs
)
3340 aco_opcode::v_bfe_u32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
3341 Operand((vertex
% 2u) * 16u), Operand(16u));
3343 offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
3346 unsigned const_offset
= nir_intrinsic_base(instr
);
3347 const_offset
+= nir_intrinsic_component(instr
);
3349 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3350 if (off_instr
->type
!= nir_instr_type_load_const
) {
3351 Temp indirect_offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3352 offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u),
3353 bld
.vadd32(bld
.def(v1
), indirect_offset
, offset
));
3355 const_offset
+= nir_instr_as_load_const(off_instr
)->value
[0].u32
* 4u;
3359 offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), offset
);
3361 unsigned itemsize
= ctx
->program
->info
->vs
.es_info
.esgs_itemsize
;
3363 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
3364 if (ctx
->stage
== geometry_gs
) {
3365 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
3367 const_offset
*= ctx
->program
->wave_size
;
3369 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
3370 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3371 aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1)};
3372 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++) {
3374 for (unsigned j
= 0; j
< elem_size_bytes
/ 4; j
++) {
3375 Operand
soffset(0u);
3376 if (const_offset
>= 4096u)
3377 soffset
= bld
.copy(bld
.def(s1
), Operand(const_offset
/ 4096u * 4096u));
3379 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
3380 mubuf
->definitions
[0] = bld
.def(v1
);
3381 subelems
[j
] = mubuf
->definitions
[0].getTemp();
3382 mubuf
->operands
[0] = Operand(offset
);
3383 mubuf
->operands
[1] = Operand(esgs_ring
);
3384 mubuf
->operands
[2] = Operand(soffset
);
3385 mubuf
->offen
= true;
3386 mubuf
->offset
= const_offset
% 4096u;
3388 mubuf
->dlc
= ctx
->options
->chip_class
>= GFX10
;
3389 mubuf
->barrier
= barrier_none
;
3390 mubuf
->can_reorder
= true;
3391 bld
.insert(std::move(mubuf
));
3393 const_offset
+= ctx
->program
->wave_size
* 4u;
3396 if (elem_size_bytes
== 4)
3397 elems
[i
] = subelems
[0];
3399 elems
[i
] = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), subelems
[0], subelems
[1]);
3400 vec
->operands
[i
] = Operand(elems
[i
]);
3402 vec
->definitions
[0] = Definition(dst
);
3403 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3404 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
3406 unsigned align
= 16; /* alignment of indirect offset */
3407 align
= std::min(align
, 1u << (ffs(itemsize
) - 1));
3409 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3411 load_lds(ctx
, elem_size_bytes
, dst
, offset
, const_offset
, align
);
3415 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
3417 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
3418 Builder
bld(ctx
->program
, ctx
->block
);
3419 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
3420 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, Operand(desc_set
<< 2));//, false, false, false);
3423 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
3427 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3429 Builder
bld(ctx
->program
, ctx
->block
);
3430 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3431 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
3432 index
= bld
.as_uniform(index
);
3433 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
3434 unsigned binding
= nir_intrinsic_binding(instr
);
3437 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
3438 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
3439 unsigned offset
= layout
->binding
[binding
].offset
;
3441 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
3442 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
3443 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
3444 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
3445 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
3448 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
3449 stride
= layout
->binding
[binding
].size
;
3452 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
3453 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
3455 if (nir_const_index
) {
3456 const_index
= const_index
* stride
;
3457 } else if (index
.type() == RegType::vgpr
) {
3458 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
3459 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
3461 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
3465 if (nir_const_index
) {
3466 const_index
= const_index
+ offset
;
3467 } else if (index
.type() == RegType::vgpr
) {
3468 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
3470 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
3474 if (nir_const_index
&& const_index
== 0) {
3476 } else if (index
.type() == RegType::vgpr
) {
3477 index
= bld
.vadd32(bld
.def(v1
),
3478 nir_const_index
? Operand(const_index
) : Operand(index
),
3481 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3482 nir_const_index
? Operand(const_index
) : Operand(index
),
3486 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
3489 void load_buffer(isel_context
*ctx
, unsigned num_components
, Temp dst
,
3490 Temp rsrc
, Temp offset
, bool glc
=false, bool readonly
=true)
3492 Builder
bld(ctx
->program
, ctx
->block
);
3494 unsigned num_bytes
= dst
.size() * 4;
3495 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
3498 if (dst
.type() == RegType::vgpr
|| (ctx
->options
->chip_class
< GFX8
&& !readonly
)) {
3499 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3500 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3501 unsigned const_offset
= 0;
3503 Temp lower
= Temp();
3504 if (num_bytes
> 16) {
3505 assert(num_components
== 3 || num_components
== 4);
3506 op
= aco_opcode::buffer_load_dwordx4
;
3507 lower
= bld
.tmp(v4
);
3508 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3509 mubuf
->definitions
[0] = Definition(lower
);
3510 mubuf
->operands
[0] = vaddr
;
3511 mubuf
->operands
[1] = Operand(rsrc
);
3512 mubuf
->operands
[2] = soffset
;
3513 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3516 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
3517 mubuf
->can_reorder
= readonly
;
3518 bld
.insert(std::move(mubuf
));
3519 emit_split_vector(ctx
, lower
, 2);
3522 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
3523 /* GFX6 doesn't support loading vec3, expand to vec4. */
3527 switch (num_bytes
) {
3529 op
= aco_opcode::buffer_load_dword
;
3532 op
= aco_opcode::buffer_load_dwordx2
;
3535 assert(ctx
->options
->chip_class
> GFX6
);
3536 op
= aco_opcode::buffer_load_dwordx3
;
3539 op
= aco_opcode::buffer_load_dwordx4
;
3542 unreachable("Load SSBO not implemented for this size.");
3544 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3545 mubuf
->operands
[0] = vaddr
;
3546 mubuf
->operands
[1] = Operand(rsrc
);
3547 mubuf
->operands
[2] = soffset
;
3548 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3551 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
3552 mubuf
->can_reorder
= readonly
;
3553 mubuf
->offset
= const_offset
;
3554 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
3556 if (dst
.size() > 4) {
3557 assert(lower
!= Temp());
3558 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
3559 instr
->definitions
[0] = Definition(upper
);
3560 bld
.insert(std::move(instr
));
3561 if (dst
.size() == 8)
3562 emit_split_vector(ctx
, upper
, 2);
3563 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
3564 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
3565 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
3566 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
3567 if (dst
.size() == 8)
3568 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
3569 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
3570 Temp vec
= bld
.tmp(v4
);
3571 instr
->definitions
[0] = Definition(vec
);
3572 bld
.insert(std::move(instr
));
3573 emit_split_vector(ctx
, vec
, 4);
3575 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
3576 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
3577 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
3578 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
3581 if (dst
.type() == RegType::sgpr
) {
3582 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
3583 instr
->definitions
[0] = Definition(vec
);
3584 bld
.insert(std::move(instr
));
3585 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
3587 instr
->definitions
[0] = Definition(dst
);
3588 bld
.insert(std::move(instr
));
3589 emit_split_vector(ctx
, dst
, num_components
);
3592 switch (num_bytes
) {
3594 op
= aco_opcode::s_buffer_load_dword
;
3597 op
= aco_opcode::s_buffer_load_dwordx2
;
3601 op
= aco_opcode::s_buffer_load_dwordx4
;
3605 op
= aco_opcode::s_buffer_load_dwordx8
;
3608 unreachable("Load SSBO not implemented for this size.");
3610 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3611 load
->operands
[0] = Operand(rsrc
);
3612 load
->operands
[1] = Operand(bld
.as_uniform(offset
));
3613 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
3614 load
->definitions
[0] = Definition(dst
);
3617 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
3618 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3619 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
3622 if (dst
.size() == 3) {
3623 Temp vec
= bld
.tmp(s4
);
3624 load
->definitions
[0] = Definition(vec
);
3625 bld
.insert(std::move(load
));
3626 emit_split_vector(ctx
, vec
, 4);
3628 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
3629 emit_extract_vector(ctx
, vec
, 0, s1
),
3630 emit_extract_vector(ctx
, vec
, 1, s1
),
3631 emit_extract_vector(ctx
, vec
, 2, s1
));
3632 } else if (dst
.size() == 6) {
3633 Temp vec
= bld
.tmp(s8
);
3634 load
->definitions
[0] = Definition(vec
);
3635 bld
.insert(std::move(load
));
3636 emit_split_vector(ctx
, vec
, 4);
3638 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
3639 emit_extract_vector(ctx
, vec
, 0, s2
),
3640 emit_extract_vector(ctx
, vec
, 1, s2
),
3641 emit_extract_vector(ctx
, vec
, 2, s2
));
3643 bld
.insert(std::move(load
));
3645 emit_split_vector(ctx
, dst
, num_components
);
3649 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3651 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3652 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3654 Builder
bld(ctx
->program
, ctx
->block
);
3656 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3657 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
3658 unsigned binding
= nir_intrinsic_binding(idx_instr
);
3659 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
3661 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
3662 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3663 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3664 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3665 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3666 if (ctx
->options
->chip_class
>= GFX10
) {
3667 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3668 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3669 S_008F0C_RESOURCE_LEVEL(1);
3671 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3672 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3674 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
3675 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
3676 Operand(0xFFFFFFFFu
),
3677 Operand(desc_type
));
3678 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
3679 rsrc
, upper_dwords
);
3681 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
3682 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
3685 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
3688 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3690 Builder
bld(ctx
->program
, ctx
->block
);
3691 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3693 unsigned offset
= nir_intrinsic_base(instr
);
3694 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
3695 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
3697 unsigned count
= instr
->dest
.ssa
.num_components
;
3698 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
3699 start
-= ctx
->args
->ac
.base_inline_push_consts
;
3700 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
3701 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
3702 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
3703 for (unsigned i
= 0; i
< count
; ++i
) {
3704 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
3705 vec
->operands
[i
] = Operand
{elems
[i
]};
3707 vec
->definitions
[0] = Definition(dst
);
3708 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3709 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
3714 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
3715 if (offset
!= 0) // TODO check if index != 0 as well
3716 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
3717 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
3722 switch (dst
.size()) {
3724 op
= aco_opcode::s_load_dword
;
3727 op
= aco_opcode::s_load_dwordx2
;
3733 op
= aco_opcode::s_load_dwordx4
;
3739 op
= aco_opcode::s_load_dwordx8
;
3742 unreachable("unimplemented or forbidden load_push_constant.");
3745 bld
.smem(op
, Definition(vec
), ptr
, index
);
3748 emit_split_vector(ctx
, vec
, 4);
3749 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
3750 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
3751 emit_extract_vector(ctx
, vec
, 0, rc
),
3752 emit_extract_vector(ctx
, vec
, 1, rc
),
3753 emit_extract_vector(ctx
, vec
, 2, rc
));
3756 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
3759 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3761 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3763 Builder
bld(ctx
->program
, ctx
->block
);
3765 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3766 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3767 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3768 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3769 if (ctx
->options
->chip_class
>= GFX10
) {
3770 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3771 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3772 S_008F0C_RESOURCE_LEVEL(1);
3774 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3775 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3778 unsigned base
= nir_intrinsic_base(instr
);
3779 unsigned range
= nir_intrinsic_range(instr
);
3781 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3782 if (base
&& offset
.type() == RegType::sgpr
)
3783 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
3784 else if (base
&& offset
.type() == RegType::vgpr
)
3785 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
3787 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
3788 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
3789 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
3790 Operand(desc_type
));
3792 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, offset
);
3795 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3797 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
3798 ctx
->cf_info
.exec_potentially_empty
= true;
3800 ctx
->program
->needs_exact
= true;
3802 // TODO: optimize uniform conditions
3803 Builder
bld(ctx
->program
, ctx
->block
);
3804 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3805 assert(src
.regClass() == bld
.lm
);
3806 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
3807 bld
.pseudo(aco_opcode::p_discard_if
, src
);
3808 ctx
->block
->kind
|= block_kind_uses_discard_if
;
3812 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
3814 Builder
bld(ctx
->program
, ctx
->block
);
3816 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
3817 ctx
->cf_info
.exec_potentially_empty
= true;
3819 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
3820 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
3822 if (ctx
->block
->loop_nest_depth
&&
3823 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
3824 /* we handle discards the same way as jump instructions */
3825 append_logical_end(ctx
->block
);
3827 /* in loops, discard behaves like break */
3828 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
3829 ctx
->block
->kind
|= block_kind_discard
;
3832 /* uniform discard - loop ends here */
3833 assert(nir_instr_is_last(&instr
->instr
));
3834 ctx
->block
->kind
|= block_kind_uniform
;
3835 ctx
->cf_info
.has_branch
= true;
3836 bld
.branch(aco_opcode::p_branch
);
3837 add_linear_edge(ctx
->block
->index
, linear_target
);
3841 /* we add a break right behind the discard() instructions */
3842 ctx
->block
->kind
|= block_kind_break
;
3843 unsigned idx
= ctx
->block
->index
;
3845 /* remove critical edges from linear CFG */
3846 bld
.branch(aco_opcode::p_branch
);
3847 Block
* break_block
= ctx
->program
->create_and_insert_block();
3848 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
3849 break_block
->kind
|= block_kind_uniform
;
3850 add_linear_edge(idx
, break_block
);
3851 add_linear_edge(break_block
->index
, linear_target
);
3852 bld
.reset(break_block
);
3853 bld
.branch(aco_opcode::p_branch
);
3855 Block
* continue_block
= ctx
->program
->create_and_insert_block();
3856 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
3857 add_linear_edge(idx
, continue_block
);
3858 append_logical_start(continue_block
);
3859 ctx
->block
= continue_block
;
3864 /* it can currently happen that NIR doesn't remove the unreachable code */
3865 if (!nir_instr_is_last(&instr
->instr
)) {
3866 ctx
->program
->needs_exact
= true;
3867 /* save exec somewhere temporarily so that it doesn't get
3868 * overwritten before the discard from outer exec masks */
3869 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
3870 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
3871 ctx
->block
->kind
|= block_kind_uses_discard_if
;
3875 /* This condition is incorrect for uniformly branched discards in a loop
3876 * predicated by a divergent condition, but the above code catches that case
3877 * and the discard would end up turning into a discard_if.
3887 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
3888 /* program just ends here */
3889 ctx
->block
->kind
|= block_kind_uniform
;
3890 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
3891 0 /* enabled mask */, 9 /* dest */,
3892 false /* compressed */, true/* done */, true /* valid mask */);
3893 bld
.sopp(aco_opcode::s_endpgm
);
3894 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
3896 ctx
->block
->kind
|= block_kind_discard
;
3897 /* branch and linear edge is added by visit_if() */
3901 enum aco_descriptor_type
{
3912 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
3913 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3915 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
3916 return dim
== ac_image_cube
||
3917 dim
== ac_image_1darray
||
3918 dim
== ac_image_2darray
||
3919 dim
== ac_image_2darraymsaa
;
3922 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
3923 enum aco_descriptor_type desc_type
,
3924 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
3926 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
3927 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
3928 if (it != ctx->tex_desc.end())
3931 Temp index
= Temp();
3932 bool index_set
= false;
3933 unsigned constant_index
= 0;
3934 unsigned descriptor_set
;
3935 unsigned base_index
;
3936 Builder
bld(ctx
->program
, ctx
->block
);
3939 assert(tex_instr
&& !image
);
3941 base_index
= tex_instr
->sampler_index
;
3943 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
3944 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
3948 assert(deref_instr
->deref_type
== nir_deref_type_array
);
3949 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
3951 constant_index
+= array_size
* const_value
->u32
;
3953 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
3954 if (indirect
.type() == RegType::vgpr
)
3955 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
3957 if (array_size
!= 1)
3958 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
3964 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
3968 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
3970 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
3971 base_index
= deref_instr
->var
->data
.binding
;
3974 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
3975 list
= convert_pointer_to_64_bit(ctx
, list
);
3977 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
3978 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
3979 unsigned offset
= binding
->offset
;
3980 unsigned stride
= binding
->size
;
3984 assert(base_index
< layout
->binding_count
);
3986 switch (desc_type
) {
3987 case ACO_DESC_IMAGE
:
3989 opcode
= aco_opcode::s_load_dwordx8
;
3991 case ACO_DESC_FMASK
:
3993 opcode
= aco_opcode::s_load_dwordx8
;
3996 case ACO_DESC_SAMPLER
:
3998 opcode
= aco_opcode::s_load_dwordx4
;
3999 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
4000 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
4002 case ACO_DESC_BUFFER
:
4004 opcode
= aco_opcode::s_load_dwordx4
;
4006 case ACO_DESC_PLANE_0
:
4007 case ACO_DESC_PLANE_1
:
4009 opcode
= aco_opcode::s_load_dwordx8
;
4010 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
4012 case ACO_DESC_PLANE_2
:
4014 opcode
= aco_opcode::s_load_dwordx4
;
4018 unreachable("invalid desc_type\n");
4021 offset
+= constant_index
* stride
;
4023 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
4024 (!index_set
|| binding
->immutable_samplers_equal
)) {
4025 if (binding
->immutable_samplers_equal
)
4028 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
4029 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4030 Operand(samplers
[constant_index
* 4 + 0]),
4031 Operand(samplers
[constant_index
* 4 + 1]),
4032 Operand(samplers
[constant_index
* 4 + 2]),
4033 Operand(samplers
[constant_index
* 4 + 3]));
4038 off
= Operand(offset
);
4040 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
4041 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
4044 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
4046 if (desc_type
== ACO_DESC_PLANE_2
) {
4048 for (unsigned i
= 0; i
< 8; i
++)
4049 components
[i
] = bld
.tmp(s1
);
4050 bld
.pseudo(aco_opcode::p_split_vector
,
4051 Definition(components
[0]),
4052 Definition(components
[1]),
4053 Definition(components
[2]),
4054 Definition(components
[3]),
4057 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
4058 bld
.pseudo(aco_opcode::p_split_vector
,
4059 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
4060 Definition(components
[4]),
4061 Definition(components
[5]),
4062 Definition(components
[6]),
4063 Definition(components
[7]),
4066 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
4067 components
[0], components
[1], components
[2], components
[3],
4068 components
[4], components
[5], components
[6], components
[7]);
4074 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
4077 case GLSL_SAMPLER_DIM_BUF
:
4079 case GLSL_SAMPLER_DIM_1D
:
4080 return array
? 2 : 1;
4081 case GLSL_SAMPLER_DIM_2D
:
4082 return array
? 3 : 2;
4083 case GLSL_SAMPLER_DIM_MS
:
4084 return array
? 4 : 3;
4085 case GLSL_SAMPLER_DIM_3D
:
4086 case GLSL_SAMPLER_DIM_CUBE
:
4088 case GLSL_SAMPLER_DIM_RECT
:
4089 case GLSL_SAMPLER_DIM_SUBPASS
:
4091 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
4100 /* Adjust the sample index according to FMASK.
4102 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4103 * which is the identity mapping. Each nibble says which physical sample
4104 * should be fetched to get that sample.
4106 * For example, 0x11111100 means there are only 2 samples stored and
4107 * the second sample covers 3/4 of the pixel. When reading samples 0
4108 * and 1, return physical sample 0 (determined by the first two 0s
4109 * in FMASK), otherwise return physical sample 1.
4111 * The sample index should be adjusted as follows:
4112 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4114 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, Temp coords
, Operand sample_index
, Temp fmask_desc_ptr
)
4116 Builder
bld(ctx
->program
, ctx
->block
);
4117 Temp fmask
= bld
.tmp(v1
);
4118 unsigned dim
= ctx
->options
->chip_class
>= GFX10
4119 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
4122 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 2, 1)};
4123 load
->operands
[0] = Operand(coords
);
4124 load
->operands
[1] = Operand(fmask_desc_ptr
);
4125 load
->definitions
[0] = Definition(fmask
);
4132 load
->can_reorder
= true; /* fmask images shouldn't be modified */
4133 ctx
->block
->instructions
.emplace_back(std::move(load
));
4135 Operand sample_index4
;
4136 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
4137 sample_index4
= Operand(sample_index
.constantValue() << 2);
4138 } else if (sample_index
.regClass() == s1
) {
4139 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
4141 assert(sample_index
.regClass() == v1
);
4142 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
4146 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
4147 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
4148 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
4149 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
4151 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
4153 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4154 * resource descriptor is 0 (invalid),
4156 Temp compare
= bld
.tmp(bld
.lm
);
4157 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
4158 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
4160 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
4162 /* Replace the MSAA sample index. */
4163 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
4166 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
4169 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4170 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4171 bool is_array
= glsl_sampler_type_is_array(type
);
4172 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
4173 assert(!add_frag_pos
&& "Input attachments should be lowered.");
4174 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
4175 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
4176 int count
= image_type_to_components_count(dim
, is_array
);
4177 std::vector
<Operand
> coords(count
);
4180 Operand sample_index
;
4181 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
4183 sample_index
= Operand(sample_cv
->u32
);
4185 sample_index
= Operand(emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
), 0, v1
));
4187 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
4188 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, is_array
? 3 : 2, 1)};
4189 for (unsigned i
= 0; i
< vec
->operands
.size(); i
++)
4190 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, src0
, i
, v1
));
4191 Temp fmask_load_address
= {ctx
->program
->allocateId(), is_array
? v3
: v2
};
4192 vec
->definitions
[0] = Definition(fmask_load_address
);
4193 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4195 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
4196 sample_index
= Operand(adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
));
4199 coords
[count
] = sample_index
;
4202 if (count
== 1 && !gfx9_1d
)
4203 return emit_extract_vector(ctx
, src0
, 0, v1
);
4206 coords
[0] = Operand(emit_extract_vector(ctx
, src0
, 0, v1
));
4207 coords
.resize(coords
.size() + 1);
4208 coords
[1] = Operand((uint32_t) 0);
4210 coords
[2] = Operand(emit_extract_vector(ctx
, src0
, 1, v1
));
4212 for (int i
= 0; i
< count
; i
++)
4213 coords
[i
] = Operand(emit_extract_vector(ctx
, src0
, i
, v1
));
4216 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
4217 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
4218 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
4219 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
4222 coords
.emplace_back(Operand(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
)));
4225 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
4226 for (unsigned i
= 0; i
< coords
.size(); i
++)
4227 vec
->operands
[i
] = coords
[i
];
4228 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
4229 vec
->definitions
[0] = Definition(res
);
4230 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4235 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4237 Builder
bld(ctx
->program
, ctx
->block
);
4238 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4239 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4240 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4241 bool is_array
= glsl_sampler_type_is_array(type
);
4242 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4244 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
4245 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
4246 unsigned num_channels
= util_last_bit(mask
);
4247 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
4248 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
4251 switch (num_channels
) {
4253 opcode
= aco_opcode::buffer_load_format_x
;
4256 opcode
= aco_opcode::buffer_load_format_xy
;
4259 opcode
= aco_opcode::buffer_load_format_xyz
;
4262 opcode
= aco_opcode::buffer_load_format_xyzw
;
4265 unreachable(">4 channel buffer image load");
4267 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
4268 load
->operands
[0] = Operand(vindex
);
4269 load
->operands
[1] = Operand(rsrc
);
4270 load
->operands
[2] = Operand((uint32_t) 0);
4272 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
4275 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
4276 load
->definitions
[0] = Definition(tmp
);
4278 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
4279 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
4280 load
->barrier
= barrier_image
;
4281 ctx
->block
->instructions
.emplace_back(std::move(load
));
4283 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
4287 Temp coords
= get_image_coords(ctx
, instr
, type
);
4288 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
4290 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
4291 unsigned num_components
= util_bitcount(dmask
);
4293 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
4296 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
4298 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
4299 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
4301 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 2, 1)};
4302 load
->operands
[0] = Operand(coords
);
4303 load
->operands
[1] = Operand(resource
);
4304 load
->definitions
[0] = Definition(tmp
);
4305 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
4306 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
4307 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4308 load
->dmask
= dmask
;
4310 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
4311 load
->barrier
= barrier_image
;
4312 ctx
->block
->instructions
.emplace_back(std::move(load
));
4314 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
4318 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4320 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4321 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4322 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4323 bool is_array
= glsl_sampler_type_is_array(type
);
4324 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
4326 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
4328 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
4329 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
4330 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
4332 switch (data
.size()) {
4334 opcode
= aco_opcode::buffer_store_format_x
;
4337 opcode
= aco_opcode::buffer_store_format_xy
;
4340 opcode
= aco_opcode::buffer_store_format_xyz
;
4343 opcode
= aco_opcode::buffer_store_format_xyzw
;
4346 unreachable(">4 channel buffer image store");
4348 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
4349 store
->operands
[0] = Operand(vindex
);
4350 store
->operands
[1] = Operand(rsrc
);
4351 store
->operands
[2] = Operand((uint32_t) 0);
4352 store
->operands
[3] = Operand(data
);
4353 store
->idxen
= true;
4356 store
->disable_wqm
= true;
4357 store
->barrier
= barrier_image
;
4358 ctx
->program
->needs_exact
= true;
4359 ctx
->block
->instructions
.emplace_back(std::move(store
));
4363 assert(data
.type() == RegType::vgpr
);
4364 Temp coords
= get_image_coords(ctx
, instr
, type
);
4365 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
4367 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
4368 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
4370 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 4, 0)};
4371 store
->operands
[0] = Operand(coords
);
4372 store
->operands
[1] = Operand(resource
);
4373 store
->operands
[2] = Operand(s4
);
4374 store
->operands
[3] = Operand(data
);
4377 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4378 store
->dmask
= (1 << data
.size()) - 1;
4380 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
4381 store
->disable_wqm
= true;
4382 store
->barrier
= barrier_image
;
4383 ctx
->program
->needs_exact
= true;
4384 ctx
->block
->instructions
.emplace_back(std::move(store
));
4388 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4390 /* return the previous value if dest is ever used */
4391 bool return_previous
= false;
4392 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
4393 return_previous
= true;
4396 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
4397 return_previous
= true;
4401 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4402 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4403 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4404 bool is_array
= glsl_sampler_type_is_array(type
);
4405 Builder
bld(ctx
->program
, ctx
->block
);
4407 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
4408 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
4410 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
4411 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
4413 aco_opcode buf_op
, image_op
;
4414 switch (instr
->intrinsic
) {
4415 case nir_intrinsic_image_deref_atomic_add
:
4416 buf_op
= aco_opcode::buffer_atomic_add
;
4417 image_op
= aco_opcode::image_atomic_add
;
4419 case nir_intrinsic_image_deref_atomic_umin
:
4420 buf_op
= aco_opcode::buffer_atomic_umin
;
4421 image_op
= aco_opcode::image_atomic_umin
;
4423 case nir_intrinsic_image_deref_atomic_imin
:
4424 buf_op
= aco_opcode::buffer_atomic_smin
;
4425 image_op
= aco_opcode::image_atomic_smin
;
4427 case nir_intrinsic_image_deref_atomic_umax
:
4428 buf_op
= aco_opcode::buffer_atomic_umax
;
4429 image_op
= aco_opcode::image_atomic_umax
;
4431 case nir_intrinsic_image_deref_atomic_imax
:
4432 buf_op
= aco_opcode::buffer_atomic_smax
;
4433 image_op
= aco_opcode::image_atomic_smax
;
4435 case nir_intrinsic_image_deref_atomic_and
:
4436 buf_op
= aco_opcode::buffer_atomic_and
;
4437 image_op
= aco_opcode::image_atomic_and
;
4439 case nir_intrinsic_image_deref_atomic_or
:
4440 buf_op
= aco_opcode::buffer_atomic_or
;
4441 image_op
= aco_opcode::image_atomic_or
;
4443 case nir_intrinsic_image_deref_atomic_xor
:
4444 buf_op
= aco_opcode::buffer_atomic_xor
;
4445 image_op
= aco_opcode::image_atomic_xor
;
4447 case nir_intrinsic_image_deref_atomic_exchange
:
4448 buf_op
= aco_opcode::buffer_atomic_swap
;
4449 image_op
= aco_opcode::image_atomic_swap
;
4451 case nir_intrinsic_image_deref_atomic_comp_swap
:
4452 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
4453 image_op
= aco_opcode::image_atomic_cmpswap
;
4456 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
4459 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4461 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
4462 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
4463 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
4464 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
4465 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
4466 mubuf
->operands
[0] = Operand(vindex
);
4467 mubuf
->operands
[1] = Operand(resource
);
4468 mubuf
->operands
[2] = Operand((uint32_t)0);
4469 mubuf
->operands
[3] = Operand(data
);
4470 if (return_previous
)
4471 mubuf
->definitions
[0] = Definition(dst
);
4473 mubuf
->idxen
= true;
4474 mubuf
->glc
= return_previous
;
4475 mubuf
->dlc
= false; /* Not needed for atomics */
4476 mubuf
->disable_wqm
= true;
4477 mubuf
->barrier
= barrier_image
;
4478 ctx
->program
->needs_exact
= true;
4479 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
4483 Temp coords
= get_image_coords(ctx
, instr
, type
);
4484 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
4485 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 4, return_previous
? 1 : 0)};
4486 mimg
->operands
[0] = Operand(coords
);
4487 mimg
->operands
[1] = Operand(resource
);
4488 mimg
->operands
[2] = Operand(s4
); /* no sampler */
4489 mimg
->operands
[3] = Operand(data
);
4490 if (return_previous
)
4491 mimg
->definitions
[0] = Definition(dst
);
4492 mimg
->glc
= return_previous
;
4493 mimg
->dlc
= false; /* Not needed for atomics */
4494 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4495 mimg
->dmask
= (1 << data
.size()) - 1;
4497 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
4498 mimg
->disable_wqm
= true;
4499 mimg
->barrier
= barrier_image
;
4500 ctx
->program
->needs_exact
= true;
4501 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
4505 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
4507 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
4508 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
4509 Builder
bld(ctx
->program
, ctx
->block
);
4511 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
4513 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
4514 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
4516 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
4517 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
4519 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
4520 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
4522 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
4523 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
4524 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
4525 if (dst
.type() == RegType::vgpr
)
4526 bld
.copy(Definition(dst
), shr_dst
);
4528 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
4530 emit_extract_vector(ctx
, desc
, 2, dst
);
4534 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4536 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4537 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4538 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4539 bool is_array
= glsl_sampler_type_is_array(type
);
4540 Builder
bld(ctx
->program
, ctx
->block
);
4542 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
4543 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
4544 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
4548 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
4551 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
4553 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4555 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 2, 1)};
4556 mimg
->operands
[0] = Operand(lod
);
4557 mimg
->operands
[1] = Operand(resource
);
4558 uint8_t& dmask
= mimg
->dmask
;
4559 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4560 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
4561 mimg
->da
= glsl_sampler_type_is_array(type
);
4562 mimg
->can_reorder
= true;
4563 Definition
& def
= mimg
->definitions
[0];
4564 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
4566 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
4567 glsl_sampler_type_is_array(type
)) {
4569 assert(instr
->dest
.ssa
.num_components
== 3);
4570 Temp tmp
= {ctx
->program
->allocateId(), v3
};
4571 def
= Definition(tmp
);
4572 emit_split_vector(ctx
, tmp
, 3);
4574 /* divide 3rd value by 6 by multiplying with magic number */
4575 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
4576 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
4578 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4579 emit_extract_vector(ctx
, tmp
, 0, v1
),
4580 emit_extract_vector(ctx
, tmp
, 1, v1
),
4583 } else if (ctx
->options
->chip_class
== GFX9
&&
4584 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
4585 glsl_sampler_type_is_array(type
)) {
4586 assert(instr
->dest
.ssa
.num_components
== 2);
4587 def
= Definition(dst
);
4590 def
= Definition(dst
);
4593 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4596 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4598 Builder
bld(ctx
->program
, ctx
->block
);
4599 unsigned num_components
= instr
->num_components
;
4601 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4602 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4603 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4605 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
4606 load_buffer(ctx
, num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), glc
, false);
4609 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4611 Builder
bld(ctx
->program
, ctx
->block
);
4612 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4613 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4614 unsigned writemask
= nir_intrinsic_write_mask(instr
);
4615 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
4617 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4618 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4620 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
4621 ctx
->options
->chip_class
>= GFX8
;
4623 offset
= bld
.as_uniform(offset
);
4624 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
4628 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
4629 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
4630 /* GFX6 doesn't support storing vec3, split it. */
4631 writemask
|= 1u << (start
+ 2);
4634 int num_bytes
= count
* elem_size_bytes
;
4636 if (num_bytes
> 16) {
4637 assert(elem_size_bytes
== 8);
4638 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
4643 // TODO: check alignment of sub-dword stores
4644 // TODO: split 3 bytes. there is no store instruction for that
4647 if (count
!= instr
->num_components
) {
4648 emit_split_vector(ctx
, data
, instr
->num_components
);
4649 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4650 for (int i
= 0; i
< count
; i
++) {
4651 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
4652 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
4654 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
4655 vec
->definitions
[0] = Definition(write_data
);
4656 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4657 } else if (!smem
&& data
.type() != RegType::vgpr
) {
4658 assert(num_bytes
% 4 == 0);
4659 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
4660 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
4661 assert(num_bytes
% 4 == 0);
4662 write_data
= bld
.as_uniform(data
);
4667 aco_opcode vmem_op
, smem_op
;
4668 switch (num_bytes
) {
4670 vmem_op
= aco_opcode::buffer_store_dword
;
4671 smem_op
= aco_opcode::s_buffer_store_dword
;
4674 vmem_op
= aco_opcode::buffer_store_dwordx2
;
4675 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
4678 vmem_op
= aco_opcode::buffer_store_dwordx3
;
4679 smem_op
= aco_opcode::last_opcode
;
4680 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
4683 vmem_op
= aco_opcode::buffer_store_dwordx4
;
4684 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
4687 unreachable("Store SSBO not implemented for this size.");
4689 if (ctx
->stage
== fragment_fs
)
4690 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
4693 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
4694 store
->operands
[0] = Operand(rsrc
);
4696 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4697 offset
, Operand(start
* elem_size_bytes
));
4698 store
->operands
[1] = Operand(off
);
4700 store
->operands
[1] = Operand(offset
);
4702 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
4703 store
->operands
[1].setFixed(m0
);
4704 store
->operands
[2] = Operand(write_data
);
4705 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
4707 store
->disable_wqm
= true;
4708 store
->barrier
= barrier_buffer
;
4709 ctx
->block
->instructions
.emplace_back(std::move(store
));
4710 ctx
->program
->wb_smem_l1_on_end
= true;
4711 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
4712 ctx
->block
->kind
|= block_kind_needs_lowering
;
4713 ctx
->program
->needs_exact
= true;
4716 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
4717 store
->operands
[0] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4718 store
->operands
[1] = Operand(rsrc
);
4719 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4720 store
->operands
[3] = Operand(write_data
);
4721 store
->offset
= start
* elem_size_bytes
;
4722 store
->offen
= (offset
.type() == RegType::vgpr
);
4723 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
4725 store
->disable_wqm
= true;
4726 store
->barrier
= barrier_buffer
;
4727 ctx
->program
->needs_exact
= true;
4728 ctx
->block
->instructions
.emplace_back(std::move(store
));
4733 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4735 /* return the previous value if dest is ever used */
4736 bool return_previous
= false;
4737 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
4738 return_previous
= true;
4741 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
4742 return_previous
= true;
4746 Builder
bld(ctx
->program
, ctx
->block
);
4747 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
4749 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
4750 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
4751 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
4753 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4754 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4755 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4757 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4759 aco_opcode op32
, op64
;
4760 switch (instr
->intrinsic
) {
4761 case nir_intrinsic_ssbo_atomic_add
:
4762 op32
= aco_opcode::buffer_atomic_add
;
4763 op64
= aco_opcode::buffer_atomic_add_x2
;
4765 case nir_intrinsic_ssbo_atomic_imin
:
4766 op32
= aco_opcode::buffer_atomic_smin
;
4767 op64
= aco_opcode::buffer_atomic_smin_x2
;
4769 case nir_intrinsic_ssbo_atomic_umin
:
4770 op32
= aco_opcode::buffer_atomic_umin
;
4771 op64
= aco_opcode::buffer_atomic_umin_x2
;
4773 case nir_intrinsic_ssbo_atomic_imax
:
4774 op32
= aco_opcode::buffer_atomic_smax
;
4775 op64
= aco_opcode::buffer_atomic_smax_x2
;
4777 case nir_intrinsic_ssbo_atomic_umax
:
4778 op32
= aco_opcode::buffer_atomic_umax
;
4779 op64
= aco_opcode::buffer_atomic_umax_x2
;
4781 case nir_intrinsic_ssbo_atomic_and
:
4782 op32
= aco_opcode::buffer_atomic_and
;
4783 op64
= aco_opcode::buffer_atomic_and_x2
;
4785 case nir_intrinsic_ssbo_atomic_or
:
4786 op32
= aco_opcode::buffer_atomic_or
;
4787 op64
= aco_opcode::buffer_atomic_or_x2
;
4789 case nir_intrinsic_ssbo_atomic_xor
:
4790 op32
= aco_opcode::buffer_atomic_xor
;
4791 op64
= aco_opcode::buffer_atomic_xor_x2
;
4793 case nir_intrinsic_ssbo_atomic_exchange
:
4794 op32
= aco_opcode::buffer_atomic_swap
;
4795 op64
= aco_opcode::buffer_atomic_swap_x2
;
4797 case nir_intrinsic_ssbo_atomic_comp_swap
:
4798 op32
= aco_opcode::buffer_atomic_cmpswap
;
4799 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
4802 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
4804 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
4805 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
4806 mubuf
->operands
[0] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4807 mubuf
->operands
[1] = Operand(rsrc
);
4808 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4809 mubuf
->operands
[3] = Operand(data
);
4810 if (return_previous
)
4811 mubuf
->definitions
[0] = Definition(dst
);
4813 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4814 mubuf
->glc
= return_previous
;
4815 mubuf
->dlc
= false; /* Not needed for atomics */
4816 mubuf
->disable_wqm
= true;
4817 mubuf
->barrier
= barrier_buffer
;
4818 ctx
->program
->needs_exact
= true;
4819 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
4822 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
4824 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4825 Builder
bld(ctx
->program
, ctx
->block
);
4826 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
4827 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
4830 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
4832 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4833 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4835 if (addr
.type() == RegType::vgpr
)
4836 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
4837 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
4840 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4842 Builder
bld(ctx
->program
, ctx
->block
);
4843 unsigned num_components
= instr
->num_components
;
4844 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
4846 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4847 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4849 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
4850 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4852 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
4853 bool global
= ctx
->options
->chip_class
>= GFX9
;
4855 if (ctx
->options
->chip_class
>= GFX7
) {
4857 switch (num_bytes
) {
4859 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
4862 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
4865 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
4868 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
4871 unreachable("load_global not implemented for this size.");
4874 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
4875 flat
->operands
[0] = Operand(addr
);
4876 flat
->operands
[1] = Operand(s1
);
4879 flat
->barrier
= barrier_buffer
;
4881 if (dst
.type() == RegType::sgpr
) {
4882 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4883 flat
->definitions
[0] = Definition(vec
);
4884 ctx
->block
->instructions
.emplace_back(std::move(flat
));
4885 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
4887 flat
->definitions
[0] = Definition(dst
);
4888 ctx
->block
->instructions
.emplace_back(std::move(flat
));
4890 emit_split_vector(ctx
, dst
, num_components
);
4892 assert(ctx
->options
->chip_class
== GFX6
);
4894 /* GFX6 doesn't support loading vec3, expand to vec4. */
4895 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
4898 switch (num_bytes
) {
4900 op
= aco_opcode::buffer_load_dword
;
4903 op
= aco_opcode::buffer_load_dwordx2
;
4906 op
= aco_opcode::buffer_load_dwordx4
;
4909 unreachable("load_global not implemented for this size.");
4912 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
4914 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4915 mubuf
->operands
[0] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
4916 mubuf
->operands
[1] = Operand(rsrc
);
4917 mubuf
->operands
[2] = Operand(0u);
4921 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
4922 mubuf
->disable_wqm
= false;
4923 mubuf
->barrier
= barrier_buffer
;
4924 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4927 if (dst
.size() == 3) {
4928 Temp vec
= bld
.tmp(v4
);
4929 instr
->definitions
[0] = Definition(vec
);
4930 bld
.insert(std::move(instr
));
4931 emit_split_vector(ctx
, vec
, 4);
4933 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4934 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4935 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4936 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4939 if (dst
.type() == RegType::sgpr
) {
4940 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4941 instr
->definitions
[0] = Definition(vec
);
4942 bld
.insert(std::move(instr
));
4943 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4944 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
4946 instr
->definitions
[0] = Definition(dst
);
4947 bld
.insert(std::move(instr
));
4948 emit_split_vector(ctx
, dst
, num_components
);
4952 switch (num_bytes
) {
4954 op
= aco_opcode::s_load_dword
;
4957 op
= aco_opcode::s_load_dwordx2
;
4961 op
= aco_opcode::s_load_dwordx4
;
4964 unreachable("load_global not implemented for this size.");
4966 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4967 load
->operands
[0] = Operand(addr
);
4968 load
->operands
[1] = Operand(0u);
4969 load
->definitions
[0] = Definition(dst
);
4972 load
->barrier
= barrier_buffer
;
4973 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4975 if (dst
.size() == 3) {
4977 Temp vec
= bld
.tmp(s4
);
4978 load
->definitions
[0] = Definition(vec
);
4979 ctx
->block
->instructions
.emplace_back(std::move(load
));
4980 emit_split_vector(ctx
, vec
, 4);
4982 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4983 emit_extract_vector(ctx
, vec
, 0, s1
),
4984 emit_extract_vector(ctx
, vec
, 1, s1
),
4985 emit_extract_vector(ctx
, vec
, 2, s1
));
4987 ctx
->block
->instructions
.emplace_back(std::move(load
));
4992 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4994 Builder
bld(ctx
->program
, ctx
->block
);
4995 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4997 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4998 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5000 if (ctx
->options
->chip_class
>= GFX7
)
5001 addr
= as_vgpr(ctx
, addr
);
5003 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5006 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5007 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
5008 /* GFX6 doesn't support storing vec3, split it. */
5009 writemask
|= 1u << (start
+ 2);
5012 unsigned num_bytes
= count
* elem_size_bytes
;
5014 Temp write_data
= data
;
5015 if (count
!= instr
->num_components
) {
5016 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5017 for (int i
= 0; i
< count
; i
++)
5018 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
5019 write_data
= bld
.tmp(RegType::vgpr
, count
);
5020 vec
->definitions
[0] = Definition(write_data
);
5021 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5024 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5025 unsigned offset
= start
* elem_size_bytes
;
5027 if (ctx
->options
->chip_class
>= GFX7
) {
5028 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
5029 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
5030 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
5031 Temp carry
= bld
.tmp(bld
.lm
);
5032 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
5034 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
5035 Operand(offset
), addr0
);
5036 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
5038 carry
).def(1).setHint(vcc
);
5040 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
5045 bool global
= ctx
->options
->chip_class
>= GFX9
;
5047 switch (num_bytes
) {
5049 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
5052 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
5055 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
5058 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
5061 unreachable("store_global not implemented for this size.");
5064 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
5065 flat
->operands
[0] = Operand(addr
);
5066 flat
->operands
[1] = Operand(s1
);
5067 flat
->operands
[2] = Operand(data
);
5070 flat
->offset
= offset
;
5071 flat
->disable_wqm
= true;
5072 flat
->barrier
= barrier_buffer
;
5073 ctx
->program
->needs_exact
= true;
5074 ctx
->block
->instructions
.emplace_back(std::move(flat
));
5076 assert(ctx
->options
->chip_class
== GFX6
);
5079 switch (num_bytes
) {
5081 op
= aco_opcode::buffer_store_dword
;
5084 op
= aco_opcode::buffer_store_dwordx2
;
5087 op
= aco_opcode::buffer_store_dwordx4
;
5090 unreachable("store_global not implemented for this size.");
5093 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
5095 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
5096 mubuf
->operands
[0] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
5097 mubuf
->operands
[1] = Operand(rsrc
);
5098 mubuf
->operands
[2] = Operand(0u);
5099 mubuf
->operands
[3] = Operand(write_data
);
5102 mubuf
->offset
= offset
;
5103 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
5104 mubuf
->disable_wqm
= true;
5105 mubuf
->barrier
= barrier_buffer
;
5106 ctx
->program
->needs_exact
= true;
5107 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5112 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5114 /* return the previous value if dest is ever used */
5115 bool return_previous
= false;
5116 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5117 return_previous
= true;
5120 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5121 return_previous
= true;
5125 Builder
bld(ctx
->program
, ctx
->block
);
5126 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5127 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5129 if (ctx
->options
->chip_class
>= GFX7
)
5130 addr
= as_vgpr(ctx
, addr
);
5132 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
5133 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
5134 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
5136 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5138 aco_opcode op32
, op64
;
5140 if (ctx
->options
->chip_class
>= GFX7
) {
5141 bool global
= ctx
->options
->chip_class
>= GFX9
;
5142 switch (instr
->intrinsic
) {
5143 case nir_intrinsic_global_atomic_add
:
5144 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
5145 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
5147 case nir_intrinsic_global_atomic_imin
:
5148 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
5149 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
5151 case nir_intrinsic_global_atomic_umin
:
5152 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
5153 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
5155 case nir_intrinsic_global_atomic_imax
:
5156 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
5157 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
5159 case nir_intrinsic_global_atomic_umax
:
5160 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
5161 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
5163 case nir_intrinsic_global_atomic_and
:
5164 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
5165 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
5167 case nir_intrinsic_global_atomic_or
:
5168 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
5169 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
5171 case nir_intrinsic_global_atomic_xor
:
5172 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
5173 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
5175 case nir_intrinsic_global_atomic_exchange
:
5176 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
5177 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
5179 case nir_intrinsic_global_atomic_comp_swap
:
5180 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
5181 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
5184 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5187 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
5188 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
5189 flat
->operands
[0] = Operand(addr
);
5190 flat
->operands
[1] = Operand(s1
);
5191 flat
->operands
[2] = Operand(data
);
5192 if (return_previous
)
5193 flat
->definitions
[0] = Definition(dst
);
5194 flat
->glc
= return_previous
;
5195 flat
->dlc
= false; /* Not needed for atomics */
5197 flat
->disable_wqm
= true;
5198 flat
->barrier
= barrier_buffer
;
5199 ctx
->program
->needs_exact
= true;
5200 ctx
->block
->instructions
.emplace_back(std::move(flat
));
5202 assert(ctx
->options
->chip_class
== GFX6
);
5204 switch (instr
->intrinsic
) {
5205 case nir_intrinsic_global_atomic_add
:
5206 op32
= aco_opcode::buffer_atomic_add
;
5207 op64
= aco_opcode::buffer_atomic_add_x2
;
5209 case nir_intrinsic_global_atomic_imin
:
5210 op32
= aco_opcode::buffer_atomic_smin
;
5211 op64
= aco_opcode::buffer_atomic_smin_x2
;
5213 case nir_intrinsic_global_atomic_umin
:
5214 op32
= aco_opcode::buffer_atomic_umin
;
5215 op64
= aco_opcode::buffer_atomic_umin_x2
;
5217 case nir_intrinsic_global_atomic_imax
:
5218 op32
= aco_opcode::buffer_atomic_smax
;
5219 op64
= aco_opcode::buffer_atomic_smax_x2
;
5221 case nir_intrinsic_global_atomic_umax
:
5222 op32
= aco_opcode::buffer_atomic_umax
;
5223 op64
= aco_opcode::buffer_atomic_umax_x2
;
5225 case nir_intrinsic_global_atomic_and
:
5226 op32
= aco_opcode::buffer_atomic_and
;
5227 op64
= aco_opcode::buffer_atomic_and_x2
;
5229 case nir_intrinsic_global_atomic_or
:
5230 op32
= aco_opcode::buffer_atomic_or
;
5231 op64
= aco_opcode::buffer_atomic_or_x2
;
5233 case nir_intrinsic_global_atomic_xor
:
5234 op32
= aco_opcode::buffer_atomic_xor
;
5235 op64
= aco_opcode::buffer_atomic_xor_x2
;
5237 case nir_intrinsic_global_atomic_exchange
:
5238 op32
= aco_opcode::buffer_atomic_swap
;
5239 op64
= aco_opcode::buffer_atomic_swap_x2
;
5241 case nir_intrinsic_global_atomic_comp_swap
:
5242 op32
= aco_opcode::buffer_atomic_cmpswap
;
5243 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
5246 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5249 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
5251 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
5253 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5254 mubuf
->operands
[0] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
5255 mubuf
->operands
[1] = Operand(rsrc
);
5256 mubuf
->operands
[2] = Operand(0u);
5257 mubuf
->operands
[3] = Operand(data
);
5258 if (return_previous
)
5259 mubuf
->definitions
[0] = Definition(dst
);
5260 mubuf
->glc
= return_previous
;
5263 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
5264 mubuf
->disable_wqm
= true;
5265 mubuf
->barrier
= barrier_buffer
;
5266 ctx
->program
->needs_exact
= true;
5267 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5271 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5272 Builder
bld(ctx
->program
, ctx
->block
);
5273 switch(instr
->intrinsic
) {
5274 case nir_intrinsic_group_memory_barrier
:
5275 case nir_intrinsic_memory_barrier
:
5276 bld
.barrier(aco_opcode::p_memory_barrier_common
);
5278 case nir_intrinsic_memory_barrier_buffer
:
5279 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
5281 case nir_intrinsic_memory_barrier_image
:
5282 bld
.barrier(aco_opcode::p_memory_barrier_image
);
5284 case nir_intrinsic_memory_barrier_shared
:
5285 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
5288 unreachable("Unimplemented memory barrier intrinsic");
5293 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5295 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
5296 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5297 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
5298 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5299 Builder
bld(ctx
->program
, ctx
->block
);
5301 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5302 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
5303 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
5306 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5308 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5309 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5310 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5311 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5312 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
5314 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
5315 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
5318 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5320 unsigned offset
= nir_intrinsic_base(instr
);
5321 Operand m
= load_lds_size_m0(ctx
);
5322 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5323 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5325 unsigned num_operands
= 3;
5326 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
5327 switch(instr
->intrinsic
) {
5328 case nir_intrinsic_shared_atomic_add
:
5329 op32
= aco_opcode::ds_add_u32
;
5330 op64
= aco_opcode::ds_add_u64
;
5331 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
5332 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
5334 case nir_intrinsic_shared_atomic_imin
:
5335 op32
= aco_opcode::ds_min_i32
;
5336 op64
= aco_opcode::ds_min_i64
;
5337 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
5338 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
5340 case nir_intrinsic_shared_atomic_umin
:
5341 op32
= aco_opcode::ds_min_u32
;
5342 op64
= aco_opcode::ds_min_u64
;
5343 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
5344 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
5346 case nir_intrinsic_shared_atomic_imax
:
5347 op32
= aco_opcode::ds_max_i32
;
5348 op64
= aco_opcode::ds_max_i64
;
5349 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
5350 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
5352 case nir_intrinsic_shared_atomic_umax
:
5353 op32
= aco_opcode::ds_max_u32
;
5354 op64
= aco_opcode::ds_max_u64
;
5355 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
5356 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
5358 case nir_intrinsic_shared_atomic_and
:
5359 op32
= aco_opcode::ds_and_b32
;
5360 op64
= aco_opcode::ds_and_b64
;
5361 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
5362 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
5364 case nir_intrinsic_shared_atomic_or
:
5365 op32
= aco_opcode::ds_or_b32
;
5366 op64
= aco_opcode::ds_or_b64
;
5367 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
5368 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
5370 case nir_intrinsic_shared_atomic_xor
:
5371 op32
= aco_opcode::ds_xor_b32
;
5372 op64
= aco_opcode::ds_xor_b64
;
5373 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
5374 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
5376 case nir_intrinsic_shared_atomic_exchange
:
5377 op32
= aco_opcode::ds_write_b32
;
5378 op64
= aco_opcode::ds_write_b64
;
5379 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
5380 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
5382 case nir_intrinsic_shared_atomic_comp_swap
:
5383 op32
= aco_opcode::ds_cmpst_b32
;
5384 op64
= aco_opcode::ds_cmpst_b64
;
5385 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
5386 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
5390 unreachable("Unhandled shared atomic intrinsic");
5393 /* return the previous value if dest is ever used */
5394 bool return_previous
= false;
5395 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5396 return_previous
= true;
5399 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5400 return_previous
= true;
5405 if (data
.size() == 1) {
5406 assert(instr
->dest
.ssa
.bit_size
== 32);
5407 op
= return_previous
? op32_rtn
: op32
;
5409 assert(instr
->dest
.ssa
.bit_size
== 64);
5410 op
= return_previous
? op64_rtn
: op64
;
5413 if (offset
> 65535) {
5414 Builder
bld(ctx
->program
, ctx
->block
);
5415 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
5419 aco_ptr
<DS_instruction
> ds
;
5420 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
5421 ds
->operands
[0] = Operand(address
);
5422 ds
->operands
[1] = Operand(data
);
5423 if (num_operands
== 4)
5424 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5425 ds
->operands
[num_operands
- 1] = m
;
5426 ds
->offset0
= offset
;
5427 if (return_previous
)
5428 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
5429 ctx
->block
->instructions
.emplace_back(std::move(ds
));
5432 Temp
get_scratch_resource(isel_context
*ctx
)
5434 Builder
bld(ctx
->program
, ctx
->block
);
5435 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
5436 if (ctx
->stage
!= compute_cs
)
5437 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
5439 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
5440 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
5442 if (ctx
->program
->chip_class
>= GFX10
) {
5443 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5444 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5445 S_008F0C_RESOURCE_LEVEL(1);
5446 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
5447 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5448 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5451 /* older generations need element size = 16 bytes. element size removed in GFX9 */
5452 if (ctx
->program
->chip_class
<= GFX8
)
5453 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
5455 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
5458 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5459 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
5460 Builder
bld(ctx
->program
, ctx
->block
);
5461 Temp rsrc
= get_scratch_resource(ctx
);
5462 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5463 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5466 switch (dst
.size()) {
5468 op
= aco_opcode::buffer_load_dword
;
5471 op
= aco_opcode::buffer_load_dwordx2
;
5474 op
= aco_opcode::buffer_load_dwordx3
;
5477 op
= aco_opcode::buffer_load_dwordx4
;
5481 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5482 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
5483 bld
.def(v4
), offset
, rsrc
,
5484 ctx
->program
->scratch_offset
, 0, true);
5485 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
5486 aco_opcode::buffer_load_dwordx4
,
5487 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
5488 offset
, rsrc
, ctx
->program
->scratch_offset
, 16, true);
5489 emit_split_vector(ctx
, lower
, 2);
5490 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
5491 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
5492 if (dst
.size() == 8) {
5493 emit_split_vector(ctx
, upper
, 2);
5494 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
5495 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
5500 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
5501 Format::PSEUDO
, dst
.size() / 2, 1)};
5502 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
5503 vec
->operands
[i
] = Operand(elems
[i
]);
5504 vec
->definitions
[0] = Definition(dst
);
5505 bld
.insert(std::move(vec
));
5506 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5510 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
5513 bld
.mubuf(op
, Definition(dst
), offset
, rsrc
, ctx
->program
->scratch_offset
, 0, true);
5514 emit_split_vector(ctx
, dst
, instr
->num_components
);
5517 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5518 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
5519 Builder
bld(ctx
->program
, ctx
->block
);
5520 Temp rsrc
= get_scratch_resource(ctx
);
5521 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5522 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5524 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5525 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5529 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5530 int num_bytes
= count
* elem_size_bytes
;
5532 if (num_bytes
> 16) {
5533 assert(elem_size_bytes
== 8);
5534 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5539 // TODO: check alignment of sub-dword stores
5540 // TODO: split 3 bytes. there is no store instruction for that
5543 if (count
!= instr
->num_components
) {
5544 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5545 for (int i
= 0; i
< count
; i
++) {
5546 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
5547 vec
->operands
[i
] = Operand(elem
);
5549 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
5550 vec
->definitions
[0] = Definition(write_data
);
5551 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5557 switch (num_bytes
) {
5559 op
= aco_opcode::buffer_store_dword
;
5562 op
= aco_opcode::buffer_store_dwordx2
;
5565 op
= aco_opcode::buffer_store_dwordx3
;
5568 op
= aco_opcode::buffer_store_dwordx4
;
5571 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
5574 bld
.mubuf(op
, offset
, rsrc
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
5578 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5579 uint8_t log2_ps_iter_samples
;
5580 if (ctx
->program
->info
->ps
.force_persample
) {
5581 log2_ps_iter_samples
=
5582 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
5584 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
5587 /* The bit pattern matches that used by fixed function fragment
5589 static const unsigned ps_iter_masks
[] = {
5590 0xffff, /* not used */
5596 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
5598 Builder
bld(ctx
->program
, ctx
->block
);
5600 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
5601 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
5602 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
5603 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
5604 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5605 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
5608 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5609 Builder
bld(ctx
->program
, ctx
->block
);
5611 unsigned stream
= nir_intrinsic_stream_id(instr
);
5612 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5613 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
5614 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
5617 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
5619 unsigned num_components
=
5620 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
5621 assert(num_components
);
5623 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
5624 unsigned stream_offset
= 0;
5625 for (unsigned i
= 0; i
< stream
; i
++) {
5626 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
5627 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
5630 /* Limit on the stride field for <= GFX7. */
5631 assert(stride
< (1 << 14));
5633 Temp gsvs_dwords
[4];
5634 for (unsigned i
= 0; i
< 4; i
++)
5635 gsvs_dwords
[i
] = bld
.tmp(s1
);
5636 bld
.pseudo(aco_opcode::p_split_vector
,
5637 Definition(gsvs_dwords
[0]),
5638 Definition(gsvs_dwords
[1]),
5639 Definition(gsvs_dwords
[2]),
5640 Definition(gsvs_dwords
[3]),
5643 if (stream_offset
) {
5644 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
5646 Temp carry
= bld
.tmp(s1
);
5647 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
5648 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
5651 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
5652 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
5654 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5655 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
5657 unsigned offset
= 0;
5658 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
5659 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
5662 for (unsigned j
= 0; j
< 4; j
++) {
5663 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
5666 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
5667 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
5668 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
5669 if (const_offset
>= 4096u) {
5670 if (vaddr_offset
.isUndefined())
5671 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
5673 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
5674 const_offset
%= 4096u;
5677 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
5678 mtbuf
->operands
[0] = vaddr_offset
;
5679 mtbuf
->operands
[1] = Operand(gsvs_ring
);
5680 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
5681 mtbuf
->operands
[3] = Operand(ctx
->outputs
.outputs
[i
][j
]);
5682 mtbuf
->offen
= !vaddr_offset
.isUndefined();
5683 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
5684 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
5685 mtbuf
->offset
= const_offset
;
5688 mtbuf
->barrier
= barrier_gs_data
;
5689 mtbuf
->can_reorder
= true;
5690 bld
.insert(std::move(mtbuf
));
5693 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
5696 /* outputs for the next vertex are undefined and keeping them around can
5697 * create invalid IR with control flow */
5698 ctx
->outputs
.mask
[i
] = 0;
5701 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
5704 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
5706 Builder
bld(ctx
->program
, ctx
->block
);
5708 if (cluster_size
== 1) {
5710 } if (op
== nir_op_iand
&& cluster_size
== 4) {
5711 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
5712 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
5713 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
5714 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
5715 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
5716 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
5717 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
5718 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
5719 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
5720 //subgroupAnd(val) -> (exec & ~val) == 0
5721 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
5722 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
5723 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
5724 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
5725 //subgroupOr(val) -> (val & exec) != 0
5726 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
5727 return bool_to_vector_condition(ctx
, tmp
);
5728 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
5729 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
5730 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5731 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
5732 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
5733 return bool_to_vector_condition(ctx
, tmp
);
5735 //subgroupClustered{And,Or,Xor}(val, n) ->
5736 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
5737 //cluster_offset = ~(n - 1) & lane_id
5738 //cluster_mask = ((1 << n) - 1)
5739 //subgroupClusteredAnd():
5740 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
5741 //subgroupClusteredOr():
5742 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
5743 //subgroupClusteredXor():
5744 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
5745 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
5746 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
5749 if (op
== nir_op_iand
)
5750 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5752 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5754 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
5756 if (ctx
->program
->chip_class
<= GFX7
)
5757 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
5758 else if (ctx
->program
->wave_size
== 64)
5759 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
5761 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
5762 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
5763 if (cluster_mask
!= 0xffffffff)
5764 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
5766 Definition cmp_def
= Definition();
5767 if (op
== nir_op_iand
) {
5768 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
5769 } else if (op
== nir_op_ior
) {
5770 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
5771 } else if (op
== nir_op_ixor
) {
5772 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
5773 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
5774 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
5776 cmp_def
.setHint(vcc
);
5777 return cmp_def
.getTemp();
5781 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
5783 Builder
bld(ctx
->program
, ctx
->block
);
5785 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
5786 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
5787 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
5789 if (op
== nir_op_iand
)
5790 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
5792 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5794 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
5795 Temp lo
= lohi
.def(0).getTemp();
5796 Temp hi
= lohi
.def(1).getTemp();
5797 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
5799 Definition cmp_def
= Definition();
5800 if (op
== nir_op_iand
)
5801 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
5802 else if (op
== nir_op_ior
)
5803 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
5804 else if (op
== nir_op_ixor
)
5805 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
5806 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
5807 cmp_def
.setHint(vcc
);
5808 return cmp_def
.getTemp();
5811 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
5813 Builder
bld(ctx
->program
, ctx
->block
);
5815 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
5816 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
5817 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
5818 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
5819 if (op
== nir_op_iand
)
5820 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
5821 else if (op
== nir_op_ior
)
5822 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
5823 else if (op
== nir_op_ixor
)
5824 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
5830 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
5832 Builder
bld(ctx
->program
, ctx
->block
);
5833 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
5834 if (src
.regClass().type() == RegType::vgpr
) {
5835 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
5836 } else if (src
.regClass() == s1
) {
5837 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
5838 } else if (src
.regClass() == s2
) {
5839 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
5841 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
5842 nir_print_instr(&instr
->instr
, stderr
);
5843 fprintf(stderr
, "\n");
5847 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
5849 Builder
bld(ctx
->program
, ctx
->block
);
5850 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
5851 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
5852 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
5854 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
5855 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
5856 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
5857 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
5860 if (ctx
->program
->chip_class
>= GFX8
) {
5861 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
5862 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
5863 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
5864 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
5865 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
5866 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
5868 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
5869 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
5870 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
5871 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
5872 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
5873 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
5874 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
5875 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
5876 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
5877 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
5880 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
5881 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
5882 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
5883 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
5884 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
5885 Temp wqm1
= bld
.tmp(v1
);
5886 emit_wqm(ctx
, tmp1
, wqm1
, true);
5887 Temp wqm2
= bld
.tmp(v1
);
5888 emit_wqm(ctx
, tmp2
, wqm2
, true);
5889 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
5893 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5895 Builder
bld(ctx
->program
, ctx
->block
);
5896 switch(instr
->intrinsic
) {
5897 case nir_intrinsic_load_barycentric_sample
:
5898 case nir_intrinsic_load_barycentric_pixel
:
5899 case nir_intrinsic_load_barycentric_centroid
: {
5900 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
5901 Temp bary
= Temp(0, s2
);
5903 case INTERP_MODE_SMOOTH
:
5904 case INTERP_MODE_NONE
:
5905 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
5906 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
5907 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
5908 bary
= ctx
->persp_centroid
;
5909 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
5910 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
5912 case INTERP_MODE_NOPERSPECTIVE
:
5913 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
5914 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
5915 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
5916 bary
= ctx
->linear_centroid
;
5917 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
5918 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
5923 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5924 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
5925 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
5926 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5927 Operand(p1
), Operand(p2
));
5928 emit_split_vector(ctx
, dst
, 2);
5931 case nir_intrinsic_load_barycentric_at_sample
: {
5932 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
5933 switch (ctx
->options
->key
.fs
.num_samples
) {
5934 case 2: sample_pos_offset
+= 1 << 3; break;
5935 case 4: sample_pos_offset
+= 3 << 3; break;
5936 case 8: sample_pos_offset
+= 7 << 3; break;
5940 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5941 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
5942 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
5943 if (addr
.type() == RegType::sgpr
) {
5946 sample_pos_offset
+= const_addr
->u32
<< 3;
5947 offset
= Operand(sample_pos_offset
);
5948 } else if (ctx
->options
->chip_class
>= GFX9
) {
5949 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
5951 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
5952 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
5954 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, Operand(offset
));
5956 } else if (ctx
->options
->chip_class
>= GFX9
) {
5957 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
5958 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
5959 } else if (ctx
->options
->chip_class
>= GFX7
) {
5960 /* addr += private_segment_buffer + sample_pos_offset */
5961 Temp tmp0
= bld
.tmp(s1
);
5962 Temp tmp1
= bld
.tmp(s1
);
5963 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
5964 Definition scc_tmp
= bld
.def(s1
, scc
);
5965 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
5966 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
5967 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
5968 Temp pck0
= bld
.tmp(v1
);
5969 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
5970 tmp1
= as_vgpr(ctx
, tmp1
);
5971 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
5972 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
5974 /* sample_pos = flat_load_dwordx2 addr */
5975 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
5977 assert(ctx
->options
->chip_class
== GFX6
);
5979 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5980 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5981 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
5983 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
5984 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
5986 sample_pos
= bld
.tmp(v2
);
5988 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
5989 load
->definitions
[0] = Definition(sample_pos
);
5990 load
->operands
[0] = Operand(addr
);
5991 load
->operands
[1] = Operand(rsrc
);
5992 load
->operands
[2] = Operand(0u);
5993 load
->offset
= sample_pos_offset
;
5995 load
->addr64
= true;
5998 load
->disable_wqm
= false;
5999 load
->barrier
= barrier_none
;
6000 load
->can_reorder
= true;
6001 ctx
->block
->instructions
.emplace_back(std::move(load
));
6004 /* sample_pos -= 0.5 */
6005 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
6006 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
6007 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
6008 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
6009 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
6011 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
6014 case nir_intrinsic_load_barycentric_at_offset
: {
6015 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6016 RegClass rc
= RegClass(offset
.type(), 1);
6017 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
6018 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
6019 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
6022 case nir_intrinsic_load_front_face
: {
6023 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
6024 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
6027 case nir_intrinsic_load_view_index
:
6028 case nir_intrinsic_load_layer_id
: {
6029 if (instr
->intrinsic
== nir_intrinsic_load_view_index
&& (ctx
->stage
& (sw_vs
| sw_gs
))) {
6030 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6031 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
6035 unsigned idx
= nir_intrinsic_base(instr
);
6036 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
6037 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
6040 case nir_intrinsic_load_frag_coord
: {
6041 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
6044 case nir_intrinsic_load_sample_pos
: {
6045 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
6046 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
6047 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
6048 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
6049 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
6052 case nir_intrinsic_load_interpolated_input
:
6053 visit_load_interpolated_input(ctx
, instr
);
6055 case nir_intrinsic_store_output
:
6056 visit_store_output(ctx
, instr
);
6058 case nir_intrinsic_load_input
:
6059 visit_load_input(ctx
, instr
);
6061 case nir_intrinsic_load_per_vertex_input
:
6062 visit_load_per_vertex_input(ctx
, instr
);
6064 case nir_intrinsic_load_ubo
:
6065 visit_load_ubo(ctx
, instr
);
6067 case nir_intrinsic_load_push_constant
:
6068 visit_load_push_constant(ctx
, instr
);
6070 case nir_intrinsic_load_constant
:
6071 visit_load_constant(ctx
, instr
);
6073 case nir_intrinsic_vulkan_resource_index
:
6074 visit_load_resource(ctx
, instr
);
6076 case nir_intrinsic_discard
:
6077 visit_discard(ctx
, instr
);
6079 case nir_intrinsic_discard_if
:
6080 visit_discard_if(ctx
, instr
);
6082 case nir_intrinsic_load_shared
:
6083 visit_load_shared(ctx
, instr
);
6085 case nir_intrinsic_store_shared
:
6086 visit_store_shared(ctx
, instr
);
6088 case nir_intrinsic_shared_atomic_add
:
6089 case nir_intrinsic_shared_atomic_imin
:
6090 case nir_intrinsic_shared_atomic_umin
:
6091 case nir_intrinsic_shared_atomic_imax
:
6092 case nir_intrinsic_shared_atomic_umax
:
6093 case nir_intrinsic_shared_atomic_and
:
6094 case nir_intrinsic_shared_atomic_or
:
6095 case nir_intrinsic_shared_atomic_xor
:
6096 case nir_intrinsic_shared_atomic_exchange
:
6097 case nir_intrinsic_shared_atomic_comp_swap
:
6098 visit_shared_atomic(ctx
, instr
);
6100 case nir_intrinsic_image_deref_load
:
6101 visit_image_load(ctx
, instr
);
6103 case nir_intrinsic_image_deref_store
:
6104 visit_image_store(ctx
, instr
);
6106 case nir_intrinsic_image_deref_atomic_add
:
6107 case nir_intrinsic_image_deref_atomic_umin
:
6108 case nir_intrinsic_image_deref_atomic_imin
:
6109 case nir_intrinsic_image_deref_atomic_umax
:
6110 case nir_intrinsic_image_deref_atomic_imax
:
6111 case nir_intrinsic_image_deref_atomic_and
:
6112 case nir_intrinsic_image_deref_atomic_or
:
6113 case nir_intrinsic_image_deref_atomic_xor
:
6114 case nir_intrinsic_image_deref_atomic_exchange
:
6115 case nir_intrinsic_image_deref_atomic_comp_swap
:
6116 visit_image_atomic(ctx
, instr
);
6118 case nir_intrinsic_image_deref_size
:
6119 visit_image_size(ctx
, instr
);
6121 case nir_intrinsic_load_ssbo
:
6122 visit_load_ssbo(ctx
, instr
);
6124 case nir_intrinsic_store_ssbo
:
6125 visit_store_ssbo(ctx
, instr
);
6127 case nir_intrinsic_load_global
:
6128 visit_load_global(ctx
, instr
);
6130 case nir_intrinsic_store_global
:
6131 visit_store_global(ctx
, instr
);
6133 case nir_intrinsic_global_atomic_add
:
6134 case nir_intrinsic_global_atomic_imin
:
6135 case nir_intrinsic_global_atomic_umin
:
6136 case nir_intrinsic_global_atomic_imax
:
6137 case nir_intrinsic_global_atomic_umax
:
6138 case nir_intrinsic_global_atomic_and
:
6139 case nir_intrinsic_global_atomic_or
:
6140 case nir_intrinsic_global_atomic_xor
:
6141 case nir_intrinsic_global_atomic_exchange
:
6142 case nir_intrinsic_global_atomic_comp_swap
:
6143 visit_global_atomic(ctx
, instr
);
6145 case nir_intrinsic_ssbo_atomic_add
:
6146 case nir_intrinsic_ssbo_atomic_imin
:
6147 case nir_intrinsic_ssbo_atomic_umin
:
6148 case nir_intrinsic_ssbo_atomic_imax
:
6149 case nir_intrinsic_ssbo_atomic_umax
:
6150 case nir_intrinsic_ssbo_atomic_and
:
6151 case nir_intrinsic_ssbo_atomic_or
:
6152 case nir_intrinsic_ssbo_atomic_xor
:
6153 case nir_intrinsic_ssbo_atomic_exchange
:
6154 case nir_intrinsic_ssbo_atomic_comp_swap
:
6155 visit_atomic_ssbo(ctx
, instr
);
6157 case nir_intrinsic_load_scratch
:
6158 visit_load_scratch(ctx
, instr
);
6160 case nir_intrinsic_store_scratch
:
6161 visit_store_scratch(ctx
, instr
);
6163 case nir_intrinsic_get_buffer_size
:
6164 visit_get_buffer_size(ctx
, instr
);
6166 case nir_intrinsic_control_barrier
: {
6167 unsigned* bsize
= ctx
->program
->info
->cs
.block_size
;
6168 unsigned workgroup_size
= bsize
[0] * bsize
[1] * bsize
[2];
6169 if (workgroup_size
> ctx
->program
->wave_size
)
6170 bld
.sopp(aco_opcode::s_barrier
);
6173 case nir_intrinsic_group_memory_barrier
:
6174 case nir_intrinsic_memory_barrier
:
6175 case nir_intrinsic_memory_barrier_buffer
:
6176 case nir_intrinsic_memory_barrier_image
:
6177 case nir_intrinsic_memory_barrier_shared
:
6178 emit_memory_barrier(ctx
, instr
);
6180 case nir_intrinsic_memory_barrier_tcs_patch
:
6182 case nir_intrinsic_load_num_work_groups
: {
6183 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6184 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
6185 emit_split_vector(ctx
, dst
, 3);
6188 case nir_intrinsic_load_local_invocation_id
: {
6189 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6190 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
6191 emit_split_vector(ctx
, dst
, 3);
6194 case nir_intrinsic_load_work_group_id
: {
6195 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6196 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
6197 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6198 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
6199 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
6200 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
6201 emit_split_vector(ctx
, dst
, 3);
6204 case nir_intrinsic_load_local_invocation_index
: {
6205 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
6207 /* The tg_size bits [6:11] contain the subgroup id,
6208 * we need this multiplied by the wave size, and then OR the thread id to it.
6210 if (ctx
->program
->wave_size
== 64) {
6211 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
6212 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
6213 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
6214 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
6216 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
6217 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
6218 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
6219 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
6223 case nir_intrinsic_load_subgroup_id
: {
6224 if (ctx
->stage
== compute_cs
) {
6225 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
6226 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
6228 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
6232 case nir_intrinsic_load_subgroup_invocation
: {
6233 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
6236 case nir_intrinsic_load_num_subgroups
: {
6237 if (ctx
->stage
== compute_cs
)
6238 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
6239 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
6241 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
6244 case nir_intrinsic_ballot
: {
6245 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6246 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6247 Definition tmp
= bld
.def(dst
.regClass());
6248 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
6249 if (instr
->src
[0].ssa
->bit_size
== 1) {
6250 assert(src
.regClass() == bld
.lm
);
6251 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6252 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
6253 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
6254 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
6255 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
6257 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6258 nir_print_instr(&instr
->instr
, stderr
);
6259 fprintf(stderr
, "\n");
6261 if (dst
.size() != bld
.lm
.size()) {
6262 /* Wave32 with ballot size set to 64 */
6263 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
6265 emit_wqm(ctx
, tmp
.getTemp(), dst
);
6268 case nir_intrinsic_shuffle
:
6269 case nir_intrinsic_read_invocation
: {
6270 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6271 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
6272 emit_uniform_subgroup(ctx
, instr
, src
);
6274 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6275 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
6276 tid
= bld
.as_uniform(tid
);
6277 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6278 if (src
.regClass() == v1
) {
6279 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
6280 } else if (src
.regClass() == v2
) {
6281 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
6282 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
6283 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
6284 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
6285 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6286 emit_split_vector(ctx
, dst
, 2);
6287 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
6288 assert(src
.regClass() == bld
.lm
);
6289 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
6290 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
6291 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
6292 assert(src
.regClass() == bld
.lm
);
6294 if (ctx
->program
->chip_class
<= GFX7
)
6295 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
6296 else if (ctx
->program
->wave_size
== 64)
6297 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
6299 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
6300 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6301 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
6302 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
6304 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6305 nir_print_instr(&instr
->instr
, stderr
);
6306 fprintf(stderr
, "\n");
6311 case nir_intrinsic_load_sample_id
: {
6312 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
6313 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6316 case nir_intrinsic_load_sample_mask_in
: {
6317 visit_load_sample_mask_in(ctx
, instr
);
6320 case nir_intrinsic_read_first_invocation
: {
6321 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6322 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6323 if (src
.regClass() == v1
) {
6325 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
6327 } else if (src
.regClass() == v2
) {
6328 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
6329 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
6330 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
6331 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
6332 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6333 emit_split_vector(ctx
, dst
, 2);
6334 } else if (instr
->dest
.ssa
.bit_size
== 1) {
6335 assert(src
.regClass() == bld
.lm
);
6336 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
6337 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
6338 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
6339 } else if (src
.regClass() == s1
) {
6340 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
6341 } else if (src
.regClass() == s2
) {
6342 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
6344 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6345 nir_print_instr(&instr
->instr
, stderr
);
6346 fprintf(stderr
, "\n");
6350 case nir_intrinsic_vote_all
: {
6351 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6352 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6353 assert(src
.regClass() == bld
.lm
);
6354 assert(dst
.regClass() == bld
.lm
);
6356 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6357 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6358 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
6361 case nir_intrinsic_vote_any
: {
6362 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6363 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6364 assert(src
.regClass() == bld
.lm
);
6365 assert(dst
.regClass() == bld
.lm
);
6367 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
6368 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
6371 case nir_intrinsic_reduce
:
6372 case nir_intrinsic_inclusive_scan
:
6373 case nir_intrinsic_exclusive_scan
: {
6374 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6375 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6376 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
6377 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
6378 nir_intrinsic_cluster_size(instr
) : 0;
6379 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
6381 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
6382 emit_uniform_subgroup(ctx
, instr
, src
);
6383 } else if (instr
->dest
.ssa
.bit_size
== 1) {
6384 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
6386 else if (op
== nir_op_iadd
)
6388 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
6390 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
6392 switch (instr
->intrinsic
) {
6393 case nir_intrinsic_reduce
:
6394 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
6396 case nir_intrinsic_exclusive_scan
:
6397 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
6399 case nir_intrinsic_inclusive_scan
:
6400 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
6405 } else if (cluster_size
== 1) {
6406 bld
.copy(Definition(dst
), src
);
6408 src
= as_vgpr(ctx
, src
);
6412 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
6427 unreachable("unknown reduction op");
6432 switch (instr
->intrinsic
) {
6433 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
6434 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
6435 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
6437 unreachable("unknown reduce intrinsic");
6440 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
6441 reduce
->operands
[0] = Operand(src
);
6442 // filled in by aco_reduce_assign.cpp, used internally as part of the
6444 assert(dst
.size() == 1 || dst
.size() == 2);
6445 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
6446 reduce
->operands
[2] = Operand(v1
.as_linear());
6448 Temp tmp_dst
= bld
.tmp(dst
.regClass());
6449 reduce
->definitions
[0] = Definition(tmp_dst
);
6450 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
6451 reduce
->definitions
[2] = Definition();
6452 reduce
->definitions
[3] = Definition(scc
, s1
);
6453 reduce
->definitions
[4] = Definition();
6454 reduce
->reduce_op
= reduce_op
;
6455 reduce
->cluster_size
= cluster_size
;
6456 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
6458 emit_wqm(ctx
, tmp_dst
, dst
);
6462 case nir_intrinsic_quad_broadcast
: {
6463 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6464 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
6465 emit_uniform_subgroup(ctx
, instr
, src
);
6467 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6468 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
6469 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
6471 if (instr
->dest
.ssa
.bit_size
== 1) {
6472 assert(src
.regClass() == bld
.lm
);
6473 assert(dst
.regClass() == bld
.lm
);
6474 uint32_t half_mask
= 0x11111111u
<< lane
;
6475 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
6476 Temp tmp
= bld
.tmp(bld
.lm
);
6477 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
6478 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
6479 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
6480 emit_wqm(ctx
, tmp
, dst
);
6481 } else if (instr
->dest
.ssa
.bit_size
== 32) {
6482 if (ctx
->program
->chip_class
>= GFX8
)
6483 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
6485 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
6486 } else if (instr
->dest
.ssa
.bit_size
== 64) {
6487 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
6488 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
6489 if (ctx
->program
->chip_class
>= GFX8
) {
6490 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
6491 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
6493 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
6494 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
6496 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6497 emit_split_vector(ctx
, dst
, 2);
6499 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6500 nir_print_instr(&instr
->instr
, stderr
);
6501 fprintf(stderr
, "\n");
6506 case nir_intrinsic_quad_swap_horizontal
:
6507 case nir_intrinsic_quad_swap_vertical
:
6508 case nir_intrinsic_quad_swap_diagonal
:
6509 case nir_intrinsic_quad_swizzle_amd
: {
6510 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6511 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
6512 emit_uniform_subgroup(ctx
, instr
, src
);
6515 uint16_t dpp_ctrl
= 0;
6516 switch (instr
->intrinsic
) {
6517 case nir_intrinsic_quad_swap_horizontal
:
6518 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
6520 case nir_intrinsic_quad_swap_vertical
:
6521 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
6523 case nir_intrinsic_quad_swap_diagonal
:
6524 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
6526 case nir_intrinsic_quad_swizzle_amd
:
6527 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
6532 if (ctx
->program
->chip_class
< GFX8
)
6533 dpp_ctrl
|= (1 << 15);
6535 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6536 if (instr
->dest
.ssa
.bit_size
== 1) {
6537 assert(src
.regClass() == bld
.lm
);
6538 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
6539 if (ctx
->program
->chip_class
>= GFX8
)
6540 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
6542 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
6543 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
6544 emit_wqm(ctx
, tmp
, dst
);
6545 } else if (instr
->dest
.ssa
.bit_size
== 32) {
6547 if (ctx
->program
->chip_class
>= GFX8
)
6548 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
6550 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
6551 emit_wqm(ctx
, tmp
, dst
);
6552 } else if (instr
->dest
.ssa
.bit_size
== 64) {
6553 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
6554 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
6555 if (ctx
->program
->chip_class
>= GFX8
) {
6556 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
6557 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
6559 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
6560 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
6562 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6563 emit_split_vector(ctx
, dst
, 2);
6565 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6566 nir_print_instr(&instr
->instr
, stderr
);
6567 fprintf(stderr
, "\n");
6571 case nir_intrinsic_masked_swizzle_amd
: {
6572 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6573 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
6574 emit_uniform_subgroup(ctx
, instr
, src
);
6577 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6578 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
6579 if (dst
.regClass() == v1
) {
6581 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
6583 } else if (dst
.regClass() == v2
) {
6584 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
6585 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
6586 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
6587 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
6588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6589 emit_split_vector(ctx
, dst
, 2);
6591 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6592 nir_print_instr(&instr
->instr
, stderr
);
6593 fprintf(stderr
, "\n");
6597 case nir_intrinsic_write_invocation_amd
: {
6598 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6599 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6600 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6601 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6602 if (dst
.regClass() == v1
) {
6603 /* src2 is ignored for writelane. RA assigns the same reg for dst */
6604 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
6605 } else if (dst
.regClass() == v2
) {
6606 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
6607 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
6608 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
6609 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
6610 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
6611 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
6612 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6613 emit_split_vector(ctx
, dst
, 2);
6615 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6616 nir_print_instr(&instr
->instr
, stderr
);
6617 fprintf(stderr
, "\n");
6621 case nir_intrinsic_mbcnt_amd
: {
6622 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6623 RegClass rc
= RegClass(src
.type(), 1);
6624 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
6625 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
6626 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6627 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
6628 emit_wqm(ctx
, wqm_tmp
, dst
);
6631 case nir_intrinsic_load_helper_invocation
: {
6632 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6633 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
6634 ctx
->block
->kind
|= block_kind_needs_lowering
;
6635 ctx
->program
->needs_exact
= true;
6638 case nir_intrinsic_is_helper_invocation
: {
6639 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6640 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
6641 ctx
->block
->kind
|= block_kind_needs_lowering
;
6642 ctx
->program
->needs_exact
= true;
6645 case nir_intrinsic_demote
:
6646 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
6648 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
6649 ctx
->cf_info
.exec_potentially_empty
= true;
6650 ctx
->block
->kind
|= block_kind_uses_demote
;
6651 ctx
->program
->needs_exact
= true;
6653 case nir_intrinsic_demote_if
: {
6654 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6655 assert(src
.regClass() == bld
.lm
);
6656 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6657 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
6659 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
6660 ctx
->cf_info
.exec_potentially_empty
= true;
6661 ctx
->block
->kind
|= block_kind_uses_demote
;
6662 ctx
->program
->needs_exact
= true;
6665 case nir_intrinsic_first_invocation
: {
6666 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
6667 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6670 case nir_intrinsic_shader_clock
:
6671 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
6672 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
6674 case nir_intrinsic_load_vertex_id_zero_base
: {
6675 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6676 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
6679 case nir_intrinsic_load_first_vertex
: {
6680 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6681 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
6684 case nir_intrinsic_load_base_instance
: {
6685 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6686 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
6689 case nir_intrinsic_load_instance_id
: {
6690 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6691 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
6694 case nir_intrinsic_load_draw_id
: {
6695 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6696 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
6699 case nir_intrinsic_load_invocation_id
: {
6700 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
6701 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6702 if (ctx
->options
->chip_class
>= GFX10
)
6703 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
6705 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
6708 case nir_intrinsic_load_primitive_id
: {
6709 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
6710 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6711 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
6714 case nir_intrinsic_emit_vertex_with_counter
: {
6715 visit_emit_vertex_with_counter(ctx
, instr
);
6718 case nir_intrinsic_end_primitive_with_counter
: {
6719 unsigned stream
= nir_intrinsic_stream_id(instr
);
6720 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
6723 case nir_intrinsic_set_vertex_count
: {
6724 /* unused, the HW keeps track of this for us */
6728 fprintf(stderr
, "Unimplemented intrinsic instr: ");
6729 nir_print_instr(&instr
->instr
, stderr
);
6730 fprintf(stderr
, "\n");
6738 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
6739 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
6740 enum glsl_base_type
*stype
)
6742 nir_deref_instr
*texture_deref_instr
= NULL
;
6743 nir_deref_instr
*sampler_deref_instr
= NULL
;
6746 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
6747 switch (instr
->src
[i
].src_type
) {
6748 case nir_tex_src_texture_deref
:
6749 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
6751 case nir_tex_src_sampler_deref
:
6752 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
6754 case nir_tex_src_plane
:
6755 plane
= nir_src_as_int(instr
->src
[i
].src
);
6762 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
6764 if (!sampler_deref_instr
)
6765 sampler_deref_instr
= texture_deref_instr
;
6768 assert(instr
->op
!= nir_texop_txf_ms
&&
6769 instr
->op
!= nir_texop_samples_identical
);
6770 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
6771 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
6772 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
6773 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
6774 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
6775 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
6777 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
6780 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
6782 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
6783 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
6784 Builder
bld(ctx
->program
, ctx
->block
);
6786 /* to avoid unnecessary moves, we split and recombine sampler and image */
6787 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
6788 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
6789 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
6790 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
6791 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
6792 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
6793 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
6794 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
6796 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
6797 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
6798 img
[0], img
[1], img
[2], img
[3],
6799 img
[4], img
[5], img
[6], img
[7]);
6800 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6801 samp
[0], samp
[1], samp
[2], samp
[3]);
6804 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
6805 instr
->op
== nir_texop_samples_identical
))
6806 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
6809 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
6810 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
6812 Builder
bld(ctx
->program
, ctx
->block
);
6814 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
6815 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
6816 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
6818 Operand
neg_one(0xbf800000u
);
6819 Operand
one(0x3f800000u
);
6820 Operand
two(0x40000000u
);
6821 Operand
four(0x40800000u
);
6823 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
6824 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
6825 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
6827 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
6828 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
6829 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
6830 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
6833 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
6834 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
6835 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
6837 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
6840 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
6841 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
6842 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
6845 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
6846 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
6848 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
6849 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
6852 void prepare_cube_coords(isel_context
*ctx
, Temp
* coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
6854 Builder
bld(ctx
->program
, ctx
->block
);
6855 Temp coord_args
[4], ma
, tc
, sc
, id
;
6856 for (unsigned i
= 0; i
< (is_array
? 4 : 3); i
++)
6857 coord_args
[i
] = emit_extract_vector(ctx
, *coords
, i
, v1
);
6860 coord_args
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coord_args
[3]);
6862 // see comment in ac_prepare_cube_coords()
6863 if (ctx
->options
->chip_class
<= GFX8
)
6864 coord_args
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coord_args
[3]);
6867 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6869 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
6870 vop3a
->operands
[0] = Operand(ma
);
6871 vop3a
->abs
[0] = true;
6872 Temp invma
= bld
.tmp(v1
);
6873 vop3a
->definitions
[0] = Definition(invma
);
6874 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
6876 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6878 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
6880 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6882 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
6884 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6887 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
6888 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
6890 for (unsigned i
= 0; i
< 2; i
++) {
6891 // see comment in ac_prepare_cube_coords()
6893 Temp deriv_sc
, deriv_tc
;
6894 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
6895 &deriv_ma
, &deriv_sc
, &deriv_tc
);
6897 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
6899 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
6900 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
6901 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
6902 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
6903 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
6904 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
6905 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
6908 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
6909 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
6913 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coord_args
[3], id
, Operand(0x41000000u
/*8.0*/));
6914 *coords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), sc
, tc
, id
);
6918 Temp
apply_round_slice(isel_context
*ctx
, Temp coords
, unsigned idx
)
6921 for (unsigned i
= 0; i
< coords
.size(); i
++)
6922 coord_vec
[i
] = emit_extract_vector(ctx
, coords
, i
, v1
);
6924 Builder
bld(ctx
->program
, ctx
->block
);
6925 coord_vec
[idx
] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coord_vec
[idx
]);
6927 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
6928 for (unsigned i
= 0; i
< coords
.size(); i
++)
6929 vec
->operands
[i
] = Operand(coord_vec
[i
]);
6930 Temp res
= bld
.tmp(RegType::vgpr
, coords
.size());
6931 vec
->definitions
[0] = Definition(res
);
6932 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6936 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
6938 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
6940 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
6941 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
6944 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
6945 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
6946 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
6950 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
6952 Builder
bld(ctx
->program
, ctx
->block
);
6953 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
6954 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
6955 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), coords
, compare
= Temp(), sample_index
= Temp(),
6956 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(), derivs
= Temp();
6957 nir_const_value
*sample_index_cv
= NULL
;
6958 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
6959 enum glsl_base_type stype
;
6960 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
6962 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
6963 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
6964 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
6965 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
6967 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
6968 switch (instr
->src
[i
].src_type
) {
6969 case nir_tex_src_coord
:
6970 coords
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
));
6972 case nir_tex_src_bias
:
6973 if (instr
->op
== nir_texop_txb
) {
6974 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6978 case nir_tex_src_lod
: {
6979 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
6981 if (val
&& val
->f32
<= 0.0) {
6984 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6989 case nir_tex_src_comparator
:
6990 if (instr
->is_shadow
) {
6991 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6995 case nir_tex_src_offset
:
6996 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6997 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
7000 case nir_tex_src_ddx
:
7001 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7004 case nir_tex_src_ddy
:
7005 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7008 case nir_tex_src_ms_index
:
7009 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
7010 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
7011 has_sample_index
= true;
7013 case nir_tex_src_texture_offset
:
7014 case nir_tex_src_sampler_offset
:
7019 // TODO: all other cases: structure taken from ac_nir_to_llvm.c
7020 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
7021 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
7023 if (instr
->op
== nir_texop_texture_samples
) {
7024 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
7026 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
7027 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
7028 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
7029 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
7031 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7032 samples
, Operand(1u), bld
.scc(is_msaa
));
7036 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
7037 aco_ptr
<Instruction
> tmp_instr
;
7038 Temp acc
, pack
= Temp();
7040 uint32_t pack_const
= 0;
7041 for (unsigned i
= 0; i
< offset
.size(); i
++) {
7042 if (!const_offset
[i
])
7044 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
7047 if (offset
.type() == RegType::sgpr
) {
7048 for (unsigned i
= 0; i
< offset
.size(); i
++) {
7049 if (const_offset
[i
])
7052 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
7053 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
7056 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
7059 if (pack
== Temp()) {
7062 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
7066 if (pack_const
&& pack
!= Temp())
7067 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
7069 for (unsigned i
= 0; i
< offset
.size(); i
++) {
7070 if (const_offset
[i
])
7073 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
7074 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
7077 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
7080 if (pack
== Temp()) {
7083 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
7087 if (pack_const
&& pack
!= Temp())
7088 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
7090 if (pack_const
&& pack
== Temp())
7091 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
7092 else if (pack
== Temp())
7098 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
7099 prepare_cube_coords(ctx
, &coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
7101 /* pack derivatives */
7102 if (has_ddx
|| has_ddy
) {
7103 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
7104 derivs
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v4
),
7105 ddx
, Operand(0u), ddy
, Operand(0u));
7107 derivs
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, ddx
.size() + ddy
.size()), ddx
, ddy
);
7112 if (instr
->coord_components
> 1 &&
7113 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
7115 instr
->op
!= nir_texop_txf
)
7116 coords
= apply_round_slice(ctx
, coords
, 1);
7118 if (instr
->coord_components
> 2 &&
7119 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
7120 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
7121 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
7122 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
7124 instr
->op
!= nir_texop_txf
&&
7125 instr
->op
!= nir_texop_txf_ms
&&
7126 instr
->op
!= nir_texop_fragment_fetch
&&
7127 instr
->op
!= nir_texop_fragment_mask_fetch
)
7128 coords
= apply_round_slice(ctx
, coords
, 2);
7130 if (ctx
->options
->chip_class
== GFX9
&&
7131 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
7132 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
7133 assert(coords
.size() > 0 && coords
.size() < 3);
7135 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size() + 1, 1)};
7136 vec
->operands
[0] = Operand(emit_extract_vector(ctx
, coords
, 0, v1
));
7137 vec
->operands
[1] = instr
->op
== nir_texop_txf
? Operand((uint32_t) 0) : Operand((uint32_t) 0x3f000000);
7138 if (coords
.size() > 1)
7139 vec
->operands
[2] = Operand(emit_extract_vector(ctx
, coords
, 1, v1
));
7140 coords
= bld
.tmp(RegType::vgpr
, coords
.size() + 1);
7141 vec
->definitions
[0] = Definition(coords
);
7142 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7145 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
7147 if (instr
->op
== nir_texop_samples_identical
)
7148 resource
= fmask_ptr
;
7150 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
7151 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
7152 instr
->op
!= nir_texop_txs
&&
7153 instr
->op
!= nir_texop_fragment_fetch
&&
7154 instr
->op
!= nir_texop_fragment_mask_fetch
) {
7155 assert(has_sample_index
);
7156 Operand
op(sample_index
);
7157 if (sample_index_cv
)
7158 op
= Operand(sample_index_cv
->u32
);
7159 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
7162 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
7163 Temp split_coords
[coords
.size()];
7164 emit_split_vector(ctx
, coords
, coords
.size());
7165 for (unsigned i
= 0; i
< coords
.size(); i
++)
7166 split_coords
[i
] = emit_extract_vector(ctx
, coords
, i
, v1
);
7169 for (; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
7170 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
7171 split_coords
[i
] = bld
.vadd32(bld
.def(v1
), split_coords
[i
], off
);
7174 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
7175 for (unsigned i
= 0; i
< coords
.size(); i
++)
7176 vec
->operands
[i
] = Operand(split_coords
[i
]);
7177 coords
= bld
.tmp(coords
.regClass());
7178 vec
->definitions
[0] = Definition(coords
);
7179 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7184 /* Build tex instruction */
7185 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
7186 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
7187 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
7189 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7192 /* gather4 selects the component by dmask and always returns vec4 */
7193 if (instr
->op
== nir_texop_tg4
) {
7194 assert(instr
->dest
.ssa
.num_components
== 4);
7195 if (instr
->is_shadow
)
7198 dmask
= 1 << instr
->component
;
7199 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
7200 tmp_dst
= bld
.tmp(v4
);
7201 } else if (instr
->op
== nir_texop_samples_identical
) {
7202 tmp_dst
= bld
.tmp(v1
);
7203 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
7204 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
7207 aco_ptr
<MIMG_instruction
> tex
;
7208 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
7210 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
7212 bool div_by_6
= instr
->op
== nir_texop_txs
&&
7213 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
7216 if (tmp_dst
.id() == dst
.id() && div_by_6
)
7217 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
7219 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 2, 1));
7220 tex
->operands
[0] = Operand(as_vgpr(ctx
,lod
));
7221 tex
->operands
[1] = Operand(resource
);
7222 if (ctx
->options
->chip_class
== GFX9
&&
7223 instr
->op
== nir_texop_txs
&&
7224 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
7226 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
7227 } else if (instr
->op
== nir_texop_query_levels
) {
7228 tex
->dmask
= 1 << 3;
7233 tex
->definitions
[0] = Definition(tmp_dst
);
7235 tex
->can_reorder
= true;
7236 ctx
->block
->instructions
.emplace_back(std::move(tex
));
7239 /* divide 3rd value by 6 by multiplying with magic number */
7240 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
7241 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
7242 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
7243 assert(instr
->dest
.ssa
.num_components
== 3);
7244 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
7245 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
7246 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
7247 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
7252 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
7256 Temp tg4_compare_cube_wa64
= Temp();
7258 if (tg4_integer_workarounds
) {
7259 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 2, 1));
7260 tex
->operands
[0] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
7261 tex
->operands
[1] = Operand(resource
);
7265 Temp size
= bld
.tmp(v2
);
7266 tex
->definitions
[0] = Definition(size
);
7267 tex
->can_reorder
= true;
7268 ctx
->block
->instructions
.emplace_back(std::move(tex
));
7269 emit_split_vector(ctx
, size
, size
.size());
7272 for (unsigned i
= 0; i
< 2; i
++) {
7273 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
7274 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
7275 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
7276 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
7279 Temp orig_coords
[2] = {
7280 emit_extract_vector(ctx
, coords
, 0, v1
),
7281 emit_extract_vector(ctx
, coords
, 1, v1
)};
7282 Temp new_coords
[2] = {
7283 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), orig_coords
[0], half_texel
[0]),
7284 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), orig_coords
[1], half_texel
[1])
7287 if (tg4_integer_cube_workaround
) {
7288 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
7289 Temp desc
[resource
.size()];
7290 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
7291 Format::PSEUDO
, 1, resource
.size())};
7292 split
->operands
[0] = Operand(resource
);
7293 for (unsigned i
= 0; i
< resource
.size(); i
++) {
7294 desc
[i
] = bld
.tmp(s1
);
7295 split
->definitions
[i
] = Definition(desc
[i
]);
7297 ctx
->block
->instructions
.emplace_back(std::move(split
));
7299 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
7300 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
7301 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
7304 if (stype
== GLSL_TYPE_UINT
) {
7305 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
7306 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
7307 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
7308 bld
.scc(compare_cube_wa
));
7310 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
7311 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
7312 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
7313 bld
.scc(compare_cube_wa
));
7315 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
7316 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
7318 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
7320 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
7321 Operand((uint32_t)C_008F14_NUM_FORMAT
));
7322 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
7324 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
7325 Format::PSEUDO
, resource
.size(), 1)};
7326 for (unsigned i
= 0; i
< resource
.size(); i
++)
7327 vec
->operands
[i
] = Operand(desc
[i
]);
7328 resource
= bld
.tmp(resource
.regClass());
7329 vec
->definitions
[0] = Definition(resource
);
7330 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7332 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7333 new_coords
[0], orig_coords
[0], tg4_compare_cube_wa64
);
7334 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7335 new_coords
[1], orig_coords
[1], tg4_compare_cube_wa64
);
7338 if (coords
.size() == 3) {
7339 coords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
),
7340 new_coords
[0], new_coords
[1],
7341 emit_extract_vector(ctx
, coords
, 2, v1
));
7343 assert(coords
.size() == 2);
7344 coords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
),
7345 new_coords
[0], new_coords
[1]);
7349 std::vector
<Operand
> args
;
7351 args
.emplace_back(Operand(offset
));
7353 args
.emplace_back(Operand(bias
));
7355 args
.emplace_back(Operand(compare
));
7357 args
.emplace_back(Operand(derivs
));
7358 args
.emplace_back(Operand(coords
));
7359 if (has_sample_index
)
7360 args
.emplace_back(Operand(sample_index
));
7362 args
.emplace_back(lod
);
7365 if (args
.size() > 1) {
7366 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
7368 for (unsigned i
= 0; i
< args
.size(); i
++) {
7369 size
+= args
[i
].size();
7370 vec
->operands
[i
] = args
[i
];
7372 RegClass rc
= RegClass(RegType::vgpr
, size
);
7373 Temp tmp
= bld
.tmp(rc
);
7374 vec
->definitions
[0] = Definition(tmp
);
7375 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7378 assert(args
[0].isTemp());
7379 arg
= as_vgpr(ctx
, args
[0].getTemp());
7382 /* we don't need the bias, sample index, compare value or offset to be
7383 * computed in WQM but if the p_create_vector copies the coordinates, then it
7384 * needs to be in WQM */
7385 if (!(has_ddx
&& has_ddy
) && !has_lod
&& !level_zero
&&
7386 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
7387 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
7388 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
7390 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
7391 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
7393 assert(coords
.size() == 1);
7394 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
7398 op
= aco_opcode::buffer_load_format_x
; break;
7400 op
= aco_opcode::buffer_load_format_xy
; break;
7402 op
= aco_opcode::buffer_load_format_xyz
; break;
7404 op
= aco_opcode::buffer_load_format_xyzw
; break;
7406 unreachable("Tex instruction loads more than 4 components.");
7409 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
7410 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
7413 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
7415 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
7416 mubuf
->operands
[0] = Operand(coords
);
7417 mubuf
->operands
[1] = Operand(resource
);
7418 mubuf
->operands
[2] = Operand((uint32_t) 0);
7419 mubuf
->definitions
[0] = Definition(tmp_dst
);
7420 mubuf
->idxen
= true;
7421 mubuf
->can_reorder
= true;
7422 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
7424 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
7429 if (instr
->op
== nir_texop_txf
||
7430 instr
->op
== nir_texop_txf_ms
||
7431 instr
->op
== nir_texop_samples_identical
||
7432 instr
->op
== nir_texop_fragment_fetch
||
7433 instr
->op
== nir_texop_fragment_mask_fetch
) {
7434 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
7435 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 2, 1));
7436 tex
->operands
[0] = Operand(arg
);
7437 tex
->operands
[1] = Operand(resource
);
7442 tex
->definitions
[0] = Definition(tmp_dst
);
7443 tex
->can_reorder
= true;
7444 ctx
->block
->instructions
.emplace_back(std::move(tex
));
7446 if (instr
->op
== nir_texop_samples_identical
) {
7447 assert(dmask
== 1 && dst
.regClass() == v1
);
7448 assert(dst
.id() != tmp_dst
.id());
7450 Temp tmp
= bld
.tmp(bld
.lm
);
7451 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
7452 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
7455 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
7460 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
7461 aco_opcode opcode
= aco_opcode::image_sample
;
7462 if (has_offset
) { /* image_sample_*_o */
7464 opcode
= aco_opcode::image_sample_c_o
;
7466 opcode
= aco_opcode::image_sample_c_d_o
;
7468 opcode
= aco_opcode::image_sample_c_b_o
;
7470 opcode
= aco_opcode::image_sample_c_lz_o
;
7472 opcode
= aco_opcode::image_sample_c_l_o
;
7474 opcode
= aco_opcode::image_sample_o
;
7476 opcode
= aco_opcode::image_sample_d_o
;
7478 opcode
= aco_opcode::image_sample_b_o
;
7480 opcode
= aco_opcode::image_sample_lz_o
;
7482 opcode
= aco_opcode::image_sample_l_o
;
7484 } else { /* no offset */
7486 opcode
= aco_opcode::image_sample_c
;
7488 opcode
= aco_opcode::image_sample_c_d
;
7490 opcode
= aco_opcode::image_sample_c_b
;
7492 opcode
= aco_opcode::image_sample_c_lz
;
7494 opcode
= aco_opcode::image_sample_c_l
;
7496 opcode
= aco_opcode::image_sample
;
7498 opcode
= aco_opcode::image_sample_d
;
7500 opcode
= aco_opcode::image_sample_b
;
7502 opcode
= aco_opcode::image_sample_lz
;
7504 opcode
= aco_opcode::image_sample_l
;
7508 if (instr
->op
== nir_texop_tg4
) {
7510 opcode
= aco_opcode::image_gather4_lz_o
;
7512 opcode
= aco_opcode::image_gather4_c_lz_o
;
7514 opcode
= aco_opcode::image_gather4_lz
;
7516 opcode
= aco_opcode::image_gather4_c_lz
;
7518 } else if (instr
->op
== nir_texop_lod
) {
7519 opcode
= aco_opcode::image_get_lod
;
7522 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
7523 tex
->operands
[0] = Operand(arg
);
7524 tex
->operands
[1] = Operand(resource
);
7525 tex
->operands
[2] = Operand(sampler
);
7529 tex
->definitions
[0] = Definition(tmp_dst
);
7530 tex
->can_reorder
= true;
7531 ctx
->block
->instructions
.emplace_back(std::move(tex
));
7533 if (tg4_integer_cube_workaround
) {
7534 assert(tmp_dst
.id() != dst
.id());
7535 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
7537 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
7539 for (unsigned i
= 0; i
< dst
.size(); i
++) {
7540 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
7542 if (stype
== GLSL_TYPE_UINT
)
7543 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
7545 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
7546 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
7548 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
7549 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
7550 val
[0], val
[1], val
[2], val
[3]);
7552 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
7553 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
7558 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
7560 Temp tmp
= get_ssa_temp(ctx
, ssa
);
7561 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
7562 return Operand(tmp
.regClass());
7564 return Operand(tmp
);
7567 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
7569 aco_ptr
<Pseudo_instruction
> phi
;
7570 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7571 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
7573 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
7574 logical
|= ctx
->block
->kind
& block_kind_merge
;
7575 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
7577 /* we want a sorted list of sources, since the predecessor list is also sorted */
7578 std::map
<unsigned, nir_ssa_def
*> phi_src
;
7579 nir_foreach_phi_src(src
, instr
)
7580 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
7582 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
7583 unsigned num_operands
= 0;
7584 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size())];
7585 unsigned num_defined
= 0;
7586 unsigned cur_pred_idx
= 0;
7587 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
7588 if (cur_pred_idx
< preds
.size()) {
7589 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
7590 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
7591 unsigned skipped
= 0;
7592 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
7594 if (cur_pred_idx
+ skipped
< preds
.size()) {
7595 for (unsigned i
= 0; i
< skipped
; i
++)
7596 operands
[num_operands
++] = Operand(dst
.regClass());
7597 cur_pred_idx
+= skipped
;
7603 Operand op
= get_phi_operand(ctx
, src
.second
);
7604 operands
[num_operands
++] = op
;
7605 num_defined
+= !op
.isUndefined();
7607 /* handle block_kind_continue_or_break at loop exit blocks */
7608 while (cur_pred_idx
++ < preds
.size())
7609 operands
[num_operands
++] = Operand(dst
.regClass());
7611 if (num_defined
== 0) {
7612 Builder
bld(ctx
->program
, ctx
->block
);
7613 if (dst
.regClass() == s1
) {
7614 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
7615 } else if (dst
.regClass() == v1
) {
7616 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
7618 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
7619 for (unsigned i
= 0; i
< dst
.size(); i
++)
7620 vec
->operands
[i
] = Operand(0u);
7621 vec
->definitions
[0] = Definition(dst
);
7622 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7627 /* we can use a linear phi in some cases if one src is undef */
7628 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
7629 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
7631 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
7632 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
7633 assert(invert
->kind
& block_kind_invert
);
7635 unsigned then_block
= invert
->linear_preds
[0];
7637 Block
* insert_block
= NULL
;
7638 for (unsigned i
= 0; i
< num_operands
; i
++) {
7639 Operand op
= operands
[i
];
7640 if (op
.isUndefined())
7642 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
7643 phi
->operands
[0] = op
;
7646 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
7647 phi
->operands
[1] = Operand(dst
.regClass());
7648 phi
->definitions
[0] = Definition(dst
);
7649 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
7653 /* try to scalarize vector phis */
7654 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
7655 // TODO: scalarize linear phis on divergent ifs
7656 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
7657 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
7658 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
7659 Operand src
= operands
[i
];
7660 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
7661 can_scalarize
= false;
7663 if (can_scalarize
) {
7664 unsigned num_components
= instr
->dest
.ssa
.num_components
;
7665 assert(dst
.size() % num_components
== 0);
7666 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
7668 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
7669 for (unsigned k
= 0; k
< num_components
; k
++) {
7670 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
7671 for (unsigned i
= 0; i
< num_operands
; i
++) {
7672 Operand src
= operands
[i
];
7673 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
7675 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
7676 phi
->definitions
[0] = Definition(phi_dst
);
7677 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
7678 new_vec
[k
] = phi_dst
;
7679 vec
->operands
[k
] = Operand(phi_dst
);
7681 vec
->definitions
[0] = Definition(dst
);
7682 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7683 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
7688 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
7689 for (unsigned i
= 0; i
< num_operands
; i
++)
7690 phi
->operands
[i
] = operands
[i
];
7691 phi
->definitions
[0] = Definition(dst
);
7692 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
7696 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
7698 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
7700 assert(dst
.type() == RegType::sgpr
);
7702 if (dst
.size() == 1) {
7703 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
7705 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
7706 for (unsigned i
= 0; i
< dst
.size(); i
++)
7707 vec
->operands
[i
] = Operand(0u);
7708 vec
->definitions
[0] = Definition(dst
);
7709 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7713 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
7715 Builder
bld(ctx
->program
, ctx
->block
);
7716 Block
*logical_target
;
7717 append_logical_end(ctx
->block
);
7718 unsigned idx
= ctx
->block
->index
;
7720 switch (instr
->type
) {
7721 case nir_jump_break
:
7722 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
7723 add_logical_edge(idx
, logical_target
);
7724 ctx
->block
->kind
|= block_kind_break
;
7726 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
7727 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
7728 /* uniform break - directly jump out of the loop */
7729 ctx
->block
->kind
|= block_kind_uniform
;
7730 ctx
->cf_info
.has_branch
= true;
7731 bld
.branch(aco_opcode::p_branch
);
7732 add_linear_edge(idx
, logical_target
);
7735 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
7736 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
7738 case nir_jump_continue
:
7739 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
7740 add_logical_edge(idx
, logical_target
);
7741 ctx
->block
->kind
|= block_kind_continue
;
7743 if (ctx
->cf_info
.parent_if
.is_divergent
) {
7744 /* for potential uniform breaks after this continue,
7745 we must ensure that they are handled correctly */
7746 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
7747 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
7748 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
7750 /* uniform continue - directly jump to the loop header */
7751 ctx
->block
->kind
|= block_kind_uniform
;
7752 ctx
->cf_info
.has_branch
= true;
7753 bld
.branch(aco_opcode::p_branch
);
7754 add_linear_edge(idx
, logical_target
);
7759 fprintf(stderr
, "Unknown NIR jump instr: ");
7760 nir_print_instr(&instr
->instr
, stderr
);
7761 fprintf(stderr
, "\n");
7765 /* remove critical edges from linear CFG */
7766 bld
.branch(aco_opcode::p_branch
);
7767 Block
* break_block
= ctx
->program
->create_and_insert_block();
7768 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7769 break_block
->kind
|= block_kind_uniform
;
7770 add_linear_edge(idx
, break_block
);
7771 /* the loop_header pointer might be invalidated by this point */
7772 if (instr
->type
== nir_jump_continue
)
7773 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
7774 add_linear_edge(break_block
->index
, logical_target
);
7775 bld
.reset(break_block
);
7776 bld
.branch(aco_opcode::p_branch
);
7778 Block
* continue_block
= ctx
->program
->create_and_insert_block();
7779 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7780 add_linear_edge(idx
, continue_block
);
7781 append_logical_start(continue_block
);
7782 ctx
->block
= continue_block
;
7786 void visit_block(isel_context
*ctx
, nir_block
*block
)
7788 nir_foreach_instr(instr
, block
) {
7789 switch (instr
->type
) {
7790 case nir_instr_type_alu
:
7791 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
7793 case nir_instr_type_load_const
:
7794 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
7796 case nir_instr_type_intrinsic
:
7797 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
7799 case nir_instr_type_tex
:
7800 visit_tex(ctx
, nir_instr_as_tex(instr
));
7802 case nir_instr_type_phi
:
7803 visit_phi(ctx
, nir_instr_as_phi(instr
));
7805 case nir_instr_type_ssa_undef
:
7806 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
7808 case nir_instr_type_deref
:
7810 case nir_instr_type_jump
:
7811 visit_jump(ctx
, nir_instr_as_jump(instr
));
7814 fprintf(stderr
, "Unknown NIR instr type: ");
7815 nir_print_instr(instr
, stderr
);
7816 fprintf(stderr
, "\n");
7821 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7822 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
7827 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
7829 append_logical_end(ctx
->block
);
7830 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
7831 Builder
bld(ctx
->program
, ctx
->block
);
7832 bld
.branch(aco_opcode::p_branch
);
7833 unsigned loop_preheader_idx
= ctx
->block
->index
;
7835 Block loop_exit
= Block();
7836 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7837 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
7839 Block
* loop_header
= ctx
->program
->create_and_insert_block();
7840 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
7841 loop_header
->kind
|= block_kind_loop_header
;
7842 add_edge(loop_preheader_idx
, loop_header
);
7843 ctx
->block
= loop_header
;
7845 /* emit loop body */
7846 unsigned loop_header_idx
= loop_header
->index
;
7847 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
7848 append_logical_start(ctx
->block
);
7849 visit_cf_list(ctx
, &loop
->body
);
7851 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
7852 if (!ctx
->cf_info
.has_branch
) {
7853 append_logical_end(ctx
->block
);
7854 if (ctx
->cf_info
.exec_potentially_empty
) {
7855 /* Discards can result in code running with an empty exec mask.
7856 * This would result in divergent breaks not ever being taken. As a
7857 * workaround, break the loop when the loop mask is empty instead of
7858 * always continuing. */
7859 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
7860 unsigned block_idx
= ctx
->block
->index
;
7862 /* create helper blocks to avoid critical edges */
7863 Block
*break_block
= ctx
->program
->create_and_insert_block();
7864 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7865 break_block
->kind
= block_kind_uniform
;
7866 bld
.reset(break_block
);
7867 bld
.branch(aco_opcode::p_branch
);
7868 add_linear_edge(block_idx
, break_block
);
7869 add_linear_edge(break_block
->index
, &loop_exit
);
7871 Block
*continue_block
= ctx
->program
->create_and_insert_block();
7872 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7873 continue_block
->kind
= block_kind_uniform
;
7874 bld
.reset(continue_block
);
7875 bld
.branch(aco_opcode::p_branch
);
7876 add_linear_edge(block_idx
, continue_block
);
7877 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
7879 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
7880 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
7882 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
7883 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7884 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
7886 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
7889 bld
.reset(ctx
->block
);
7890 bld
.branch(aco_opcode::p_branch
);
7893 /* fixup phis in loop header from unreachable blocks */
7894 if (ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
) {
7895 bool linear
= ctx
->cf_info
.has_branch
;
7896 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
7897 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
7898 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
7899 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
7900 /* the last operand should be the one that needs to be removed */
7901 instr
->operands
.pop_back();
7902 } else if (!is_phi(instr
)) {
7908 ctx
->cf_info
.has_branch
= false;
7910 // TODO: if the loop has not a single exit, we must add one °°
7911 /* emit loop successor block */
7912 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
7913 append_logical_start(ctx
->block
);
7916 // TODO: check if it is beneficial to not branch on continues
7917 /* trim linear phis in loop header */
7918 for (auto&& instr
: loop_entry
->instructions
) {
7919 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
7920 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
7921 new_phi
->definitions
[0] = instr
->definitions
[0];
7922 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
7923 new_phi
->operands
[i
] = instr
->operands
[i
];
7924 /* check that the remaining operands are all the same */
7925 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
7926 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
7927 instr
.swap(new_phi
);
7928 } else if (instr
->opcode
== aco_opcode::p_phi
) {
7937 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
7941 append_logical_end(ctx
->block
);
7942 ctx
->block
->kind
|= block_kind_branch
;
7944 /* branch to linear then block */
7945 assert(cond
.regClass() == ctx
->program
->lane_mask
);
7946 aco_ptr
<Pseudo_branch_instruction
> branch
;
7947 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
7948 branch
->operands
[0] = Operand(cond
);
7949 ctx
->block
->instructions
.push_back(std::move(branch
));
7951 ic
->BB_if_idx
= ctx
->block
->index
;
7952 ic
->BB_invert
= Block();
7953 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7954 /* Invert blocks are intentionally not marked as top level because they
7955 * are not part of the logical cfg. */
7956 ic
->BB_invert
.kind
|= block_kind_invert
;
7957 ic
->BB_endif
= Block();
7958 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7959 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
7961 ic
->exec_potentially_empty_old
= ctx
->cf_info
.exec_potentially_empty
;
7962 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
7963 ctx
->cf_info
.parent_if
.is_divergent
= true;
7964 ctx
->cf_info
.exec_potentially_empty
= false; /* divergent branches use cbranch_execz */
7966 /** emit logical then block */
7967 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
7968 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7969 add_edge(ic
->BB_if_idx
, BB_then_logical
);
7970 ctx
->block
= BB_then_logical
;
7971 append_logical_start(BB_then_logical
);
7974 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
7976 Block
*BB_then_logical
= ctx
->block
;
7977 append_logical_end(BB_then_logical
);
7978 /* branch from logical then block to invert block */
7979 aco_ptr
<Pseudo_branch_instruction
> branch
;
7980 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7981 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
7982 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
7983 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7984 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
7985 BB_then_logical
->kind
|= block_kind_uniform
;
7986 assert(!ctx
->cf_info
.has_branch
);
7987 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
7988 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
7990 /** emit linear then block */
7991 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
7992 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7993 BB_then_linear
->kind
|= block_kind_uniform
;
7994 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
7995 /* branch from linear then block to invert block */
7996 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7997 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
7998 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
8000 /** emit invert merge block */
8001 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
8002 ic
->invert_idx
= ctx
->block
->index
;
8004 /* branch to linear else block (skip else) */
8005 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
8006 branch
->operands
[0] = Operand(ic
->cond
);
8007 ctx
->block
->instructions
.push_back(std::move(branch
));
8009 ic
->exec_potentially_empty_old
|= ctx
->cf_info
.exec_potentially_empty
;
8010 ctx
->cf_info
.exec_potentially_empty
= false; /* divergent branches use cbranch_execz */
8012 /** emit logical else block */
8013 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
8014 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8015 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
8016 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
8017 ctx
->block
= BB_else_logical
;
8018 append_logical_start(BB_else_logical
);
8021 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
8023 Block
*BB_else_logical
= ctx
->block
;
8024 append_logical_end(BB_else_logical
);
8026 /* branch from logical else block to endif block */
8027 aco_ptr
<Pseudo_branch_instruction
> branch
;
8028 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
8029 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
8030 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
8031 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8032 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
8033 BB_else_logical
->kind
|= block_kind_uniform
;
8035 assert(!ctx
->cf_info
.has_branch
);
8036 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
8039 /** emit linear else block */
8040 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
8041 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8042 BB_else_linear
->kind
|= block_kind_uniform
;
8043 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
8045 /* branch from linear else block to endif block */
8046 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
8047 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
8048 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
8051 /** emit endif merge block */
8052 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
8053 append_logical_start(ctx
->block
);
8056 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
8057 ctx
->cf_info
.exec_potentially_empty
|= ic
->exec_potentially_empty_old
;
8058 /* uniform control flow never has an empty exec-mask */
8059 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
8060 ctx
->cf_info
.exec_potentially_empty
= false;
8063 static void visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
8065 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
8066 Builder
bld(ctx
->program
, ctx
->block
);
8067 aco_ptr
<Pseudo_branch_instruction
> branch
;
8069 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
8071 * Uniform conditionals are represented in the following way*) :
8073 * The linear and logical CFG:
8076 * BB_THEN (logical) BB_ELSE (logical)
8080 * *) Exceptions may be due to break and continue statements within loops
8081 * If a break/continue happens within uniform control flow, it branches
8082 * to the loop exit/entry block. Otherwise, it branches to the next
8085 append_logical_end(ctx
->block
);
8086 ctx
->block
->kind
|= block_kind_uniform
;
8089 assert(cond
.regClass() == bld
.lm
);
8090 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
8091 cond
= bool_to_scalar_condition(ctx
, cond
);
8093 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
8094 branch
->operands
[0] = Operand(cond
);
8095 branch
->operands
[0].setFixed(scc
);
8096 ctx
->block
->instructions
.emplace_back(std::move(branch
));
8098 unsigned BB_if_idx
= ctx
->block
->index
;
8099 Block BB_endif
= Block();
8100 BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8101 BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
8103 /** emit then block */
8104 Block
* BB_then
= ctx
->program
->create_and_insert_block();
8105 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8106 add_edge(BB_if_idx
, BB_then
);
8107 append_logical_start(BB_then
);
8108 ctx
->block
= BB_then
;
8109 visit_cf_list(ctx
, &if_stmt
->then_list
);
8110 BB_then
= ctx
->block
;
8111 bool then_branch
= ctx
->cf_info
.has_branch
;
8112 bool then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
8115 append_logical_end(BB_then
);
8116 /* branch from then block to endif block */
8117 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
8118 BB_then
->instructions
.emplace_back(std::move(branch
));
8119 add_linear_edge(BB_then
->index
, &BB_endif
);
8120 if (!then_branch_divergent
)
8121 add_logical_edge(BB_then
->index
, &BB_endif
);
8122 BB_then
->kind
|= block_kind_uniform
;
8125 ctx
->cf_info
.has_branch
= false;
8126 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
8128 /** emit else block */
8129 Block
* BB_else
= ctx
->program
->create_and_insert_block();
8130 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8131 add_edge(BB_if_idx
, BB_else
);
8132 append_logical_start(BB_else
);
8133 ctx
->block
= BB_else
;
8134 visit_cf_list(ctx
, &if_stmt
->else_list
);
8135 BB_else
= ctx
->block
;
8137 if (!ctx
->cf_info
.has_branch
) {
8138 append_logical_end(BB_else
);
8139 /* branch from then block to endif block */
8140 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
8141 BB_else
->instructions
.emplace_back(std::move(branch
));
8142 add_linear_edge(BB_else
->index
, &BB_endif
);
8143 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8144 add_logical_edge(BB_else
->index
, &BB_endif
);
8145 BB_else
->kind
|= block_kind_uniform
;
8148 ctx
->cf_info
.has_branch
&= then_branch
;
8149 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= then_branch_divergent
;
8151 /** emit endif merge block */
8152 if (!ctx
->cf_info
.has_branch
) {
8153 ctx
->block
= ctx
->program
->insert_block(std::move(BB_endif
));
8154 append_logical_start(ctx
->block
);
8156 } else { /* non-uniform condition */
8158 * To maintain a logical and linear CFG without critical edges,
8159 * non-uniform conditionals are represented in the following way*) :
8164 * BB_THEN (logical) BB_THEN (linear)
8166 * BB_INVERT (linear)
8168 * BB_ELSE (logical) BB_ELSE (linear)
8175 * BB_THEN (logical) BB_ELSE (logical)
8179 * *) Exceptions may be due to break and continue statements within loops
8184 begin_divergent_if_then(ctx
, &ic
, cond
);
8185 visit_cf_list(ctx
, &if_stmt
->then_list
);
8187 begin_divergent_if_else(ctx
, &ic
);
8188 visit_cf_list(ctx
, &if_stmt
->else_list
);
8190 end_divergent_if(ctx
, &ic
);
8194 static void visit_cf_list(isel_context
*ctx
,
8195 struct exec_list
*list
)
8197 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
8198 switch (node
->type
) {
8199 case nir_cf_node_block
:
8200 visit_block(ctx
, nir_cf_node_as_block(node
));
8202 case nir_cf_node_if
:
8203 visit_if(ctx
, nir_cf_node_as_if(node
));
8205 case nir_cf_node_loop
:
8206 visit_loop(ctx
, nir_cf_node_as_loop(node
));
8209 unreachable("unimplemented cf list type");
8214 static void export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
8216 int offset
= ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
8217 uint64_t mask
= ctx
->outputs
.mask
[slot
];
8218 if (!is_pos
&& !mask
)
8220 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
8222 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
8223 exp
->enabled_mask
= mask
;
8224 for (unsigned i
= 0; i
< 4; ++i
) {
8225 if (mask
& (1 << i
))
8226 exp
->operands
[i
] = Operand(ctx
->outputs
.outputs
[slot
][i
]);
8228 exp
->operands
[i
] = Operand(v1
);
8230 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
8231 * Setting valid_mask=1 prevents it and has no other effect.
8233 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
8235 exp
->compressed
= false;
8237 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
8239 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
8240 ctx
->block
->instructions
.emplace_back(std::move(exp
));
8243 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
8245 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
8246 exp
->enabled_mask
= 0;
8247 for (unsigned i
= 0; i
< 4; ++i
)
8248 exp
->operands
[i
] = Operand(v1
);
8249 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
8250 exp
->operands
[0] = Operand(ctx
->outputs
.outputs
[VARYING_SLOT_PSIZ
][0]);
8251 exp
->enabled_mask
|= 0x1;
8253 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
8254 exp
->operands
[2] = Operand(ctx
->outputs
.outputs
[VARYING_SLOT_LAYER
][0]);
8255 exp
->enabled_mask
|= 0x4;
8257 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
8258 if (ctx
->options
->chip_class
< GFX9
) {
8259 exp
->operands
[3] = Operand(ctx
->outputs
.outputs
[VARYING_SLOT_VIEWPORT
][0]);
8260 exp
->enabled_mask
|= 0x8;
8262 Builder
bld(ctx
->program
, ctx
->block
);
8264 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
8265 Operand(ctx
->outputs
.outputs
[VARYING_SLOT_VIEWPORT
][0]));
8266 if (exp
->operands
[2].isTemp())
8267 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
8269 exp
->operands
[2] = Operand(out
);
8270 exp
->enabled_mask
|= 0x4;
8273 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
8275 exp
->compressed
= false;
8276 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
8277 ctx
->block
->instructions
.emplace_back(std::move(exp
));
8280 static void create_vs_exports(isel_context
*ctx
)
8282 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->vs
.outinfo
;
8284 if (outinfo
->export_prim_id
) {
8285 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
8286 ctx
->outputs
.outputs
[VARYING_SLOT_PRIMITIVE_ID
][0] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
8289 if (ctx
->options
->key
.has_multiview_view_index
) {
8290 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
8291 ctx
->outputs
.outputs
[VARYING_SLOT_LAYER
][0] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
8294 /* the order these position exports are created is important */
8296 export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
8297 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
8298 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
8300 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
8301 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
8302 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
8303 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
8305 if (ctx
->export_clip_dists
) {
8306 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
8307 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
8308 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
8309 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
8312 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
8313 if (i
< VARYING_SLOT_VAR0
&& i
!= VARYING_SLOT_LAYER
&&
8314 i
!= VARYING_SLOT_PRIMITIVE_ID
)
8317 export_vs_varying(ctx
, i
, false, NULL
);
8321 static void export_fs_mrt_z(isel_context
*ctx
)
8323 Builder
bld(ctx
->program
, ctx
->block
);
8324 unsigned enabled_channels
= 0;
8328 for (unsigned i
= 0; i
< 4; ++i
) {
8329 values
[i
] = Operand(v1
);
8332 /* Both stencil and sample mask only need 16-bits. */
8333 if (!ctx
->program
->info
->ps
.writes_z
&&
8334 (ctx
->program
->info
->ps
.writes_stencil
||
8335 ctx
->program
->info
->ps
.writes_sample_mask
)) {
8336 compr
= true; /* COMPR flag */
8338 if (ctx
->program
->info
->ps
.writes_stencil
) {
8339 /* Stencil should be in X[23:16]. */
8340 values
[0] = Operand(ctx
->outputs
.outputs
[FRAG_RESULT_STENCIL
][0]);
8341 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
8342 enabled_channels
|= 0x3;
8345 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
8346 /* SampleMask should be in Y[15:0]. */
8347 values
[1] = Operand(ctx
->outputs
.outputs
[FRAG_RESULT_SAMPLE_MASK
][0]);
8348 enabled_channels
|= 0xc;
8351 if (ctx
->program
->info
->ps
.writes_z
) {
8352 values
[0] = Operand(ctx
->outputs
.outputs
[FRAG_RESULT_DEPTH
][0]);
8353 enabled_channels
|= 0x1;
8356 if (ctx
->program
->info
->ps
.writes_stencil
) {
8357 values
[1] = Operand(ctx
->outputs
.outputs
[FRAG_RESULT_STENCIL
][0]);
8358 enabled_channels
|= 0x2;
8361 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
8362 values
[2] = Operand(ctx
->outputs
.outputs
[FRAG_RESULT_SAMPLE_MASK
][0]);
8363 enabled_channels
|= 0x4;
8367 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
8368 * writemask component.
8370 if (ctx
->options
->chip_class
== GFX6
&&
8371 ctx
->options
->family
!= CHIP_OLAND
&&
8372 ctx
->options
->family
!= CHIP_HAINAN
) {
8373 enabled_channels
|= 0x1;
8376 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
8377 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
8380 static void export_fs_mrt_color(isel_context
*ctx
, int slot
)
8382 Builder
bld(ctx
->program
, ctx
->block
);
8383 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
8386 for (unsigned i
= 0; i
< 4; ++i
) {
8387 if (write_mask
& (1 << i
)) {
8388 values
[i
] = Operand(ctx
->outputs
.outputs
[slot
][i
]);
8390 values
[i
] = Operand(v1
);
8394 unsigned target
, col_format
;
8395 unsigned enabled_channels
= 0;
8396 aco_opcode compr_op
= (aco_opcode
)0;
8398 slot
-= FRAG_RESULT_DATA0
;
8399 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
8400 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
8402 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
8403 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
8407 case V_028714_SPI_SHADER_ZERO
:
8408 enabled_channels
= 0; /* writemask */
8409 target
= V_008DFC_SQ_EXP_NULL
;
8412 case V_028714_SPI_SHADER_32_R
:
8413 enabled_channels
= 1;
8416 case V_028714_SPI_SHADER_32_GR
:
8417 enabled_channels
= 0x3;
8420 case V_028714_SPI_SHADER_32_AR
:
8421 if (ctx
->options
->chip_class
>= GFX10
) {
8422 /* Special case: on GFX10, the outputs are different for 32_AR */
8423 enabled_channels
= 0x3;
8424 values
[1] = values
[3];
8425 values
[3] = Operand(v1
);
8427 enabled_channels
= 0x9;
8431 case V_028714_SPI_SHADER_FP16_ABGR
:
8432 enabled_channels
= 0x5;
8433 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
8436 case V_028714_SPI_SHADER_UNORM16_ABGR
:
8437 enabled_channels
= 0x5;
8438 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
8441 case V_028714_SPI_SHADER_SNORM16_ABGR
:
8442 enabled_channels
= 0x5;
8443 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
8446 case V_028714_SPI_SHADER_UINT16_ABGR
: {
8447 enabled_channels
= 0x5;
8448 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
8449 if (is_int8
|| is_int10
) {
8451 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
8452 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
8454 for (unsigned i
= 0; i
< 4; i
++) {
8455 if ((write_mask
>> i
) & 1) {
8456 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
8457 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
8465 case V_028714_SPI_SHADER_SINT16_ABGR
:
8466 enabled_channels
= 0x5;
8467 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
8468 if (is_int8
|| is_int10
) {
8470 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
8471 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
8472 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
8473 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
8475 for (unsigned i
= 0; i
< 4; i
++) {
8476 if ((write_mask
>> i
) & 1) {
8477 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
8478 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
8480 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
8481 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
8488 case V_028714_SPI_SHADER_32_ABGR
:
8489 enabled_channels
= 0xF;
8496 if (target
== V_008DFC_SQ_EXP_NULL
)
8499 if ((bool) compr_op
) {
8500 for (int i
= 0; i
< 2; i
++) {
8501 /* check if at least one of the values to be compressed is enabled */
8502 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
8504 enabled_channels
|= enabled
<< (i
*2);
8505 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
8506 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
8507 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
8509 values
[i
] = Operand(v1
);
8512 values
[2] = Operand(v1
);
8513 values
[3] = Operand(v1
);
8515 for (int i
= 0; i
< 4; i
++)
8516 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
8519 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
8520 enabled_channels
, target
, (bool) compr_op
);
8523 static void create_fs_exports(isel_context
*ctx
)
8525 /* Export depth, stencil and sample mask. */
8526 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
8527 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
8528 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
]) {
8529 export_fs_mrt_z(ctx
);
8532 /* Export all color render targets. */
8533 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
) {
8534 if (ctx
->outputs
.mask
[i
])
8535 export_fs_mrt_color(ctx
, i
);
8539 static void emit_stream_output(isel_context
*ctx
,
8540 Temp
const *so_buffers
,
8541 Temp
const *so_write_offset
,
8542 const struct radv_stream_output
*output
)
8544 unsigned num_comps
= util_bitcount(output
->component_mask
);
8545 unsigned writemask
= (1 << num_comps
) - 1;
8546 unsigned loc
= output
->location
;
8547 unsigned buf
= output
->buffer
;
8549 assert(num_comps
&& num_comps
<= 4);
8550 if (!num_comps
|| num_comps
> 4)
8553 unsigned start
= ffs(output
->component_mask
) - 1;
8556 bool all_undef
= true;
8557 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
8558 for (unsigned i
= 0; i
< num_comps
; i
++) {
8559 out
[i
] = ctx
->outputs
.outputs
[loc
][start
+ i
];
8560 all_undef
= all_undef
&& !out
[i
].id();
8567 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
8568 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
8569 /* GFX6 doesn't support storing vec3, split it. */
8570 writemask
|= 1u << (start
+ 2);
8574 unsigned offset
= output
->offset
+ start
* 4;
8576 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
8577 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
8578 for (int i
= 0; i
< count
; ++i
)
8579 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
8580 vec
->definitions
[0] = Definition(write_data
);
8581 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8586 opcode
= aco_opcode::buffer_store_dword
;
8589 opcode
= aco_opcode::buffer_store_dwordx2
;
8592 opcode
= aco_opcode::buffer_store_dwordx3
;
8595 opcode
= aco_opcode::buffer_store_dwordx4
;
8598 unreachable("Unsupported dword count.");
8601 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
8602 store
->operands
[0] = Operand(so_write_offset
[buf
]);
8603 store
->operands
[1] = Operand(so_buffers
[buf
]);
8604 store
->operands
[2] = Operand((uint32_t) 0);
8605 store
->operands
[3] = Operand(write_data
);
8606 if (offset
> 4095) {
8607 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
8608 Builder
bld(ctx
->program
, ctx
->block
);
8609 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
8611 store
->offset
= offset
;
8613 store
->offen
= true;
8617 store
->can_reorder
= true;
8618 ctx
->block
->instructions
.emplace_back(std::move(store
));
8622 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
8624 Builder
bld(ctx
->program
, ctx
->block
);
8627 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
8628 for (unsigned i
= 0; i
< 4; i
++) {
8629 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
8633 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, Operand(i
* 16u));
8636 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
8637 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
8639 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
8641 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
8644 begin_divergent_if_then(ctx
, &ic
, can_emit
);
8646 bld
.reset(ctx
->block
);
8648 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
8650 Temp so_write_offset
[4];
8652 for (unsigned i
= 0; i
< 4; i
++) {
8653 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
8658 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
8659 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
8660 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
8661 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
8663 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
8665 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
8666 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
8667 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
8668 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
8672 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
8673 struct radv_stream_output
*output
=
8674 &ctx
->program
->info
->so
.outputs
[i
];
8675 if (stream
!= output
->stream
)
8678 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
8681 begin_divergent_if_else(ctx
, &ic
);
8682 end_divergent_if(ctx
, &ic
);
8685 } /* end namespace */
8687 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
8689 /* Split all arguments except for the first (ring_offsets) and the last
8690 * (exec) so that the dead channels don't stay live throughout the program.
8692 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
8693 if (startpgm
->definitions
[i
].regClass().size() > 1) {
8694 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
8695 startpgm
->definitions
[i
].regClass().size());
8700 void handle_bc_optimize(isel_context
*ctx
)
8702 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
8703 Builder
bld(ctx
->program
, ctx
->block
);
8704 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
8705 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
8706 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
8707 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
8708 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
8709 if (uses_center
&& uses_centroid
) {
8710 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
8711 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
8713 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
8715 for (unsigned i
= 0; i
< 2; i
++) {
8716 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
8717 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
8718 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8719 persp_centroid
, persp_center
, sel
);
8721 ctx
->persp_centroid
= bld
.tmp(v2
);
8722 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
8723 Operand(new_coord
[0]), Operand(new_coord
[1]));
8724 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
8727 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
8729 for (unsigned i
= 0; i
< 2; i
++) {
8730 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
8731 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
8732 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8733 linear_centroid
, linear_center
, sel
);
8735 ctx
->linear_centroid
= bld
.tmp(v2
);
8736 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
8737 Operand(new_coord
[0]), Operand(new_coord
[1]));
8738 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
8743 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
8745 Program
*program
= ctx
->program
;
8747 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
8749 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
8750 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
8751 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
8752 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
8753 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
8755 program
->next_fp_mode
.must_flush_denorms32
=
8756 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
8757 program
->next_fp_mode
.must_flush_denorms16_64
=
8758 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
8759 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
8761 program
->next_fp_mode
.care_about_round32
=
8762 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
8764 program
->next_fp_mode
.care_about_round16_64
=
8765 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
8766 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
8768 /* default to preserving fp16 and fp64 denorms, since it's free */
8769 if (program
->next_fp_mode
.must_flush_denorms16_64
)
8770 program
->next_fp_mode
.denorm16_64
= 0;
8772 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
8774 /* preserving fp32 denorms is expensive, so only do it if asked */
8775 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
8776 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
8778 program
->next_fp_mode
.denorm32
= 0;
8780 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
8781 program
->next_fp_mode
.round32
= fp_round_tz
;
8783 program
->next_fp_mode
.round32
= fp_round_ne
;
8785 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
8786 program
->next_fp_mode
.round16_64
= fp_round_tz
;
8788 program
->next_fp_mode
.round16_64
= fp_round_ne
;
8790 ctx
->block
->fp_mode
= program
->next_fp_mode
;
8793 void cleanup_cfg(Program
*program
)
8795 /* create linear_succs/logical_succs */
8796 for (Block
& BB
: program
->blocks
) {
8797 for (unsigned idx
: BB
.linear_preds
)
8798 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
8799 for (unsigned idx
: BB
.logical_preds
)
8800 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
8804 void select_program(Program
*program
,
8805 unsigned shader_count
,
8806 struct nir_shader
*const *shaders
,
8807 ac_shader_config
* config
,
8808 struct radv_shader_args
*args
)
8810 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
8812 for (unsigned i
= 0; i
< shader_count
; i
++) {
8813 nir_shader
*nir
= shaders
[i
];
8814 init_context(&ctx
, nir
);
8816 setup_fp_mode(&ctx
, nir
);
8819 /* needs to be after init_context() for FS */
8820 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
8821 append_logical_start(ctx
.block
);
8822 split_arguments(&ctx
, startpgm
);
8826 if (shader_count
>= 2) {
8827 Builder
bld(ctx
.program
, ctx
.block
);
8828 Temp count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | (i
* 8u)));
8829 Temp thread_id
= emit_mbcnt(&ctx
, bld
.def(v1
));
8830 Temp cond
= bld
.vopc(aco_opcode::v_cmp_gt_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), count
, thread_id
);
8832 begin_divergent_if_then(&ctx
, &ic
, cond
);
8836 Builder
bld(ctx
.program
, ctx
.block
);
8837 assert(ctx
.stage
== vertex_geometry_gs
);
8838 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
8839 bld
.sopp(aco_opcode::s_barrier
);
8841 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
8842 } else if (ctx
.stage
== geometry_gs
)
8843 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
8845 if (ctx
.stage
== fragment_fs
)
8846 handle_bc_optimize(&ctx
);
8848 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
8849 visit_cf_list(&ctx
, &func
->body
);
8851 if (ctx
.program
->info
->so
.num_outputs
&& ctx
.stage
== vertex_vs
)
8852 emit_streamout(&ctx
, 0);
8854 if (ctx
.stage
== vertex_vs
) {
8855 create_vs_exports(&ctx
);
8856 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8857 Builder
bld(ctx
.program
, ctx
.block
);
8858 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
8859 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
8862 if (ctx
.stage
== fragment_fs
)
8863 create_fs_exports(&ctx
);
8865 if (shader_count
>= 2) {
8866 begin_divergent_if_else(&ctx
, &ic
);
8867 end_divergent_if(&ctx
, &ic
);
8870 ralloc_free(ctx
.divergent_vals
);
8873 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
8875 append_logical_end(ctx
.block
);
8876 ctx
.block
->kind
|= block_kind_uniform
| block_kind_export_end
;
8877 Builder
bld(ctx
.program
, ctx
.block
);
8878 if (ctx
.program
->wb_smem_l1_on_end
)
8879 bld
.smem(aco_opcode::s_dcache_wb
, false);
8880 bld
.sopp(aco_opcode::s_endpgm
);
8882 cleanup_cfg(program
);
8885 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
8886 ac_shader_config
* config
,
8887 struct radv_shader_args
*args
)
8889 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
8891 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
8892 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
8893 program
->next_fp_mode
.must_flush_denorms32
= false;
8894 program
->next_fp_mode
.must_flush_denorms16_64
= false;
8895 program
->next_fp_mode
.care_about_round32
= false;
8896 program
->next_fp_mode
.care_about_round16_64
= false;
8897 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
8898 program
->next_fp_mode
.denorm32
= 0;
8899 program
->next_fp_mode
.round32
= fp_round_ne
;
8900 program
->next_fp_mode
.round16_64
= fp_round_ne
;
8901 ctx
.block
->fp_mode
= program
->next_fp_mode
;
8904 append_logical_start(ctx
.block
);
8906 Builder
bld(ctx
.program
, ctx
.block
);
8908 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
8910 Operand
stream_id(0u);
8911 if (args
->shader_info
->so
.num_outputs
)
8912 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
8913 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
8915 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
8917 std::stack
<Block
> endif_blocks
;
8919 for (unsigned stream
= 0; stream
< 4; stream
++) {
8920 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
8923 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
8924 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
8927 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
8929 unsigned BB_if_idx
= ctx
.block
->index
;
8930 Block BB_endif
= Block();
8931 if (!stream_id
.isConstant()) {
8933 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
8934 append_logical_end(ctx
.block
);
8935 ctx
.block
->kind
|= block_kind_uniform
;
8936 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
8938 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
8940 ctx
.block
= ctx
.program
->create_and_insert_block();
8941 add_edge(BB_if_idx
, ctx
.block
);
8942 bld
.reset(ctx
.block
);
8943 append_logical_start(ctx
.block
);
8946 unsigned offset
= 0;
8947 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
8948 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
8951 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
8952 unsigned length
= util_last_bit(output_usage_mask
);
8953 for (unsigned j
= 0; j
< length
; ++j
) {
8954 if (!(output_usage_mask
& (1 << j
)))
8957 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
8958 Temp voffset
= vtx_offset
;
8959 if (const_offset
>= 4096u) {
8960 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
8961 const_offset
%= 4096u;
8964 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
8965 mubuf
->definitions
[0] = bld
.def(v1
);
8966 mubuf
->operands
[0] = Operand(voffset
);
8967 mubuf
->operands
[1] = Operand(gsvs_ring
);
8968 mubuf
->operands
[2] = Operand(0u);
8969 mubuf
->offen
= true;
8970 mubuf
->offset
= const_offset
;
8973 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
8974 mubuf
->barrier
= barrier_none
;
8975 mubuf
->can_reorder
= true;
8977 ctx
.outputs
.mask
[i
] |= 1 << j
;
8978 ctx
.outputs
.outputs
[i
][j
] = mubuf
->definitions
[0].getTemp();
8980 bld
.insert(std::move(mubuf
));
8986 if (args
->shader_info
->so
.num_outputs
) {
8987 emit_streamout(&ctx
, stream
);
8988 bld
.reset(ctx
.block
);
8992 create_vs_exports(&ctx
);
8993 ctx
.block
->kind
|= block_kind_export_end
;
8996 if (!stream_id
.isConstant()) {
8997 append_logical_end(ctx
.block
);
8999 /* branch from then block to endif block */
9000 bld
.branch(aco_opcode::p_branch
);
9001 add_edge(ctx
.block
->index
, &BB_endif
);
9002 ctx
.block
->kind
|= block_kind_uniform
;
9004 /* emit else block */
9005 ctx
.block
= ctx
.program
->create_and_insert_block();
9006 add_edge(BB_if_idx
, ctx
.block
);
9007 bld
.reset(ctx
.block
);
9008 append_logical_start(ctx
.block
);
9010 endif_blocks
.push(std::move(BB_endif
));
9014 while (!endif_blocks
.empty()) {
9015 Block BB_endif
= std::move(endif_blocks
.top());
9018 Block
*BB_else
= ctx
.block
;
9020 append_logical_end(BB_else
);
9021 /* branch from else block to endif block */
9022 bld
.branch(aco_opcode::p_branch
);
9023 add_edge(BB_else
->index
, &BB_endif
);
9024 BB_else
->kind
|= block_kind_uniform
;
9026 /** emit endif merge block */
9027 ctx
.block
= program
->insert_block(std::move(BB_endif
));
9028 bld
.reset(ctx
.block
);
9029 append_logical_start(ctx
.block
);
9032 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
9034 append_logical_end(ctx
.block
);
9035 ctx
.block
->kind
|= block_kind_uniform
;
9036 bld
.sopp(aco_opcode::s_endpgm
);
9038 cleanup_cfg(program
);